_:n6c8e065ec45c43b6bfab09e245732ccexb22
<http://schema.org/text>
"plained by clock speed differences.\n\nAs it stands now the latency to access main memory is simply too high on Ryzen, which is the primary bottleneck in g\n\nThis is why the Zen3 rumor of shared L3 between all 6-8 cores on a chiplet is important, rather than 16MB/4 cores, it will be 32MB/8 cores (meaning in lightly threaded workloads, effective shared L3 cache is doubled), which will decrease cache misses and make the FCLK limit less of an issue.\n\nHowever, single and lightly threaded games/workloads aren't going away, and this change seems like an expensive way to kick the can down the road as L3 cache is not cheap from a real estate, power, and heat standpoint.\n\nMy initial though was, as long as AMD don't correct what seems to be an obvious drawback with the memory subsystem, won't this still be an issue? However, it could be that the cost (from a real estate, power, and heat standpoint) of improving IF at this point is economically higher than boosting L3 cache, and perhaps Zen4 team is already working on memory subsystem improvements, hence the shared L3 is a good stop-gap."
<https://forums.anandtech.com/threads/video-ryzen-7-3800x-5ghz-vs-core-i9-9900k-5-ghz.2580198/>