<http://schema.org/description>
"...Minimum MSEE + 6 years or BSEE + 9 years of digital design experience using verilog. Experience translating complex algorithms from written architecture specifications to working code required. DSP skills, multimedia knowledge, UVM, design automation, and multi-site development experience are a plus.\n\nWe\nare an Equal Opportunity Employer and do not discriminate against applicants\ndue to male, female, veterans status or on the basis of disability.\n\nJob\n\u00A0\nR&amp;D\n\nPrimary Location\nUnited States-Cali..."^^<http://www.w3.org/2001/XMLSchema#string>
<https://tapwage.com/company/avago-technologies/senior/jobs>