<http://schema.org/description>
"...: DFT engineers at NVIDIA own the testing methodology from strategy definition through, logic design and insertion, pre-silicon verification, pattern generation, and ATE bringup. This position will focus on all of the above for NVIDIA chips, with special emphasis on ATE bringup, pattern/generation and validation, yield debug, failure analysis and volume diagnosis for ramp to production. MINIMUM REQUIREMENTS: - MSEE - Strong understanding of DFT logic, fault models, ATPG, and fault simulation. -..."^^<http://www.w3.org/2001/XMLSchema#string>
<https://tapwage.com/city/1674199-yilan-taiwan/perl/jobs>