title: Verilog equivalent of "wait until ... for ..."?
body: <p>In a Verilog testbench, I'm trying to code the following behavior:</p>
  
  <ul>
  <li><p>Wait until an event occurs (rising / falling edge) for a maximum time, i.e. an equivalent of the VHDL instruction:</p>
  
  <pre><code>wait until &lt;event&gt; for &lt;duration&gt;;
  </code></pre></li>
  </ul>
  
  <p>which has the following behavior (reminder):</p>
  
  <ul>
  <li>either the event occurs;</li>
  <li>or the duration expires.</li>
  </ul>
  
  <p>Unless I'm mistaken, I did not find any direct equivalent of this function in Verilog... So I tried the following code:</p>
  
  <pre><code>reg watchdog;
  // ...
  
  // Set a signal 'watchdog' in background which will be triggered in 10 us.
  fork
    watchdog &lt;= #10_000 1'b1;
  join
  
  // Wait until SIGNAL is set to '1' *OR* watchdog event occurs.
  @(posedge SIGNAL or posedge watchdog);
  
  // Reset the watchdog
  watchdog &lt;= 1'b0;
  </code></pre>
  
  <p>This code does the work but the last instruction does not cancel or supercede the <code>fork</code> instruction. So, in a second call to this code (with for example <code>watchdog &lt;= #50_000 1'b1;</code>), the first <code>watchdog</code> may be triggered (too soon unfortunately).</p>
  
  <p>Any better idea? (either an equivalent or a way to cancel the first planned <code>fork</code>?)</p>
  
  <p>P-S : to do it in SystemVerilog is not an option... ;-)</p>