title: VHDL Testbench code doesn't work for register
body: <p>I want to  simulate the register  logic , but  the test bench don't  working , when affect the input signal  "Si, ECi, Ri, Ci", all signal input fixed to "0000000001"  when I run the simulation in Xlinix , and Output fixed to "ZZZZZZZZ0" I don't know why?</p>
  
  <p>Here's the code vhdl of register </p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all; 
  use IEEE.std_logic_unsigned.all;
  use IEEE.numeric_std.all;
  
  entity Registre is
      Generic ( N: positive :=10);
      Port ( R : in  STD_LOGIC_VECTOR (N downto 1);
             EC : in  STD_LOGIC_VECTOR (N downto 1); 
             C : in  STD_LOGIC_VECTOR (N downto 1);
             S : in  STD_LOGIC_VECTOR (N downto 1);
             Vss : in  STD_LOGIC_VECTOR (N downto 1);
             Vdd : in STD_LOGIC_VECTOR (N downto 1);
             DA : out  STD_LOGIC_VECTOR (N downto 1));
  end Registre;
  
  architecture Behavioral of Registre is
  
      component SA_REG 
          Port ( EC : in  STD_LOGIC;
                 C : in  STD_LOGIC;
                 R : in  STD_LOGIC;
                 S : in  STD_LOGIC;
                 Q : out  STD_LOGIC;
                 Vss : in  STD_LOGIC;
                 Vdd : in  STD_LOGIC);
      end component;
  
      Component SA_REGDR
          Port ( R : in  STD_LOGIC;
                 C : in  STD_LOGIC;
                 EC : in  STD_LOGIC;
                 Q : out  STD_LOGIC;
                 Vss: in STD_LOGIC;
                 Vdd: in STD_LOGIC
             );
      end component;
  
  begin
  
      DR : SA_REGDR port map ( R=&gt; R(10) ,EC=&gt; EC(10), C=&gt; C(10), Vss=&gt; Vss(10), Vdd=&gt; Vdd(10), Q=&gt; DA(10) );
  
      Mgen : for i in 1 to N-1 generate
          M : SA_REG port map (R=&gt;R(i), EC=&gt; EC(i), C=&gt; C(i),S=&gt; S(i), Vss=&gt; Vss(i), Vdd=&gt; Vdd(i), Q=&gt; DA(i) ); 
      end generate;
  
  end Behavioral;
  </code></pre>
  
  <p>Test bench  :</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.std_logic_unsigned.all;
  use IEEE.numeric_std.all;
  
  entity Registre_tb is
  end Registre_tb;
  
  architecture Behavioral of Registre_tb is
      component Registre
          generic( N : integer :=10);
          Port ( R : in  STD_LOGIC_VECTOR (10 downto 1);
                 EC : in  STD_LOGIC_VECTOR (10 downto 1);
                 C : in  STD_LOGIC_VECTOR (10 downto 1);
                 S : in  STD_LOGIC_VECTOR (10 downto 1);
                 Vss : in  STD_LOGIC_VECTOR (10 downto 1);
                 Vdd : in STD_LOGIC_VECTOR (10 downto 1);
                 DA : out  STD_LOGIC_VECTOR (10 downto 1));
      end component;
  
      signal  Ri  : STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '0');
      signal  Ci  : STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '0');
      signal  ECi : STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '0');
      signal  Si  : STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '0');
      signal  Vssi: STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '0');
      signal  Vddi: STD_LOGIC_VECTOR (10 downto 1):= (others =&gt; '1');
      signal  DAi : STD_LOGIC_VECTOR (10 downto 1);
  
      signal clk : std_logic := '0';
  begin
      -- instanciate 
      component_in_test : Registre port map( --instantiation of the Registre component
          R =&gt; Ri,
          C =&gt; Ci,
          EC =&gt; ECi,
          S =&gt; Si,
          Vss =&gt; Vssi,
          Vdd =&gt; Vddi,
          DA =&gt; DAi
      );
  
      -- stimulis 
      clk &lt;= not clk after 1ns; --creates 100MHz clock inside testbench
  
      Ri_gen : process(clk) is   --process which will check Ri with every possible value
      begin
          if clk'Event and clk = '1' then
              Ri &lt;= Ri + 1;
          end if;
      end process;
  
      Ci_gen : process(clk) is   --process which will check Ci with every possible value
      begin
          if clk'Event and clk = '1' then
              Ci &lt;= Ci + 1;
          end if;
      end process;
  
      ECi_gen : process(clk) is   --process which will check ECi with every possible value
      begin
          if clk'Event and clk = '1' then
              ECi &lt;= ECi + 1;
          end if;
      end process;
  
      Si_gen : process(clk) is   --process which will check Si with every possible value
      begin
          if clk'Event and clk = '1' then
              Si &lt;= Si + 1;
          end if;
      end process;
  
  end Behavioral;
  </code></pre>
  
  <p>Simulation 
  <img src="https://i.stack.imgur.com/eW00A.png" alt="enter image description here"></p>