title: for-generate inside process vhdl
body: <p>I know it is not possible to write for-generate inside the process but I want to achieve a functionality as presented by the code.It is basically an address decoder. Any help is appreciated. </p>
  
  <p>The following code gives the syntax error : "Syntax error near generate"</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity address_decoder is
  generic (CAM_DEPTH: integer := 8);
  port (in_address: in std_logic_vector(CAM_DEPTH-1 downto 0);
          out_address: out std_logic_vector(2**CAM_DEPTH-1 downto 0);
          clk : in std_logic;
          rst: in std_logic
      );
  end address_decoder;
  
  architecture Behavioral of address_decoder is
  
  begin
  decode_process:
  process(clk,rst) begin
  
  if(clk'event and clk='1') then
          if (rst = '1') then
              out_address &lt;= (others =&gt; '0');
          else
              NAME: for i in 0 to 10 generate
                  if (i = to_integer(unsigned(in_address))) then
                      out_address(i) &lt;= '1';
              else
                      out_address(i) &lt;= '0';
                  end if;
          end generate NAME;
  end if;
  end if;
  
  end process;
  
   end Behavioral;
  </code></pre>