title: systemVerilog signed doesn't work correctly
body: <p>I have the following function:</p>
  
  <pre><code>   function tx_upconv_out_transaction predict(tx_upconv_in_transaction in_trx);
        tx_upconv_out_transaction predicted = tx_upconv_out_transaction::type_id::create("predicted");
        //-------golden model-----
  //      predicted.y = (in_trx.xi * in_trx.cos - in_trx.xq * in_trx.sin)/ (2 ** 17);
        $display(" xi = %d, cos = %d xq = %d sin = %d", $signed(in_trx.xi),$signed(in_trx.cos),$signed(in_trx.xq),$signed(in_trx.sin) );
        predicted.y = ($signed(in_trx.xi) * $signed(in_trx.cos) - $signed(in_trx.xq) * $signed(in_trx.sin))/ (131072);      
        return predicted;
     endfunction: predict 
  </code></pre>
  
  <p>Where:
  The field in in_trx are defined by:</p>
  
  <pre><code>   bit [15:0]  xi;
     bit [15:0]  xq;
     bit [15:0]  sin;
     bit [15:0]  cos;  
  </code></pre>
  
  <p>For the input:</p>
  
  <pre><code>xi, qq = fffa (hex)
  sin = 0
  cos = 7ffe (hex)
  </code></pre>
  
  <p>The output (display) is:</p>
  
  <pre><code>xi =     -6, cos =  32766 xq =     -6 sin =      0
  </code></pre>
  
  <p>Where it should be:</p>
  
  <pre><code> xi =     -6, cos =  -2 xq =     -6 sin =      0
  </code></pre>