title: cannot be driven by primitives or continuous assignment
body: <p>I got</p>
  <blockquote>
  <p>reg OUT; cannot be driven by primitives or continuous assignment.</p>
  </blockquote>
  <p>error.</p>
  <p>The Counter module is:</p>
  <pre><code>module Counter(
      input             clk,
      input             clear,
      input             load,
      input             up_down, // UP/~DOWN
      input[3:0]        IN,
      input             count,
      output reg[3:0]   OUT
      );
      always @(posedge clk, negedge clear)
      if (~clear) OUT &lt;= 4'b0000;
      else if(load) OUT &lt;= IN;
      else if(count)
      begin
         if(up_down) OUT &lt;= OUT + 1'b1;
         else OUT &lt;= OUT - 1'b1;
      end
      else OUT &lt;= OUT;
  endmodule
  </code></pre>
  <p>And the testbench is:</p>
  <pre><code>module test;
     .
     .
     .
     reg [3:0] IN;
     reg [3:0] OUT;
  
     Counter c1(clk, clear, load, up_down, IN, count, OUT);
  endmodule
  </code></pre>
  <p>The error is in the <code>Counter c1(clk, clear, load, up_down, IN, count, OUT);</code> line.</p>