title: VerilogHDL - Error connecting Array with non-Array expressions
body: <p>I am struggling with my code, which is a Carry-Save Multiplier. </p>
  
  <pre><code>module csm (A,B,So,Co);
  
  parameter n = 8, m = 16;
  input [7 : 0] A,B;
  output [m-1 : 0] So;
  output Co; // carry out
  
  wire [7:0] CARRY [7:0];
  reg [8:0] SUM [8:0];
  
  assign So = {SUM[7][7],SUM[6][7],SUM[5][7],SUM[4][7],SUM[3][7], SUM[2][7],SUM[1][7],SUM[0][7],SUM[0][6],SUM[0][5],SUM[0][4],SUM[0][3],SUM[0][2],SUM[0][1],SUM[0][0]};
  
  genvar i, j;
  // Assign Carry out to the last carry related w/ overflow
  assign Co = CARRY[7][7];
  // Assign A[n] to SUM
  //assign SUM[i][j] = {A[i],B[j]};
  always@(*)
  begin
   SUM[0][0] &lt;= A[0];
   SUM[1][0] &lt;= A[1];
   SUM[2][0] &lt;= A[2];
   SUM[3][0] &lt;= A[3];
   SUM[4][0] &lt;= A[4];
   SUM[5][0] &lt;= A[5];
   SUM[6][0] &lt;= A[6];
   SUM[7][0] &lt;= A[7];
   SUM[7][1] &lt;= A[7];
   SUM[7][2] &lt;= A[7];
   SUM[7][3] &lt;= A[7];
   SUM[7][4] &lt;= A[7];
   SUM[7][5] &lt;= A[7];
   SUM[7][6] &lt;= A[7];
   SUM[7][7] &lt;= A[7];
  end
  //Assign B[n] to SUM
  /*
  assign SUM[i][0] = B[0];
  assign SUM[i][1] = B[1];
  assign SUM[i][2] = B[2];
  assign SUM[i][3] = B[3];
  assign SUM[i][4] = B[4];
  assign SUM[i][5] = B[5];
  assign SUM[i][6] = B[6];
  assign SUM[i][7] = B[7];
  */
  /*
  generate
      for(i=0; i &lt;= 7; i = i + 1) // first row (J=0)
      begin : first row
          full_adder fa_1(.A_i(SUM[i][0]),.B_i(B[0]),.C_i(1'b0),.S_o(SUM[i][0]),.C_o(CARRY[i][0]));
      end
  endgenerate
  */
  generate 
  
      for(i=0; i &lt;= 7; i = i + 1) // first row (J=0)
      begin : first_row
          full_adder fa_1(.A_i(SUM[i][0]),.B_i(B[0]),.C_i(1'b0),.S_o(SUM[i][0]),.C_o(CARRY[i][0]));
      end
  
      for(j = 1; j &lt;= 7; j = j + 1)
      begin : column
          for(i=0; i &lt;= 7; i = i + 1) // other rows[]
          begin : row
              full_adder fa(.A_i(SUM[i+1][j-1]),.B_i(B[j]),.C_i(CARRY[i][j-1]),.S_o(SUM[i][j]),.C_o(CARRY[i][j]));
          end
      end
  endgenerate
  
  endmodule 
  
  
  // Full Adder module 
  
  module full_adder(A_i, B_i, C_i, C_o, S_o);
  
  input  A_i, B_i, C_i;
  output C_o, S_o;
  
  wire  A_i, B_i, C_i;
  wire C_o;
  reg S_o;
  
  //assign 
  always@(*)
  begin
  S_o = (A_i ^ B_i ^ C_i);
  end 
  assign C_o = ((A_i &amp; B_i) | (B_i &amp; C_i) | (A_i &amp; C_i)); 
  
  endmodule
  </code></pre>
  
  <p>I'm getting this error in Quartus: "Error (10663): Verilog HDL Port Connection error at csm.v(59): output or inout port "S_o" must be connected to a structural net expression"</p>
  
  <p>I am just not seeing the error. If you guys have a tip to me, I'll appreciate a lot (I have to finish this code ASAP :( ).</p>
  
  <p>Thank you all.</p>