title: Linux kernel ARM Translation table base (TTB0 and TTB1)
body: <p>Compiled Linux kernel 2.6.34.3 for ARMv7 (Cortex-a8)  </p>
  
  <p>I looked into the kernel code and it looks like the Linux kernel sets the hardware page tables for the kernel address space (everything over 0xC0000000)on TTB1 (translation table base) and the user process on ttb0 (everything under 0xC0000000) which changes for every process context switch. Is this correct? I'm still confused how the MMU knows which ttb to look at for translations? </p>
  
  <p>I read that the TTBCR (translation table base control register) determines which of the ttb register to walk when an MVA is not found, however the register always reads 0 which means always use TTBR0 in the ARM architecture reference manual. How is that possible? Can anyone explain to me how the Linux kernel uses these two ttbs?</p>
  
  <p>I read how the ttb works from this site <a href="https://www.cs.rutgers.edu/~pxk/416/notes/10-paging.html" rel="nofollow noreferrer">https://www.cs.rutgers.edu/~pxk/416/notes/10-paging.html</a> but I still dont understand how the kernel use the two ttbs</p>
  
  <p>(Double checked the kernel code, for some reason both ttb0 and ttb1 is set, but it seems like ttb1 is never used, i set the TTB1 register to 0 and the Linux kernel continue to run as usual)</p>