title: code for clock generation in structural verilog
body: <p>I was trying to teach myself verilog programming from "The Verilog HDL" book by Thomas Moorby. In one of the exercises, they asked to generate a clock using structural verilog only (except for the $monitor part of course). </p>
  
  <p>I tried the following:</p>
  
  <pre><code>module clock();
      wor clk;
      assign clk=0;
  
      initial begin 
          $monitor($time,,"clk=%b", clk);
          #100 $finish;
      end
  
      assign #5 clk = ~clk;
  endmodule
  </code></pre>
  
  <p>Problem is, it works in iVerilog 0.9.7, but for version 10.0 and above, it does not work.. I simply get undefined value for clk!</p>
  
  <p>Does not seem like a bug in iVerilog, otherwise it would probably have been fixed in one of the 10.x releases. Is there any other way to get this working? Also, what is wrong with the current code (if any) ?</p>