title: Creating a pulse in low state with Output Compare, must be high by default + Timer not enabling when needed
body: <p>This question has its origin in <a href="https://stackoverflow.com/questions/45209384/repeat-an-instruction-a-certain-number-of-times-without-a-loop">my other question</a>. I've decided to create a new one because it's a very particular thing that I haven't been able to find anywhere.</p>
  
  <p>In a STM32F415 I want the Output Compare of a timer to be high by default, and low for the number of clock cycles I tell him. My aim is to <strong>disable</strong> one timer using another timer. In the <a href="http://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf" rel="nofollow noreferrer">Reference Manual</a> page 620, there's an example on <em>Using one timer to enable another timer</em>.</p>
  
  <p>In my case, I want TIM3 to control TIM2 and TIM4 to control TIM5. TIM2 and TIM5 are triggering DAC requests to the DMA, and they are working fine.</p>
  
  <p>This is how I initialise TIM3 (this function is called in <em>main</em> before the infinite loop):</p>
  
  <pre><code>void TIM3_Config(void)
  {
  TIM_TimeBaseInitTypeDef     TIM_TimeBaseStructure;
  TIM_OCInitTypeDef           TIM_OCInitBaseStructure;
  
  TIM_DeInit(TIM3);
  
  // TIM3 Periph clock enable
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
  
  // Time base configuration
  TIM_TimeBaseStructInit(&amp;TIM_TimeBaseStructure);
  TIM_TimeBaseStructure.TIM_Period = 0x46;        //ARR = 70 (cycles low will be 0-63)
  TIM_TimeBaseStructure.TIM_Prescaler = 0;
  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
  TIM_TimeBaseInit(TIM3, &amp;TIM_TimeBaseStructure);
  
  // TIM3 Output Compare configuration
  TIM_OCStructInit(&amp;TIM_OCInitBaseStructure);
  TIM_OCInitBaseStructure.TIM_OCMode=TIM_OCMode_Active;
  TIM_OCInitBaseStructure.TIM_Pulse=0x3C;   //CCR
  TIM_OCInitBaseStructure.TIM_OutputState=TIM_OutputState_Enable;
  TIM_OC1Init(TIM3,&amp;TIM_OCInitBaseStructure);
  TIM3-&gt;CCMR1 &amp;= 0xFFF7;      // OC1PE: Output compare 1 preload disabled
  TIM3-&gt;CCMR1 &amp;= 0xFFFC;      //  CC1S[1:0]=00 CC1 channel is configured as output.
  TIM3-&gt;CR1 |= 0x8;
  TIM3-&gt;CR2 |= 0x40;
  TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_OC1Ref);       //  MSM[2:0] = 100 OC1REF as TIM3 TRGO
  
  TIM_Cmd(TIM3, ENABLE);
  }
  </code></pre>
  
  <p>Then, in the corresponding DMA IRQ handler:</p>
  
  <pre><code>void DMA1_Stream6_IRQHandler(void)           /* DAC2 */
  {
  
  if (DMA_GetITStatus(DMA1_Stream6,DMA_IT_HTIF6) == SET)
  {
      DMA_ClearITPendingBit(DMA1_Stream6,DMA_IT_HTIF6);
  
      TIM3-&gt;CNT  = 0x0;     // Reset timer
      TIM3-&gt;CR1 |= 0x1;     // Enable timer
  }
  /* Some code for the Transfer Complete case */
  }
  </code></pre>
  
  <p>In another point of the program I change the CCR according to the number of cycles I want the slave timer (TIM2 or TIM5) to be disabled.</p>
  
  <p>My main problem is that it doesn't work at all, and while debugging I've found that TIM3 and TIM4 enable instructions seem to do nothing: the enable bit (CEN in the TIMx CR1 register) stays '0' instead of changing to '1'. TIM2 and TIM5 initialisation are pretty much the same, without the Output Compare and with the gated input configuration to the corresponding timer TRGO, and they can be enabled and disabled without problems.</p>
  
  <p>I haven't found any condition or limitation to how I should enable a Timer that could affect my program so I'm a bit lost with this.</p>
  
  <p>Any help would be appreciated, thank you!</p>