title: Problems assigning to LEDs in a case block
body: <p>When I enter something like this:</p>
  <pre><code>always @* begin
      case(SW[17])
          1'b0: assign LEDG = SW[7:0];
          1'b1: assign LEDG = SW[15:8];
      endcase
  end
  </code></pre>
  <p>where <code>LEDG</code> is set of [7:0] green LEDs, I get the error:</p>
  <blockquote>
  <p>Error (10137): Verilog HDL Procedural Assignment error at
  part2.v(20): object &quot;LEDG&quot; on left-hand side of assignment must have a
  variable data type</p>
  </blockquote>
  <p>upon trying to compile.  However, when I put a similar assignment statement outside the case block, such as:</p>
  <pre><code>assign LEDG = SW[7:0];
  </code></pre>
  <p>it assigns just fine.  I can't seem to figure out the issue.</p>