title: Detect ARMv8 A53 vs A57 architecture at runtime?
body: <p>I'm benchmarking a library against ARMv8 machines. I have four Cortex-A53 dev-boards, and our NEON intrinsics implementation outperforms the C/C++ implementation by about 30%. This is expected.</p>
  
  <p>The GCC compile farm offers a Softiron Overdrive 1000. Its a Cortex-A57 server board, and the C/C++ code outperforms the intrinsics implementation by a factor of 50%. This was surprising.</p>
  
  <p>We'd like to use our NEON implementation for A-53, but use the C/C++ implementation for the A57. We have code that can make runtime feature selections, like <code>HasNEON()</code>, <code>HasCRC()</code>, <code>HasAES()</code> and <code>HasSHA()</code>. We don't have anything for the architecture, like A53 vs A57.</p>
  
  <p>My question is, how do we detect an A53 vs A57 at runtime?</p>
  
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  <p>We have similar code for x86 code paths for the P4 processor. The P4 has some slow word operations. We detect the P4 by checking CPUID bits, but ARM systems are different. ARM systems the CPUID-like instruction is reading a MSR, and it usually requires a higher privilege level (EL1 or above).</p>
  
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  <p>If interested, the Cortex-A57 is slower for a particular hash algorithm because it relies heavily on shifts, rotates and xors. The <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.uan0015b/index.html" rel="nofollow noreferrer">A57 Optimization guide</a> tells us shifts and rotates are more expensive. It takes 4 or 5 cycle in the ASIMD coprocessor for the shift, and only the F1 pipe can perform the operation (per section 3.14).</p>
  
  <p>It could also be the Cortex-A53 has the same penalty, and its integer unit is slower so non-NEON code does not outperform the NEON code.</p>