title: what llvm store instruction pattern do i need?
body: <p>im trying to make an llvm backend and i dont know what i need to fix this error </p>
  
  <pre><code>LLVM ERROR: Cannot select: t5: ch = store&lt;ST4[%retval]&gt; t0, Constant:i32&lt;0&gt;, FrameIndex:i64&lt;0&gt;, undef:i64
  </code></pre>
  
  <p>this is the ir im trying to process</p>
  
  <pre><code>define i32 @main() #0 {
  %retval = alloca i32, align 4
  store i32 0, i32* %retval, align 4
  ret i32 0
  }
  </code></pre>
  
  <p>but i don't know what dag pattern i need to be able to match it.</p>
  
  <p>a tablegen file that contains some of the instructions my arch supports is here <a href="https://github.com/jfmherokiller/customllvm/blob/master/llvm/lib/Target/ZCPU/zcpuInstr.td" rel="nofollow noreferrer">https://github.com/jfmherokiller/customllvm/blob/master/llvm/lib/Target/ZCPU/zcpuInstr.td</a></p>