title: like #if in c, is there `if in verilog
body: <p>How to compare the Macro with constants in Verilog?. Below code is giving error.</p>
  
  <pre><code>module top;
    `define A 10
  
    `if (`A==10)
      initial $display("10");
    `else
      initial $display("11");
    `endif
  
  endmodule
  </code></pre>