title: Eight Bit Divider: Quotient and Remainder
body: <p>I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.</p>
  
  <p>The errors I am receiving are:</p>
  
  <pre><code>Error-[ICPD] Invalid procedural driver combination
  "divide.v", 2
  Variable "Q" is driven by an invalid combination of procedural drivers. 
  Variables written on left-hand of "always_comb" cannot be written to by any 
  other processes, including other "always_comb" processes.
  "divide.v", 2: logic [7:0] Q;
  "divide.v", 8: always_comb  begin
  if (x &lt;= R) begin
  ...
  "divide.v", 5: Q = 8'b0;
  
  Error-[ICPD] Invalid procedural driver combination 
  "divide.v", 2
  Variable "R" is driven by an invalid combination of procedural drivers. 
  Variables written on left-hand of "always_comb" cannot be written to by any 
  other processes, including other "always_comb" processes.
  "divide.v", 2: logic [7:0] R;
  "divide.v", 8: always_comb  begin
  if (x &lt;= R) begin
  ...
  "divide.v",6: R = y;
  </code></pre>
  
  <p>My SystemVerilog Code is:</p>
  
  <pre><code>module divider(input  logic [7:0] x,y,
                 output logic [7:0] Q,R);
    initial
      begin
        Q = 8'd0;
        R = y;
      end
    always_comb
      begin
        if (x&lt;=R)
          begin R &lt;= R - x; Q &lt;= Q + 8'd1; end
      end
  endmodule
  
  module test1; 
  
    logic [7:0] x,y,Q,R;
  
    divider Divider1 (x,y,Q,R);
  
    initial 
      begin
        x = 8'd2;
        y = 8'd8;
      end
  endmodule
  </code></pre>