title: vhdl std_logic not declared error
body: <p>I'm keep getting this annoying error that the std_logic is not declared. I don't know why am I getting this error because I have included all necessary libraries.
  here's my code and the errors.</p>
  
  <pre><code>     ---------------------------------------------------------------------    -------------
            -- Company: 
            -- Engineer: 
            -- 
  -- Create Date:    15:26:41 08/23/2015 
  -- Design Name: 
  -- Module Name:    Deficit-Round_Robbin_algorithem - Behavioral 
  -- Project Name: 
  -- Target Devices: 
  -- Tool versions: 
  -- Description: 
  --
  -- Dependencies: 
  --
  -- Revision: 
  -- Revision 0.01 - File Created
  -- Additional Comments: 
  --
  ----------------------------------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_arith.all;
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;
  package TwoDArray is
    Type array_integer is array(1 to 6) of integer range 0 to 6;
  end package TwoDArray;
  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
    entity Deficit_Round_Robbin_algorithem is
  
  generic(
  Quantom:integer range 0 to 256:=2;
  Num_queues:integer:=5 ;
  IN_FIFO_DEPTH_BIT:integer:=6
  );
  port(
  clk,axi_resetn,m_axis_tready:in std_logic;
  --packet_size:in array_integer range 0 to Num_queues+1;
  --fifo_out_tlast,empty:in std_logic_vector(Num_queues - 1 downto 0);
  --depth_of_fifo:in integer range 0 to Num_queues+1;
  --rd_en:out std_logic_vector(Num_queues - 1 downto 0);
  pkt_fwd:out std_logic
  );
  end Deficit_Round_Robbin_algorithem;
  
  architecture Behavioral of Deficit_Round_Robbin_algorithem is
  --signal cur_queue,cur_queue_next,cur_queue_plus1:integer range 0 to Num_queues-1:=0;
  --signal pkt_fwd_next:std_logic:='0'; 
  --
  --signal Drr_counter:array_integer ;
  --
  --subType STATE_TYPE is bit_vector (1 downto 0);
  --signal next_state,state:STATE_TYPE :="00"; --00 start state
  --constant Idle:STATE_TYPE:="00";
  --constant WR_PKT:STATE_TYPE:="01";
  begin
  --cur_queue_plus1&lt;=0 when cur_queue=Num_queues-1 else cur_queue + 1;
  --Drr_counter[cur_queue]&lt;=Drr_counter[cur_queue] + Quantom;
  --Medvedev_state_diagram:process(state,cur_queue,empty,m_axis_tready,fifo_out_tlast,depth_of_fifo) is
  --begin
  --      cur_queue_next  &lt;= cur_queue;
  --      rd_en           &lt;= (others =&gt;'0');
  --      pkt_fwd_next    &lt;= '0';
  --      case state is
  --      when Idle=&gt; if(empty[cur_queue]='0') then
  --                          if(m_axis_tready) then
  --                              if(Drr_counter[cur_queue] &gt;= packet_size[cur_queue]) then
  --                                  next_state&lt;= WR_PKT;
  --                                  rd_en[cur_queue] &lt;= '1';
  --                                  pkt_fwd_next &lt;= '1';
  --                              end if;
  --                          end if;
  --                      else
  --                      cur_queue_next &lt;= cur_queue_plus1;
  --                      end if;
  --                      end case;
  --end process;
  
  end Behavioral;
  </code></pre>
  
  <p>My errors</p>
  
  <pre><code>ERROR:HDLCompiler:69 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 42: &lt;std_logic&gt; is not declared.
  ERROR:HDLCompiler:69 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 47: &lt;std_logic&gt; is not declared.
  ERROR:HDLCompiler:854 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 34: Unit &lt;deficit_round_robbin_algorithem&gt; ignored due to previous errors.
  ERROR:HDLCompiler:374 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 51: Entity &lt;deficit_round_robbin_algorithem&gt; is not yet compiled.
  </code></pre>