title: should signals in vhdl be signed/unsigned to perform arithmetic operations?
body: <p>I am practising some basic vhdl programs.Now i came across arithmetic operations.I used bit_vector and multiplied the input signals directly but it errors <strong>"No feasible entries for infix operator"</strong>.The program is below:</p>
  
  <pre><code>   entity multiplier is
     port(a,b : in bit_vector(3 downto 0);
     c: out bit_vector(7 downto 0));
     end  multiplier;
  
     architecture ar of multiplier is
  
     begin
  
     c&lt;=(a*b);
  
     end ar;
  </code></pre>
  
  <p>But i came across this program which works fine with std_logic_vector</p>
  
  <pre><code>   library IEEE;
     use IEEE.STD_LOGIC_1164.ALL;
     use IEEE.NUMERIC_STD.ALL;
     entity Multiplier_VHDL is
     port(
    Nibble1, Nibble2: in std_logic_vector(3 downto 0);
    Result: out std_logic_vector(7 downto 0)
    );
    end entity Multiplier_VHDL;
  
   architecture Behavioral of Multiplier_VHDL is
   begin
  
   Result &lt;= std_logic_vector(unsigned(Nibble1) * unsigned(Nibble2));
  
   end ;
  </code></pre>
  
  <p>My questions are:</p>
  
  <p><strong>1.cant we simply add 2 signal bits c&lt;=a+b as we do in verilog?</strong></p>
  
  <p><strong>2.should a signal be signed/unsigned to perform arithmetic operations?</strong></p>
  
  <p><strong>3.like c which is signed by default,what about vhdl/verilog?</strong></p>
  
  <p><strong>4.are signed &amp; unsigned present in use ieee.std_logic_arith.all and use IEEE.NUMERIC_STD.ALL same?</strong></p>