title: variable target in a makefile
body: <p>I am trying to compile set of targets. However it only seems to do the first one. Below is a cut down of the my makefile that shows the error.</p>
  
  <pre><code>  OBJECTS = abc def ghi
    SOURCES = abc.c def.c ghi.c
  
    $(OBJECTS):     $(SOURCES)
            @echo target is $@, source is $&lt;
  </code></pre>
  
  <p>In shell,</p>
  
  <pre><code>  $ touch abc.c def.c ghi.c
    $ make
  </code></pre>
  
  <p>When I run make I get the following output:</p>
  
  <pre><code>  target is abc, source is abc.c
  </code></pre>
  
  <p>So it only seems to be running the first target.</p>
  
  <p>If I replace $&lt; with $^, the output is:</p>
  
  <pre><code>  target is abc, source is abc.c def.c ghi.c
  </code></pre>
  
  <p><strong>My question, is it possible to perform expansions on variables like with the (%: %) pattern?</strong></p>