title: Is there a way to do nested generate statements in Verilog?
body: <p>I am trying to reduce some code by using generate statements, but I can only figure out how to do via nesting, but I don't believe that that is allowed.</p>
  
  <p>What I have is essentially some for-loops running (which require a generate), and within them I want to run one of three sections of code depending on a value that is set when the code is built (which then requires a second generate).  Is there a way to do this and make the tools happy?</p>
  
  <p>Here is a quick-and-dirt picture of what I am trying:</p>
  
  <pre><code>    //TAPS_PER_CHAN is a value defined when the code is built
  genvar srcNode, dstNode, tapIdx;
   generate
    for (dstNode=0; dstNode&lt;NODES; dstNode=dstNode+1)
      begin: dstForLoop
      generate
          if(TAPS_PER_CHAN &lt;= 4)
          begin
              call module one
          end    
          else if (TAPS_PER_CHAN &lt;= 8)
          begin
              call module two
          end      
         else if (TAPS_PER_CHAN &lt;= 16)
         begin  
              call module three
          end
      endgenerate
      end
  endgenerate
  </code></pre>