title: Percent operator in makefile isn't working for subfolder
body: <p>In my <code>Makefile</code>, I have the following target:</p>
  <pre><code>%: %.sv
    $(VCC) $(VFLAGS) $^
  </code></pre>
  <p>Any file in the current directory with the extension <code>.sv</code> (system verilog) is captured in this. This works perfectly if I run the following command:</p>
  <pre class="lang-sh prettyprint-override"><code>make alu
  </code></pre>
  <p>I have targets set up for building simulation <code>C++</code> files which are dependent on the specific system verilog targets above:</p>
  <pre><code>$(BUILD_DIR)/sim_alu: sim_alu.cc alu | $(BUILD_DIR)
     $(CC) $(STD) $(CFLAGS) -o $@ $&lt; -Wall -Wno-sign-compare
  </code></pre>
  <p>These work fine when I run the following command:</p>
  <pre class="lang-sh prettyprint-override"><code>make build/sim_alu
  </code></pre>
  <p>But expanding on this, in the same <code>Makefile</code>, if I replace the target above with this one, it fails with the error &quot;No rule to make target&quot;:</p>
  <pre><code>$(BUILD_DIR)/sim_%: sim_%.cc % | $(BUILD_DIR)
     $(CC) $(STD) $(CFLAGS) -o $@ $&lt; -Wall -Wno-sign-compare
  </code></pre>
  <p>What am I doing wrong?</p>
  <p>EDIT: FYI, <code>BUILD_DIR</code> is created as follows:</p>
  <pre><code>$(BUILD_DIR):                                                                                                                          
     mkdir -p $@
  </code></pre>