title: Why there are 6 Base Address Registers (BARs) in PCIe endpoint?
body: <p>After some reading about the PCIe, I came around the PCI compatible configuration headers and after understanding the header there is Base address Register(BAR) field. Where there are total 6 BARs in each PCIe endpoint. Why there are 6 BARs and not just 2 (1 in case 32 bit address and 2 in case 64 bit). I mean what is the detailed functionality of all the BARs?
  <a href="https://i.stack.imgur.com/CIO78.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CIO78.jpg" alt="PCI Express PCI-Compatible Configuration Header"></a></p>