title: circuits gates in Python
body: <p>I have downloaded a program made in Python called logic.py from the following source:</p>
  
  <p><a href="http://www.openbookproject.net/courses/python4fun/logic.html" rel="nofollow noreferrer">http://www.openbookproject.net/courses/python4fun/logic.html</a></p>
  
  <p>By reading the source code it seems not so hard to understand, but the problem that I got is with the implementation of the XOR gate, I have labeled the figure with the gates I suppose that are correct and the code is below:</p>
  
  <p><img src="https://i.stack.imgur.com/euFuR.jpg" alt="enter image description here"></p>
  
  <pre><code>class Xor(Gate2):
      def __init__(self, name):
          Gate2.__init__(self, name)
          self.A1 = And("A1")   # See circuit drawing to follow connections
          self.A2 = And("A2")
          self.I1 = Not("I1")
          self.I2 = Not("I2")
          self.O1 = Or("O1")
          self.A.connect([self.A1.A, self.I2.A])
          self.B.connect([self.I1.A, self.A2.A])
          self.I1.B.connect([self.A1.B ])
          self.I2.B.connect([self.A2.B ])
          self.A1.C.connect([self.O1.A ])
          self.A2.C.connect([self.O1.B ])
          self.O1.C.connect([self.C ])
  </code></pre>
  
  <p>The question that I have is what are the following parts doing:</p>
  
  <pre><code>self.A.connect([self.A1.A, self.I2.A])     (*)
  self.B.connect([self.I1.A, self.A2.A])     (**)
  </code></pre>
  
  <p>because for what I see the output of the NOT gate (I1) connects to the second input of the AND gate (A1), and then the output of the I2 connects to the second input of A2. At the end both outputs of A1 and A2 (which are C) connects as inputs of the OR gate. So what is the purpose of (* and **)? I do not see where they are attached in the circuit.</p>
  
  <p>Any tip?</p>
  
  <p>PD. I have tested the program by using Python 2.5 and 2.7; and in both cases I got an error in the following line:</p>
  
  <pre><code>print(int(F3.Cout.value), end='')
  </code></pre>
  
  <p>it is in the test4bit function, so I had to erase it; I said that just in case somebody got the same error.</p>
  
  <p>Update: According to the solutions they gave me, this particular line:</p>
  
  <pre><code>self.A.connect([self.A1.A, self.I2.A])
  </code></pre>
  
  <p>I suppose that is getting connected as the input A from the AND gate A1, but where does it says that in the code? That is the part in which I am lost.</p>
  
  <p>Thanks</p>