title: VHDL driving signal from different processes
body: <p>I have a little problem with following VHDL code:</p>
  
  <pre><code>process (zbroji)
  begin
      if rising_edge(zbroji) then
          oduzima &lt;= '0';
          ucitanPrvi &lt;= '1';
          broj1 &lt;= ulaz_broj;
      end if;
  end process;
  
  process (oduzmi)
  begin
      if rising_edge(oduzmi) then
          oduzima &lt;= '1';
          ucitanPrvi &lt;= '1';
          broj1 &lt;= ulaz_broj;
      end if;
  
  end process;
  </code></pre>
  
  <p>The problem is that signal ucitanPrvi always has value X. If I don't try to set it's value in two processes, then I don't have any problems ... So I know that I mustn't drive one signal from multiple processes, but I don't know how to write this differently ...
  Does anyone have an idea how I could resolve this problem ?</p>
  
  <p>Thanks !</p>
  
  <p>EDIT: Thank you all guys for replying :) Now I understand why I can't drive one signal from multiple processes (at least in the way I wanted it to work).</p>