title: Makefile: using variable with computed name as prerequisite
body: <p>In Make it's possible to compute variable names in runtime using double-evaluation, like <code>$($(var))</code>.</p>
  
  <p>I'm interested if it's possible somehow to make this work:</p>
  
  <pre><code>one.js_DEPS=a b
  two.js_DEPS=c b
  
  all: one.js two.js
  
  %.js: $(%.js_DEPS)
      cat $^ &gt; $@
  </code></pre>
  
  <p>I can make this work by declaring two rules with explicit dependencies, like this:</p>
  
  <pre><code>one.js: $(one.js_DEPS)
  </code></pre>
  
  <p>But this seems a bit anti-DRY. So I'm wondering if I miss something because make doesn't seem to understand me. I use GNU Make 3.81.</p>