title: How to implement cleanall in when a common make file is used
body: <p>Hi I am using common makefile.inc for my project.  For my src folders, I define a makefile which sets some variables and includes makefile.inc.  I can also define DIRS= variable (sample #2) which will call make -C on each one of the directories specified there.   This all works.  However, I cannot get a "clean" or "cleanall" to work properly.  If DIRS= is defined, I need a way to go through all the directories listed and call "make -C xxx clean".   Any ideas?</p>
  
  <h2>Sample makefile #1</h2>
  
  <pre><code>TYPE = exe
  SOURCES = test.cpp
  INCLUDES = -I. -I/usr/local/include -I../src
  LIBS = -lpcre
  OUT = test
  
  include ../../makefile.inc
  </code></pre>
  
  <h2>Sample makefile #2</h2>
  
  <pre><code>DIRS = src test
  
  include ../makefile.inc
  </code></pre>
  
  <h2>makefile.inc</h2>
  
  <pre><code>OBJS = $(SOURCES:.cpp=.o)
  
  ifeq ($(CFG),)
  CFG=debug
  endif
  
  ifeq ($(CFG),debug)
  CXXFLAGS += -g -Wall -DNDEBUG
  else
  CXXFLAGS += -O2 -Wall
  endif
  
  all: dirs cfgcheck $(OUT)
  
  .PHONY: clean cleanall all
  
  cfgcheck:
  ifneq ($(CFG),release)
  ifneq ($(CFG),debug)
      @echo "Error: Invalid CFG '$(CFG)'' (options: debug,release)"
      @exit 1
  endif
  endif
      @echo "Making '$(CURDIR)' CFG="$(CFG)
  
  $(OUT): $(OBJS)
  ifeq ($(TYPE),lib)
      $(AR) rcs $(OUT) $(OBJS)
  endif
  ifeq ($(TYPE),exe)
      $(CXX) -o $@ $^ ${LDFLAGS} $(LIBS)
  endif
  
  -include $(OBJS:.o=.d)
  
  %.o: %.cpp
      $(CXX) -c $(INCLUDES) $(CXXFLAGS) $*.cpp -o $*.o
      $(CXX) -MM $(CXXFLAGS) $*.cpp &gt; $*.d
      @cp -f $*.d $*.d.tmp
      @sed -e 's/.*://' -e 's/\\$$//' &lt; $*.d.tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' &gt;&gt; $*.d
      @rm -f $*.d.tmp
  
  dirs: $(DIRS)
  $(DIRS):
      $(MAKE) -C $@
  
  clean:
      rm -f $(OUT) *.o *.d
  </code></pre>