title: verilog : Instantiation of modules in generate block with variable inputs
body: <p>I have just started with verilog and trying to implement a small block where I want to call a module inside the generate block but with variable parameters, like:</p>
  
  <pre><code>module abc(a,b,c,d)
  input a,b;
  output c,d;
  
  generate
  if(a=1) begin
  xyz xyz1(a,b,c,d);
  end 
  if(a=0) begin
  efj xyz1(a,b,c,d);
  endgenerate
  
  endmodule
  </code></pre>
  
  <p>The values of <code>a</code> and <code>b</code> are changing at every clock cycle. I know we can only use constant values in generate block but how can I handle this? Is there any way out?</p>