title: Confusion in VHDL code
body: <p>I am trying to implement a recoding logic for a 32 bit multiplier in VHDL. Besides, the input bit vector (<code>x_in</code>) to be recoded, it has one extra input "one". The intent is when "one" is <code>'1'</code> the output should be <code>x_in</code> else if "one" is <code>'0'</code>, it should be twice <code>x_in</code>. And if "neg" is high then the output has to be inverted. Here is my VHDL code:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use IEEE.std_logic_arith.all;
  
  package sum_vector_pkg is
      type partial_sum_array is array (0 to 15) of std_logic_vector(32 downto 0);
  end package;
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use IEEE.std_logic_arith.all;
  use work.sum_vector_pkg.all;
  use work.test.all;
  
  entity multipleGenerator is 
      generic(
             constant WIDTH : integer := 32
      );
      port(
          x_in      : in std_logic_vector(WIDTH - 1 downto 0);
          one       : in std_logic_vector(WIDTH/2 - 1 downto 0);
          multiple  : out partial_sum_array
      );
  end entity multipleGenerator;
  
  architecture logic of multipleGenerator is
      signal sum  : std_logic_vector(WIDTH downto 0);
  
  begin
      gen : for i in 0 to WIDTH/2 - 1 generate
          process (one,sum,x_in) is begin
              case one(i) is
                  when '0' =&gt; sum &lt;= x_in &amp; '0'; -- twice x_in
                  when '1' =&gt; sum &lt;= '0' &amp; x_in; -- same as x_in
                  when others =&gt; sum &lt;= x"00000000" &amp;'0';
              end case;
              multiple(i) &lt;= sum;
              report "The sum is " &amp; toString(sum) &amp; " one(i) is " &amp; toString(one(i)) &amp; " x_in is " &amp; toString(x_in);
          end process;
      end generate;
  end architecture logic;
  </code></pre>
  
  <p>I am running it with the following testbench:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use work.sum_vector_pkg.all;
  
  entity tb_multipleGenerator is
  
  end entity tb_multipleGenerator;
  
  architecture logic of tb_multipleGenerator is
  
      component multipleGenerator
          generic(
             constant WIDTH : integer := 32
          );
          port(
              x_in      : in std_logic_vector(31 downto 0);
              one       : in std_logic_vector(15 downto 0);
              multiple  : out partial_sum_array
          );
      end component;
  
      signal x_tb        : std_logic_vector(31 downto 0);
      signal one_tb      : std_logic_vector(15 downto 0);
      signal multiple_tb : partial_sum_array;
  
  begin
      process begin
          x_tb &lt;= x"00000000";
          one_tb &lt;= x"0000";
          wait for 200 ns;
          x_tb &lt;= x"00001111";
          one_tb &lt;= x"0011";
          wait;
      end process;
  
      u_mult: multipleGenerator
          generic map (
             WIDTH =&gt; 32
          )
          port map (
              x_in     =&gt; x_tb,   
              one      =&gt; one_tb,
              multiple =&gt; multiple_tb
          );
  end architecture logic;
  </code></pre>
  
  <p>To check the output I am using the following package:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use IEEE.std_logic_arith.all;
  
  package test is
      function toString(v : std_logic_vector) return string;
      function toString(b : std_logic) return string;
  end package;
  
  package body test is 
      function toString(b : std_logic) return string is
          variable str : string(1 to 3);
          begin
              str := std_logic'image(b);
              return "" &amp; str(2);
      end toString;
  
      function toString(v : std_logic_vector) return string is
          variable str    : string(1 to 1);
          variable strOut : string(1 to v'length);
          begin
              for i in 1 to v'length  loop
                  str := toString(v(i-1));
                  strOut(v'length - i + 1) := str(1);
              end loop;
              return strOut;
      end toString;
  end test;
  </code></pre>
  
  <p>When I run the above code I get <code>'X'</code> in the output. Here is the sample output:</p>
  
  <pre><code>    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(12)
  # ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
  #    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(13)
  # ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
  #    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(14)
  # ** Note: The sum is 0000000000000000000XX00XX00XX00XX one(i) is 0 x_in is 00000000000000000001000100010001
  #    Time: 200 ns  Iteration: 2  Region: /tb_multiplegenerator/u_mult/gen(15)
  </code></pre>
  
  <p>Could someone please explain why this code is not working?</p>