title: How to vary a struct going through a port in system verilog - generate doesnt work
body: <pre><code>module testy
      #(
          parameter W = 10,
          parameter C = 2
       )
       (
           aa
       );
  
     generate
        if (W == 8)
          begin:W8
             if(C == 1)
                  begin:W8C1
                  typedef struct {
                     logic [8:0] so;
                  }my_struct;
  
                  end 
             if(C == 2)
               begin:W8C2
                  typedef struct {
                     logic [10:0] so;
                  }my_struct;
               end
          end
     endgenerate
  
  input my_struct aa;
  
  endmodule
  </code></pre>
  
  <p>I get this error:</p>
  
  <pre><code>irun(64): 14.20-p001: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
  file: testy.v
  input my_struct aa;
                |
  ncvlog: *E,SVNOTY (testy.v,30|14): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
      module worklib.testy:v
          errors: 1, warnings: 0
  ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
  irun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 2).
  </code></pre>
  
  <p>I thought generates were statically determined but I have problems compiling it - since parameters cant be overridden in packages and couldn't think of a way to do this in design which needs to be synthesized and didn't want to add interfaces or classes. Is there a bettwe way to do this. My struct has over 100 entries if I include all the combinations and use only what I want but I thought using generates I could trim it to what I want based on a set of parameters. </p>
  
  <p>Thanks</p>