title: Unexpected "end" and "endmodule" in Test Bench?
body: <p>I'm working on a Verilog project where I need to find the 9's complement of a 4-bit binary number. I wrote a module that I believe should work, but I'm     having a strange error with the testbench:</p>
  
  <pre><code>module test_nine();
  
  reg [3:0] A; //inputs
  
  wire w,x,y,z; //outputs
  
  integer loop_counter; //for loop counter
  
  NinesComplement nc0(A[0],A[1],A[2],A[3],w,x,y,z);
  
  initial
    begin
  
    for(loop_counter=0; loop_counter&lt;16; loop_counter=loop_counter+1)
    begin
    #8 A=loop_counter;
    end
  
    #8 $finish()
    end
  endmodule
  </code></pre>
  
  <p>When I run it, I get an error: </p>
  
  <blockquote>
    <p>Unexpected token "end" and "endmodule" found.</p>
  </blockquote>
  
  <p>Aren't those necessary? Just in case the error is in my main module, I'll add it below:</p>
  
  <pre><code>module NinesComplement(a,b,c,d,w,x,y,z);
  
  //inputs
  input a,b,c,d;
  
  //outputs
  output w,x,y,z;
  
  //wires
  wire ab,an,bn,cn,dn;
  
  
  not #8
  //creates a'
  n0a(an,a),
  
  //creates b'
  n0b(bn,b),
  
  //creates c'
  n0c(cn,c),
  
  //creates d'
  n0d(dn,d);
  
  
  and #8
  a0a(ab,an,bn),
  
  a0b(w,ab,cn),
  
  a0c(y,c,c);
  
  xor #8
  
  x0a(x,b,c);
  
  
  nand #8
  
  n1a(z,dn,dn);
  
  endmodule
  </code></pre>