title: Convolution of signals using VHDL
body: <p>I have been working on implementing convolution operation using VHDL in MultiSim Student PE Edition. The following code compiles successfully, however When I click Simulate i am getting the following error:</p>
  
  <pre><code># vsim 
  # Start time: 10:32:20 on Apr 26,2015
  # Loading std.standard
  # ** Error: (vsim-13) Recompile work.convolution because work.convolution has changed.
  # 
  # ** Error (suppressible): (vsim-12) Recompile work.convolution(behavioral) after work.convolution, work.convolution are recompiled.
  # 
  # Error loading design
  </code></pre>
  
  <p>Here is the source code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.std_logic_arith.all;
  
  package Convolution IS
      TYPE real_vector is ARRAY(integer RANGE &lt;&gt;) OF real;
  end;
  
  use work.Convolution.ALL;
  
  entity convolution is
      port (x:in real_vector(0 to 3);
            h:in real_vector(0 to 1);
            y:out real_vector (0 to 4));
  end convolution;
  
  
  
  architecture Behavioral of convolution is
  BEGIN   
      process (x,h)
      variable sum :real := 0.0;
      variable temp :integer := 0;
  
      begin
      for k in y'range loop
          sum:=0.0;
          for n in h'range loop
                  temp := k-n;
              if temp &gt;= 0 then
                  sum := sum + h(n)*x(temp);  --we are assuming all singnals are positively indexed, negative indices deafult to 0.       
              end if;
              end loop;
              y(k) &lt;= sum ;
      end loop;
      end process;
  end Behavioral;
  </code></pre>
  
  <p>Help me with this issue please.</p>