title: Makefile always rebuilding
body: <p>I am using the following simple Makefile to build some simple files. I am really new to making Makefile. I don't know why it keeps in rebuilding even though the files are built after first make and I am not editing any of the file.</p>
  
  <pre><code>EXE    = nextgenrsm
  CC     = gcc
  LIBS   = StarterWare_Files/
  CFLAGS = -c 
  
  INCLUDE_PATH =  StarterWare_Files/
  
  MAIN_SRC = $(wildcard *.c)
  MAIN_OBS = $(patsubst %.c,%.o,$(MAIN_SRC))
  
  LIB_SRC = $(wildcard StarterWare_Files/*.c)
  LIB_OBS = $(patsubst StarterWare_Files/%.c,%.o,$(LIB_SRC))
  
  output: $(EXE)
  
  $(EXE): $(MAIN_OBS) $(LIB_OBS)
      $(CC) $(MAIN_OBS) $(LIBS)$(LIB_OBS) -o $(EXE) 
  
  $(MAIN_OBS): $(MAIN_SRC) 
      $(CC) $(CFLAGS) *.c -I$(INCLUDE_PATH)
  
  $(LIB_OBS): $(LIB_SRC) 
      cd $(LIBS); \
      $(CC) $(CFLAGS) *.c -I../
  
  clean:
      rm -rf $(LIBS)*.o $(EXE) *.o
  </code></pre>
  
  <p><strong>NEW EDITED MAKEFILE</strong></p>
  
  <pre><code>EXE    = nextgenrsm
  CC     = gcc
  LIBS   = StarterWare_Files/
  CPPFLAGS = _IStarterWare_Files/
  
  
  MAIN_OBS = $(patsubst %.c,%.o,$(wildcard *.c))
  LIB_OBS  = $(patsubst %.c,%.o,$(wildcard StarterWare_Files/*.c))
  
  all: $(EXE)
  
  $(EXE): $(MAIN_OBS) $(LIB_OBS)
     $(CC) -o $@ $(LDFLAGS) $(MAIN_OBS) $(LIB_OBS) $(LDLIBS)
  
  %.o: %.c 
     $(CC) -o $@ -MD -MP $(CPPFLAGS) $(CFLAGS) -c $^
  
  ALL_DEPS = $(patsubst %.o,%.d,$(MAIN_OBS), $(LIB_OBS))
  -include $(ALL_DEPS)
  
  clean:
     rm -f $(LIB_OBS) $(EXE) $(MAIN_OBS) $(ALL_DEPS)
  
  .PHONY: all clean
  </code></pre>
  
  <p>Whenever I do touch StarterWare_Files/example.h and try to do make again it throws me error that gcc cannot specify -o with -c or -S with Multiple files. Basically the command becomes something like this gcc -o main.o -IStarterWare_Files -c main.c StarterWare_Files/test.h StarterWare_Files/add.h..</p>