title: ModelSim Error Loading Design
body: <p>I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (<code>Compile &gt; Compile All</code>), I'm typing <code>vsim</code> into the console, and the only error thrown is</p>
  
  <pre><code># vsim
  # Start time: [time]
  # Error loading design
  </code></pre>
  
  <p>Is there any way of having <code>vsim</code> be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong?</p>
  
  <p>For reference, my code is below:</p>
  
  <p><strong>methods.v</strong></p>
  
  <pre><code>module dFlipFlop(
      D,
      Clk,
      En,
      Q
  );
  
  input D, Clk, En;
  output Q;
  reg Q;
  
  always @ (posedge Clk)
  if(~En) begin
      Q &lt;= 1'b0;
  end else begin
      Q &lt;= D;
  end
  
  endmodule
  
  module masterSlaveDFF(
      D,
      Clk,
      En,
      Q
  );
  
  input D, Clk, En;
  output Q;
  
  wire Y, inClk;
  
  assign inClk = ~Clk;
  
  dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y));
  dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q));
  
  endmodule
  </code></pre>
  
  <p><strong>dflipflop.v</strong> (My Testbench)</p>
  
  <pre><code>`include "methods.v"
  
  module masterSlaveTest();
  
  reg D, Clk, En, Q;
  
  initial begin
      $monitor(D, Clk, En, Q);
  
      D = 1;
      Clk = 1;
      En = 0;
  
      #5 $finish;
  end
  
  always begin
      #5 Clk = ~Clk;
  end
  
  endmodule
  </code></pre>