title: How to run multiple testcases in verilog?
body: <p>I have written my testcases in "tc1.v" and "tc2.v". The test cases are in the form of tasks. for example:</p>
  
  <pre><code>//tc1.v
  
  task tc1(input reg [31:0] j,input reg Reset,output reg dataValidIn);
  
   //logic
  endtask
  
  //tc2.v
  
  task tc2(input reg [31:0] counter,input reg Reset,output reg dataValidIn);
  
  //logic
  
  endtask
  
  
  module top_test;
  
    //inputs and outputs
    //logic
  
     `ifdef testcase1
        `include "tc1.v";
     `else 
       `include "tc2.v"
     `endif
  
  
  endmodule
  </code></pre>
  
  <p>Problem is I want to run the testcases for every posedge clock. If I include the 'ifdef part in always block, modelsim throws an error. Is there anyway I can achieve this?</p>