title: What is wrong with my partial product generator
body: <p>I'm trying to write VHDL code for a partial product generator. The code is as follows: </p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_signed.all;
  use ieee.numeric_std.all;
  entity boothencoder_ppg is
  port(Y: in std_logic_vector(53 downto 1);
       X: in std_logic_vector(53 downto 1);
       PPG: out std_logic_vector(53 downto 1)
       );
  end boothencoder_ppg;
  architecture behavioral of boothencoder_ppg is
  signal U, SFT, W, M, A: std_logic;
      begin
      for m in 1 to 53 loop
      U = Y(m+1) xnor Y(m);
      SFT = Y(m-1) xnor Y(m);
      W = U and SFT;
      M = SFT? X(m-1) : X(m);
      A = M xor Y(m+1);
      PPG = A nor W;
      end loop;
  end behavioral;
  </code></pre>
  
  <p>I'm getting errors in all the lines within the loop. Perhaps I have implemented the loop incorrectly? Any help would be great.</p>
  
  <p>Thanks.</p>