title: Verilog always@(..) output not working as expected
body: <p>So, im trying to synthesize my verilog code to send data from ps2 keybord ->fpga->vga. Just for the background of the code, I want to press the button "1", and that to appear on the center of the screen (called the display_area)</p>
  
  <p>I realised that something is not working as expected.
  After carefull debugging, i realised that the problem lies in the module that converts the parallel data bus from the rom, into serial output, to assign a value in each pixel. </p>
  
  <p>The code itself is pretty simple, im just providing as much info as i can.</p>
  
  <p>We need a positive edge of the clock to enter the always area (or a reset). If the value display_area_enable is 1, we activate a counter from 7 till 0 (8 cycles) to index the data from the rom.</p>
  
  <p>However, on the first clock, if the display area becomes 1 the exact moment when the vga_clk pulse becomes 1, the counter gets the value as it should, but the one_bit_output (the output of the module) doesnt. One_bit_output gets its first correct value the 2nd time that the always block is accessed. as a result we need 9 cycles to access an 8 bit bus.</p>
  
  <p>I ll provide the code and a modelsim testbench</p>
  
  <pre><code>module shifter(reset,char_rom_data_out,vga_clk,display_area_enable,one_bit_output,counter);
  input [7:0]char_rom_data_out;
  input vga_clk,display_area_enable,reset;
  output reg one_bit_output;
  output reg [2:0]counter;
  always @(posedge vga_clk or posedge reset)
  begin
  if (reset)
      begin
          counter=3'd7;
          one_bit_output=0;
      end
      else if (display_area_enable==1)
          begin 
          one_bit_output&lt;=(char_rom_data_out[counter]==1);
          counter&lt;=counter-1;
          end
      else if (display_area_enable==0) 
      begin
      counter&lt;=3'd7;
      one_bit_output&lt;=0;
     end
  end
  endmodule
  
  module testbz();
  reg reset,vga_clk,display_area_enable;
  reg [7:0]char_rom_data_out;
  wire [2:0] counter;
  wire one_bit_output;
  
  shifter dignitas(reset,char_rom_data_out,vga_clk,display_area_enable,one_bit_output,counter);
  
  initial 
  begin
  reset&lt;=1; char_rom_data_out&lt;=8'b11110001; vga_clk&lt;=0;display_area_enable=0; //sto 10 skaei o prwtos kyklos, kai meta ana 20
  #5 reset&lt;=0; display_area_enable&lt;=0;
  #5 display_area_enable&lt;=1;
  #160 display_area_enable&lt;=0;
  end
  always
  begin
   #10 vga_clk=~vga_clk;
   end
  
  endmodule
  </code></pre>
  
  <p>and the simulation is :</p>
  
  <p><a href="https://i.stack.imgur.com/8WtXg.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/8WtXg.png" alt="verilog simulation code"></a></p>
  
  <p>Can someone explain to me why on the first pulse of the vga_clk, the output is not expected?</p>