title: Object is used but not declared
body: <p>I understand this is a fairly common question. Regardless, having gone through forums, I couldn't find a satisfactory answer as to why I'm getting the following CT error, for the given VHDL code. Can you help me please?</p>
  
  <p>VHDL Code</p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  entity design is
  port(clk:IN std_logic;
  reset:IN std_logic;
  A:IN std_logic;
  B:IN std_logic;
  Q:OUT std_logic);
  end design;
  
  architecture behave of design is
  --signal R0,R1,R2,R3,R4:std_logic;
  begin
  process(clk,reset)
  variable R0,R1,R2,R3,R4:std_logic;
  begin
  if (reset='1') then
  R0:='0';
  R1:='0';
  R2:='0';
  R3:='0';
  R4:='0';
  elsif falling_edge(clk) then
  R0:=R4;
  R1:=R0 xor A;
  R2:=R1 xor B;
  R3:=R2;
  R4:=R2 xor R3;
  end if;
  end process;
  Q&lt;=R4;       -- ERROR POINTED HERE
  end behave;
  </code></pre>
  
  <p>Error:-</p>
  
  <pre><code>Error (10482): VHDL error at design.vhd(31): object "R4" is used but not declared
  </code></pre>
  
  <p>Is there a proper way of assigning variable to port, that I'm missing?</p>