title: memory bank conflict in parallel reduction sequential addressing
body: <p>I was reading a slide from NVIDIA discussing about parallel reduction algorithm available <a href="https://developer.download.nvidia.com/assets/cuda/files/reduction.pdf" rel="nofollow noreferrer">here</a>.</p>
  <p>in slide 15:
  <a href="https://i.stack.imgur.com/nlLZD.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/nlLZD.png" alt="enter image description here" /></a></p>
  <p>the writer discusses that using sequential addressing, we avoid memory bank conflict. I think this is wrong and here is my reason:
  in slide 10, we assume that each thread block has 128 threads inside. in the sequential code provided in the blue box in the picture, thread 0 tries to use both <code>sdata[0]</code> and <code>sdata[64]</code> at the same and since we have 32 memory banks, these 2 accesses lead to a memory bank conflict.
  Which part of my inference is wrong?</p>