title: vhdl error code 10500 for keywords already present
body: <p>This code is for a PRBS (pseudo-random binary sequence) receiver. it is supposed to take three values and simulate a PRBS generator and check the obtained vales with the values generated.
  But the code is showing errors for keywords like begin which are already present</p>
  
  <pre><code>    library ieee;
      use ieee.std_logic_1164.all;
      use ieee. std_logic_arith.all;
      use ieee. std_logic_unsigned.all;
  
      entity receiver is
      port(
          inp : in std_logic;
          clock : in std_logic;
          count : out std_logic_vector(4 downto 0);
          check : out std_logic);
      end receiver;
  
      architecture rec of receiver is
      signal P : std_logic_vector(2 downto 0);
      signal O : std_logic_vector(2 downto 0);
  
      process (clock)
          variable cnt  : integer range 0 to 3;
          begin
              if clock'event and clock='1'  then
                  P &lt;= inp &amp; P(2 downto 1);
                  cnt&lt;=cnt+1;
              end if;
              if (cnt = 3) then
                  O&lt;=P;
                  elseif (cnt &gt;3)
                  O &lt;= inp &amp; O(2 downto 1);
              end if;
              if((O(2) xor O(0)) = P(0))  
                  check &lt;= '0';
              else
                  check &lt;= '1';
                  count &lt;= count +1;
              end if;
          end process;
      end rec;
  </code></pre>
  
  <blockquote>
    <p>Error (10500): VHDL syntax error at receiver.vhd(18) near text "process";  expecting "begin", or a declaration statement</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(21) near text "if";  expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(21) near text "and";  expecting "(", or "'", or "."</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(24) near text "if";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(25) near text "then";  expecting "&lt;="</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(28) near text "O";  expecting "(", or "'", or "."</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(29) near text "if";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(31) near text "check";  expecting "&lt;="</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(32) near text "else";  expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement</p>
    
    <p>Error (10500): VHDL syntax error at receiver.vhd(35) near text "if";  expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"</p>
  </blockquote>