title: Is the ++ operator in System Verilog blocking or non-blocking?
body: <p>Good coding convention says that we should use blocking assignments in a combinational block, and non-blocking assignments in a sequential block.  I want to use the <code>++</code> operator in a combinatorial block, but I don't know if it is blocking.  So is this code:</p>
  
  <pre><code>input [3:0] some_bus;
  logic [2:0] count_ones;
  always_comb begin
    count_ones = '0;
    for(int i=0; i&lt;4; i++) begin
      if(some_bus[i])
        count_ones++;
    end
  end
  </code></pre>
  
  <p>equivalent to this:</p>
  
  <pre><code>input [3:0] some_bus;
  logic [2:0] count_ones;
  always_comb begin
    count_ones = '0;
    for(int i=0; i&lt;4; i++) begin
      if(some_bus[i])
        count_ones = count_ones + 1;
    end
  end
  </code></pre>
  
  <p>or this:</p>
  
  <pre><code>input [3:0] some_bus;
  logic [2:0] count_ones;
  always_comb begin
    count_ones = '0;
    for(int i=0; i&lt;4; i++) begin
      if(some_bus[i])
        count_ones &lt;= count_ones + 1;
    end
  end
  </code></pre>
  
  <p>I did look in the 1800-2012 standard but could not figure it out.  An answer that points me to the appropriate section in the standard would be appreciated.</p>