title: Verilog HDL error: Illegal left-hand side assignment
body: <p>I am learning CPU Design and basic Verilog HDL. I have a processor running in tkgate on Fedora 29 and I have designed a hardware RAM disk. I can't test the RAM but have decided to replace it with an HDL RAM disk. Whenever I try to simulate the circuit, I get the error:<br>
  <strong>RAM_HDL, line 17: Illegal use of 'w7' in left-hand-side assignment.</strong><br>
  Here is my code for the RAM:  </p>
  
  <pre><code>module RAM_HDL(RAM, Data_In, Data_Out, Address, RW);  
      reg [15:0] RAM [127:0];  
      wire [15:0] Data_In;  
      wire [15:0] Data_Out;  
      wire [7:0] Address;  
      wire RW;  
  
      initial  
          $readmemb("RAM_DATA.BIN", RAM);  
  
      always @(*)  
          begin  
              if (RW)  
                  RAM[Address] &lt;= Data_In;  
              Data_Out &lt;= Address;  
          end  
  
     endmodule  
  </code></pre>
  
  <p>The error is on line 17:  </p>
  
  <pre><code>Data_Out &lt;= Address;  
  </code></pre>