title: VHDL inout port set to high impedance
body: <p><strong>UPDATE</strong></p>
  
  <p>I updated the testbench code but now, it seems that databuffer doesn't drive the signals. </p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  ENTITY databus_buffer_tb IS
  END databus_buffer_tb;
  
  
  ARCHITECTURE dataflow OF databus_buffer_tb IS
    SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL T_Ctrl:STD_LOGIC:='0';
    COMPONENT databus_buffer IS
        PORT
           (
             --IDATA represent the bus lines that comes from the uC for reading and writing;
             --ODATA represents the bus lines that communicate with the internal bus;
             IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
             CTRL:     IN      STD_LOGIC;
             ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000"
       );
     END COMPONENT;
  
  BEGIN
    databuffer:databus_buffer PORT MAP
      (
        IDATA=&gt;T_Idata,
        CTRL=&gt;T_Ctrl,
        ODATA=&gt;T_Odata
        );
    PROCESS
    BEGIN
  
  
  
      T_Idata&lt;="00001111";
  
      T_Ctrl&lt;='0';
      WAIT FOR 10 ns;
      assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;
  
      T_Odata&lt;="11110000";
  
      T_Ctrl&lt;='1';
      WAIT FOR 10 ns;
      assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;
  
  
      T_Ctrl&lt;='Z';
      WAIT FOR 10 ns;
      assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
      assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
      wait;
    END PROCESS;
  END dataflow;
  </code></pre>
  
  <p>And <a href="https://i.stack.imgur.com/IlMoc.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/IlMoc.png" alt="enter image description here"></a></p>
  
  <hr>
  
  <p>I tried to understand how INOUT port should be implemented in VHDL but I failed. 
  Here is the code:</p>
  
  <pre><code>    library ieee;
  use ieee.std_logic_1164.all;
  ----------------------------
  -- Databus Buffer
  ----------------------------
  ENTITY databus_buffer IS
  -- data bus buffer have the next ports:
  -- IDATA:        8 bit bus       -&gt;inout
  -- CTRL:        1 bit control   -&gt;in
  -- ODATA:       8 bit bus       -&gt;inout
      PORT
      (
          --IDATA represent the bus lines that comes from the uC for reading and writing;
          --ODATA represents the bus lines that communicate with the internal bus;
              IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
              CTRL:     IN      STD_LOGIC;
              ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
          );
  
  
  
  END databus_buffer;
  ARCHITECTURE behaviour OF databus_buffer IS
  -- behaviour of databus buffer;
  
  BEGIN
  -- is a 3 state bidirection 8 bit buffer.
  -- if CTRL is 1, IDATA=ODATA; reading from counter operation
  -- if CTRL is 0, ODATA=IDATA; writing to control word
  -- if CTRL is Z, IDATA=Z; this happens when nor read and write are active but
  -- cs is active;
  -- also, data bus can be in 3rd state if the chip is not selected, this means
  -- that CTRL will be Z;
  
  
      ODATA&lt;=IDATA WHEN CTRL='0' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=&gt;'Z');
      IDATA&lt;=ODATA WHEN CTRL='1' else "ZZZZZZZZ" WHEN CTRL='Z' else (OTHERS=&gt;'Z');
  
  
  
  END behaviour;  
  </code></pre>
  
  <p>This code works when CTRL is 0 or 1. But when I set CTRL to be 'Z', in high impedance, IDATA and ODATA are not set to high impedance.</p>
  
  <p>My testbench:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  ENTITY databus_buffer_tb IS
  END databus_buffer_tb;
  
  
  ARCHITECTURE dataflow OF databus_buffer_tb IS
    SIGNAL T_Idata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL T_Odata:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
    SIGNAL T_Ctrl:STD_LOGIC:='0';
    COMPONENT databus_buffer IS
        PORT
           (
             --IDATA represent the bus lines that comes from the uC for reading and writing;
             --ODATA represents the bus lines that communicate with the internal bus;
             IDATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
             CTRL:     IN      STD_LOGIC;
             ODATA:    INOUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
     END COMPONENT;
  
  BEGIN
    databuffer:databus_buffer PORT MAP
      (
        IDATA=&gt;T_Idata,
        CTRL=&gt;T_Ctrl,
        ODATA=&gt;T_Odata
        );
    PROCESS
    BEGIN
      T_Idata&lt;="00000000";
      T_Odata&lt;="00000000";
      T_Ctrl&lt;='0';
  
      T_Idata&lt;="00001111";
      T_ODATA&lt;="ZZZZZZZZ";
      T_Ctrl&lt;='0';
      WAIT FOR 10 ns;
      assert(T_Odata="00001111") REPORT "Expected 00001111" SEVERITY error;
  
      T_Odata&lt;="11110000";
      T_IDATA&lt;="ZZZZZZZZ";
      T_Ctrl&lt;='1';
      WAIT FOR 10 ns;
      assert(T_Idata="11110000") REPORT "Expected 11110000" SEVERITY error;
  
      T_IData&lt;="00000000";
      T_OData&lt;="00000000";    
      T_Ctrl&lt;='Z';
      WAIT FOR 10 ns;
      assert(T_Idata="ZZZZZZZZ") REPORT "Expected Z FOR T_Idata" SEVERITY error;
      assert(T_Odata="ZZZZZZZZ") REPORT "Expected Z FOR T_Odata" SEVERITY error;
      wait;
    END PROCESS;
  END dataflow;
  </code></pre>
  
  <p>Also, how can be controlled the inout ports in a process, in a sequential way?</p>