title: module selection in verilog
body: <p>I have a group of modules, say module_1, module_2, ... module_N. They perform similar yet different logic operations (out = logic_n). However, since the N is very large (thousands), it is unfeasible to use them in a higher level module by manually instantiate them. I was trying to write a python code for this. I was also wondering is that possible to use parameterized module for this purpose? What I mean is something like.</p>
  
  <pre><code>module module_generic(in, out)
  
  parameter module_number;
  
  case (module_number) 
  
     0 : out = logic_1; 
  
     1 : out = logic_2; 
  
     ...
  
     N : out = logic_N;
  
  endcase
  
  endmodule
  </code></pre>
  
  <p>By doing this, I can use generate statement to easily generate the code in the higher level module. Has anyone try this method before? Can it behave like the way I want? After synthesis, is it equivalent to the brute-force solution?</p>