title: Problem with getting the right values of the signals in my vhdl code
body: <p>I am working on my diploma thesis and I am writing in VHDL. In my code as it is shown below, I have assigned values to the two signals (<code>counting</code> and <code>get_lbp_from_blks</code>) at the same time. However, in my simulation wave in Modelsim I see that signal <code>get_lbp_from_blks</code> gets value <code>1</code> two cycles earlier than signal <code>counting</code>. Do you have any idea why is this happening? <a href="https://i.stack.imgur.com/y4QA2.jpg" rel="nofollow noreferrer">Waveform from Modelsim</a></p>
  
  <pre><code>if (making_blocks = '1') then 
      ...doing some stuff...
      making_blocks &lt;= '0';
      get_lbp_from_blks &lt;= '1';
      counting &lt;= '1';
      incr_i &lt;= '1';
  end if;
  </code></pre>
  
  <p>PS: Modelsim shows me a message </p>
  
  <pre><code>** Warning: Design size of 34160 statements or 279 leaf instances exceeds ModelSim PE 
  Student Edition recommended capacity.
   Expect performance to be quite adversely affected.". 
  </code></pre>
  
  <p>Is there any possibility that this affects my code?</p>
  
  <p>Thanks in advance!</p>