title: Is there a way to ignore combinational loop error in HDL code?
body: <p>I am trying to formally verify a small module in a very big Project code. I have anayzed and elaborated the design. I cannot verify the small module because the tool gives me a "Found Combinational Loop" error. </p>
  
  <p>I am quite sure that this small module is not affected by this Loop error. So i want to avaid getting this error. Is it even possible?</p>
  
  <p>Thanks!</p>