title: Verilog compiler error
body: <pre><code>    module router (clock, ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3, PacketIn0, PacketIn1, PacketIn2, PacketIn3, PacketOut0, PacketOut1, PacketOut2, PacketOut3);
  
     input   clock;
     input   ValidPacket0, ValidPacket1, ValidPacket2, ValidPacket3;  
     input [7:0] PacketIn0, PacketIn1, PacketIn2, PacketIn3;
     output [7:0] PacketOut0,PacketOut1, PacketOut2, PacketOut3;
  
     reg [3:0]   bvp, vp;
     reg [1:0]   counter0, counter1, counter2, counter3;
     reg [2:0]   sel0, sel1, sel2, sel3;
     reg [3:0]   zero=0;
     reg [7:0]   addr0, addr1, addr2, addr3, out0, out1, out2, out3l;
     wire        np0, np1, np2, np3;
     wire [7:0]  PacketOut0, PacketOut1, Packetout2, Packetout3;
  
     always@(posedge clock)
       bvp[0]&lt;=ValidPacket0;
     if (ValidPacket0 &amp;&amp; !bvp[0]) vp[0]=1'b1;
     else vp[0]=0;
  </code></pre>
  
  <p>The above code gives me the following error:</p>
  
  <pre>
  ** Error: proj1a.v(23): near "[": syntax error, unexpected '[', expecting "IDENTIFIER" or "TYPE_IDENTIFIER" or '#' or '('
  Line 23 is at the if statement.
  </pre>
  
  <p>Any Insight?</p>