title: Reusable code in PSL(VHDL)
body: <p>Currently I'm writing assertions using PSL (RTL is in VHDL). Totally 30 + IPs are there I want to reuse the same psl file for all the modules</p>
  
  <pre><code>vunit IP1_assert ip1_top() {
  
  signal reg_1 :std_uloic_vector(15 downto 0);
  
  reg_1 : &lt;= signal ip_1.inst_1.inst_2.clk_reg : std_ulogic_vector(15 downto 0)&gt;&gt;;
  
  }
  
  vunit IP2_assert ip2_top() {
  
  signal reg_1 :std_uloic_vector(15 downto 0);
  
  reg_1 : &lt;= signal ip_2.inst_1.inst_2.clk_reg : std_ulogic_vector(15 downto 0)&gt;&gt;;
  
  }
  </code></pre>
  
  <p>How to change the above one as reusable one (i.e 2 Vunits into one).</p>
  
  <p>In other words any ideas:</p>
  
  <ol>
  <li>to replace the pathnames  ip_1 and ip_2 as generic one, </li>
  <li>can we pass entity name as a parmeter to PSL Vunit?</li>
  </ol>