title: Simple subtraction in Verilog
body: <p>I've been working on a hex calculator for a while, but seem to be stuck on the subtraction portion, particularly when B>A. I'm trying to simply subtract two positive integers and display the result. It works fine for A>B and A=B. So far I'm able use two 7-segment displays to show the integers to be subtracted and I get the proper difference as long as A>=B </p>
  
  <p>When B>A I see a pattern that I'm not able to debug because of my limited knowledge in Verilog case/if-else statements. Forgive me if I'm not explaining the best way but what I'm observing is that once the first number, A, "reaches" 0 (after being subtracted from) it loops back to F. The remainder of B is then subtracted from F rather than 0.</p>
  
  <p>For example: If A=1, B=3</p>
  
  <p>A - B =</p>
  
  <p>1 - 1 = 0</p>
  
  <p>0 - 1 = F</p>
  
  <p>F - 1 = E </p>
  
  <p>Another example could be 4-8=C</p>
  
  <p>Below are the important snippets of code I've put together thus far.</p>
  
  <p>First, my subtraction statement</p>
  
  <pre><code>always@*
      begin
          begin
                   Cout1 = 7'b1000000; //0
          end
  
  case(PrintDifference[3:0])
      4'b0000 : Cout0 = 7'b1000000;   //0
      4'b0001 : Cout0 = 7'b1111001;   //1
      ...
      4'b1110 : Cout0 = 7'b0000110;   //E
      4'b1111 : Cout0 = 7'b0001110;   //F
    endcase
  end
  </code></pre>
  
  <p>My subtraction is pretty straightforward</p>
  
  <pre><code>output [4:0]Difference;
  output [4:0] PrintDifference;
  assign PrintDifference = A-B;
  </code></pre>
  
  <p>I was thinking I could just do something like</p>
  
  <pre><code>if A&gt;=B, Difference = B-A
  else, Difference = A-B
  </code></pre>
  
  <p>Thank you everyone in advance!</p>