title: New DCM CLK instantiation error?
body: <p>here's the code within the .xco file which was branched off my main vhdl file:</p>
  
  <pre><code>-- The following code must appear in the VHDL architecture header:
  ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
  component DCM_18
  port
   (-- Clock in ports
    CLK_IN1           : in     std_logic;
    -- Clock out ports
    CLK_OUT1          : out    std_logic
   );
  end component;
  
  -- COMP_TAG_END ------ End COMPONENT Declaration ------------
  -- The following code must appear in the VHDL architecture
  -- body. Substitute your own instance name and net names.
  ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
  your_instance_name : DCM_18
    port map
     (-- Clock in ports
      CLK_IN1 =&gt; CLK_IN1,
      -- Clock out ports
      CLK_OUT1 =&gt; CLK_OUT1);
  -- INST_TAG_END ------ End INSTANTIATION Template ------------
  </code></pre>
  
  <p>the goal was to produce a 18.432 MHz clk from a 50 MHz clock.  Here's the code I added to my main vhdl file:</p>
  
  <pre><code>clk: in std_logic;                         -- 50 MHz clock
  
  signal test_clk: std_logic; -- new 18.432 MHz clock
  -----------------------------------------------------
  
  
  component DCM_18
  port
  (-- Clock in ports
      CLK_IN1           : in     std_logic;
      -- Clock out ports
      CLK_OUT1          : out    std_logic
  );
  end component;
  
  -------------------------------------------------
  
  new_CLK : DCM_18
   port map
   (-- Clock in ports                      
   CLK_IN1 =&gt; clk,
     -- Clock out ports
   CLK_OUT1 =&gt; test_clk
   );
  </code></pre>
  
  <p><strong>However</strong>, I am recieving this error: </p>
  
  <blockquote>
    <p>ERROR:Xst:2035 - Port  has illegal connections. This port is
    connected to an input buffer and other components.</p>
  </blockquote>
  
  <p>Any ideas?</p>
  
  <p><strong>EDIT: COMPLETE CODE</strong></p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.math_real.all;
  
  entity basic_uart is
    generic (
      DIVISOR: natural := 120 -- DIVISOR = 50,000,000 / (16 x BAUD_RATE)
      -- 9600 -&gt; 120
       -- 19200 -&gt; 60
    );
    port (
      clk: in std_logic;                         -- clock
      reset: in std_logic;                       -- reset
  
      -- Client interface
      rx_data: out std_logic_vector(7 downto 0); -- received byte
      rx_enable: out std_logic;                  -- validates received byte (1 system clock spike)
      tx_data: in std_logic_vector(7 downto 0);  -- byte to send
      tx_enable: in std_logic;                   -- validates byte to send if tx_ready is '1'
      tx_ready: out std_logic;                   -- if '1', we can send a new byte, otherwise we won't take it
  
      -- Physical interface
      rx: in std_logic;
      tx: out std_logic
    );
  end basic_uart;
  
  architecture Behavioral of basic_uart is
  
      component DCM_18
      port
      (-- Clock in ports
          CLK_IN1           : in     std_logic;
          -- Clock out ports
          CLK_OUT1          : out    std_logic
      );
      end component;
  
    constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
  
    type fsm_state_t is (idle, active); -- common to both RX and TX FSM
  
    type rx_state_t is
    record
      fsm_state: fsm_state_t;                -- FSM state
      counter: std_logic_vector(3 downto 0); -- tick count
      bits: std_logic_vector(7 downto 0);    -- received bits
      nbits: std_logic_vector(3 downto 0);   -- number of received bits (includes start bit)
      enable: std_logic;                     -- signal we received a new byte
    end record;
  
    type tx_state_t is
    record
      fsm_state: fsm_state_t; -- FSM state
      counter: std_logic_vector(3 downto 0); -- tick count
      bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
      nbits: std_logic_vector(3 downto 0); -- number of bits left to send
      ready: std_logic; -- signal we are accepting a new byte
    end record;
  
    signal rx_state,rx_state_next: rx_state_t;
    signal tx_state,tx_state_next: tx_state_t;
  
    signal sample, test_clk: std_logic; -- 1 clk spike at 16x baud rate
    signal sample_counter: std_logic_vector(COUNTER_BITS - 1 downto 0); -- should fit values in 0..DIVISOR-1
  
  begin
  
  new_CLK : DCM_18
    port map
     (-- Clock in ports
      --CLK_IN1 =&gt; clk,
       CLK_IN1 =&gt; clk,
      -- Clock out ports
      CLK_OUT1 =&gt; test_clk
      );
  
    -- sample signal at 16x baud rate, 1 CLK spikes
    sample_process: process (clk,reset) is
    begin
      if reset = '1' then
        sample_counter &lt;= (others =&gt; '0');
        sample &lt;= '0';
      elsif rising_edge(clk) then
        if sample_counter = DIVISOR - 1 then
          sample &lt;= '1';
          sample_counter &lt;= (others =&gt; '0');
        else
          sample &lt;= '0';
          sample_counter &lt;= sample_counter + 1;
        end if;
      end if;
    end process;
  
    -- RX, TX state registers update at each CLK, and RESET
    reg_process: process (clk,reset) is
    begin
      if reset = '1' then
        rx_state.fsm_state &lt;= idle;
        rx_state.bits &lt;= (others =&gt; '0');
        rx_state.nbits &lt;= (others =&gt; '0');
        rx_state.enable &lt;= '0';
  
        tx_state.fsm_state &lt;= idle;
        tx_state.bits &lt;= (others =&gt; '1');
        tx_state.nbits &lt;= (others =&gt; '0');
        tx_state.ready &lt;= '1';
  
      elsif rising_edge(clk) then
        rx_state &lt;= rx_state_next;
        tx_state &lt;= tx_state_next;
  
      end if;
    end process;
  
    -- RX FSM
    rx_process: process (rx_state,sample,rx) is
    begin
      case rx_state.fsm_state is
  
      when idle =&gt;
        rx_state_next.counter &lt;= (others =&gt; '0');
        rx_state_next.bits &lt;= (others =&gt; '0');
        rx_state_next.nbits &lt;= (others =&gt; '0');
        rx_state_next.enable &lt;= '0';
        if rx = '0' then
          -- start a new byte
          rx_state_next.fsm_state &lt;= active;
        else
          -- keep idle
          rx_state_next.fsm_state &lt;= idle;
        end if;
  
      when active =&gt;
        rx_state_next &lt;= rx_state;
        if sample = '1' then
          if rx_state.counter = 8 then
            -- sample next RX bit (at the middle of the counter cycle)
            if rx_state.nbits = 9 then
              rx_state_next.fsm_state &lt;= idle; -- back to idle state to wait for next start bit
              rx_state_next.enable &lt;= rx; -- OK if stop bit is '1'
            else
              rx_state_next.bits &lt;= rx &amp; rx_state.bits(7 downto 1);
              rx_state_next.nbits &lt;= rx_state.nbits + 1;
            end if;
          end if;
  
          rx_state_next.counter &lt;= rx_state.counter + 1;
        end if;
  
      end case;
    end process;
  
    -- RX output
    rx_output: process (rx_state) is
    begin
      rx_enable &lt;= rx_state.enable;
      rx_data &lt;= rx_state.bits;
    end process;
  
    -- TX FSM
    tx_process: process (tx_state,sample,tx_enable,tx_data) is
    begin
      case tx_state.fsm_state is
  
      when idle =&gt;
        if tx_enable = '1' then
          -- start a new bit
          tx_state_next.bits &lt;= tx_data &amp; '0';  -- data &amp; start
          tx_state_next.nbits &lt;= "0000" + 10; -- send 10 bits (includes '1' stop bit)
          tx_state_next.counter &lt;= (others =&gt; '0');
          tx_state_next.fsm_state &lt;= active;
          tx_state_next.ready &lt;= '0';
        else
          -- keep idle
          tx_state_next.bits &lt;= (others =&gt; '1');
          tx_state_next.nbits &lt;= (others =&gt; '0');
          tx_state_next.counter &lt;= (others =&gt; '0');
          tx_state_next.fsm_state &lt;= idle;
          tx_state_next.ready &lt;= '1';
        end if;
  
      when active =&gt;
        tx_state_next &lt;= tx_state;
        if sample = '1' then
          if tx_state.counter = 15 then
            -- send next bit
            if tx_state.nbits = 0 then
              -- turn idle
              tx_state_next.bits &lt;= (others =&gt; '1');
              tx_state_next.nbits &lt;= (others =&gt; '0');
              tx_state_next.counter &lt;= (others =&gt; '0');
              tx_state_next.fsm_state &lt;= idle;
              tx_state_next.ready &lt;= '1';
            else
              tx_state_next.bits &lt;= '1' &amp; tx_state.bits(8 downto 1);
              tx_state_next.nbits &lt;= tx_state.nbits - 1;
            end if;
          end if;
          tx_state_next.counter &lt;= tx_state.counter + 1;
        end if;
  
      end case;
    end process;
  
    -- TX output
    tx_output: process (tx_state) is
    begin
      tx_ready &lt;= tx_state.ready;
      tx &lt;= tx_state.bits(0);
    end process;
  
  end Behavioral;
  </code></pre>
  
  <p>EDIT:  .XCO file code</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.numeric_std.all;
  
  library unisim;
  use unisim.vcomponents.all;
  
  entity DCM_18 is
  port
   (-- Clock in ports
    CLK_IN1           : in     std_logic;
    -- Clock out ports
    CLK_OUT1          : out    std_logic
   );
  end DCM_18;
  
  architecture xilinx of DCM_18 is
    attribute CORE_GENERATION_INFO : string;
    attribute CORE_GENERATION_INFO of xilinx : architecture is "DCM_18,clk_wiz_v3_6,{component_name=DCM_18,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
    -- Input clock buffering / unused connectors
    signal clkin1      : std_logic;
    -- Output clock buffering / unused connectors
    signal clkfbout         : std_logic;
    signal clkfbout_buf     : std_logic;
    signal clkout0          : std_logic;
    signal clkout1_unused   : std_logic;
    signal clkout2_unused   : std_logic;
    signal clkout3_unused   : std_logic;
    signal clkout4_unused   : std_logic;
    signal clkout5_unused   : std_logic;
    -- Unused status signals
    signal locked_unused    : std_logic;
  
  begin
  
  
    -- Input buffering
    --------------------------------------
    clkin1_buf : IBUFG
    port map
     (O =&gt; clkin1,
      I =&gt; CLK_IN1);
  
  
    -- Clocking primitive
    --------------------------------------
    -- Instantiation of the PLL primitive
    --    * Unused inputs are tied off
    --    * Unused outputs are labeled unused
  
    pll_base_inst : PLL_BASE
    generic map
     (BANDWIDTH            =&gt; "OPTIMIZED",
      CLK_FEEDBACK         =&gt; "CLKFBOUT",
      COMPENSATION         =&gt; "SYSTEM_SYNCHRONOUS",
      DIVCLK_DIVIDE        =&gt; 1,
      CLKFBOUT_MULT        =&gt; 14,
      CLKFBOUT_PHASE       =&gt; 0.000,
      CLKOUT0_DIVIDE       =&gt; 38,
      CLKOUT0_PHASE        =&gt; 0.000,
      CLKOUT0_DUTY_CYCLE   =&gt; 0.500,
      CLKIN_PERIOD         =&gt; 20.000,
      REF_JITTER           =&gt; 0.010)
    port map
      -- Output clocks
     (CLKFBOUT            =&gt; clkfbout,
      CLKOUT0             =&gt; clkout0,
      CLKOUT1             =&gt; clkout1_unused,
      CLKOUT2             =&gt; clkout2_unused,
      CLKOUT3             =&gt; clkout3_unused,
      CLKOUT4             =&gt; clkout4_unused,
      CLKOUT5             =&gt; clkout5_unused,
      LOCKED              =&gt; locked_unused,
      RST                 =&gt; '0',
      -- Input clock control
      CLKFBIN             =&gt; clkfbout_buf,
      CLKIN               =&gt; clkin1);
  
    -- Output buffering
    -------------------------------------
    clkf_buf : BUFG
    port map
     (O =&gt; clkfbout_buf,
      I =&gt; clkfbout);
  
  
    clkout1_buf : BUFG
    port map
     (O   =&gt; CLK_OUT1,
      I   =&gt; clkout0);
  
  
  
  end xilinx;
  </code></pre>
  
  <p><strong>EDIT (NEW CLK instantiation): creating a 18.4 MHz CLK from a 50 MHz CLK</strong></p>
  
  <pre><code>-- &lt;-----Cut code below this line and paste into the architecture body----&gt;
  
     -- DCM_CLKGEN: Frequency Aligned Digital Clock Manager
     --             Spartan-6
     -- Xilinx HDL Language Template, version 14.7
  
     DCM_CLKGEN_inst : DCM_CLKGEN
     generic map (
        CLKFXDV_DIVIDE =&gt; 2,       -- CLKFXDV divide value (2, 4, 8, 16, 32)
        CLKFX_DIVIDE =&gt; 38,         -- Divide value - D - (1-256)
        CLKFX_MD_MAX =&gt; 0.0,       -- Specify maximum M/D ratio for timing anlysis
        CLKFX_MULTIPLY =&gt; 14,       -- Multiply value - M - (2-256)
        CLKIN_PERIOD =&gt; 20.0,       -- Input clock period specified in nS
        SPREAD_SPECTRUM =&gt; "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
                                   -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2" 
        STARTUP_WAIT =&gt; FALSE      -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
     )
     port map (
        CLKFX =&gt; new_CLK,         -- 1-bit output: Generated clock output
        CLKFX180 =&gt; OPEN,   -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
        CLKFXDV =&gt; OPEN,     -- 1-bit output: Divided clock output
        LOCKED =&gt; OPEN,       -- 1-bit output: Locked output
        PROGDONE =&gt; OPEN,   -- 1-bit output: Active high output to indicate the successful re-programming
        STATUS =&gt; OPEN,       -- 2-bit output: DCM_CLKGEN status
        CLKIN =&gt; CLK,         -- 1-bit input: Input clock
        FREEZEDCM =&gt; OPEN, -- 1-bit input: Prevents frequency adjustments to input clock
        PROGCLK =&gt; OPEN,     -- 1-bit input: Clock input for M/D reconfiguration
        PROGDATA =&gt; OPEN,   -- 1-bit input: Serial data input for M/D reconfiguration
        PROGEN =&gt; OPEN,       -- 1-bit input: Active high program enable
        RST =&gt; OPEN              -- 1-bit input: Reset input pin
     );
  
     -- End of DCM_CLKGEN_inst instantiation
  </code></pre>
  
  <p><em>Got this error:</em></p>
  
  <blockquote>
    <p>ERROR:Pack:198 - NCD was not produced.  All logic was removed from the
    design.     This is usually due to having no input or output PAD
    connections in the    design and no nets or symbols marked as 'SAVE'. 
    You can either add PADs or    'SAVE' attributes to the design, or run
    'map -u' to disable logic trimming in    the mapper.</p>
  </blockquote>