title: How to fix "Unknown formal identifier" error in VHDL
body: <p>I am facing an error with my VHDL code. I am using ModelSim software for it.</p>
  <p>I am new in it. There are similar questions posted but that were not solve my problem. Actual issue in port map. I assigned a signals for intermediate wires but it is still showing unknown formal identifier. That's why I am here.</p>
  <pre><code>-- Insert library and use clauses
  LIBRARY IEEE;
  USE IEEE.STD_LOGIC_1164.ALL;
  USE IEEE.NUMERIC_STD.ALL;
  
  -- Begin entity declaration for top-level &quot;mult8x8&quot;
  ENTITY mult8x8 IS
  -- Begin port declartion
  PORT (
      -- Declare control inputs &quot;clk&quot;, &quot;start&quot; and &quot;reset_a&quot;
      clk, start, reset_a : IN STD_LOGIC;
      
      -- Declare data inputs &quot;dataa&quot; and &quot;datab&quot;
      dataa, datab : IN UNSIGNED(7 DOWNTO 0);
  
      -- Declare multiplier output &quot;product8x8_out&quot;
      product8x8_out : OUT UNSIGNED(15 DOWNTO 0);
      
      -- Declare seven segment display outputs
      seg_a, seg_b, seg_c, seg_d, seg_e, seg_f, seg_g, done_flag : OUT 
      STD_LOGIC
  );
  
     -- End entity
     END ENTITY mult8x8;
  
     ARCHITECTURE logic OF mult8x8 IS
  
  -- Declare all lower level components
  COMPONENT adder
      PORT (  
          dataa, datab : IN UNSIGNED (15 DOWNTO 0);
          sum : OUT UNSIGNED (15 DOWNTO 0)
            );
  END COMPONENT adder;
  
   ---##################################################  
   -- complete component instantiations
   -- the components were created in the prior labs
   --- ############### ----
  
  COMPONENT mult4x4
      PORT(
          dataa, datab : IN UNSIGNED(3 DOWNTO 0);
          product : OUT UNSIGNED(7 DOWNTO 0)
          );
  END COMPONENT mult4x4;
  
  COMPONENT mux4
      PORT(
          mux_in_a, mux_in_b: IN UNSIGNED(3 DOWNTO 0);
          mux_sel : IN STD_LOGIC;
          mux_out : OUT UNSIGNED(3 DOWNTO 0)
          );
  END COMPONENT mux4;
  
  COMPONENT shifter
          Port ( 
              input: IN UNSIGNED (7 DOWNTO 0);
          shift_cntrl : IN UNSIGNED (1 DOWNTO 0);
          shift_out : OUT UNSIGNED (15 DOWNTO 0)
          );
  END COMPONENT shifter;
  
  COMPONENT counter
      PORT (
          clk, aclr_n : IN STD_LOGIC;
          count_out : OUT UNSIGNED (1 DOWNTO 0)
      );
  END COMPONENT counter;
  
  COMPONENT mult_control
      PORT (
          clk, reset_a, start : IN STD_LOGIC;
          count : IN UNSIGNED (1 DOWNTO 0);
          input_sel, shift_sel : OUT UNSIGNED(1 DOWNTO 0);
          state_out : OUT UNSIGNED(2 DOWNTO 0);
          done, clk_ena, sclr_n : OUT STD_LOGIC
      );
  END COMPONENT mult_control; 
  
  COMPONENT seven_segment_cntrl
      Port ( input : in  UNSIGNED (2 downto 0);
                 seg_a : out  STD_LOGIC;
                 seg_b : out  STD_LOGIC;
                 seg_c : out  STD_LOGIC;
                 seg_d : out  STD_LOGIC;
                 seg_e : out  STD_LOGIC;
                 seg_f : out  STD_LOGIC;
                 seg_g : out  STD_LOGIC);
  END COMPONENT seven_segment_cntrl;
  
  COMPONENT reg16
      Port(
          clk, clk_ena, sclr_n : IN STD_LOGIC;
          datain: IN UNSIGNED (15 DOWNTO 0);
          reg_out : OUT UNSIGNED (15 DOWNTO 0)
          );
  END COMPONENT  reg16; 
  --- ############### ----
  
  
  -- Declare internal signals to use as wires to connect blocks
  -- used these signals to connect up all the components
  -- you should not need anymore signals
  ---
  SIGNAL aout, bout : UNSIGNED(3 DOWNTO 0);
  SIGNAL product : UNSIGNED(7 DOWNTO 0);
  SIGNAL shift_out, sum, product8x8 : UNSIGNED(15 DOWNTO 0);
  SIGNAL count, shift : UNSIGNED(1 DOWNTO 0);
  SIGNAL state_out : UNSIGNED(2 DOWNTO 0);
  SIGNAL clk_ena, sclr_n, start_n : std_logic;
  SIGNAL sel : UNSIGNED(1 DOWNTO 0);
  
  BEGIN
  -- Start SIGNAL requires inversion before connecting to counter
  start_n &lt;= not(start);
  
  -- Connect blocks per schematic in the lab manual
  -- this port map is completed
  u1: mux4 PORT MAP (mux_in_a =&gt; dataa(3 DOWNTO 0), 
                     mux_in_b =&gt; dataa(7 DOWNTO 4), 
                     mux_sel =&gt; sel(0),
                     mux_out =&gt; aout(3 DOWNTO 0));
  
                     
  u2: mux4 PORT MAP (mux_in_a =&gt; dataa(3 DOWNTO 0), 
                     mux_in_b =&gt; dataa(7 DOWNTO 4), 
                     mux_sel =&gt; sel(0),
                     mux_out =&gt; aout(3 DOWNTO 0));
  
  u3: mult4x4 PORT MAP (aout =&gt; dataa (3 DOWNTO 0),
                bout =&gt; datab (3 DOWNTO 0),
                     product =&gt; product(7 DOWNTO 0));
  
  u4: shifter PORT MAP (product =&gt; input (7 DOWNTO 0),
                  shift =&gt; shift_cntrl (1 DOWNTO 0),
                  shift_out =&gt; shift_out (15 DOWNTO 0));
  
  u5: counter PORT MAP (clk =&gt; clk, 
                start =&gt; aclr_n,
                  count =&gt; count_out (1 DOWNTO 0));
  
  u6: mult_control PORT MAP (clk =&gt; clk, 
                 reset_a =&gt; reset_a, 
                 start =&gt; start,
                 count =&gt; count (1 DOWNTO 0),
                  sel =&gt; input_sel (1 DOWNTO 0), 
                  shift =&gt; shift_sel (1 DOWNTO 0),
                  state_out =&gt; state_out (2 DOWNTO 0),
                  done =&gt; done, 
                  clk_ena =&gt; clk_ena, 
                  sclr_n =&gt; sclr_n);
  
  u7: reg16 PORT MAP (clk =&gt; clk, 
              clk_era =&gt; clk_ena, 
              sclr_n =&gt; sclr_n,
              sum =&gt; datain (15 DOWNTO 0),
                  product8x8 =&gt; reg_out (15 DOWNTO 0));
  
  
  u8: adder PORT MAP (shift_out =&gt; dataa (15 DOWNTO 0), 
              product8x8 =&gt; datab (15 DOWNTO 0),
                  sum =&gt; sum (15 DOWNTO 0));
  
  
  
  u9: seven_segment_cntrl PORT MAP (state_out =&gt; input (2 downto 0),
                      seg_a =&gt; seg_a,
                      seg_b =&gt; seg_b,
                      seg_c =&gt; seg_c,
                      seg_d =&gt; seg_d,
                      seg_e =&gt; seg_e,
                      seg_f =&gt; seg_f,
                      seg_g =&gt; seg_g);
  
  
              
  product8x8_out &lt;= product8x8;
  
  -- End architecture
  END ARCHITECTURE logic;
  </code></pre>
  <p>When I compliled it, it is showing these errors.</p>
  <blockquote>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(151): (vcom-1484) Unknown formal identifier &quot;aout&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(152): (vcom-1484) Unknown formal identifier &quot;bout&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(155): (vcom-1136) Unknown identifier &quot;input&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(156): (vcom-1136) Unknown identifier &quot;shift_cntrl&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(155): (vcom-1484) Unknown formal identifier &quot;product&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(156): (vcom-1484) Unknown formal identifier &quot;shift&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160): (vcom-1136) Unknown identifier &quot;aclr_n&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(161): (vcom-1136) Unknown identifier &quot;count_out&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160): (vcom-1484) Unknown formal identifier &quot;start&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(161): (vcom-1484) Unknown formal identifier &quot;count&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(167): (vcom-1136) Unknown identifier &quot;input_sel&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(168): (vcom-1136) Unknown identifier &quot;shift_sel&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(170): (vcom-1136) Unknown identifier &quot;done&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(167): (vcom-1484) Unknown formal identifier &quot;sel&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(168): (vcom-1484) Unknown formal identifier &quot;shift&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(177): (vcom-1136) Unknown identifier &quot;datain&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(178): (vcom-1136) Unknown identifier &quot;reg_out&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(175): (vcom-1484) Unknown formal identifier &quot;clk_era&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(177): (vcom-1484) Unknown formal identifier &quot;sum&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(178): (vcom-1484) Unknown formal identifier &quot;product8x8&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(181): (vcom-1484) Unknown formal identifier &quot;shift_out&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(182): (vcom-1484) Unknown formal identifier &quot;product8x8&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(187): (vcom-1136) Unknown identifier &quot;input&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(187): (vcom-1484) Unknown formal identifier &quot;state_out&quot;.</p>
  <p>** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(201): VHDL Compiler exiting</p>
  </blockquote>
  <p>Kindly help me to resolve the errors. I will be very thankful to you and it will be really appreciable for me.</p>