title: Avoid duplicating GNU Make rules
body: <p>I've been writing a Makefile that performs some dependency generation and I've found myself having to duplicate rules because the (legacy) codebase contains a mixture of <code>.cpp</code> and <code>.cc</code> files. It seems a bit unsightly. Is there anyway to specify that the prerequisites of a target can be either <code>.cpp</code> or <code>.cc</code> files? </p>
  
  <p>So rather than having:        </p>
  
  <pre><code>%.d : %.cpp
      $(CPP) -MM $(CPPFLAGS) $&lt;
  
  %.d : %.cc
      $(CPP) -MM $(CPPFLAGS) $&lt;
  </code></pre>
  
  <p>Create something without the duplication like:</p>
  
  <pre><code>%.d : %.(cpp | cc)
      $(CPP) -MM $(CPPFLAGS) $&lt;
  </code></pre>
  
  <p>Or is this enforced redundancy just an unfortunate element of GNU Make's design?</p>