title: SystemVerilog ignore unused ports
body: <p>I have a module that is instantiated many times in other modules. Two of the inputs to this module are used very rarely, and to avoid code bloat I don't want to have to connect them in every instantiation. Is there a way to mark these two ports to the compiler to indicate they can be left unconnected?</p>
  
  <p>eg.</p>
  
  <pre><code>module mymod(input logic foo, unused1, unused2, output logic out);
  //...
  endmodule
  
  
  module top(...);
  //...
  mymod(.foo(1'b0));
  endmodule
  </code></pre>
  
  <p>will not compile due to port mismatch errors. How can I change the code so <code>unused1</code> and <code>unused2</code> don't need to be connected?</p>