title: Makefile - compile multiple C file at once
body: <p>This question is different from the one at <a href="https://stackoverflow.com/questions/170467/makefiles-compile-all-c-files-at-once">makefiles - compile all c files at once</a> in the sense that I have one extra requirement: I want to redirect all the object files in a separate directory.</p>
  
  <p>Here is the setup:</p>
  
  <p>I have multiple sources in a directory say <code>src/mylib</code>.<br>
  I want the objects files to end up in <code>build/mylib</code>.<br>
  Please note also that under <code>mylib</code> there are subdirectories.</p>
  
  <p>The first attempt was as follows:</p>
  
  <pre><code>sources = $(shell find src/ -name ".c")
  objects_dirs = $(subst src/, build/, $(dir $(sources)) # This variable is used by the build rule to create directories for objects files prior to compilation
  objects = $(subst src/, build/, $(patsubst %.c, %.o, $(sources))) # This variable has the paths to the objects files that will be generated in the build directory
  
  # This is where things aren't working as expected
  $(objects): build $(sources)
      $(cc) $(cflags) -o $@ $(word 2, $^))
  
  build:
      $(foreach dir, $(objects_dirs), $(shell mkdir -p $(dir)))
  </code></pre>
  
  <p>For the makefile above, only one object file was being generated. I guessed this might have something to do with GCC only being able to generate one object file at a time. Regardless of that, checking the values of <code>$@</code> and <code>$(word 2, $^)</code> in the <code>$(objects)</code> target shows that only one file is being considered even though I have multiple files.</p>
  
  <p>So I changed my makefile to the following:</p>
  
  <pre><code>sources = $(shell find src/ -name ".c")
  objects = $(subst src/, build/, $(patsubst %.c, %.o, $(sources))) # This variable has the paths to the objects files that will be generated in the build directory
  
  # This works as expected but it appears to me like make is generating all the objects files even though source files did not change. This can be seen by checking the timestamps on new object files after running make again.
  $(objects): build $(sources)
      $(foreach source, $(sources), $(shell $(cc) $(cflags) -o $(subst src/,build/, $(patsubst %.o,%.c,$(source))) $(source)))
  
  build:
      $(foreach dir, $(objects_dirs), $(shell mkdir -p $(dir)))
  </code></pre>
  
  <p>The second makefile works as expected but objects files are being rebuilt again which defeats another purpose of using make: only recompile those source files that changed from the last compilation.</p>
  
  <p>Hence my question: how does one generate all object files in a separate directory <em>at once</em> (by this I mean perform the compilation of all sources files in one rule) while making sure that if a source file didn't change the associated object file should not be regenerated.</p>
  
  <p><strong>I am not after speeding up compilation. What I seek is one rule that will generate all objects files such that only updated source files should be recompiled.</strong></p>
  
  <p>The last makefile does the job but there is a recompiling of <strong>all source files</strong> which defeats another purpose of using make: only changed source files should be recompiled.</p>
  
  <h3>EDIT</h3>
  
  <p>After reading comments, it appears I have not phrased my question properly. As the details of what I have are already present, I leave the question as it is with additional details below.</p>
  
  <p>The second makefile in the source code above <strong>does work</strong>. But it does only half the job. The <code>build</code> directory effectively mirrors the <code>src</code> directory.<br>
  So if I have say a file as <code>src/mylib/point/point.c</code>, I get <code>build/mylib/point/point.o</code> generated. This is the first part.<br>
  The second part is that if <code>point.c</code> <strong>does not</strong> changes, <code>point.o</code> in the <code>build/mylib/point/</code> directory must not be regenerated. But after checking timestamps on the object file, I can tell that a new object file replaced the old one after running <code>make</code> again. This is not good because for large projects, compilation time remains <code>O(n)</code> with <code>n</code> being the number of source files to compile.</p>
  
  <p>So this question is about how to preserve the second makefile without <code>make</code> regenerating object files.<br>
  From what I can gather from comments, I am asking too much from <code>make</code>. But if anyone knows how to make this happen, I leave the question open.</p>