en en el fr en en en en it en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en en fr en en en en en en en en en fr en en en en en en en en en en en en en en en fr en en en en en en en en en en ceb en en en en en en en en en en en en en en en en en en en en en fr en en en fr en en en fr en en en en en en en en en en en en en en en en en en
Hiroshi Inoue - Patents and Patent Applications
Thomas J Watson Research Center
Professional Associations:  ACM SIGPLAN  |  Information Processing Society of Japan (IPSJ)
Direct memory access of dynamically allocated memory
Horii, Hiroshi and Inoue, Hiroshi and Ogata, Kazunori
Efficient back-projection operation using precomputed table
A method and system are provided. Te method includes pre-computing, by a computing device having a processor, a plurality of coefficients for a given two-dimensional point on which a voxel of a three-dimensional object is projected, based on integer parts of
Calculation method and apparatus for evaluating response time of computer system in which plurality of units of execution can be run on each processor core
A calculation method for evaluating response time in a computer system in which a plurality of units of execution are run on individual processor cores. Te calculation method evaluates response time in a computer system in which a plurality of units of execution are
Controlling priority of dynamic compilation
Horii, Hiroshi and Inoue, Hiroshi and Onodera, Tamiya
US Patent App. 14/832,726
A method for controlling priority of dynamic compilation by a computer system is disclosed. A task is executed by using a thread pooled in a thread pool. A metric related to te dynamic compilation is monitored. And then, determination is done whether te metric meets a
Sorting an array consisting of a large number of elements
US Patent App. 14/965,190
Sorting an array consisting of large number of elements. Te present invention provides an apparatus for executing a multiway merging process which generates one output sequence from N input sequences on an array consisting of a large number of elements. Te
Reducing overhead in loading constants
US Patent App. 14/446,567
Determining a method to inline using an actual footprint calculation
Hiroshi Inoue, Takuya Nakaike
US Patent App. 14/186,136
Adaptive next-executing-cycle trace selection for trace-driven code optimizers
Jose G Castanos, Hiroshige Hayashizaki, Hiroshi Inoue, Mauricio J Serrano, Peng Wu
Trace generation method, trace generation device, trace generation program product, and multi-level compilation using trace generation method
US Patent App. 14/028,648
Hiroshi Inoue, Hiroshige Hayashizaki, Peng Wu
Optimization apparatus, optimization method and optimization program
US Patent App. 13/886,840
Transaction processing method, program, and system
Hiroshi Horii, Hiroshi Inoue
US Patent App. 14/060,659
Integration of trace selection and trace profiling in dynamic optimizers
Hiroshige Hayashizaki, Hiroshi Inoue, Peng Wu
SIMD merge-sort and duplicate removal operations for data arrays
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
Estimating power consumption of a virtual server
Reduced data transfer during processor context switching
Hiroshi Inoue, Moriyoshi Ohara, Takao Moriyama, Yukihiko Sohda, Hideaki Komatsu
Compression system, program and method
Hiroshi Inoue, Takao Moriyama
Memory management method and system
Multi-core processor for performing matrix operations
Method of memory management for server-side scripting language runtime system
Hiroshi Inoue, Hideaki Komatsu
Instruction execution apparatus, instruction execution method, and instruction execution program
US Patent App. 13/165,850
Merge operations of data arrays based on SIMD instructions
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
Preprocessor to improve te performance of message-passing-based parallel programs on virtualized multi-core processors
Hiroshi Inoue, Hideaki Komatsu, Takao Moriyama, Moriyoshi Ohara, Yukihiko Sohda
Fast implementation of decoding function for variable length encoding
Hiroshi Inoue, Hideaki Komatsu, Moriyoshi Ohara
Delimiter lookup using processor permutation instruction
Hiroshi Inoue, Takao Moriyama, Motohiro Kawahito, Hideaki Komatsu
Method for sorting data using SIMD instructions
Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu
US Patent App. 11/320,095
Java JIT Compiler (at Tokyo)
Systems Research in Tokyo
Knowledge Discovery and Data Mining
Performance Modeling and Analysis
Programming Languages & Software Engineering