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CPRI-SC-U4, Lattice Semiconductor Corporation CPRI-SC-U4 Dáileacháin - Electronics-ic.com
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DEV IP CORE CPRI SC USER CONFIG
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Common Public Radio Interface - CPRI IP Core
SERDES and Physical Coding Sublayer (PCS) functionality integrated in the
layer of the CPRI specification and interleaves IQ data with synchronization,
control and management information. It can be used to connect Radio
Equipment Control (REC) and Radio Equipment (RE) modules.
Supports the physical link layer (Layer 1) of the CPRI
Supports three standard bit rates of the CPRI
Supports 8b/10b encoding/decoding performed in the
Supports code-violation detection performed in the
Performs CPRI Hyperframe Framing
Performs interleaving of IQ data, sync, C&M data,
and vendor specific information
Provides an 8-, 16-, or 32-bit parallel interface for
Supports a slow C&M channel based on a serial
HDLC interface at standard bit rates (240 Kbps, 480
Kbps,960 Kbps, and 1920 Kbps). The HDLC framer,
if needed, must be provided as a separate IP core.
Supports a fast C&M channel based on a serial
Ethernet interface (84.48 Mbps max.) to the user
logic, anon-standard rate MII Ethernet interface to
a MAC, or a 100 Mbps MII interface to a PHY
device. Accepts a user-selected pointer to the CPRI
subchannel where the Ethernet link starts. The
Performs synchronization and timing as defined in
section 4.2.8 of the CPRI Specification
Supports the L1 Inband Protocol
Provides a parallel interface for merging vendor
specific data into the CPRI frame
Provides a start-up sequence state machine in
hardware for both REC and RE nodes which performs:
Synchronization and Rate Negotiation
Performs Link Maintenance as defined in section 4.2.10
of the CPRI Specification:
Optional top-level template that implements user
registers for control and status management
Optional 8-bit register interface through the JTAG port
e 1 of 3CPRI
CPRI-SC-U4 Achoimre na n-ábhar
Home > Products > Intellectual Proper ty > Lattice IP Cores > CPRI Common Public Radio Interface - CPRI IP Core Overview The Lattice Common Public Radio Interface (CPRI) IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeECP3 , LatticeECP2M , LatticeSC/M FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be us ed to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules . Features Supports the physical link layer (L
Ethernet MAC function isprovided as a separate IP core. Low Latency option for LatticeECP2M/S, LatticeECP3 The low latency CPRI core configuration supports all of the features specified for the basic core configuration with the following key exceptions/modifications: Supports the LatticeECP2M/S and LatticeECP3 FPGAs only Supports 1228.8 Mbps, 2457.6 Mbps an d 3072.0 Mbps line bit rates only FPGA bridge FIFOs in the SERDES/PCS block are bypassed in both the receive and transmit direc tions Logic blocks supporting receive direction 10b word alignment, 10b/8b decoding and core-violation detectio
Watch the LatticeECP3 CPRI Video Configuration SLICEs LUTs Registers sysMEM EBRs Matched Low Latency 1743 2432 157 6 2 Fixed Low Latency 1809 2574 1630 6 1. Performance and utilization data are generated targeting an LFE2M35E-5F672C device using Lattice D iamond 1.0 and Synplify Pr o for Lattice D-2009.12L-1 software. Performance m ay vary when usin g a different software version or targeting a different device density or speed grade within the LatticeECP2M/S family. Configuration SLICEs LUTs Registers sysMEM EBRs Serial Basic 913 1270 1123 2 Matched Basic 1267 1646 1267 2 Fixed Basic 1321 17
páirteanna gaolmhara do CPRI-SC-U4
DEV IP CORE CPRI SC USER CONFIG
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DS-5 PROFESSIONAL EDITION FL 1YR
SUITE DGTL VID BROADCASTING ECP3
LIBRARY SW SPCH ENCOD/DECOD 5K
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DEV IP CORE CPRI ECP3 USER CONF
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eochairfhocail a bhaineann le CPRI-SC-U4
Lattice Semiconductor Corporation CPRI-SC-U4
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