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VN380SP13TR, STMicroelectronics VN380SP13TR Dáileacháin - Electronics-ic.com
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IC SSR SMART SOLENOID POWERSO10
Request Price & Lead Time
PMIC - MOSFET, Bridge Drivers - Internal Switch
Atá ann faoi láthair - Aschur / Channel
Atá ann faoi láthair - Aschur Buaic
6 V ~ 24 V
PowerSO-10 Exposed Bottom Pad
Tape & Reel (TR)
VN380SP13TR Achoimre na n-ábhar
www.ti.com HFCLK and 32K synchronizing problem causes clock-gating error I 2 C data hold time in HS mode is higher than the specification when reading I 2 C registers. This leads to a data setup issue, which introduces a frequency limitation in HS mode (cannot reach 3.4 MHz as specified in I 2 C standard). The limitation is for the control I 2 C. The limitation is also for SmartReflex I 2 C only when used with products other than OMAP35xx with SmartReflex. HS mode works correctly for SmartReflex I 2 C when using OMAP35xx. System Clock for TWL5031 SR I 2 C Using OMAP35xx Control I 2 C 19.2 MHz
VIO efficiency loss when VBAT is less than 3.0V and the DCDC is in PFM mode www.ti.com Description: VDD1 and/or VDD2 clock system may hang during switching the clock source from internal oscillator to external. In such situation, DCDC outputs collapse. The feature is enabled by asserting bit EXT_FS_CLK_EN of registers VIO_OSC, VDD1_OSC and VDD2_OSC to ‘1’. Workaround: Fixed in ES1.2 (TPS65950A2, TPS65950A3, TPS65920A2, TPS65930A2) 28 VIO efficiency loss when VBAT is less than 3.0V and the DCDC is in PFM mode Impact: VIO power consumption slightly increases, versus the expected value, when
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Cuardaigh Chuid Uimhir dhíth ort anseo:
Iontráil cuid uimhir iomlán nó páirteach monaróir le ar a laghad de 3 litreacha nó uimhreacha
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