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fixed_point_adder | Implement a module of a parameterized fixed-point adder for arithmetic operations with fixed precision.
Module name:
fixed_point_adder
Input parameters:
Q: Number of fractional bits (precision). Default to 15.
N: Total number of bits, including integer and fractional parts. Default to 32.
Input ports:
a [N-1:0]: First N-bit fixed-point input operand.
b [N-1:0]: Second N-bit fixed-point input operand.
Output ports:
c [N-1:0]: N-bit output representing the result of the fixed-point addition.
Internal Registers:
res [N-1:0]: N-bit register used to store the result of the addition or subtraction.
Implementation:
1. Absolute Value Addition:
- If the most significant bits (MSBs) of `a` and `b` are the same (both positive or both negative), their absolute values are added.
- The MSB of the result is set to match the MSBs of `a` and `b` (sign bit remains consistent).
2. Absolute Value Subtraction:
- If the MSBs of `a` and `b` are different (one is positive, the other negative), the larger absolute value is determined.
- If `a` is greater than `b`, the result is `a - b` and the MSB of the result is set to 0 (positive).
- If `b` is greater than `a`, the result is `b - a`. The MSB of the result is set according to whether the result is zero or negative.
3. Precision:
- The operands `a` and `b` consist of integer and fractional parts, with the fractional part determined by parameter `Q`.
- The precision is consistent across both inputs and the output to ensure accurate fixed-point arithmetic.
4. Overflow Handling:
- Overflow is managed internally by observing the MSB to ensure the result fits within the N-bit range.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n // Parameters\n parameter Q = 15;\n parameter N = 32;\n\n // Inputs\n reg [N-1:0] a;\n reg [N-1:0] b;\n\n // Output\n wire [N-1:0] c;\n reg [N-1:0] expected_result;\n integer error = 0;\n\n fixed_point_adder #(.Q(Q), .N(N)) fp_adder (\n .a(a),\n .b(b),\n .c(c)\n );\n\n initial begin \n for (integer i = 0; i < 100; i = i + 1) begin\n a = $random % (1 << N);\n b = $random % (1 << N);\n\n #10;\n\n if ((a[N-1] == b[N-1]) || (a[N-1] == 0 && b[N-1] == 1 && a[N-2:0] >= b[N-2:0]) || (a[N-1] == 1 && b[N-1] == 0 && a[N-2:0] < b[N-2:0])) begin\n expected_result = a + b;\n end\n else if (a[N-1] == 0 && b[N-1] == 1 && a[N-2:0] < b[N-2:0]) begin\n expected_result = b - a;\n end\n else begin\n expected_result = a - b;\n end\n\n if (c !== expected_result) begin\n error = error + 1;\n $display(\"Failed: a = %b, b = %b, c = %b, expected_result = %b\", a, b, c, expected_result);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n // End simulation\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = fixed_point_adder\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module fixed_point_adder #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin
res[N-2:0] = a[N-2:0] + b[N-2:0];
res[N-1] = a[N-1];
end
// one of them is negative...
else if(a[N-1] == 0 && b[N-1] == 1) begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] - b[N-2:0];
res[N-1] = 0;
end
else begin
res[N-2:0] = b[N-2:0] - a[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
end
else begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] - b[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
else begin
res[N-2:0] = b[N-2:0] - a[N-2:0];
res[N-1] = 0;
end
end
end
endmodule |
adder_16bit | Implement a module of a 16-bit full adder in combinational logic.
Module name:
adder_16bit
Input ports:
a[15:0]: 16-bit input operand A.
b[15:0]: 16-bit input operand B.
Cin: Carry-in input.
Output ports:
y[15:0]: 16-bit output representing the sum of A and B.
Co: Carry-out output.
Implementation:
In the adder_16bit module, you need to design a small bit-width adder(8-bit adder), which will be instantiated multiple times.
| [
{
"content": "`timescale 1ns/1ps\n\nmodule add16_tb();\n\n reg [15:0] a;\n reg [15:0] b;\n reg Cin;\n\n wire [15:0] y;\n wire Co;\n\n wire [16:0] tb_sum;\n wire tb_co;\n\n assign tb_sum = a + b;\n assign tb_co = tb_sum[16];\n\n integer i;\n integer error = 0;\n\n initial begin\n for (i = 0; i < 100; i = i + 1) begin\n a = {$random};\n b = {$random};\n Cin = 0;\n\n #10;\n error = (y !== tb_sum[15:0] || Co !== tb_co) ? error + 1 : error;\n end\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d / 100 failures===========\", error);\n $fatal;\n end\n end\n\n adder_16bit uut (\n .a(a),\n .b(b),\n .Cin(Cin),\n\n .y(y),\n .Co(Co)\n );\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = adder_16bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module adder_16bit (
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
wire Co_temp;
add8 add8_inst1 (
.a(a[15:8]),
.b(b[15:8]),
.Cin(Co_temp),
.y(y[15:8]),
.Co(Co)
);
add8 add8_inst2 (
.a(a[7:0]),
.b(b[7:0]),
.Cin(Cin),
.y(y[7:0]),
.Co(Co_temp)
);
endmodule
module add8 (
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
wire Co_temp;
add4 add4_inst1 (
.a(a[7:4]),
.b(b[7:4]),
.Cin(Co_temp),
.y(y[7:4]),
.Co(Co)
);
add4 add4_inst2 (
.a(a[3:0]),
.b(b[3:0]),
.Cin(Cin),
.y(y[3:0]),
.Co(Co_temp)
);
endmodule
module add4 (
input wire [3:0] a,
input wire [3:0] b,
input wire Cin,
output wire [3:0] y,
output wire Co
);
wire Co_temp;
add2 add2_inst1 (
.a(a[3:2]),
.b(b[3:2]),
.Cin(Co_temp),
.y(y[3:2]),
.Co(Co)
);
add2 add2_inst2 (
.a(a[1:0]),
.b(b[1:0]),
.Cin(Cin),
.y(y[1:0]),
.Co(Co_temp)
);
endmodule
module add2 (
input wire [1:0] a,
input wire [1:0] b,
input wire Cin,
output wire [1:0] y,
output wire Co
);
wire Co_temp;
add1 add1_inst1 (
.a(a[1]),
.b(b[1]),
.Cin(Co_temp),
.y(y[1]),
.Co(Co)
);
add1 add1_inst2 (
.a(a[0]),
.b(b[0]),
.Cin(Cin),
.y(y[0]),
.Co(Co_temp)
);
endmodule
module add1 (
input wire a,
input wire b,
input wire Cin,
output wire y,
output wire Co
);
assign y = ((~a) & (~b) & Cin | (~a) & b & (~Cin) | a & (~b) & (~Cin) | (a & b & Cin));
assign Co = ((~a & b & Cin) | (a & ~b & Cin) | (a & b & ~Cin) | (a & b & Cin));
endmodule |
multi_booth_8bit | Implement an 8-bit Radix-4 booth multiplier that performs the multiplication of two 8-bit inputs (a and b) using the Booth algorithm. It utilizes a clock signal (clk), and a reset signal (reset), and provides the product output (p) and a ready signal (rdy). The ready signal (rdy) is set to 1 to indicate the completion of the multiplication process.
Module name:
multi_booth_8bit
Input ports:
clk: Clock signal used for synchronous operation.
reset: Reset signal used to initialize the multiplier module.
a: 8-bit input representing the multiplicand.
b: 8-bit input representing the multiplier.
Output ports:
p: 16-bit output representing the product of the multiplication.
rdy: Ready signal indicating the completion of the multiplication operation.
Implementation:
On the positive edge of the clock signal (clk) or the positive edge of the reset signal (reset), the module performs the multiplication process.
If the reset signal (reset) is high, two 16-bit registers multiplier <= {{8{a[7]}}, a} and multiplicand <= {{8{b[7]}}, b}.
If the reset signal (reset) is low, indicating normal operation, the module checks if the counter (5bit ctr) is less than 16.
If the counter (ctr) is less than 16, the multiplicand register (multiplicand) is left-shifted by 1 to simulate the Booth algorithm's shifting operation.
If the current bit of the multiplier register (multiplier[ctr]) is 1, indicating a positive Booth encoding, the product register (p) accumulates the value of the multiplicand register (multiplicand).
The counter (ctr) is incremented by 1. Once the counter (ctr) reaches 16, indicating the completion of the multiplication process, the ready signal (rdy) is set to 1.
| [
{
"content": "`timescale 1ns/1ns\n`define width 8\n`define TESTFILE \"test_data.dat\"\n\nmodule booth4_mul_tb () ;\n reg signed [`width-1:0] a, b;\n reg clk, reset;\n\n wire signed [2*`width-1:0] p;\n wire rdy;\n\n integer total, err;\n integer i, s, fp, numtests;\n\n wire signed [2*`width-1:0] ans = a*b;\n\n multi_booth_8bit dut( .clk(clk),\n .reset(reset),\n .a(a),\n .b(b),\n .p(p),\n .rdy(rdy));\n\n // Set up 10ns clock\n always #5 clk = ~clk;\n\n task apply_and_check;\n input [`width-1:0] ain;\n input [`width-1:0] bin;\n begin\n // Set the inputs\n a = ain;\n b = bin;\n // Reset the DUT for one clock cycle\n reset = 1;\n @(posedge clk);\n // Remove reset \n #1 reset = 0;\n\n while (rdy == 0) begin\n @(posedge clk); // Wait for one clock cycle\n end\n if (p == ans) begin\n $display($time, \" Passed: %d * %d = %d\", a, b, p);\n end else begin\n $display($time, \" Fail: %d * %d: %d, expect %d\", a, b, p, ans);\n err = err + 1;\n end\n total = total + 1;\n end\n endtask // apply_and_check\n\n initial begin\n clk = 1;\n total = 0;\n err = 0;\n\n // Get all inputs from file: 1st line has number of inputs\n fp = $fopen(`TESTFILE, \"r\");\n s = $fscanf(fp, \"%d\\n\", numtests);\n // Sequences of values pumped through DUT \n for (i=0; i<numtests; i=i+1) begin\n s = $fscanf(fp, \"%d %d\\n\", a, b);\n apply_and_check(a, b);\n end\n if (err > 0) begin\n $display(\"=========== Failed ===========\");\n $fatal;\n end else begin\n $display(\"===========Your Design Passed===========\");\n end\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = multi_booth_8bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
},
{
"content": "10\n5 5\n2 3\n10 1\n10 2\n20 20\n-128 2\n10 -128\n-1 -1\n10 0\n0 2",
"name": "test_data.dat"
}
] | `timescale 1ns / 1ps
module multi_booth_8bit (p, rdy, clk, reset, a, b);
input clk, reset;
input [7:0] a, b;
output [15:0] p;
output rdy;
reg [15:0] p;
reg [15:0] multiplier;
reg [15:0] multiplicand;
reg rdy;
reg [4:0] ctr;
always @(posedge clk or posedge reset) begin
if (reset)
begin
rdy <= 0;
p <= 0;
ctr <= 0;
multiplier <= {{8{a[7]}}, a};
multiplicand <= {{8{b[7]}}, b};
end
else
begin
if(ctr < 16)
begin
multiplicand <= multiplicand << 1;
if (multiplier[ctr] == 1)
begin
p <= p + multiplicand;
end
ctr <= ctr + 1;
end
else
begin
rdy <= 1;
end
end
end //End of always block
endmodule |
sequence_detector | Implement a module of a sequence detector to detect a specific 4-bit binary sequence 1001.
Module name:
sequence_detector
Input ports:
clk: Clock signal to synchronize the detector.
rst_n: Reset signal to initialize the state machine.
data_in: 1-bit binary input signal to feed the bitstream for sequence detection.
Output ports:
sequence_detected: 1-bit output signal that is set high when the specific sequence is detected.
Internal logic:
State Machine: The sequence detector uses a finite state machine (FSM) with the following states:
IDLE: Waiting for the start of the sequence.
S1: The first bit of the desired sequence is detected.
S2: The second bit of the desired sequence is detected.
S3: The third bit of the desired sequence is detected.
S4: The fourth and final bit of the desired sequence is detected, and the output sequence_detected is set high.
Implementation:
-FSM Design: The FSM transitions through states based on the bitstream data_in. On each clock cycle, the detector checks for a match of the specific sequence.
-Sequence Detection: The module checks the input data_in and transitions between states. Once the complete sequence is detected, sequence_detected is asserted.
-Reset Behavior: When reset is high, the state machine returns to the IDLE state, resetting the detection process. | [
{
"content": "`timescale 1ns / 1ps\n\nmodule tb_sequence_detector();\n\n reg clk, rst_n, data_in;\n wire sequence_detected;\n\n sequence_detector dut (\n .clk(clk),\n .rst_n(rst_n),\n .data_in(data_in),\n .sequence_detected(sequence_detected)\n );\n integer error = 0; \n // Clock generation\n always #5 clk = ~clk;\n\n initial begin\n // Initialize signals\n clk = 0;\n rst_n = 0;\n data_in = 1;\n #2 rst_n = 1;\n\n\n // Sending 1001\n #6 data_in = 1;\n #10 data_in = 1;\n #10 data_in = 0;\n #10 data_in = 0;\n #10 data_in = 1;\n #10;data_in = 1; \n if (!sequence_detected) begin\n error = error+1;\n end\n #10;data_in = 1;\n #10 data_in = 0;\n if (sequence_detected) begin\n error = error+1;\n end\n #10 data_in = 0;\n #10 data_in = 1;\n #10;\n if (!sequence_detected) begin\n error = error+1;\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end \n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = sequence_detector\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module sequence_detector(
input clk,
input rst_n,
input data_in,
output sequence_detected
);
parameter IDLE = 5'b00001;
parameter S1 = 5'b00010;
parameter S2 = 5'b00100;
parameter S3 = 5'b01000;
parameter S4 = 5'b10000;
reg [4:0] curr_state;
reg [4:0] next_state;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
curr_state <= IDLE;
end
else begin
curr_state <= next_state;
end
end
always@(*) begin
if(!rst_n) begin
next_state <= IDLE;
end
else begin
case(curr_state)
IDLE :next_state = data_in?S1:IDLE;
S1 :next_state = data_in?S1:S2;
S2 :next_state = data_in?S1:S3;
S3 :next_state = data_in?S4:IDLE;
S4 :next_state = data_in?S1:S2;
default:next_state = IDLE;
endcase
end
end
assign sequence_detected = (curr_state ==S4) ? 1'b1 : 1'b0;
endmodule |
comparator_4bit | Implement a module of a 4-bit comparator with multiple bit-level comparators in combinational logic.
Module name:
comparator_4bit
Input ports:
A [3:0]: First 4-bit input operand (binary number to compare).
B [3:0]: Second 4-bit input operand (binary number to compare).
Output ports:
A_greater: 1-bit output indicating if A is greater than B.
A_equal: 1-bit output indicating if A is equal to B.
A_less: 1-bit output indicating if A is less than B.
Implementation:
Comparison Logic: The module compares the two 4-bit binary numbers A and B using combinational logic.
- A subtraction operation is performed: A - B. The result of this subtraction helps determine whether A is greater than, equal to, or less than B.
- Carry Generation: If a borrow occurs during the subtraction, A is less than B (A_less).
- If no borrow occurs and the result of subtraction is non-zero, A is greater than B (A_greater).
- If A and B are equal, the result of subtraction is zero (A_equal).
Output Encoding: The outputs (A_greater, A_equal, A_less) are mutually exclusive, ensuring only one of the three outputs is high (1) at any given time.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [3:0] A; // Input A (4 bits)\n reg [3:0] B; // Input B (4 bits)\n wire A_greater; \n wire A_equal; \n wire A_less; \n integer i; \n integer error = 0; \n\n comparator_4bit uut (\n .A(A),\n .B(B),\n .A_greater(A_greater),\n .A_equal(A_equal),\n .A_less(A_less)\n );\n\n\n initial begin\n\n for (i = 0; i < 100; i = i + 1) begin\n // Generate random 4-bit inputs\n A = $random % 16;\n B = $random % 16;\n\n // Wait for the operation to complete\n #10;\n\n // Calculate expected results\n if ((A > B && !A_greater) || (A == B && !A_equal) || (A < B && !A_less)) begin\n error = error + 1;\n $display(\"Failed: A = %b, B = %b, A_greater = %b, A_equal = %b, A_less = %b\",\n A, B, A_greater, A_equal, A_less);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = comparator_4bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module comparator_4bit(
input [3:0] A, // First 4-bit input operand
input [3:0] B, // Second 4-bit input operand
output A_greater,
output A_equal,
output A_less
);
wire [3:0] diff;
wire cout;
assign {cout, diff} = A - B;
// A > B: if there's no borrow and the difference isn't zero
assign A_greater = (~cout && diff != 4'b0000);
assign A_equal = (A == B);
assign A_less = cout;
endmodule
|
width_8to16 | Implement a data width conversion circuit that converts 8-bit data input to 16-bit data output. The module provides two output ports: valid_out, which indicates the validity of the output data, and data_out, which represents the converted 16-bit output data. The first arriving 8-bit data should be placed in the higher 8 bits of the 16-bit data output. The valid_out and data_out signals are generated in the next clock cycle after the two data inputs. When there is only one data input, valid_out and data_out are not generated immediately. Instead, they wait for the arrival of the next data input to complete the concatenation of the two data inputs before generating valid_out and data_out.
Module name:
width_8to16
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
valid_in: Input signal indicating the validity of the input data.
data_in: 8-bit input data to be converted.
Output ports:
valid_out: Output signal indicating the validity of the output data.
data_out: 16-bit output data resulting from the width conversion.
Implementation:
The data_out register is triggered on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, the data_out register is cleared to 0.
If the input data is valid (valid_in) and the flag signal is active, the data_out register is updated by concatenating the contents of the data_lock register (8 bits) and the data_in register (8 bits) to form a 16-bit output. The first valid data is temporarily stored, and when the second valid data is inputted, they are concatenated to produce the output valid_out and data_out.
| [
{
"content": "`timescale 1ns/1ns\nmodule testbench();\n reg rst,valid_in;\n reg clk=1;\n reg[7:0] data_in;\n wire valid_out;\n wire [15:0] data_out;\n\nwidth_8to16 dut(\n .clk (clk),\n .rst_n(rst),\n .valid_in(valid_in),\n .data_in(data_in),\n .valid_out(valid_out),\n .data_out(data_out)\n);\n always #5 clk = ~clk;\n\ninteger error = 0;\ninitial \nbegin\n rst=0; valid_in=0;\n #10 rst=1; valid_in=1; data_in=8'b10100000;\n error = valid_out ==0 ? error : error+1; \n if (valid_out != 0) begin\n $display(\"Failed testcase: valid_in = 1, data_in = 8'b10100000 at time = %d\", $time);\n end\n #10 data_in=8'b10100001; \n $display(\"data_in = 8'b10100001 at time = %d\", $time);\n #10 data_in=8'b10110000;\n error = (data_out == 16'b1010000010100001 && valid_out ==1 )? error : error+1;\n if (data_out != 16'b1010000010100001 || valid_out != 1) begin\n $display(\"Failed testcase: valid_in = 1, data_in = 8'b10110000 at time = %d\", $time);\n end\n #10 valid_in=0;\n $display(\"valid_in = 0 at time = %d\", $time);\n #20 valid_in=1;data_in=8'b10110001; \n $display(\"valid_in = 1, data_in = 8'b10110001 at time = %d\", $time);\n #10 valid_in=0;\n error = (data_out == 16'b1011000010110001 && valid_out ==1 )? error : error+1;\n if (data_out != 16'b1011000010110001 || valid_out != 1) begin\n $display(\"Failed testcase: valid_in = 0, data_in = 8'b10110001 at time = %d\", $time);\n end\n #30\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d / 3 failures===========\", error);\n $fatal;\n end\n\n $finish;\nend \n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = width_8to16\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module width_8to16(
input clk ,
input rst_n ,
input valid_in ,
input [7:0] data_in ,
output reg valid_out,
output reg [15:0] data_out
);
reg [7:0] data_lock; //data buffer
reg flag ;
//input data buff in data_lock
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_lock <= 'd0;
else if(valid_in && !flag)
data_lock <= data_in;
end
//generate flag
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
flag <= 'd0;
else if(valid_in)
flag <= ~flag;
end
//generate valid_out
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
valid_out <= 'd0;
else if(valid_in && flag)
valid_out <= 1'd1;
else
valid_out <= 'd0;
end
//data stitching
always @(posedge clk or negedge rst_n ) begin
if(!rst_n)
data_out <= 'd0;
else if(valid_in && flag)
data_out <= {data_lock, data_in};
end
endmodule |
edge_detect | Implement a module for edge detection. There is a slowly changing 1-bit signal a. When "a" changes from 0 to 1, the indicating signal rise is 1. When "a" changes from 1 to 0, the falling edge of signal a is shown, the indicating signal down is 1. rise or down will be set to 1 on the next clock when the corresponding edge appears, and then return to 0 until the corresponding edge appears again.
Module name:
edge_detect
Input ports:
clk: Clock signal.
rst_n: Reset signal (active low).
a: Input signal.
Output ports:
rise: Output signal indicating a rising edge.
down: Output signal indicating a falling edge.
Implementation:
The edge_detect module detects rising and falling edges in the input signal a and generates corresponding output signals rise and down. The rising and falling edges are detected on the positive edge of the clock signal clk. If a rising edge is detected, the rise output signal is set to 1. If a falling edge is detected, the down output signal is set to 1. Otherwise, both output signals are set to 0. These output signals are synchronized with the clock and remain set to 1 until the corresponding edge appears again.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n reg clk;\n reg rst_n;\n reg a;\n wire rise;\n wire down;\n\n edge_detect dut (\n .clk(clk),\n .rst_n(rst_n),\n .a(a),\n .rise(rise),\n .down(down)\n );\n\n integer error=0;\n initial begin\n // Initialize inputs\n clk = 0;\n rst_n = 1;\n a = 0;\n\n // Wait for a few clock cycles to ensure the module stabilizes\n #5;\n\n // Test scenario 1: No edge\n a = 0;\n #10;\n a = 0;\n #10;\n error = (rise != 0 && down != 0) ? error+1 : error;\n // Test scenario 2: Rising edge\n a = 0;\n #10;\n a = 1;\n #10;\n a = 1;\n error = (rise != 1 && down != 0) ? error+1 : error;\n // Test scenario 3: Falling edge\n a = 1;\n #10;\n a = 0;\n #10;\n a = 0;\n error = (rise != 0 && down != 1) ? error+1 : error;\n // Test scenario 4: Reset\n rst_n = 0;\n #10;\n rst_n = 1;\n #10;\n error = (rise != 0 && down != 0) ? error+1 : error;\n \n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\", error);\n $fatal;\n end\n\n // Finish simulation\n $finish;\n end\n\n always #5 clk = ~clk;\n \nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = edge_detect\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module edge_detect(
input clk,
input rst_n,
input a,
output reg rise,
output reg down
);
reg a0;
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
rise <= 1'b0;
down <= 1'b0;
end
else begin
if(a & ~a0) begin
rise <= 1;
down <= 0;
end
else if (~a & a0) begin
rise <= 0;
down <= 1;
end else begin
rise <= 0;
down <= 0;
end
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
a0 <= 0;
else
a0 <= a;
end
endmodule
|
ROM | A Read-Only Memory (ROM) module designed for storing fixed data. This module provides a way to access predefined data based on an 8-bit address input.
Module name:
ROM
Input ports:
addr [7:0]: 8-bit address input used to select the data location in memory.
Output ports:
dout [15:0]: 16-bit output that delivers the data stored in the ROM at the specified address.
Memory Array:
reg [15:0] mem [0:255]: Defines a ROM with 256 locations, each 16 bits wide.
Initial Block:
The initial block is used to pre-load the ROM with fixed data. In this example, memory locations 0 through 3 are initialized with specific values (16'hA0A0, 16'hB1B1, 16'hC2C2, 16'hD3D3). Other locations can be initialized as needed.
Behavior:
The always @(*) block continuously outputs the data stored in the ROM at the memory location specified by addr.
Since ROM is read-only, this module includes only read operations.
Give me the complete code. | [
{
"content": "module rom_tb;\n\n reg [7:0] addr_tb; // Address input for the ROM\n wire [15:0] dout_tb; // Data output from the ROM\n\n ROM rom_inst (\n .addr(addr_tb),\n .dout(dout_tb)\n );\n\n integer error;\n\n initial begin\n // Initialize simulation\n $display(\"Starting ROM Testbench...\");\n error = 0;\n\n // Test reading data from different memory locations\n addr_tb = 8'h00; // Read from address 0\n #10;\n if (dout_tb !== 16'hA0A0) begin\n $display(\"Error: Data read from address 0 is incorrect\");\n error = error + 1;\n end\n\n addr_tb = 8'h01; // Read from address 1\n #10;\n if (dout_tb !== 16'hB1B1) begin\n $display(\"Error: Data read from address 1 is incorrect\");\n error = error + 1;\n end\n\n addr_tb = 8'h02; // Read from address 2\n #10;\n if (dout_tb !== 16'hC2C2) begin\n $display(\"Error: Data read from address 2 is incorrect\");\n error = error + 1;\n end\n\n addr_tb = 8'h03; // Read from address 3\n #10;\n if (dout_tb !== 16'hD3D3) begin\n $display(\"Error: Data read from address 3 is incorrect\");\n error = error + 1;\n end\n\n // Add more test cases here if needed\n\n // Check for errors\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end else begin\n $display(\"Test completed with %d errors.\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = ROM\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module ROM (
input wire [7:0] addr, // 8-bit Address input
output reg [15:0] dout // 16-bit Data output
);
// Declare a memory array of 256 locations, each 16 bits wide, initialized with fixed data
reg [15:0] mem [0:255];
// Initial block to initialize the ROM with data
initial begin
mem[0] = 16'hA0A0;
mem[1] = 16'hB1B1;
mem[2] = 16'hC2C2;
mem[3] = 16'hD3D3;
// Initialize other memory locations as needed
end
// Combinational logic: Read data from the ROM at the specified address
always @(*) begin
dout = mem[addr];
end
endmodule |
JC_counter | Implement a 64-bit Johnson counter (torsional ring counter), and the state of the similar 4-bit Johnson counter example is as follows: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000.
Module name:
JC_counter
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal to initialize the counter.
Output port:
Q: 64-bit register representing the current count value.
Implementation:
On every rising edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the counter value is updated.
If the reset signal (rst_n) is low, indicating a reset condition, the counter value (Q) is set to 0.
Otherwise, if the least significant bit (Q[0]) is 0, the counter increments by shifting the current value (Q[63:1]) to the right and appending a 1 at the most significant bit position.
If the least significant bit (Q[0]) is 1, the counter decrements by shifting the current value (Q[63:1]) to the right and appending a 0 at the most significant bit position.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n\n // Parameters\n parameter CLK_PERIOD = 10; // Clock period in simulation time units\n \n // Inputs\n reg clk;\n reg rst_n;\n \n // Outputs\n wire [63:0] Q;\n\n // Instantiate the module\n JC_counter uut (\n .clk(clk),\n .rst_n(rst_n),\n .Q(Q)\n );\n \n // Clock generation\n always #((CLK_PERIOD)/2) clk = ~clk;\n \n integer error=0;\n // Initial block for stimulus generation\n initial begin\n // Initialize inputs\n clk = 0;\n rst_n = 1;\n \n // Wait for a few clock cycles\n #((CLK_PERIOD) * 2);\n \n // Release reset\n rst_n = 0;\n #((CLK_PERIOD) * 2);\n rst_n = 1;\n \n // Simulate for a number of clock cycles\n #((CLK_PERIOD) * 20);\n error = (Q ==64'b 1111111111111111111100000000000000000000000000000000000000000000)? error : error+1;\n #((CLK_PERIOD) * 44);\n error = (Q ==64'b 1111111111111111111111111111111111111111111111111111111111111111)? error : error+1;\n #((CLK_PERIOD) * 1);\n error = (Q ==64'b 0111111111111111111111111111111111111111111111111111111111111111)? error : error+1;\n #((CLK_PERIOD) * 62);\n error = (Q ==64'b 0000000000000000000000000000000000000000000000000000000000000001)? error : error+1;\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n $display(\"Q = %b\", Q); \n \n // Finish simulation\n $finish;\n end\n\nendmodule\n\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = JC_counter\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module JC_counter(
input clk ,
input rst_n,
output reg [63:0] Q
);
always@(posedge clk or negedge rst_n)begin
if(!rst_n) Q <= 'd0;
else if(!Q[0]) Q <= {1'b1, Q[63 : 1]};
else Q <= {1'b0, Q[63 : 1]};
end
endmodule
|
pulse_detect | Implement a module for pulse detection. The 1-bit input signal data_in is a continuous input, which is triggered by clk. When "data_in" changes from 0 to 1 to 0(3 cycles), this is considered as a "pulse". The indicating signal dataout is 1 at the end cycle of the "pulse", and then returns to 0 until the corresponding pulse appears again. For example, if data_in is 01010(5 cycles), the data_out is 00101.
Module name:
pulse_detect
Input ports：
clk: Clock signal.
rst_n: Reset signal (active low).
data_in: One-bit input signal.
Output ports：
data_out: Output signal indicating the presence of pulses.
Implementation:
Declare the module pulse_detect with input and output ports as specified in the ports statement.
Declare a register state to keep track of the current state of the pulse detection process.
Inside an always block, sensitive to the positive edge of the clk signal and the negative edge of the rst_n signal, implement the logic for pulse detection and output generation.
In the reset condition (~rst_n), set the state register to the initial state and set the data_out output to 0, indicating no pulse. Continue the detection process for the remaining states. For each state, check the value of data_in and transition to the next state accordingly. If the current state satisfies the last state of a "pulse", set data_out to 1, indicating the end of a pulse. Otherwise, set data_out to 0.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule pulse_detect_tb;\n reg clk;\n reg rst_n;\n reg data_in;\n wire data_out;\n\n // Instantiate the DUT (Design Under Test)\n pulse_detect dut (\n .clk(clk),\n .rst_n(rst_n),\n .data_in(data_in),\n .data_out(data_out)\n );\n\n // Generate clock\n initial begin\n clk=0;\n forever #5 clk=~clk;\n end\n\n integer error = 0;\n initial begin\n // Initialize inputs\n #10;\n rst_n = 0;\n data_in = 0;\n #28;\n rst_n = 1;\n #10 data_in = 0;\n #10 data_in = 0; \n #10 data_in = 0;\n #10 data_in = 1;\n #10 data_in = 0;\n #10 data_in = 1;\n #10 data_in = 0;\n #10 data_in = 1;\n #10 data_in = 1;\n #10 data_in = 0;\n #10;\n // Finish simulation\n $finish;\n end\n\n initial begin\n #5;\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 0) ? error : error+1;\n if (data_out != 0) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n error = (data_out == 1) ? error : error+1;\n if (data_out != 1) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #20;\n error = (data_out == 1) ? error : error+1;\n if (data_out != 1) begin\n $display(\"Failed testcase: data_in = %b at time = %d\", data_in, $time);\n end\n #10;\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n end\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = pulse_detect\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module pulse_detect(
input clk,
input rst_n,
input data_in,
output reg data_out
);
parameter s0 = 2'b00; // initial
parameter s1 = 2'b01; // 0, 00
parameter s2 = 2'b10; // 01
parameter s3 = 2'b11; // 010
reg [1:0] pulse_level1, pulse_level2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
pulse_level1 <= s0;
else
pulse_level1 <= pulse_level2;
end
always @(*) begin
case (pulse_level1)
s0: begin
if (data_in == 0)
pulse_level2 = s1;
else
pulse_level2 = s0;
end
s1: begin
if (data_in == 1)
pulse_level2 = s2;
else
pulse_level2 = s1;
end
s2: begin
if (data_in == 0)
pulse_level2 = s3;
else
pulse_level2 = s0;
end
s3: begin
if (data_in == 1)
pulse_level2 = s2;
else
pulse_level2 = s1;
end
endcase
end
// always @(posedge clk or negedge rst_n) begin
// if (~rst_n)
// data_out <= 0;
// else if (pulse_level1 == s2 && data_in == 0)
// begin
// data_out <= 1;
// end
// else
// data_out <= 0;
// end
always @(*) begin
if (~rst_n)
data_out = 0;
else if (pulse_level1 == s2 && data_in == 0)
data_out = 1;
else
data_out = 0;
end
endmodule
|
adder_8bit | Implement a module of an 8-bit adder with multiple bit-level adders in combinational logic.
Module name:
adder_8bit
Input ports:
a[7:0]: 8-bit input operand A.
b[7:0]: 8-bit input operand B.
cin: Carry-in input.
Output ports:
sum[7:0]: 8-bit output representing the sum of A and B.
cout: Carry-out output.
Implementation:
The module utilizes a series of bit-level adders (full adders) to perform the addition operation.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n \n reg [7:0] a;\n reg [7:0] b;\n reg cin;\n wire [7:0] sum;\n wire cout;\n \n integer i; // Declare the loop variable here\n integer fail_count;\n integer error = 0;\n \n // Instantiate the module\n adder_8bit uut (\n .a(a), \n .b(b), \n .cin(cin), \n .sum(sum), \n .cout(cout)\n );\n \n // Randomize inputs and check output\n initial begin\n for (i = 0; i < 100; i = i + 1) begin\n a = $random & 8'hff;\n b = $random & 8'hff;\n cin = $random & 1'b1;\n #10;\n error = (sum !== a + b + cin) ? error+1 : error; \n if (sum !== a + b + cin) begin\n $display(\"Error: a=%d, b=%d, cin=%d, sum=%d, expected=%d\", a, b, cin, sum, a + b + cin);\n end\n end\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /100 failures===========\", error);\n $fatal;\n end\n\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = adder_8bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module adder_8bit(
input [7:0] a, b,
input cin,
output [7:0] sum,
output cout);
wire [8:0] c;
full_adder FA0 (.a(a[0]), .b(b[0]), .cin(cin), .sum(sum[0]), .cout(c[0]));
full_adder FA1 (.a(a[1]), .b(b[1]), .cin(c[0]), .sum(sum[1]), .cout(c[1]));
full_adder FA2 (.a(a[2]), .b(b[2]), .cin(c[1]), .sum(sum[2]), .cout(c[2]));
full_adder FA3 (.a(a[3]), .b(b[3]), .cin(c[2]), .sum(sum[3]), .cout(c[3]));
full_adder FA4 (.a(a[4]), .b(b[4]), .cin(c[3]), .sum(sum[4]), .cout(c[4]));
full_adder FA5 (.a(a[5]), .b(b[5]), .cin(c[4]), .sum(sum[5]), .cout(c[5]));
full_adder FA6 (.a(a[6]), .b(b[6]), .cin(c[5]), .sum(sum[6]), .cout(c[6]));
full_adder FA7 (.a(a[7]), .b(b[7]), .cin(c[6]), .sum(sum[7]), .cout(c[7]));
assign cout = c[7];
endmodule
module full_adder (input a, b, cin, output sum, cout);
assign {cout, sum} = a + b + cin;
endmodule |
traffic_light | Implement a traffic light, with red, yellow and green three small indicators and a pedestrian button, under normal circumstances, the motor vehicle lane indicator light according to 60 clock cycles of green, 5 clock cycles of yellow, 10 clock cycles of red. When the pedestrian button is pressed, if the remaining green time is greater than 10 clocks, it is shortened to 10 clocks, and if it is less than 10 clocks, it remains unchanged. The lane light and the sidewalk light should be paired, when the lane light is green or yellow, the sidewalk light is red; When the lane light is red, the sidewalk light is green, and for the sake of simplicity, only the lane light is considered.
Module name:
traffic_light
Inputs:
rst_n: Reset signal (active low).
clk: Clock signal.
pass_request: Request signal for allowing vehicles to pass.
Outputs:
clock[7:0]: An 8-bit output representing the count value of the internal counter.
red, yellow, green: Output signals representing the state of the traffic lights.
Parameters:
idle, s1_red, s2_yellow, s3_green: Enumeration values representing different states of the traffic light controller.
Registers and Wires:
cnt: A 8-bit register used as an internal counter for timing purposes.
state: A 2-bit register representing the current state of the traffic light controller.
p_red, p_yellow, p_green: 1-bit registers representing the next values for the red, yellow, and green signals.
Implementation:
The following is the design track we recommend:
The first always block is responsible for the state transition logic. It uses a case statement to handle different states. Here's a summary of each state:
idle: Initial state where all signals are set to 0. Transition to s1_red state occurs immediately.
s1_red: Sets the red signal to 1 and waits for a count of 3 before transitioning to s3_green state. Otherwise, it remains in s1_red state.
s2_yellow: Sets the yellow signal to 1 and waits for a count of 3 before transitioning to s1_red state. Otherwise, it remains in s2_yellow state.
s3_green: Sets the green signal to 1 and waits for a count of 3 before transitioning to s2_yellow state. Otherwise, it remains in s3_green state.
The second always block handles the counting logic of the internal counter (cnt). The counter is decremented by 1 on every positive edge of the clock or negative edge of the reset signal. The counter values are adjusted based on various conditions:
If (!rst_n), the counter is set to 10.
If the pass_request signal is active and the green signal is active, the counter is set to 10.
If the green signal is inactive and the previous green signal (p_green) was active, the counter is set to 60.
If the yellow signal is inactive and the previous yellow signal (p_yellow) was active, the counter is set to 5.
If the red signal is inactive and the previous red signal (p_red) was active, the counter is set to 10.
Otherwise, the counter is decremented normally.
The assign statement assigns the value of the internal counter (cnt) to the output clock.
The final always block handles the output signals. It assigns the previous values (p_red, p_yellow, p_green) to the output signals (red, yellow, green) on the positive edge of the clock or negative edge of the reset signal.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule tb_traffic_light;\n \n reg clk;\n reg rst_n;\n reg pass_request;\n wire [7:0] clock;\n wire red;\n wire yellow;\n wire green;\n integer i;\n // Instantiate the module\n traffic_light uut (\n .clk(clk), \n .rst_n(rst_n),\n .pass_request(pass_request), \n .clock(clock), \n .red(red),\n .yellow(yellow),\n .green(green)\n );\n \n // Clock generation\n always begin\n #5 clk = ~clk;\n end\n\n integer error = 0;\n integer clock_cnt;\n // Test sequence\n initial begin\n clk = 0; // Initialize clock\n rst_n = 1; // De-assert reset\n pass_request = 0; // No pass request initially\n\n // Perform reset\n rst_n = 0;\n #10;\n rst_n = 1;\n #30;\n \n // test red\n error = (red==1)&&(yellow==0)&&(green==0) ?error :error+1;\n if (red != 1 || yellow != 0 || green != 0) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n #100;\n // test green\n error = (red==0)&&(yellow==0)&&(green==1) ?error :error+1;\n if (red != 0 || yellow != 0 || green != 1) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n #600;\n // test yellow\n error = (red==0)&&(yellow==1)&&(green==0) ?error :error+1;\n if (red != 0 || yellow != 1 || green != 0) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n #150;\n clock_cnt = clock;\n $display(\"clock_cnt = %d at time = %d\", clock_cnt, $time);\n // test pass_request\n #30;\n error = (clock!=(clock_cnt+3)) ?error :error+1;\n if (clock == (clock_cnt+3)) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n pass_request = 1;\n $display(\"pass_request = %d at time = %d\", pass_request, $time);\n #10;\n error = (clock==10)&&(green==1) ?error :error+1;\n if (clock != 10 || green != 1) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Failed===========\", error);\n $fatal;\n end\n\n $finish; // End of test\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = traffic_light\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module traffic_light
(
input rst_n,
input clk,
input pass_request,
output wire[7:0]clock,
output reg red,
output reg yellow,
output reg green
);
parameter idle = 2'd0,
s1_red = 2'd1,
s2_yellow = 2'd2,
s3_green = 2'd3;
reg [7:0] cnt;
reg [1:0] state;
reg p_red,p_yellow,p_green;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= idle;
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b0;
end
else case(state)
idle:
begin
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b0;
state <= s1_red;
end
s1_red:
begin
p_red <= 1'b1;
p_green <= 1'b0;
p_yellow <= 1'b0;
if (cnt == 3)
state <= s3_green;
else
state <= s1_red;
end
s2_yellow:
begin
p_red <= 1'b0;
p_green <= 1'b0;
p_yellow <= 1'b1;
if (cnt == 3)
state <= s1_red;
else
state <= s2_yellow;
end
s3_green:
begin
p_red <= 1'b0;
p_green <= 1'b1;
p_yellow <= 1'b0;
if (cnt == 3)
state <= s2_yellow;
else
state <= s3_green;
end
endcase
end
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt <= 7'd10;
else if (pass_request&&green&&(cnt>10))
cnt <= 7'd10;
else if (!green&&p_green)
cnt <= 7'd60;
else if (!yellow&&p_yellow)
cnt <= 7'd5;
else if (!red&&p_red)
cnt <= 7'd10;
else cnt <= cnt -1;
assign clock = cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
yellow <= 1'd0;
red <= 1'd0;
green <= 1'd0;
end
else
begin
yellow <= p_yellow;
red <= p_red;
green <= p_green;
end
endmodule
|
serial2parallel | Implement a series-parallel conversion circuit. It receives a serial input signal "din_serial" along with a control signal "din_valid" indicating the validity of the input data. The module operates on the rising edge of the clock signal "clk" and uses a synchronous design. The input din_serial is a single-bit data, and when the module receives 8 input data, the output dout_parallel outputs the 8-bit data(The serial input values are sequentially placed in dout_parallel from the most significant bit to the least significant bit), and the dout_valid is set to 1.
Module name:
serial2parallel
Input ports:
clk: Clock signal.
rst_n: Reset signal (active low).
din_serial: Serial input data.
din_valid: Validity signal for input data.
Output ports:
dout_parallel: Parallel output data (8 bits wide).
dout_valid: Validity signal for the output data.
Implementation:
The module utilizes a 4-bit counter (cnt) to keep track of the number of serial input data bits received. Every eight din_serial input, dout_parallel will output. When all 8 serial data bits have been received, the valid output signal is set to 1, indicating that the parallel output data is valid. Otherwise, the valid output signal is set to 0, indicating that the parallel output data is not valid.
| [
{
"content": "module tb();\n reg clk,rst_n;\n reg din_serial,din_valid;\n wire dout_valid;\n wire[7:0]dout_parallel;\n \nalways #5 clk = ~clk;\ninteger error = 0;\ninitial begin\n clk <= 1'b0;\n rst_n <= 1'b0;\n #12\n rst_n <= 1'b1;\n din_valid <= 1'b1;\n\n din_serial <= 1'b1; #10; $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b1; #10; $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b1; #10; $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b1; #10; $display(\"din_serial = 1 at time = %d\", $time);\n error = (dout_valid == 0) ? error : error + 1;\n if (dout_valid != 0) begin\n $display(\"Failed: expect dout_valid = 0, got dout_valid = %b\", dout_valid);\n end\n din_serial <= 1'b0; #10; $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b0; #10; $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b0; #10; $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b0; #10; $display(\"din_serial = 0 at time = %d\", $time);\n while(dout_valid == 0) begin\n #5;\n end\n error = (dout_parallel == 8'b11110000) ? error : error + 1;\n if (dout_parallel != 8'b11110000) begin\n $display(\"Failed: expect dout_parallel = 8'b11110000, got dout_parallel = %b\", dout_parallel);\n end\n\n din_valid <= 1'b0; \n #30;\n din_valid <= 1'b1;\n $display(\"din_valid reset\");\n\n din_serial <= 1'b1; #10 $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b1; #10 $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b0; #10 $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b0; #10 $display(\"din_serial = 0 at time = %d\", $time);\n error = (dout_valid == 0) ? error : error + 1;\n if (dout_valid != 0) begin\n $display(\"Failed: expect dout_valid = 0, got dout_valid = %b\", dout_valid);\n end\n din_serial <= 1'b0; #10 $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b0; #10 $display(\"din_serial = 0 at time = %d\", $time);\n din_serial <= 1'b1; #10 $display(\"din_serial = 1 at time = %d\", $time);\n din_serial <= 1'b1; #20 $display(\"din_serial = 1 at time = %d\", $time);\n din_valid <= 1'b0;\n while(dout_valid == 0) begin\n #5;\n end\n error = (dout_parallel == 8'b11000011) ? error : error + 1;\n if (dout_parallel != 8'b11000011) begin\n $display(\"Failed: expect dout_parallel = 8'b11000011, got dout_parallel = %b\", dout_parallel);\n end\n #10\n error = (dout_valid == 0) ? error : error + 1;\n if (dout_valid != 0) begin\n $display(\"Failed: expect dout_valid = 0, got dout_valid = %b\", dout_valid);\n end\n\n #10\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n\n $finish;\nend \n\nserial2parallel u0(\n .clk (clk) ,\n .rst_n (rst_n) ,\n .din_serial (din_serial) ,\n .dout_parallel (dout_parallel) ,\n .din_valid (din_valid) ,\n .dout_valid (dout_valid)\n); \nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\nTEST_DESIGN = serial2parallel\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] |
module serial2parallel(
input clk,
input rst_n,
input din_serial,
input din_valid,
output reg [7:0]dout_parallel,
output reg dout_valid
);
reg[7:0]din_tmp;
reg[3:0]cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 0;
else if(din_valid)
cnt <= (cnt == 4'd8)?0:cnt+1'b1;
else
cnt <= 0;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
din_tmp <= 8'b0;
else if(din_valid && cnt <= 4'd7)
din_tmp <= {din_tmp[6:0],din_serial};
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dout_valid <= 1'b0;
dout_parallel <= 8'b0;
end
else if(cnt == 4'd8)begin
dout_valid <= 1'b1;
dout_parallel <= din_tmp;
end
else begin
dout_valid <= 1'b0;
end
end
endmodule
|
asyn_fifo | Implement an asynchronous FIFO, FIFO bit width and depth can be configured(parameter DEPTH = 16, parameter WIDTH = 8). The asynchronous FIFO structure is divided into several parts. The first part is dual-port RAM, which is used for data storage. Instantiate dual-port RAM as a submodule, The RAM ports are input wclk, input wenc, input [$clog2(DEPTH)-1:0] waddr, input [WIDTH-1:0] wdata, input rclk, input renc, input [$clog2(DEPTH)-1:0] raddr, output reg [WIDTH-1:0] rdata. The second part is the data write controller. The third part is the data read controller. The fourth part is the read pointer synchronizer. The read pointer is collected using the two-stage trigger of the write clock and output to the data write controller. The fifth part is the write pointer synchronizer, which uses the two-stage trigger of the read clock to collect the write pointer and output it to the data read controller.
The method of empty and full judgment is to generate empty and full signals by comparing the Gray code. Use 4-bit Gray code as a read/write pointer for a FIFO with depth 8. The gray code is converted to a four-digit binary number, using the lower three digits of the binary number as the address to access RAM. When the read and write Pointers are equal, the FIFO is null.
When the write pointer has one more cycle RAM than the read pointer, the highest and second-highest bits of the read and write pointer are opposite, the remaining bits are the same, and the FIFO is full.
Module name:
asyn_fifo
Input ports:
wclk: Write clock signal used for synchronous write operations.
rclk: Read clock signal used for synchronous read operations.
wrstn: Write reset signal. Defined as 0 for reset and 1 for reset signal inactive.
rrstn: Read reset signal. Defined as 0 for reset and 1 for reset signal inactive.
winc: Write increment signal. Used to trigger write operations.
rinc: Read increment signal. Used to trigger read operations.
wdata: Write data input. The width [WIDTH-1:0] is configurable and represents the data to be written into the FIFO.
Output ports:
wfull: Write full signal. Indicates if the FIFO is full and cannot accept further write operations.
rempty: Read empty signal. Indicates if the FIFO is empty and cannot provide any data for read operations.
rdata: Read data output. The width [WIDTH-1:0] is configurable and represents the data read from the FIFO.
Parameter:
WIDTH = 8
DEPTH = 16
Implementation:
The module implements an asynchronous FIFO using a dual-port RAM module and additional logic for managing read and write pointers.
Dual-port RAM:
The module instantiates a dual-port RAM module named "dual_port_RAM" with configurable depth and width.
The RAM module has separate clock inputs for write (wclk) and read (rclk) operations.
The RAM module has separate address inputs for write (waddr) and read (raddr) operations.
The RAM module has a write enable input (wenc) and a write data input (wdata).
The RAM module has a read enable input (renc) and a read data output (rdata).
The RAM module stores data in a two-dimensional array, RAM_MEM, with a size of DEPTH by WIDTH.
Write and Read Pointers:
The module includes logic to manage write and read pointers for asynchronous operation.
The write and read pointers are represented by binary registers, waddr_bin and raddr_bin, respectively.
The write and read pointers are incremented based on the write and read increment signals (winc and rinc), respectively.
The write pointer is incremented on the positive edge of the write clock (posedge wclk) and reset to 0 on write reset (~wrstn).
The read pointer is incremented on the positive edge of the read clock (posedge rclk) and reset to 0 on read reset (~rrstn).
Gray Code Conversion:
The write and read pointers are converted to Gray code using XOR operations with right-shifted values.
The converted write and read pointers are stored in registers wptr and rptr, respectively.
The Gray code conversion reduces glitches and ensures proper synchronization of the write and read pointers.
Pointer Buffers:
The module includes buffer registers (wptr_buff and rptr_buff) to hold the previous values of the write and read pointers.
The buffer registers are updated on the positive edge of the respective clocks and reset to 0 on the respective resets (~wrstn and ~rrstn).
The buffer registers are used to synchronize the write and read pointers for determining the full and empty conditions.
Full and Empty Signals:
The module compares the current write and read pointers (wptr and rptr_syn) to determine if the FIFO is full or empty.
The wfull output is set to 1 when the write pointer is equal to the bitwise negation of the most significant bit of the read pointer concatenated with the remaining bits of the read pointer.
The rempty output is set to 1 when the read pointer is equal to the write pointer.
Input and Output Connections:
The module connects the input and output signals to the dual-port RAM module based on the control signals and pointer values.
The wen and ren signals control the write and read enable signals of the RAM module, respectively.
The wdata input is connected to the write data input (wdata) of the RAM module.
The rdata output is connected to the read data output (rdata) of the RAM module.
| [
{
"content": "01\n01\nab\nab\nac\nac\nad\nad\nae\nae\naf\naf\nb0\nb0\nb1\nb1\nb2\nb2\nb3\nb3\nb4\nb4\nb5\nb5\nb6\nb6\nb7\nb7\nb8\nb8\nb9\nb9\n01\n01\n01\n01\nab\nab\nac\nac\nad\nad\nae\nae\naf\naf\nb0\nb0\n",
"name": "tdata.txt"
},
{
"content": "0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n",
"name": "rempty.txt"
},
{
"content": "`timescale 1ns/1ns\n\nmodule asyn_fifo_tb;\n\n reg wclk, rclk, wrstn, rrstn, winc, rinc;\n reg [7:0] wdata;\n wire wfull, rempty;\n wire [7:0] rdata;\n \n asyn_fifo #(.WIDTH(8), .DEPTH(16)) dut (\n .wclk(wclk),\n .rclk(rclk),\n .wrstn(wrstn),\n .rrstn(rrstn),\n .winc(winc),\n .rinc(rinc),\n .wdata(wdata),\n .wfull(wfull),\n .rempty(rempty),\n .rdata(rdata)\n );\n \n always #5 wclk = ~wclk;\n always #10 rclk = ~rclk;\n \n initial begin\n wclk = 0;\n rclk = 0;\n wrstn = 0;\n rrstn = 0;\n winc = 0;\n rinc = 0;\n wdata = 0;\n end\n\n // Apply reset and initialize FIFO\n initial begin\n wrstn = 0;\n rrstn = 0;\n #20;\n wrstn = 1;\n rrstn = 1;\n #10;\n winc = 1; // Enable write\n wdata = 8'hAA; // Write data\n #10;\n winc = 0; // Disable write\n #500;\n rinc = 1;\n #500;\n #10;\n $finish;\n end\n integer outfile1;\n integer outfile2;\n integer outfile3;\n reg[31:0]data1[0:50];\n reg[31:0]data2[0:50];\n reg[31:0]data3[0:50];\n integer i = 0;\n integer error =0;\n\n initial begin\n #550;\n $readmemh(\"wfull.txt\",data1);\n $readmemh(\"rempty.txt\",data2);\n $readmemh(\"tdata.txt\",data3);\n // outfile1 = $fopen(\"wfull.txt\", \"w\");\n // outfile2 = $fopen(\"rempty.txt\", \"w\");\n // outfile3 = $fopen(\"tdata.txt\", \"w\");\n repeat(48) begin\n #10;\n // $fwrite(outfile1, \"%h\\n\", wfull);\n // $fwrite(outfile2, \"%h\\n\", rempty);\n // $fwrite(outfile3, \"%h\\n\", rdata);\n error = (wfull==data1[i] && rempty == data2[i] && rdata ==data3[i]) ? error:error+1;\n if (wfull!=data1[i] || rempty != data2[i] || rdata !=data3[i]) begin\n $display(\"Failed: expect wfull=%d, rempty=%d, rdata=%h, got wfull=%d, rempty=%d, rdata=%h\", data1[i], data2[i], data3[i], wfull, rempty, rdata);\n end\n i = i + 1;\n end\n if(error==0)\n begin\n $display(\"===========Your Design Passed===========\");\n end\n else\n begin\n $display(\"===========Error===========\");\n $fatal;\n end\n\n // $fclose(outfile1);\n // $fclose(outfile2);\n // $fclose(outfile3);\n end\n // Display FIFO status\n // always @(posedge wclk) begin\n // $display(\"wfull=%d, rempty=%d, rdata=%h\", wfull, rempty, rdata);\n // end\n\n initial begin\n repeat (17) begin\n #20;\n if (wfull) begin\n $display(\"FIFO is full (wfull=1) at depth %d\", $time);\n break;\n end\n winc = 1; // Enable write\n wdata = wdata + 1; // Write data\n #10;\n winc = 0; // Disable write\n end\n end\n \nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = asyn_fifo\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
},
{
"content": "1\n1\n1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n",
"name": "wfull.txt"
}
] | `timescale 1ns/1ns
/***************************************RAM*****************************************/
module dual_port_RAM #(parameter DEPTH = 16, parameter WIDTH = 8)
(
input wclk ,
input wenc ,
input [$clog2(DEPTH)-1:0] waddr ,
input [WIDTH-1:0] wdata ,
input rclk ,
input renc ,
input [$clog2(DEPTH)-1:0] raddr ,
output reg [WIDTH-1:0] rdata
);
reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];
always @(posedge wclk) begin
if(wenc)
RAM_MEM[waddr] <= wdata;
end
always @(posedge rclk) begin
if(renc)
rdata <= RAM_MEM[raddr];
end
endmodule
/**************************************AFIFO*****************************************/
module asyn_fifo#(
parameter WIDTH = 8,
parameter DEPTH = 16
)(
input wclk ,
input rclk ,
input wrstn ,
input rrstn ,
input winc ,
input rinc ,
input [WIDTH-1:0] wdata ,
output wire wfull ,
output wire rempty ,
output wire [WIDTH-1:0] rdata
);
parameter ADDR_WIDTH = $clog2(DEPTH);
reg [ADDR_WIDTH:0] waddr_bin;
reg [ADDR_WIDTH:0] raddr_bin;
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
waddr_bin <= 'd0;
end
else if(!wfull && winc)begin
waddr_bin <= waddr_bin + 1'd1;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
raddr_bin <= 'd0;
end
else if(!rempty && rinc)begin
raddr_bin <= raddr_bin + 1'd1;
end
end
wire [ADDR_WIDTH:0] waddr_gray;
wire [ADDR_WIDTH:0] raddr_gray;
reg [ADDR_WIDTH:0] wptr;
reg [ADDR_WIDTH:0] rptr;
assign waddr_gray = waddr_bin ^ (waddr_bin>>1);
assign raddr_gray = raddr_bin ^ (raddr_bin>>1);
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
wptr <= 'd0;
end
else begin
wptr <= waddr_gray;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
rptr <= 'd0;
end
else begin
rptr <= raddr_gray;
end
end
reg [ADDR_WIDTH:0] wptr_buff;
reg [ADDR_WIDTH:0] wptr_syn;
reg [ADDR_WIDTH:0] rptr_buff;
reg [ADDR_WIDTH:0] rptr_syn;
always @(posedge wclk or negedge wrstn) begin
if(~wrstn) begin
rptr_buff <= 'd0;
rptr_syn <= 'd0;
end
else begin
rptr_buff <= rptr;
rptr_syn <= rptr_buff;
end
end
always @(posedge rclk or negedge rrstn) begin
if(~rrstn) begin
wptr_buff <= 'd0;
wptr_syn <= 'd0;
end
else begin
wptr_buff <= wptr;
wptr_syn <= wptr_buff;
end
end
assign wfull = (wptr == {~rptr_syn[ADDR_WIDTH:ADDR_WIDTH-1],rptr_syn[ADDR_WIDTH-2:0]});
assign rempty = (rptr == wptr_syn);
/***********RAM*********/
wire wen ;
wire ren ;
wire wren;//high write
wire [ADDR_WIDTH-1:0] waddr;
wire [ADDR_WIDTH-1:0] raddr;
assign wen = winc & !wfull;
assign ren = rinc & !rempty;
assign waddr = waddr_bin[ADDR_WIDTH-1:0];
assign raddr = raddr_bin[ADDR_WIDTH-1:0];
dual_port_RAM #(.DEPTH(DEPTH),
.WIDTH(WIDTH)
)dual_port_RAM(
.wclk (wclk),
.wenc (wen),
.waddr(waddr[ADDR_WIDTH-1:0]), //The depth is logarithmic to 2 to get the bit width of the address
.wdata(wdata), //data_write
.rclk (rclk),
.renc (ren),
.raddr(raddr[ADDR_WIDTH-1:0]),
.rdata(rdata)
);
endmodule |
RAM | Implement a dual-port RAM with a depth of 8 and a bit width of 6 bits, with all data initialized to 000000. It has two groups of ports, respectively for reading data and writing data, and read and write operations can be carried out at the same time. When the read_en signal is 1, the read_data of the corresponding position is read through the read_addr signal and output; When the write_en signal is 1, data is written to the corresponding position through the write_addr signal and write-data signal.
Module name:
RAM
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
write_en: Write enable signal to initiate a write operation.
write_addr: Address for the write operation.
write_data: Data to be written to the RAM.
read_en: Read enable signal to initiate a read operation.
read_addr: Address for the read operation.
Output ports:
read_data: Output signal representing the data read from the RAM.
Parameter:
WIDTH = 6;
DEPTH = 8;
Implementation:
RAM Array:
The module includes a register array, RAM. The array is defined as reg [DEPTH - 1 : 0] RAM [2**WIDTH-1:0], allowing for 2^6 memory locations, each with a width of 6 bits.
Write Operation:
The first always block triggers on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, all memory locations in the RAM array are cleared to 0.
If the write enable signal (write_en) is active, the data (write_data) is written to the RAM array at the specified address (write_addr).
Read Operation:
The second always block triggers on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by !rst_n, the read_data register is cleared to 0.
If the read enable signal (read_en) is active, the data at the specified address (read_addr) in the RAM array is assigned to the read_data register.
If the read enable signal is not active, the read_data register is cleared to 0.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule tb_RAM;\n\n // Parameters\n parameter CLK_PERIOD = 10; // Clock period in simulation time units\n \n // Inputs\n reg clk;\n reg rst_n;\n reg write_en;\n reg [7:0] write_addr;\n reg [5:0] write_data;\n reg read_en;\n reg [7:0] read_addr;\n \n // Outputs\n wire [5:0] read_data;\n\n // Instantiate the module\n RAM uut (\n .clk(clk),\n .rst_n(rst_n),\n .write_en(write_en),\n .write_addr(write_addr),\n .write_data(write_data),\n .read_en(read_en),\n .read_addr(read_addr),\n .read_data(read_data)\n );\n \n // Clock generation\n always #((CLK_PERIOD)/2) clk = ~clk;\n\n integer error = 0;\n // Initial block for stimulus generation\n initial begin\n // Initialize inputs\n clk = 0;\n rst_n = 1;\n repeat(100) begin\n write_en = 0;\n write_addr = 0;\n write_data = 0;\n read_en = 0;\n read_addr = 0;\n // Wait for a few clock cycles\n #((CLK_PERIOD) * 5);\n // Release reset\n rst_n = 0;\n #((CLK_PERIOD) * 2);\n rst_n = 1;\n // Write operation\n write_en = 1;\n write_addr = 3'b000;\n write_data = $random;\n #((CLK_PERIOD) * 1);\n write_en = 0;\n #((CLK_PERIOD) * 1);\n \n // Read operation\n read_en = 1;\n read_addr = 3'b000;\n #((CLK_PERIOD) * 1);\n $display(\"read_data = %b, expected = %b\", read_data, write_data);\n error = (read_data == write_data) ? error : error+1;\n read_en = 0;\n #((CLK_PERIOD) * 1);\n $display(\"read_data = %b, expected = 0\", read_data);\n error = (read_data == 0) ? error : error+1;\n end\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\", error);\n $fatal;\n end\n // Finish simulation\n $finish;\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = RAM\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module RAM (
input clk,
input rst_n,
input write_en,
input [7:0]write_addr,
input [5:0]write_data,
input read_en,
input [7:0]read_addr,
output reg [5:0]read_data
);
//defination
reg [7 : 0] RAM [11:0];
//output
integer i;
always@(posedge clk or negedge rst_n)begin
if(!rst_n) begin
for(i = 0; i < 8; i = i + 1) begin
RAM[i] <= 'd0;
end
end
else if(write_en)
RAM[write_addr] <= write_data;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
read_data <= 'd0;
else if(read_en)
read_data <= RAM[read_addr];
else
read_data <= 'd0;
end
endmodule
|
counter_12 | Implement a module of a counter design that requires counting from 4 'b0000 to 4' d11. The counting can be controlled by the input signal valid_count. That is, the count is paused if valid_count is 0. The counter increments on each clock cycle when the valid_count signal is active and resets to 0 when the reset signal (rst_n) is active.
Module name:
counter_12
Input ports:
rst_n: Reset signal (active low)
clk: Clock signal
valid_count: Signal to enable counting
Output ports:
out: 4-bit output representing the current count value
Implementation:
If the reset signal is active (!rst_n), the counter is reset to 0 by assigning the value 4'b0000 to the output register (out). If the valid_count signal is 1, the counter increments. It checks if the current count value (out) is equal to 4'd11 (maximum count value). If it is, the counter wraps around and resets to 0 by assigning the value 4'b0000 to the output register (out). Otherwise, it increments the output register by 1. If the valid_count = 0, the counter will stop, and the output register (out) remains unchanged.
| [
{
"content": "`timescale 1ns/1ps\nmodule counter_12_tb;\n\n reg clk, rst_n, valid_count;\n wire [3:0] out;\n\n counter_12 dut (\n .rst_n(rst_n),\n .clk(clk),\n .valid_count(valid_count),\n .out(out)\n );\n\n\n always #5 clk = ~clk;\n integer i = 0;\n integer error = 0;\n initial begin\n clk = 0;\n rst_n = 0;\n valid_count = 0;\n\n #20 rst_n = 1;\n // testcase1: validation of valid_count\n repeat(15) begin \n $display(\"case1 (rst_n = 1, valid_count = 0): Expect out = 0, got out = %d\", out);\n error = (out == 0) ?error:error+1;\n #10;\n end\n // testcase2: counter\n #100 valid_count = 1;\n repeat(11) begin \n $display(\"case2 (rst_n = 1, valid_count = 1): Expect out = %d, got out = %d\", i, out);\n error = (out == i) ?error:error+1;\n i = i+1;\n #10;\n end\n // testcase3: the count is paused if valid_count is invalid\n valid_count = 0;\n repeat(5) begin \n $display(\"case3 (rst_n = 1, valid_count = 0): Expect out = 11, got out = %d\", out);\n error = (out == 11) ?error:error+1;\n #10;\n end\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Failed===========\", error);\n $fatal;\n end\n $finish;\n end\n\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = counter_12\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ps
module counter_12
(
input rst_n,
input clk,
input valid_count,
output reg [3:0] out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
begin
out <= 4'b0000;
end
else if (valid_count)
begin
if (out == 4'd11)
begin
out <= 4'b0000;
end
else begin
out <= out + 1;
end
end
else begin
out <= out; // Pause the count when valid_count is invalid
end
end
endmodule
|
multi_pipe_8bit | Implement the design of unsigned 8bit multiplier based on pipelining processing. It utilizes a clock signal (clk), an active-low reset signal (rst_n), an input enable signal (mul_en_in), and provides an output enable signal (mul_en_out) and the product output (mul_out) of size 16 bits.
Module name:
multi_pipe_8bit
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
mul_en_in: Input enable signal that controls the multiplication operation.
mul_a: Input signal representing the multiplicand with a data width of 8 bits.
mul_b: Input signal representing the multiplier with a data width of 8 bits.
Output ports:
mul_en_out: Output enable signal indicating if the multiplication operation is enabled.
mul_out: Product output signal with a data width of 16 bits.
Implementation:
The module utilizes a pipeline architecture to improve performance. It consists of several key components:
Input Control:
The module includes an input enable signal, mul_en_in, which controls the multiplication operation.
On the positive edge of the clock signal, the module samples the input enable signal and stores it in a register, mul_en_out_reg.
The output enable signal, mul_en_out, is derived from the most significant bit of mul_en_out_reg, indicating whether the multiplication operation is enabled.
Input Registers:
The module includes registers, mul_a_reg and mul_b_reg, to store the input multiplicand and multiplier, respectively.
On the positive edge of the clock signal, the module samples the input values and stores them in the corresponding registers.
The registers are only updated when the input enable signal is active.
Partial Product Generation:
The module generates partial products by performing bitwise operations between the multiplicand and the individual bits of the multiplier.
It uses conditional assignments to select the appropriate bits from the multiplicand based on the multiplier bits.
The partial products are stored in a set of wires, temp, with each wire representing a different bit position.
Partial Sum Calculation:
The module performs addition operations on the partial products to calculate partial sums.
It uses a set of registers, sum, to store the intermediate sum values.
Each register corresponds to a group of partial products and is updated on the positive edge of the clock signal.
Final Product Calculation:
The module sums up all the partial sums to obtain the final product.
It uses a register, mul_out_reg, to store the accumulated sum.
On the positive edge of the clock signal, the register is updated with the sum of all partial sums.
Output Assignment:
The module assigns the output product value, mul_out, based on the output enable signal and the value in mul_out_reg.
If the output enable signal is active, indicating a valid product, the value in mul_out_reg is assigned to mul_out.
Otherwise, mul_out is set to 0.
| [
{
"content": "`timescale 1ns/1ns\n`define clk_period 20\nmodule tb_multi_pipe();\n \n reg [7:0] mul_a;\n reg [7:0] mul_b;\n reg mul_en_in;\n \n reg clk;\n reg rst_n;\n \n wire mul_en_out;\n wire [15:0] mul_out;\n\n reg [15:0] expected_product;\n \n multi_pipe_8bit u1(\n .clk(clk), \n .rst_n(rst_n), \n .mul_a(mul_a), \n .mul_b(mul_b),\n .mul_en_in(mul_en_in), \n \n .mul_en_out(mul_en_out),\n .mul_out(mul_out) \n);\n \n \n \ninitial clk = 1;\nalways # 10 clk = ~clk; \ninteger error = 0; \n \ninitial begin\n rst_n = 0;\n mul_a = 0;\n mul_b = 0;\n mul_en_in = 0;\n \n #(`clk_period*200+1);\n \n rst_n = 1;\n \n #(`clk_period*10);\n \n mul_a = 'd35;\n mul_b = 'd20;\n mul_en_in = 'd1;\n repeat (100) begin\n mul_en_in = 0;\n #(`clk_period*20);\n rst_n = 1;\n #(`clk_period*10);\n mul_a = $random;\n mul_b = $random;\n\n mul_en_in = 'd1;\n #(`clk_period);\n expected_product = mul_a * mul_b;\n #(`clk_period);\n error = ((mul_en_out==1) && (mul_out == expected_product)) ? error+1 : error;\n while (mul_en_out == 0) begin\n @(posedge clk); // Wait for one clock cycle\n end\n // //========it can be changed depending on your pipelining processing latency\n // #(`clk_period*4);\n // //========it can be changed depending on your pipelining processing latency\n error = (mul_out != expected_product) ? error+1 : error;\n if (mul_out != expected_product) begin\n $display(\"Failed testcase: mul_a = %d, mul_b = %d\", mul_a, mul_b);\n end\n end\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /100 failures===========\", error);\n $fatal;\n end\n \n $finish; \n \nend\n \nendmodule ",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = multi_pipe_8bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module multi_pipe_8bit#(
parameter size = 8
)(
clk,
rst_n,
mul_a,
mul_b,
mul_en_in,
mul_en_out,
mul_out
);
input clk;
input rst_n;
input mul_en_in;
input [size-1:0] mul_a;
input [size-1:0] mul_b;
output reg mul_en_out;
output reg [size*2-1:0] mul_out;
reg [2:0] mul_en_out_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
mul_en_out_reg <= 'd0;
mul_en_out <= 'd0;
end
else begin
mul_en_out_reg <= {mul_en_out_reg[1:0],mul_en_in};
mul_en_out <= mul_en_out_reg[2];
end
reg [7:0] mul_a_reg;
reg [7:0] mul_b_reg;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
mul_a_reg <= 'd0;
mul_a_reg <= 'd0;
end
else begin
mul_a_reg <= mul_en_in ? mul_a :'d0;
mul_b_reg <= mul_en_in ? mul_b :'d0;
end
wire [15:0] temp [size-1:0];
assign temp[0] = mul_b_reg[0]? {8'b0,mul_a_reg} : 'd0;
assign temp[1] = mul_b_reg[1]? {7'b0,mul_a_reg,1'b0} : 'd0;
assign temp[2] = mul_b_reg[2]? {6'b0,mul_a_reg,2'b0} : 'd0;
assign temp[3] = mul_b_reg[3]? {5'b0,mul_a_reg,3'b0} : 'd0;
assign temp[4] = mul_b_reg[4]? {4'b0,mul_a_reg,4'b0} : 'd0;
assign temp[5] = mul_b_reg[5]? {3'b0,mul_a_reg,5'b0} : 'd0;
assign temp[6] = mul_b_reg[6]? {2'b0,mul_a_reg,6'b0} : 'd0;
assign temp[7] = mul_b_reg[7]? {1'b0,mul_a_reg,7'b0} : 'd0;
reg [15:0] sum [3:0];//[size/2-1:1]
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
sum[0] <= 'd0;
sum[1] <= 'd0;
sum[2] <= 'd0;
sum[3] <= 'd0;
end
else begin
sum[0] <= temp[0] + temp[1];
sum[1] <= temp[2] + temp[3];
sum[2] <= temp[4] + temp[5];
sum[3] <= temp[6] + temp[7];
end
reg [15:0] mul_out_reg;
always @(posedge clk or negedge rst_n)
if(!rst_n)
mul_out_reg <= 'd0;
else
mul_out_reg <= sum[0] + sum[1] + sum[2] + sum[3];
always @(posedge clk or negedge rst_n)
if(!rst_n)
mul_out <= 'd0;
else if(mul_en_out_reg[2])
mul_out <= mul_out_reg;
else
mul_out <= 'd0;
endmodule |
radix2_div | Implement a simplified radix-2 divider on 8-bit signed or unsigned integers. and the inputs are two 8-bit operands. The module accepts a dividend and a divisor as inputs and provides a 16-bit result containing both the quotient and the remainder. The design supports both signed and unsigned division operations.
Module name:
radix2_div
Input ports:
clk: Clock signal used for synchronous operation.
rst: The reset signal to initialize or reset the module.
sign: 1-bit indicates if the operation is signed (1) or unsigned (0).
dividend: 8-bit input signal representing the dividend for division.
divisor: 8-bit input signal representing the divisor for division.
opn_valid: 1-bit indicates that a valid operation request is present.
Output ports:
res_valid: 1-bit output signal indicating the result is valid and ready.
result: 16-bit the output containing the remainder in the upper 8 bits and the quotient in the lower 8 bits.
Implementation:
Operation Start:
When opn_valid is high and res_valid is low, the module saves the inputs dividend and divisor.
Initializes the shift register SR with the absolute value of the dividend shifted left by one bit.
Sets NEG_DIVISOR to the negated absolute value of the divisor.
Sets the counter cnt to 1 and start_cnt to 1 to begin the division process.
Division Process(If start_cnt is high, the module performs the following steps):
If the counter cnt reaches 8 (most significant bit of cnt is set), the division is complete:
cnt and start_cnt are cleared.
Updates the shift register SR with the final remainder and quotient.
Otherwise, the counter cnt is incremented, and the shift register SR is updated based on the subtraction result:
Computes the subtraction of NEG_DIVISOR.
Uses a multiplexer to select the appropriate result based on the carry-out.
Updates SR by shifting left and inserting the carry-out.
Result Validity:
res_valid is managed based on the reset signal, the counter, and whether the result has been consumed.
| [
{
"content": "`timescale 1ns/1ps\n\nmodule radix2_div_tb;\n reg clk;\n reg rst;\n reg [7:0] dividend, divisor;\n reg sign;\n reg opn_valid;\n reg res_ready;\n wire res_valid;\n wire [15:0] result;\n\n // Instantiate the radix2_div module\n radix2_div uut (\n .clk(clk),\n .rst(rst),\n .dividend(dividend),\n .divisor(divisor),\n .sign(sign),\n .opn_valid(opn_valid),\n .res_valid(res_valid),\n .res_ready(res_ready),\n .result(result)\n );\n\n integer i;\n integer error = 0;\n reg [7:0] a_test [0:7];\n reg [7:0] b_test [0:7];\n reg [15:0] expected_result [0:7];\n reg sign_test [0:7];\n\n initial begin\n // Initialize test vectors\n a_test[0] = 8'd100; b_test[0] = 8'd10; sign_test[0] = 0; expected_result[0] = {8'd0, 8'd10}; \n a_test[1] = -8'd100; b_test[1] = 8'd10; sign_test[1] = 1; expected_result[1] = {8'd0, -8'd10};\n a_test[2] = 8'd100; b_test[2] = -8'd10; sign_test[2] = 1; expected_result[2] = {8'd0, -8'd10};\n a_test[3] = -8'd100; b_test[3] = -8'd10; sign_test[3] = 1; expected_result[3] = {8'd0, 8'd10};\n a_test[4] = 8'd123; b_test[4] = 8'd123; sign_test[4] = 0; expected_result[4] = {8'd0, 8'd1};\n a_test[5] = 8'd0; b_test[5] = 8'd123; sign_test[5] = 0; expected_result[5] = {8'd0, 8'd0};\n a_test[6] = 8'd123; b_test[6] = 8'd251; sign_test[6] = 0; expected_result[6] = {8'd123, 8'd0};\n a_test[7] = 8'd255; b_test[7] = 8'd7; sign_test[7] = 0; expected_result[7] = {8'd3, 8'd36};\n\n // Generate clock signal\n clk = 0;\n forever #5 clk = ~clk;\n end\n\n initial begin\n // Initialize\n rst = 1;\n opn_valid = 0;\n res_ready = 1;\n #20;\n rst = 0;\n\n for (i = 0; i < 8; i = i + 1) begin\n // Apply test vectors\n dividend = a_test[i];\n divisor = b_test[i];\n sign = sign_test[i];\n opn_valid = 1;\n #10;\n opn_valid = 0;\n\n // Wait for result\n wait(res_valid);\n #10;\n\n // Check result\n if (result !== expected_result[i]) begin\n error = error + 1;\n $display(\"Failed testcase: dividend = %d, divisor = %d, sign = %d\", a_test[i], b_test[i], sign_test[i]);\n end\n\n res_ready = 1;\n #10;\n end\n\n // Display final result\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end else begin\n $display(\"===========Failed===========\", error);\n $fatal;\n end\n\n $finish;\n end\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = radix2_div\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ps
module radix2_div(
input wire clk,
input wire rst,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire sign,
input wire opn_valid,
output reg res_valid,
input wire res_ready,
output wire [15:0] result
);
reg [7:0] dividend_save, divisor_save;
reg [15:0] SR;
reg [8 :0] NEG_DIVISOR;
wire [7:0] REMAINER, QUOTIENT;
assign REMAINER = SR[15:8];
assign QUOTIENT = SR[7: 0];
wire [7:0] divident_abs;
wire [8:0] divisor_abs;
wire [7:0] remainer, quotient;
assign divident_abs = (sign & dividend[7]) ? ~dividend + 1'b1 : dividend;
assign remainer = (sign & dividend_save[7]) ? ~REMAINER + 1'b1 : REMAINER;
assign quotient = sign & (dividend_save[7] ^ divisor_save[7]) ? ~QUOTIENT + 1'b1 : QUOTIENT;
assign result = {remainer,quotient};
wire CO;
wire [8:0] sub_result;
wire [8:0] mux_result;
assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR;
assign mux_result = CO ? sub_result : {1'b0,REMAINER};
reg [3:0] cnt;
reg start_cnt;
always @(posedge clk) begin
if(rst) begin
SR <= 0;
dividend_save <= 0;
divisor_save <= 0;
cnt <= 0;
start_cnt <= 1'b0;
end
else if(~start_cnt & opn_valid & ~res_valid) begin
cnt <= 1;
start_cnt <= 1'b1;
dividend_save <= dividend;
divisor_save <= divisor;
SR[15:0] <= {7'b0,divident_abs,1'b0};
NEG_DIVISOR <= (sign & divisor[7]) ? {1'b1,divisor} : ~{1'b0,divisor} + 1'b1;
end
else if(start_cnt) begin
if(cnt[3]) begin
cnt <= 0;
start_cnt <= 1'b0;
SR[15:8] <= mux_result[7:0];
SR[0] <= CO;
end
else begin
cnt <= cnt + 1;
SR[15:0] <= {mux_result[6:0],SR[7:1],CO,1'b0};
end
end
end
wire data_go;
assign data_go = res_valid & res_ready;
always @(posedge clk) begin
res_valid <= rst ? 1'b0 :
cnt[3] ? 1'b1 :
data_go ? 1'b0 : res_valid;
end
endmodule
|
float_multi | Implement a module of a 32-bit floating-point multiplier for IEEE-754 standard single-precision arithmetic.
The float_multi module is designed to perform high-precision multiplication of 32-bit single-precision floating-point numbers, following the IEEE 754 standard. This module enables accurate arithmetic operations essential for various computational applications.
Module name:
float_multi
Input ports:
clk (input): Clock signal for synchronization.
rst (input): Reset signal (active high).
a (input [31:0]): First operand in IEEE 754 format.
b (input [31:0]): Second operand in IEEE 754 format.
Output ports:
z (output reg [31:0]): Result of the multiplication in IEEE 754 format.
Internal signals:
counter (reg [2:0]): Cycle counter for operation sequencing.
a_mantissa, b_mantissa, z_mantissa (reg [23:0]): Mantissas of input and output numbers.
a_exponent, b_exponent, z_exponent (reg [9:0]): Exponents of input and output numbers.
a_sign, b_sign, z_sign (reg): Sign bits for inputs and output.
product (reg [49:0]): Intermediate product of the mantissas.
guard_bit, round_bit, sticky (reg): Rounding control bits.
Implementation:
-Initialization: The counter is reset to zero on the rst signal.
-Input Processing: The mantissas, exponents, and sign bits of inputs a and b are extracted during the first clock cycle.
-Special Cases Handling: The module identifies special cases like NaN (Not a Number) and infinity based on the inputs.
-Normalization: Mantissas are normalized if needed.
-Multiplication: The mantissas are multiplied, combining the signs and adjusting the exponents.
-Rounding and Adjustment: The module rounds the result and adjusts the exponent to ensure accurate representation.
-Output Generation: The final result is formatted in IEEE 754 standard, addressing overflow and underflow scenarios.
Give me the complete code. | [
{
"content": "module fmultiplier_tb;\n\nreg [31:0] a, b;\nwire [31:0] z;\nreg clk, rst;\n\nfloat_multi uut(clk , rst, a, b, z);\ninteger error = 0;\ninitial begin\n clk <= 0;\n rst <= 1;\n repeat(17000)\n #5 clk <= ~clk;\nend\n\ninitial #13 rst <= 0;\n\ninitial begin\n #3\n repeat(2) begin\n #80\n a = 32'b00111110100110011001100110011010;\n b = 32'b00111110100110011001100110011010;\n end\n \n #80\n error = (z==32'b00111101101110000101000111101100) ? error:error+1;\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d/20 failures ===========\", error);\n $fatal;\n end\n $finish;\nend\n\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = float_multi\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module float_multi(clk, rst, a, b, z);
input clk, rst;
input [31:0] a, b;
output reg [31:0] z;
reg [2:0] counter;
reg [23:0] a_mantissa, b_mantissa, z_mantissa; //Mantissa
reg [9:0] a_exponent, b_exponent, z_exponent; //EXPONENTS
reg a_sign, b_sign, z_sign; // Sign_Bit
reg [49:0] product;
reg guard_bit, round_bit, sticky;
always @(posedge clk or rst) begin
if(rst)
counter <= 0;
else
counter <= counter + 1;
end
always @(counter) begin
if(counter == 3'b001) begin
//IEEE 754 Representation
a_mantissa <= a[22:0];
b_mantissa <= b[22:0];
a_exponent <= a[30:23] - 127;
b_exponent <= b[30:23] - 127;
a_sign <= a[31];
b_sign <= b[31];
end
end
always @(counter) begin
if(counter == 3'b010) begin
if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin //Not a Number
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
else if (a_exponent == 128) begin //INF A
z[31] <= a_sign ^ b_sign;
z[30:23] <= 255;
z[22:0] <= 0;
if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin //NAN IF B = 0
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
end
else if (b_exponent == 128) begin //INF B
z[31] <= a_sign ^ b_sign;
z[30:23] <= 255;
z[22:0] <= 0;
if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin //NAN IF A = 0
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
end
end
else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin //0 if A = 0
z[31] <= a_sign ^ b_sign; //Sign_Bit
z[30:23] <= 0;
z[22:0] <= 0;
end
else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin //0 if B = 0
z[31] <= a_sign ^ b_sign;
z[30:23] <= 0;
z[22:0] <= 0;
end
else begin
if ($signed(a_exponent) == -127) //DENORMALIZING A
a_exponent <= -126;
else
a_mantissa[23] <= 1;
if ($signed(b_exponent) == -127) //DENORMALIZING B
b_exponent <= -126;
else
b_mantissa[23] <= 1;
end
end
end
always @(counter) begin
if(counter == 3'b011) begin
if (~a_mantissa[23]) begin //NORMALIZE A
a_mantissa <= a_mantissa << 1;
a_exponent <= a_exponent - 1;
end
if (~b_mantissa[23]) begin //NORMALIZE B
b_mantissa <= b_mantissa << 1;
b_exponent <= b_exponent - 1;
end
end
end
always @(counter) begin
if(counter == 3'b100) begin //GET THE SIGNS XORED and EXPONENTS ADDED and GET THE INTERMEDIATE MANTISSA MULTIPLICATION
z_sign <= a_sign ^ b_sign;
z_exponent <= a_exponent + b_exponent + 1 ;
product <= a_mantissa * b_mantissa * 4;
end
end
always @(counter) begin
if(counter == 3'b101) begin
z_mantissa <= product[49:26];
guard_bit <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
end
end
always @(counter) begin
if(counter == 3'b110) begin
if ($signed(z_exponent) < -126) begin
z_exponent <= z_exponent + (-126 -$signed(z_exponent));
z_mantissa <= z_mantissa >> (-126 -$signed(z_exponent));
guard_bit <= z_mantissa[0];
round_bit <= guard_bit;
sticky <= sticky | round_bit;
end
else if (z_mantissa[23] == 0) begin
z_exponent <= z_exponent - 1;
z_mantissa <= z_mantissa << 1;
z_mantissa[0] <= guard_bit;
guard_bit <= round_bit;
round_bit <= 0;
end
else if (guard_bit && (round_bit | sticky | z_mantissa[0])) begin
z_mantissa <= z_mantissa + 1;
if (z_mantissa == 24'hffffff)
z_exponent <=z_exponent + 1;
end
end
end
always @(counter) begin
if(counter == 3'b111) begin
z[22:0] <= z_mantissa[22:0];
z[30:23] <= z_exponent[7:0] + 127;
z[31] <= z_sign;
if ($signed(z_exponent) == -126 && z_mantissa[23] == 0)
z[30:23] <= 0;
if ($signed(z_exponent) > 127) begin //IF OVERFLOW RETURN INF
z[22:0] <= 0;
z[30:23] <= 255;
z[31] <= z_sign;
end
end
end
endmodule |
instr_reg | An instruction register module designed to hold and process CPU instructions. It captures incoming instructions from various sources and separates them into distinct fields for further processing.
Module name:
instr_reg
Input ports:
clk: Clock signal for synchronization.
rst: Active low reset signal to initialize the register.
fetch [1:0]: Control signal indicating the source of the instruction (1 for register, 2 for RAM/ROM).
data [7:0]: 8-bit data input representing the instruction to be fetched.
Output ports:
ins [2:0]: High 3 bits of the instruction, indicating the opcode or operation.
ad1 [4:0]: Low 5 bits of the instruction, representing the register address.
ad2 [7:0]: The full 8-bit data from the second source.
Implementation:
The instruction register contains two 8-bit registers (ins_p1 and ins_p2) to store instructions from different sources.
On the rising edge of the clock (clk), if the reset (rst) signal is low, both registers are initialized to zero.
Based on the fetch signal:
If fetch is 2'b01, the instruction is fetched from the data input into ins_p1.
If fetch is 2'b10, the instruction is fetched from the data input into ins_p2.
If neither condition is met, the previous values in both registers are retained.
The outputs ins, ad1, and ad2 are derived from the stored instructions.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule instr_reg_tb;\n\nreg clk;\nreg rst;\nreg [1:0] fetch;\nreg [7:0] data;\n\nwire [2:0] ins;\nwire [4:0] ad1;\nwire [7:0] ad2;\n\ninstr_reg uut (\n .clk(clk),\n .rst(rst),\n .fetch(fetch),\n .data(data),\n .ins(ins),\n .ad1(ad1),\n .ad2(ad2)\n);\n\ninteger error;\ninteger expected_ins;\ninteger expected_ad1;\ninteger expected_ad2;\n\ninitial begin\n // Initialize Inputs\n clk = 0;\n rst = 0;\n fetch = 2'b00;\n data = 8'h00;\n error = 0;\n\n // Wait 100 ns for initialization\n #100;\n\n // De-assert reset\n rst = 1;\n #10;\n\n // Perform fetch operation 1 from register\n fetch = 2'b01;\n #5;\n data = 8'b01011100;\n expected_ins = 3'b010;\n expected_ad1 = 5'b11100;\n expected_ad2 = 8'b00;\n #20;\n\n // Check the values\n if (ins !== expected_ins) begin\n error = error + 1; \n $display(\"Failed: fetch operation 1: clk=%d, ins=%b (expected %d)\", clk, ins, expected_ins);\n end\n\n if (ad1 !== expected_ad1) begin\n error = error + 1; \n $display(\"Failed: fetch operation 1: clk=%d, ad1=%b (expected %d)\", clk, ad1, expected_ad1);\n end\n\n if (ad2 !== expected_ad2) begin\n error = error + 1; \n $display(\"Failed: fetch operation 1: clk=%d, ad2=%b (expected %d)\", clk, ad2, expected_ad2);\n end\n\n // Additional test cases can be added here\n\n // Finish simulation and display total errors\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d failures ===========\", error);\n $fatal;\n end\n $finish;\nend\n\nalways #5 clk = ~clk;\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = instr_reg\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module instr_reg (
input clk,
input rst,
input [1:0] fetch,
input [7:0] data,
output [2:0] ins,
output [4:0] ad1,
output [7:0] ad2
);
reg [7:0] ins_p1, ins_p2;
reg [2:0] state;
always @(posedge clk or negedge rst) begin
if (!rst) begin
ins_p1 <= 8'd0;
ins_p2 <= 8'd0;
end else begin
if (fetch == 2'b01) begin // Fetch operation 1, from REG
ins_p1 <= data;
ins_p2 <= ins_p2;
end else if (fetch == 2'b10) begin // Fetch operation 2, from RAM/ROM
ins_p1 <= ins_p1;
ins_p2 <= data;
end else begin
ins_p1 <= ins_p1;
ins_p2 <= ins_p2;
end
end
end
assign ins = ins_p1[7:5]; // High 3 bits, instructions
assign ad1 = ins_p1[4:0]; // Low 5 bits, register address
assign ad2 = ins_p2;
endmodule |
accu | Implement a module to achieve serial input data accumulation output, input is 8bit data. The valid_in will be set to 1 before the first data comes in. Whenever the module receives 4 input data, the data_out outputs 4 received data accumulation results and sets the valid_out to be 1 (will last only 1 cycle).
Module name:
accu
Input ports:
clk: Clock input for synchronization.
rst_n: Active-low reset signal.
data_in[7:0]: 8-bit input data for addition.
valid_in: Input signal indicating readiness for new data.
Output ports:
valid_out: Output signal indicating when 4 input data accumulation is reached.
data_out[9:0]: 10-bit output data representing the accumulated sum.
Implementation:
When valid_in is 1, data_in is a valid input. Accumulate four valid input data_in values and calculate the output data_out by adding these four values together.
There is no output when there are fewer than four data_in inputs in the interim. Along with the output data_out, a cycle of valid_out=1 will appear as a signal.
The valid_out signal is set to 1 when the data_out outputs 4 received data accumulation results. Otherwise, it is set to 0.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule tb_valid_ready;\n\n\nparameter PERIOD = 10;\nreg clk = 0 ;\nreg rst_n = 0 ;\nreg [7:0] data_in = 0 ;\nreg valid_in = 0 ;\n\nwire valid_out ;\nwire [9:0] data_out ;\n\n\ninitial\nbegin\n forever #(PERIOD/2) clk=~clk;\nend\n\ninitial\nbegin\n #(PERIOD*2) rst_n = 1;\nend\n\naccu uut (\n .clk ( clk ),\n .rst_n ( rst_n ),\n .data_in ( data_in [7:0] ),\n .valid_in ( valid_in ),\n\n .valid_out ( valid_out ),\n .data_out ( data_out [9:0] )\n);\n\ninitial\nbegin\n #(PERIOD*1+0.01); \n #(PERIOD) data_in = 8'd1;valid_in = 1;\n #(PERIOD) data_in = 8'd2;\n #(PERIOD) data_in = 8'd3;\n #(PERIOD) data_in = 8'd14;\n\n #(PERIOD) data_in = 8'd5;\n #(PERIOD) data_in = 8'd2;\n #(PERIOD) data_in = 8'd103;\n #(PERIOD) data_in = 8'd4;\n\n #(PERIOD) data_in = 8'd5;\n #(PERIOD) data_in = 8'd6;\n #(PERIOD) data_in = 8'd3;\n #(PERIOD) data_in = 8'd54;\n #(PERIOD*2);\n $finish;\nend\n\nreg [9:0] result [0:2];\ninitial begin\n result[0] = 9'd20;\n result[1] = 9'd114;\n result[2] = 9'd68;\nend\n\ninteger i;\ninteger casenum = 0;\ninteger error = 0;\n\ninitial\nbegin\n for (i = 0; i < 15; i = i + 1) begin\n #((PERIOD) * 1); \n if (valid_out) begin\n error = (data_out == result[casenum]) ? error : error + 1;\n if (data_out != result[casenum]) begin\n $display(\"Failed testcase: data_in = %d\", i);\n end\n casenum = casenum + 1;\n end \n end\n if(error==0 && casenum==3)\n begin\n $display(\"===========Your Design Passed===========\");\n end\n else\n begin\n $display(\"===========Error===========\");\n $fatal;\n end\n $finish;\nend\n\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = accu\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module accu(
input clk ,
input rst_n ,
input [7:0] data_in ,
input valid_in ,
output reg valid_out ,
output reg [9:0] data_out
);
reg [1:0] count;
wire add_cnt;
wire ready_add;
wire end_cnt;
reg [9:0] data_out_reg;
assign add_cnt = ready_add;
assign end_cnt = ready_add && (count == 'd3);
//count
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 0;
end
else if(end_cnt) begin
count <= 0;
end
else if(add_cnt) begin
count <= count + 1;
end
end
//data_out_reg
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out_reg <= 0;
end
else if (add_cnt && count == 0) begin
data_out_reg <= data_in;
end
else if (add_cnt) begin
data_out_reg <= data_out_reg + data_in;
end
end
//data_out
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_out <= 0;
end
else if (add_cnt && count == 0) begin
data_out <= data_in;
end
else if (add_cnt) begin
data_out <= data_out + data_in;
end
end
//ready_add
assign ready_add = !valid_out | valid_in;
//valid_out
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
valid_out <= 0;
end
else if(end_cnt) begin
valid_out <= 1;
end
else begin
valid_out <= 0;
end
end
endmodule |
fsm | Implement a Mealy FSM detection circuit that detects a single-bit input IN. When the input is 10011, output MATCH is 1, and MATCH is 0 in other cases. Support for continuous input and loop detection.
Module name:
fsm
Input ports:
IN: Input signal to the FSM.
CLK: Clock signal used for synchronous operation.
RST: Reset signal to initialize the FSM.
Output ports:
MATCH: Output signal indicating a match condition based on the FSM state.
Implementation:
The module implements an FSM detection.
On every change in the input signal (IN) or positive edge of CLK or RST, if RST is active, the output signal MATCH is set to 0.
If the sequence of inputs IN is 1, 0, 0, 1, 1, the MATCH signal is 1 at the same time as the last occurrence of IN=1. If the sequence of inputs IN is 1, 0, 0, 1, 1, 0, 0, 1, 1, the MATCH signal becomes 1 at the fifth and ninth of IN; otherwise, it is set to 0.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule main();\n\nreg clk, rst;\nreg IN;\nwire MATCH;\n\nfsm DUT(.CLK(clk), .RST(rst), .IN(IN), .MATCH(MATCH));\n\ninitial begin\n clk = 0;\n forever #5 clk = ~clk;\nend\n\ninteger error = 0;\ninitial begin\n #10;\n rst = 1;\n #28;\n rst = 0;\n IN = 0;\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 1) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 0;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 0) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n #10 IN = 1;\n error = (MATCH == 1) ? error : error + 1;\n if (MATCH != 0) begin\n $display(\"Failed testcase: IN = %d at time = %d\", IN, $time);\n end\n\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n $finish;\nend\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = fsm\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module fsm(IN,MATCH,CLK,RST);
input IN,CLK,RST;
output reg MATCH;
reg [2:0] ST_cr,ST_nt;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
always@(posedge CLK or posedge RST) begin
if(RST)
ST_cr <= s0;
else
ST_cr <= ST_nt;
end
always@(*) begin
case(ST_cr)
s0:begin
if (IN==0)
ST_nt = s0;
else
ST_nt = s1;
end
s1:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s1;
end
s2:begin
if (IN==0)
ST_nt = s3;
else
ST_nt = s1;
end
s3:begin
if (IN==0)
ST_nt = s0;
else
ST_nt = s4;
end
s4:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s5;
end
s5:begin
if (IN==0)
ST_nt = s2;
else
ST_nt = s1;
end
endcase
end
always@(*) begin
if(RST)
MATCH <= 0;
else if (ST_cr == s4 && IN == 1)
MATCH <= 1;
else
MATCH <= 0;
end
endmodule |
signal_generator | Implement a Triangle Wave signal generator module that generates a waveform by incrementing and decrementing a 5-bit signal named "wave". The waveform cycles between 0 and 31, which is incremented or decremented by 1.
Module name:
signal_generator
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for reset and 1 for reset signal inactive.
Output ports:
wave: 5-bit output waveform signal representing the generated waveform.
Implementation:
State and Waveform Generation:
The module includes a register, state, used to control the state of the waveform generation.
The module also includes a register, wave, with a width of 5 bits, which represents the generated waveform.
The state and waveform registers are updated in the always block, triggered on the positive edge of the clock signal (posedge clk) or the negative edge of the reset signal (negedge rst_n).
On reset, indicated by ~rst_n, the state register is cleared to 0, and the wave register is cleared to 0.
The waveform generation is controlled using a case statement based on the current state:
If the state is 0, the waveform (wave) is incremented by 1.
If the waveform reaches 31 (wave == 31), the state is transitioned to 1.
If the state is 1, the waveform is decremented by 1.
If the waveform reaches 0 (wave == 0), the state is transitioned back to 0.
The waveform generation continues to cycle between 0 and 31 based on the state transitions.
| [
{
"content": "module tb_signal_generator;\nreg clk,rst_n;\nwire[4:0] wave;\n\nsignal_generator uut(\n .clk(clk),\n .rst_n(rst_n),\n .wave(wave)\n );\n\nreg[31:0]reference[0:99];\n\ninteger i = 0;\ninteger error = 0;\n// integer outfile;\ninitial begin\n $readmemh(\"tri_gen.txt\",reference);\n clk = 0;\n rst_n = 0;\n #10\n rst_n = 1;\n repeat(100) begin\n error=(wave==reference[i])?error:error+1;\n if (wave!=reference[i]) begin\n $display(\"Failed: expect wave=%h at %d, got wave=%h\", reference[i], i, wave);\n #10;\n i = i+1;\n end\n end\n if(error==0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n $finish;\nend\n \nalways #5 clk =~clk;\n \nendmodule\n\n",
"name": "testbench.v"
},
{
"content": "00\n01\n02\n03\n04\n05\n06\n07\n08\n09\n0a\n0b\n0c\n0d\n0e\n0f\n10\n11\n12\n13\n14\n15\n16\n17\n18\n19\n1a\n1b\n1c\n1d\n1e\n1f\n1f\n1e\n1d\n1c\n1b\n1a\n19\n18\n17\n16\n15\n14\n13\n12\n11\n10\n0f\n0e\n0d\n0c\n0b\n0a\n09\n08\n07\n06\n05\n04\n03\n02\n01\n00\n00\n01\n02\n03\n04\n05\n06\n07\n08\n09\n0a\n0b\n0c\n0d\n0e\n0f\n10\n11\n12\n13\n14\n15\n16\n17\n18\n19\n1a\n1b\n1c\n1d\n1e\n1f\n1f\n1e\n1d\n1c\n",
"name": "tri_gen.txt"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = signal_generator\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module signal_generator(
input clk,
input rst_n,
output reg [4:0] wave
);
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= 2'b0;
wave <= 5'b0;
end
else begin
case (state)
2'b00:
begin
if (wave == 5'b11111)
state <= 2'b01;
else
wave <= wave + 1;
end
2'b01:
begin
if (wave == 5'b00000)
state <= 2'b00;
else
wave <= wave - 1;
end
endcase
end
end
endmodule |
multi_8bit | Implement a module of an 8-bit multiplier based on shifting and adding operations.
Module name:
multi_8bit
Input ports:
A [7:0]: First 8-bit input operand (representing a multiplicand).
B [7:0]: Second 8-bit input operand (representing a multiplier).
Output ports:
product [15:0]: 16-bit output representing the product of the two 8-bit inputs (A * B).
Implementation:
Multiplication: The module performs multiplication of A and B using the shift-and-add method.
- The algorithm iterates through each bit of the multiplier (B). For each bit that is set (1), the multiplicand (A) is added to the product at the corresponding shifted position.
- The process continues until all bits of the multiplier have been processed.
Shifting: After each addition, the multiplicand is logically shifted left by one bit to prepare for the next addition, simulating the traditional multiplication process.
The final product is stored in the output port, which is 16 bits wide to accommodate the maximum possible product of two 8-bit numbers.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [7:0] A; // Input A (8 bits)\n reg [7:0] B; // Input B (8 bits)\n wire [15:0] product; // Product result (16 bits)\n integer i; // Loop variable\n integer error = 0; // Error count for failed tests\n\n multi_8bit uut (\n .A(A),\n .B(B),\n .product(product)\n );\n\n // Test cases\n initial begin\n\n for (i = 0; i < 100; i = i + 1) begin\n // Generate random 8-bit inputs\n A = $random;\n B = $random;\n\n // Wait for the operation to complete\n #10;\n\n // $display(\"A = %d, B = %d, Expected Product = %d\", A, B, A * B);\n\n // Check the result of the multiplication\n if (product !== A * B) begin\n error = error + 1;\n $display(\"Failed: A = %d, B = %d, Expected Product = %d, Got = %d\", A, B, A * B, product);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = multi_8bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module multi_8bit (
input [7:0] A,
input [7:0] B,
output reg [15:0] product
);
reg [7:0] multiplicand;
reg [3:0] shift_count;
always @* begin
product = 16'b0;
multiplicand = A;
shift_count = 0;
for (int i = 0; i < 8; i = i + 1) begin
if (B[i] == 1) begin
product = product + (multiplicand << shift_count);
end
shift_count = shift_count + 1;
end
end
endmodule |
freq_divbyeven | Frequency divider that divides the input clock frequency by even numbers. This module generates a divided clock signal by toggling its output every specified number of input clock cycles.
Module name:
freq_divbyeven
Input ports:
clk: Input clock signal that will be divided.
rst_n: Active-low reset signal to initialize the module.
Output ports:
clk_div: Divided clock output signal.
Implementation:
The frequency divider uses a counter (`cnt`) to count the number of clock cycles. The `NUM_DIV` parameter specifies the division factor, which must be an even number.
- When the reset signal (`rst_n`) is low, the counter and the divided clock signal (`clk_div`) are initialized to zero.
- On each positive edge of the input clock (`clk`), if the counter is less than half of `NUM_DIV - 1`, the counter increments without changing the divided clock output.
- When the counter reaches the specified limit, it resets to zero and toggles the `clk_div` output signal, effectively dividing the frequency of the input clock by the even number specified by `NUM_DIV`.
Counter:
- The counter is a 4-bit register (`cnt`) that tracks the number of clock cycles.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\nmodule testb_div_even;\n // Inputs\n reg clk;\n reg rst_n;\n // Outputs\n wire clk_div;\n \n // Instantiate the Unit Under Test (UUT)\n freq_divbyeven uut (\n .clk(clk), \n .rst_n(rst_n), \n .clk_div(clk_div)\n );\n always #5 clk = ~clk;\n \n integer error = 0;\n integer expected_value = 0;\n integer i;\n initial begin\n // Initialize Inputs\n clk = 1;\n rst_n = 0;\n # 10 rst_n = 1;\n #100;\n\n $finish;\n end\n initial begin\n // $monitor(\"clk=%d, clk_div=%d\",clk,clk_div);\n #5;\n for (i = 1; i < 20; i = i + 1) begin\n if (clk_div !== expected_value) begin\n error = error + 1; \n $display(\"Failed: expect clk_div = %d, got clk_div = %d\", expected_value, clk_div);\n end\n\n if (i < 6) expected_value = 0; // First five pairs\n else if (i < 12) expected_value = 1; // Next five pairs\n else if (i < 18) expected_value = 0; // Next five pairs\n else expected_value = 1; // Last five pairs\n #5;\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d/20 failures ===========\", error);\n $fatal;\n end\n end\nendmodule\n ",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = freq_divbyeven\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module freq_divbyeven(
clk,
rst_n,
clk_div
);
input clk;
input rst_n;
output clk_div;
reg clk_div;
parameter NUM_DIV = 6;
reg [3:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 4'd0;
clk_div <= 1'b0;
end
else if(cnt < NUM_DIV / 2 - 1) begin
cnt <= cnt + 1'b1;
clk_div <= clk_div;
end
else begin
cnt <= 4'd0;
clk_div <= ~clk_div;
end
endmodule |
adder_pipe_64bit | Implement a module of a 64-bit ripple carry adder, which includes several registers to enable the pipeline stages. The output result is available on the result port, and the o_en = 1 indicates the availability of the result.
Module name:
adder_pipe_64bit
Input ports:
clk: Clock input
rst_n: Active low reset signal
i_en: Enable signal for addition operation
adda: 64-bit input operand A
addb: 64-bit input operand B
Output ports:
result: 65-bit output representing the sum of adda and addb.
o_en: Output enable signal.
Implementation:
The module includes several registers to enable the pipeline stages and synchronize the input enable signal (i_en). These registers are controlled by the clock (clk) and reset (rst_n) signals.
The sum values for each pipeline stage are calculated by adding the corresponding input operands and carry signals.
The output enable signal (o_en) is updated based on the pipeline stages and synchronized with the clock (clk) and reset (rst_n) signals.
| [
{
"content": "module tb_adder64();\n\n parameter DATA_WIDTH = 64;\n parameter STG_WIDTH = 16;\n\n reg CLK;\n reg RST;\n reg i_en;\n wire o_en;\n reg [DATA_WIDTH-1:0] PLUS_A;\n reg [DATA_WIDTH-1:0] PLUS_B;\n wire [DATA_WIDTH:0] SUM_OUT;\n wire [DATA_WIDTH:0] sum_out_golden;\n reg [DATA_WIDTH:0] sum_out_golden_ff1;\n reg [DATA_WIDTH:0] sum_out_golden_ff2;\n reg [DATA_WIDTH:0] sum_out_golden_ff3;\n reg [DATA_WIDTH:0] sum_out_golden_ff4;\n\n assign {sum_out_golden} = PLUS_A + PLUS_B;\n\n always #2 CLK = ~CLK;\n\n integer error = 0;\n initial begin\n CLK = 0;\n repeat (100) begin\n RST = 0;\n i_en = 0;\n #8 RST = 1;\n i_en = 1'b1;\n PLUS_A = $random * $random;\n PLUS_B = $random * $random;\n while(o_en==0) begin\n @(negedge CLK);\n end\n error = ((PLUS_A + PLUS_B) == SUM_OUT && o_en ==1 ) ? error : error + 1;\n if ((PLUS_A + PLUS_B) != SUM_OUT || o_en != 1) begin\n $display(\"Failed testcase: PLUS_A = %d, PLUS_B = %d\", PLUS_A, PLUS_B);\n end\n @(negedge CLK);\n end\n\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d / 100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\n always @(posedge CLK, negedge RST) begin\n if (!RST) begin\n sum_out_golden_ff1 <= 'd0;\n sum_out_golden_ff2 <= 'd0;\n sum_out_golden_ff3 <= 'd0;\n sum_out_golden_ff4 <= 'd0;\n end\n else begin\n sum_out_golden_ff1 <= sum_out_golden;\n sum_out_golden_ff2 <= sum_out_golden_ff1;\n sum_out_golden_ff3 <= sum_out_golden_ff2;\n sum_out_golden_ff4 <= sum_out_golden_ff3;\n end\n end\n\n adder_pipe_64bit #(\n .DATA_WIDTH(DATA_WIDTH),\n .STG_WIDTH(STG_WIDTH)\n )\n u_pip_add64 (\n .clk (CLK),\n .rst_n (RST),\n .i_en (i_en),\n .adda (PLUS_A),\n .addb (PLUS_B),\n .result (SUM_OUT),\n .o_en (o_en)\n );\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = adder_pip_64bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module adder_pipe_64bit
#(
parameter DATA_WIDTH = 64,
parameter STG_WIDTH = 16
)
(
input clk,
input rst_n,
input i_en,
input [DATA_WIDTH-1:0] adda,
input [DATA_WIDTH-1:0] addb,
output [DATA_WIDTH:0] result,
output reg o_en
);
reg stage1;
reg stage2;
reg stage3;
wire [STG_WIDTH-1:0] a1;
wire [STG_WIDTH-1:0] b1;
wire [STG_WIDTH-1:0] a2;
wire [STG_WIDTH-1:0] b2;
wire [STG_WIDTH-1:0] a3;
wire [STG_WIDTH-1:0] b3;
wire [STG_WIDTH-1:0] a4;
wire [STG_WIDTH-1:0] b4;
reg [STG_WIDTH-1:0] a2_ff1;
reg [STG_WIDTH-1:0] b2_ff1;
reg [STG_WIDTH-1:0] a3_ff1;
reg [STG_WIDTH-1:0] b3_ff1;
reg [STG_WIDTH-1:0] a3_ff2;
reg [STG_WIDTH-1:0] b3_ff2;
reg [STG_WIDTH-1:0] a4_ff1;
reg [STG_WIDTH-1:0] b4_ff1;
reg [STG_WIDTH-1:0] a4_ff2;
reg [STG_WIDTH-1:0] b4_ff2;
reg [STG_WIDTH-1:0] a4_ff3;
reg [STG_WIDTH-1:0] b4_ff3;
reg c1;
reg c2;
reg c3;
reg c4;
reg [STG_WIDTH-1:0] s1;
reg [STG_WIDTH-1:0] s2;
reg [STG_WIDTH-1:0] s3;
reg [STG_WIDTH-1:0] s4;
reg [STG_WIDTH-1:0] s1_ff1;
reg [STG_WIDTH-1:0] s1_ff2;
reg [STG_WIDTH-1:0] s1_ff3;
reg [STG_WIDTH-1:0] s2_ff1;
reg [STG_WIDTH-1:0] s2_ff2;
reg [STG_WIDTH-1:0] s3_ff1;
assign a1 = adda[STG_WIDTH-1:0];
assign b1 = addb[STG_WIDTH-1:0];
assign a2 = adda[STG_WIDTH*2-1:16];
assign b2 = addb[STG_WIDTH*2-1:16];
assign a3 = adda[STG_WIDTH*3-1:32];
assign b3 = addb[STG_WIDTH*3-1:32];
assign a4 = adda[STG_WIDTH*4-1:48];
assign b4 = addb[STG_WIDTH*4-1:48];
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
stage1 <= 1'b0;
stage2 <= 1'b0;
stage3 <= 1'b0;
o_en <= 1'b0;
end
else begin
stage1 <= i_en;
stage2 <= stage1;
stage3 <= stage2;
o_en <= stage3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
a2_ff1 <= 'd0;
b2_ff1 <= 'd0;
a3_ff1 <= 'd0;
b3_ff1 <= 'd0;
a3_ff2 <= 'd0;
b3_ff2 <= 'd0;
a4_ff1 <= 'd0;
b4_ff1 <= 'd0;
a4_ff2 <= 'd0;
b4_ff2 <= 'd0;
a4_ff3 <= 'd0;
b4_ff3 <= 'd0;
end
else begin
a2_ff1 <= a2;
b2_ff1 <= b2;
a3_ff1 <= a3;
b3_ff1 <= b3;
a3_ff2 <= a3_ff1;
b3_ff2 <= b3_ff1;
a4_ff1 <= a4;
b4_ff1 <= b4;
a4_ff2 <= a4_ff1;
b4_ff2<= b4_ff1;
a4_ff3 <= a4_ff2;
b4_ff3 <= b4_ff2;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
s1_ff1 <= 'd0;
s1_ff2 <= 'd0;
s1_ff3 <= 'd0;
s2_ff1 <= 'd0;
s2_ff2 <= 'd0;
s3_ff1 <= 'd0;
end
else begin
s1_ff1 <= s1;
s1_ff2 <= s1_ff1;
s1_ff3 <= s1_ff2;
s2_ff1 <= s2;
s2_ff2 <= s2_ff1;
s3_ff1 <= s3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c1 <= 1'b0;
s1 <= 'd0;
end
else if (i_en) begin
{c1, s1} <= a1 + b1;
end
else begin
c1 <= c1;
s1 <= s1;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c2 <= 1'b0;
s2 <= 'd0;
end
else if (stage1) begin
{c2, s2} <= a2_ff1 + b2_ff1 + c1;
end
else begin
c2 <= c2;
s2 <= s2;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c3 <= 1'b0;
s3 <= 'd0;
end
else if (stage2) begin
{c3, s3} <= a3_ff2 + b3_ff2 + c2;
end
else begin
c3 <= c3;
s3 <= s3;
end
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
c4 <= 1'b0;
s4 <= 'd0;
end
else if (stage3) begin
{c4, s4} <= a4_ff3 + b4_ff3 + c3;
end
else begin
c4 <= c4;
s4 <= s4;
end
end
assign result = {c4, s4, s3_ff1, s2_ff2, s1_ff3};
endmodule |
square_wave | The module is a simple yet effective generator designed to produce square wave signals with variable frequency. It takes an input clock signal and a frequency value, and outputs a square wave signal toggling at the specified frequency.
Module name:
square_wave
Input ports:
clk: Clock signal that drives the module.
[7:0]freq: Frequency control, specifying how often the square wave toggles.
Output ports:
wave_out: Square wave output signal.
Internal Registers:
count (reg [7:0]): Counter register used to track cycles between wave toggles.
Implementation:
Counter Operation:
The count register increments on each rising edge of the clk.
When count reaches (freq - 1), the count is reset to 0 and wave_out is toggled (i.e., flipped from 0 to 1 or from 1 to 0).
If count has not reached freq, it simply increments by one on the next clock cycle.
Square Wave Generation:
The module produces a square wave by flipping the wave_out signal at the rate determined by freq.
The higher the freq value, the slower the square wave toggles (i.e., the lower the output frequency), and vice versa.
| [
{
"content": "module square_wave_tb;\n\n reg clk_tb = 0; \n reg [8:0] freq_tb = 8'b0000100; \n wire wave_out_tb; \n integer ones_count = 0; // Counter for consecutive ones\n integer error = 0; // Error flag\n\n square_wave square_wave_inst (\n .clk(clk_tb),\n .freq(freq_tb),\n .wave_out(wave_out_tb)\n );\n\n initial begin\n // Monitor output\n // $monitor(\"Time: %0t | Clock: %b | Frequency: %d | Square Wave Output: %b | Error: %d\", $time, clk_tb, freq_tb, wave_out_tb, error);\n\n // Simulate for a certain time\n repeat (200) begin\n if (wave_out_tb == 1) begin\n ones_count = ones_count + 1;\n if (ones_count > 8) begin\n $display(\"Error: More than 8 consecutive ones detected at time %0t\", $time);\n error = 1; // Set error flag\n $finish; // Stop the simulation\n end\n end else begin\n ones_count = 0;\n end\n #5; // Time delay between clock cycles\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"===========Error===========\");\n $fatal;\n end\n\n $finish; // Finish the simulation\n end\n\n always #5 clk_tb = ~clk_tb;\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = square_wave\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module square_wave(
input clk,
input [7:0] freq,
output reg wave_out
);
reg [7:0] count;
initial begin
wave_out = 0;
count = 0;
end
always @(posedge clk) begin
if(count == freq - 1 ) begin
count <= 0;
wave_out <= ~wave_out ;
end else begin
count <= count + 1;
end
end
endmodule |
div_16bit | Implement a 16-bit divider module, the dividend is 16-bit and the divider is 8-bit in combinational logic. Extract the higher bits of the dividend, matching the bit width of the divisor. Compare these bits with the divisor: if the dividend bits are greater, set the quotient to 1, otherwise set it to 0, and use the difference as the remainder. Concatenate the remainder with the highest remaining 1-bit of the dividend, and repeat the process until all dividend bits are processed.
Module name:
div_16bit
Input ports:
A: 16-bit dividend.
B: 8-bit divisor.
Output ports:
result: 16-bit quotient.
odd: 16-bit remainder.
Implementation:
The module uses two always blocks to perform the division operation.
The first always block is a combinational block triggered by any change in the input values A and B. It updates the values of two registers, a_reg and b_reg, with the values of A and B, respectively.
The second always block is also a combinational block triggered by any change in the input values A and B.
| [
{
"content": "`timescale 1ns/1ps\nmodule tb_division();\n\nreg [15:0] A;\nreg [7:0] B;\nwire [15:0] result;\nwire [15:0] odd;\n\ninteger i; \ninteger error = 0; \nreg [15:0] expected_result;\nreg [15:0] expected_odd;\ninitial begin\n for (i = 0; i < 100; i = i + 1) begin\n A = $urandom_range(1'b0, 16'b1111_1111_1111_1111);\n B = $urandom_range(1'b1, 8'b1111_1111);\n expected_result = A/B;\n expected_odd = A%B;\n #10; \n error = (expected_odd != odd || expected_result != result) ? error+1 : error;\n if (expected_odd != odd || expected_result != result) begin\n end\n $display(\"Failed testcase: A = %d, B = %d\", A, B);\n end\n \n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /100 failures===========\", error);\n $fatal;\n end\n \n $finish;\nend\n\ndiv_16bit uut (.A(A), .B(B), .result(result), .odd(odd));\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = div_16bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module div_16bit(
input wire [15:0] A,
input wire [7:0] B,
output wire [15:0] result,
output wire [15:0] odd
);
reg [15:0] a_reg;
reg [15:0] b_reg;
reg [31:0] tmp_a;
reg [31:0] tmp_b;
integer i;
always@(*) begin
a_reg = A;
b_reg = B;
end
always@(*) begin
begin
tmp_a = {16'b0, a_reg};
tmp_b = {b_reg, 16'b0};
for(i = 0;i < 16;i = i+1) begin
tmp_a = tmp_a << 1;
if (tmp_a >= tmp_b) begin
tmp_a = tmp_a - tmp_b + 1;
end
else begin
tmp_a = tmp_a;
end
end
end
end
assign odd = tmp_a[31:16];
assign result = tmp_a[15:0];
endmodule |
LIFObuffer | A Last-In-First-Out (LIFO) buffer for temporary data storage. This 4-bit wide buffer can hold up to 4 entries, allowing for push and pop operations controlled by read/write (RW) signals.
Module name:
LIFObuffer
Input ports:
dataIn [3:0]: 4-bit input data to be pushed onto the buffer.
RW: Read/Write control signal (1 for read, 0 for write).
EN: Enable signal to activate buffer operations.
Rst: Active high reset signal to initialize the buffer.
Clk: Clock signal for synchronous operations.
Output ports:
EMPTY: Flag indicating whether the buffer is empty.
FULL: Flag indicating whether the buffer is full.
dataOut [3:0]: 4-bit output data retrieved from the buffer.
Implementation:
The buffer uses a stack memory array (stack_mem) to store the data. A stack pointer (SP) tracks the current position in the stack.
On the rising edge of the clock (Clk), if the enable (EN) signal is high:
If the reset (Rst) signal is high, the stack is cleared, the stack pointer is set to 4 (indicating an empty buffer), and all memory locations are initialized to 0.
If the reset signal is low, the buffer checks if it is full or empty and processes data accordingly:
If RW is low (write operation) and the buffer is not full, data from dataIn is pushed onto the stack, and the stack pointer is decremented.
If RW is high (read operation) and the buffer is not empty, data is popped from the stack into dataOut, the corresponding stack memory is cleared, and the stack pointer is incremented.
Flags for EMPTY and FULL are updated based on the stack pointer status.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\n\nmodule LIFObuffer_tb;\n\n// Inputs\nreg [3:0] dataIn;\nreg RW;\nreg EN;\nreg Rst;\nreg Clk;\n\n// Outputs\nwire [3:0] dataOut;\nwire EMPTY;\nwire FULL;\n\n// Instantiate the Unit Under Test (UUT)\nLIFObuffer uut (\n .dataIn(dataIn),\n .dataOut(dataOut),\n .RW(RW),\n .EN(EN),\n .Rst(Rst),\n .EMPTY(EMPTY),\n .FULL(FULL),\n .Clk(Clk)\n);\ninteger error = 0;\ninitial begin\n // Initialize Inputs\n dataIn = 4'h0;\n RW = 1'b0;\n EN = 1'b0;\n Rst = 1'b1;\n Clk = 1'b0;\n\n // Wait 100 ns for global reset to finish\n #100;\n\n // Add stimulus here\n EN = 1'b1;\n Rst = 1'b1;\n #40;\n Rst = 1'b0;\n RW = 1'b0;\n $display(\"RW = %d at time = %d\", RW, $time);\n dataIn = 4'h0;\n $display(\"dataIn = %d at time = %d\", dataIn, $time);\n #20;\n dataIn = 4'h2;\n $display(\"dataIn = %d at time = %d\", dataIn, $time);\n #20;\n dataIn = 4'h4;\n $display(\"dataIn = %d at time = %d\", dataIn, $time);\n #20;\n dataIn = 4'h6;\n $display(\"dataIn = %d at time = %d\", dataIn, $time);\n #20;\n RW = 1'b1;\n $display(\"RW = %d at time = %d\", RW, $time);\n #5;\n error = (FULL && !EMPTY) ? error : error+1;\n if (!FULL || EMPTY) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n #20;\n error = (dataOut==6) ? error : error+1;\n if (dataOut != 6) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n #20;\n error = (dataOut==4) ? error : error+1;\n if (dataOut != 4) begin\n $display(\"Failed testcase: at time = %d\", $time);\n end\n\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d/20 failures ===========\", error);\n $fatal;\n end\n $finish;\nend\n\nalways #10 Clk = ~Clk;\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = LIFObuffer\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module LIFObuffer (
input [3:0] dataIn,
input RW,
input EN,
input Rst,
input Clk,
output reg EMPTY,
output reg FULL,
output reg [3:0] dataOut
);
reg [3:0] stack_mem[0:3];
reg [2:0] SP;
integer i;
always @ (posedge Clk) begin
if (EN == 0) begin
// Do nothing if EN is 0
end else begin
if (Rst == 1) begin
SP = 3'd4;
EMPTY = SP[2];
dataOut = 4'h0;
for (i = 0; i < 4; i = i + 1) begin
stack_mem[i] = 0;
end
end else if (Rst == 0) begin
FULL = SP ? 0 : 1;
EMPTY = SP[2];
dataOut = 4'hx;
if (FULL == 1'b0 && RW == 1'b0) begin
SP = SP - 1'b1;
FULL = SP ? 0 : 1;
EMPTY = SP[2];
stack_mem[SP] = dataIn;
end else if (EMPTY == 1'b0 && RW == 1'b1) begin
dataOut = stack_mem[SP];
stack_mem[SP] = 0;
SP = SP + 1;
FULL = SP ? 0 : 1;
EMPTY = SP[2];
end else begin
// Do nothing if neither condition is met
end
end else begin
// Do nothing if neither condition is met
end
end
end
endmodule
|
multi_pipe_4bit | Implement the design of 4bit unsigned number pipeline multiplier. It consists of two levels of registers to store intermediate values and control the multiplication process.
Module name:
multi_pipe_4bit
Module parameter:
size = 4
Input ports:
clk: Clock signal used for synchronous operation.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
mul_a: Input signal representing the multiplicand with a data width of "size" bits.
mul_b: Input signal representing the multiplier with a data width of "size" bits.
Output ports:
mul_out: Product output signal with a data width of 2*size bits.
Implementation:
Extension of input signals:
The input signals (mul_a and mul_b) are extended by adding "size" number of zero bits at the most significant bit positions.
Multiplication operation:
The module uses a generate block to perform multiplication for each bit position of the multiplier (mul_b) and generate the partial products.
For each bit position i from 0 to size-1, the partial product is calculated as follows:
If the corresponding bit in the multiplier is 1, the multiplicand is left-shifted by i positions.
If the corresponding bit in the multiplier is 0, the partial product is set to 0 ('d0).
Add of partial products:
The module uses registers to store the intermediate sum values.
On the positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module performs add operations.
If the reset signal (rst_n) is low, indicating a reset condition, the registers are set to 0.
If the reset signal (rst_n) is high, the registers are updated with the sum of the corresponding partial products.
Final product calculation:
On the positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module calculates the final product.
If the reset signal (rst_n) is low, indicating a reset condition, the product output (mul_out) is set to 0.
If the reset signal (rst_n) is high, the product output (mul_out) is updated with the sum of registers.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule multi_pipe_tb;\n reg clk;\n reg rst_n;\n reg [3:0] mul_a;\n reg [3:0] mul_b;\n wire [7:0] mul_out;\n wire signed [7:0] perfect = mul_a*mul_b;\n // Instantiate the DUT (Design Under Test)\n multi_pipe_4bit #(.size(4)) dut (\n .clk(clk),\n .rst_n(rst_n),\n .mul_a(mul_a),\n .mul_b(mul_b),\n .mul_out(mul_out)\n );\n\n // Generate clock\n always #5 clk = ~clk;\n\n integer fail_count =0;\n integer i=0;\n initial begin\n // Initialize inputs\n clk = 0;\n rst_n = 0;\n mul_a = 4'b0;\n mul_b = 4'b0;\n\n // Wait for a few clock cycles for reset to settle\n #10;\n\n // Apply reset\n rst_n = 1;\n \n // Perform test case\n for (i = 0; i < 100; i = i + 1) begin\n mul_a = $random;\n mul_b = $random;\n #10;\n // without pipeline\n fail_count = (perfect == mul_out)? fail_count+1:fail_count;\n if (perfect == mul_out) begin\n $display(\"Failed: Without pipeline: expect mul_out = %d, got mul_out = %d\", perfect, mul_out);\n end\n #20;\n fail_count = (perfect == mul_out)? fail_count:fail_count+1;\n if (perfect != mul_out) begin\n $display(\"Failed: With pipeline: expect mul_out = %d, got mul_out = %d\", perfect, mul_out);\n end\n end\n\n if (fail_count == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d / 100 failures===========\", fail_count);\n $fatal;\n end\n $finish;\n end\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = multi_pipe\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module multi_pipe_4bit#(
parameter size = 4
)(
input clk ,
input rst_n ,
input [size-1:0] mul_a ,
input [size-1:0] mul_b ,
output reg [size*2-1:0] mul_out
);
parameter N = 2 * size;
reg [N-1:0] sum_tmp1 ;
reg [N-1:0] sum_tmp2 ;
wire [N-1:0] mul_a_extend ;
wire [N-1:0] mul_b_extend ;
wire [N-1:0] mul_result[size-1:0] ;
genvar i;
generate
for(i = 0; i < size; i = i + 1) begin:add
assign mul_result[i] = mul_b[i] ? mul_a_extend << i : 'd0;
end
endgenerate
assign mul_a_extend = {{size{1'b0}}, mul_a};
assign mul_b_extend = {{size{1'b0}}, mul_b};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sum_tmp1 <= 'd0;
sum_tmp2 <= 'd0;
end
else begin
sum_tmp1 <= mul_result[0] + mul_result[1];
sum_tmp2 <= mul_result[2] + mul_result[3];
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mul_out <= 'd0;
end
else begin
mul_out <= sum_tmp1 + sum_tmp2;
end
end
endmodule
|
right_shifter | Implement a right shifter. The module performs an 8-bit right shift on a 1-bit input by first initializing the q register to 0. On each rising edge of the clock, the module shifts the contents of the q register to the right by one bit and inserts the new input bit d into the most significant position of the register.
Module name:
right_shifter
Input ports:
clk: Clock signal used for synchronous operation.
d: Input signal to be right-shifted.
Output ports:
q: Output signal representing the result of the right shift operation.
Implementation:
The register is defined as reg [7:0] q and initialized to 0 using the initial statement. The value of q is right-shifted by 1 bit using the >> operator: q <= (q >> 1).
The most significant bit (q[7]) of the register is assigned the value of the input signal (d): q[7] <= d.
| [
{
"content": "`timescale 1ns/1ns\nmodule right_shifter_tb;\n reg clk;\n reg d;\n wire [7:0] q;\n\n // Instantiate the DUT (Design Under Test)\n right_shifter dut (\n .clk(clk),\n .d(d),\n .q(q)\n );\n\n // Generate clock\n always #5 clk = ~clk;\n\n initial begin\n // Initialize inputs\n clk = 0;\n d = 0;\n #20;\n d = 1;\n #10;\n d = 0;\n #10;\n d = 1;\n #10;\n d = 0;\n #10;\n d = 1;\n #10;\n d = 1;\n #10;\n d = 1;\n #10;\n \n // Check the output\n if(q==8'b11101010) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Failed===========\");\n $fatal;\n end\n // Finish simulation\n $finish;\n end\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = right_shifter\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module right_shifter(clk, q,d);
input clk;
input d;
output [7:0] q;
reg [7:0] q;
initial q = 0;
always @(posedge clk)
begin
q <= (q >> 1);
q[7] <= d;
end
endmodule |
freq_divbyodd | A frequency divider that divides the input clock frequency by odd numbers. The module generates a divided clock output by an odd divisor value provided as a parameter.
Module name:
freq_divbyodd
Input ports:
clk: Input clock signal.
rst_n: Active low reset signal that initializes the divider.
Output ports:
clk_div: Divided clock output.
Implementation:
The module divides the input clock frequency by an odd number defined by the parameter NUM_DIV, which defaults to 5.
Two counters, cnt1 and cnt2, are used for tracking the rising and falling edges of the clock. Each counter counts up to NUM_DIV - 1.
Two separate clock dividers, clk_div1 and clk_div2, are used for positive and negative edges of the clock, respectively. These are toggled when the counters reach half of NUM_DIV.
The final divided clock output, clk_div, is derived by logically OR-ing clk_div1 and clk_div2 to account for both clock edges.
The active low reset signal rst_n initializes the counters and the clock divider outputs.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\nmodule testb_div_odd;\n // Inputs\n reg clk;\n reg rst_n;\n // Outputs\n wire clk_div;\n \n // Instantiate the Unit Under Test (UUT)\n freq_divbyodd uut (\n .clk(clk), \n .rst_n(rst_n), \n .clk_div(clk_div)\n );\n always #5 clk = ~clk;\n \n integer error = 0;\n integer expected_value = 1;\n integer i;\n initial begin\n // Initialize Inputs\n clk = 1;\n rst_n = 0;\n # 10 rst_n = 1;\n #120;\n\n $finish;\n end\n initial begin\n // $monitor(\"clk=%d, clk_div=%d\",clk,clk_div);\n #15;\n for (i = 1; i < 20; i = i + 1) begin\n if (clk_div !== expected_value) begin\n error = error + 1; \n $display(\"Failed testcase: clk = %d\", i);\n end\n\n if (i < 5) expected_value = 1; \n else if (i < 10) expected_value = 0; \n else if (i < 15) expected_value = 1; \n else expected_value = 0; \n #5;\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d/20 failures ===========\", error);\n $fatal;\n end\n end\nendmodule\n ",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = freq_divbyodd\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module freq_divbyodd(
clk,
rst_n,
clk_div
);
input clk;
input rst_n;
output clk_div;
reg clk_div;
parameter NUM_DIV = 5;
reg[2:0] cnt1;
reg[2:0] cnt2;
reg clk_div1, clk_div2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt1 <= 0;
else if(cnt1 < NUM_DIV - 1)
cnt1 <= cnt1 + 1'b1;
else
cnt1 <= 0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
clk_div1 <= 1'b1;
else if(cnt1 < NUM_DIV / 2)
clk_div1 <= 1'b1;
else
clk_div1 <= 1'b0;
always @(negedge clk or negedge rst_n)
if(!rst_n)
cnt2 <= 0;
else if(cnt2 < NUM_DIV - 1)
cnt2 <= cnt2 + 1'b1;
else
cnt2 <= 0;
always @(negedge clk or negedge rst_n)
if(!rst_n)
clk_div2 <= 1'b1;
else if(cnt2 < NUM_DIV / 2)
clk_div2 <= 1'b1;
else
clk_div2 <= 1'b0;
assign clk_div = clk_div1 | clk_div2;
endmodule |
barrel_shifter | Module name:
barrel_shifter
Function:
A barrel shifter for rotating bits efficiently. This 8-bit barrel shifter takes an 8-bit input and shifts or rotates the bits based on a 3-bit control signal.
Input ports:
in [7:0]: 8-bit input to be shifted.
ctrl [2:0]: 3-bit control signal that determines how many positions to shift. The control signal specifies the amount of shift, where each bit indicates a shift by 1, 2, or 4 positions.
Output ports:
out [7:0]: 8-bit shifted output.
Implementation:
The barrel shifter shifts the input `in` based on the value of the `ctrl` signal. The shifting happens in stages, where each stage shifts by 4, 2, or 1 position, as controlled by `ctrl[2]`, `ctrl[1]`, and `ctrl[0]`, respectively.
The shifts are achieved using a series of 2-to-1 multiplexers (`mux2X1`) that select between the shifted input and the original input. Each stage of multiplexers performs the shift, and the result is passed to the next stage for further shifting if required.
- When `ctrl[2]` is high, the input is shifted by 4 positions.
- When `ctrl[1]` is high, the intermediate result is shifted by 2 positions.
- When `ctrl[0]` is high, the intermediate result is shifted by 1 position.
The `mux2X1` submodule is used to select between two input values based on the `sel` signal, determining which bit is used in the shifted output at each stage.
Give me the complete code. | [
{
"content": "module barrel_shifter_tb;\n reg [7:0] in;\n reg [2:0] ctrl;\n wire [7:0] out; \n \nbarrel_shifter uut(.in(in), .ctrl(ctrl), .out(out));\n\ninteger error = 0;\n\ninitial \n begin\n in= 8'd0; ctrl=3'd0; //no shift\n #10 in=8'd128; ctrl= 3'd4; //shift 4 bit\n #10 error = (out==8)?error : error+1;\n if (out != 8) begin\n $display(\"Failed testcase: in = %d, ctrl = %d\", in, ctrl);\n end\n #10 in=8'd128; ctrl= 3'd2; //shift 2 bit\n #10 error = (out==32)?error : error+1;\n if (out != 32) begin\n $display(\"Failed testcase: in = %d, ctrl = %d\", in, ctrl);\n end\n #10 in=8'd128; ctrl= 3'd1; //shift by 1 bit\n #10 error = (out==64)?error : error+1;\n if (out != 64) begin\n $display(\"Failed testcase: in = %d, ctrl = %d\", in, ctrl);\n end\n #10 in=8'd255; ctrl= 3'd7; //shift by 7bit\n #10 error = (out==1)?error : error+1;\n if (out != 1) begin\n $display(\"Failed testcase: in = %d, ctrl = %d\", in, ctrl);\n end\n // end\n // initial begin\n // $monitor(\"Input=%d, Control=%d, Output=%d\",in,ctrl,out);\n // end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d failures ===========\", error);\n $fatal;\n end\n $finish;\n end\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = barrel_shifter\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module barrel_shifter (in, ctrl, out);
input [7:0] in;
input [2:0] ctrl;
output [7:0] out;
wire [7:0] x,y;
//4bit shift right
mux2X1 ins_17 (.in0(in[7]),.in1(1'b0),.sel(ctrl[2]),.out(x[7]));
mux2X1 ins_16 (.in0(in[6]),.in1(1'b0),.sel(ctrl[2]),.out(x[6]));
mux2X1 ins_15 (.in0(in[5]),.in1(1'b0),.sel(ctrl[2]),.out(x[5]));
mux2X1 ins_14 (.in0(in[4]),.in1(1'b0),.sel(ctrl[2]),.out(x[4]));
mux2X1 ins_13 (.in0(in[3]),.in1(in[7]),.sel(ctrl[2]),.out(x[3]));
mux2X1 ins_12 (.in0(in[2]),.in1(in[6]),.sel(ctrl[2]),.out(x[2]));
mux2X1 ins_11 (.in0(in[1]),.in1(in[5]),.sel(ctrl[2]),.out(x[1]));
mux2X1 ins_10 (.in0(in[0]),.in1(in[4]),.sel(ctrl[2]),.out(x[0]));
//2 bit shift right
mux2X1 ins_27 (.in0(x[7]),.in1(1'b0),.sel(ctrl[1]),.out(y[7]));
mux2X1 ins_26 (.in0(x[6]),.in1(1'b0),.sel(ctrl[1]),.out(y[6]));
mux2X1 ins_25 (.in0(x[5]),.in1(x[7]),.sel(ctrl[1]),.out(y[5]));
mux2X1 ins_24 (.in0(x[4]),.in1(x[6]),.sel(ctrl[1]),.out(y[4]));
mux2X1 ins_23 (.in0(x[3]),.in1(x[5]),.sel(ctrl[1]),.out(y[3]));
mux2X1 ins_22 (.in0(x[2]),.in1(x[4]),.sel(ctrl[1]),.out(y[2]));
mux2X1 ins_21 (.in0(x[1]),.in1(x[3]),.sel(ctrl[1]),.out(y[1]));
mux2X1 ins_20 (.in0(x[0]),.in1(x[2]),.sel(ctrl[1]),.out(y[0]));
//1 bit shift right
mux2X1 ins_07 (.in0(y[7]),.in1(1'b0),.sel(ctrl[0]),.out(out[7]));
mux2X1 ins_06 (.in0(y[6]),.in1(y[7]),.sel(ctrl[0]),.out(out[6]));
mux2X1 ins_05 (.in0(y[5]),.in1(y[6]),.sel(ctrl[0]),.out(out[5]));
mux2X1 ins_04 (.in0(y[4]),.in1(y[5]),.sel(ctrl[0]),.out(out[4]));
mux2X1 ins_03 (.in0(y[3]),.in1(y[4]),.sel(ctrl[0]),.out(out[3]));
mux2X1 ins_02 (.in0(y[2]),.in1(y[3]),.sel(ctrl[0]),.out(out[2]));
mux2X1 ins_01 (.in0(y[1]),.in1(y[2]),.sel(ctrl[0]),.out(out[1]));
mux2X1 ins_00 (.in0(y[0]),.in1(y[1]),.sel(ctrl[0]),.out(out[0]));
endmodule
module mux2X1( in0,in1,sel,out);
input in0,in1;
input sel;
output out;
assign out=(sel)?in1:in0;
endmodule |
comparator_3bit | Implement a module of a 3-bit comparator for comparing binary numbers.
Module name:
comparator_3bit
Input ports:
A [2:0]: First 3-bit input operand (the first binary number to compare).
B [2:0]: Second 3-bit input operand (the second binary number to compare).
Output ports:
A_greater: 1-bit output indicating if A is greater than B.
A_equal: 1-bit output indicating if A is equal to B.
A_less: 1-bit output indicating if A is less than B.
Implementation:
Comparison Logic: The module compares the two 3-bit binary numbers A and B using combinational logic.
- The outputs A_greater, A_equal, and A_less are determined based on the comparison of A and B.
- A_greater is set to 1 if A > B, A_equal is set to 1 if A == B, and A_less is set to 1 if A < B.
Output Encoding: The outputs are mutually exclusive, meaning only one of the three outputs will be high (1) at any given time, based on the comparison results.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [2:0] A; // Input A (3 bits)\n reg [2:0] B; // Input B (3 bits)\n wire A_greater; \n wire A_equal; \n wire A_less; \n integer i; \n integer error = 0; \n\n comparator_3bit uut (\n .A(A),\n .B(B),\n .A_greater(A_greater),\n .A_equal(A_equal),\n .A_less(A_less)\n );\n\n\n initial begin\n\n for (i = 0; i < 100; i = i + 1) begin\n // Generate random 3-bit inputs\n A = $random % 8;\n B = $random % 8;\n\n // Wait for the operation to complete\n #10;\n\n // Calculate expected results\n if ((A > B && !A_greater) || (A == B && !A_equal) || (A < B && !A_less)) begin\n error = error + 1;\n $display(\"Failed: A = %b, B = %b, A_greater = %b, A_equal = %b, A_less = %b\",\n A, B, A_greater, A_equal, A_less);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = comparator_3bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module comparator_3bit (
input [2:0] A,
input [2:0] B,
output A_greater,
output A_equal,
output A_less
);
assign A_greater = (A > B) ? 1'b1 : 1'b0;
assign A_equal = (A == B) ? 1'b1 : 1'b0;
assign A_less = (A < B) ? 1'b1 : 1'b0;
endmodule |
adder_32bit | Implement a module of a carry-lookahead 32-bit adder that uses the Carry-Lookahead Adder (CLA) architecture.
Module name:
adder_32bit
Input ports:
A[32:1]: 32-bit input operand A.
B[32:1]: 32-bit input operand B.
Output ports:
S[32:1]: 32-bit output representing the sum of A and B.
C32: Carry-out output.
Implementation:
The top module adder_32bit consists of several instances of the 16 bit CLA block you design.
| [
{
"content": "`timescale 1ns/1ns\nmodule adder32_tb;\n \n reg [31:0] A;\n reg [31:0] B;\n wire [31:0] S;\n wire C32;\n \n integer i; \n integer error = 0; \n reg [33:0] expected_sum; \n \n // Instantiate the module\n adder_32bit uut (\n .A(A), \n .B(B), \n .S(S), \n .C32(C32)\n );\n \n // Randomize inputs and check output\n initial begin\n for (i = 0; i < 100; i = i + 1) begin\n A = $random;\n B = $random;\n #10; \n // Calculate expected sum and carry out\n expected_sum = A + B;\n error = (S !== expected_sum[31:0] || C32 !== expected_sum[32]) ? error+1 : error; \n end\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /100 failures===========\", error);\n $fatal;\n end\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = adder_32bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module adder_32bit(A,B,S,C32);
input [32:1] A;
input [32:1] B;
output [32:1] S;
output C32;
wire px1,gx1,px2,gx2;
wire c16;
CLA_16 CLA1(
.A(A[16:1]),
.B(B[16:1]),
.c0(0),
.S(S[16:1]),
.px(px1),
.gx(gx1)
);
CLA_16 CLA2(
.A(A[32:17]),
.B(B[32:17]),
.c0(c16),
.S(S[32:17]),
.px(px2),
.gx(gx2)
);
assign c16 = gx1 ^ (px1 && 0), //c0 = 0
C32 = gx2 ^ (px2 && c16);
endmodule
module CLA_16(A,B,c0,S,px,gx);
input [16:1] A;
input [16:1] B;
input c0;
output gx,px;
output [16:1] S;
wire c4,c8,c12;
wire Pm1,Gm1,Pm2,Gm2,Pm3,Gm3,Pm4,Gm4;
adder_4 adder1(
.x(A[4:1]),
.y(B[4:1]),
.c0(c0),
.c4(),
.F(S[4:1]),
.Gm(Gm1),
.Pm(Pm1)
);
adder_4 adder2(
.x(A[8:5]),
.y(B[8:5]),
.c0(c4),
.c4(),
.F(S[8:5]),
.Gm(Gm2),
.Pm(Pm2)
);
adder_4 adder3(
.x(A[12:9]),
.y(B[12:9]),
.c0(c8),
.c4(),
.F(S[12:9]),
.Gm(Gm3),
.Pm(Pm3)
);
adder_4 adder4(
.x(A[16:13]),
.y(B[16:13]),
.c0(c12),
.c4(),
.F(S[16:13]),
.Gm(Gm4),
.Pm(Pm4)
);
assign c4 = Gm1 ^ (Pm1 & c0),
c8 = Gm2 ^ (Pm2 & Gm1) ^ (Pm2 & Pm1 & c0),
c12 = Gm3 ^ (Pm3 & Gm2) ^ (Pm3 & Pm2 & Gm1) ^ (Pm3 & Pm2 & Pm1 & c0);
assign px = Pm1 & Pm2 & Pm3 & Pm4,
gx = Gm4 ^ (Pm4 & Gm3) ^ (Pm4 & Pm3 & Gm2) ^ (Pm4 & Pm3 & Pm2 & Gm1);
endmodule
module adder_4(x,y,c0,c4,F,Gm,Pm);
input [4:1] x;
input [4:1] y;
input c0;
output c4,Gm,Pm;
output [4:1] F;
wire p1,p2,p3,p4,g1,g2,g3,g4;
wire c1,c2,c3;
adder adder1(
.X(x[1]),
.Y(y[1]),
.Cin(c0),
.F(F[1]),
.Cout()
);
adder adder2(
.X(x[2]),
.Y(y[2]),
.Cin(c1),
.F(F[2]),
.Cout()
);
adder adder3(
.X(x[3]),
.Y(y[3]),
.Cin(c2),
.F(F[3]),
.Cout()
);
adder adder4(
.X(x[4]),
.Y(y[4]),
.Cin(c3),
.F(F[4]),
.Cout()
);
CLA CLA(
.c0(c0),
.c1(c1),
.c2(c2),
.c3(c3),
.c4(c4),
.p1(p1),
.p2(p2),
.p3(p3),
.p4(p4),
.g1(g1),
.g2(g2),
.g3(g3),
.g4(g4)
);
assign p1 = x[1] ^ y[1],
p2 = x[2] ^ y[2],
p3 = x[3] ^ y[3],
p4 = x[4] ^ y[4];
assign g1 = x[1] & y[1],
g2 = x[2] & y[2],
g3 = x[3] & y[3],
g4 = x[4] & y[4];
assign Pm = p1 & p2 & p3 & p4,
Gm = g4 ^ (p4 & g3) ^ (p4 & p3 & g2) ^ (p4 & p3 & p2 & g1);
endmodule
module CLA(c0,c1,c2,c3,c4,p1,p2,p3,p4,g1,g2,g3,g4);
input c0,g1,g2,g3,g4,p1,p2,p3,p4;
output c1,c2,c3,c4;
assign c1 = g1 ^ (p1 & c0),
c2 = g2 ^ (p2 & g1) ^ (p2 & p1 & c0),
c3 = g3 ^ (p3 & g2) ^ (p3 & p2 & g1) ^ (p3 & p2 & p1 & c0),
c4 = g4^(p4&g3)^(p4&p3&g2)^(p4&p3&p2&g1)^(p4&p3&p2&p1&c0);
endmodule
module adder(X,Y,Cin,F,Cout);
input X,Y,Cin;
output F,Cout;
assign F = X ^ Y ^ Cin;
assign Cout = (X ^ Y) & Cin | X & Y;
endmodule |
adder_bcd | Implement a module of a 4-bit BCD adder for decimal arithmetic operations.
Module name:
adder_bcd
Input ports:
A [3:0]: First BCD input (4-bit, representing a decimal digit from 0 to 9).
B [3:0]: Second BCD input (4-bit, representing a decimal digit from 0 to 9).
Cin: Carry-in input (1-bit).
Output ports:
Sum [3:0]: 4-bit output representing the sum of the two BCD inputs, corrected to be a valid BCD digit (0–9).
Cout: Carry-out output (1-bit), used when the sum exceeds the decimal value of 9.
Implementation:
Addition: The module performs binary addition of A, B, and Cin.
BCD Correction: If the sum exceeds 9 (binary 1001), a correction of 6 (binary 0110) is added to the sum. This correction ensures that the result is within the BCD range.
Carry Generation: If the result of the addition exceeds 9, a carry-out (Cout) is generated, signaling that the BCD sum exceeds a single decimal digit.
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [3:0] A; // First BCD input (4 bits)\n reg [3:0] B; // Second BCD input (4 bits)\n reg Cin; // Carry-in input (1 bit)\n wire [3:0] Sum; // BCD sum output (4 bits)\n wire Cout; // Carry-out output (1 bit)\n\n integer i; \n integer error = 0; \n reg [4:0] expected_sum; \n\n\n adder_bcd uut (\n .A(A),\n .B(B),\n .Cin(Cin),\n .Sum(Sum),\n .Cout(Cout)\n );\n\n initial begin\n for (i = 0; i < 100; i = i + 1) begin\n A = $random % 10; \n B = $random % 10;\n Cin = $random % 2;\n if (A > 9) A = A % 10;\n if (B > 9) B = B % 10;\n // Wait for the operation to complete\n #10;\n\n expected_sum = A + B + Cin;\n\n // Adjust for BCD overflow (sum greater than 9)\n if (expected_sum > 9) begin\n expected_sum = expected_sum + 6; // Correct the sum for BCD\n end\n\n // Check the result of the BCD adder\n if ({Cout, Sum} !== expected_sum) begin\n error = error + 1;\n $display(\"Failed: A = %d, B = %d, Cin = %d | Expected = %d, Got = %d, Cout = %d\", \n A, B, Cin, expected_sum, Sum, Cout);\n end\n end\n \n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = adder_bcd\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module adder_bcd (
input [3:0] A, // First BCD number (0-9)
input [3:0] B, // Second BCD number (0-9)
input Cin, // Input carry
output [3:0] Sum, // BCD sum (0-9)
output Cout // Output carry
);
wire [4:0] temp_sum; // Temporary 5-bit sum to store initial result
wire [3:0] corrected_sum; // Adjusted BCD sum
wire carry_out; // Corrected carry-out
// Step 1: Perform binary addition of A, B, and Cin
assign temp_sum = A + B + Cin;
// Step 2: If the sum is greater than 9, adjust the sum by adding 6
assign carry_out = (temp_sum > 9) ? 1 : 0; // If sum exceeds 9, set carry
assign corrected_sum = (temp_sum > 9) ? (temp_sum + 4'b0110) : temp_sum; // Add 6 to correct BCD
// Output the corrected sum and the carry
assign Sum = corrected_sum[3:0]; // The BCD sum is the lower 4 bits
assign Cout = carry_out; // Output the carry
endmodule
|
synchronizer | Implement a multi-bit MUX-based synchronizer, data_in will remain constant during the period when data_en is high, and data_en is high for at least 3 clk_b clock cycles. When the value of data_en is high, data can be synchronized. The data change frequency of data_in is very low. The change interval between two adjacent data is at least 10 clk_b clock cycles.
The clock clk_a is responsible for: input data_in is refer to clock a. enable signal data_en is refer to clock a.
The clock clk_b is responsible for the enable signal data_en delays two cycles, that is, two D flip-flops. This is done with reference to clock b. And the data is finally output dataout, and the output refers to clock b.
Module name:
synchronizer
Input ports:
clk_a: Clock signal A used for synchronous operations.
clk_b: Clock signal B used for synchronous operations.
arstn: Active-low reset signal A. Defined as 0 for reset and 1 for reset signal inactive.
brstn: Active-low reset signal B. Defined as 0 for reset and 1 for reset signal inactive.
data_in: Input data signal of size 4 bits.
data_en: Input enable signal that controls the selection operation.
Output ports:
dataout: Output data signal of size 4 bits.
Implementation:
Data Register:
The module includes a register, data_reg, to store the input data signal, data_in.
On the positive edge of clock signal A (clk_a) or the falling edge of reset signal A (arstn), the module updates the register. If the reset signal A (arstn) is low, indicating a reset condition, the register (data_reg) is set to 0. If the reset signal A (arstn) is high, the register (data_reg) is updated with the input data signal (data_in).
Enable Data Register:
The module includes a register, en_data_reg, to store the input enable signal, data_en.
On the positive edge of clock signal A (clk_a) or the falling edge of reset signal A (arstn), the module updates the register. If the reset signal A (arstn) is low, the register (en_data_reg) is set to 0. If the reset signal A (arstn) is high, the register (en_data_reg) is updated with the input enable signal (data_en).
Enable Control Registers:
The module includes two registers, en_clap_one and en_clap_two, to control the selection of the input data. On the positive edge of clock signal B (clk_b) or the falling edge of reset signal B (brstn), the module updates the registers. If the reset signal B (brstn) is low, indicating a reset condition, both registers (en_clap_one and en_clap_two) are set to 0.
If the reset signal B (brstn) is high, the registers (en_clap_one and en_clap_two) are updated based on the value of en_data_reg. The register en_clap_one is assigned the value of en_data_reg, and en_clap_two is assigned the previous value of en_clap_one.
Output Assignment:
On the positive edge of clock signal B (clk_b) or the falling edge of reset signal B (brstn), the module assigns the output data value. If the reset signal B (brstn) is low, indicating a reset condition, the output data (dataout) is set to 0. If the reset signal B (brstn) is high and the control signal (en_clap_two) is active, the output data (dataout) is assigned the value of the data register (data_reg). If the control signal (en_clap_two) is inactive, the output data (dataout) retains its previous value.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule testbench;\n // Inputs\n reg clk_a;\n reg clk_b;\n reg arstn;\n reg brstn;\n reg [3:0] data_in;\n reg data_en;\n\n // Outputs\n wire [3:0] dataout;\n\n // Instantiate the mux module\n synchronizer dut(\n .clk_a(clk_a),\n .clk_b(clk_b),\n .arstn(arstn),\n .brstn(brstn),\n .data_in(data_in),\n .data_en(data_en),\n .dataout(dataout)\n );\n\n // Clock generation\n always #5 clk_a = ~clk_a;\n always #10 clk_b = ~clk_b;\n\n integer error=0;\n initial begin\n clk_a = 0;\n clk_b = 0;\n arstn = 0;\n brstn = 0;\n data_en = 0;\n data_in = 0;\n \n #20 arstn = 1; // Release reset\n #5 brstn = 1; \n #50 data_in = 4; // Set data_in to 4\n #10 data_en = 1; // Enable data\n $display(dataout);\n #100;\n $display(\"dataout = %d, expected = 4\", dataout);\n error = (dataout == 4)? error : error+1;\n #10 data_en = 0; // Disable data\n #100;\n #50 data_in = 7; // Set data_in to 7\n #10 data_en = 1; // Enable data\n $display(dataout);\n #80;\n $display(\"dataout = %d, expected = 7\", dataout);\n error = (dataout == 7)? error : error+1;\n #10 data_en = 0; // Disable data\n #100;\n #50;\n #20 arstn = 0; // Assert reset\n #100;\n #20 arstn = 1; // Release reset\n #50 data_in = 9; // Set data_in to 9\n #10 data_en = 1; // Enable data\n $display(dataout);\n #100;\n $display(\"dataout = %d, expected = 9\", dataout);\n error = (dataout == 9)? error : error+1;\n #10 data_en = 0; // Disable data\n #100;\n\n // Display results\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /3 failures===========\", error);\n $fatal;\n end\n $finish;\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = synchronizer\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module synchronizer(
input clk_a ,
input clk_b ,
input arstn ,
input brstn ,
input [3:0] data_in ,
input data_en ,
output reg [3:0] dataout
);
reg [3:0] data_reg;
always@(posedge clk_a or negedge arstn)
begin
if(!arstn) data_reg <= 0;
else data_reg <= data_in;
end
reg en_data_reg;
always@(posedge clk_a or negedge arstn)
begin
if(!arstn) en_data_reg <= 0;
else en_data_reg <= data_en;
end
reg en_clap_one; //1
reg en_clap_two; //2
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) en_clap_one <= 0;
else en_clap_one <= en_data_reg;
end
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) en_clap_two <= 0;
else en_clap_two <= en_clap_one;
end
always@(posedge clk_b or negedge brstn)
begin
if(!brstn) dataout <= 0;
else dataout <= (en_clap_two) ? data_reg : dataout;
end
endmodule
|
fixed_point_substractor | Implement a module of a fixed-point subtractor for precise arithmetic operations with fixed precision.
Module name:
fixed_point_subtractor
Parameterized values:
Q: Represents the number of fractional bits in the fixed-point representation. Defaults to 15.
N: Represents the total number of bits (both integer and fractional) used for inputs and outputs. Defaults to 32.
Input ports:
a [N-1:0]: First N-bit fixed-point input operand.
b [N-1:0]: Second N-bit fixed-point input operand.
Output ports:
c [N-1:0]: N-bit output representing the result of the fixed-point subtraction.
Internal registers:
res [N-1:0]: N-bit register used to store the result of the subtraction operation.
Implementation:
Same Sign Subtraction: When the signs of a and b are the same, their fractional and integer parts are subtracted. The sign of the result will be the same as the inputs.
Different Sign Subtraction:
If a is positive and b is negative, the absolute values of a and b are added. The result will have a positive sign if a is greater than b, and a negative sign otherwise.
If a is negative and b is positive, the same logic applies, with the result's sign depending on the relative sizes of a and b.
Handling Zero:
When the result is zero, the sign bit is explicitly set to 0 to handle this edge case.
Precision:
The fixed-point precision is defined by the parameters Q (fractional bits) and N (total bits). This ensures that the subtraction is performed accurately while maintaining the necessary precision for both integer and fractional parts.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\n\nmodule tb_fixed_point_subtractor;\n\n // Parameters\n parameter Q = 15;\n parameter N = 32;\n\n // Inputs\n reg [N-1:0] a;\n reg [N-1:0] b;\n\n // Output\n wire [N-1:0] c;\n integer error = 0;\n reg [N-1:0] expected_result;\n\n // Instantiate the fixed point subtractor module\n fixed_point_subtractor #(.Q(Q), .N(N)) uut (\n .a(a),\n .b(b),\n .c(c)\n );\n\n // Initial values for inputs\n initial begin\n\n\n for (integer i = 0; i < 100; i = i + 1) begin\n // Generate random N-bit inputs\n a = $random % (1 << N);\n b = $random % (1 << N);\n\n // Delay for the operation to complete\n #10;\n\n // Calculate expected results\n if (a[N-1] == b[N-1]) begin\n expected_result = a - b;\n end\n else if (a[N-1] == 0 && b[N-1] == 1) begin\n if (a[N-2:0] > b[N-2:0]) begin\n expected_result = a + b;\n end\n else begin\n expected_result = b - a;\n end\n end\n else begin\n if (a[N-2:0] > b[N-2:0]) begin\n expected_result = a - b;\n end\n else begin\n expected_result = b - a;\n end\n end\n\n if (c !== expected_result) begin\n error = error + 1;\n $display(\"Failed: a = %b, b = %b, c = %b, expected_result = %b\", a, b, c, expected_result);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n // End simulation\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = fixed_point_substractor\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module fixed_point_subtractor #(
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin
res[N-2:0] = a[N-2:0] - b[N-2:0];
res[N-1] = a[N-1];
end
// one of them is negative
else if(a[N-1] == 0 && b[N-1] == 1) begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] + b[N-2:0];
res[N-1] = 0;
end
else begin
res[N-2:0] = b[N-2:0] + a[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
end
else begin
if( a[N-2:0] > b[N-2:0] ) begin
res[N-2:0] = a[N-2:0] + b[N-2:0];
if (res[N-2:0] == 0)
res[N-1] = 0;
else
res[N-1] = 1;
end
else begin
res[N-2:0] = b[N-2:0] + a[N-2:0];
res[N-1] = 0;
end
end
end
endmodule |
calendar | Implement a module of perpetual calendar. The starting value of Secs, Mins, and Hours are all 0. Both Secs and Mins loop continuously from 0 to 59. When Secs=59, Min increases by 1 at the next cycle, and when Min=59 && Secs=59, Hours increases by 1 at the next cycle. Hours is counted from the 0-23 cycle.
Module name:
calendar
Input ports:
CLK: Clock input
RST: Active high reset signal
Output ports:
Hours: 6-bit output representing the current hours
Mins: 6-bit output representing the current minutes
Secs: 6-bit output representing the current seconds
Implementation:
The calendar module uses three always blocks to update the values of seconds, minutes, and hours based on the clock signal and reset signal.
The first always block triggers on the positive edge of the clock signal (posedge CLK) or the positive edge of the reset signal (posedge RST). It checks if the reset signal is active (RST) and sets the seconds value (Secs) to 0. If the seconds value is 59, it wraps around and sets the seconds value to 0. Otherwise, it increments the seconds value by 1.
The second always block also triggers on the positive edge of the clock signal or the positive edge of the reset signal. It handles the minutes value (Mins). If the reset signal is active, it sets the minutes value to 0. If both the minutes and seconds values are 59, it wraps around and sets the minutes value to 0. If the seconds value is 59, it increments the minutes value by 1. Otherwise, it keeps the minutes value unchanged.
The third always block triggers on the positive edge of the clock signal or the positive edge of the reset signal. It handles the hours value (Hours). If the reset signal is active, it sets the hours value to 0. If the hours, minutes, and seconds values are all at their maximum (23, 59, and 59 respectively), it wraps around and sets the hours value to 0. If the minutes and seconds values are both 59, it increments the hours value by 1. Otherwise, it keeps the hours value unchanged.
| [
{
"content": "`timescale 1ns/1ps\nmodule main();\nreg clk,rst;\n\nwire[5:0] out1,out2,out3;\n\ncalendar dut(.CLK(clk),.RST(rst),.Hours(out1),.Mins(out2),.Secs(out3));\n\ninitial begin\n clk=0;\n forever #5 clk=~clk;\nend\n\ninteger outfile;\nreg [17:0] clocktime;\nalways @(posedge clk) begin\n clocktime[17:12] <= out1;\n clocktime[11:6] <= out2;\n clocktime[5:0] <= out3;\nend\n\nreg [17:0] reference_data [0:4000];\ninteger i=0;\ninteger error = 0;\ninitial begin\n #10;\n rst = 1;\n #25;\n rst = 0;\n // outfile = $fopen(\"reference.txt\", \"w\");\n $readmemh(\"reference.txt\",reference_data);\n repeat(4000) begin \n // $fwrite(outfile, \"%h\\n\", clocktime);\n $display(\"Time: %t, Hours: %d, Mins: %d, Secs: %d\", $time, out1, out2, out3);\n error = (reference_data[i] == clocktime) ? error :error +1;\n i = i + 1;\n\n #10;\n end\n if(error==0)\n begin\n $display(\"===========Your Design Passed===========\");\n end\n else\n begin\n $display(\"===========Error===========\");\n $fatal;\n end\n // $fclose(outfile);\n $finish;\nend\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = calendar\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
},
{
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"name": "reference.txt"
}
] | module calendar(CLK,RST,Hours,Mins,Secs);
input CLK,RST;
output [5:0] Hours,Mins,Secs;
reg [5:0] Hours,Mins,Secs;
always@(posedge CLK or posedge RST) begin
if (RST)
Secs <= 0;
else if (Secs == 59)
Secs <= 0;
else
Secs <= Secs + 1;
end
always@(posedge CLK or posedge RST) begin
if (RST)
Mins <= 0;
else if((Mins==59)&&(Secs==59))
Mins <= 0;
else if(Secs== 59)
Mins <= Mins + 1;
else
Mins <= Mins;
end
always@(posedge CLK or posedge RST) begin
if (RST)
Hours <= 0;
else if((Hours == 23)&&(Mins==59)&&(Secs==59))
Hours <= 0;
else if((Mins == 59)&&(Secs==59))
Hours <= Hours + 1;
else
Hours <= Hours;
end
endmodule |
pe | Implement a Multiplying Accumulator for 32bit integer. In the MAC_PE, there is a register that stores the partial sum (the intermediate accumulation result), and in each cycle, the result of “a multiplied by b” will be accumulated in this register, and the “c” shows the value of the register.
Module name:
pe
Input ports:
clk: Clock signal used for synchronous operations.
rst: Reset signal. Defined as 1 for reset and 0 for reset signal inactive.
a: 32-bit input operand A.
b: 32-bit input operand B.
Output ports:
c: 32-bit output representing the accumulated result.
Implementation:
The module implements a parallel multiplier and accumulator using registers and an always block. It multiplies the input operands and accumulates the result into an output register.
Accumulator Register:
The module includes a register, c, to store the accumulated result.
On the positive edge of the clock signal (clk) or the positive edge of the reset signal (rst), the module updates the register.
If the reset signal (rst) is high, indicating a reset condition, the register (c) is set to 0. If the reset signal (rst) is low, the register (c) is updated by adding the product of the input operands (a and b) to its current value.
Multiplication and Accumulation:
Inside the always block, the module performs the multiplication and accumulation operation. If the reset signal (rst) is high, the register (c) is set to 0. If the reset signal (rst) is low, the module adds the product of the input operands (a and b) to the register (c).
| [
{
"content": "`timescale 1ns / 1ps\n\nmodule test54();\n\n reg clk;\n reg rst;\n reg [31:0] a,b;\n wire [31:0] c;\n \n pe dut(clk,rst,a,b,c);\n\n\n initial begin\n\n a=0;\n b=0;\n clk=0;\n rst=1;\n #5;\n clk=1;\n #5;\n clk=0;\n rst=0;\n #5;\n\n a=1;\n b=1;\n #5;\n clk=1;\n #5;\n clk=0;\n\n a=2;\n b=2;\n #5;\n clk=1;\n #5;\n clk=0;\n\n a=3;\n b=3;\n #5;\n clk=1;\n #5;\n clk=0;\n\n $display(\"%h\", c);\n\n if(c==32'h0000000e)\n begin\n $display(\"===========Your Design Passed===========\");\n end\n else\n begin\n $display(\"===========Error===========\");\n $fatal;\n end\n end\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = pe\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module pe(
input clk,
input rst,
input [31:0] a,
input [31:0] b,
output [31:0] c
);
reg [31:0] cc;
assign c = cc;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
cc <= 0;
end
else
begin
cc <= cc + a*b;
end
end
endmodule |
alu | Implement an ALU for a 32-bit MIPS-ISA CPU. The “a” and “b” are the two operands of the ALU, the “aluc” is the opcode, and the “r” gives out the result. “zero” means if the result is zero, “carry” means if there is a carry bit, “negative” means if the result is negative, “overflow” means if the computation is overflow, the “flag” is the result of “slt” and “sltu” instructions. The supported operations and corresponding opcode are shown below:
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter LUI = 6'b001111;
Module name:
alu
Input ports:
a: a 32-bit input operand
b: a 32-bit input operand
aluc: a 6-bit control signal for selecting the operation to be performed
Output ports:
r: a 32-bit output representing the result of the operation
zero: a 1-bit output indicating whether the result is zero
carry: a 1-bit output indicating whether a carry occurred during the operation
negative: a 1-bit output indicating whether the result is negative
overflow: a 1-bit output indicating whether an overflow occurred during the operation
flag: a 1-bit output representing a general flag, which is set based on specific operations (SLT and SLTU)
Implementation:
The module uses parameters to define the control signals for various operations, such as ADD, SUB, AND, OR, etc.
The module assigns the input operands to the signed wires and the output result (r) to the lower 32 bits of the register (res[31:0]). The flag output is determined based on the control signal (aluc) and is set to '1' when the operation is SLT or SLTU, and 'z' (high-impedance) otherwise. The zero output is set to '1' when the result is all zeros, and '0' otherwise.
Inside the always block, a case statement is used to perform the appropriate operation based on the control signal (aluc). The result is assigned to the register (res) accordingly. For shift operations (SLL, SRL, SRA, SLLV, SRLV, SRAV), the shift amount is determined by the value of 'a' or 'a[4:0]'. For the LUI operation, the upper 16 bits of 'a' are concatenated with 16 zeros to form the result.
If the control signal (aluc) does not match any defined operation, the result is assigned as 'z' (high-impedance).
| [
{
"content": "0000003d\n0000003d\nfffffffb\nfffffffb\n00000000\n0000003d\n0000003d\nffffffc2\n00000001\n00000001\n10000000\n00000000\n00000000\n10000000\n00000000\n00000000\n001c0000\n",
"name": "reference.dat"
},
{
"content": "`timescale 1ns / 1ps\n\nmodule test_alu();\n\n reg [31:0] a;\n reg [31:0] b;\n reg [5:0] aluc;\n wire [31:0] r;\n wire zero;\n wire carry;\n wire negative;\n wire overflow;\n wire flag;\n reg[4:0]cnt;\n \n alu uut(a,b,aluc,r,zero,carry,negative,overflow,flag);\n\n parameter ADD = 6'b100000;\n parameter ADDU = 6'b100001;\n parameter SUB = 6'b100010;\n parameter SUBU = 6'b100011;\n parameter AND = 6'b100100;\n parameter OR = 6'b100101;\n parameter XOR = 6'b100110;\n parameter NOR = 6'b100111;\n parameter SLT = 6'b101010;\n parameter SLTU = 6'b101011;\n parameter SLL = 6'b000000;\n parameter SRL = 6'b000010;\n parameter SRA = 6'b000011;\n parameter SLLV = 6'b000100;\n parameter SRLV = 6'b000110;\n parameter SRAV = 6'b000111;\n parameter JR = 6'b001000;\n parameter LUI = 6'b001111;\n\n reg[5:0]opcodes[0:31];\n reg[31:0]reference[0:31];\n reg error=0;\n integer file_open;\n initial begin\n\n $readmemh(\"reference.dat\",reference);\n\n opcodes[0]=ADD;\n opcodes[1]=ADDU;\n opcodes[2]=SUB;\n opcodes[3]=SUBU;\n opcodes[4]=AND;\n opcodes[5]=OR;\n opcodes[6]=XOR;\n opcodes[7]=NOR;\n opcodes[8]=SLT;\n opcodes[9]=SLTU;\n opcodes[10]=SLL;\n opcodes[11]=SRL;\n opcodes[12]=SRA;\n opcodes[13]=SLLV;\n opcodes[14]=SRLV;\n opcodes[15]=SRAV;\n //opcodes[16]=JR;\n opcodes[16]=LUI;\n a=32'h0000001c;\n b=32'h00000021;\n #5;\n\n cnt = 0;\n\n \n for(cnt=0;cnt<17;cnt=cnt+1)\n begin\n #5;\n aluc=opcodes[cnt];\n #5;\n error=error|(reference[cnt]!=r);\n if (reference[cnt] != r) begin\n $display(\"Failed: Expected r = %d, Got r = %d\",reference[cnt], r);\n end\n end\n\n if(error==0)\n begin\n $display(\"===========Your Design Passed===========\");\n end\n else\n begin\n $display(\"===========Error===========\");\n $fatal;\n end\n $finish;\n end\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = alu\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns / 1ps
module alu(
input [31:0] a,
input [31:0] b,
input [5:0] aluc,
output [31:0] r,
output zero,
output carry,
output negative,
output overflow,
output flag
);
parameter ADD = 6'b100000;
parameter ADDU = 6'b100001;
parameter SUB = 6'b100010;
parameter SUBU = 6'b100011;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter XOR = 6'b100110;
parameter NOR = 6'b100111;
parameter SLT = 6'b101010;
parameter SLTU = 6'b101011;
parameter SLL = 6'b000000;
parameter SRL = 6'b000010;
parameter SRA = 6'b000011;
parameter SLLV = 6'b000100;
parameter SRLV = 6'b000110;
parameter SRAV = 6'b000111;
parameter JR = 6'b001000;
parameter LUI = 6'b001111;
wire signed [31:0] a_signed;
wire signed [31:0] b_signed;
reg [32:0] res;
assign a_signed = a;
assign b_signed = b;
assign r = res[31:0];
assign flag = (aluc == SLT || aluc == SLTU) ? ((aluc == SLT) ? (a_signed < b_signed) : (a < b)) : 1'bz;
assign zero = (res == 32'b0) ? 1'b1 : 1'b0;
always @ (a or b or aluc)
begin
case(aluc)
ADD: begin
res <= a_signed + b_signed;
end
ADDU: begin
res <= a + b;
end
SUB: begin
res <= a_signed - b_signed;
end
SUBU: begin
res <= a - b;
end
AND: begin
res <= a & b;
end
OR: begin
res <= a | b;
end
XOR: begin
res <= a ^ b;
end
NOR: begin
res <= ~(a | b);
end
SLT: begin
res <= a_signed < b_signed ? 1 : 0;
end
SLTU: begin
res <= a < b ? 1 : 0;
end
SLL: begin
res <= b << a;
end
SRL: begin
res <= b >> a;
end
SRA: begin
res <= b_signed >>> a_signed;
end
SLLV: begin
res <= b << a[4:0];
end
SRLV: begin
res <= b >> a[4:0];
end
SRAV: begin
res <= b_signed >>> a_signed[4:0];
end
LUI: begin
res <= {a[15:0], 16'h0000};
end
default:
begin
res <= 32'bz;
end
endcase
end
endmodule
|
sub_64bit | Implement a module of a 64-bit subtractor with overflow checking for high-precision arithmetic operations.
Module name:
sub_64bit
Input ports:
A [63:0]: First 64-bit input operand (representing a large signed integer).
B [63:0]: Second 64-bit input operand (representing a large signed integer to be subtracted from A).
Output ports:
result [63:0]: 64-bit output representing the difference of the two operands (A - B).
overflow: 1-bit output indicating whether an overflow occurred during the subtraction operation.
Implementation:
Subtraction: The module performs binary subtraction of A and B to obtain the result.
Overflow Detection: The module checks for overflow conditions by examining the sign bits of A, B, and the result.
- Positive overflow occurs when a positive number (A) is subtracted by a negative number (B) and the result is negative.
- Negative overflow occurs when a negative number (A) is subtracted by a positive number (B) and the result is positive.
The overflow flag is set to 1 if an overflow condition is detected; otherwise, it is set to 0.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\n\nmodule testbench;\n\n reg [63:0] A; // Input A (64 bits)\n reg [63:0] B; // Input B (64 bits)\n wire [63:0] result; // Subtraction result (64 bits)\n wire overflow; // Overflow signal\n integer i; // Loop variable\n integer error = 0; // Error count for failed tests\n\n // Instantiate the verified_sub_64bit module\n sub_64bit uut (\n .A(A),\n .B(B),\n .result(result),\n .overflow(overflow)\n );\n\n // Randomize inputs and check output\n initial begin\n for (i = 0; i < 100; i = i + 1) begin\n // Generate random 64-bit inputs\n A = $random;\n B = $random;\n\n // Wait for the operation to complete\n #10;\n\n // Calculate expected result using system task\n // $monitor(\"A = %d, B = %d, Expected Result = %d, Overflow = %b\", A, B, A - B, overflow);\n\n // Check the result of the subtraction\n if (result !== (A - B) || (A - B < 0 && overflow !== 1)) begin\n error = error + 1;\n $display(\"Failed: A = %d, B = %d, Expected Result = %d, Got = %d, Overflow = %b\", A, B, A - B, result, overflow);\n end\n end\n\n // Final test result summary\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d /100 failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = sub_64bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module sub_64bit(
input [63:0] A,
input [63:0] B,
output reg [63:0] result,
output reg overflow
);
always @(*) begin
result = A - B;
// Overflow happens when the sign of A and B are different, but the sign of result matches B
if ((A[63] != B[63]) && (result[63] != A[63])) begin
overflow = 1;
end else begin
overflow = 0;
end
end
endmodule |
clkgenerator | A clock generator module that produces a periodic clock signal, toggling its output state at regular intervals defined by the PERIOD parameter.
Module name:
clkgenerator
Parameter:
PERIOD = 10
Output ports:
clk: The output clock signal generated by the module.
Implementation:
This module uses an initial block to set the initial state of the clock signal to 0. The clock toggles every half of the specified PERIOD, creating a square wave clock signal with the desired frequency.
Give me the complete code. | [
{
"content": "module clkgenerator_tb;\n\n reg clk_tb; // Clock signal from the testbench\n reg res = 1'b0;\n integer error = 0;\n // Instantiate the clkgenerator module\n clkgenerator clkgenerator_inst (\n .clk(clk_tb)\n );\n\n initial begin\n // Monitor the clock signal\n // $monitor(\"Time=%0t, clk=%b\", $time, clk_tb);\n\n // Simulate for a certain number of clock cycles\n repeat (20) begin // Simulate 20 clock cycles\n #5; // Time delay between clock cycles\n error = (res == clk_tb) ? error :error+1;\n res = res + 1;\n $display(clk_tb);\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d failures ===========\", error);\n $fatal;\n end\n // Finish simulation\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = clkgenerator\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module clkgenerator (
output reg clk
);
parameter PERIOD = 10; // Clock period in time units
// Initial block to set the initial state of the clock
initial begin
clk = 0; // Initialize the clock signal to 0
end
always begin
# (PERIOD / 2) clk = ~clk; // Toggle the clock every half period
end
endmodule
|
up_down_counter | Module name:
up_down_counter
Function:
A 16-bit counter that can increment or decrement based on control signals.
Input ports:
clk: Clock signal (1-bit), used to synchronize the counting process.
reset: Reset signal (1-bit), used to reset the counter to zero.
up_down: Control signal (1-bit), determines the counting direction.
If up_down = 1, the counter increments; if up_down = 0, it decrements.
Output ports:
count [15:0]: 16-bit output representing the current counter value.
Implementation:
The module uses a synchronous process triggered by the rising edge of the clock signal (`clk`).
If the reset signal (`reset`) is active, the counter resets to zero.
If the `up_down` control signal is high, the counter increments on each clock cycle.
If the `up_down` control signal is low, the counter decrements on each clock cycle.
The `count` output reflects the current value of the counter, which can range from 0 to 65535.
| [
{
"content": "module testbench;\n\n reg clk;\n reg reset;\n reg up_down;\n wire [15:0] count;\n\n // Instantiate the up_down_counter module\n up_down_counter uut (\n .clk(clk),\n .reset(reset),\n .up_down(up_down),\n .count(count)\n );\n\n integer error = 0;\n always begin\n #5 clk <= ~clk;\n end\n\n // Initial \n initial begin\n clk = 0;\n reset = 1;\n up_down = 1; \n #10 reset = 0;\n end\n\n // Monitor for displaying count\n // always @(posedge clk) begin\n // $display(\"Count = %d\", count);\n // end\n\n // Test counting up\n initial begin\n #20 up_down = 1;\n #100 up_down = 0; // Switch to counting down\n $display(\"Count = %d, expected = 11\", count);\n error = (count==11)?error : error+1;\n #200 up_down = 1; // Switch back to counting up\n $display(\"Count = %d, expected = 65527\", count);\n error = (count==65527)?error : error+1;\n #300 ;\n $display(\"Count = %d, expected = 21\", count);\n error = (count==21)?error : error+1;\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d failures ===========\", error);\n $fatal;\n end\n\n $finish;\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = up_down_counter\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module up_down_counter (
input wire clk,
input wire reset,
input wire up_down,
output reg [15:0] count
);
always @(posedge clk or posedge reset)
begin
if (reset) begin
count <= 16'b0;
end else begin
if (up_down) begin
// Increment the counter if up_down is high
if (count == 16'b1111_1111_1111_1111) begin
count <= 16'b0;
end else begin
count <= count + 1;
end
end else begin
// Decrement the counter if up_down is low
if (count == 16'b0) begin
count <= 16'b1111_1111_1111_1111;
end else begin
count <= count - 1;
end
end
end
end
endmodule |
parallel2serial | Implement a module for parallel-to-serial conversion, where every four input bits are converted to a serial one bit output (from MSB to LSB). The output signal valid_out is set to 1 to indicate the availability of valid serial output. When valid_out = 1, the most significant bit of d is output, and the remaining three bits are output sequentially in the following 3 cycles.
Module name:
parallel2serial
Input ports:
clk: Clock signal used for synchronous operations.
rst_n: Reset signal. Defined as 0 for reset and 1 for reset signal inactive.
d: 4-bit parallel data input.
Output ports:
valid_out: Valid signal indicating the availability of serial output.
dout: Serial output representing the converted data.
Implementation:
The most significant bit of the parallel input is assigned to the serial output (dout). On each clock cycle, if the counter (cnt) is 3, indicating the last bit of the parallel input, the module updates the data register (data) with the parallel input (d), resets the counter (cnt) to 0, and sets the valid signal (valid) to 1.
Otherwise, the module increments the counter (cnt) by 1, sets the valid signal (valid) to 0, and shifts the data register (data) one bit to the left, with the most significant bit shifted to the least significant bit.
Counter Register: If the reset signal (rst_n) is high, the register (cnt) is incremented by 1.
| [
{
"content": "`timescale 1ns/1ns\n\nmodule parallel2serial_tb;\n reg clk;\n reg rst_n;\n reg [3:0] d;\n wire valid_out;\n wire dout;\n\n // Instantiate the DUT (Design Under Test)\n parallel2serial dut (\n .clk(clk),\n .rst_n(rst_n),\n .d(d),\n .valid_out(valid_out),\n .dout(dout)\n );\n\n // Generate clock\n always #5 clk = ~clk;\n integer error = 0;\n integer failcase = 0;\n integer i = 0;\n initial begin\n for (i=0; i<100; i=i+1) begin\n error = 0;\n // Initialize inputs\n clk = 0;\n rst_n = 0;\n d = 4'b0;\n\n #10;\n rst_n = 1;\n #10;\n d = $random;\n while (valid_out == 0) begin\n @(posedge clk); // Wait for one clock cycle\n end\n error = (dout == d[3] && valid_out==1) ? error : error+1;\n if (dout != d[3] || valid_out != 1) begin\n $display(\"Failed testcase: d = %b\", d);\n end\n #10;\n error = (dout == d[2] && valid_out==0) ? error : error+1;\n if (dout != d[2] || valid_out != 0) begin\n $display(\"Failed testcase: d = %b\", d);\n end\n #10;\n error = (dout == d[1] && valid_out==0) ? error : error+1;\n if (dout != d[1] || valid_out != 0) begin\n $display(\"Failed testcase: d = %b\", d);\n end\n #10;\n error = (dout == d[0] && valid_out==0) ? error : error+1;\n if (dout != d[0] || valid_out != 0) begin\n $display(\"Failed testcase: d = %b\", d);\n end\n #10;\n error = (valid_out==1) ? error : error+1;\n if (valid_out != 1) begin\n $display(\"Failed testcase: d = %b\", d);\n end\n #10;\n failcase = (error==0)? failcase :failcase+1;\n\n end\n if(failcase==0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d /100 failures===========\", failcase);\n $fatal;\n end\n $finish; \n end\n\nendmodule\n\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = parallel2serial\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | `timescale 1ns/1ns
module parallel2serial(
input wire clk ,
input wire rst_n ,
input wire [3:0]d ,
output wire valid_out ,
output wire dout
);
reg [3:0] data = 'd0;
reg [1:0]cnt;
reg valid;
assign dout = data[3];
assign valid_out =valid;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
data<= 'd0;
cnt <= 'd0;
valid <= 'd0;
end
else begin
if (cnt == 'd3) begin
data <= d;
cnt <= 'd0;
valid <= 1;
end
else begin
cnt <= cnt + 'd1;
valid <= 0;
data <= {data[2:0],data[3]};
end
end
end
endmodule |
LFSR | A Linear Feedback Shift Register (LFSR) designed for generating pseudo-random sequences. This 4-bit LFSR uses a specific feedback mechanism to produce a sequence of bits that appears random.
Module name:
LFSR
Input ports:
clk: Clock signal to synchronize the shifting operation.
rst: Active high reset signal to initialize the register.
Output ports:
out [3:0]: 4-bit output representing the current state of the LFSR.
Implementation:
The LFSR operates on the principle of shifting bits and applying feedback based on the XOR of specific bits in the register.
The feedback is calculated by XORing the most significant bit (out[3]) and the second most significant bit (out[2]). The result is inverted to produce the feedback signal.
On the rising edge of the clock (clk), if the reset (rst) is high, the register is initialized to zero. Otherwise, the bits in the register are shifted left, and the new feedback value is inserted at the least significant bit (LSB).
| [
{
"content": "module lfsr_tb();\nreg clk_tb;\nreg rst_tb;\nwire [3:0] out_tb;\n\nLFSR DUT(out_tb,clk_tb,rst_tb);\n\ninitial\nbegin\n clk_tb = 0;\n rst_tb = 1;\n $display(\"clk = %b, rst = %b at time = %d\", clk_tb, rst_tb, $time);\n #15;\n rst_tb = 0;\n $display(\"clk = %b, rst = %b at time = %d\", clk_tb, rst_tb, $time);\n #200;\n if (out_tb == 4'b1101) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"clk = %b, rst = %b at time = %d\", clk_tb, rst_tb, $time);\n $display(\"Failed: expect out_tb=4'b1101, got out_tb=%b\", out_tb);\n $display(\"=========== Failed ===========\");\n $fatal;\n end\n $finish;\nend\n\nalways\nbegin\n #5;\n clk_tb = ~ clk_tb;\nend\n\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = LFSR\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module LFSR (out, clk, rst);
input clk, rst;
output reg [3:0] out;
wire feedback;
assign feedback = ~(out[3] ^ out[2]);
always @(posedge clk, posedge rst)
begin
if (rst)
out = 4'b0;
else
out = {out[2:0],feedback};
end
endmodule |
multi_16bit | Implement the design of an unsigned 16-bit multiplier. It utilizes shift and accumulate operations to generate the product output (yout). The module also includes control signals such as clock (clk), reset (rst_n), and start (start), along with a completion flag (done) indicating the completion of the multiplication operation.
Module name:
multi_16bit
Input ports:
clk: Chip clock signal.
rst_n: Active-low reset signal. Defined as 0 for chip reset and 1 for reset signal inactive.
start: Chip enable signal to initiate the multiplication operation.
ain: Input signal representing the multiplicand (a) with a data width of 16 bits.
bin: Input signal representing the multiplier (b) with a data width of 16 bits.
Output ports:
yout: Product output signal with a data width of 32 bits.
done: Chip output flag signal. Defined as 1 indicates the completion of the multiplication operation.
Implementation:
Data bit control:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the shift count register (i) is updated.
If the reset signal (rst_n) is low, indicating a reset condition, the shift count register (i) is set to 0.
If the start signal is active (start) and the shift count register (i) is less than 17, the shift count register (i) increments by 1.
If the start signal is inactive (!start), the shift count register (i) is reset to 0.
Multiplication completion flag generation:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the multiplication completion flag (done_r) is updated.
If the reset signal (rst_n) is low, the multiplication completion flag (done_r) is set to 0.
If the shift count register (i) is equal to 16, indicating the completion of the multiplication operation, the multiplication completion flag (done_r) is set to 1.
If the shift count register (i) is equal to 17, the multiplication completion flag (done_r) is reset to 0.
Shift and accumulate operation:
On every positive edge of the clock signal (clk) or the falling edge of the reset signal (rst_n), the module performs the shift and accumulate operation.
If the reset signal (rst_n) is low, indicating a reset condition, the multiplicand register (areg), multiplier register (breg), and product register (yout_r) are reset to 0.
If the start signal is active (start), the module starts the multiplication operation.
When the shift count register (i) is 0, the multiplicand (ain) and multiplier (bin) are stored in the respective registers (areg and breg).
For shift counts greater than 0 and less than 17, if the bit at position i-1 in the multiplicand register (areg) is high, the product register (yout_r) accumulates the shifted value of the multiplier register (breg) by shifting it left by i-1 positions and appending zeros at the least significant bit positions.
Output assignment:
The product output (yout) is assigned the value of the product register (yout_r).
| [
{
"content": "module tb_multi_16bit;\n \n reg clk;\n reg rst_n;\n reg start;\n reg [15:0] ain;\n reg [15:0] bin;\n wire [31:0] yout;\n wire done;\n\n integer i; // Declare the loop variable here\n integer fail_count = 0; // Declare a variable to count the failures\n integer timeout; // Declare a timeout counter here\n reg [31:0] expected_product; // Declare a variable to store the expected product\n\n // Instantiate the module\n multi_16bit uut (\n .clk(clk), \n .rst_n(rst_n),\n .start(start),\n .ain(ain), \n .bin(bin), \n .yout(yout),\n .done(done)\n );\n \n // Clock generation\n always begin\n #5 clk = ~clk;\n end\n\n // Randomize inputs and check output\n initial begin\n clk = 0; // Initialize clock\n rst_n = 1; // De-assert reset\n start = 0; // Initialize start\n\n // Perform reset\n rst_n = 0;\n for (i = 0; i < 100; i = i + 1) begin\n #100;\n rst_n = 1;\n #50;\n ain = $random;\n bin = $random;\n #50;\n start = 1; // Start the operation\n while(done !== 1) begin\n #10;\n end\n expected_product = ain * bin;\n \n if (done == 1) begin\n fail_count = (yout == expected_product)? fail_count:fail_count+1;\n end\n start = 0; // Stop the operation\n rst_n = 0;\n #100;\n end\n \n if (fail_count == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Test completed with %d / 100 failures===========\", fail_count);\n $fatal;\n end\n $finish;\n end\n\n initial begin\n #50000;\n $finish;\n end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = multi_16bit\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module multi_16bit(
input clk, // Chip clock signal.
input rst_n, // Active-low reset signal. Defined as 0 for chip reset; defined as 1 for reset signal inactive.
input start, // Chip enable signal.
input [15:0] ain, // Input a (multiplicand) with a data width of 16 bits.
input [15:0] bin, // Input b (multiplier) with a data width of 16 bits.
output [31:0] yout, // Product output with a data width of 32 bits.
output done // Chip output flag signal. Defined as 1 indicates multiplication operation completion.
);
reg [15:0] areg; // Multiplicand a register.
reg [15:0] breg; // Multiplier b register.
reg [31:0] yout_r; // Product register.
reg done_r;
reg [4:0] i; // Shift count register.
//------------------------------------------------
// Data bit control
always @(posedge clk or negedge rst_n)
if (!rst_n) i <= 5'd0;
else if (start && i < 5'd17) i <= i + 1'b1;
else if (!start) i <= 5'd0;
//------------------------------------------------
// Multiplication completion flag generation
always @(posedge clk or negedge rst_n)
if (!rst_n) done_r <= 1'b0;
else if (i == 5'd16) done_r <= 1'b1; // Multiplication completion flag
else if (i == 5'd17) done_r <= 1'b0; // Flag reset
assign done = done_r;
//------------------------------------------------
// Dedicated register for shift and accumulate operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
areg <= 16'h0000;
breg <= 16'h0000;
yout_r <= 32'h00000000;
end
else if (start) begin // Start operation
if (i == 5'd0) begin // Store multiplicand and multiplier
areg <= ain;
breg <= bin;
end
else if (i > 5'd0 && i < 5'd17) begin
if (areg[i-1])
yout_r <= yout_r + ({16'h0000, breg} << (i-1)); // Accumulate and shift
end
end
end
assign yout = yout_r;
endmodule |
freq_div | Implement a frequency divider that the input clock frequency of 100MHz signal, and the outputs are 3 clock frequencies: 50MHz, 10MHz, 1MHz.
Module name:
freq_div
Input ports:
CLK_in: Input clock signal
RST: Reset signal
Output ports:
CLK_50: Output clock signal with a frequency of CLK_in divided by 2.
CLK_10: Output clock signal with a frequency of CLK_in divided by 10.
CLK_1: Output clock signal with a frequency of CLK_in divided by 100.
Implementation:
The module uses three counters to divide the input clock frequency.
CLK_50 generation:
On every positive edge of CLK_in or RST, if RST is active, CLK_50 is set to 0.
Otherwise, CLK_50 is toggled by inverting its current value.
CLK_10 generation:
On every positive edge of CLK_in or RST, if RST is active, CLK_10 is set to 0, and the counter cnt_10 is reset to 0.
If the counter cnt_10 reaches a value of 4, CLK_10 is toggled by inverting its current value, and the counter cnt_10 is reset to 0.
Otherwise, the counter cnt_10 is incremented by 1.
CLK_1 generation:
On every positive edge of CLK_in or RST, if RST is active, CLK_1 is set to 0, and the counter cnt_100 is reset to 0.
If the counter cnt_100 reaches a value of 49, CLK_1 is toggled by inverting its current value, and the counter cnt_100 is reset to 0.
Otherwise, the counter cnt_100 is incremented by 1.
| [
{
"content": "module test ();\n\nreg clk,rst;\n\nwire out1;\nwire out2;\nwire out3;\n\nfreq_div dut(.CLK_in(clk),.RST(rst),.CLK_50(out1),.CLK_10(out2),.CLK_1(out3));\n\ninitial begin\n clk = 0;\n forever #5 clk = ~clk;\nend\n\ninteger error=0;\n\ninitial begin \n #10;\n rst = 1;\n #35;\n rst = 0;\n // 45, clk: 1, clk50: 0, rclk10: 0, clk1: 0\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 0 || out2 != 0 || out3 !=0 ) ? error+1 : error;\n // 55, clk: 1, clk50: 1, rclk10: 0, clk1: 0\n #10;\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 1 || out2 != 0 || out3 !=0 ) ? error+1 : error;\n // 95, clk50: 0, rclk10: 1, clk1: 0\n #40;\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 1 || out2 != 1 || out3 !=0 ) ? error+1 : error;\n // 225, clk: 1, clk50: 0, rclk10: 1, clk1: 0\n #130;\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 0 || out2 != 1 || out3 !=0 ) ? error+1 : error;\n // 625, clk: 1, clk50: 0, rclk10: 1, clk1: 1\n #400;\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 0 || out2 != 1 || out3 !=1 ) ? error+1 : error;\n // 1035, clk: 1, clk50: 1, rclk10: 1, clk1: 1\n #410;\n $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n error = (out1 != 1 || out2 != 1 || out3 !=1 ) ? error+1 : error;\n if (error == 0) begin\n $display(\"===========Your Design Passed===========\");\n end\n else begin\n $display(\"===========Error===========\", error);\n $fatal;\n end\n $finish;\nend\n\n// initial begin \n// repeat(500) begin\n// #5\n// $display(\"Time: %t, clk: %b, clk50: %b, rclk10: %b, clk1: %b\", $time, clk, out1, out2, out3);\n// end\n// end\n\nendmodule",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = freq_div\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n /home/coguest/luyao/SmallDesigns/chatgpt35/t5/freq_div.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module freq_div (CLK_in,CLK_50,CLK_10,CLK_1,RST);
input CLK_in,RST;
output reg CLK_50,CLK_10,CLK_1;
reg [3:0] cnt_10;
reg [6:0] cnt_100;
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_50<= 1'b0;
end
else begin
CLK_50<= ~CLK_50;
end
end
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_10<= 1'b0;
cnt_10<=0;
end
else if (cnt_10==4) begin
CLK_10<= ~CLK_10;
cnt_10<=0;
end
else begin
cnt_10<=cnt_10+1;
end
end
always @(posedge CLK_in or posedge RST) begin
if (RST) begin
CLK_1<= 1'b0;
cnt_100<=0;
end
else if (cnt_100==49) begin
CLK_1<= ~CLK_1;
cnt_100<=0;
end
else begin
cnt_100<=cnt_100+1;
end
end
endmodule |
ring_counter | Implement a module of an 8-bit ring counter for cyclic state sequences.
Module name:
ring_counter
Input ports:
clk: Clock signal that drives the state transitions of the ring counter.
reset: Reset signal to initialize the counter to its starting state.
Output ports:
out [7:0]: 8-bit output representing the current state of the ring counter. Only one bit is set high at any time, and the set bit cycles through the 8-bit output.
Internal logic:
1. State Transition: The ring counter follows a cyclic pattern where exactly one bit is set to 1 in the output at any given time, and the 1 shifts to the next bit with each clock pulse.
2. Initialization: When the reset signal is high, the counter is initialized to its starting state, typically with the least significant bit (LSB) of out set to 1 (i.e., out = 8'b0000_0001).
3. Cycling Behavior: On each rising edge of the clock signal, the 1 shifts to the next bit in the sequence, and after reaching the most significant bit (MSB), it wraps around to the LSB, creating a cyclic sequence.
Reset Behavior: When reset is high, the ring counter is reset to its initial state (out = 8'b0000_0001).
Give me the complete code. | [
{
"content": "module testbench;\n\n reg clk;\n reg reset;\n wire [7:0] out;\n\n ring_counter ring_counter_inst (\n .clk(clk),\n .reset(reset),\n .out(out)\n );\n\n always begin\n #5 clk <= ~clk;\n end\n\n \n\n reg [3:0] i;\n reg [7:0] data [0:9] = {8'b00000001, 8'b00000001, 8'b00000010, 8'b00000100, 8'b00001000,8'b00010000, 8'b00100000, 8'b01000000, 8'b10000000, 8'b00000001};\n\n initial begin\n clk = 0;\n reset = 1;\n i=0;\n #10 reset = 0;\n end\n // Monitor for displaying output\n always @(posedge clk) begin\n \n if (out !== data[i]) begin\n $display(\"Failed at i=%d, out=%b, expected=%b\", i, out, data[i]);\n // $finish;\n end\n i = i + 1;\n end\n\n // Stop simulation after checking all values\n always @(posedge clk) begin\n if (i == 9) begin\n $display(\"=========== Your Design Passed ===========\");\n $finish;\n end else begin\n $display(\"=========== Error ===========\");\n $fatal;\n end\n end\n // Stop simulation after 100 clock cycles\n initial begin\n #100 $finish;\n end\n\nendmodule\n",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = ring_counter\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module ring_counter (
input wire clk,
input wire reset,
output reg [7:0] out
);
reg [7:0] state;
// State initialization
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= 8'b0000_0001;
else
state <= {state[6:0], state[7]};
end
assign out = state;
endmodule
|
freq_divbyfrac | A frequency divider that divides the input clock frequency by fractional values. It generates a clock signal with a fractional frequency division (3.5x), using the double-edge clocking technique to achieve half-integer division while adjusting for duty cycle imbalance. By dividing uneven clock cycles and phase-shifting them, a smooth fractional clock output is produced.
Module name:
freq_divbyfrac
Input ports:
clk: Input clock signal.
rst_n: Active low reset signal to initialize the module.
Output ports:
clk_div: Fractionally divided clock output.
Implementation:
The module performs fractional frequency division by counting clock cycles and generating an intermediate divided clock signal. For 3.5x division:
The counter cycles through 7 clock cycles (MUL2_DIV_CLK = 7).
It generates two uneven clock periods: one with 4 source clock cycles and another with 3 source clock cycles.
In the next cycle, phase-shifted versions of the divided clock are generated. One phase is delayed by half a clock period, and the other is advanced by half a clock period.
Finally, the two intermediate clocks are logically OR-ed to produce the final fractional divided clock output, ensuring the divided clock signal has a uniform period.
Give me the complete code. | [
{
"content": "`timescale 1ns / 1ps\nmodule freq_divbyfrac_tb;\n // Inputs\n reg clk;\n reg rst_n;\n // Outputs\n wire clk_div;\n \n // Instantiate the Unit Under Test (UUT)\n freq_divbyfrac uut (\n .clk(clk), \n .rst_n(rst_n), \n .clk_div(clk_div)\n );\n always #5 clk = ~clk;\n \n integer error = 0;\n integer expected_value = 1;\n integer i;\n initial begin\n // Initialize Inputs\n clk = 1;\n rst_n = 0;\n # 10 rst_n = 1;\n #120;\n\n $finish;\n end\n initial begin\n // $monitor(\"clk=%d, clk_div=%d\",clk,clk_div);\n #15;\n for (i = 0; i < 20; i = i + 1) begin\n if (clk_div !== expected_value) begin\n error = error + 1; \n $display(\"Failed: expect clk_div = %d, got clk_div = %d\", expected_value, clk_div);\n end\n\n if (i < 2) expected_value = 1; \n else if (i < 6) expected_value = 0; \n else if (i < 9) expected_value = 1; \n else if (i < 13) expected_value = 0; \n else if (i < 16) expected_value = 1; \n else if (i < 20) expected_value = 0; \n else expected_value = 1; // Last five pairs\n #5;\n end\n if (error == 0) begin\n $display(\"=========== Your Design Passed ===========\");\n end\n else begin\n $display(\"=========== Test completed with %d/20 failures ===========\", error);\n $fatal;\n end\n end\nendmodule\n ",
"name": "testbench.v"
},
{
"content": ".PHONY: vcs sim clean\n\nTEST_DESIGN = freq_divbyfrac\n\nvcs:\n vcs -sverilog +v2k -timescale=1ns/1ns \\\n -debug_all \\\n -l compile.log \\\n ${TEST_DESIGN}.v testbench.v\n\nsim:\n ./simv -l run.log\n\nclean:\n rm -rf *.log csrc simv* *.key *.vpd DVEfiles coverage *.vdb output.txt\n",
"name": "makefile"
}
] | module freq_divbyfrac(
input rst_n ,
input clk,
output clk_div
);
parameter MUL2_DIV_CLK = 7 ;
reg [3:0] cnt ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 'b0 ;
end
else if (cnt == MUL2_DIV_CLK-1) begin
cnt <= 'b0 ;
end
else begin
cnt <= cnt + 1'b1 ;
end
end
reg clk_ave_r ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_ave_r <= 1'b0 ;
end
//first cycle: 4 source clk cycle
else if (cnt == 0) begin
clk_ave_r <= 1 ;
end
//2nd cycle: 3 source clk cycle
else if (cnt == (MUL2_DIV_CLK/2)+1) begin
clk_ave_r <= 1 ;
end
else begin
clk_ave_r <= 0 ;
end
end
//adjust
reg clk_adjust_r ;
always @(negedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_adjust_r <= 1'b0 ;
end
else if (cnt == 1) begin
clk_adjust_r <= 1 ;
end
else if (cnt == (MUL2_DIV_CLK/2)+1 ) begin
clk_adjust_r <= 1 ;
end
else begin
clk_adjust_r <= 0 ;
end
end
assign clk_div = clk_adjust_r | clk_ave_r ;
endmodule
|
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