LaMPlace: Learning to Optimize Cross-Stage Metrics in Macro Placement
Zijie Geng Jie Wang Ziyan Liu Siyuan Xu Zhentao Tang Shixiong Kai Mingxuan Yuan Jianye HAO Feng Wu
Machine learning techniques have shown great potential in enhancing macro placement, a critical stage in modern chip design.
However, existing methods primarily focus on *online* optimization of *intermediate surrogate metrics* that are available at the current placement stage, rather than directly targeting the *cross-stage metrics*---such as the timing performance---that measure the final chip quality.
This is mainly because of the high computational costs associated with performing post-placement stages for evaluating such metrics, making the *online* optimization impractical.
Consequently, these optimizations struggle to align with actual performance improvements and can even lead to severe manufacturing issues.
To bridge this gap, we propose **LaMPlace**, which **L**earns **a** **M**ask for optimizing cross-stage metrics in macro placement.
Specifically, LaMPlace trains a predictor on *offline* data to estimate these *cross-stage metrics* and then leverages the predictor to quickly generate a mask, i.e., a pixel-level feature map that quantifies the impact of placing a macro in each chip grid location on the design metrics.
This mask essentially acts as a fast evaluator, enabling placement decisions based on *cross-stage metrics* rather than *intermediate surrogate metrics*.
Experiments on commonly used benchmarks demonstrate that LaMPlace significantly improves the chip quality across several key design metrics, achieving an average improvement of 9.6\%, notably 43.0\% and 30.4\% in terms of WNS and TNS, respectively, which are two crucial cross-stage metrics that reflect the final chip quality in terms of the timing performance.
Macro placement, Chip design, EDA
We propose a learning-based method for optimizing cross-stage metrics in macro placement.