1. Field of the Invention
The present invention relates generally to a precharge circuit for charging a pair of complementary signal lines to the same potential prior to generation of a potential difference between the pair of complementary signal lines by a given potential, more particularly, to a precharge circuit for charging a bit line pair in an static random access memory (SRAM) circuit.
2. Description of the Related Art
FIG. 6(B) shows part of a precharge circuit and a memory cell array of a prior art SRAM circuit. Hereinafter, symbols X and *X generally denote complementary signal lines. In order to precharge bit lines B1 and *B1 by a power source potential VDD prior to read from and write to a 4 transistor memory cell MC1, a PMOS transistor Q2 is connected between the bit lines B1 and *B1, a PMOS transistor Q1 is connected between the bit line B1 and the power source potential VDD, and a PMOS transistor Q3 is connected between the bit line *B1 and the power source potential PCG.
For example, in a case where the bit lines B1 and *B1 are at high and low potential levels, respectively, and when a precharge control signal line PCG is driven high, currents flow from the power source potential VDD through the PMOS transistor Q3 to the bit line *B1, from the bit line B1 through the PMOS transistor Q2 to the bit line *B1, from the power source potential VDD through the PMOS transistor Q1 to the bit line B1, and from the power source potential VDD through the PMOS transistors Q1 and Q2 to the bit line *B1 such that the bit lines B1 and *B1 goes to the power source potential VDD. This applies to precharge operation on other bit line pairs in similar manner.
FIG. 6(A) shows a layout of transistors and contacts thereto of the precharge circuit of FIG. 6(B).
The bit lines B1 and *B1 formed in a metal wiring layer above the transistors are connected through contacts BIC and *BIC to P type regions 11 and 12, respectively, each in common to adjacent PMOS transistors. The power supply line VDD formed in a power supply line layer above the transistors is connected through respective contacts Cl and C2 to P type regions 13 and 14 each in common to adjacent PMOS transistors.
The gate electrodes 15 to 17 of the respective PMOS transistors Q1 to Q3 are parallel to each other, so the P type regions of sufficient spaces can be ensured between the gate electrodes to realize high speed precharge with decreasing in resistance of each transistor which is on. Further, short circuits between the gate electrodes in device fabrication can be prevented.
In recent memory devices, a memory cell pitch has been narrowed in company with a high storage density, and design rules adopted in a memory cell array have been stricter in comparison with those of peripheral circuitry. Hence a three transistor width W1=3d, where d is a transistor pitch, of a precharge circuit cannot be confined within the memory cell pitch, with the result that realization of higher storage density in memory circuit is hindered.
When such a problem arose before the quarter micron technology, the three transistor width W1 of the precharge circuit was able to be narrowed by the use of bent gate electrodes in transistors of the precharge circuit. After the quarter micron technology, however, such a layout has been practically impossible since a space between adjacent bent gate electrodes is narrower with not only increasing resistance of transistors which are on, but also decreasing a product yield due to short circuits generated in device fabrication.
A precharge circuit with two transistors is disclosed in JP 3-209690 A, which is obtained by omitting a transistor connected between one bit line of a bit line pair and the power source potential VDD in the above described precharge circuit with three transistors.
However, by omitting the transistor, when a bit line on the omitted transistor side is at a low level, a precharge speed with driving this bit line to a high level is reduced, resulting in a longer memory access time.
Accordingly, it is an object of the present invention to provide a precharge circuit capable of suppressing a reduction in a precharge speed with a smaller width thereof.
In one aspect of the present invention, there is provided a precharge circuit for precharging first and second signal lines to a given potential, comprising: first and second switching transistors connected between a first end side of the first signal line and the given potential and between a second end side of the second signal line and the given potential, respectively; and third and fourth switching transistors connected between the first and second signal lines at the first end side and at the second end side, respectively.
According to this configuration, since the number of switching transistors in each of precharge circuits at first and second end sides of one signal line pair is two, a width in a direction perpendicular to the signal lines can be narrower than that of the prior art precharge circuit having three switching transistors at one side of the signal line pair, thereby enabling higher storage density in memory circuit.
Further, although a switching transistor between a second signal line and a given potential is omitted at a first end side of the second signal line, a switching transistor is not omitted at a second end side of the second signal line and likewise, although a switching transistor between a first signal line and the predetermined potential is omitted at the second end side of the first signal line, a switching transistor is not omitted at the first end side of the first signal line; therefore, a reduction in precharge speed due to omission of the switching transistors can be suppressed.
In another aspect of the present invention, there is provided a precharge circuit for precharging a plurality of signal line pairs to a given potential, comprising: a first switching transistor connected between one signal line of each of the signal line pairs and the given potential; a second switching transistor connected between signal lines of each of the signal line pairs; and a third switching transistor connected between adjacent signal lines of adjacent pairs of the signal line pairs.
According to this configuration, since the defect caused by omitting the above-described transistors is compensated by the third switching transistors for causing all the bit lines to be conductive therebetween, reduction in precharge speed is suppressed. Further, since one third transistor is added between each adjacent signal line pairs, an average number of switching transistors for each signal line pair is 2.5 and therefore, a width in a direction perpendicular to the signal lines can be narrower than that of the prior art having three switching transistors for each signal line pair, thereby enabling a higher storage density in memory circuit.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.