1. Field of the Invention
The present invention relates to a flash memory having redundant circuits, and more particularly, to a flash memory capable of improving yields.
2. Description of the Prior Art
FIG. 13 is a configuration for illustrating a conventional flash memory device. In FIG. 13, reference numerals 1 to 5 represent memory blocks, respectively. Reference numerals 11 to 15 represent redundant circuits (redundant memory blocks), respectively. The redundant circuits 11 to 15 are positioned adjacent to the memory blocks 1 to 5, respectively. In the flash memory device being illustrated, bit lines BL0 to BL15 are located across the memory blocks 1 to 5. In addition, spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. For example, when a memory cell 8 is at fault in the memory block 5 in the flash memory device being illustrated, the memory cell 8 is replaced with the redundant circuit 15.
By the way, a wafer test 0 (WT0) is carried out in concern to a wafer in order to check whether or not a wafer has a malfunctioned memory cell after a wafer process finishes. More particularly, the WT0 is for checking whether or not the flash memory device has the malfunctioned memory cell. When the flash memory device has the malfunctioned memory cell, the location of the malfunctioned memory cell is stored which may be a malfunctioned memory cell 8 in FIG. 13. By laser trimming and so on, saving information is produced which is for use in replacing the bit line BL8 with the spare bit line SBL1 of the redundant circuits 11 to 15. The malfunctioned memory cell 8 is positioned at the bit line BL8.
After the above-mentioned WT0 is completed, the bit line BL8 having the malfunctioned memory cell 8 is replaced with spare bit line SBL1 of the redundant circuits 11 to 15 by the laser trimming on the basis of the remedy or saving information. A wafer test 1 (WT1) is carried out which is for testing the flash memory device in addition to the spare bit line SBL1 of the redundant circuits 11 to 15. When the flash memory device passes the test, the flash memory device is conveyed to a next process.
FIG. 14 shows a view for illustrating a structure of the memory cell. Reference numeral 101 represents a control gate (CG). A predetermined voltage is applied to the control gate 101 on carrying out a writing/erasing operation. Reference numeral 102 represents a floating gate. The floating gate 102 traps electrons on the basis of the writing/erasing operation. Reference numeral 103 represents an insulating film having an ONO structure. Reference numeral 104 represents a tunnel oxide film through which the electrons travel between the floating gate 102 and a base 105 in accordance with tunnel phenomenon.
In FIG. 14, +10V may be, for example, applied to the control gate 101 and 0V may be applied to the base 105 in case of setting a threshold voltage Vth of the memory cell to a high voltage, on the writing/erasing operation. On the other hand, xe2x88x9210V may be applied to control gate 101 and +10V is applied to the base 105 in case of setting the threshold voltage Vth of the memory cell to a low voltage.
As described above, the voltage of 20V is applied between the control gate 101 and the base 105 in case of setting the threshold voltage Vth of the memory cell to the low voltage. As a result, an electrical breakdown often occurs in each of the tunnel oxide film 104 and the ONO insulating film 103 when the memory cell has a defect or a foreign particle.
There is the breakdown of the insulating film and so on which are based on applying the high voltage to the tunnel oxide film 104 and the ONO insulating film 103, as a memory cell destruction mode on the wafer test. In the above-mentioned WT0 and WT1, the malfunctioned memory cell is removed which is based on the breakdown of the insulating film.
In general, the writing/erasing operations are repeated in concern to the memory blocks 1 to 5 at the WT0 and the WT1, in order to carry out the sufficient testing of the memory blocks 1 to 5. On the other hand, a minimum testing is carried out in concern to the redundant circuits 11 to 15 on the WT0, taking the testing time and the testing cost into consideration, inasmuch as there are some questions as to whether or not each of the redundant circuits 11 to 15 is actually used. For example, only one reading/writing operation is carried out in concern to the redundant circuits 11 to 15, in order to check whether or not data are correctly written in the each of the redundant circuits 11 to 15.
Under the circumstances, the probability of discovery of the malfunctioned memory cell is very high in concern to each of the memory blocks 1 to 5. It is often difficult to discover the malfunctioned memory cell and to remove the malfunctioned memory cell in concern to each of the redundant circuits 11 to 15.
As described above, there is a problem in a case where it is impossible to remove the malfunctioned memory cell in the WT0 even if any one of the redundant circuits has the malfunctioned memory cell. In other words, it is impossible to use the part corresponding to the memory cell of the memory block 2 that is positioned on the bit line BL8, when an error or destruction occurs in the memory cell (for example, the memory cell 9 of the redundant circuit 12) positioned on the spare bit line SBL1 of the replaced redundant circuit in the middle of repeating the writing/erasing operation in the next WT1. As a result, there is a problem in which the flash memory becomes an inferior product.
More particularly, it is necessary to carry out a serious testing inasmuch as the number of the writing/erasing operations inevitably increases, when the memory block is a boot memory block in which accessing frequencies are very high. When there is the malfunctioned memory cell in the redundant circuit 12 which corresponds to the boot memory block 2 after the malfunctioned memory cell of the boot memory block 2 is replaced with the redundant circuit in the WT0, there is a problem in which it is impossible to use the flash memory device although the malfunctioned memory cell of the boot memory block 2 has a very small memory area in comparison to the entire memory area of the flash memory device.
In addition, a potentially malfunctioned memory cell may be included in each of the redundant circuits inasmuch as the testing is not perfectly carried out in concern to each of the redundant circuits through the WT0 and the WT1. There is a problem in which the potentially malfunctioned memory cell becomes an actually malfunctioned memory cell when the flash memory device is under an actual use.
In a case where the malfunctioned memory cell is replaced with the redundant circuit (spare memory cell) in the manner described above, the replaced memory cell is destroyed on the basis of a great number of rewriting operations so that the word line concerned to the replaced memory cell becomes at fault. As a result, the flash memory device becomes at fault. In this event, it is necessary for the memory block to have no potentially malfunctioned memory cell in case where a great number of rewriting operations are carried out in concern to the memory block.
In addition, dummy bit lines may be positioned at both sides of each memory cell in the flash memory device, in order to make a work shape become stable in the wafer process. A memory cell exists on each of the dummy bit line which is connected to the memory cell of the memory block and the memory cell (spare memory cell) of the redundant circuit.
In this case, it is impossible to carry out testing of dummy bit lines through the WT0 and WT1. For example, when the dummy bit line corresponding to the boot memory block is destroyed on the basis of a great number of rewriting operations, the word line concerned to the memory cell of the dummy bit line becomes at fault. As a result, the flash memory device may be at fault. Under the circumstances, it is also necessary for the memory block to have no potentially malfunctioned memory cell in the dummy bit line in order to ensure the memory block to carry out a great number of rewriting operations. However, there is a problem in which quality assurance is difficult inasmuch as it is impossible to carry out the testing of each of dummy bit lines in the WT0 and WT1.
In order to dissolve the above-mentioned problems, it is an object of this invention to provide a flash memory device capable of preventing reduction of the yield that is based on a memory cell failure of a redundant circuit.
In addition, it is another object of this invention to provide a flash memory device capable of preventing occurrence of failure that is based on a potentially malfunctioned memory cell of a redundant circuit, in an actual use.
Furthermore, it is still another object of this invention to provide a flash memory device capable of preventing occurrence of failure that is based on a potentially malfunctioned memory cell positioned on a dummy bit line, in an actual use.
A flash memory device according to this invention comprises a plurality of memory blocks and redundant circuits corresponding to said memory blocks, respectively. The flash memory device further comprises replacing means for carrying out replacement by remaining redundant circuits except a particular one of the redundant circuits that corresponds to at least predetermined one of the memory blocks, when a memory cell failure occurs in at least one of the remaining memory blocks except the predetermined memory block.
In a flash memory device according to this invention, bit lines are located across the memory blocks and spare bit lines are located across the redundant circuits. The replacing means makes a specific one of the spare bit lines turn the particular redundant circuit to connect the specific spare bit line to the predetermined memory block when the memory cell failure occurs in at least one of the remaining memory blocks and when the bit line corresponding to the memory cell failure is replaced with the specific spare bit line.
In a flash memory device according to this invention, the predetermined memory block is a memory block which has highest access frequencies among the memory blocks.
In a flash memory device according to this invention, the predetermined memory block is a memory block which has a least memory capacity among the memory blocks.
A flash memory device according to this invention comprises a plurality of memory blocks and redundant circuits corresponding remaining memory blocks, respectively, except at least predetermined one of said memory blocks. The flash memory device further comprises bit lines located across said memory blocks, spare bit lines located across said redundant circuits, and means for connecting the predetermined memory block to a specific one of the spare bit lines when a memory cell failure occurs in at least one of the remaining memory blocks so that the bit line corresponding to the memory cell failure is replaced with the specific spare bit line.
In a flash memory device according to this invention, a word line is located along each pair of the memory block and the redundant circuit. The word line located along the predetermined memory block is disconnected between the predetermined memory block and the particular redundant circuit. A predetermined voltage is applied to the word line located along the predetermined memory block, at a side of the particular redundant circuit.
In a flash memory device according to this invention, a word line is located along to each pair of the memory block and the redundant circuit. The word line located along the predetermined memory block is disconnected between the predetermined memory block and the particular redundant circuit. The word line located along the predetermined memory block is put into a floating state at a side of the particular redundant circuit.
In a flash memory device according to this invention, a word line is located along each pair of the memory block and the redundant circuit. Well are formed in each of the predetermined memory block and the particular redundant circuit to be independent of each other. A predetermined voltage is applied to the well formed in the particular redundant circuit.
In a flash memory device according to this invention, each of the memory blocks and the redundant circuits has a memory cell. The memory cell of the particular redundant circuit has no floating gate.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along each pair of the memory block and the dummy cell. A selected word line located along a selected memory block is selectively disconnected between the memory block and the dummy cell. A predetermined voltage is applied to the word line at a side of the dummy cell for the word line disconnected between the memory block and the dummy cell.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along to each pair of the memory block and the dummy cell. The word line located along each of the memory blocks is selectively disconnected between the memory block and the dummy cell. The word line is put into a floating state at a side of the dummy cell when the word line is disconnected between the memory block and the dummy cell.
A flash memory device according to this invention comprises a plurality of memory blocks and dummy cells corresponding to the memory blocks, respectively. A word line is located along each pair of the memory block and the redundant circuit. Wells are selectively formed in each pair of the predetermined memory block and the dummy cell so as to be independent of each other. A predetermined voltage is applied to the well formed in the dummy cell.