The present invention relates to a method and apparatus for determining the write recovery time of a semiconductor memory on an integrated circuit.
A number of problems occur in testing embedded semiconductor memories, foremost among which is the problem of determining when the relevant events occur at the memory itself. This is due to the fact that the components of the memory are not directly accessible.
One particularly difficult performance indicator for a memory, especially a RAM, is the maximum operating frequency (Fmax). Typically, Fmax is limited by the ability of a memory to perform a write followed by a read. This is because during a write operation the bit lines are set to a maximum differential, for example Vcc and O for a logic 1, and O and Vcc for a logic O. For the next read to occur reliably, the precharge and equalization period must be long enough for both the bit lines to return substantially to Vcc. The time needed for a read following a write is referred to as the xe2x80x9cwrite recoveryxe2x80x9d time.
Measuring the write recovery time is difficult because direct and delay-free access to the relevant circuit nodes is not available. Such paths as are available have indeterminate delays which may be substantial by comparison with this write recovery time.
It is accordingly an object of the present invention to provide an apparatus and method for determining the-write recovery time of a semiconductor memory on an integrated circuit.
According to a first aspect of the present invention there is provided a method of measuring the write recovery time of an embedded memory having an externally accessible first pad for providing an activation signal to equalization and precharge circuitry to thereby cause equalization and precharging of bit lines of said memory, the method comprising: addressing a memory cell storing a first logic level whereby said memory cell causes bit lines connected thereto to separate in potential; applying a precharge signal to said pad at a time such that while said bit lines are at substantially a maximum differential, said equalization and precharge circuitry is activated; thereafter sensing the potential on bit lines connected to a cell storing a second logic level, opposite said first logic level; and determining the minimum time necessary after application of said precharge signal to said pad before said sensing operation achieves a valid result.
Preferably said equalization and precharge circuitry further comprises sense amplifier circuitry activated by said activation signal for performing said sensing operation, and said memory has an externally accessible clock pad for receiving a clock signal for starting a read operation, said read operation comprising said sensing operation, and circuitry connected to receive said clock pulse, said circuitry being operable during said read operation to provide said activation signal a fixed time after said clock signal, wherein said determining step comprises measuring the minimum time-spacing after application of said precharge signal before a clock signal gives rise to a valid result in its read operation, and establishing said fixed time.
Advantageously said fixed time is established as the minimum duration from applying a clock signal to said clock pad until a said control signal is applied in response to which the sense amplifier circuitry produces a valid output.
According to a second aspect of the invention there is provided a method of determining the write recovery performance of a memory, the memory having at least one pair of complementary bit lines, plural memory cells for coupling to said bit lines, and sense and precharge circuitry responsive to an activation signal for sensing the logic value of memory cells coupled to said bit lines and for precharging said bit lines, the method comprising: a pseudo-write step comprising coupling first memory cells storing a first logic value to said bit lines whereby said bit lines separate in potential, and after said bit lines have separated to a substantially maximum separation, applying said activation signal to said sense and precharge circuitry: a reading step comprising addressing second memory cells storing a second logic value opposite to said first value, whereby said second memory cells are coupled to said bit lines and whereby said activation signal is supplied to said sense and precharge circuitry at a fixed delay after said addressing; determining the minimum time-spacing between the instant of applying said activating signal in said pseudo-write step and the instant of said addressing in said reading step for which the output of said sense and precharge circuitry remains valid.
Preferably said memory further comprises address latch circuitry, a self-timing path and a two-input multiplexer having a control input, the address latch circuitry having a clock input node connected to a first external clock pad, the self-timing path having an input and an output, said input being responsive to a clock edge at said first external clock pad and said output, in use, providing said activation signal in response thereto after said fixed time to one input of said two-input multiplexer, the other input of the two input multiplexer being connected to a second external pad and the control input of the two-input multiplexer being coupled to a third external pad, wherein: in said pseudo-write step, said coupling step comprises providing a transition from a first to a second voltage level, to said first external clock pad whereby said first memory cells are addressed and thereby coupled to said bit lines, and whereby a transition from said first to said second level is provided at said output of said self-timing path after said fixed delay, and in said pseudo-write step, said applying step comprises maintaining an input of said first level at said second external pad, providing a control signal at said third external pad to cause said two-input multiplexer to connect said input of said first level at said second pad to said sense and precharge circuitry to maintain said sense and precharge circuitry inactive beyond the occurrence of said transition to said second level at said output of said self-timing path, and causing a change in said control signal whereby said two-input multiplexer switches and connects the second level output from the self-timing path to activate said sense and precharge circuitry.
Advantageously said memory further has comprises address latch circuitry, a self-timing path and a two-input multiplexer having a control input, the address latch circuitry having a clock input node connected to a first external clock pad, the self-timing path having an input and an output, said input being responsive to a clock edge at said first external clock pad and said output, in use, providing said activation signal in response thereto after said fixed time to one input of said two-input multiplexer, the other input of the two input multiplexer being connected to a second external pad and the control input of the two-input multiplexer being coupled to a third external pad, wherein: in said pseudo-write step, said coupling step comprises providing a transition from a first to a second voltage level, to said first external clock pad whereby said first memory cells are addressed and thereby coupled to said bit lines, and whereby a transition from said first to said second level is provided at said output of said self-timing path after said fixed delay, and in said pseudo-write step, said applying step comprises maintaining an input of said first level at said second external pad, providing a control signal at said third external pad to cause said two-input multiplexer to connect said input of said first level at said second pad to said sense and precharge circuitry to maintain said sense and precharge circuitry inactive beyond the occurrence of said transition to said second level at said output of said self-timing path, and causing a change in said control signal whereby said two-input multiplexer switches and connects the second level output from the self-timing path to activate said sense and precharge circuitry.
Conveniently the method further comprises selecting said predetermined period as an access time of said memory.
Advantageously said selecting said predetermined period as an access time of said memory.
Conveniently the method further comprises determining said fixed time and adding said fixed time to said period to provide a measure of said write recovery performance.
Advantageously the step of determining said fixed time comprises establishing said time as the minimum duration between providing a clock transition to said first external clock pad and application of a said control signal to said third external pad, which duration results in a valid output from said output latch circuitry.
According to a further aspect of the invention there is provided a device for determining the write recovery time of a memory, the memory having at least one pair of complementary bit lines, plural memory cells for coupling to said bit lines, and sense and precharge circuitry responsive to an activation signal for sensing the logic value of memory cells coupled to said bit lines and for precharging said bit lines, address latch circuitry having a clock input node connected to a first external clock pad, a self-timing path having an input and an output, said self-timing path input being responsive to a clock edge at said first external clock pad and said self-timing path output during a read cycle of said memory providing said activation signal in response to said clock edge after a fixed time, the memory further comprising first cells storing a first logic value and second cells storing a second logic value opposite said first logic value; the device comprising a two-input multiplexer having a control input, one input of said two-input multiplexer, being connected to the output of said self-timing path, the other input of the two input multiplexer being connected to a second external pad and the control input of the two-input multiplexer being coupled to a third external pad; address circuitry for selecting said first memory cells; testing circuitry for providing said clock edge to said first external clock pad to couple said first memory cells to said bit lines whereby said bit lines separate in potential, for maintaining a control signal on said third external pad to couple said other input of the two-input multiplexer to said sense and precharge circuitry and for providing a fixed potential on said second external pad whereby said sense and precharge circuitry remains inactivated and after said bit lines have separated to substantially a maximum separation, for applying a change in control signal level causing said control signal to switch said multiplexer to thereby apply said activating signal to said sense and precharge circuitry, whereby said bit lines are precharged; whereby after said precharge commences, said address circuitry is operable to address said second memory cells, said testing circuitry is operable to apply a said clock edge to said first external clock pad whereby said second memory cells are coupled to said bit lines and to supply a control signal to said third external pad to connect said self-timing path output via said two-input multiplexer to said sense and precharge circuitry; wherein said write recovery time is determined as the minimum period between said application of a change in control signal level and the instant at which an edge applied at said third external pad would coincide with the appearance of a transition in said self-timing path output when said edge reached said sense and precharge circuitry.