1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit that has a parasitic silicon controlled rectifier (SCR) and can be triggered in advance.
2. Description of the Related Art
In the conventional method for protecting the electrostatic discharge by the implementation of hardware, an on-chip ESD protection circuit is disposed between the internal circuit and the pad in order to protect its internal circuit.
FIG. 1 schematically shows a conventional ESD protection circuit. When the pad 10 receives a positive charge high voltage 110, as the high voltage 110 generated by the ESD is applied to the drain of an N-type transistor 100, when the high voltage 110 exceeds an avalanche breakdown voltage between the drain and a bulk substrate, the junction between the drain of the N-type transistor 100 and the bulk substrate is broken down, and the generated basic current triggers the parasitic lateral NPN BJT (bipolar junction transistor) of the N-type transistor so as to bypass the big current generated by the ESD and thereby protect an internal circuit 102.
To meet need for the semiconductor fabricating process, thickness of a gate oxide becomes smaller, and the avalanche breakdown voltage of the gate oxide is relatively lowered. If the lowered avalanche breakdown voltage of the gate oxide in the internal circuit approaches the junction avalanche breakdown voltage of the N-type transistor 100, the high voltage generated by the ESD punches through the gate oxide of the internal circuit 102, thereby damaging the internal circuit 102.
FIG. 2 schematically shows another conventional ESD protection circuit. The circuit shown in FIG. 2 uses an N-type transistor 240 as a resistor so as to save the area occupied by the chip. A parasitic capacitance (not shown) exists between the drain and the gate of the N-type transistor 250. Therefore, once the pad 20 receives a positive charge high voltage 210, a small positive voltage is induced on the second terminal of the parasitic capacitance, thus a voltage drop is generated between the gate and the source of the N-type transistor 250 and turns on it. Accordingly, the ESD protection element is triggered to be turned on in advance to protect the internal circuit 202. In addition, the gate of an N-type transistor 240 is electrically coupled to a voltage source VDD through a resistor 230. Thus, the N-type transistor 250 is not turned on while the IC is normally operated.
FIG. 3 schematically shows an ESD protection circuit disclosed in U.S. Pat. No. 5,452,171. The circuit comprises a SCR 31, an N-type transistor 301, an inverter 302, a pad 30, and a to-be-protected circuit 32. Wherein, the SCR 31 comprises a P-type BJT 311, an N-type BJT 312, and two resistors R31 and R32. When the electrostatic charge occurs between the pad 30 and the ground terminal, that is, the pad 30 receives a positive charge high voltage 320, as the high voltage 320 generated by the ESD turns on a P-type transistor inside the inverter 302, the ESD voltage is coupled to the gate of the N-type transistor 301 so as to turn on the N-type transistor 301. Therefore, in addition to using the SCR 31 to drain the ESD, the N-type transistor 301 also can be used as a path for draining the ESD.
FIG. 4 schematically shows an ESD protection circuit disclosed in U.S. Pat. No. 6,034,552. This patent is mainly used to prevent the output stage from being damaged by the ESD. The circuit comprises a pad 40, two N-type transistors 401 and 402, a P-type transistor 403, an output stage 41, and a transistor capacitor 404.
Once the pad 40 receives a positive charge high voltage 430, the high voltage 430 generated by the ESD is coupled to the gate of the N-type transistor 401 through a parasitic capacitor C40 of the N-type transistor 401. In such a circuit design, the resistances of the P-type transistor and the transistor capacitance 404 must be high enough. Therefore, when ESD occurs, the N-type transistor 402 is cut-off. Accordingly, the N-type transistor 401 is turned on by the positive voltage 440 so that an ESD discharge path is provided. However, such circuit design wastes a larger chip layout area due to the existence of the transistor capacitance 404.