The present invention relates to a semiconductor memory device for writing/reading data at high speed, as well as storing the data.
Conventionally, among semiconductor memory devices, dynamic random access memories (DRAMs), for example, have found many applications as devices capable of storing and holding a large capacity of data. FIG. 9 shows a basic configuration of a DRAM. Referring to FIG. 9, the DRAM includes a memory cell array 1. As partly shown in FIG. 10, the memory cell array 1 includes a number of memory cells 21 arranged in rows and columns. Each memory cell 21 is constructed of one capacitor C and one MOS transistor MT. The reference numeral 23 denotes bit lines into which data stored in the memory cells 21 are read, and 22 denotes word lines by which data in the memory cells 21 are read into the bit lines 23. A sense amplifier 24 amplifies data read into the bit lines 23. Data stored in the capacitor C of each memory cell 21 disappears with time due to leakage of a signal charge. Refresh operation is therefore required before disappearance of the data, in which the signal data is amplified by the sense amplifier 24 and the amplified data is written again in the capacitor C.
Referring back to FIG. 9, the DRAM also includes: a sense amplifier array 2 constructed of a plurality of sense amplifiers 24 described above; a row decoder 5 for selecting one word line in the memory cell array 1; a selector 3 connected to the sense amplifiers 24 in the sense amplifier array 2; a column decoder 6 for outputting a column selection signal to the selector 3 for selection of a predetermined number of data units amplified by the sense amplifiers 24; a Din buffer 7 for receiving input data Din and outputting the data to the selector 3; a Dout buffer 8 for externally outputting the data selected by the selector 3; and an address buffer 4 for receiving an external address Add on the occasion of a data read or write request and outputting the address to the row decoder 5 and the column decoder 6.
FIG. 11 is a view showing details of the row-related components of the DRAM in FIG. 9. In FIG. 11, the same components as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted. A control circuit 13 receives a read/write command on the occasion of an external data read or write request. The address buffer 4 receives an external address Add under control of the control circuit 13. A row predecoder 16 predecodes a row address received from the address buffer 4. A refresh counter 14 updates a refresh address for the memory cells 21. A selector 70 selects either the refresh counter 14 or the row predecoder 16. The control circuit 13 controls the selector 70 to select the row predecoder 16 when the read/write command is input, or select the refresh counter 14 when a refresh command is input.
Having the above configuration, the conventional semiconductor memory device is prevented from performing data read or write operation during refresh operation performed upon receipt of the refresh command. This disadvantageously deteriorates the access time of the DRAM. Overcoming this disadvantage is particularly important under the circumstances in these days where improvement in performance of semiconductor memory devices is sought.
Under the above circumstances, Japanese Laid-Open Patent Publication No. 10-134569, for example, discloses the following technique. A semiconductor memory device includes a plurality of banks each constructed of a set of one memory cell array and one row decoder. While data read or write operation is performed for the memory cell array in one bank, data read or write operation is also performed in parallel for a memory cell in the memory cell array in another bank.
The above conventional semiconductor memory device has the following problem. While refresh operation is possible in a bank in which data read or write operation is not underway, it is yet impossible to perform refresh operation in a bank in which data read or write operation is underway.
An object of the present invention is providing a semiconductor memory device capable of performing read or write operation at all times while requiring no external refresh request.
To attain the above object, according to the present invention, data read or write operation and refresh operation are performed simultaneously in one memory cell array in which one word line is internally selected in response to an external read or write access request. Specifically, the memory cell array is divided into a plurality of memory sub-arrays. During read or write operation for data in a memory cell in one memory sub-array, refresh operation is performed for the other memory sub-arrays simultaneously with the read or write operation.
The semiconductor memory device of the present invention is a semiconductor memory device having a memory cell array in which a word line is selected according to an external access, and includes: a plurality of memory sub-arrays obtained by dividing the memory cell array; normal word line selection means for selecting a word line in the memory cell array according to an external access; refresh word line selection means for selecting a word line at the same timing as the selection of the word line by the normal word line selection means in a memory sub-array other than a memory sub-array to which the word line selected by the normal word line selection means belongs; and sense amplifier sub-arrays provided for the respective memory sub-arrays for amplifying data corresponding to the word line selected by any of the two word line selection means.
In the semiconductor memory device described above, the refresh word line selection means may be shared by the plurality of memory sub-arrays. Alternatively, the refresh word line selection means may be provided for each of the memory sub-arrays.
In the semiconductor memory device described above, the refresh word line selection means is preferably constructed of a shift register for selecting one word line sequentially.
In the semiconductor memory device described above, the selection of a word line by the refresh word line selection means is preferably performed at a predetermined refresh period for each memory sub-array.
Preferably, the semiconductor memory device described above further includes refresh period setting means for setting the predetermined refresh period for the refresh word line selection means by dividing an external clock.
In the semiconductor memory device described above, the refresh period setting means preferably changes a dividing factor according to the period of the external clock.
In the semiconductor memory device described above, preferably, the memory cell array includes a plurality of memory cells, each of the memory cells includes one capacitor and two MOS transistors connected to the capacitor, and the two MOS transistors are connected to different bit lines, and data in the capacitor is read into the two bit lines alternately by operating the two MOS transistors alternately.
Thus, according to the present invention, in a memory cell array in which one word line is selected according to an external read or write access, one word line is selected in one memory sub-array during an external access, and simultaneously, one word line is also selected in each of the memory sub-arrays other than the memory sub-array to which the selected word line belongs by the refresh word line selection means. This makes it possible to perform automatic internal refresh operation simultaneously with data read or write operation performed according to an external read or write access, in one memory cell array. Thus, while refresh operation is performed automatically without the necessity of external request for refresh operation, external read or write access can be executed freely at all times without restriction by the refresh operation.
In particular, according to the present invention, one word line in each memory sub-array may be directly selected and activated by a shift register. This eliminates the necessity of supplying a refresh address to the memory sub-arrays, and thus improves the simplicity and efficiency of the semiconductor memory device.