Communication within or between integrated circuits is a fundamental attribute of electronic devices. Such communication can involve communication between similar or different chips on a laminate printed circuit board or similar substrate material or within the chip itself. The chips themselves may be manufactured using similar or different technologies. Recent trends show demand for high-speed communication technology is increasing and is critical to address the demand of higher bandwidth and to accommodate testing of high-speed devices at the device and circuit levels. In addition to this, as devices are increasing in complexity there is increasing need to lower the power consumption, decrease the size and reduce the overall system cost. This has created a significant momentum in the area for high-speed interfacing and interconnect.
In recent years interconnect technology has evolved from parallel digital to serial based communication to enable transfer of data in the gigabit range using direct wiring or external transform coupling. Conventional serial I/O cells require ESD (Electro Static Discharge) protection circuits resulting in less power-efficiency, speed limitations, and larger pad size. Furthermore, within a modest power budget, signals can only be consistently and reliably transmitted over a short data path, making them prone to interference and of limited operating range for high-speed/frequency. It is possible to overcome the signal limits but at the expense of increased power. For example it is possible to go 10 Gbits/second using the 10 G Ethernet serial wired link. However, such transceivers require up to 15 Watts of power which is not a practical communications method except for point to point communication for a small number of channels. Power consumption is a major limiting factor where multiple channels of I/O are required thus each individual I/O channel must meet a prescribed power budget many times lower than that of the proposed 10 G standard. Large amounts of power are required as a consequence of techniques used to address signal degradation which increases with the length of the data path. Data path length and its impact on signal integrity is often a major concern with prior art solutions. Examples of high-speed signal communication include transfer and/or sharing of data at chip-to-chip, chip-to-substrate, and board-to-board or backplane level and their converse.
The most commonly used methods of signal communication between electronic devices include making physical, electrical contact between two nodes. Electrical signals may comprise DC or AC signals or both. Alternative methods to interconnect nodes include methods of AC coupling including capacitive and inductive techniques where the DC component is not available or where the DC component would add noise or have some other unwanted effect. Further, signals may be coupled using optical methods, magnetic methods, or radio frequency transmission/reception. While digital communications between integrated circuits are of primary interest, communication involving both digital and analog signals is also needed.
Referring to FIG. 1a, a conventional apparatus of an integrated circuit (IC or chip) 10 is shown for input of a signal 14 sent from a first internal electronic application specific circuit 16 on the chip 10 to one or more pads 112. First application specific circuit 16 may be an output device or an input device such as a receiver for receiving signal 14 from an external source. Signal 14 may be digital or analog. Signal 14 is conditioned as it is propagated toward pad 112 via a buffer 18. Electrostatic discharge protection (ESD) is provided by diodes 20 which divert ESD currents to ground or power supply or other protective circuits. The protective circuits are intended to absorb and dissipate destructive energy originating from an external source coming in electrical contact with pad 112 before reaching sensitive internal application specific circuits 16.
Such apparatus 10 has limitations. Compensation is required when buffers 18 and pad 112 have different characteristics. Electrostatic discharge diodes 20 and associated protective circuits exhibit a large amount of parasitic capacitance and thus apparatus 10 introduces a large amount of capacitance into the signal path. The signal energy is absorbed by the parasitic capacitance and dissipated as heat as signal 14 is propagated toward pad 112. Generally, the amount of signal loss increases with frequency. Further, signal 14 is delayed in time as it is propagated by the chain of buffers 18. The compensation and protection thus provided lowers the energy of wanted signals 14 coming from or going between the internal circuits and the external pad and, by extension, lowers available signal levels at a far transmitter or receiver.
Prior art I/O cells involve use of protective diodes and passive and active elements to absorb and attenuate destructive voltages and currents. These typically involve active structures, which load the I/O cell. For example, it is known that a typical protection diode structure has an equivalent capacitance of approximately 1 pF. The effect of a 1 pF capacitance in the signal path of a 2 GHz signal would be an effective load of 88 ohms per wire In a differential signalling schema this would present an equivalent load of 44 ohm compared to a typical transmission impedance of 50 ohms. In other words there is more energy used (in this case) overcoming the load of the protection system than is used to send the active signals, and so the signal path requires additional amplification to compensate for the signal loss. Consequently, in our example, the system requires twice the area and consumes twice the power. While this case is a simplification, it is illustrative of the problems that the current practices involve. In fact, if an I/O system is to achieve higher data rates the problem is even worse: at twice the frequency approximately 80% of the driver's energy is consumed to overcome the load of the protection circuitry.
Referring to FIG. 1b, for conventional apparatus 10, an essentially similar apparatus may be used for input of a signal through pad 112 to one or more internal circuits 24 or to an output device for transmission of signal 14 to an external receiver.
FIG. 16a of United States Publication No. 2005/0271147 (Dupuis) entitled “Transformer isolation for digital power supply” teaches a transformer apparatus to provide isolation between two integrated circuits located in close proximity within a single component package (Dupuis FIGS. 6, 15, 15a, 16, and 16a). While Dupuis describes this as a high-speed data link, Dupuis actually uses a RF carrier that is 20 times the actual data (information) rate.
Similarly, Lane et al. in U.S. Pat. No. 7,064,442 teaches an apparatus to provide isolation between two integrated circuits located in close proximity within a single component package using a transformer, the transformer being located on a separate circuit within the same package. In this case, the external I/O signals interface directly with active electronic elements. Only for internal signals, after active electronics processing, within the package is the transformer/dielectric isolation formed and utilized.
In a similar manner as Lane et al, U.S. Pat. No. 5,952,849 (Haigh) entitled “Logic isolator with high transient immunity”, discloses an apparatus to provide isolation between two circuits using a transformer, where the transformer 38 is formed by windings 36 and 42 on separate and discrete ferrite cores coupled by winding 42.
In a similar manner as Dupuis, U.S. Pat. No. 7,075,329 (Chen et al.) entitled “Signal isolators using micro-transformers” discloses an apparatus that provides isolation between two circuits using a transformer, where the transformer is a separate and discrete component. In Chen the external I/O pads or signals labelled ‘input’ and ‘output’ are interfaced with active electronics before and after the transformer isolation occurs and thus share the disadvantages of the Dupuis, Lane, Haigh and others.
The article H. Ishikuro, N. Miura, and T. Kuroda, “Wideband Inductive-coupling Interface for High-performance Portable System”, IEEE 2007 Custom Integrated Circuits Conference (CICC) shows an inductive coupling system in which chips are designed with inductive elements which enable direct face to face chip to chip communications. In this case the inductor on chip is an individual element and not combined with an integrated second inductive element on the same IC. This reference also shows separate coils for applications outside a package. In this case, the coils are fabricated separately and interfaced conductively with drive electronics.
U.S. Pat. No. 5,361,277 (Grover) entitled “Method and apparatus for clock distribution and for distributed clock synchronization” describes a system in which the timing is coordinated such that transmitters and receivers are coordinated so that even with distant systems a common time and clocking reference is obtained. In a similar manner, U.S. Pat. No. 5,243,703 (Farmwald et al.) entitled “Apparatus for synchronously generating clock signals in a data processing system” and U.S. Pat. No. 5,954,804 (Farmwald et al.) entitled “Synchronous memory device having an internal register” describe a system in which timing is coordinated through the knowledge of clock edges following different paths. It should also be noted that the Grover and Farmwald patents describe wired systems such as direct wired memory or logic systems which further limit their systems. Wired systems as shown in the prior art are encumbered by the need for ESD structures which limit speed and increase power consumption.
U.S. Pat. No. 6,882,239 (Miller et al.) entitled “Electromagnetically coupled interconnect system” describes electromagnetic coupling between components in a test system in which the IC is contained in a package with a separate electromagnetic (EM) coupler. In general, this patent provides loosely coupled signals in which there is at least 10 dB of attenuation and further loss because of extra shielding. The goal of Miller et al. is to receive loosely coupled signals and is restricted for the case of testing and measuring other signals without major interference to those other signals which are required to be not perturbed.
U.S. Pat. No. 7,200,830 (Drost et al.) entitled “Enhanced electrically-aligned proximity communication and United States publication no. 20060224796 (Vigouroux et al.) entitled “Network chip design for grid communication” describe systems for self described ‘proximity’ communications which are close field capacitive coupling to enable the communications path. These are targeted at coupling chips capacitively to enable high speed communications, and require nearly intimate coupling contact to enable sufficient capacitive field interaction for communications.
Another form of near field interconnect package is shown in United States publication no. 20060022336 (Franzon et al.) entitled “Microelectronic packages including solder bumps and AC-coupled interconnect elements” and 20030100200 (Franzon, et al.) entitled “Buried solder bumps for AC-coupled microelectronic interconnects”. These include solder bumps and AC-coupled interconnect elements. In the same vein is U.S. Pat. Nos. 6,885,090 (Franzon et al.) entitled “Inductively coupled electrical connectors” and 6,927,490 (Franzon et al.) entitled “Buried solder bumps for AC-coupled microelectronic interconnects”. The Franzon packages are dependent on separately constructed and maintained structures. In U.S. Pat. No. 6,885,090, an essential element is to keep the structures separate because they will conduct if touching. The Franzon applications discuss a specific package technique and interconnect topology solder posts.