A typical computer system consists of several basic components, including a central processor, volatile and non-volatile memory, and various peripheral devices, including graphics controller(s), mass storage devices, and I/O devices. An I/O controller typically includes a PCI interface for expansion cards as well as a plurality of interfaces to I/O devices. An I/O controller may include various external bus interfaces, such as, for example, a PCI bus interface, or a system management bus (SMBus) (see “System Management Bus Specification,” version 2.0, hereinafter “SMBus specification”).
External system management controllers typically interface with the I/O controller using the SMBus. As defined by the SMBus specification, SMBALERT# is an input-only signal to the I/O controller. In particular, SMBALERT# is an optional signal that is an interrupt line for devices that trade their ability to master for a pin. SMBALERT# is a wired-AND signal and used in conjunction with the SMBus general call address. Messages invoked with the SMBus are two bytes long. A slave-only device, such as an external system management controller, can signal the host through SMBALERT# that it wants to talk. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through the alert response address.
Since SMBALERT# is a unidirectional signal, conventional I/O controllers cannot alert an external system management controller through the SMBus nor control the SMBALERT# output from the system management controller. Additionally, external system management controllers that capture and re-drive SMBALERT# require two separate pins on the system management controller IC. Status bits must be polled at regular intervals. If an event happens after the management controller polling cycle, it does not get detected until the next polling cycle.