1. Field of Invention
The present invention relates to a DRAM cell. More particularly, the present invention relates to a DRAM cell with enhanced capacitor area.
2. Description of Related Art
Dynamic random access memories (DRAM) cell, such as Embedded DRAM (eDRAM) cell, includes mainly a metal oxide semiconductor field effective transistor (MOSFET), and a capacitor cell. In a conventional planar type eDRAM cell, the gate dielectric layer and gate poly layer are used as a cell capacitor structure to store the signal in the inversion charge below the capacitor dielectric. Please refer to FIG. 1, a convention planar type eDRAM cell. A dielectric layer 102 such as a silicon oxide layer is formed on a silicon substrate 104. A poly layer 106 is formed on top of the dielectric layer 102 to form a capacitance between the poly layer 106 and the inversion charge region 108 in the substrate 104. The dielectric layer 102 and the poly layer 106 are patterned to form a gate structure 110 and a cell capacitor structure 112. The cell capacitor 112 provides a capacitance value proportional to the interface area between the inversion charge region 108 and the poly layer 106.
In recent years, as the cell size shrinks to keep up with the current technology evolvement, the interface area also shrinks dramatically. From the DRAM design point of view, lowering the capacitance value in a DRAM cell is undesirable, yet the physical limitations cannot be avoided with the current capacitor structure. The conventional planar type eDRAM cells suffer from low cell capacitance area due to non-scalable gate oxide thickness of the cell transistor and cell capacitor. Therefore, the cell size could not be scaled down below the N90 generation and thus expensive MiM based eDRAM needed to be used.
Various attempts to increase the capacitance of a eDRAM cell while maintaining the cell size involves further complications to the cell structure and thus suffers in integration with the current manufacturing process of an eDRAM cell. For example, U.S. Pat. No. 4,864,464 disclosed a DRAM cell capacitor with an additional dielectric layer and poly layer to form extra capacitance on top of the pre-existing dielectric layer a poly layer. However, in this case, an additional third poly layer is dedicated to make the connection between storage nodes. Also, the prior art design is not compatible with salicide process, thus requires a dedicated DRAM cell process in order to achieve the projected performance.
For the forgoing reasons, there is a need for a new DRAM cell structure and manufacturing method with higher capacitor values while having a small cell size.