This invention relates to interrupt controllers in microprocessors, and more particularly relates to processing interrupts arranged in groups on a priority basis.
Microprocessors are equipped with the capability of responding to interrupt signals that interrupt processing within the microprocessor and invoke a service routine dedicated to the handling of the event with which the interrupt is associated. A typical microprocessor architecture is shown in FIG. 1 in which can be seen a microprocessor 10 in which are a stack of registers 12, units 14 for performing fetch, decode and dispatch of instructions, execution units 16 for executing instructions, and an interrupt handler 18. The instructions and data are passed to and from external memory (not shown) on a data bus 20, and are written to or read from locations in the external memory identified by memory addresses on an address bus 22. Interrupts are communicated to the interrupt handler 18 via dedicated interrupt lines 24. An interrupt that is communicated by way of a dedicated interrupt line directly to the microprocessor interrupt handler 18 to invoke an associated service routine are called hardware interrupts. In general, the microprocessor operates in response to the cycles of a system clock (not shown).
Interrupts may be arranged in groups. For example, the occurrence of interrupts may be signaled by the setting of a bit in a register. One of such registers may be associated with packet data transfer events, for example, another with transmit and receive events, in the case of a microcontroller for a wireless base station, for example. The registers thus reflect a grouping of such interrupts. In addition, interrupts may be assigned differing priorities.
Prior art interrupt controllers handle requests among all interrupts assigned to a given hardware interrupt on a direct priority basis. This requires a very fast system response to any such interrupt request, since otherwise the system may lose track of multiple requests of the same interrupt request. In addition, such prior art interrupt controllers are not able to trace, with hardware, the event sequence within the same group of interrupt requests, which places a burden on the interrupt service routine to attempt to determine the event sequence. This creates undesired complexity in the interrupt service routine, and slows the interrupt process. In addition, such priority basis systems can have the lower priority requests of a given group significantly under-selected if higher priority requests of the same group occur more frequently.
It is therefore desired to have an improved interrupt controller that overcomes the above described deficiencies of the prior art.
The present invention provides a microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis. A priority encoder unit is included for receiving the interrupt requests stored in the storage units and providing the interrupt requests as outputs for processing by the microprocessor, on a priority basis.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.