Continuing decreases in the sizes and power requirements for electronic devices has resulted in a requirement for ever decreasing supply voltages for digital and analog circuits. For example, as more and more circuits are designed for implementation in scaled nanometer CMOS technologies, the supply voltages will continue to decrease from 1.2 V to 0.5 V. These decreasing supply voltages often have the added benefit of prolonging battery life in portable devices.
In order to address the decreasing supply voltages, it is desirable to provide circuit designs that operate on lower supply voltages.