Much of modern electronics is based upon the processing of digital signals containing information about one or more parameters of interest. A digital signal is typically a voltage that may be at any one of a plurality of discrete levels at a given point in time. The number of different levels employed is referred to as the "radix" of the system and the information contained in the signal is a function of both the system's radix and the discrete levels assumed by the voltage.
Digital systems having a variety of different radices have been developed. The most common radix for digital signals, however, is the binary radix, in which the voltage properly assumes one of two levels or states. These levels are conventionally termed "high" or "low", "true" or "false", or "1" or "0".
One of the fundamental elements of systems for processing binary digital signals is the logic gate. A logic gate typically converts one or more binary inputs into a binary output, whose level is a function both of the input levels and the particular "logic" operation performed by the gate. By employing the proper logic operation, the gate can produce a desired true/false response to the presence of binary inputs having substantially any combination of voltage levels.
A simple example of a situation in which such a logic operation might usefully be performed is provided by a manufacturing process involving the application of heat to a workpiece. Assume that a plurality of temperature sensors are employed to monitor the temperature of the workpiece at different points. Each sensor produces a high output when the temperature of the workpiece at the point monitored reaches some threshold. The sensor outputs are then transmitted to a central station for further processing by a logic gate.
To prevent the workpiece from being overheated, a logic gate that produces a high output in response to the production of a high output by any one of the sensors is employed. This high gate output then triggers an alarm, indicating that the temperature threshold has been exceeded at some point on the workpiece and allowing the operator to take corrective action. Alternatively, if the workpiece is to be uniformly heated, a different logic gate may be employed at the central station. This logic gate produces a high output only when the output of each sensor is high, indicating that the threshold temperature has been exceeded at each monitored point of the workpiece. The logic gate output then lights a display indicative of uniform workpiece heating.
To better understand the manner in which logic operations can be employed in this or other applications, a brief review of the more common operations is provided. In accordance with classic notions of Boolean algebra, there are three fundamental logic operations. These operations are commonly designated NOT, AND, and OR and can be combined to produce substantially any other logic operation.
FIG. 1A illustrates both the circuit symbol for the NOT operation, or gate, and the corresponding truth table, which indicates the output levels produced by the NOT operation for a given set of inputs. Briefly, the NOT gate, or inverter, receives a digital input A and produces an output C that is the logical inversion of the input. As a result, when the input A is low (a logic 0), the output C is high (a logic 1) and when the input A is a logic 1, the output C is a logic 0, as shown in the truth table of FIG. 1A.
FIG. 1B illustrates both the circuit symbol for the AND operation, or gate, as well as the corresponding truth table. As shown, two inputs A and B are applied to the gate, which produces an output C that is only a logic 1 when both inputs A and B are at logic 1. When either one or both logic inputs A and B are at logic 0, the output C is also a logic 0.
In FIG. 1C, the circuit symbol for the OR operation, or gate, is illustrated, along with the corresponding truth table. As shown, inputs A and B are combined to produce an output C that is a logic 1 if either or both inputs A and B are also at a logic 1. Thus, output C is only a logic 0 in the event that both inputs A and B are at logic 0.
From these fundamental logic operations, other logic operations can be produced. For example, a NAND operation can be performed by combining the AND and NOT operations described above. The circuit symbol and truth table for the NAND operation are depicted in FIG. 1D. As shown, the output C of the NAND gate is a logic 1 for all input conditions other than both inputs A and B being at logic 1.
The OR and NOT operations can also be combined to produce a NOR logic operation whose circuit symbol and truth table are shown in FIG. 1E. As shown, the output C of the NOR gate is a logic 1 only when both inputs A and B are at logic 0. Otherwise, output C of the NOR gate is at a logic 0.
Finally, in FIG. 1F, the circuit symbol and truth table for an exclusive-OR operation are shown. The output C of the exclusive OR gate is a logic 1 only when one or the other, but not both, of the inputs A and B are at a logic 1. Thus, as shown, when both inputs A and B are either a logic 0 or a logic 1, the exclusive-OR output C is at a logic 0.
As suggested previously, the various logic operations illustrated in FIG. 1 can be combined in accordance with a number of rules, laws, and theorems from Boolean algebra to perform other, more complex operations. In addition, many logic operations can be broken down into simpler operations by such algebra. Further, although the various operations or gates illustrated in FIGS. 1B through 1F are shown as having two inputs, additional inputs can be employed. For example, the AND gate of FIG. 1B could respond to four input gates, producing a logic 1 at output C only when all four inputs are at a logic 1.
Discussing now the manner in which such logic operations have traditionally been performed, a number of implementations have been adopted. For example, electromechanical arrangements have been developed employing electromagnetic relays that respond to high and low voltage levels to open and close switch contacts that further control the establishment of other voltages. Similarly, arrangements employing pneumatically controlled switch elements have been developed.
Most modern digital systems and computers, however, employ electronic circuits to perform logic functions. These circuits are typically constructed from a plurality of semiconductor devices, which can be densely packed in a relatively small space by use of integrated circuit techniques. The devices included in such semiconductor logic circuits are formed from semiconducting materials such as silicon (Si), germanium (Ge), selenium (Se), gallium arsenide (GaAs), or cadmium sulfide (CdS). Although silicon is currently the most prevalently used semiconducting material, the enhanced speed characteristics of GaAs is leading to its increased usage.
The electrical properties of these semiconducting materials may be varied by intentionally "doping," or adding impurities to them. In that regard, a donor dopant introduces additional negative charge carriers or electrons (n) into the material, while an acceptor dopant introduces additional positive charge carriers or holes (p) into the material. In the case of GaAs semiconducting materials, the donor dopant is typically silicon (Si) and the acceptor dopant is typically zinc (Zn).
The most common element of logic circuits formed from such semiconducting materials is the transistor. Transistors can be either of bipolar or unipolar design, with the unipolar arrangement being of primary interest in this context. Unipolar transistors, commonly known as field-effect transistors (FETs), can be further classified as junction field-effect transistors (JFETs) or insulated-gate field-effect transistors (IGFETs).
Addressing the IGFET construction in greater detail, as shown in FIG. 2, an IGFET includes a substrate with drain and source regions D and S formed therein. The drain and source are both doped with charge carriers of the same polarity (for example, n), while the substrate is doped with charge carriers of the opposite polarity (for example, p). A gate region G is provided over the substrate between the source and drain but is separated therefrom by an insulator or semiconductor. Although the most common construction of IGFETs is the metal-silicon dioxide-silicon, field-effect transistor (MOSFET), an arrangement frequently used with GaAs semiconductors is the metal-semiconductor, field-effect transistor (MESFET). The MESFET includes a thin film of GaAs deposited onto the transistor substrate over the channel, with a layer of metal directly deposited onto the surface of the GaAs film.
In a depletion mode of operation, the IGFET includes a channel region of material, extending between the source and drain, that is doped with charge carriers of the same polarity as the source and drain. This channel provides a current path through the IGFET. Specifically, assuming the use of acceptor dopant in the channel, with the source and substrate electrically connected and a low logic level voltage applied between the gate and source, current easily flows through the channel. Thus, the IGFET is said to be "normally ON". When a high logic level voltage is applied between the gate and source and/or the drain and source, however, the gate and drain voltages may repel charge carriers from the channel, increasing the resistance of the channel to the flow of current. In this condition, the IGFET is said to be "OFF".
In an enhancement mode of operation, the IGFET does not normally include a doped channel. Thus, the enhancement-mode IGFET is said to be normally "OFF". A channel can be formed, however, by the repulsion of charge from the substrate between the source and drain. For acceptor-doped drain and source regions, this repulsion is accomplished by applying a high logic level voltage between the gate and source. This voltage ultimately results in the formation of a region, having charge carriers similar to the source and drain, through which current can flow. In this condition, the IGFET is said to be "ON".
As will be appreciated, IGFETs can be constructed to employ either n- or p-type materials for their channels. Basically, the operation of n-channel depletion-mode and enhancement-mode transistors is the same as the p-channel operation described above. Because the polarity of the charge carriers in the channel is reversed, however, the signs of the voltages and currents defining IGFET operation are reversed.
Having reviewed the basic logic operations to be performed, as well as the structure of an IGFET component of a circuit for performing them, the manner in which such IGFET building blocks are combined to perform logic operations is now discussed. Traditionally, the semiconductor circuits that implement logic operations are known as "gates" and are grouped according to their "family". These family groupings are a function of characteristics common to each gate in the family, such as the type of elements included, in the case of transistor-transistor logic (TTL), or the manner in which the elements are connected, in the case of emitter-coupled logic (ECL).
Many of the operational characteristics of a family are important to a digital circuit designer in deciding which families to employ in a particular application. For example, the speed at which the gates of a family can perform logic operations is important in many applications. As used in this context, speed collectively refers to propagation time and rise and fall time. The propagation time of a logic gate is the interval of time required for a change in the logic level at an input of the gate to produce a change in the logic level at the gate's output. The rise and fall times of the gate correspond to the times required for the output of the gate to change from a low level to a high level and from a high level to a low level, respectively.
Another important characteristic of a logic family is the amount of power dissipated in its elements. Power dissipation affects the size of power supply required to operate the gates and leads to the undesirable heating of components. Higher component temperatures may, in turn, affect gate performance or limit the integration level of the devices. Power consumption for gates in most families is on the order of milliwatts and, for the reasons outlined above, is preferably as low as possible.
The manner in which a logic gate interfaces with other gates or elements is also important to the circuit designer. As discussed, the logic gate produces an output that is a function of several inputs. The number of inputs that can be applied to the gate is referred to as its fan-in. Similarly, the fan-out of the gate is an indication of the number of unit logic gates that the gate can drive.
Another important characteristic of the logic gate is its noise immunity. This term refers to the gate's ability to avoid erroneous operation that might otherwise occur if, for example, the high-frequency noise produced by high-speed circuits caused the gate to misinterpret an input logic level. One measure of the noise immunity of a gate is its noise margin. Noise margin is basically the difference in the definition of logic levels at the input and output terminals of the gate.
As a simple illustrative example of noise margin, assume that the logic gate interprets any inputs below one volt to be a logic 0 and any inputs above four volts to be a logic 1. In contrast, the gate produces a logic 0 output that is always less than one-half volt and a logic 1 that is always greater than four and one-half volts. Provided that less than one-half volt of noise is introduced between the output of a first logic gate and the input of a subsequent gate, a logic 0 will still be recognized as a logic 0 and a logic 1 will still be recognized as a logic 1. Thus, erroneous operation will not occur. A gate constructed in this manner has a noise immunity of one-half volt.
Although perhaps somewhat less important than the factors noted above, there are a number of additional characteristics of a family of logic gates that may be of interest. For example, the temperature stability and process spread of the gate are generally important. Similarly, the complexity, or number of devices required to produce a gate, can be significant to the circuit designer. Further, factors including circuit reliability, the number of devices that can be integrated into a given area of a semiconductor substrate, and the yield, or percentage of integrated devices that are ultimately usable, can be important.
A number of different logic family designs have been developed to improve these various GaAs logic family characteristics. One such design is the direct-coupled FET logic (DCFL) family shown in FIG. 3A. The NOR gate illustrated includes two enhancement-mode transistors T1 and T2 and one depletion-mode transistor T3. The source terminals of transistors T1 and T2 are coupled to ground. Inputs A and B are applied to the gate terminals of transistors T1 and T2, respectively. The drain terminals of transistors T1 and T2 are coupled to the gate and source terminals of transistor T3, all of which define an output C. The drain terminal of transistor T3 is coupled to the supply voltage V.sub.DD.
In operation, the depletion-mode transistor T3 is always ON, by virtue of its interconnected gate and source terminals, and operates as a current source. The enhancement-mode input transistors T1 and T2 are normally OFF, preventing the flow of current from source transistor T3 to ground. Because source transistor T3 itself provides little resistance to the flow of current, the output C rises or is "pulled" to a high logic level (roughly V.sub.DD). Output C remains at this logic level until one or both of the inputs A and/or B are at a high logic level, causing the input transistors T1 and/or T2 to turn ON. At that point, there is little resistance between the output C and ground, and output C is pulled to a low logic level near ground. As will be appreciated from FIG. 1E, such operation is in accordance with standard NOR logic.
The DCFL family has "medium" speed characteristics, achieving roughly a 1500 megahertz flip-flop toggle rate. In addition, gates in the family exhibit low power consumption on the order to 0.2 to 0.4 milliwatt per gate. The family also has relatively poor noise margin characteristics and offers limited complexity.
As shown in FIG. 3B, a gate from a buffered MESFET logic (BFL) family adds to the basic DCFL configuration a buffered output section. This output section includes an enhancement-mode transistor T4, a depletion-mode transistor T5, and a diode D1. While the basic operation of this NOR gate is the same as that of the NOR gate illustrated in FIG. 3A, the pull-up transistor T4 loads the gate and its size influences both the power dissipation and speed of the gate. The diode D1 adds a voltage drop between the source V.sub.DD and the output C so that the logic levels of the output C are within the thresholds of the next gate.
As will be appreciated from a comparison of FIGS. 3A and 3B, the BFL gate is more complex than DCFL gate. In addition, the BFL family consumes more power. The BFL family does, however, advantageously accommodate a higher fan-out and exhibits a good noise margin. Further, BFL gates are relatively insensitive to processing and power supply variations.
A third logic family employing depletion-mode and enhancement-mode field effect transistors in the low-power FET logic (LPFL) family. As shown in FIG. 3C, an LPFL NOR gate adds to the BFL NOR gate of FIG. 3B, another depletion-mode transistor T6, coupled between the source terminals of transistors T1 and T2 and ground. This additional transistor T6, like transistor T3, operates as a current source. The basic operation of the LPFL NOR gate is the same as the BFL NOR gate. While the power requirements of the LPFL family are significantly less than those of the BFL family, LPFL may be slower than BFL.
As will be appreciated from the preceding remarks, it would be desirable to produce a logic family employing enhancement- and depletion-mode FETs and having, for example, improved speed, power consumption, noise margin, and fan-in and fan-out characteristics.