During turn-off of an IGBT, the voltage (VCE) across the collector (C) and emitter (E) terminals of the IGBT often overshoots beyond its nominal value. Such VCE turn-off overshoot reduces the safety margin of IGBT operation and can lead to immediate destruction of the IGBT once the maximum VCE breakdown voltage rating is exceeded. A key factor in reducing the VCE turn-off overshoot is reducing the time rate of rise (diC/dt) of the collector current IC during turn-off. However, diC/dt during turn-off is difficult to control. This is particularly true for trench-gate IGBTs in which the insulated gate is disposed in a trench formed in a semiconductor material such as Silicon. Trench-gate IGBTs have significantly higher internal capacitance compared to planar-gate IGBTs. This internal capacitance stores charges during turn on of the IGBT, and these charges must be removed during turn off of the IGBT. The high internal capacitance of the IGBT makes it more difficult to control IGBT turn off, and therefore more difficult to reduce VCE overshoot without significantly reducing efficiency.
There are five main approaches to reduce VCE turn-off overshoot for trench-gate IGBT. In a first approach, the turn-off gate resistor RGOFF is increased. This approach uses a higher gate resistor during the IGBT turn-off process. One disadvantage of this approach is the entire turn-off process is slowed down, leading to significant increase in turn-off loss EOFF.
In a second approach, the turn-off gate voltage is adjustable. This approach uses a different gate voltage below the threshold voltage to reduce the discharge rate of the gate during turn-off. One disadvantage of this approach is the entire whole switching process is slowed down, leading to significantly increased turn-off loss EOFF.
In a third approach, active voltage clamping is used. This approach use collector voltage feedback to turn-on the gate momentarily when VCE exceeds a predefined level during the turn-off process. One disadvantage of this approach is voltage feedback from the collector of the IGBT is needed, which leads to reliability problems for high-voltage IGBT applications. In addition, this approach does not control or reduce turn-off dIC/dt.
In a fourth approach, dynamic voltage rise control (DVRC) is used. DVRC uses one or more capacitors to sense the collector voltage and uses the sensed signal to turn-on the gate momentarily when dVCE/dt exceeds a predefined level during the turn-off process. One disadvantage of this approach is voltage feedback from the collector of IGBT is needed, which leads to reliability problems for high-voltage IGBT applications.
In a fifth approach, di/dt control is implemented by emitter inductance voltage feedback. This approach utilize the emitter stray inductance to generate the diE/dt voltage signal, which is added to the gate voltage and functions as negative feedback to the gate voltage when IE is falling. A Zener diode and/or resistor network may be added to clamp or adjust the feedback voltage. This approach is useful in reducing VCE overvoltage after short-circuit, when very high current has to be turned-off with high diE/dt, by substantially reducing the turn-off diE/dt achieved with high gain in the feedback loop, at the expense of increase turn-off time and thus turn-off loss EOFF. When using this technique to reduce turn-off VCE overshoot during normal operation, since the feedback action is active throughout the current fall time tF (voltage overshoot period), it will increase the fall time tF and EOFF quite significantly, which is often not acceptable for normal operation.