1. Field of the Invention
The invention relates generally to the field of semiconductors. More particularly, the invention relates to a low voltage electrostatic discharge clamp.
2. Discussion of the Related Art
Electrostatic discharge (ESD) is an important reliability concern for most classes of integrated circuits. In order to protect the circuit core, a circuit designer may use a protective element connected in parallel with the circuit, connecting an input/output (I/O) pad to the ground. However, providing an ESD protection element that is able to shunt high levels of ESD current while maintaining low clamping voltages, that uses a relatively small area, and that is compatible with exciting IC process technologies is particularly challenging.
An ESD protection element must provide a high level of protection with minimum parasitic loading area. Additionally, an ESD protection device is required to exhibit a failure current that is large and that properly scales with the area of the protection device itself.
An unsatisfactory approach to protecting a circuit from ESD includes utilizing a floating-body n-channel metal-oxide semiconductor (NMOS) device. Floating-body NMOS transistors may be used as ESD clamps and usually present good ESD protection. Nevertheless, problems with this technology include a high direct leakage current (DC leakage) and greater susceptibility to latch-up. In the case of an NMOS transistor, for example, DC leakage may be in the form of an undesirable current from the drain to the source. Latch-up may occur, for example, when the parasitic thyristor structures formed by the NMOS and adjacent devices are inadvertently triggered.
Thus, there is need for a device which presents good ESD protection characteristics with low DC leakage and high latch-up immunity.