1. Field of the Invention
The present invention relates to a technique for generating sampling clocks which are synchronized with analog video signals input from a computer or the like.
2. Description of Related Art
Video signals which are output from an engineering work station, a personal computer or a display terminal of a computer are output as an signal based on dots which correspond to picture elements on a display screen.
In the prior art, the video signals are converted to a digital signal, and then the digital signal is subjected to various kinds of image processing such as conversion processing of a signal format such as a field frequency, an aspect ratio, etc., enlargement and reduction processing, frame composite processing, geometric conversion processing, etc. by using a memory, an operation processing circuit, etc.
In order to perform such digital signal processing as described above, A/D conversion processing is used for converting analog video signals to digital data.
The analog video signals are sampled and converted to digital data by an A/D converting circuit at a timing which is determined on the basis of the sampling clocks. Therefore, the phase of the sampling clocks must be perfectly synchronized with the phase of the dots on the video signals (hereinafter referred to as “dot phase”) when the analog video signals are sampled and converted to the digital signal by the A/D converting circuit.
If the phase of the sampling clocks is not accurately coincident with the dot phase, picture elements frequently occur that have obscure intermediate gradation at an edge portion corresponding to a shift from white to black or from black to white, resulting in degradation in image quality. The degradation in image quality is particularly apparent when characters or fine patterns are displayed.
In general, the frequency of the dots on the video signals (hereinafter referred to as “dot frequency”) is set to an integer multiple of the horizontal scanning frequency of a display. Therefore, in the prior art, those signals which are synchronized in phase with horizontal synchronizing signals and have the frequency of the integer multiple of the horizontal scanning frequency are generated by a PLL (Phase Locked Loop) circuit, thereby generating sampling clocks which are synchronized with the phase of the dot phase of the dot frequency.
As described above, the sampling clocks are controlled to be synchronized with the horizontal synchronizing signals by the PLL. However, actuality, the phase of the sampling clocks generated on the basis of the synchronizing signals is not always synchronized in phase with the dot phase due to the processing delay of a synchronizing separating circuit for separating the horizontal synchronizing signals from the video signals (when the synchronizing signals are transmitted while superposed on the video signals), the difference in processing delay between the horizontal synchronizing signals and the video signals which are normally processed in a different system, or the variance between the length of a transmission cable for transmitting the horizontal synchronizing signals and the length of a transmission cable for transmitting the video signals (when the synchronizing signals are transmitted independently from the video signals). Therefore, in this case, the phase of the sampling clocks or the synchronizing signals is required to be delayed through a delay line, thereby adjusting the sampling clock phase.
Recently, display video signals in an engineering work station, a personal computer, etc. have been improved in resolution and fineness, and this improvement promotes increasing of the dot frequency up to about 150 MHz . Such an improvement in resolution and fineness for the video signals is expected to be further promoted. Further, the adjustment of the sampling clock phase as described above must be performed with sufficient precision which corresponds to about at least one-tenth of the dot period time. For example, for the dot frequency of 100 MHz , the adjustment must be performed with 1-ns level precision.
Such a phase adjustment is needed every time a device for outputting the video signals and the synchronizing signals to be sampled is replaced by another, or when the horizontal scanning frequency or the dot frequency of the input video signals is varied.
Therefore, in the conventional device, an operator must adjust the sampling clock phase while seeing a display image or the like on a screen every time the input video signals are changed.
Furthermore, as a sampling-phase adjusting manner, it may be considered to beforehand check the adjustment amount of the sampling clock phase for all the video signals which are possibly input, and vary a set value in accordance with the change of the input video signals. However, even in this case, the operator must perform the phase adjustment as described above for all the video signals while seeing a display image on the screen when adjustment for installation is performed or new signals are reviewed.
That is, the conventional technique for the adjustment of the sampling clock phase has various problems in that the adjustment of the sampling clock phase is cumbersome, it is inconvenient to users and the adjustment for installation requires a long time.