Large high-performance very large scale integration (VLSI) chips have an internal clock that is a function of an external clock. Associated with the internal clock is an internal cycle time. The internal clock cycle time comprises several components, such as (1) delays associated with storage devices on the chip, (2) clock skew, (3) logic evaluation, and (4) signal transmission. Of these four components only the logic evaluation component performs real work, the other three components are overhead that merely add to the cycle An internal clock signal is distributed to the circuits in a chip through some form of distribution network. Clock skew within a chip is the variability in the time that the internal clock signal reaches various parts of the circuit. The main contributors to clock skew are (1) the resistance and capacitance (RC) transmission delay variations, (2) device variations and, (3) localized loading variations.
Clock skew has in the past been a relatively small portion of the cycle time. But as cycle times decrease, that proportion of the clock skew to the cycle time has dramatically increased due to both the base technology and to the increase in typical chip sizes. In addition to clock skew's effect on a circuit's cycle time, the delay between a circuit's external clock and its internal clock in proportion to cycle time has been increasing, which makes interfacing difficult. Conventional techniques for controlling this delay are also limited by clock skew since they rely on sampling the internal clock.
Current techniques to control clock skew focus on controlling the RC variations by equalizing the routing loading and/or distance, and by controlling the loading variations by adding dummy loads to equalize the load capacitance of the distribution network. These techniques are limited in their effectiveness by both the precision to which they can equalize loads and distance, and by ignoring the device (both transistor and line) variations.
Accordingly, what is needed is a system and method for reducing the clock skew in a clock distribution network. The present invention addresses such a need.