1. Field of the Invention
The present invention relates generally to circuits made using transistors, and particularly to buffers made using transistors for coupling a circuit operating at a low voltage to a circuit operating at a high voltage, or vice versa.
2. Description of the Related Art
There is a continuing need in the art of electronics to increase the number and decrease the size of transistors in integrated circuit (IC) chips to obtain greater complexity, functionality, computational power, and performance speed. There is also a continuing need to reduce the power consumed by IC chips due to increases in the number of transistors fabricated on such IC chips, and due to market demands for highly reliable and battery operated integrated circuitry. These various needs have prompted the development of mixed voltage integrated circuitry, wherein a circuit operating at a low voltage (LV.sub.DD) is coupled to a circuit operating at a high voltage (HV.sub.DD).
Such mixed voltage integrated circuitry typically includes an output buffer having an input coupled to an output of the circuit operating at LV.sub.DD, and having an output coupled via a bus to an input or output of the circuit operating at HV.sub.DD. An input buffer for the circuit operating at LV.sub.DD is also coupled to the bus in some instances.
Many conventional output buffers operate improperly or fail structurally when used in mixed voltage integrated circuitry. Signals at HV.sub.DD received at the output of a conventional output buffer can forward bias a drain/body semiconductor junction of a transistor or transistors in the output buffer. Further, a signal at HV.sub.DD on the bus can trigger a latch-up of these transistors. Such latch-up typically results in erroneously asserted signals at output and high leakage currents, and sometimes causes structural failure of the output buffer. Further, such latch-up can bum an IC Chip on which the output buffer is fabricated.
One type of conventional output buffer used in mixed voltage integrated circuitry includes a field effect transistor (FET) fabricated within a well that switches from receiving LV.sub.DD from an LV.sub.DD supply to receiving HV.sub.DD from a signal at HV.sub.DD on the bus. This type of well is commonly called a "floating well" because the voltage of the well can rise along with the voltage on the bus. A floating well typically is implemented in an output stage FET that drives the bus, as follows. The well and source of the output stage FET are coupled together using a first diode. The well and drain of the output stage FET are coupled together using a second diode. Finally, the well of the output stage FET is coupled to the source of a pre-output stage FET that drives the gate of the output stage FET.
A floating well is difficult to implement properly because the switching time for the floating well is highly dependent on layout pattern and operation of the diodes and transistors in the output and pre-output stages, and on the impedance of the bus and circuitry coupled to the bus. Further, the diodes used typically must have a low cut-in voltage for the floating well to operate properly. Fabrication of such diodes requires an expensive additional manufacturing procedure.
There is thus a continuing need for an improved output buffer for use in mixed voltage integrated circuitry. Such an output buffer should preferably be able to couple a circuit operating at LV.sub.DD to a circuit operating at HV.sub.DD, and preferably should not suffer the device failure and improper operation encountered in conventional output buffers. Further, such an output buffer should preferably be easy to manufacture, operate quickly and reliably, and be highly tolerant to signals at HV.sub.DD received from the bus or other circuitry.