Most modern systems have well defined operating states, or modes of operation and most of these systems use one or more frequency synthesizers to generate multiple output signals of different frequencies. Typical high performance frequency synthesizers utilize a phase locked loop (PLL) that is locked to the frequency of a crystal oscillator. In order to reduce the silicon area required to implement multiple frequencies, a single PLL frequency synthesizer employing multiple fractional frequency dividers at the output of the PLL frequency synthesizer is commonly used in order to provide the required output frequencies.
In the prior art, generating multiple output frequencies from a single PLL frequency synthesizer requires the use of multiple fractional frequencies dividers at the output of the PLL. Fractional frequency dividers are known to generate undesirable spurs in the output signal of the fractional frequency divider. While techniques are known in the art to enhance the spur compensation in the fractional frequency dividers, regardless of the whether the fractional frequency divider is positioned within the PLL feedback path or after the PLL, as a post-divider, the circuitry required for spur compensation can be very challenging to design. In addition, calibration algorithms and associated circuitry consume a large amount of die area, thus minimizing any benefits of using fractional frequency dividers at the output of the PLL to avoid multiple on-chip PLLs.
Accordingly, what is needed in the art is a compact, power efficient, system and method for generating multiple frequencies that are fractionally related to a reference signal and also have adequately suppressed spurs in the output spectrum.