The present invention relates a method and apparatus for controlling the ramp rate at which a high voltage from a charge pump of a non-volatile memory array device supplies the increased voltage to sectors of the non-volatile memory array. The present invention also relates to a method and apparatus for limiting the amount of current supplied to each sector of non-volatile memory cells in the event one or more cells in a sector are defective.
Non-volatile memory arrays using memory cells having floating gate to store charges thereon to control the flow of current in a channel beneath the floating gate are well known in the art. Typically, because the memory cell is programmed or erased by subjecting the electrons to a high voltage, an onboard high voltage pump is needed. However, a high voltage pump has a limited amount of current-carrying capacity.
Heretofore, it is also well known to divide a non-volatile memory array into a plurality of sectors of memory cells. Each sector comprises a plurality of memory cells arranged, typically, in one or more rows with a word line in a row connecting the control gates of the memory cells. However, it is not intended by this invention to limit to those memory arrays of the type wherein a word line connects the control gates of the memory cells in the same row line. It is also well known to provide redundant sectors of memory cells. Thus, in the event a sector of memory cells is or becomes defective, a spare or redundant sector of memory cells is used in place of the defective memory cells. Typically, a failure condition results in the memory incapable of storing charges caused by a xe2x80x9cshortxe2x80x9d. This means that if a high voltage were applied to the memory cells of the defective sector, a short occurs and a large amount of current would flow through the defective memory cell(s) of the sector. This clearly is undesirable because there would not be enough current from the charge pump to operate the other sectors and the redundant sectors which are placed into operation, because typically a charge pump boosts the voltage supplied externally to the chip and generates an internal high voltage, which is current limited.
Referring to FIG. 1 there is shown a block level diagram of a non-volatile memory device 10 of the prior art to which the control circuit of the present invention may be used. The non-volatile memory device 10 comprises an array 12 of non-volatile memory cells, divided into a plurality of sectors, designated as S1, S2 . . . Sn, each having a word line connected thereto. A row decoder 18 and a column decoder 16 receive address signals from an address bus (not shown) and decode the signals and access the particular memory cell(s) from the array 12. A sense amplifier 20 receives signals from the array 12, and provides the output from the device 10. Finally, a high voltage charge pump 14 generate a high voltage which is supplied to each sector, S1, S2, . . . Sn, through its respective word line.
In the prior art, it is also known to provide circuitry to limit the current flow into each sector thereby assuring that even if a sector had defective memory cells, the shortage created thereby would not draw an overwhelming large amount of current from the charge pump. Referring to FIG. 2, there is shown a prior art control circuit 30 interposed between the high voltage charge pump 14 and the word line of each sector. As can be seen, the control circuit 30 of the prior art required a large number of transistors. Such transistors take up valuable real estate in the integrated circuit memory array. Accordingly, it is desirable to reduce the number of transistors in such a control circuit 30 while at the same time performing the desirable function of limiting the current flowing into a defective sector.
Accordingly, in the present invention, a control circuit for a non-volatile memory array distributes a first voltage to a plurality of sectors with each sector having a plurality of non-volatile memory cells connected by a line. The control circuit has a plurality of first transistors with each transistor having a first terminal, a second terminal and a channel therebetween, and a gate for controlling the flow of the current between the first and second terminals. The first terminal of each first transistor is connected to the line of a different sector. The second terminals of the plurality of first transistors are all connected together to receive the first voltage. A second transistor has a first terminal, a second terminal and a channel therebetween and a gate for controlling the flow of current between the first and second terminals. The first terminal of the second transistor is connected to the second terminals of the plurality of first transistors. The gate of the plurality of first transistors and the gate of the second transistor are connected together and to the second terminal of the second transistor. A current limiter circuit is connected to the second terminal of the second transistor for limiting the current supply to the plurality of sectors.
The present invention also relates to a distribution circuit which control the rate of the voltage supplied to each sector depending upon the capacitance within the sector, the voltage from the charge pump, the width to length ratio of the first and second transistors and the current from the current limiter.