1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly relates to a technique for remedying defective bits caused in fabrication process steps.
2. Description of the Prior Art
Flash EEPROMs have been known as one type of electrically rewritable nonvolatile semiconductor memory devices. Flash EEPROMs are capable of simultaneously erasing a plurality of memory cells and an erase time can be reduced. Therefore, flash EEPROMs have been widely used in memory cards and the like.
In a flash EEPROM, a write/erase time varies among EEPROM cells. According to a known technique, depending on locations in a memory cell array, a threshold voltage set for each memory cell is made to be variable. This allows reduction in variation in characteristics of memory cells due to the locations of the memory cells and thus improvement of the reliability and write speed of a semiconductor memory device can be achieved (see United States Patent Application No. 2007/0064482A1).
As the capacity of flash EEPROMs has been increased more and more, the problem of reduction in yield arose. Specifically, due to causes in fabrication process steps for fabricating a large capacity flash EEPROM, some completed products in which a specific EEPROM cell requires a long write/erase time than that of a normal EEPROM cell are fabricated. Such products are judged as defectives in a test process step before shipping, so the yield of the flash EEPROM is reduced.
To cope with this problem, a technique in which a redundant circuit is provided to improve a fabrication yield has been used. Specifically, according to the technique using a redundant circuit, besides a normal memory cell array (regular memory cell array), an auxiliary memory cell array, for example, for remedying a defective row of the regular memory cell array and an auxiliary address decoder (programmable decoder) for performing row selection in the auxiliary memory cell array are provided on the same semiconductor chip. Thus, defective cells in the regular memory cell array, which have been found in a test process step in a fabrication stage, are remedied.