1. Field of the Invention
The present invention relates in general to a non-volatile memory cell and method for fabricating the same. More particularly, it relates to a vertical nitride read-only memory (NROM) cell and method for fabricating the same.
2. Description of the Related Art
In the non-volatile memory industry, the development of nitride read-only memory (NROM) started in 1996. The new non-volatile memory technology utilizes oxide-nitride-oxide (ONO) gate dielectric and known mechanisms of program and erase to create two separate bits per cell. Thus, the NROM bit size is half of the cell area. Since silicon die size is the main element in the cost structure, it is apparent why the NROM technology is considered an economical breakthrough.
FIG. 1 is a cross-section showing a conventional NROM cell structure. This cell includes a silicon substrate 100 which has two separated bit lines (source and drain) 102, two bit line oxides 104 formed over each of the bit lines 102, respectively, and an ONO layer 112 having a silicon nitride layer 108 sandwiched between bottom silicon oxide layer 106 and top silicon oxide layer 110 formed on the substrate 100 between bit line oxides 102. A gate conductive layer 114 (word line) lies on the top of the bit line oxides 104 and the ONO layer 112.
The silicon nitride layer 108 in the ONO structure 112 has two chargeable areas 107 and 109 adjacent to the bit lines 102. These areas 107 and 109 are used for storing charges during memory cell programming. To program the left bit close to area 107, left bit line 102 is the drain and receives the high programming voltage. Simultaneously, right bit line 102 is the source and is grounded. The opposite is true for programming area 109. Moreover, each bit is read in a direction opposite its programming direction. To read the left bit, stored in area 107, left bit line 102 is the source and right bit line 102 is the drain. The opposite is true for reading the right bit, stored in area 109. In addition, the bits are erased in the same direction that they are programmed.
Increasing cell density for integration of ICs requires reducing the bit line area or shrinking the width of the ONO layer. Unfortunately, reducing bit line area may increase the resistance of the bit line, and results in lowered operating speed of the memory cell. In addition, shrinking the gate length may induce cell disturbance during program, erase, or read, in particular, when width of the gate length is less than 10 nm. Therefore, the cell density is limited.