A semiconductor memory device may include a memory cell array region and a peripheral circuit region, and signal lines may be arranged on two layers above these regions. An electrode to apply a voltage for the memory cells may be arranged between the memory cell region and the signal lines. Word lines are arranged above the electrode, and column selecting lines are arranged above the word lines.
A conventional semiconductor memory device, however, may have a voltage difference between a voltage applied to the electrode and a voltage applied to the word lines. Accordingly, a leakage current may flow from the electrode to the word lines if defects occur in a dielectric between the electrode and the word lines.
FIG. 1 is a block diagram illustrating a memory cell array of a conventional semiconductor memory device and a method of arranging signal lines thereof. In FIG. 1, 10 denotes a memory cell array, CJ denotes junction regions, SWD denotes sub word line driver regions, SA denotes sense amplifier regions, and SMCA denotes sub memory array regions. MC denotes memory cells, BL denotes a bit line, PXL denotes word selecting signal lines, NWL denotes main word lines, SWL denotes sub word lines, CSL denotes column selecting signal lines, LIO denotes local data I/O lines, and GIO denotes global data I/O lines.
In the memory cell array 10 of FIG. 1, blocks which include the junction region CJ, the sub word line driver region SWD, the sense amplifier region SA, and the sub memory cell array region SMCA are repeatedly arranged in transverse and vertical directions. A sub memory cell array is arranged in the sub memory cell array region SMCA. A control signal generating circuit that controlls a sub word line driver and a control signal generating circuit that controlls a sense amplifier are arranged in the junction region CJ. Sub word line drivers are arranged in the sub word line driver region SWD, and the sense amplifier is arranged in the sense amplifier region SA. Functions of the components and signal line arrangements of the semiconductor memory device of FIG. 1 will be explained below.
Each sub memory cell array region SMCA includes a memory cell MC connected between a sub word line SWL and a bit line BL to write/read data to/from the selected memory cell MC. The sense amplifier of the sense amplifier region SA amplifies data of the bit line. The sub word line driver region SWD combines signals transmitted to a word selecting signal line PXL and a main word line NWL to select the sub word line.
The sub word line is arranged in a vertical direction, and the bit line BL is arranged in a transverse direction. The column selecting signal line CSL is arranged in the same direction as the bit line to cross over the sense amplifier region SA and the sub memory cell array region SMCA, and the main word line is arranged in the same direction as the sub word line SWL to cross over the sub word line driver region SWD and the sub memory cell array region SMCA. The word line selecting signal line PXL is arranged in the same direction as the sub word line SWL to cross over the junction region CJ and the sense amplifier region SA.
FIG. 2A is a block diagram illustrating an embodiment of the sub memory cell array region SMCA and the sense amplifier region SA of the conventional memory device of FIG. 1. FIG. 2A shows that two word selecting signal lines PX1 and PX2, and two word selection signal lines PX3 and PX4 are respectively arranged on left and right sides of the sub memory cell array region SMCA. Two-least significant bit (LSBs) row addresses among row addresses are decoded to select the word selecting signal lines PX1 to PX4, and the remaining-LSB row addresses among the row addresses are decoded to select the main word lines NWL1 to NWLi, etc.
FIG. 2B is a block diagram illustrating an alternative sub memory cell array region SMCA and the sense amplifier region SA of the conventional memory device of FIG. 1. The configuration of FIG. 2B is the same as that of FIG. 2A except that a bit line pair BL1, BL1B arranged to cross over the sub memory cell array region SMCA is twisted.
In FIGS. 2A and 2B, respective sub word lines SWL11 to SWL14 are selected by combining respective signals transmitted through the word selecting signal lines PX1 to PX4 and a signal transmitted to the main word line NWL1, and respective sub word lines SWLi1 to SWLi4 are selected by combining respective signals transmitted through the word selecting signal lines PX1 to PX4 and a signal transmitted to the main word line NWLi. Each of the memory cells MC11 to MC14 are connected between each of the sub word lines SWL11 to SWL14 and one of the bit line pair BL1, BL1B. Each of the memory cells MCi1 to MCi4 are connected between each of the sub word lines SWLi1 to SWLi4 and one of the bit line pair BL1, BL1B.
Pre-charge circuits PRE1 and PRE2, bit line isolation gates ISOG1 and ISOG2, and a bit line sense amplifier BLSA are connected between the bit line pair BL1, BL1B. An I/O gate IOG is connected between the bit line pair BL1, BL1B and a local data I/O line pair LIO1, LIO1B. A local global I/O gate LGIOG is connected between the local data I/O line pair LIO1, LIO1B and a global data I/O line pair GIO1, GIO1B. Functions of the components of FIGS. 2A and 2B will be explained below.
The pre-charge circuits PRE1 and PRE2 precharge the bit line pair BL1, BL1B. Each of the bit line isolation gates ISO1 and ISO2 separates the bit line pair BL1, BL1B. If a memory cell on the left side of the bit line pair BL1, BL1B is selected, the bit line isolation gate ISO1 is turned on, and the bit line isolation gate ISO2 is turned off. If a memory cell on the right side of the bit line pair BL1, BL1B is selected, the bit line isolation gate ISO1 is turned off, and the bit line isolation gate ISO2 is turned on. The bit line sense amplifier BLSA senses and amplifies data of the bit line pair BL1, BL1B. The I/O gate IOG transmits data between the bit line pair BL1, BL1B and the local data I/O line pair LIO1, LIO1B, and the global I/O data gate LGIOG transmits data between the local data I/O line pair LIO1, LIO1B and the global data I/O line pair GIO1, GIO1B.
Even though the local data line pair LIO1, LIO1B appear to be arranged above the memory cell array 10 in a transverse direction, the local data line pair LIO1, LIO1B is actually arranged in a unit of a predetermined number of sub memory cell array regions SMCA which are arranged in a vertical direction.
FIG. 3A shows a signal line arrangement of the semiconductor memory device of FIG. 2A. In FIG. 3A, a plate poly PP covers the whole surface of the memory cell array 10. The word selecting signal lines PX1 to PX4 are arranged in a vertical direction, the main word lines NWL1 to NWLi, etc., and the local data I/O lines LIO are arranged on a first layer, and power lines P1 are arranged between the word selecting signal lines PX1 to PX4. Column selecting signal lines CSL1 are arranged in a transverse direction, and the global data I/O lines GIO1 are arranged on a second layer. A power line P2 is arranged between the column selecting signal line CSL1 and the global data I/O line GIO.
FIG. 3B shows a signal line arrangement of the semiconductor memory device of FIG. 2B. In FIG. 3B, a power line P1 is additionally arranged in a central region in which the bit line pair of the sub memory cell array region SMCA arranged in a vertical direction is twisted.
That is, in the semiconductor memory device of FIG. 2B, the main word line pairs NWL1 to NWLi, etc. are not arranged in a central region in which the twisted bit line pair is arranged. Accordingly, the power line P1 is additionally arranged in this region. A signal line may also be arranged in this region.
A dynamic memory cell MC of FIGS. 2A and 2B includes one capacitor and one transistor. One side of the capacitor is connected to the transistor, and the other side is connected to the plate poly PP. One half of an array inside power voltage is applied to the plate poly PP; a high voltage VPP is applied to one of the word selecting signal lines PX1 to PX4 and one of the main word lines NWL1 to NWLi, etc. which are selected when it is in active status; and a ground voltage or a voltage of lower level than a ground voltage is applied to the remaining word selecting signal lines PX1 to PX4 and the remaining main word lines NWL1 to NWLi, etc. which are not selected. When it is in standby status, a ground voltage or a voltage of lower level than a ground voltage is applied to all word selecting signal lines PX1 to PX4 and all main word lines NWL1 to NWLi, etc.
Thus, the plate poly PP and the word selecting signal lines PX1 to PX4 and the main word lines NWL1 to NWLi, etc. are arranged closely, and a dielectric provided between these lines may be relatively thin. Leakage current may thus flow between the plate poly PP and the word selecting signal lines PX1 to PX4 and the main word lines NWL1 to NWLi, etc. due to dielectric defect(s).
That is, leakage current may flow from the plate poly PP to which (array inside power voltage)/2 is applied in active or standby status to the word selecting signal lines PX1 to PX4 and the main word lines NWL1 to NWLi, etc. to which a ground voltage or a voltage of lower level than a ground voltage is applied. A voltage applied to the plate poly PP may thus be lower than the (array inside power voltage)/2, thereby adversely affecting operation of the semiconductor memory device.