As the integration density of integrated circuit memory devices has increased, research into materials that have a high dielectric constant, such as Ta2O5, BST, and PZT, for use as a dielectric layer in an integrated circuit memory device capacitor has increased. Conventionally, polysilicon has been used as a storage node and a plate node of a capacitor. However, a high dielectric constant layer typically interacts with polysilicon, such that oxygen atoms in the dielectric layer penetrate into the polysilicon, which may degrade electrical properties of the capacitor. Also, when an electrode comprises polysilicon, leakage current may increase due to polysilicon's small work function. For this reason, extensive studies have been made in which a noble metal, such as Ru and Pt, is used in place of polysilicon as a capacitor electrode of an integrated circuit memory device.
Forming a memory device, such as a DRAM, that has a capacitor electrode that comprises a noble metal typically involves a hydrogen alloy process. Memory device capacitors that include an electrode that comprises a noble metal, such as, for example, metal-insulator-metal (MIM) capacitors and/or a metal-insulator-silicon (MIS) capacitors, a catalytic action of the noble metal may allow hydrogen ions to penetrate into the dielectric layer of the capacitor. The hydrogen penetrates into the dielectric layer and may degrade electrical properties of an interface between electrodes and the dielectric layer of the capacitor.
Aluminum oxide (Al2O3) may be deposited on a capacitor as a hydrogen barrier layer to inhibit penetration of hydrogen into the dielectric layer as is disclosed in U.S. Patent Publication No. 2002/0074588 entitled “Ferroelectric Capacitors for Integrated Circuit Memory Devices and Methods of Manufacturing the Same,” published in Jun. 20, 2002, by inventor Kyu-Mann Lee. The technique of depositing aluminum oxide on a capacitor as a hydrogen barrier layer may, however, cause contact resistance to increase during a subsequent etching process for forming a metal contact hole.
FIGS. 1 and 2 are cross-sectional views that illustrate a method of forming a conventional capacitor that includes electrodes that comprise a noble metal. Referring to FIG. 1, a transistor (not shown) and a bit line 14 are formed on a semiconductor substrate 10, and then a first interlayer dielectric (ILD) layer 12 is deposited thereon and planarized. An etch stop layer 16 is formed, and a lower electrode 18, a dielectric layer 20, and an upper electrode 22 are sequentially deposited thereon to form a capacitor 24. After this, an aluminum oxide layer 26 is deposited using a blanket method to prevent penetration of hydrogen into the dielectric layer 20 during a subsequent hydrogen alloy process.
Referring to FIG. 2, a second ILD layer 28 is thickly formed on the surface of the semiconductor substrate where the aluminum oxide layer 26 is deposited as the hydrogen barrier layer. A photoresist layer is coated on the second ILD layer 28 and then a metal contact hole 30 for connecting a bit line 14 and a metal line is formed using photolithographic and etching processes. The etching process for forming the metal contact hole may be a dry etching process. If the aluminum oxide layer 26 for the hydrogen barrier layer is exposed during the etching process for forming the contact hole 30, then the contact hole 30 may be incorrectly formed (A). As a result, the contact hole 30 may be obliquely formed or incompletely made (A). When a poorly formed contact hole is filled with a conductive material for a contact plug a contact resistance may increase in the metal contact region, thereby degrading electrical properties of an integrated circuit device incorporating the capacitor.
FIG. 3 is a cross-sectional view that illustrates another method of forming a conventional capacitor that includes electrodes that comprise a noble metal. Referring to FIG. 3, an aluminum oxide layer 26a that is used as a hydrogen barrier layer does not extend to a metal contact region to avoid increasing the contact resistance at a metal contact region. A capacitor 24 is formed and the aluminum oxide layer 26a for the hydrogen barrier layer is deposited on a capacitor upper electrode 22. The capacitor 24 and the aluminum oxide layer 26a comprising the hydrogen barrier layer are etched together. Thus, the increase in a contact resistance in a contact hole 30 caused by oblique etching or incomplete etching can be avoided. Because a sidewall of the capacitor is exposed during a hydrogen alloy process, however, hydrogen may penetrate into a dielectric layer 20 and degrade electrical properties of an integrated circuit device that incorporates the capacitor.
FIG. 4 is a graph of leakage current versus voltage for a capacitor formed using the method described above with reference to FIG. 3. The x-axis represents a voltage (V) applied to a semiconductor device including a capacitor, and the y-axis represents a leakage current per a unit cell (A/cell). In the drawing, the solid line denotes a leakage current characteristic before a hydrogen alloy process is performed. The line illustrated as -●- denotes a leakage current characteristic after the aluminum oxide layer for the hydrogen barrier layer is deposited to a thickness of 150 Å. As can be seen from FIG. 4, the leakage current increased even with use of the aluminum oxide layer for the hydrogen barrier layer. It may be presumed that hydrogen penetrated into sidewalls of the capacitor and degraded characteristics of an electrode interface or a dielectric layer, thus increasing the leakage current.
According to conventional methods of forming a capacitor that includes electrodes comprising a noble metal, a contact resistance may increase in a metal contact hole or hydrogen may penetrate into sidewalls of the capacitor, thus degrading characteristics of electrodes and/or a dielectric layer of the capacitor. As a result, a leakage current may increase.