1. Field of Invention
The present invention relates to an apparatus for efficient testing of embedded modules within electronic systems. More particularly, the present invention provides an access scheme for efficient testing of reusable modules within integrated circuits using reusable module test vectors regardless of the configuration of the modules within the integrated circuit.
2. Description of the Prior Art
Integrated circuits find application today in many areas far afield of their original domain in the computer industry. They can be found in devices from dishwashers and microwave ovens to planes, medical equipment and communications devices. Because proper functioning of embedded integrated circuits is often critical to the device in which they operate, it is essential that comprehensive testing be performed when they are being mass produced to ensure that the end product performs as designed, and is as fault and error free as possible. Thus, because every chip must be tested during production, test overhead becomes a serious concern for semiconductor manufacturers.
As chip designs become more complex, the physical overhead and time required for testing can contribute significantly to the overall cost of the devices. For simple chip designs it is a simple matter to test the chip as a whole. A set of test inputs and expected responses, the test vectors, are developed, and if the chip is in good condition, its response to the test inputs will match the expected responses predicted. However, as integrated circuits become more complex, the development of new test vectors becomes very difficult and expensive to implement for every chip design. Further, testing chips as a whole makes it difficult to isolate problems that may be occurring in specific functional areas of the chip.
Today, integrated circuit design has taken on a modular approach in which there are certain modules that will be common within many integrated circuits, though they may be configured differently. For example, common modules include timers, counters, digital-to-analog converter, central processing units (CPU), direct memory access controllers (DMA), etc. Application Specific Integrated Circuits (ASIC) may also be built around different configurations of the same pre-existing modules. However, the configuration of the modules within a given chip will determine what test vectors are required to implement a chip-as-a-whole testing scheme. Thus, even though two chips may contain exactly the same modular elements, their unique configurations may require the development of completely different test schemes and test vectors. This is so because many of the modules will be embedded within the chip such that there is no direct access to them. Their inputs will be signals which have propagated through other modules prior to reaching them while their outputs may need to propagate through other modules before they are accessible outside the chip. For example, in one configuration, to test a timer might require developing test vectors that will have to pass through a CPU on their way to the timer and then have to be propagated through a counter on their way out of the chip. In addition to the arduous task of simulating the chip to determine the required inputs to get desired outputs, a bad response won't guarantee that the problem is within the timer. The problem may be occurring within the CPU or the counter or at any of the interconnects between any of those modules.
Obviously the problem is exacerbated when the number of modules within the integrated circuit increases and the level of module embeddedness increases. If it were possible to access each module directly then a standard set of test vectors for that type of module could be implemented. That is, every use of a module of a particular type would receive exactly the same test vectors as inputs, and exactly the same results would be expected. The problem is that rarely is every module directly accessible for all inputs and outputs. It would require a large silicon and package pin overhead to design complex integrated circuits such that all modules would be directly accessible to system pins in that manner. Thus, there is a need for a design scheme which provides for accessing modules to deliver standard test vectors and a way to access those modules' outputs, but without the overhead of trying to design integrated circuits with direct pin access to every module's complete input and output set.
One approach to the problem of embedded module testing is to use a bus to convey input test vectors to a desired module and another bus to convey the module's output signals out of the chip. These busses may have their own pins on the chip, but are more likely to be multiplexed with pins which are employed for other uses. Traditionally, the bus for conveying the module's output is coupled to each of the module's outputs. While this method allows for accessing the module directly for testing, it does not provide for verifying the module's connections with other modules. Testing these connections would then typically require additional test hardware, a new test method and would also require that an additional configuration-specific test be written.