1. Technical Field
A pseudo SRAM device is disclosed, and more specifically, to a refresh control circuit of a pseudo SRAM, wherein power consumption in the standby mode can be conserved.
2. Discussion of Related Art
Generally, a RAM (Random Access Memory) is a memory to store data within memory cells, and can be classified into a SRAM (Static RAM) and a DRAM (Dynamic RAM; DRAM). SRAM cells have a static latching structure consisting of six transistors or a combination of four transistors and two resistors. The data can be stored indefinitely if supplied with power. DRAM cells have a structure including a capacitor and an access transistor.
The pseudo SRAM is a memory that internally and automatically performs a refresh operation on memory cells without an external control and has a similar interface and operational timing as those of a SRAM in terms of its function. Like DRAM cells, pseudo SRAM cells have cells that include an access transistor and a capacitor. The pseudo SRAM, like DRAM cells, includes a refresh related circuit, unlike existing SRAM cells.
In a pseudo SRAM, data stored as electric charges is accumulated on a capacitor. The data may be lost because initial capacitor charges stored can be lost due to various causes such as leakage current. In order to prevent this, the data stored within a memory cell should be read before the data can be lost, and the memory cell should be re-charged with initial charges according to read information. Only if this operation is repeated regularly can the storage of data be maintained. Such a recharging process of cell is called a “refresh” operation.
In the conventional pseudo SRAM, refresh is performed with refresh control being carried out on a bank basis. If one word line performs an access operation in any one bank, other banks can perform nothing operation. Furthermore, a cell array is generally comprised of four banks. One bank includes four word lines. Accordingly, if a cell array has a refresh period of 256 ms, an oscillator has to be designed to have a period of 16 μs in order to refresh 16K word lines and, the current in a standby mode is consumed at a period of 16 μs. An average current at this time is current consumption at a standby mode. Current consumption in a standby mode is very important since a pseudo SRAM is used for mobile devices. An increase in current consumption causes to degrade the yield of mass production.
If the refresh period is quadrupled to reduce the current consumption in the standby mode, the number of word lines to be refreshed during a refresh period of 256 ms is also quadrupled. However, problems can arise because the internal power becomes lower than original design rule due to excessive current consumption, and the amount of the charges in the restored cells is thus reduced. This requires the refresh period to be shortened. In this case, the period has to be reduced again, which leads to an increase in the current of the standby mode.