The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, interconnects conductive lines and associated dielectric materials that facilitate wiring between the transistors and other devices play more and more important role on IC performance improvement. Studies and researches are heavily conducted to search not only new conductive and dielectric materials, such as copper metallurgy and low dielectric constant (k) material, but also new process integration schemes for a better interconnection. Although existing methods of fabricating IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, to minimize process-induced-damage on the low-k dielectric material layer raises challenges in IC process developments. It is desired to have improvements in this area.