In telecommunications systems that are designed to handle signals with high peak-to-average power ratios (PAPR), Doherty power amplifier architectures have become popular due to their relatively high linearity and efficiency at backoff levels, when compared with other types of amplifier topologies. A conventional two-way Doherty power amplifier includes a class-AB biased carrier amplifier and a class-C biased peaking amplifier in a parallel arrangement. When an input signal has relatively low to moderate power, the carrier amplifier operates to amplify the input signal, and the peaking amplifier is minimally contributing. Conversely, when an input signal has relatively high power, the input signal is split (e.g., using a 3- or other decibel (dB) quadrature coupler) between the carrier and peaking amplifier paths, both amplifiers operate to amplify their respective portion of the input signal, and the amplified signals are thereafter reactively combined to produce the final amplified output signal.
As the Doherty amplifier input signal level increases beyond the point at which the carrier amplifier is operating in compression, the peaking amplifier conduction also increases, thus supplying more current to the load. In response, the load impedance of the carrier amplifier output decreases. In fact, an impedance modulation effect occurs in which the load line of the carrier amplifier changes dynamically in response to the input signal (i.e., the peaking amplifier provides active load pulling to the carrier amplifier). An impedance inverter at the output of the carrier amplifier transforms the carrier amplifier output impedance to a high value, allowing the peaking amplifier to efficiently supply power to the load.
In many cases, the carrier amplifier is implemented in a packaged device that is coupled to a printed circuit board (PCB). In such a system, a portion of the impedance transformation and phase shift is performed within the packaged device, and a portion of the impedance transformation and phase shift is performed on the PCB. Using conventional designs, a significant amount of the impedance transformation is performed on the PCB, and the package plane impedance under Doherty impedance modulation conditions can become very low. Accordingly, the PCB is required to handle relatively high currents, and the design limit for overall RF bandwidth (RFBW) can become reduced. Generally, impedance transformation components implemented on the PCB tend to be more lossy than impedance transformation components implemented in the device. Because most of the losses on the PCB are I2R losses, the relatively high level of impedance transformation implemented on the PCB using conventional designs limits both achievable efficiency and RFBW of such designs.