1. Field of the Invention
The present invention relates to a data input circuit and a semiconductor device utilizing the data input circuit. The present invention more particularly relates to a data input circuit receiving serial data synchronously to a clock, and converting the serial data to parallel data, and a semiconductor device utilizing the data input circuit.
2. Description of the Related Art
Some semiconductor devices include an input circuit converting serial data supplied from outside the semiconductor devices to parallel data, and outputting the parallel data to a data bus by following an address signal. The input circuit creates a plurality of address signals from a single address signal supplied in accordance with a command signal, and outputs the parallel data to the data bus by following the plurality of address signals.
FIG. 1 is a diagram showing a configuration of a conventional input circuit. An input circuit 100 includes an input buffer 110, a shift register 120 (a data-acquiring buffer) and a data switch unit 130. The data switch unit 130 includes switches 131 through 134. Additionally, FIGS. 2A and 2B are diagrams showing signal processes performed by the input circuit 100. It should be noted that FIGS. 1, 2A and 2B show a case in which data is supplied to the input circuit 100 by a DDR (Double Data Rate) method supplying the data with a frequency twice as higher than that of an external clock, for instance.
An address signal A2 is initially supplied to the input circuit 100 with a data-write command as shown in FIG. 2A. The address signal A2 is one of address signals A0, A1, A2 and A3 expressed by a combination of the least two significant bits (Y1, Y0) of an address. Additionally, the address signal A2 supplied with the data-write command to the input circuit 100 indicates that input data is supplied to the input circuit 100 in order of data A2, data A3, data A0 and data A1 continuously after the address signal A2 and the data-write command have been supplied. To be concrete, the data A2, A3, A0 and A1 is supplied through the input buffer 110 to the shift register 120 in the order of the data A2, A3, A0 and A1 by following a frequency of an internal clock CLK1. The shift register 120 shifts data supplied thereto one by one as shown in FIG. 2B. For example, if an address signal supplied with the data-write command to the input circuit 100 is the address signal A2, the shift register 120 stores the data A2, A3, A0 and A1 respectively in areas N0, N1, N2 and N3 of the shift register 120.
The areas N0, N1, N2 and N3 of the shift register 120 are respectively connected to the switches 131, 132, 133 and 134 included in the data switch unit 130. The switches 131 through 134 are connected to data buses A0 through A3. The input circuit 100 outputs input data to a data bus corresponding to a supplied address signal by controlling the switches 131 through 134 by following the supplied address signal. For example, in the case in which an address signal supplied with the data-write command to the input circuit 100 is the address signal A2, the areas N0, N1, N2 and N3 are respectively connected with the data buses A2, A3, A0 and A1 as shown in FIG. 2B. As described above, the input circuit 100 creates a group of four address signals, each address signal corresponding to a combination of the least two significant bits of an address, automatically recognizes an order of four input data, and outputs the four input data to their corresponding data buses. Such an operation is called a 4N operation.
As described above, the input circuit 100 needs to include a large number of switches in the data switch unit 130. The data switch unit 130 needs to have (2n)2 switches in a case of creating a group of 2n address signals, each address signal corresponding to a combination of the least “n” significant bits of an address, automatically recognizing an order of 2n input data, and outputting the 2n input data to their corresponding data buses. For instance, in the 4N operation, the data switch unit 130 needs to have 42 switches. Consequently, a circuit area of the input circuit 100 increases by a larger amount as the number of input data increases. Additionally, the configuration of the input circuit 100 becomes more complicated.
FIG. 3 is a diagram showing a configuration of another conventional input circuit. An input circuit 200 shown in FIG. 3 includes the input buffer 110, data-acquiring buffers 140 (N0) through 143 (N3), and an address counter 150. Additionally, FIGS. 4A, 4B and 4C are diagrams showing signal processes performed by the input circuit 200. The input circuit 200 achieves the 4N operation by controlling a data-acquiring clock supplied to the data-acquiring buffers 140 through 143 that are provided for the input data A0 through A3.
The address signal A2 is initially supplied to the input circuit 200 with the data-write command as shown in FIG. 4A. The address counter 150 generates data-acquiring clocks 1 through 4 by following the address signal A2 as shown in FIG. 4B, and supplies the data-acquiring clocks to the data-acquiring buffers 140 through 143. To be concrete, the data-acquiring clocks 1, 2, 3 and 4 are respectively supplied to the data-acquiring buffers 140, 141, 142 and 143. The data-acquiring buffers 140 through 143 obtain the input data A0 through A3 respectively at rising edges of the data-acquiring clocks 1 through 4 as shown in FIG. 4C. Subsequently, the data-acquiring buffers 140 through 143 outputs obtained input data, for example, the input data A0 through A3 respectively to the data buses A1 through A3.
The input circuit 200 shown in FIG. 3 needs to generate the data-acquiring clocks at the highest frequency possible. However, since a logical circuit such as the address counter 150 must generate the data-acquiring clocks, speed up of processes executed by the input circuit 200 is hard.