Wafer level packaging processes can be broadly divided into two categories: Fan-In Wafer Level Packaging (FI-WLP) and Fan-Out Wafer Level Packaging (FO-WLP) processes. FI-WLP processes enable the production of Chip Scale Packages (CSP packages) containing one or more non-encapsulated die. FI-WLP processes may be performed entirely on the wafer level, while producing CSP packages having planform dimensions equal to the size of die. Electrical interconnection between the packaged die and the external contact array may be provided by a leadframe, an interposer, or a number of Redistribution Layers (RDL layers), depending upon the particular CSP approach employed. By comparison, FO-WLP processes allow the production of larger microelectronic packages having peripheral fan-out areas, which enlarge the surface area of the package topside over which the contact array is formed. In one known FO-WLP packaging approach, referred to as a “Redistributed Chip Packaging” approach, an array of singulated die is encapsulated in a molded panel over which one or more RDL layers and a Ball Grid Array (BGA) are formed. After formation of the RDL layers and the BGA, the panel is singulated to yield a number of RCP packages each containing a semiconductor die embedded within a molded body. Relative to CSP packages, RCP and other such FO-WLP packages typically provide an increased I/O pin count and superior mechanical protection of the packaged die.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.