1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit memory devices comprising arrays of data storage cells. More specifically, the present invention relates to a method and apparatus for reducing the cell voltage required for a logical "1" to be detected.
2. Description of the Related Art
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory devices. The memory device stores data in large arrays of memory cells. Each cell conventionally stores a single bit of data (a logical "1" or a logical "0") and can be individually accessed or addressed. A data bit is output from a memory cell during a read operation and a data bit is stored into a memory cell during a write operation.
In a standard read or write operation, a column decoder and a row decoder translate address signals into a single intersection of a row (wordline) and column (digit line) within the memory array. This function permits a data bit to be read from the memory cell at that location or for data bit to be placed in the cell. The processing of data is dependent on the time it takes to store or retrieve individual bits of data in the memory cells. Storing and retrieving the bits of data are controlled generally by a microprocessor, whereby data are passed to and from the memory array through a fixed number of input/output (I/O) lines and I/O pins. The accuracy of sensing data is further dependent on the magnitude of charge stored in a memory cell and the capacitance inherent in the integrated circuit. Typically, a logical "1" is stored in a memory cell as V.sub.CC on a storage node side of a capacitor with a potential of V.sub.CC /2 on the common plate of the memory cell capacitor. When reading a logical "1" from the capacitor, the row line turns on the access transistor between the storage node side of the capacitor and the digit line. The charge from the storage node dumps onto the digit line and brings the voltage of the digit line up slightly above the equilibrium level of V.sub.CC /2 or approximately V.sub.CC /2 plus 50 mV. The reason that the cell only brings the digit up slightly is because of the large capacitance of the digit line with respect to the cell capacitance. Thus, the same charge that raises the storage node of the cell to V.sub.CC can only move the digit lines slightly above their equilibrium level of V.sub.CC /2.
The same principles apply to dumping a "0" onto a digit line. Even though the storage node side of the cell is at ground when the row line turns on the access gate to the cell, very little charge transferred from the digit line is needed to cause the digit line and the cell to be at the same level. This new level is slightly lower than the equilibrium level of V.sub.CC /2 of the digit line, or approximately V.sub.CC /2 minus 50 mV.
A sense amplifier uses the difference between the digit line having the memory cell dump and a reference digit line that remains at the equilibrium level to determine which line to pull up to V.sub.CC and which line to pull down to ground. The accuracy of the sensing operation is thus dependent on the signal clarity between sensing V.sub.CC /2 plus 50 mV and V.sub.CC /2 minus 50 mV.
Because a logical "1" in a DRAM is stored as V.sub.CC on the cell, the use of a high voltage (VCCP) on the gate of the access transistor and on the gate of the isolation transistor is required. This high voltage may pose reliability problems as the gate oxide thickness continues to decrease. Also, a p-channel sense amplifier is needed to pull the V.sub.CC /2 biased digit line up to V.sub.CC during a read to restore the charge in the cell. Static refresh is limited because the cell nitride has to be thick enough to withstand voltages of V.sub.CC /2 across it, and the reverse junction leakage and sub-threshold leakage currents of the access transistor are increased by the use of V.sub.CC in the cell.