Thin film transistor-liquid crystal display (TFT-LCD) is known as the display required for the high pixel density and quality. In general, the TFT-LCD includes a bottom plate formed with thin film transistors and pixel electrodes and a top plate formed with color filters. The liquid crystal is filled between the top plate and the bottom plate. In each unit pixel, a capacitor and a further capacitor are provided which are formed by virtue of the TFT serving as the switching element of the unit pixel. In the operation, a gate signal voltage is applied to the TFT that is the switching element of each unit pixel. The TFT receives the gate signal voltage, it is turn on so that data voltage carrying image information can be applied to the corresponding pixel electrode and the liquid crystal via the TFT. When the data voltage is applied to the TFT, the arrangement of the liquid crystal moleculers is change, thereby changing the optical properties and displaying the image.
A conventional method for forming a TFT will be described in conjunction with FIGURES 1A-1L.
In accordance with the prior method, an opaque metal layer such as Al, Ta, or Cr is formed on a substrate 2. The metal layer is patterned to serve as a gate electrode 4 and a metal interconnection (MI) 3. A stacked layer consisted of a first silicon nitride layer 6, an amorphous silicon layer 8 and a second silicon nitride layer 10 are formed on the substrate 2. A positive photoresist 12 is patterned on the second silicon nitride layer 10. Next, an exposure indicated by 16 is performed from the back side of the substrate 2 using the gate electrodes as a mask. Then, the portion 10a covered by the gate electrode is left after the steps. The portion on the MI 3 can be removed by masking and etching procedures.
Subsequently, a doping area 18 is performed by using implanting ions into the amorphous silicon layer 8. Next, turning to FIG. 1E to FIG. 1F, a metal layer 20 is formed on the doping area 18. An annealing step is used to react the silicon layer 10 and the metal layer to generate metal silicide layer 22 on the amorphous silicon layer 8. A second photoresist 24 is patterned over the gate electrode 4 using photo-lithography method, as shown in FIG. 1G. Then, the source and drain regions are defined by etching the silicide layer 22 and the amorphous silicon layer 8 exposed by the second photoresist 24. The result is shown in FIG. 1H. The source and drain regions are separated by the structure 10a. The second photoresist 24 is removed.
Referring to FIG. 1I-1L, an indium tin oxide (ITO) 26 is patterned on the first silicon nitride layer 6 adjacent to the source and drain regions. The first silicon nitride layer 6 over the MI 3 is removed, then a metal connection 28 are formed over the MI 3, the source and drain regions 22. Typically, the metal connection 28 is formed of Cr/Al. Finally, a passivation layer 30 is formed to cover the metal connection 28 and the source and drain regions 22.
The conventional method uses the ion implantation to form the source and drain silicide 22 and also act as n+ source. After the step, various steps, such as ITO pattern, contact etching and source and drain pattern are need for forming the TFT. However, these steps that involves the oxygen plasma or BOE (buffer oxide etching) etching will increase the resistance of the silicide 22, thereby reducing the performance of the TFT device. Further, the method needs implanter for doping and the method mentioned above needs at least seven masking processes. What is required is a new method for forming the TFT device.