1. Field of the Invention
The present invention relates to a video display system which generates and displays the frame signal of an output video signal at a higher frame rate than that of an input video signal from the frame signal of a continuously inputted video signal.
2. Description of the Related Art
After the dominance of CRT technology in the display industry for over 100 years, Flat Panel Display (FPD) and Projection Display have gained popularity because of their space efficiency and larger screen size. Projection displays using micro-display technology are gaining popularity among consumers because of their high picture quality and lower cost. There are two types of micro-displays used for projection displays in the market. One is micro-LCD (Liquid Crystal Display) and the other is micro-mirror technology. Because a micro-mirror device uses un-polarized light, it produces better brightness than micro-LCD, which uses polarized light.
Although significant advances have been made in technologies of implementing electromechanical micro-mirror devices as spatial light modulators, there are still limitations in their high quality images display. Specifically, when display images are digitally controlled, image quality is adversely due to an insufficient number of gray scales.
Electromechanical micro-mirror devices have drawn considerable interest because of their application as spatial light modulators (SLMs). A spatial light modulator requires an array of a relatively large number of micro-mirror devices. In general, the number of required devices ranges from 60,000 to several million for each SLM. Referring to FIG. 1A, an image display system 1 including a screen 2 is disclosed in a relevant U.S. Pat. No. 5,214,420. A light source 10 is used to generate light beams to project illumination for the display images on the display screen 2. The light 9 projected from the light source is further concentrated and directed toward lens 12 by way of mirror 11. Lenses 12, 13 and 14 form a beam collimator operative to columnate the light 9 into a column of light 8. A spatial light modulator 15 is controlled by a computer through data transmitted over data cable 18 to selectively redirect a portion of the light from path 7 toward lens 5 to display on screen 2. FIG. 1B shows a SLM 15 that has a surface 16 that includes an array of switchable reflective elements 17, 27, 37, and 47, each of these reflective elements is attached to a hinge 30. When the element 17 is in an ON position, a portion of the light from path 7 is reflected and redirected along path 6 to lens 5 where it is enlarged or spread along path 4 to impinge on the display screen 2 to form an illuminated pixel 3. When the element 17 is in an OFF position, the light is reflected away from the display screen 2 and, hence, pixel 3 is dark.
The on-and-off states of the micromirror control scheme, as that implemented in the U.S. Pat. No. 5,214,420 and in most conventional display systems, impose a limitation on the quality of the display. Specifically, applying the conventional configuration of a control circuit limits the gray scale gradations produced in a conventional system (PWM between ON and OFF states), limited by the LSB (least significant bit, or the least pulse width). Due to the ON-OFF states implemented in the conventional systems, there is no way of providing a shorter pulse width than the duration represented by the LSB. The least quantity of light, which determines the gray scale, is the light reflected during the least pulse width. The limited levels of the gray scale lead to a degradation of the display image
Specifically, FIG. 1C exemplifies, as related disclosures, a circuit diagram for controlling a micromirror according to U.S. Pat. No. 5,285,407. The control circuit includes memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5, and M7 are p-channel transistors; transistors, M6, M8, and M9 are n-channel transistors. The capacitances, C1 and C2, represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a based on a Static Random Access switch Memory (SRAM) design. All access transistors M9 on a Row line receive a DATA signal from a different Bit-line 31a. The particular memory cell 32 is accessed for writing a bit to the cell by turning on the appropriate row select transistor M9, using the ROW signal functioning as a Word-line. Latch 32a consists of two cross-coupled inverters, M5/M6 and M7/M8, which permit two stable states that include a state 1 when is Node A high and Node B low, and a state 2 when Node A is low and Node B is high.
The control circuit positions the micro-mirrors to be at either an ON or an OFF angular orientation, as that shown in FIG. 1A. The brightness, i.e., the number of gray scales of display for a digitally control image system, is determined by the length of time the micro-mirror stays at an ON position. The length of time a micromirror is in an ON position is controlled by a multiple bit word.
FIG. 1D shows the “binary time intervals” when controlling micromirrors with a four-bit word. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, 8, which in turn define the relative brightness for each of the four bits where “1” is the least significant bit and “8” is the most significant bit. According to the control mechanism as shown, the minimum controllable differences between gray scales for showing different levels of brightness is a represented by the “least significant bit” that maintains the micromirror at an ON position.
For example, assuming n bits of gray scales, one time frame is divided into 2n−1 equal time periods. For a 16.7-millisecond frame period and n-bit intensity values, the time period is 16.7/(2n−1) milliseconds.
Having established these times for each pixel of each frame, pixel intensities are quantified such that black is a 0 time period, the intensity level represented by the LSB is 1 time period, and the maximum brightness is 2n−1 time periods. Each pixel's quantified intensity determines its ON-time during a time frame. Thus, during a time frame, each pixel with a quantified value of more than 0 is ON for the number of time periods that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For controlling deflectable mirror devices, the PWM applies data to be formatted into “bit-planes”, with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element. According to the PWM control scheme described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled according to bit-plane values corresponding to the value of each bit during one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed for 1 time period.
Among conventional display systems, there is a system which generates and displays the frame signal of an output video signal at a higher frame rate than that of an input video signal from the frame signal of a continuously inputted video signal.
A system which displays a video image using a display device, such as a liquid crystal display (LCD) panel, retains one frame of video image information of each pixel for a single frame period and is enabled to display a smooth video image with little shaking of a dynamic image by generating and displaying an output video signal with a 120 Hz frame rate from an input video signal with a 60 Hz frame rate.
FIG. 2 is a diagram showing an example of generating a 120 Hz high frame rate output video signal from a 60 Hz frame-rate input video signal. This example is configured to generate anew the video signal of one frame on the basis of information from two adjacent frames of an input video signal, insert the generated video signal in between the aforementioned two input video signals, and generate anew a continuous video signal, and thereby a higher frame rate output video signal than the input video signal is generated. Incidentally, in the example shown in FIG. 2, the video image of the input video signal is the image of a ball moving from the bottom left to the top right. Further, the inputted video signal of each frame has 10-bit gray scale data for each pixel, and the video signal of a frame generated from the video signal of the two adjacent frames of the input video signal also has 10-bit gray scale data for each pixel. Therefore, the gray scale level of intensity (i.e., brightness) perceived by the human eye, in this example, is the same between the input video signal and the output video signal.
In order to more smoothly display the motion of a video image, it is desirable to use a video signal with a higher frame rate to display the image.
More specifically, the conventional method for generating a continuous video signal having a higher frame rate from a video signal continuously inputted at a specific frame rate, described above, includes a method of detecting the moving portion of the video image from the continuously inputted video signal and generating a new video signal of a frame so as to interpolate the motion. The conventional method also includes a method of generating a video signal of an interpolation frame by determining the intensity of each pixel constituting the video image of a frame to be interpolated on the basis of the change in the intensity information of each pixel constituting the aforementioned continuously inputted video signal.
Such techniques for generating and displaying the output video signal from an input video signal at a higher frame rate than that of the input video signal are disclosed in, among others, U.S. Pat. No. 4,771,331, JP2007-166050A, and WO/1997/046022. In recent years, such techniques enable the generating and displaying of video signals of a high frame rate in excess of 240 Hz without degrading the image quality of a video signal which is inputted at a 60 Hz frame rate.
Furthermore, in a display system employing a color sequential display method, it is also possible to prevent the color breakup phenomena by carrying out a display using a high frame rate video signal. In a display system such as an LCD display system, however, if a high frame rate video signal is generated by a video image processing apparatus, such as a video processor, and if the generated video signal is displayed, problems occur such as an increased load taken up by the display processing and lower response speed, thus limiting the simple improvement of a frame rate of the video signal to be displayed.
FIG. 3 is a diagram showing an example of generating a 360 Hz high-frame rate output video signal from a 60 Hz frame rate input video signal in a display system employing a color sequential display method. More specifically, the video image of the input video signal is the image in which a ball is moving from the bottom left to the top right, also shown in FIG. 3.
Referring to FIG. 3, if the input video signal is a color video signal constituted by an RGB (red, green and blue) signal and if the video signal of the frame has 10-bit gray scale data for each of the respective colors R, G and B for each pixel, a high frame rate output video signal is preferably generated so that the video signal of the frame has 10-bit gray scale data for each of the respective colors R, G and B for each pixel. In order to accomplish this, however, it is necessary to drastically improve the processing speed of the video image processing apparatus used for generating the new video signal of the frame by processing the input video signal, and to increase the memory space used for temporarily storing the video signals of a plurality of frames of the input video signal or the generated video signals of the frames.
Specifically, if an output video signal with a 360 Hz frame rate is to be generated, and if the video signal of the frame is to have 10-bit gray scale data for each of the respective colors R, G and B, it is necessary to use a video image processing apparatus having at least three times the processing speed and three times the memory space than when generating a 120 Hz frame rate output video signal from a 60 Hz frame rate input video signal, as shown in FIG. 3. This introduces the problems of an enlarged system size and a substantial cost increase.
Moreover, while it is necessary to provide a display system enabled to display a video image at three times the speed of the current rate, if such a system cannot be employed due to the problems described above, the information volume of each frame signal of a video signal to be displayed needs to be decreased to a third.