1. Field of the Invention
The present invention relates to a tester for testing a semiconductor device, and in particular to a tester for testing a semiconductor device wherein various timings are generated based on a time delay instead of using a plurality of clocks to improve a test efficiency and reduce a manufacturing cost.
2. Description of Prior Art
A tester for testing a semiconductor device tests whether the semiconductor device is defective. The tester for testing the semiconductor device is designed and developed according to a development state of a memory device, a DRAM in particular which takes up most of the memory devices since the tester for testing the semiconductor device is mostly used for testing the memory devices.
The development of the DRAM is progressing from an EDO (Extended Data Output) DRAM, SDRAM (Synchronous DRAM), Rambus DRAM to DDR (Double Data Rate) DRAM.
In order to test the DRAM, a high speed and a high accuracy are required for the tester so as to correspond to a high speed DRAM. In addition, as a capacity of the memory is increased, a time required for testing the DRAM also increases. Therefore, a testing speed is also required to be increased. Moreover, a cost for testing the memory should be reduced by embodying a miniaturized and economical tester.
Of the tester for testing the semiconductor device, the memory tester in particular is typically used for testing and verifying a memory component or a memory module in a form of a SIMM or DIMM. The tester detects a functional defect of the memory module or the memory component prior to an installation thereof in a real computer system.
The tester is classified into a hardware semiconductor device tester and a software diagnostic program executed in a PC environment. However, since the software diagnostic program diagnoses a state of the memory when the memory module or the memory component is installed in the real computer, the hardware semiconductor device tester is mainly used during a semiconductor memory manufacturing process.
The tester may be classified as a high-end tester referred to as an ATE (Automatic Test Equipment), a medium range memory tester and a low-end memory tester.
The ATE which is the high-end tester is typically used in order to carry out a test process of the memory device. The conventional ATE carries out tests such as a DC test for testing whether a DC parameter is suitable for a digital operation of a circuit, a transmission delay time of signals, and an AC margin related to a set-up time and a hold time. The ATE also generates a test pattern and a timing for the test. However, a manufacturing cost of the ATE is high since the ATE is manufactured using a dedicated equipment such as a main frame having a large size and a high price.
FIG. 1 is a block diagram illustrating a conventional tester for testing a semiconductor device.
As shown in FIG. 1, the conventional tester comprises a pattern generator 110, a timing generator 120, a format controller 130, a driver 140, a comparator 150, and a test result storage 160. In addition to these components, the conventional tester may comprise a power supply controller for the DC test, a component for generating a clock signal, a component for supplying a power for an operation of a DUT (Device Under Test) 180, a component for relaying a test pattern data to the DUT 180 and receiving a test result from the DUT 180, a component for receiving a test pattern program from an outside, and a component for transmitting the test result to the outside. However, a description thereof is omitted.
The pattern generator 110 generates the test pattern data required for testing the DUT 180 based on the test pattern program. For instance, the test pattern program is written to include an instruction for carrying out various operations in order to carry out the test. The pattern generator 110 generates the test pattern data by receiving and interpreting the test pattern program from an external storage for instance. The test pattern data includes a data such as a command, address and a data inputted to the DUT 180. In addition, an expected data corresponding to the generated test pattern data is generated.
The timing generator 120 generates a timing edge which is a reference for converting the test pattern data generated in the pattern generator 110 into various waveforms. The timing edge is generated using a plurality of clocks for a smooth conversion.
The format controller 130 converts the test pattern data to a desired waveform based on the timing edge.
The conversion of the test pattern data is described below in detail.
FIG. 2 is a diagram illustrating an example of converting a test waveform in a conventional tester for testing a semiconductor device.
Referring to FIG. 2, the pattern generator 110 generates the test pattern data. On the other hand, the timing generator 120 generates a plurality of timing edges using a plurality of clocks ACLK, BCLK and CCLK as shown. Because the format controller 130 requires a timing reference in order to convert the test pattern data to the desired test waveform at a desired moment, the timing generator 120 generates the plurality of timing edges using the plurality of clocks in order to configure the timing reference. The plurality of clocks is particularly used to generate the pattern data for a test of an asynchronous semiconductor device.
The format controller 130 converts the test pattern to the desired test waveform based on each of the timing edges. For instance, when the clock ACLK is used, the format controller 130 may convert the test pattern data to the test waveform of NRZA or /NRZA. “NRZ” represents a conversion wherein ‘0 ’ is not returned during a cycle in which the test pattern data is ‘1 ’, a character “A” represents that the test pattern data is converted through the clock ACLK, and a character “/” represents that the test pattern data is inverted. When the clock BCLK is used, the format controller 130 may convert the test pattern data to the test waveform of NRZB or /NRZB. When the clock CCLK is used, the format controller 130 may convert the test pattern data to the test waveform of NRZC or /NRZC. When the clocks BCLK and CCLK are used simultaneously, the format controller 130 may convert the test pattern data to the test waveform of NRZBC or /NRZBC. As described above, the test pattern data may be converted to the test waveform by the format controller 130 using the plurality of clocks.
The driver 140 transmits the converted test waveform to the DUT 180.
The comparator 150 tests the DUT 180 by comparing the test output data being outputted from the DUT 180 after an operation of the DUT 180 is complete by the test waveform applied to the DUT 180 with the expected data generated in the pattern generator 110.
The test result storage 160 stores a test result based on a result of the comparison of the comparator 150. For instance, an information on a defective DUT is stored.
As described above, the conventional ATE is a very highly priced equipment. Therefore, it is preferable that a manufacturer designs the highly priced ATE efficiently in order to increase a competitiveness by minimizing a manufacturing cost thereof. For the efficient design of the ATE, the generation of the test pattern and the timing should be optimized.
Particularly, in order to embody the timing generating function of the timing generator 120, a highly priced components are required. In addition, even when the highly priced components are used, a function of generating an accurate timing for the test of the semiconductor device operating at a high speed is difficult to embody. The function of generating the timing using the plurality of clocks may be used for the test of asynchronous device. However, the function of generating the timing using the plurality of clocks is not optimum for a synchronous device.
Moreover, the when the converted test waveform is transmitted to the DUT 180, the test waveform may be delayed for a predetermined cycle. The expected data may be also delayed by the comparator 150 in order to carry out the comparison with the data being outputted from the DUT 180. Because the delays are carried out after the conversion by the format controller 130, the driver 140 or the comparator 150 may convert an actual test waveform or the expected data again by considering each of the delays.
In addition, the test pattern data generated in the pattern generator 110 should be converted according to each of channels of the DUT 180, i.e. pins of the DUT 180. The conversion for the pins is carried out before the test pattern data is applied to the format controller 130. In such case, a multiplexing of the test pattern data to be applied to each of the pins is carried out. However, because the multiplexing is carried out to correspond to the each of the pins, a resource is wasted.