1. Field of the Present Invention
The present invention is in the field of microprocessors and, more particularly, microprocessors employing extended register sets.
2. History of Related Art
Microprocessors (processors) generally have a set of general purpose registers available to programmers. General purpose -registers store values that are used in arithmetic instructions, branch instructions, and memory access (load/store) instructions. The number of general purpose registers included in a processor design reflects a trade off between performance, which benefits from a large number of general purpose registers, and factors such as cost, complexity, and die size (the physical size of the processor), which benefit from fewer general purpose registers.
After a processor's architecture (including the number of general purpose registers) is defined, programmers develop software based on the defined architecture. As a body of such software comes into existence, compatibility considerations make it impracticable to alter the fundamental processor architecture. More specifically, existing code needs to be executable, preferably without recompilation, by all subsequent revisions of a processor.
Despite the concern with compatibility, some complex applications would benefit from having access to a larger number of general purpose registers. Accommodating such applications is difficult because a processor's instruction set generally restricts the number of general purpose registers that are accessible. For example, the instruction set for a processor having 32 general purpose registers usually includes 5-bit field(s) for referencing registers. A 5-bit register field is limited to addressing 32 registers. Accordingly, enabling applications to access a greater number of registers, while maintaining compatibility with existing code, generally requires an extended register set and an extended instruction set. An extended register set is a set of registers not addressable by a processor's legacy instruction set, but which may be accessible using instruction set extensions (e.g., instruction prefixes).
As the number of extended registers increases, context switching becomes a significant performance consideration. In a conventional extended register set implementation, context switching is achieved by saving the entire extended register set to memory as part of a code block's state. While this approach is simple, it becomes more time consuming and expensive as the number of extended registers increases.
In addition, conventional extended register set implementations do not have a compiler-independent mechanism (i.e., a run time mechanism) for allocating extended registers among different code blocks. Independent (separately compiled) code blocks are unaware of which, if any, extended registers are allocated to other code blocks. This limitation requires each code block to save and restore any extended registers that it uses, even when no other code block is using them. It would be desirable to implement an extended register set processor that addressed these limitations.