1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an In-Plane switching mode LCD device.
2. Discussion of the Related Art
As demands for various display devices increase, development of various flat-type display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, electroluminescent display (ELD) devices, and vacuum fluorescent display (VFD) devices, has increased. Among the various flat-type display devices, the LCD devices have been commonly used because of their thin profile, lightweight, and low power consumption. Specifically, the LCD devices have been developed as substitutes for Cathode Ray Tube (CRT) devices that are used in computer monitors and television displays. In addition, mobile-type LCD devices have been developed for use in notebook computers.
Key developments will rely upon whether the LCD devices can implement a high quality picture, such as high resolution and high luminance, in large-sized displays while still maintaining their lightweight, thin profile, and low power consumption. Accordingly, active matrix-type LCD devices have been developed because of their high resolution and image quality, wherein thin film transistors and pixel electrodes are arranged in a matrix-type configuration.
In general, LCD devices include an LCD panel for displaying an image and a driver for supplying a driving signal to the LCD panel. In addition, the LCD panel includes first and second substrates bonded to each other having a cell gap formed therebetween and a liquid crystal material layer disposed within the cell gap. The first substrate (i.e., TFT array substrate) includes a plurality of gate lines arranged along a first direction at fixed intervals, a plurality of data lines arranged along a second direction perpendicular to the first direction at fixed intervals, a plurality of pixel electrodes arranged in a matrix-type configuration within pixel regions defined by crossing of the gate and data lines, and a plurality of thin film transistors enabled according to signals supplied to the gate lines for transmitting signals from the data lines to the pixel electrodes. The second substrate (i.e., color filter array substrate) includes a black matrix layer that prevents light from portions of the first substrate except at the pixel regions, an RGB color filter layer for displaying various colors, and a common electrode, which together with the pixel electrode, induces an electric field to the liquid crystal material layer for producing the image.
The cell gap is maintained between the first and second substrates by spacers, and the first and second substrates are bonded together by a sealant material having a liquid crystal injection inlet, wherein the liquid crystal material is injected between the first and second substrates through the liquid crystal injection inlet. Initially, the cell gap between the bonded first and second substrates is maintained in a vacuum state, and the liquid crystal injection inlet is dipped into a container filed with the liquid crystal material. Accordingly, the liquid crystal material is injected into the cell gap between the first and second substrates using capillary action. After injection of the liquid crystal material into the cell gap has been completed, the liquid crystal injection inlet is sealed by the sealant material.
In general, the LCD device is driven according to optical anisotropy and polarizing characteristics of the liquid crystal material. An alignment direction of liquid crystal molecules of the liquid crystal material is controlled by the induced electric field to the liquid crystal material. Accordingly, light irradiated through the liquid crystal material may be controlled by the alignment direction of the liquid crystal molecules. If the pixel electrode is formed on the first substrate and the common electrode is formed on the second substrate, the liquid crystal material is driven by the electric field that is perpendicular to the first and second substrates. Thus, it is difficult to obtain a wide viewing angle. However, In-Plane switching mode LCD devices drive the liquid crystal material using an In-Plane mode electric field, thereby providing wide viewing angles. For example, along a front direction of the In-Plane switching mode LCD device, a viewer can have a viewing angle of 70° in all directions (i.e., lower, upper, left, and right directions). Compared to general TN mode LCD devices, In-Plane switching mode LCD devices have simplified fabrication process steps, and reduced color shift.
FIG. 1 is a cross sectional view of an In-Plane switching mode LCD device according to the related art. In FIG. 1, an In-Plane switching mode LCD device includes first and second substrates 1 and 2 being opposite to each other, and a liquid crystal material layer 3 disposed between the first and second substrates 1 and 2. A thin film transistor (TFT) array is formed on the first substrate 1 in a matrix-type configuration. Although not shown, a drain electrode of the thin film transistor is connected to a pixel electrode 20, and a common electrode 30 is formed spaced apart from the pixel electrode 20. In addition, the second substrate 2 includes a black matrix layer (not shown) that prevents light from portions of the first substrate 1 except with pixel regions, and a color filter layer for displaying various colors. In the In-Plane switching mode LCD device, the pixel electrode 20 and the common electrode 30 are formed along the same plane, whereby the liquid crystal material is driven by an induced In-Plane mode electric field.
A method for driving the In-Plane switching mode LCD device includes supplying a scanning signal to the gate line and supplying a video signal to the pixel corresponding to the gate line receiving the scanning signal. The liquid crystal material injected between the first and second substrates 1 and 2 may deteriorate when a DC voltage is applied for an extended period of time. In order to prevent such a problem, a polarity of the supplied voltage is cyclically changed, which is commonly referred to as a polarity inversion method. The polarity inversion method is classified into one of a frame inversion method, a line inversion method, a column inversion method, and a dot inversion method.
In the frame inversion method, positive and negative polarities of a data voltage supplied to the liquid crystal material for a common electrode voltage are alternately supplied during each frame. For example, if a positive (+) polarity data voltage is supplied to an even frame, a negative (−) polarity data voltage is supplied to an odd frame. Thus, the same polarity data voltage is supplied according to the even or odd frame, thereby decreasing consumption current during a switching mode. However, the frame inversion method is sensitive to flicker generated according to an asymmetrical transmittance between the positive and negative polarities. In addition, the frame inversion method is susceptible to crosstalk caused by interference between data signals of adjacent pixels.
The line inversion method is commonly used for low-resolution devices (i.e., VGA and SVGA devices), in which a data voltage is supplied such that a polarity of a data voltage supplied to the liquid crystal material for a common electrode voltage is changed according to a vertical direction. For example, in a first frame, a positive (+) polarity data voltage is supplied to an odd gate line, and a negative (−) polarity data voltage is supplied to an even gate line. Next, in a second frame, the negative (−) polarity data voltage is supplied to the odd gate line, and a positive (+) polarity data voltage is supplied to the even gate line. In the line inversion method, the polarities of the data voltage are oppositely supplied to adjacent lines such that a luminance difference is offset between the lines according to spatial averaging, thereby preventing the flicker during frame inversion. For example, the opposite-polarity data voltages are supplied along a vertical direction, whereby a coupling phenomenon of the data signals is offset, thereby decreasing vertical crosstalk during the frame inversion. However, the polarity of the data voltage is the same along a horizontal direction, so that horizontal crosstalk is generated, and consumption current is increased due to an increase of the number of switching operations, as compared with that during the frame inversion.
In the column inversion method, the same polarity of a data voltage supplied to liquid crystal material for a common electrode voltage is supplied in the vertical direction, and positive and negative polarities of the data voltage are alternately supplied along the horizontal direction. Thus, it is possible to minimize flicker by spatial averaging and to minimize horizontal crosstalk. However, the column inversion method requires a high-voltage column drive IC since the opposite-polarity data voltages are supplied to the adjacent lines according to the vertical direction.
The dot inversion method is supplied to high-resolution devices (i.e., XGA, SXGA, and UXGA device) for obtaining the greatest quality picture image. In the dot inversion method, a polarity of a data voltage is differently supplied to all-direction adjacent pixels. Accordingly, it is possible to minimize flicker by spatial averaging. However, the dot inversion method is problematic since the dot inversion method has a high consumption current by using a high-voltage source driver.
FIG. 2 is a plan view of a pixel structure of an In-Plane switching mode LCD device according to the related art. In FIG. 2, an In-Plane switching mode LCD device includes a plurality of gate and data lines 40 and 50 crossing each other to define a plurality of pixel regions, a plurality of storage lines 60 spaced apart from the plurality of gate lines 40, a plurality of thin film transistors (TFT) each disposed at crossing regions of the plurality of gate and data lines 40 and 50, a plurality of pixel electrodes 20 arranged as a “1-shaped” region within pixel regions 20 in parallel with the data lines, and a common electrode 30 formed as an “inverted U-shaped” region within a circumference of the pixel region.
FIG. 3 is a cross sectional view along I-I′ of FIG. 2 according to the related art, and FIG. 4 is a cross sectional view along II-II′ of FIG. 2 according to the related art.
In FIG. 2, a metal layer is deposited on an entire surface of a substrate 10 (in FIGS. 3 and 4), and then selectively removed, thereby forming a gate line 40 having a gate electrode (not shown) disposed along a horizontal direction, and a storage line 60 disposed along the same direction as the gate line 40 and spaced apart by a predetermined interval from the gate line 40. Then, a gate insulating layer 25 (in FIGS. 3 and 4) is formed on an entire surface of the substrate 10 including the gate line 40 and the storage line 60. Subsequently, a semiconductor layer (not shown) is formed on the gate insulating layer 25 above the gate electrode to serve as an active layer of a thin film transistor. Next, in FIGS. 3 and 4, a metal layer is deposited on the substrate 10 including the gate insulating layer 25 and the semiconductor layer, and then selectively removed to form a data line 50 perpendicular to the gate line 40 and source/drain electrodes 50c. Accordingly, the thin film transistor (TFT) comprising the gate electrode (not shown), the semiconductor layer (not shown), and the source/drain electrodes 50c are formed on the substrate 10.
In FIGS. 3 and 4, a passivation layer 35 is formed on an entire surface of the substrate 10 including the data line 50, and contact holes are formed in the passivation layer 35 corresponding to the drain electrode 50c of the TFT and the storage line 60. Then, a metal layer is deposited on an entire surface of the passivation layer 35, and patterned to form a pixel electrode 20 connected to the drain electrode 50c of the TFT, and a common electrode 30 connected to the storage line 60 spaced apart from the pixel electrode 20. Accordingly, the common electrode 30 contacts the storage line 60 formed under the common electrode 30 to provide power to the common electrode 30, and a data voltage is supplied to the pixel electrode 20 according to a conductive state of the TFT. In addition, the storage lines 60 are connected to one another and the same common voltage signal Vcom is applied to the storage lines 60, wherein the common voltage signal Vcom is DC voltage.
FIG. 5 is a schematic circuit diagram of the pixel structure of FIG. 2 according to the related art. In FIG. 5, in a unit pixel of the In-Plane switching mode LCD device of FIG. 2, a storage capacitor Cst is formed between the storage line 60 and the drain electrode 50c of the TFT formed between of the gate and data lines 40 and 50. Then, a liquid crystal capacitor CLC is formed between the pixel electrode 20 and the common electrode 30, and the storage capacitor Cst is connected to the liquid crystal capacitor CLC in parallel.
As shown in FIG. 6, the common voltage Vcom signal is maintained at a constant level even though the signal voltage of the pixel or the gate line 40 is changed, or the frame is changed. At this time, the polarity of the data voltage is inversely applied to the respective pixels in the horizontal direction. That is, the data voltage is applied such that positive (+) and negative (−) polarities for the Vcom are inversely applied to the respective pixels by alternately applying the positive (+) and negative (−) polarity data voltages to the data lines crossing the gate lines. The common voltage Vcom is maintained at a level between the positive (+) and negative (−) polarity data voltages applied to the pixel electrode 20. At this time, the same polarity of the data voltage is applied to respective odd data lines, or respective even data lines.
In order to drive the corresponding pixel, a gate driver (not shown) applies a select pulse through the gate line, and a source driver (not shown) applies a video signal to the thin film transistor turned on by a signal line. On applying the data voltage by the turned-on thin film transistor, the liquid crystal capacitor CLC and the storage capacitor Cst formed between the drain electrode of the thin film transistor and the storage line are charged during turning-on the thin film transistor. After turning-off the thin film transistor, electric charges are maintained until the thin film transistor is turned-on.
FIG. 6 is a timing diagram of a pixel voltage compared to a voltage signal supplied to gate and storage lines according to the related art. In FIG. 6, a pixel voltage (dark line) is changed by a difference amount (arrow) according to a parasitic capacitor formed between the gate and source electrodes of the thin film transistor along a falling edge of the scanning signal supplied to the gate line, whereby an alignment direction of the liquid crystal material is induced by the difference amount.
FIG. 7 is a polarity change diagram of common voltages in pixel regions according to odd/even frames of an In-Plane switching mode LCD device according to the related art. In FIG. 7, when an In-Plane switching mode LCD device uses the dot inversion method, polarity (i.e., data voltage for common voltage) is inversely supplied to adjacent pixels, whereby the polarities of the adjacent pixels are opposite to each other. Whenever the frame is changed, the polarity of the pixel is inverted. For example, the polarity of the pixel is alternately changed to a positive (+) and negative (−) to be different from the polarity of the adjacent pixel, thereby obtaining high-quality picture images.
FIG. 8 is a block diagram of a gate driver of an In-Plane switching mode LCD device according to the related art. In FIG. 8, a gate driver of an In-Plane switching mode LCD device includes a shift register part 61, a level shifter 62, and a buffer 63. The shift register part 61 includes a plurality of shift registers receiving a Gate Start Pulse signal GSP, a Gate Shift Clock signal GSC, and a Left/Right select signal L/R from a processor (i.e., computer), whereby the plurality of shift registers are sequentially operated. In addition, the level shifter 62 receives a Gate Output Enable signal (GOE) from the processor for sequentially shifting signals output from the shift register part 61, and the buffer 63 outputs signals for the gate lines Gout1, Gout2, . . . , Goutn that are supplied to the gate lines as a state selected from VGH, VGL, VCC, and VSS levels.
FIG. 9 is a diagram of a gate driver structure and a timing sequence of an In-Plane switching mode LCD device according to the related art. In FIG. 9, during operation of a gate driver the shift register part 61 shifts the GSP signal by the GSC signal, thereby sequentially enabling the gate lines. After completing enabling of the gate lines during one frame, a carry value is carried so that the gate lines of a second frame are enabled. Subsequently, the level shifter 62 sequentially level-shifts the signals supplied to the gate lines, and outputs the level-shifted signals to the buffer 63. Accordingly, the plurality of gate lines connected to the buffer 63 are sequentially enabled. In addition, a predetermined gate line synchronized by the GSC signal is maintained at the VGH level, and then the predetermined gate line is maintained at the VGL level along a rising edge of the GOE signal.
FIG. 10 is a block diagram of a source driver of an In-Plane switching mode LCD device according to the related art. In FIG. 10, a source driver of an In-Plane switching mode LCD device includes a shift register 81, first and second latch parts 82 and 83, a decoder 84, and an output buffer 85. The shift register 81 receives a Source Start Pulse signal (SSP), a Source Shift Clock signal (SSC), and a Left/Right select signal (L/R) from a processor, and stores the signals according to addresses. In addition, the first and second latch parts 82 and 83 receive a Load signal from the processor to receive and store RGB Data signals for even/odd modes in corresponding addresses. The decoder DAC 84 converts digital signals stored in the first and second latch parts 82 and 83 into analog signals, and the output buffer 85 outputs the signals of the decoder 84 according to the corresponding data lines.
Operation of the source driver includes sequentially receiving of the RGB Data signal from the processor through the shift register 81 in a dot clock, and latching by the first and second latch parts 82 and 83, thereby changing a timing system of Dot at a Time Scanning to a timing system of Line at a Time Scanning. Then, the data signals stored in the first latch part 82 are transmitted to the second latch part 83 according to horizontal clocks. The data signals stored in the second latch part 83 are transmitted to the decoder DAC 84. Then, the decoder DAC 84 receives a gamma standard voltage, and responds to a Polarity Out Load signal (POL) supplied from the processor, whereby the digital data is converted into an analog voltage, and then the analog voltage is output. The analog voltage is supplied to the data lines through the output buffer 85 according to a control signal supplied from the analog power source and the processor.
FIG. 11 is a gamma standard voltage circuit establishing a gamma standard voltage and a data voltage output extent of a source driver using the gamma standard voltage circuit according to the related art. In FIG. 11, in order to obtain a 256 gray level scale, a source driver of an In-Plane switching mode LCD device forms 256 gray level voltages for positive (+) fields and 256 gray level voltages for negative (−) fields using one gamma voltage driving circuit. After setting a maximum standard voltage value for the positive (+) fields, and a minimum standard voltage value for the negative (−) fields using an R-string method, the gamma standard voltage value is output at a level between the maximum standard voltage value for the positive (+) fields and the minimum standard voltage value for the negative (−) fields. Then, the DAC 84 receives the gamma standard voltage value, and the source driver is operated. In case of the positive (+) fields for the common voltage Vcom, the source driver outputs the data voltage having a larger value than that of the common voltage Vcom. Meanwhile, in case of the negative (−) fields for the common voltage Vcom, the source driver outputs the data voltage having a smaller value than that of the common voltage Vcom.
A method for driving the In-Plane switching mode LCD device having the aforementioned gate and source drivers includes the source driver (in FIGS. 10 and 11) sequentially receiving video data signals of the respective pixels supplied from the processor, and stores the video data signals corresponding to the respective data lines. Then, the gate driver (in FIGS. 8 and 9) sequentially supplies the scanning signals to the plurality of gate lines by outputting the Gate Shift Clock signal (GSC), the Gate Shift Pulse signal (GSC), and the Gate Output Enable signal (GOE). Accordingly, the plurality of thin film transistors connected to the selected gate line are turned ON, whereby the video data signals (i.e., data voltage type) output from the source driver are supplied to the drain electrode of the thin film transistor, thereby displaying the video data on an LCD display panel. Next, the aforementioned process steps are repetitively performed, thereby displaying the video data on the LCD display panel. Accordingly, a plurality of pins from 1 to n are sequentially formed at an output side of a gate driver Tape Carrier Package (TCP) to output signals for the gate lines.
However, the related art In-Plane switching mode LCD device has the following disadvantages. When driving the In-Plane switching mode LCD device using the dot inversion method, a constant value is supplied to the common voltage signal in a DC state, and the positive (+) and negative (−) polarity data voltages for the common voltage signal are alternately supplied to the data lines of the respective pixels. Accordingly, the pixel voltage supplied to the liquid crystal has the polarity dependent on the data voltage, so that it is required to use the source driver having a great output voltage difference to induce a high voltage to the liquid crystal material. The source driver of the In-Plane switching mode LCD device generally has an extended output using a constant voltage VDD power source of 15V. Accordingly, the pixel voltage supplied to the liquid crystal material is about (−)6V or (+)6V. However, since the source driver having the high output value is expensive, low power consumption has been developed by lowering the output value to decrease manufacturing costs.
In the In-Plane switching mode LCD device, the liquid crystal material is driven according to a fringe field formed between the pixel electrode and the common electrode. Accordingly, it is required to form the fringe field having a great value by narrowing an interval between the pixel electrode and the common electrode. In order to narrow the interval between the pixel electrode and the common electrode, it is necessary to pattern the pixel and common electrodes having a finger-type crossing at a predetermined interval when patterning the pixel and common electrodes. However, although it is possible to narrow the interval between the pixel electrode and the common electrode, an aperture ratio of the pixel is deteriorated.
To improve the aperture ratio, the pixel or common electrode may be formed of a transparent material, such as ITO. However, patterns having various shapes are formed within the pixel region so that it is difficult to uniformly transmit the light. When widening the interval between the pixel electrode and the common electrode for improving the aperture ratio, the In-Plane mode electric field formed between the pixel electrode and the common electrode decreases. Thus, in order to obtain the required luminance, the output of the data voltage must be extended.