Non-volatile memory architectures such as EPROM devices usually require operating voltages above voltage supply levels (“VDD”) of the integrated circuits (“ICs”) on which they reside. For example, in order to perform Program (“PGM”), Read, and/or Erase operations, memory cells according to specific technologies (e.g. NROM) may require voltages of up to 10.5V. To obtain these relatively high voltages, charge-pumps may be utilized to multiply VDD (typically 1.8-3.6V) by some factor. A charge pump's voltage multiplying factor may be a function of the charge pump's circuit configuration, which circuit configuration may include a number of transistor/diode pairs. The size and current consumption of a charge pumps is usually based on the amount of Power (Voltage x Current) the pump must provide.
Various operations or operating modes of a non-volatile memory cell may require distinct voltage and current levels. Typically, since NROM EPROM chips and other memory cell arrays operate in several different modes, where each mode has a distinct voltage and current requirement, multiple charge pumps are required. Table #1 shows the operating modes and typical voltage and current levels of an NROM device.
WLBLSelectOperatingVoltageVoltageBL Current per cellTransistorMode(V)(V)(A)Voltage (V)READ4210u (programmed bit)4-660u (erased bit)PROGRAM10.54-6250u10.5(steppedat 200mV)ERASE−74-61n10.5stepped
Table 1 lists voltage and current levels which may be required for the three basic operating modes of a non-volatile memory, specifically an NROM in this case. For each mode, the table lists the voltage and/or current levels which may be required for a memory cell's: (1) Word Line (“WL”), which is usually the gate terminal (e.g. of an EPROM); (2) Bit Line (“BL”), which is usually the source or drain terminal of a memory cell; and (3) the gate of one or more select transistors. Since a gate of a memory cell, to which a WL may lead, and a gate of a select transistor are almost purely capacitive loads, there is little to no DC load current associated with either. Thus, no WL or select transistor currents are listed in Table 1. However, since the BL is usually connected to the drain of a memory cell (e.g. EPROM), which is a current loading element, current levels associated with the BL are listed for each of the three possible operations or modes of operation.
FIG. 1 shows a circuit and a method of operating, (e.g. programming) a memory cell according to the prior art, at the voltage levels substantially similar to those listed in table #1. Turning now to FIG. 1, there is shown a block diagram of a circuit architecture which has been utilized to provide pumped voltages to a memory array 100 (e.g. EPROM) through WL 110 and BL 120 during a PGM operation. Based on the address of a memory cell to be programmed, an Xdecoder 200 (“XDEC”) may determine which WL 110 to access and may provide voltage to the selected WL 110. All other WLs may be maintained at ground (GND) during PGM. A Y-Muliplexor 300 (“YMUX” or “YM”) may access the BL 120 via a select transistor 130, providing positive voltage to the enabled BL 120. Inverters and/or drivers, 140a and/or 140b, may be used to interface the output of XDEC 200 or YMUX 300 with a relevant transistor gate. A High Voltage charge pump 400 (“HV Pump”) may provide a regulated 10.5V to the WL 110 and to the select transistor 130. During PGM, the WL 110 may be required to be at or about 10.5V. It is thus convenient to have the select transistor 130 connected to the same IV Pump 400 as the WL 110.
Regulation of the HV Pump 400 may be internal to the HV Pump 400 (as shown as in U.S. patent No. 6,577,514, entitled “Efficient Charge Pump with Constant Boosted Output Voltage” and assigned to the assignee of the present invention) or can be provided by a voltage regulator circuit connected in series between the HV pump and the load (not shown). A second pump, the Drain Pump (“DPUMP”) 500, may provide a 7V to 8V supply to a BL regulator 600. The regulator 600 may regulate the output of the DPUMP to a precise trimmed bit line voltage (“VPPD”) level. The VPPD/BL voltage level may be adjusted according to a smart programming algorithm to a voltage level between 4V and 7V using small voltage steps or increments (e.g. 200 mV). Although the DPUMP 500 may provide a lower voltage than the HV Pump 400, it may consume more current than the HV Pump 400, since the DPUMP 500 may drive as much as several milli-amperes of current, while in contrast, the load of the HV Pump is substantially capacitive and may require almost no DC current.
As mentioned above, charge pump circuits are required to provide all voltage levels above VDD and below VSS (VSS=GND=0). As seen in FIG. 1, according to the prior art, two or more charge pumps are required on a memory chip. Since each charge pump circuit may have a pumping efficiency (Power Out/Power In) of 20-30% (e.g. each 1 mA of current pumped at 8-10V may require 10-12 mA of VDD current), charge pump currents can comprise the majority of VDD current used by a memory chip. In addition, charge pumps are large circuits and can take up as much as 50% of a chip's die area.
What has been absent from the prior art, and is desired, is a method and circuit capable of driving the WL/select capacitive loads and efficiently driving high currents to the BL at a lower voltage, while avoiding the necessity of having two distinct positive charge pumps. Thus, it would be beneficial to reduce the number of charge pumps required for a non-volatile memory array such as an NROM EPROM array.