1. Field of the Invention
The present invention generally relates to a designing method of an electronic device that consists of an STI (Shallow Trench Isolation) structure, a wiring structure, and the like, to which a chemical mechanical polishing (CMP) method is applied, and a manufacturing method of the electronic device to which the above-mentioned designing method is applied. Here, the electronic device referred to in the present document is not limited to semiconductor devices, but thin film magnetic heads, CCD elements, semiconductor laser diodes, etc. to which the CMP method is applied, are included.
2. Description of the Related Art
In the electronic devices, such as semiconductor devices and magnetic heads, an element and a wiring structure that have a thin-film lamination structure are used. When manufacturing the element, the wiring structure, and the like, the CMP method is used in order to obtain planarity of the surface of the lamination.
For example, the CMP method is used in an STI process when manufacturing a MOS (Metal Oxide Semiconductor) device. The STI process embeds an insulating material and forms an element isolation region that electrically separates an element region from other element regions on a semiconductor board. Hereafter, the conventional STI process is explained, referring to FIG. 1.
Sections (A) through (E) of FIG. 1 show steps of the STI process.
With reference to Section (A) of FIG. 1, a silicon oxide film 12 is formed on a silicon board 11 by heat oxidation. Further, the silicon nitride film 13 is formed by a sputtering method, a CVD (chemical vapor deposition) method, etc.
Next, with reference to Section (B) of FIG. 1, the silicon nitride film 13 in the portion that is to be used as an element isolation region is removed using a photo lithography method and dry etching. Next, the silicon oxide film 12 and Si in the element isolation region are removed, and a trench (slot) 14 is formed by a dry etching method using the silicon nitride film 13 that remains as a mask.
With reference to Section (C) of FIG. 1, the inner wall of the trench 14 is heat-oxidized, a silicon oxide film 15 is formed, and a silicon oxide film 16 is formed by a CVD method using TEOS (tetra ethyl ortho-silicate), HDP (High Density Plasma), etc.
With reference to Section (D) of FIG. 1, the silicon oxide film 16 is polished by the CMP method until the silicon nitride film 13 becomes exposed. Here, the silicon nitride film 13 serves as a polishing stopper, the speed of polishing the silicon oxide film 16 being 3 to 4 times faster than the speed of polishing the silicon nitride film 13.
With reference to Section (E) of FIG. 1, the silicon nitride film 13 is removed by wet etching using phosphoric acid, etc. Further, the silicon oxide film 12 is removed by wet etching using HF. In this manner, element isolation regions 17, which are unpolished portions of the silicon oxide film 16, and element regions 18 are formed.
By the way, the degree of planarity (flatness) of a substrate that is polished by the CMP method is known to depend on how elements are laid out. That is, polishing progress of the silicon nitride film 13 may be different from place to place, depending on the density of the element regions 18 where the silicon nitride film 13 is formed. For example, where the element regions 18 are densely provided, volume of the silicon oxide film 16 deposited on the silicon nitride film 13 is large, and it takes a relatively long time to polish until the silicon nitride film 13 becomes exposed. Conversely, if the element regions 18 are sparsely provided, the volume of the silicon oxide film 16 on the silicon nitride film 13 is small, and it takes a relatively short time to polish until the silicon nitride film 13 becomes exposed. For this reason, time sufficient to polish one place may be insufficient or excessively long to polish other places.
To cope with this problem, technology to uniformly polish by the CMP method is indicated by JP, 9-102539, A (hereinafter, called “the conventional technology 1”), which is explained below with reference to FIG. 2.
Sections (A) through (F) of FIG. 2 show the STI process of the conventional technology 1.
With reference to Section (A) of FIG. 2, a silicon oxide film 22 and a silicon nitride film 23 are laminated in this sequence on a silicon board 21, and a trench 24 with a depth of 0.4 μm and an element region 25 in a convex shape are formed by the above-mentioned process.
Next with reference to Section (B) of FIG. 2, a silicon oxide film 26 is deposited by the CVD method. Here, the thickness of the silicon oxide film 26 to be deposited is set at about the same as the depth of the trench 24.
With reference to Section (C) of FIG. 2, the photoresist film 27 is applied to the silicon oxide film 26, patterning is carried out, and an opening is formed immediately above the element region 25. Here, the pattern of the photoresist film 27 is a reversal pattern of the element region 25 and the trench 24.
Next with reference to Section (D) of FIG. 2, the silicon oxide film 26 on the element region 25 is removed by anisotropic etching that uses the photoresist film 27 as a mask.
With reference to Section (E) of FIG. 2, the photoresist film 27 is removed, and the silicon oxide film 26 is etched by dry etching using Ar ion, incidence of the Ar ions being at a right angle to the substrate 21. In this manner, the silicon oxide film 26 becomes almost flat.
With reference to Section (F) of FIG. 2, the silicon oxide film 26 is removed by the CMP method until the silicon nitride film 23 becomes exposed. A flat polished surface of the silicon oxide film 26 and the silicon nitride film 23 is formed, and an element isolation region 28 is formed. Thus, according to the conventional technology 1 whereon the surface before polishing is almost flat, deformation of a polish cloth is suppressed, and variation in polish speed from place to place is minimized, thereby the planarity (flatness) of the surface after polishing is supposed to be improved.
Further, another technology for uniformly polishing by the CMP method is indicated by JP, 10173035, A, (hereinafter, called “the conventional technology 2”). According to the conventional technology 2, uniform polishing is supposed to be attained by setting the distance between each element at 100 μm or less, or alternatively, if the distance is greater than 100 μm, a dummy region is added such that the density of the elements is equalized.
However, in the case of the conventional technology 1, the mask process, the dry etching process, etc. for patterning the photoresist are required in addition to the conventional STI process, which causes manufacturing cost to rise.
In the case of the conventional technology 2, there is a problem as explained below. FIG. 3 shows an example of an arrangement of element regions and element isolation regions on a substrate 30 (not shown). With reference to FIG. 3, two element regions 31, each having a 500 μm long side, are formed, sandwiching an element isolation region 32 that is 1 micrometer long, length of the three element regions being about 1 mm in total. Further, to the right-hand side of FIG. 3, square-shaped element regions 33 whose one side is 0.5 micrometers long are formed with element isolation regions 34 that are 1 micrometer long inserted between adjacent square element regions 33, as shown in the expanded view, length of the regions being about 1 mm long in total. These element regions and element isolation regions are formed on the substrate 30 (refer to FIG. 4) in a laminating structure such as shown at Section (C) of FIG. 1. A silicon oxide film 35 on the surface of the substrate 30 is polished by the CMP method like the STI process explained in FIG. 1. FIG. 4 is a sectional drawing, showing the principal parts of the substrate 30 after polishing. With reference to FIG. 4, in the element region 31 whose one side is 500 micrometers long, the silicon oxide film 35 remains on a silicon nitride film 36, that is, polish is insufficient. Further, a dent (erosion) is generated in the element regions 33, each of which having a 0.5 micrometer long side, that is, polishing is excessive. Thus, the substrate 30 contains two undesired polishing states, i.e., insufficient polishing and excessive polishing. This problem cannot be solved, even if optimization of the amount of polishing, such as polishing time, is attempted.
To cope with the problem of the conventional technology 2, JP, 2001-7114 (hereinafter, called “the conventional technology 3”) proposes that elements be laid out according to a specified area ratio in order to attain uniform polishing. The conventional technology 3 is relative to wiring structures; however, an explanation of the conventional technology 3 as adapted to element domains follows.
According to the conventional technology 3, uniform polishing is supposed to be obtained if an area ratio of each of predefined small regions falls within a predetermined range, the small regions being divisions of a region to be polished, and each of the small regions including element regions and element isolation regions. Further, the area ratio is expressed by the area of the element regions in the small region/the area of the small region. Specifically, for example, a region that is the polishing target is divided into a plurality of 100-μm squares as shown in FIG. 5, each of the squares being called a small region that consists of element regions and element isolation regions. In FIG. 5, a small region 51 with no background shade (white box) represents a small region where the area ratio is, e.g., 80%. A small region 52 with shaded background (shaded box) represents a small region where the area ratio is, e.g., 20%. Assuming that small regions having the 80% area ratio and small regions having the 20% area ratio are arranged at random, an area ratio that satisfies a predetermined planarity (flatness) is specified. That is, elements are arranged such that each small region satisfies the specified area ratio. In this manner, according to the conventional technology 3, uniform polishing is supposed to be obtained by making the area ratio of each small region fall within a predetermined range, where only one size of the small regions is considered.
However, if the 20% area ratio small regions 52 are provided contiguously over several mm, and then the 80% area ratio small regions 51 are provided contiguously over several mm as shown in FIG. 6, uniform polishing of all the small regions cannot be obtained, resulting in poor planarity (flatness). Specifically, polishing is insufficient for the 80% area ratio small regions, and excessive polishing is carried out for the 20% area ratio small regions, which problems cannot be solved simultaneously.