Instruction sets used in computer systems employing so-called Complex Instruction Set Computing (CISC) architecture include both simple instructions (e.g. LOAD, or ADD) and complex instructions (e.g. PROGRAM CALL, or LOAD ADDRESS SPACE PARAMETERS). As an example to which the invention has particular relevance, see “IBM Enterprise Systems Architecture/390 Principles of Operation” (Publication Number SA22-7201-02, available from IBM Corporation, Armonk, N.Y.), which is incorporated herein by reference in its entirety. As these computer systems (e.g. IBM System 390) have become more powerful, larger percentages of the instruction set have been implemented using hardware execution units to increase system performance. Conventionally, the complex functions are implemented in microcode because building hardware execution units to execute them is expensive and error prone.
The TRANSLATE AND TEST (TRT) instruction was introduced in the original IBM System/360 architecture in 1964 and is well known in the art as described in detail in “z/Architecture Principles of Operation” (Publication Number IBM publication SA22-7832-03, available from IBM Corporation, Armonk, N.Y.), which is incorporated herein by reference in its entirety. The TRANSLATE AND TEST instruction is particularly useful in syntactically parsing a buffer, scanning left to right for specific tokens or delimiting characters. The TRANSLATE AND TEST REVERSE (TRTR) instruction is similar to TRANSLATE AND TEST, except that processing of the one-byte argument characters is done in a right-to-left manner rather than left-to-right.
The TRANSLATE AND TEST instruction shown in FIG. 1 uses a table of 256 bytes to scan a string of bytes. Each string byte is used as an index into a table, and the selected table byte is fetched. For the TRANSLATE AND TEST instruction, the selected bytes are tested, and the first non-zero table byte selected is returned to the program in a general register along with the address of the string byte which selected it; the instruction also sets the condition code, and does not update storage.
FIG. 1. depicts the format of the TRANSLATE AND TEST instruction. The bytes of the first operand are used as eight-bit arguments to select function bytes from a list designated by the second-operand address. The first nonzero function byte is inserted in a second general register, and the related argument address in a first general register. The L field specifies the length of only the first operand. The bytes of the first operand are selected one by one for translation, proceeding left to right. The first operand remains unchanged in storage.
Calculation of the address of the function byte is performed as in the TRANSLATE instruction. The function byte retrieved from the list is inspected for a value of zero. When the function byte is zero, the operation proceeds with the next byte of the first operand. When the first-operand field is exhausted before a nonzero function byte is encountered, the operation is completed by setting condition code 0. The contents of the first and second general registers remain unchanged.
When the function byte is nonzero, the operation is completed by inserting the function byte in second general register and the related argument address in first general register. The address points to the argument byte last processed. The function byte replaces bits 56-63 of second general register, and bits 0-55 of this register remain unchanged. In the 24-bit addressing mode, the address replaces bits 40-63 of first general register, and bits 0-39 of this register remain unchanged. In the 31-bit addressing mode, the address replaces bits 33-63 of first general register, bit 32 of this register is set to zero, and bits 0-31 of the register remain unchanged. In the 64-bit addressing mode, the address replaces bits 0-63 of first general register. When the function byte is nonzero, either condition code 1 or 2 is set, depending on whether the argument byte is the rightmost byte of the first operand.
Condition code 1 is set if one or more argument bytes remain to be translated. Condition code 2 is set if no more argument bytes remain. The contents of access first general register always remain unchanged. Access exceptions are recognized only for those bytes in the second operand that are actually required. Access exceptions are not recognized for those bytes in the first operand that are to the right of the first byte for which a nonzero function byte is obtained. This results in the following Condition codes: 0 if all function bytes zero; 1 if nonzero function byte and first-operand field is not exhausted; and 2 if nonzero function byte and the first-operand field is exhausted.
Currently, the TRANSLATE AND TEST instruction and the TRANSLATE AND TEST REVERSE instruction have limitations. One important limitation is that the TRANSLATE AND TEST and TRANSLATE AND TEST REVERSE instructions are only capable of scanning 8-bit characters. The text characters used in early data-processing systems were limited to 8-bit (or fewer) encoding such as ASCII or EBCDIC; the characters used in modem systems must accommodate a broader scope. For example, the Unicode standard uses a 16-bit encoding for characters. However, the TRANSLATE AND TEST instruction and the TRANSLATE AND TEST REVERSE instruction are only capable of scanning 8-bit characters, which requires complex coding to accommodate Unicode processing. Another limitation of the TRANSLATE AND TEST instruction and the TRANSLATE AND TEST REVERSE instruction is that the length of the buffer to be scanned by the instructions is hard-coded in the 8-bit L field of the instruction text. If the instruction is the target of an EXECUTE instruction, the length can be supplied in a register, but this requires more complicated programming, and the EXECUTE instruction slows the processing. A further limitation of the TRANSLATE AND TEST instruction and the TRANSLATE AND TEST REVERSE instruction is that they return only an 8-bit function code. Although the 8-bit function code is sufficient for most programs, it may be a limit in future designs of finite-state processes.