1. Field of the Invention
The present invention relates to a D to A converter for converting a digital input signal into a current or voltage corresponding to the digital input signal and outputting it and, more particularly, to a current segment type D to A converter.
2. Description of the Related Art
FIG. 1 shows a conventional current segment type D to A converter. This D to A converter includes a decoder 11, current source cells 12-1 to 12-n, and a resistor R1. The decoder 11 decodes digital input signals D0, D1, D2, . . . , Dm to generate control signals SD-1 to SD-n. The current source cells 12-1 to 12-n include constant current sources 12A-1 to 12A-n and switching circuits 12B-1 to 12B-n, which are ON/OFF-controlled by the control signals SD-1 to SD-n, respectively. One terminal of each of the switching circuits 12B-1 to 12B-n is connected to an output terminal 13. The resistor R1 is connected between the output terminal 13 and a power supply V.sub.DD.
In the above arrangement, for example, when the digital signals D0, D1, D2, . . . , Dm are 4 bit (m=3) signals, the number of the current source cells 12-1 to 12-n must be 15 (n=15), and the digital input signals D0, D1, D2, and D3 are decoded by the decoder 11, thereby generating control signals SD-1 to SD-15.
FIG. 2 shows a relationship between the digital input signals D0, D1, D2, and D3 and the control signals SD-1 to SD-15. In this case, the resistance of the resistor R1 is set to be 1 kQ, the power supply V.sub.DD is set to be 5 V, and each of the current values I0 of the constant current sources 12A-1 to 12A-15 is set to be 100 .mu.A. When a control signal SD-k (k=1 to 15) is set to "1" level, a switching circuit 12B-k controlled by this signal is turned on. When the control signal SD-k is set to "0" level, the switching circuit 12B-k controlled by this signal is turned off. A current Iout and a voltage Vout output from the output terminal 13 of the D to A converter are represented as follows, and an analog signal according to a digital input signal is output. EQU Iout=(2.sup.3 D3+2.sup.2 D2+2.sup.1 D1+2.sup.0 D0)I0 EQU Vout=V.sub.DD -R1 {(2.sup.3 D3+2.sup.2 D2+2.sup.1 D1+2.sup.0 D0)I0}
As shown in FIG. 3, MOS transistors Tr are used in the switching circuits 12B-1 to 12B-n of the CMOS type D to A converter. Each of the MOS transistors Tr has parasitic capacitances Cs1 and Cs2 between the gate and the drain and between the gate and the source, respectively. That is, the parasitic capacitance Cs1 is present between the output terminal 13 and the gate of the MOS transistor Tr. Theoretically, as shown in FIG. 2, when the digital input signals D0, D1, D2, and D3 are changed from D0=D1=D2=D3=0 to D0=D1=D2=D3=1, according to this, all the control signals SD-1 to SD-15 are changed from "0" level to "1" level, and the all the MOS transistors Tr, which are set in an OFF state, are turned on. As a result, the output voltage Vout drops from 5 V to 3.5 V. However, when the control signals SD-1 to SD-n are changed from "0" level to "1" level due to the presence of the parasitic capacitance Cs1, as shown in FIG. 4, the output voltage Vout is temporarily boosted to 5 V or more due to coupling caused by the parasitic capacitance Cs1, thereby generating some switching noise. The level of this switching noise is increased, as the number of transistors which must be simultaneously switched is large. For this reason, when a D to A converter has a high resolution, i.e., a large number of bits, the above switching noise is disadvantageously increased.