Multiprocessor systems often include a single bus to which a plurality of processors are connected. Many such busses have a bus master (e.g., one of the processors) that controls or initiates data transfers, while the other processors or other devices on the bus are slaves. Some systems allow changes as to which device or processor is the bus master, such that the current bus master will release the bus, and a short time later, another device becomes bus master. Such computer systems include single-processor systems (using a single processor coupled on a bus to a plurality of other devices), as well as multiple-processor systems.
Some such systems include a tri-state bus (or similar bus), wherein devices connected to the bus can drive the voltage low (e.g., a data zero), drive the voltage high (e.g., a data one), or provide a high-impedance and not drive the voltage (this last state allows another device on the bus to drive the bus with its data). When a bus master releases the bus, it will stop driving the bus, and go to a high-impedance state, and the next bus master will then start to drive the bus. In between, the bus is, or can be, in an entirely high-impedance state, in which no device is driving the bus (all devices are in a high-impedance state). This can occur in the entire bus, or on just one or a small number of lines of the bus.
During periods in which one or more lines of the bus are in an undriven or high-impedance state, these lines are quite susceptible to noise, e.g., electromagnetic signals are picked up by the high-impedance lines, such that they can have a voltage that is interpreted by receivers on the line as a voltage or a clock edge. As signal frequencies increase, radiated electromagnetic signals increase, making the problem worse.
The problem is particularly problematic for clock and strobe signal lines, since receivers can misinterpret noise on such clock lines as the clock signal from the new bus master before the new bus master has had a chance to establish the data that is to be clocked, and before the new bus master has had a chance to send its own clock signal.
Very fast access to data transmitted on the bus along with reliable data transfer (with no errors) is desired to enhance the speed of the computer systems which use those busses, and at the same time, reliability and serviceability of the computer system is required. Thus, it is desirable to minimize the times during bus-master changes.
Further, when data are passed over a distance, there is a need to synchronize the data to a local clock. For example, if one or more processors are connected across a common bus to a node-interface chip, even though the processor(s) and the node-interface chip are provided a common clock signal, the data passed between them will be shifted in phase or time relative to their local copy of the common clock.
Thus, there is a need for a method and apparatus that can quickly and reliably handle bus-master changes. There is also a need for a method and apparatus that can quickly and reliably re-synchronize data to a local clock.