Embodiments described herein relate generally to a semiconductor memory apparatus, and more particularly, to a domain crossing circuit of a semiconductor memory apparatus.
A synchronous semiconductor memory apparatus is a semiconductor apparatus that performs an operation in synchronization with a clock. At this time, command signals and data must be synchronized with an external clock in order to properly operate in internal circuits, and internal signals synchronized with internal clock signals must be synchronized with the external clock. This is referred to as a region switchover between an internal clock region and an external clock region, and is commonly referred to as a domain crossing.
For example, a domain crossing circuit allows the command signals or data, etc. to be synchronized with the internal clock generated using a delay-locked loop (DLL) in order to provide synchronized signal to the clock required in the internal circuit unit. However, according to physical positions of control pins (RAS, CAS, WE, CS, etc.) used with command signals, a difference may exist between the time when command signals are applied from an external system and the time when signals are actually received by the control pins. Therefore, when the signals applied to the control pins, etc. are delayed by a predetermined time to be synchronized with the internal clock, in consideration of such physical positions, it is difficult to synchronize nonsynchronization signals in a high-frequency clock accurately. As such, a timing margin of the signals may be insufficient.