Electronic devices such as programmable logic devices include input/output (I/O) circuits to interface with external devices. Many I/O standards exist for such circuits. One particular class of I/O standards involves the use of differential signaling to achieve enhanced noise rejection. For example, a differential input receiver determines the state of an input signal by comparing the difference between two differential input signals, which may be differential in either current or voltage. A conventional differential input receiver 100 is illustrated in FIG. 1. If the input pins are left floating, i.e., not driven with input signals, the output of receiver 100 is generally in an unknown state. Because receiver 100 is very sensitive to small differences in potential (or current, depending upon whether receiver 100 is designed to respond to voltage or current differences), a relatively small amount of noise present on the input pins will cause receiver 100 to drive its output into either a logic high state or a logic low state. Alternatively, receiver 100 may drive its output to oscillate between the two logic states.
Because unpredictable logic states and potential oscillations should be avoided in digital systems, failsafe biasing techniques have been developed for differential I/O circuits. For example, a conventional failsafe-biased differential input receiver 200 is illustrated in FIG. 2. Receiver 200 has input pins that couple to nodes on a circuit board 205. For example, a first input pin 210 couples to a node 215 whereas a second input pin 220 couples to a node 225. Thus, the potentials of pins 210 and 220 are tied to the potentials of nodes 215 and 225, respectively. To prevent pins 210 and 220 from floating, a weak pull-up resister R1 weakly pulls a potential of node 215 towards VCC. Similarly, a weak pull-down resister R2 weakly pulls a potential of node 225 towards ground. Because of the relative weakness of resistors R1 and R2, receiver 200 may still respond to differential input signals driven onto pins 210 and 220. However, when these pins float, receiver 200 will respond to the weak pull up and pull down of nodes 215 and 225 by driving its output into a known logic high state. A termination resistor RT may be present across nodes 215 and 225 to, for example, match an input impedance on pins 210 and 220 to a characteristic impedance on input traces (not illustrated) on circuit board 205. The combined impedance of the R1, R2, RT resistor network is thus given by RT | | (R1+R2) (RT in parallel with (R1+R2)). Assuming that the resistance for R1 and R2 is much larger than that of RT, then R1 and R2 have a negligible effect on the line termination. The resistance of RT may be adjusted as necessary to provide a desired input impedance.
Although the failsafe biasing of receiver 200 provides a known output state, a user has no way of altering this state. For example, during design of circuit board 205, design errors may occur such that input traces may need to be swapped to maintain the output of receiver 200 in a desired logical state while the input pins float. Accordingly, there is a need in the art for improved failsafe-biased differential input receiver designs.