This invention concerns integrated circuit electronics and more particularly a programmable fuse embodied in an integrated circuit.
Programmable fuses make it possible for a completed and packaged integrated circuit (IC) to be configured as desired by biasing terminals of the IC with voltages appropriate to alter selected fuses. For example, IC options such as output signal polarities can be programmed by fuses.
Integrated circuit memories comprise many essentially identical one bit memory element cells, arranged in rows and columns. When the completed IC is tested, some cells are usually found to be defective. IC memories are commonly provided with spare ("redundant") cells, and programmable fuses which can be selectively altered to reconfigure the memory circuit and substitute spare cells for defective cells, thereby repairing the memory.
In electrically programmable nonvolatile memory circuits (i.e. memories capable of retaining data without being continuously supplied with power), memory elements comprise either permanently programmable fuses, or indefinitely programmable, and erasable, charge traps. A fuse memory element in its initial unaltered state represents one binary value, and is programmed or altered to represent the other binary value.
Integrated circuit fuses generally have the drawback of requiring programming voltages and currents substantially above the normal operating range of typical integrated circuits. The fuse programming power requires relatively large access (addressing) transistors, which increase the size and cost of the IC, and also lengthen the time needed during normal operation to access the circuit elements. Lower fuse programming voltages more compatible with normal IC operating ranges are desirable.
In bipolar programmable read only memory (PROM) devices, fuses are typically formed by reduced cross section high resistance intervals in polycrystalline silicon or metal access lines to the memory cells. Polycrystalline silicon and metal (such as titanium-tungsten) fuses, like fuses in general, are initially closed (i.e. conductive) and programmed to be open (nonconductive). Applying a high voltage, typically 15 to 20 volts, to a polycrystalline silicon fuse causes typically 25 to 30 mA of current, which heats and oxidizes the polycrystalline silicon fuse into insulating SiO.sub.2.
ICs are normally covered with a protective passivating layer of Si.sub.3 N.sub.4, SiO.sub.2, or sandwich of Si.sub.3 N.sub.4 /SiO.sub.2. However, the heat from burning a polycrystalline silicon or metal fuse is also likely to fracture the overlying passivating layer. Therefore, polycrystalline silicon fuses require an opening in the overhead passivating layer to allow dissipation of heat during the programming of fuses. Unfortunately, any environmental moisture which penetrates the IC package is heated to a high temperature by blowing the polycrystalline silicon fuses, and can corrode conductors or electrical contacts not covered by the passivation layer. ICs using polycrystalline silicon fuses need to be hermetically sealed in ceramic packages, which are more expensive than the plastic packages which could otherwise be used.
Electrically programmable ROMs are also made from field effect devices. U.S. Pat. No. 4,502,208 describes a fuse 10 (FIG. 1) formed in substrate 11 by a V-groove 12 lined with 500.+-.50 angstroms of oxide dielectric 14 and covered with polycrystalline silicon electrode 16. Polycrystalline silicon 16 is connected to the source region of an associated access transistor (not shown). A programming voltage applied to both the gate and drain of the access transistor biases electrode 16 to create an electric field, focused at the apex of V-groove 12, which draws electrons through oxide dielectric 14 in an intense current which breaks molecular bonds in, or "ruptures", dielectric 14 while not breaking down planar gate oxide of the same thickness in the accompanying access transistor. Fuse oxide 14 may be formed thinner (500 angstroms) than the access transistor gate oxide (800 to 1000 angstroms) to facilitate breaking down the fuse oxide. Although the 0.3 mW of power used to program fuse 10 does not require large access transistors, the 25 volt programming voltage is significantly more than the normal operating range of a typical IC memory in which fuse 10 would be used. In addition, the depth of the V-groove, and thus the penetration of the apex into substrate 11, is difficult to control. One would not think of making oxide layer 14 thinner still, because thinner oxides have not been reliably reproduceable until recent developments in the separate technology of Electrically Eraseable Programmable Read Only Memories (EEPROMs).
Memory elements in erasable PROMs (EPROMs) are nondestructively (reversibly) programmed by charge traps rather than permanently programmed fuses. One type of EPROM, a Floating gate Avalanche junction MOS (FAMOS) device, resembles structure 20 of FIG. 2, which can also be used for a fuse, as explained below. In use as an EPROM, structure 20 operates basically like an NMOS transistor except that gate 23 "floats" electrically unconnected. With source 21 held at ground potential, 15 to 50 volt pulses applied to drain 26 reverse bias channel-drain PN junction 25 so that thermally generated electrons are accelerated with sufficient force that collisions dislodge other electrons and multiply the number of electron-hole pairs, generating an avalanche breakdown current of about 1 nA. Collisions scatter some electrons by hot electron injection into overlying oxide layer 24. Gate oxide 24 is not adversely affected by this current. Some electrons which penetrate oxide layer 24 are trapped in charge traps in floating gate 23 and exert an electric field which determines the conduction threshold of channel 22 and thereby programs cell 20. Exposing floating gate 23 to ultraviolet (U.V.) light excites trapped electrons, some of which are emitted from the bottom of gate 23 through oxide 24 to channel/substrate 22, thereby removing charge from floating gate 23, and thus "erasing" the cell. EPROMS are normally packaged in ceramic packages (not shown) which have a quartz window above the floating gates to admit U.V. light. The quartz window can be covered to block out radiation, or the EPROM can be packaged in a cheaper plastic package without a quartz window, to make the EPROM non-erasable and thus one-time programmable, which is equivalent to a PROM.
U.S. Pat. No. 4,507,757 to McElroy describes an oxide fuse 20 (FIG. 2), similar to a FAMOS EPROM transistor, in which gate 23 is connected to a lead (not shown) rather than floating. Fuse 20 is programmed one-time by reverse biasing channel body-drain PN junction 25 by 20 volts, which causes intense avalanching. Scatter-injected electrons heat and burn oxide 24, leaving a hole into which adjacent polycrystalline silicon melts, shorting gate 23 to drain 26. Oxide 24 is formed in a separate process step to be thinner (approximately 300A) and to have lower break down characteristics than the approximately 600A thick gate oxide used for access transistors (not shown). The 20 volt bias applied to gate 23 causes a field-plate effect between gate 23 and drain 26, which reduces the voltage necessary for reliable avalanche breakdown of oxide layer 24 to about 20 volts, which is less than the 25 volt programming voltage of fuse 10 (FIG. 1), but still exceeds, and is incompatible with, the normal operating range of typical integrated circuits. Junctions 25 for nonprogrammed cells have to withstand 25 volts, which makes it very difficult to "scale down" (reduce) the size of fuse 20. EPROM dimensions are presently scaled down to 1.25 micron width lines, with 250 angstrom thick gate oxide layers.
An electrically erasable EPROM (EEPROM) (not shown) is formed by a floating gate tunnel oxide (FLOTOX) structure which resembles an EPROM. A high programming or "write" potential (20V) applied to the control gate creates an electric field which draws electrons by Fowler-Nordheim tunneling from the grounded channel through a thin (50 to 200A) layer of thermally grown tunnel oxide, to be trapped in the floating gate and remain to exert an electric field on the underlying channel and thereby program the threshold voltage, as in an EPROM. The control gate charge is erased by an applied potential opposite the write potential which draws holes through the thin tunnel oxide to neutralize a previously written electron charge. In some prior art EEPROMS, one-time programmable memory elements are provided by spare EPROM cells rather than by fuses. Spare EEPROM cells are manufactured with no extra process steps, and are programmed using normal IC voltage levels, but are larger than other fuses. Also, erasable cells tend to leak charge and eventually revert to the erased (unprogrammed) state. There remains, therefore, a need for a one-time programmable fuse which is produced with no, or a minimum number of, additional process steps in an MOS IC memory device, which is small and does not require excesively high programming voltages, which has a small propagation delay, which is reliable, and which does not require an overhead opening, thereby making it suitable for use in circuits packaged in plastic packages.