A system bus in a computer can cause a power drain as a result of being left floating during periods of nonoperation. If the bus, which contains a plurality of conductive lines (sometimes called data lines or bit lines or bus lines or lines) on which signals are transmitted, is left floating during periods of nonoperation, circuit elements which are connected to the lines in the bus can move to an undesired state. This is especially true in CMOS circuitry because CMOS transistor pairs can receive a voltage level at which both transistors of the pair are conductive.
A standard industry design practice to deal with this problem is to connect a separate resistor from each line of the bus to a desired voltage source. When the bus is not operating, current passes through these resistors to adjust the voltage on the bus to the source voltage level. The problem with this solution is that where current passes through the resistors power loss results. Also, since one resistor is required for each data line, these resistors take up circuit board space. As computers get smaller and more portable, both space available for all the circuitry and the power used in the computer circuitry must be minimized. It is also beneficial to remove any unnecessary components to reduce the cost of the overall system.
FIG. 1 shows a typical way a central processing unit (CPU) is connected through an ASIC (Application Specific Integrated Circuit) device to drive data signals onto two buses in a computer system (only one bit line of each bus is shown). Each bit line of each bus has a pull-up resistor connected between it and a 5 volt source. The 80C88 compatible CPU, in FIG. 1, sends address, data, and status signals to the ASIC during operation. The ASIC with a 8237 compatible DMA, a 8259 compatible Interrupt Controller, a 8288 compatible Bus Controller, at least two data multiplexers (MUX) with MUX control signals inputs, with one MUX feeding through a buffer to a system (random access memory--RAM) bus, and one MUX feeding through a buffer to an expansion bus. A resistor is attached to each bit line of each bus and connected to a known voltage source.
The ASIC uses the above mentioned components as appropriate to place signals on the RAM bus and the expansion bus when the appropriate MUX control signal is provided during a normal operating cycle. Each resistor shown is typical for each bit line of a bus wherein said resistor pulls up (or can pull down) each bit line of a bus for bus stabilization. The resistance of the resistor is sufficiently high that during normal operation there is not enough current bleed across the resistor to or from the bus side of the circuit to distort the signal on the bus. When a normal operating cycle is completed the bus is left unconnected to any data source. If any bus line of an unconnected bus is at a different voltage than the voltage source on the other side of the resistor then current flows through the pull-up/pull-down resistor connected to that bus line until the source voltage level is reached by that bus line. Power is dissipated in the resistor as current flows to equalize the voltage on each side of the resistor. Each time a normal operating cycle ends, which can be many times a second, current flows in all resistors connected to bus lines where the source voltage is different than the bus voltage and power is dissipated, shortening battery life.
In another example of the prior art, where buses are directly tied to a central processing unit (CPU), several manufacturers, for example, Harris in their 80C88 device described at page 3-89 of their 1988 Digital Product Data Book, have addressed this problem by placing a bus hold circuit in the CPU with two inverters in series between the output of the output driver to the bus and the input of the input buffer from the bus. An example of a typical prior art bus hold circuit is shown in FIG. 1A. "Bus hold" circuits maintain a valid logic state if no driving source is present. In the Harris device mentioned above, to overdrive the "bus hold" circuits, an external driver must be capable of supplying 400 .mu.A minimum sink or source current at valid voltage levels. Since this "bus hold" circuitry is active and not a "resistive" type, the associated power supply current is negligible. Power dissipation is significantly reduced when compared to the use of passive pull-up resistors. As with pull-up resistors, one "bus hold" circuit is required for each bus line.
Power dissipation is reduced in the circuitry of FIG. 1A when compared to pull-up or down resistors by avoiding switching the bus from a high or low state to its opposite state during the approximately fifty percent of the time the next active signal carried by the bus is the same as the previous signal carried by the bus.
The CPU type "bus hold" circuit shown in FIG. 1A is a circuit which maintains a logical zero or one based on a stronger signal without any external means for selecting between feedback and data signals to apply to the bus. It relies on internal resistance to override the "bus hold" inverters, providing no means for anticipating when the bus use will occur, and as a result can introduce timing delays and excessive current requirements when additional devices, including additional CPUs, are introduced to the bus.