The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can enable a double word line by using the fact that word lines of two blocks are enabled at the same time in a block set of 2N rows during an NK refresh operation.
In an isolated cell capacitor, a data is stored in the form of electric charges. The electric charges stored in the cell capacitor become extinct by the leakage current. It is thus necessary to bring out, read and re-write the data before the data is completely extinguished. This is called a refresh operation.
The refresh operation is performed by varying a row address strobe signal/RAS from high to low, turning on a word line corresponding to a row address, and enabling a sense amp. Accordingly, all the cells connected to one word line are refreshed at the same time.
The refresh operation of the DRAM is carried out by one cycle of externally receiving a refresh address and dropping and raising the RAS signal/RAS. A refresh cycle indicates the number of the cycles selecting all the rows of the DRAM and finishing the refresh operation. That is, the refresh cycle indicates how many word lines must be enabled to refresh all cells of the DRAM.
The conventional memory device such as the DRAM is so designed that its refresh cycle can simultaneously support the NK and 2NK refresh operations, and is processed according to a bonding option. After fabricated, the memory device is used on a board where the NK refresh operation is supported or a board where the 2NK refresh operation is supported. In general, in the case of the 2NK refresh operation, the memory device is processed according to the "H" bonding option, and in the case of the NK refresh operation, the memory device is processed according to the "L" bonding option.
The conventional memory device always performs an access operation (namely, read/write) according to the 2NK refresh operation, regardless of the refresh cycle.
FIG. 1 is a block diagram showing addresses of a row path of the conventional semiconductor memory device performing the NK refresh operation.
A first buffer 10 receives and buffers a block set division address ADD_2NK and a row active refresh mode designating signal NK_REFRESHB, a second buffer 12 receives and buffers a block selection address ADD_BLOCK, and a third buffer 14 receives and buffers a word line selection address ADD_WL for selecting one word line from a cell array in the selected block.
When the refresh mode designating signal NK_REFRESHB is at a low level, output signals ADDX_2NK, ADDXB_2NK from the first buffer 10 are compressed and fixed to a high level. The fixed signals are re-buffered in a fourth buffer 16 with output signals ADDX_BLOCK, ADDXB_BLOCK from the second buffer 12, and inputted to a block control unit 20. The block set division address ADD_2NK is compressed in the block control unit 20, and thus two of the 2N blocks (B; set of cell arrays) are selected. Output signals ADDX_WL, ADDXB_WL from the third buffer 14 are re-buffered in a fifth buffer 18, decoded by a decoder 22 and inputted to the two selected blocks B.
Accordingly, a bit line sense amp BL S/A and a bit line are connected by corresponding bit line sense amp control units CTRL_1.about.CTRL_2n+1 in the two selected blocks B. The word lines existing on the cell arrays 24a, 24b, 24c, 24d in the two blocks B are enabled by main word line driving units MWL_1.about.MWL_2n.
FIG. 2 is a block diagram illustrating the address ADD_2NK for dividing the whole cell array into two in the conventional 2NK block set. The conventional 2NK block set consists of two 1NK block sets, and the respective cell arrays 0.about.N include K word lines. The most significant bit of the addresses 00 . . . 00.about.11 . . . 11 for respectively designating the cell arrays is the address ADD_2NK which divides the whole cell array into two in the 2NK block set and which is compressed during the NK refresh operation. On the other hand, the addresses except for the most significant bit become the block selection addresses ADD_BLOCK. An upper cell array and a lower cell array are selected at the same time by the identical block selection address ADD_BLOCK in the block set which is divided into an upper NK block set and a lower NK block set due to the address ADD_2NK compressed during the NK refresh operation.
As described above, in the case that the NK refresh operation and the 2NK refresh operation are implemented in one memory device and the NK refresh operation is performed by the bonding option, any of the row addresses is not used, and the number of the word lines to be enabled during the read/write operation is increased by two times. As a result, the current consumption of the row path is increased by two times during the access operation, as compared with the semiconductor memory device performing the 2NK refresh operation.