1. Field of the Invention
The present invention relates to a buffer circuit, which is suitable for an input interface circuit receiving an input signal from the outside of a chip of a semiconductor integrated circuit using a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor), and particularly used as an input buffer circuit suitable for a TTL (Transistor--Transistor Logic) input/output protocol.
2. Description of the Related Art
FIG. 1 shows a typical circuit diagram of a TTL input buffer circuit obtained by a conventional technique. This circuit is two-input NOR circuit using the most basic push-pull logic circuit technique of a CMOS structure. Q.sub.1 and Q.sub.2 are PMOS (P channel type MOS) transistors, and Q.sub.3 and Q.sub.4 are NMOS (N channel type MOS) transistors. A denotes an input signal from the external portion of a chip, and reference numeral 11 denotes an input signal terminal of the chip. If a chip selection signal CS* is in a selection mode, that is, low potential level ("0" level), an inverting signal of the input signal A (A) is output as an output signal A. If the chip selection signal CS* is in a non-selection mode, the output signal A is set to "0" level.
Since the signal is generated in the chip, the so-called CMOS logic level, that is, a high potential level ("1" level) is 5 V (power source potential) and a low potential level ("0" level) is 0 V (earth potential). An input/output signal of the external section of the chip, generally is operated at a logical level, which is suitable for TTL input/output protocol. At this time, the input level "1" is 2.2 V (or 2.0 V) or more, and the input level "0" is 0.8 V or less. Regarding a logical amplitude of TTL circuit, for example, the high potential level is 3.4 and the low potential level is 0.4 V, and an amplitude margin is small in the TTL circuit.
At this time, a logical threshold voltage (inverting voltage) of input A of a NOR circuit in FIG. 1 is preferably 1.5 V, which is an intermediate level ("1/2" level) between "1" level and "0" level, in view of a noise margin. Particularly, since the logical amplitude is large in the TTL circuit, and large noise is generated, it is required that the logic threshold voltage of the input of the CMOS logic circuit be constant. A gate width W of each transistor and a gate length L are selected to adjust to the threshold voltage 1.5 V. In this case, the logical threshold voltage V.sub.INV can be expressed by the following simple approximate expressions if an analytical method wherein a current voltage characteristic of the MOS transistor is expressed by Shockley type is used. ##EQU1## wherein V.sub.CC is power supply voltage, V.sub.TN, V.sub.TP are a threshold voltage of NMOS transistor and that of PMOS transistor, respectively, W.sub.nl /L.sub.pl, W.sub.n2 /L.sub.p2 are gate width/gate length of the respective transistors Q.sub.3, Q.sub.1, Q.sub.2, and .mu..sub.N and .mu..sub.P are carrier mobility of NMOS transistor and that of PMOS transistor, respectively.
The above conventional circuit may be designed such that V.sub.INV in expression (1)=1.5 V under a standard voltage by controlling .beta..sub.N /.beta..sub.P (that is, size of transistor). However, in TTL input/output protocol, V.sub.CC =5 V.+-.0.5 V, and V.sub.INV definitely changes if the power supply voltage V.sub.CC changes in the TTL input/output protocol. However, since V.sub.TN and V.sub.TP must be allowed to vary in the range of .+-.0.2 V in the variation in the manufacturing process, this generates variation of V.sub.INV. Moreover, V.sub.TN, V.sub.TP, .beta..sub.N, and .beta..sub.P varies by influence of the change of temperature. Due to this, in the prior art, V.sub.INV easily varies in the range of .+-.0.5 V in the TTL input/output protocol, so that noise margin in the TTL input/output protocol of the input level in FIG. 1 is largely reduced. There is need for the output buffer to be delayed in order to avoid increasing noise. However, this will prevent the high speed performance of the operation frequency of LSI.
In order to overcome the above disadvantage, the prior art of FIG. 2 shows a system in which a standard voltage source V.sub.CS (about 1.5 V) where a power supply voltage characteristic and a temperature characteristic are compensated and an input signal A from the external unit are compared and amplified by a CMOS type differential amplifier 21, thereafter obtaining an inverting signal of the input signal A through a NOR circuit. According to this system, the output voltage of the CMOS type differential amplifier 21 is largely amplified to the amplitude (0 to 5 V) of a CMOS circuit. Due to this, it can be discriminated whether input signal level is "1" or "0" without depending on the change of the power supply voltage and that of the temperature. However, the speed of the input buffer circuit was delayed by the operation response speed of the differential amplifier 21.