1. Field of the Invention
The present invention relates to techniques for handling coprocessor instructions in a data processing apparatus.
2. Description of the Prior Art
A data processing apparatus will typically incorporate a processor core for processing a sequence of data processing instructions. To improve the performance of the data processing apparatus, it is known to provide one or more coprocessors designed specifically to handle particular computations. As an example, it has been found that general purpose processors are not well suited to the performance of floating-point computations, and hence this has led to the development of specialised floating-point units (FPUs) to handle such computations. The FPU may be embodied as a coprocessor which the processor core can use to handle floating-point computations. As another example, a coprocessor may be provided specifically for performing MPEG encoding/acceleration.
In data processing apparatus incorporating a number of coprocessors, the sequence of data processing instructions to be processed by the processor core will typically include a number of coprocessor instructions for handling by the appropriate coprocessor. Accordingly, when the processor core comes across such a coprocessor instruction, it will pass that coprocessor instruction to the appropriate coprocessor for execution. In order to identify the appropriate coprocessor for any particular coprocessor instruction, each coprocessor instruction typically has a coprocessor number associated therewith that uniquely identifies the coprocessor which is to execute that coprocessor instruction.
It will be appreciated that the number of bits set aside for specification of the coprocessor number limits the number of coprocessors that may be specified. For example, if four bits are used to specify the coprocessor number, then it is clear that up to sixteen coprocessors can be uniquely identified. Typically, bit space is at a premium. Accordingly, if the number of coprocessors desired in a particular implementation would exceed that uniquely identifiable by the existing bits allocated to specify coprocessor numbers, it will not typically be possible merely to increase the number of bits used to specify the coprocessor number in order to allow all of the desired coprocessors to be uniquely identified.
As an example, the coprocessor number is often specified as a field within the instruction itself. The instruction needs to be specified by a predetermined number of bits, for example 32 bits, and needs to include a variety of information, for example any conditions for execution of the instruction, an identification of the computation required, identification of source and destination registers, etc. Accordingly, each bit within the instruction has to be used very carefully to ensure that all of the required information can be specified within the available bits. Hence, considering the earlier example where four bits are used to specify the coprocessor number, thereby allowing sixteen coprocessors to be uniquely identified, it is unlikely that it would be possible to subsequently allow 5 bits to be used to specify the coprocessor number if it is desired to provide more than sixteen coprocessors.
Further, in certain implementations, one or more of the possible coprocessor numbers may be reserved for future use, and this serves to further limit the number of coprocessors that may be incorporated within any particular design.
Accordingly, as it becomes desirable to add more and more coprocessors into a data processing apparatus design, the problem of allocating coprocessor numbers to those coprocessors will become more acute.