1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particulculy, to an improvement of the output circuit of a semiconductor memory device such as a synchronous dynamic random access memory (SDRAM) device.
2. Description of the Related Art
An output portion of a prior art semiconductor memory device is constructed by a data bus, a data bus charging circuit formed by a load transistor for charging the data bus, a data bus discharging circuit for discharging the data bus in accordance with a cell read data signal, a buffer connected to the data bus, and a CMOS push-pull type output circuit formed by a P-channel MOS transistor connected between a power supply terminal and an output terminal and an N-channel MOS transistor connected between the output terminal and a ground terminal. This will be explained later in detail.
In the above-described prior art semiconductor memory device, however, since the transistor of the push-pull type output circuit on the power supply terminal is of a P-channel type, the pulling up drive ability of this transistor is so small that the read operation speed is low. If the drive ability of this transistor is increased, the transistor has to be increased in size, which would increase the device in size.
Also, in the above-described semiconductor memory device, when the cell read data signal stays at the same data such as "1" for a plurality of cycles, the voltage at the output terminal repeats a high level and a low level, which would increase the power consumption.
Further, in the above-described semiconductor memory device, when the cell read data signal is high to turn ON the data bus charging circuit, the load transistor becomes in an ON-state, which also would increase the power consumption.