The present invention relates to methods and apparatus for allocating Direct Memory Access (DMA) communication bandwidth between competing entities within a computing system.
Real time, multimedia applications are becoming increasingly important. These applications require extremely fast processing speeds, and data transfer speeds, such as many thousands of megabits of data per second. While some processing systems employ a single processor to achieve fast processing speeds, others are implemented utilizing multiprocessor architectures. In multiprocessor systems, a plurality of sub processors can operate in parallel (or at least in concert) to achieve desired processing results.
In recent years, there has been an insatiable desire for faster computer processing data throughputs because cutting edge computer applications are becoming more and more complex, and are placing ever increasing demands on processing systems. Graphics applications are among those that place the highest demands on a processing system because they require such vast numbers of data accesses, data computations, and data manipulations in relatively short periods of time to achieve desirable visual results.
In some processing systems, DMA techniques are employed where the computer architecture allows data to be sent directly between a device and a memory without involving any microprocessor(s) in the data transfer. The architecture usually includes a memory controller that receives data transfer commands from the device(s) of the system to cause the transfer of data. A conventional DMA command may specify a data block size, a starting virtual address within the system memory from/to which data are to be transferred, and a start address of the device to/from which data are to be transferred. In this manner, data may be rapidly transmitted between a specified device and a specified memory without burdening a processor.
Where only one device and/or one memory seek access to a data bus to conduct DMA data transfer, the above process is effective. However, a problem may arise where several devices or entities seek DMA data transfers, or DMA communication tasks, for the same, or at least for overlapping, time periods. This is particularly true where different levels of urgency are associated with different respective DMA communication tasks. If the DMA communication task that starts first proceeds to completion without interruption, a more urgent DMA communication task may experience an unacceptable processing delay. Accordingly, there is a need in the art to allocate DMA communication bandwidth among competing devices and/or among competing DMA communication tasks.