Density and complexity of today's high-end application-specific integrated circuit (ASIC) chips continue to increase. As a result, multiple clock domains, i.e., logic circuits operating at different clock frequencies, often exist within a single chip. The asynchronous boundaries between clock domains are typically not timed interfaces, such that the values at the asynchronous boundaries arrive unpredictably. This creates a challenge when performing simultaneous logic built-in self-testing (LBIST) of all clock domains in a chip, such that there is a relatively high probability of not matching a good chip signature, due to multi-cycle characteristics of asynchronous boundaries. One solution has been to perform a separate LBIST sequence on each separate clock domain. Unfortunately, this is inefficient since it requires multiple LBIST iterations for each clock domain, and, moreover, does not address asynchronous boundary testing. Another solution has been to utilize an optimized clock design with special tuned circuitry to delay capture clocks in order to exclusively test AC or DC characteristics at specific asynchronous boundaries, without taking into account conflicting effects due to internal logic or other asynchronous boundaries. In either case, there is a requirement of detailed, a priori knowledge of the clock domain frequency requirements of each component as well as additional test design overhead to achieve desired test results.
Accordingly, it is desirable to provide an improved technique for self-testing IC's having multiple clock domains. It is further desirable that such technique provides for testing internal chip logic, while simultaneously providing for testing asynchronous clock boundaries. Such a technique would advantageously facilitate aggregation of independently designed logic circuits employed in Systems on a Chip (SoC's), for example, each having its own independently designed clock domain.