Memory devices, such as random access memory (RAM), read-only memory (ROM), non-volatile memory (NVM) and the like, are well known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing, programming/erasing and data retrieval operations.
These devices provide an indication of the data, which is stored, therein by providing an output electrical signal. A device called a sense amplifier (SA) is used for detecting the signal and determining the logical content thereof.
In general, sense amplifiers determine the logical value stored in a cell by comparing the output of the cell (voltage or current) with a threshold level (voltage or current). If the output is above the threshold, the cell is determined to be erased (with a logical value of 1) and if the output is below the threshold, the cell is determined to be programmed (with a logical value of 0).
The threshold level is typically set as a level between the expected erased and programmed levels, which is high enough (or sufficiently far from both expected levels) so that noise on the output will not cause false results.
An example of a prior art sense amplifier circuit is shown in FIG. 1. This sense amplifier circuit is similar to a sense amplifier described in U.S. Pat. No. 6,469,929 to Alexander Kushnarenko and Oleg Dadashev, entitled “Structure and method for high speed sensing of memory array”.
FIG. 1 illustrates a prior art sensing system for a memory array 110, which includes a plurality of memory cells arranged in any number of rows and columns. For purposes of illustration, assume that a memory cell 111 is to be read (i.e. sensed). Memory cell 111 has its drain and source terminals coupled to array bit lines BN and BN+1 and its control terminal coupled to a word line W1. Memory cell 111 is selectively coupled to a system bit line BL using a column decoder 104 (for selecting the array bit lines) and a row decoder 103 (for selecting the word lines). The system bit line BL may include an associated parasitic capacitance CBL that is proportional to the number of memory cells coupled to the selected array bit line.
Similarly for a memory array 112, a memory cell 113 has its drain and source terminals coupled to array bit lines BM and BM+1 and its control terminal coupled to a word line W1. Memory cell 113 is selectively coupled to a system bit line BL_REF using a column decoder 105 (for selecting the array bit lines) and a row decoder 106 (for selecting the word lines). The system bit line BL may include an associated parasitic capacitance CREF_BL that is proportional to the number of memory cells coupled to the selected array bit line.
To read (i.e. sense) the state of memory cell 111 in memory array 110, the array bit line BN is coupled to the system bit line BL, the array bit line BN+1 is coupled to a predetermined voltage (e.g. ground), and the word line W1 is coupled to a read voltage (e.g., 3 volts). The operation of decoders 103 and 104 to provide the above-described coupling is well known and therefore not described in detail herein.
The previous paragraph and the following description hold true, mutatis mutandis, for memory cell 113 in memory array 112, that is, the circuitry on the right side of FIG. 1.
To ensure that a sense amplifier 145 correctly senses the logic state of memory cell 111, the system bit line BL may be charged to a predetermined level (e.g., approximately 2V) before the sensing of memory cell 111. The optimal charging of the system bit line BL may facilitate a quick transition to the predetermined voltage without overshooting this predetermined voltage. This charging operation may be initiated using a charge initiation device P2 and advantageously controlled using a control unit 120 (control unit 121 for the right side of FIG. 1) that quickly and efficiently charges the system bit line BL.
Specifically, to initiate a charge operation, an active signal CHARGE turns on charge initiation device P2 (P7 for the right side of FIG. 1). Charge initiation device P2 may comprise a PMOS (p-channel metal oxide semiconductor) transistor, wherein the active signal CHARGE is a logic 0. When conducting, charge initiation device P2 transfers a pull-up signal provided by the sense amplifier 145 (explained in detail below) to control unit 120.
Control unit 120 may comprise a static clamp including an NMOS (n-channel metal oxide semiconductor) transistor N1 (N2 for the right side of FIG. 1) and a dynamic clamp including a PMOS transistor P1 (P8 for the right side of FIG. 1). The transistor N1 may have its drain connected to charge initiation device P2 and its source connected to system bit line BL. Transistor N1 receives a bias voltage VB on its gate. Bias voltage VB is the gate bias voltage for transistor N1 as defined by:VTN<VB<VBLD+VTN                wherein VBLD is the desired voltage on bit line BL and VTN is the threshold voltage of the n-type transistor (e.g., 0.6V). In this manner, transistor N1 charges bit line BL very quickly to VB-VTN. At this point, transistor N1 transitions to non-conducting, i.e. the static clamp deactivates, and the dynamic clamp is activated (as explained below).        
The dynamic clamp of control unit 120 may include PMOS transistor P1 having its source connected to charge initiation device P2 (also the drain of transistor N1) and its drain coupled to bit line BL (also the source of transistor N1). The dynamic clamp further comprises a comparator C1 (C2 for the right side of FIG. 1), which compares a reference voltage BIAS and the bit line voltage BL and then outputs a signal VG representative of that comparison. Specifically, comparator C1 outputs a low signal VG if VBL is less than BIAS and outputs a high signal VG if VBL is greater than BIAS (or if comparator C1 is disabled). The reference voltage BIAS may be approximately equal to the desired bit line voltage VBLD on the system bit line BL. The transistor P1 receives the signal VG on its control gate.
Sense amplifier 145 may include first stages 130 and 131 and second stage 140. The first stage 130 includes a pull-up device N4, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P2, and a current sensing device P3, which is a PMOS transistor having its drain and gate connected to charge initiation device P2 and its source connected to the supply voltage VDD. Note that in this configuration, current sensing device P3 advantageously functions as a diode, which is explained in further detail below.
The first stage 131 has an identical configuration to first stage 130. Specifically, first stage 131 includes a pull-up device N3, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P7, and a current sensing device P6, which is a PMOS transistor having its drain and gate connected to charge initiation device P7 and its source connected to the supply voltage VDD.
After charge initiation device P2 (P7 for the right side of FIG. 1) is activated, both pull-up transistor N4 (N3) and current sensing device P3 (P6) conduct strongly. During the charge operation, the system bit line BL initially receives a pull-up voltage of VDD-VTN via pull-up transistor N4 (N3). Then, via current sensing device P3 (P6), the voltage on the system bit line BL increases to VDD-VTP, wherein VTP is the threshold voltage of the PMOS transistor. Note that the voltage VDD-VTP is substantially equal to the desired system bit line voltage VBLD. At this point, this increased voltage on the system bit line BL turns off pull-up transistor N4 (N3). Because current sensing device P3 (P6) is connected as a diode, only current IBL (IBL13 REF) is detected. Therefore, depending on the state of the sensed memory cell, a predetermined current can flow through current sensing device P3 (P6).
Current sensing devices P3 and P6 in first stages 130 and 131, respectively, have current mirrors provided in second stage 140. Specifically, the current IBL through current sensing device P3 is reflected in the current I1 through a PMOS transistor P4, whereas the current IBL13 REF through current sensing device P6 is reflected in the current I2 through a PMOS transistor P5. The ratio of the currents through current sensing device P3 and PMOS transistor P4 defines the gain of first stage 130, whereas the ratio of the current through current sensing device P6 and PMOS transistor P6 defines the gain of first stage 131. A latch circuit 141 (e.g., amplifier block) may amplify and compare currents I1 and I2.
The sense amplifier 145 may not operate properly unless the VDD supply voltage is greater than a minimum voltage VDD_MIN, which is defined as follows:VDD—MIN=VDIODE—MAX+VBL—MIN+VP1/P8+VP2/P7  (1)
In equation (1), VDIODE_MAX is the maximum voltage drop across PMOS transistor P3 or PMOS transistor P6, VBL_MIN is the minimum acceptable bit line voltage for the non-volatile memory technology, VP1/P8 is the drain-to-source voltage drop of PMOS transistor P1 (or PMOS transistor P8), and VP2/P7 equal to the drain-to-source voltage drop on PMOS transistor P2 (or PMOS transistor P7).
For example, if VDIODE_MAX is equal to 1.0 Volt, VBL_MIN is equal to 1.8 Volts, and VP1/P8 and VP2/P7 are equal to 0.05 Volts, then the minimum supply voltage VDD_MIN is equal to 2.9 Volts (1.8V+1V+0.05V+0.05V). In such a case, memory device 100 would not be usable in applications that use a VDD supply voltage lower than 2.9 Volts.
In addition, sense amplifier first stages 130 and 131 are sensitive to noise in the VDD supply voltage. If, during a read operation, the VDD supply voltage rises to an increased voltage of VDD_OVERSHOOT, then the voltages VSA1 and VSA2 on the drains of PMOS transistors P3 and P6 rise to a level approximately equal to VDD_OVERSHOOT minus a diode voltage drop. If the VDD supply voltage then falls to a reduced voltage of VDD_UNDERSHOOT, then transistors P3 and P6 may be turned off. At this time, sense amplifier first stages 130 and 131 cannot operate until the cell currents IBL and IBL_REF discharge the voltages VSA1 and VSA2. If the cell current IBL is low, then sense amplifier first stage 130 will remain turned off until the end of the read operation, thereby causing the read operation to fail.
Accordingly, it is desirable to provide a sensing system that can accommodate low supply voltages and tolerate supply voltage fluctuations.