The nonvolatile memory that has become the mainstream on today's market, as typified by flash memory and SONOS memory, is realized by technology in which electrical charge is accumulated on an insulating film disposed above a channel, and the threshold voltage of a semiconductor transistor is varied. In this type of charge accumulation type of nonvolatile memory, miniaturization of the transistors is essential in order to achieve large capacity, but as the film of the insulating film that retains the charge becomes thinner, leakage currents increase, so the charge retention capability is reduced. Therefore it is difficult to achieve large capacity with the charge accumulation transistor type of nonvolatile memory.
Therefore attention has been focused on variable resistance elements that can be switched between not less than two values of electrical resistance level by some kind of electrical stimulation, as a nonvolatile memory element. The reason for this is that for normal variable resistance elements, in most cases differences in electrical resistance can be detected even when miniaturized, so it is considered that if there are materials and a principle for varying the resistance value, then they can be advantageously miniaturized. In contrast, in the type that accumulates electrical charge on a capacitance, such as a DRAM for example, the signal voltage becomes lower as the quantity of charge accumulated is reduced due to miniaturization, so it becomes difficult to detect the signal.
Several technologies have already been proposed as technologies for varying the electrical resistance value. For example, when a voltage or current is applied to a structural body having a structure in which a metal oxide is sandwiched between electrodes (metal/metal oxide/metal), it is known that the resistance value of the metal oxide varies. Normally a memory device that uses this property is referred to as a Resistance Random Access Memory (ReRAM). A 3-dimensional cross-point structure has been proposed for an actual variable resistance memory device structure, in which memory cells are disposed at the intersection points of word lines (WL) and bit lines (BL), from the point of view of large scale integration.
However, further large scale integration of 3-dimensional cross-point structure memory devices is becoming difficult. This is because as plane structures are miniaturized, the amount of investment in photolithography machines significantly increases for devices in the 20 nm generation and beyond. Also, as the number of stacked layers increases, the number of processes increases accordingly. As a result the increase in manufacturing cost due to multiple layering is greater than the effect of the reduction in the wafer cost per bit due to multiple layering, so on the contrary the cost per bit increases. Also, as a result of the increase in the number of stacked layers, contacts extending in the vertical direction become longer, so wiring delays become significant, and the operating margin of the memory cells becomes smaller.