1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to the fabrication of semiconductor devices.
2. Description of the Related Art
The process used to form capacitors is very important when manufacturing semiconductor devices with reduced design rules. A great deal of effort has been expended developing processes to form capacitors which occupy small areas.
In general, the capacitance of a capacitor is determined by the area of the capacitor and the dielectric constant of the dielectric layer. The area of the capacitor is determined by the effective area of the dielectric layer located between the storage electrode and the plate electrode of the capacitor. In general, the magnitude of the capacitance of a capacitor is proportional to the effective area of the dielectric layer. NO (nitride-oxide) is often used as a dielectric layer for capacitors. The NO (nitride-oxide) dielectric layer can be replaced by a high-k dielectric layer such as Ta2O5, Al2O3, BST ((Ba, Sr) TiO3). A high-k dielectric layer can be used with a metal electrode; however, use of metal electrodes presents many difficulties.
Methods have been developed to increase the effective area of a dielectric layer by modifying the charge storage electrode. A structure of three-dimensional electrodes is taught in U.S. Pat. No. 5,597,756 by Fazan, et. al., entitled “Process for fabricating a cut-shaped DRAM capacitor using a multi-layer partly-sacrificial stack”.
FIGS. 1a and 1b show a prior art method of fabricating a semiconductor device having a three-dimensional electrode. FIG. 1a shows a semiconductor substrate 10 that has a lower structure including capacitor contact plugs 15. The structure shown has an interlayer insulating layer 16 and an etch stop pattern 17. A molding pattern 18 is formed on the interlayer insulating layer 16, so as to expose the capacitor contact plug 15 and the interlayer insulating layer 16 around it. The etch stop pattern 17 is formed to prevent the interlayer insulating layer 16 from being damaged during an etch process which removes the molding pattern 18.
A lower structure includes landing plugs 14, gate electrodes 11, and mask insulating layers 12. The capacitor contact plugs 15 are connected to the semiconductor substrate 10 via the landing plugs 14. The landing plugs 14 are connected to the semiconductor substrate 10 via the exposed area between spacer insulating layers 13 covering the sidewalls of the gate electrode 11 and the mask insulating layer 12.
The interlayer insulating layer 16 is formed of a material that has good flow characteristics for planarization. The interlayer insulating layer 16 having a good flow characteristic typically has a high wet etch rate. The etch rate of the material in the interlayer insulating layer 16 should be higher than the etch rate of the material in the molding pattern 18. The interlayer insulating layer 16 that is exposed around the capacitor contact plug 15 may be wet etched relatively quickly after the molding pattern 18 is formed. The wet etch creates an undercut U under the etch stop pattern 17. If the undercut U is excessively formed it may connect neighboring charge storage electrodes thereby causing a problem.
As shown in FIG. 1b, a cylindrical-shaped charge storage electrode 19 may be achieved by first, forming a conductive layer pattern on the inner walls of the molding pattern 18 and on the capacitor contact plugs 15, and by second, removing the molding pattern 18. The undercut U is covered with a conductive layer during the deposition of the conductive layer and as shown in FIG. 1b and a connection A, between of the neighboring charge storage electrodes 19 may occur. The potential of such connections deteriorate the reliability of the devices formed using the process described above.