The continuing trend toward increasing the number of semiconductor devices in chips has driven a continued reduction in the feature sizes of the devices. Although device feature sizes are decreasing, in some memory devices, such as dynamic random access memories (DRAMs), capacitors therein should continue to provide at least a threshold capacitance so as to reliably store data.
One method of increasing the capacitance of capacitors in semiconductor memories includes reducing an equivalent thickness of oxide (EOT; Toxeq) of a dielectric layer therein. For example, capacitors that are fabricated according to a 70 nm design rule may need a dielectric layer thickness of about 14 EOT to provide sufficient capacitance when the capacitors have a cylindrical structure height of 1.8 μm. The lower electrode of the capacitors is often formed from polysilicon. Because the polysilicon can become undesirably oxidized during fabrication of the capacitors, it can be difficult to reduce their dielectric layer EOT to 14 or lower.
Fabrication of capacitors with metal lower electrodes have been proposed to avoid such oxidation of the lower electrode during fabrication. Capacitors with metal lower electrodes have been formed from titanium nitride (TiN), which provides low reactivity, stable leakage current, and high conductivity.
A conventional method of forming a lower electrode using TiN is explained below with reference to FIGS. 1A through 1C.
Referring to FIG. 1A, an interlayer insulating layer 20 with a conductive plug 25 extending there through is formed on a semiconductor substrate 10. An etch stopper 30 of silicon nitride is deposited on the interlayer insulating layer 20. A mold oxide layer 35 is formed on the etch stopper 30. The mold oxide layer 35 and the etch stopper 30 are etched to expose a predetermined portion of the conductive plug 25, thereby defining a lower electrode region 35a. A titanium nitride (TiN) layer 40 for a lower electrode is deposited on the lower electrode region 35a and the mold oxide layer 35. A sacrificial oxide layer 45a is deposited on the titanium nitride layer 40.
Referring to FIG. 1B, a chemical mechanical polishing (CMP) process is performed on the sacrificial oxide layer 45a and the titanium nitride layer 40 until a surface of the mold oxide layer 35 is exposed. Then, the remaining sacrificial oxide layer 45a and the mold oxide layer 35 are wet-etched using an LAL solution (mixture solution of deionized water, NH4F and HF) or HF solution to form a lower electrode 40a. 
Referring to FIG. 1C, after a dielectric layer 45b is formed on a surface of the lower electrode 40a and on the etch stopper 30, an upper electrode 50 is formed on the dielectric layer 45b to form a capacitor 55.
When removing the remaining sacrificial oxide layer 45a and the mold oxide layer 35 to form the lower electrode 40a, the wet etch chemical may penetrate into the lower electrode 40a or the interface between the lower electrode 40a and the etch stopper 30. When the etch chemical so penetrates, the interlayer insulating layer 20, which is located below the lower electrode 40a and the etch stopper 30, may be partially removed. Moreover, when the conductive plug 25 is formed from polysilicon, the conductive plug 25 may be also partially removed by the penetrating etch chemical. When the interlayer insulating layer 20 and/or the conductive plug 25 are partially removed by the etch chemical, the electrical characteristics of the capacitor 55 may be deteriorated and cause a bit failure in the associated memory device.