This invention relates to a parallel-serial converter and more particularly to a parallel-serial converter which is formed of MOS transistors and adapted to be included in a large scale integrated (LSI) circuit.
The conventional parallel-serial converter is constructed, as shown in FIG. 1, by cascade connecting a plurality of selection-delay unit circuits 1, each of which receives the corresponding one of parallel signals P1 to Pn, and also an output signal from the immediately preceding unit circuit, and sends forth an output signal to the immediately succeeding unit circuit, and is further so arranged that the final unit circuit issues parallel signals Pn to P1. The conventional selection-delay unit circuit, for example, the unit circuit 1 supplied with a parallel signal P1 is arranged as shown in FIG. 1. The unit circuit 1 comprises a selection circuit 2 and delay circuit or shift register 3. The selection circuit 2 comprises AND gates 2a, 2b, NOR gate 2c and inverter 2d. The shift register 3 comprises transfer gates 3a, 3b, and shift register 3 comprises transfer gates 3a, 3b, and inverters 3c, 3d. The AND gate 2a is supplied with a parallel signal P1 and mode selection signal S/L. The AND gate 2b is supplied with a mode selection signal S/L and an output signal Q from the immediately preceding unit circuit. The selection circuit 2 selects either the output signal Q or the parallel signal P1 and delivers the selected signal to the shift register 3. This shift register 3 is actuated in response to input clock signals .0.1 and .0.2 and delivers an output signal Q delayed by the period of the clock signal .0.1 or .0.2 to the immediately succeeding unit circuit. To describe in greater detail with reference to FIGS. 2A to 2C, a clock signal .0.1 shown in FIG. 2A is supplied to the control gate of the transfer gate 3b. The clock signal .0.2 having an opposite phase to that of the clock signal .0.1 of FIG. 2A is conducted to the control gate of the transfer gate 3a. The period of the clock signals .0.1, .0.2 has a period of one .tau.. As shown in FIG. 2C, the mode selection signal S/L has a pulse width of one .tau. and a period of n.tau.. (The numeral n denotes a number of parallel signals.) Where the mode selection signal S/L has a logic level "1" (referred to as "a load mode"), then a parallel signal P1 is supplied to the selection circuit 2. Where the mode selection signal S/L has a logic level "0" where referred to as "a shift mode", then the parallel signal P1 supplied to the selection circuit 2 is shifted in the shift register 3 by one .tau.. A signal thus shifted is conducted to the selection circuit 2 of the immediately succeeding unit circuit 1. As a result, the final unit circuit 1 sends forth serial signals converted from the parallel signals P1 to Pn in the order of Pn to P1.
As seen from FIG. 1, the conventional selection circuit 2 comprises two AND gates 2a, 2b and NOR gate 2c and inverter 2d. When arranged into the LSI form, therefore, the parallel-serial converter has the drawbacks of unavoidably enlarging a chip size and increasing power consumption. Where the parallel signals have a large bit number n, the above-mentioned drawbacks prominently appear.