This application claims priority to Korean Patent Application No. 2004-105326, filed on Dec. 14, 2004, the disclosure of which is hereby incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a driver circuit in a semiconductor device such as a semiconductor memory device, with signal swing balance and enhanced testing capability.
2. Description of the Related Art
Various semiconductor devices implemented as integrated circuit chips, such as a central processing unit (CPU), a memory device, or a gate array, are used within electronic products such as personal computers, servers, or workstations. As the operating speed of such electronic products becomes faster, a swing width of signals interfaced between the semiconductor devices decreases for minimizing signal delay time. However, as the swing width decreases, external noise interference increases and signal reflection due to impedance mismatching at an interface stage becomes critical.
Impedance mismatching may be caused by external noise, variation of power supply voltage, changes in operating temperature, and variations during manufacturing processes. Such impedance mismatching impedes high-speed data transmission and may distort output data. In turn, transmission of a distorted output signal frequently causes problems at a receiving side, such as setup/hold fail, erroneous input level determination, and the like.
In particular, in electronic products employing a dynamic random access memory (DRAM), the frequency of a signal bus has dramatically increased for high speed operation. Various bus termination techniques are being studied for minimizing the distortion of signal integrity by solving the impedance mismatching problem. One study revealed that, in an electronic system having a stub bus structure, on-die termination (ODT) rather than mother board termination (MBT) is more advantageous for signal integrity. One prior art reference relating to motherboard termination is U.S. Pat. No. 5,945,886, and one prior art reference relating to on-die termination is U.S. Pat. No. 6,157,206.
For on-die termination, bus termination is at an I/O port of a memory mounted on a memory module. Thus, on-die termination is also referred to as on-chip termination and is employed in the vicinity of pads in an integrated circuit chip.
In a semiconductor memory device such as a SDRAM (synchronous DRAM) of a double data rate (DDR) type, a resistor having a fixed resistance is coupled to a pad as typical on-die termination for impedance matching. However, such fixed resistance is disadvantageous for resistance termination when the environment of the signal receiver changes. Recently, on-die termination with changing resistance is being developed.
Data exchange modes in semiconductor devices employing on-die termination may be classified into a single-ended mode and a differential-ended mode. The single-ended mode semiconductor memory devices use a DC voltage as a reference voltage and determine the state of data based on a difference between the reference voltage and a data signal, thus requiring one data pad to transmit one-bit data. On the contrary, differential-ended mode semiconductor memory devices determine the state of data based on two complementary data signals, thus requiring two data pads to transmit one-bit data.
The differential-ended mode is robust to common mode noise for reduced signal swing width, thereby increasing operating frequency. Thus, the differential-ended mode is mainly used for an input and output circuit of high-speed semiconductor devices.
In general, an open test and a short and leakage test are performed on a semiconductor device. A main purpose of the open test is to determine whether a connection between a test system and a semiconductor device is normal. For a wafer, the state of a contact between each pad of a semiconductor device and a probe card is checked. For a package, the state of a contact between a pin of a semiconductor device and a socket is checked.
In the open test, input and output pads/pins of a semiconductor device are all grounded and a bias current is applied to a pad/pin to be tested. Thereafter, a voltage at the test pad/pin is measured to determine whether the measured voltage is within an acceptable range. If the measured voltage is within the acceptable range, the test pad/pin is determined as being in normal contact. If the reference range is not within the acceptable range, the test pad/pin is determined to be short-circuited or open-circuited.
The short and leakage test is for discovering a short fault between a pin and a pin, between a pin and a power supply voltage pin, or between a pin and a ground node. The short and leakage test may also be for measuring possible leakage current. In the short and leakage test, different voltage levels are applied to a test pin to be test and to adjacent pins, and then a current flowing through the test pin is measured. The measured current indicates any fault when compared to a suggested specification.
Testing of the single-ended mode semiconductor memory device is not as trouble-some as testing of the differential-ended mode semiconductor memory device. Differential-ended mode testing is disclosed in U.S. Pat. No. 5,488,306. In testing the differential-ended mode semiconductor memory device, termination resistance and an externally applied voltage may cause a problem, which will be described in greater detail with reference to FIG. 1.
FIG. 1 shows a conventional output driver circuit as an example of a differential-ended mode semiconductor device using on-die termination with variable resistance. As shown in FIG. 1, the conventional output driver circuit has a differential-ended mode structure, such as a differential amplifier. The output driver circuit comprises a first resistance unit 10, a second resistance unit 20, a clock input unit 30, and a biasing unit 40.
The first resistance unit 10 includes a plurality of resistors coupled in parallel between an external voltage terminal Vext and a first data pad DQ that outputs a first data signal. The first resistance unit 10 has a termination resistance that determines a voltage swing width of the first data signal. The second resistance unit 20 includes a plurality of resistors coupled in parallel between the external voltage terminal Vext and a second data pad DQB that outputs a second data signal. The second resistance unit 20 has a termination resistance that determines a voltage swing width of the second data signal. The first data signal is complementary to the second data signal.
The clock input unit 30 comprises a first NMOS transistor N10 connected between the first data pad DQ and the biasing unit 40 for receiving a first input clock signal IN at its gate, and a second NMOS transistor N12 connected between the second data pad DQB and the biasing unit 40 for receiving a second input clock signal INB at its gate. The second input clock signal INB is complementary to the first input clock signal IN.
The biasing unit 40 acts as a current source and determines the swing width of the first and second data signals. The biasing unit 40 includes NMOS transistors N14, N16, N18, N20 and N22 connected in parallel between the clock input unit 30 and a ground terminal. An external bias signal Bias applied at the gates of the NMOS transistors N14, N16, N18, N20 and N22 determines a current flowing through the biasing unit 40.
In the prior art of FIG. 1, the first resistance unit 10 and the second resistance unit 20 are controlled by one control signal Ctrl. Assuming that the first resistance unit 10 or the second resistance unit 20 each comprises three resistors, the control signal Ctrl has three binary control bits. The control signal Ctrl controls a number of resistors of the first resistance unit 10 and the second resistance unit 20 that becomes coupled to the respective data pads for such resistance units 10 and 20. The use of binary control bits allows fine control of the termination resistance.
The control signal Ctrl is commonly determined by a mode register set (MRS) code which is now briefly described. A mode register stores data programmed to control several operating modes of a synchronous semiconductor memory device. The asynchronous memory device has operating modes or features that are determined by a control signal. A central processing unit (CPU) sets operating modes to use, such as column address strobe (CAS) latency, a burst length and the like, of the synchronous semiconductor memory device in advance and then accesses the synchronous semiconductor memory device.
Such operating modes are set in the mode register, and a collection of a series of mode registers is called a mode register set (MRS). A series of codes indicating modes of the semiconductor memory device are set in the mode register set, and these codes are called mode register set codes.
Since the resistance of the first resistance unit 10 and the resistance of the second resistance unit 20 in the conventional output driver circuit are controlled by one control signal Ctrl, the resistances of the first and second resistance units 10 and 20 are the same in the prior art of FIG. 1.
FIG. 2 shows data signals output at data pads in FIG. 1 for a normal state, and FIG. 3 shows data signals in FIG. 1 having different voltage swing widths. In a normal state, the first data signal output at the first data pad DQ and the second data signal output at the second data pad DQB have the same voltage swing width S1, as shown in FIG. 2.
The logic state of data is determined based on whether a value obtained by subtracting a voltage level of the second data signal from a voltage level of the first data signal is positive or negative. For example, if the value obtained by subtracting the second data signal from the first data signal is positive, the logic state of data is “1” and, if the value is negative, the logic state is “0.” If the first data signal and the second data signal have the same voltage swing width, the logic state of data is easily determined.
However, when the first data signal and the second data have different swing widths, the logic state of data may not be easily determined. For example in FIG. 3, a swing width S1 of the first data signal at the first data pad DQ is the same as the normal value in FIG. 2. However, a swing width S2 of the second data signal at the second data pad DQB is smaller than the normal value. With such variation in swing width, the logic state of data may not be easily determined.
The reduced swing width may be caused by variation in the resistance of the second resistance unit (20 of FIG. 1). Accordingly, control of the resistance of the second resistance unit 20 is desired. However, because the resistance of the first resistance unit 10 and the resistance of the second resistance unit 20 are controlled by one control signal, change in the control signal for controlling the resistance of the second resistance unit 20 also results in corresponding change in the resistance of the first resistance unit 10. Thus, achieving a same swing width in the first data signal and the second data signal is difficult.
In addition, detecting faults during an open test or a short and leakage test in the differential output driver circuit may be difficult because of a voltage level at the external voltage terminal Vext and because of the presence of the first and second resistance units 10 and 20. In other words, in the open test for the first data pad DQ or the second data pad DQB, detection of faults may be difficult because the voltage level at the external voltage terminal Vext is measured together through the first resistance unit 10 and the second resistance unit 20. In the short or leakage test on the first data pad DQ or the second data pad DQB, even though another voltage for testing is applied on adjacent pads, detection of faults may be difficult since current may flow from a voltage difference between the external voltage terminal Vext and the test voltage.
Thus, a driver circuit is desired with signal swing balance and with enhanced testing capability.