1. Technical Field
This invention generally relates to memory devices, and more specifically relates to clocked memory devices.
2. Background Art
The proliferation of modern electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. One important component in many modem electronic systems is memory. Various types of memory devices have been developed. Static Random Access Memory (SRAM) is a type of memory device that retains its memory contents as long as the device has power without the need for refreshing the memory. Dynamic Random Access Memory (DRAM) is a type of memory device that must be continually refreshed in order for its contents to be maintained. The support circuitry for DRAMs is thus more complex than for SRAMs because the DRAM must be periodically refreshed. However, the advantage of DRAMs is the smaller size of each cell, making it possible to build DRAMs that have much higher memory density than is possible with SRAMs.
Several different types of DRAMs have been developed. The first DRAMs were asynchronous DRAMS that specified access time in nanoseconds (ns). This means that the appropriate address and control signals were applied to the DRAM, and the data was guaranteed to be present on the output data lines within the specified access time. Later, synchronous DRAMs (SDRAMs), a type of clocked memory device, were developed to use a clock input to synchronize the operations within the DRAM device. The result is higher data rate with access times specified in clock cycles. The first SDRAMs have become known as single data rate devices, because the data transfer occurs at a rate of one transfer per clock cycle. Newer devices are known as double data rate (DDR) devices because the data transfer occurs at a rate of two transfers per clock cycle (one on the rising edge of the clock, and one on the falling edge of the clock).
One important timing parameter for clocked memory devices such as SDRAMs is known as write recovery time, which is the time between when the last data bit is written to the device and when the device can go into its precharge operation. In the prior art, write recovery time is an asynchronous parameter that is set according to the anticipated operational conditions for the device. The write-recovery time is typically a hard-wired feature of an SDRAM design, and can be specified in a number of clock cycles or a timer delay value or a combination of both, but is typically specified in nanoseconds (ns).
As the speed of operation for SDRAMS has increased over time, problems with having a hardwired write recovery time have become apparent. Without a way to dynamically set write recovery time in a clocked memory device, these devices will not deliver adequate performance over a broad range of operating frequencies. As a result, device manufacturers will have to tune a clocked memory device and set its hard-wired write recovery time for a specific range of speeds, which may limit the frequency of operation of the clocked memory device.
According to the preferred embodiments, a clocked memory device includes a programming mechanism that allows the write recovery time during a command with auto precharge enabled to be dynamically set to some function of the input clock. In the preferred embodiments, the programming mechanism includes a control register with programmable bits that allows specifying the write recovery time according to the bit values written to the control register. For example, write recovery time could be specified as a whole or fractional number of clock cycles. By specifying the write recovery time as a function of the clock that may be dynamically set, the clocked memory device may be used at its highest performance capabilities over a wide range of operating frequencies.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.