Mask ROM's have information written into them during the manufacturing process. They are suited for cases where a large volume of ROM's with the identical memory content are used. Mask ROM's are consequently used in systems such as control memories in microprogram-control-type computers, microcomputer program memories, and for various kinds of terminals.
Conventional mask ROM's may be classified into two types. The first type is where the "0" or "1" information to be written is distinguished by the presence or absence, of electrode contact holes, the pattern of which is formed by a custom-made photomask. More specifically, the transistors are arranged in a matrix, and electric contact holes are selectively formed in the transistor drain regions. Application of an input signal to the gate of the transistors results in either a high or low potential level output of each transistor, depending on whether or not the each drain region is connected to the electric source via an electrode contact hole. The different outputs enable determination of whether the information stored in each transistor is "0" or "1".
The first type of mask ROM is manufactured by the following process. Many enhancement type metal-insulator semiconductor (MIS) (typically, metal-oxide semiconductor (MOS)) transistors are arranged on a semiconductor substrate to form memory cells. The substrate is then covered by an insulation layer. A program photomask is used to selectively form electrode contact holes in the insulation layer at the drain regions of the memory cell transistors based on the desired information content. Subsequent completion of the mask ROM requires only the formation of a surface protective layer on which wiring is formed and the formation of bonding pad.
This manufacturing process is advantageous in that the processing from the master slice device to the completed mask ROM is very short. At the same time, however, the process is disadvantageous because the necessity of providing drain regions for the formation of electrode contact windows for each memory cell MOS transistor reduces integration density.
In the second type of mask ROM, the "0" or "1" information to be written is distinguished by whether the transistor is an enhancement type or depletion type. More specifically, a plurality of memory cell MOS transistors are connected in series. A high level input signal is supplied to the gate of the nonselected MOS transistors and a low level input signal to the gate of the selected MOS transistors. This places selected MOS transistors of the enhancement type in the off state, and produces a high output level at the source terminal of the series-connected MOS transistors. At the same time, this places selected MOS transistors of the depletion type in the on state and produces a low output level at the source terminal of the series-connected MOS transistors. In other words, the memory matrix is formed as a NAND gate circuit.
The second type of mask ROM is manufactured by the following process. When the MOS transistors are formed on the semiconductor substrate, a programmed mask is used to create impurity introduction layers only on the regions forming the MOS transistors. MOS transistors are then formed into either depletion types of enhancement types in accordance with the desired memory information.
With the second type of mask ROM, it is not necessary to provide electrode contact windows for each MOS transistor, therefore enabling higher integration density than the first type. However, this second type of mask ROM requires many processing steps from the programming process to the completed mask ROM, such as the formation of the gate electrodes and output wiring, formation of the source.multidot.drain region, formation of the electrode contact windows, formation of the metallic wiring layer, formation of the surface protective layer, and formation of bonding pads.