Due to the rapid growth in the electronic industry, electronic devices have gradually been developed towards the direction of multi-function, high speed and low-profile, and as a result reducing surface area of circuit board and miniaturization of the package are the two primary targets in the electronic industry. In the demand of high integration and miniaturization of semiconductor packages, many have adopted a multi-chip module (MCM) with multi-layer board using the technology of interlayer connection so as to increase the usable surface area of the circuit bard in order to meet the demand of high integrated circuit.
However as semiconductor devices become more highly integrated and with increased multi-layers, electronic components within the multi-chip module are also increased in number. In the condition where the number of leads and circuit complexity are increased but the circuit volume is decreased, the noise accompanying with it is also increases. This is usually solved by providing passive components such as resistor, inductance, and capacitor in the semiconductor package for reducing noise, stabilizing circuits as well as increasing electronic functionality.
Conventionally, these passive components are mounted on the surface of the circuit board where it is not occupied by the semiconductor chip using a surface mounting technology (SMT). However this method requires a relative larger surface area of the circuit board, thereby making it difficult to reduce the overall size of the semiconductor package. Moreover these passive components are often mounted into different regions of the circuit board, thereby increasing the difficulty of disposing circuit and the complexity of fabricating process.
As shown in FIG. 1, a plurality of passive components 12 are mounted on one surface of the circuit board 1. The circuit board can be a printed circuit board or a substrate. In order to prevent the passive components to hinder the connection between the semiconductor chip and the circuit board, conventionally the passive components 12 are mounted at the edge or corner of the circuit board 1 or the places where the semiconductor chip would not be interfered. This type of arrangement although increases the circuit disposing area but the effectiveness of eliminating noise and stabilizing circuit is decreased accordingly. Moreover, as the semiconductor device is developed toward high functionality, the number of passive components 12 in the package is increased accordingly, therefore using conventional method, the volume of semiconductor package would be increased so as to accommodate semiconductor chips 11 and large number of passive components 12, thereby making it not possible to meet the requirement of low-profile package.
In addition, as the semiconductor device is developed towards the direction of more multi-functions, higher operational speed, and reduced volume, multi-layer circuit board must be developed with low-profile, increased multi-layers, high circuit layout density and low noise level. As a result, in order to further reduce the volume of circuit board, a multi-layer circuit board with embedded passive components is developed by stacking the passive components between each multi-layered circuit board in a film-like manner. The material and method of forming passive components within the multi-layered stacking circuit board has been one of major focuses in the industry. Generally, prior to forming a new layer, a material forming passive components are formed on the dielectric layer, then the process of printing and photolithography is followed to define the shape, resistance and capacitance of the passive components. Then the dielectric layer is laminated and a circuit patterning is performed to form a circuit layer so as to electrically connect the embedded passive components and other electronic components.
Although the technology of forming embedded film-like passive components between each layers of the multi-layered circuit board can solve the problem of limitation of available circuit disposing area in the prior art, the fabricating process of forming embedded passive components between each layers of the multi-layered circuit board is complex and moreover because of the large difference of coefficient of thermal expansion (CTE) between the dielectric layer and embedded passive components, a peeling issue is often involved in the fabricating process.
Accordingly, there is an urgent need to develop a semiconductor package in which the prior art problems are solved and is low-profiled and able to accommodate sufficient number of capacitor passive components in a single unit, so as to improve the functionality of the electronic device.