Multi-power domain provides a good approach to achieve low power applications. For example, depending on situations, a circuitry may be configured to use a lower instead of a higher power supply to reduce power consumption. Traditional approaches generally use a level shift to shift signals between two power domains in a multi-power domain design. In various memory arrays, a level shift circuitry (also referred to as a level shift) is used in every LIO of the memory array. The level shift circuitry, depending on complexity, can include a large number of transistors and associated circuitry. Depending on the size of the array, the number of LIOs can be numerous. For example, in U.S. Pat. No. 5,594,696, the level shift circuit uses about six transistors constituting a relatively large portion of the memory cell. For another example, a 4 Megabit (Mb) memory could include as many as 600 LIOs. As a result, using a level shift in every LIO consumes a large portion of die area, which is generally undesirable, especially in advanced technologies where electronics devices and appliances are continually decreasing in size.