1. Field of the Disclosure
The present disclosure relates to non-volatile memory cells and processes for forming them, and more particularly to non-volatile memory cells including capacitor structures and processes for forming the same.
2. Description of the Related Art
A conventional non-volatile memory (“NVM”) cell includes a control gate electrode and a floating gate electrode. One of the design challenges for NVM cells has been to increase the capacitive coupling between the control gate electrode and the charge storage layer (e.g., a floating gate electrode) without significantly increasing the substrate area occupied by the NVM cell. The coupling ratio is given by the following equation.αFC=CFC/CFT=CFC/(CFC+CFS+CFB+CFD),
wherein:
αFC is the coupling ratio;
CFC is the capacitance between the charge storage layer and the control gate electrode;
CFT is the capacitance between the charge storage layer and other parts of the NVM cell;
CFS is the capacitance between the charge storage layer and the source region;
CFB is the capacitance between the charge storage layer and the channel region; and
CFD is the capacitance between the charge storage layer and the drain region.
EPROM Tunnel Oxide (“ETOX”) NVM cell has a control gate electrode and a floating gate electrode with sides that are substantially coterminous. The coupling ratio for an ETOX NVM cell is approximately 0.5. Floating-gate Electron Tunneling MOS (“FETMOS”) NVM cell has a control gate electrode that overlies and laterally surrounds at least part of the floating gate electrode. The area occupied by the floating gate electrode can be about the same as for the ETOX NVM cell. The coupling ratio is approximately 0.6; however, the FETMOS NVM cell is typically larger than an ETOX NVM cell because the control gate electrode extends beyond the sides of the floating gate electrode.
Another design is disclosed in U.S. patent application Ser. No. 10/871,772, entitled “Transistor with Vertical Dielectric Structure” by Matthew et al. filed Jun. 18, 2004, which is assigned to the current assignee hereof. The structure disclosed in the patent application is of a type referred to as a “FinFET” NVM cell. With a conventional FinFET NVM cell, a coupling ratio higher than 0.7 but less than 0.75 may be achieved. While the coupling ratio for the FinFET NVM cell is an improvement over the ETOX and FETMOS NVM cells, a higher coupling ratio without incurring a significant increase in NVM cell area is still desired.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments.