1. Field of the Invention
The present invention relates generally to the field of microprocessor-based data processing systems and, more particularly, to regulating power consumption in snoopable components.
2. Description of the Related Art
Advances in semiconductor processing technology have made it possible to compact the feature sizes of integrated circuits to allow more transistors to be fabricated on a single semiconductor substrate. For example, the most sophisticated microprocessors being manufactured today typically comprise a single integrated circuit made up of several million transistors. Although these astounding technological advances have made it possible to dramatically increase the performance and data handling capabilities of modern data processing systems, these advances have come at the cost of increased power consumption. Increased power consumption, of course, means that there is more heat that must be dissipated from the integrated circuits.
Because excessive power consumption and heat dissipation are now a critical problem facing computer designers, various power-saving techniques have evolved for minimizing power supply and current levels within computer systems. Many of these techniques adopt the strategy of powering down the microprocessor when not in use to conserve power. This approach, however, is not without drawbacks.
Some power management modes targeting snoopable components require components to flush their snoopable contents before entering a non-snoopable low power mode. Depending on the cache size, flushing all cache contents could take tens of thousands of cycles, and often can limit the application of power management modes. Also, some components are prevented from entering into a low power mode, because the component still needs to respond to snoops. However, power is wasted if the time between snoops is relatively long.
Therefore, a method and apparatus is needed for an opportunistic system able to enter into a low power mode during periods between snoops.