1. Technical Field
The invention relates generally to computer systems and more particularly relates to a CPU/Peripheral bus interface where the processor local (system) bus is wider than the peripheral bus.
In an exemplary embodiment, a CPU/peripheral bus interface and bus arbitration protocol are used in a computer system based on a 64-bit x86 class microprocessor in which the processor local bus is 64-bits, and the peripheral bus is the 32-bit BL bus.
2. Related Art
Microprocessor-based computer systems commonly include both a processor local (system) bus, and a peripheral bus. The local bus is used for data transfers between the microprocessor (CPU) and system memory (DRAM and L2 cache)--address and control buses are included in the local bus architecture. The peripheral bus is used for data transfers to/from various peripheral devices (such a video controller, disk, keyboard, etc.).
The CPU initiates data transfers with peripheral devices by running I/O Read/Write bus cycles--in addition, if the computer system supports direct memory access (DMA), a peripheral device can initiate DMA transfers with system memory. For DMA Reads/Writes, and arbitration protocol is used to arbitrate control of the local bus for DMA transfers.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: in an computer system based on a 64-bit x86 microprocessor, providing an improved interface between the 64-bit processor local bus and a 32-bit VL peripheral bus, and improving DMA operations.
For x86 computer systems, a typical 64-bit system configuration includes a 64-bit microprocessor such as a Power.sup.586 manufactured by Cyrix Corporation interfaced to a memory subsystem (DRAM and L2 cache) over a 64-bit local bus, allowing data transfers of two dwords (8 bytes). Such 64 bit systems are commonly configured with both a high performance peripheral bus, such as the 32-bit VL bus, and a 16-bit ISA bus for compatibility with existing ISA peripherals.
System (chipset) logic includes memory/bus controller for controlling CPU-Memory (DRAM and L2 cache) data transfers, and in the case of DMA transfers, arbitration of control of the local bus. This chipset logic also controls the CPU-Peripheral bus interface between the 64-bit local bus and the peripheral bus, supporting both CPU-initiated and DMA transfers.
In the x86 bus architecture, bus cycles (on the local bus) are defined by bus cycle definition and control signals. Bus cycle definition signals are driven by the CPU, and include (a) M/IO#--distinguishes memory and I/O cycles, (b) D/C#--distinguishes between data transfer cycles and control operations (such as halt, interrupt acknowledge, and code fetch), and (c) W/R#--distinguishes between write and read cycles. Bus cycle control signals include: (a) ADS#--driven by the CPU to indicate that valid address and bus cycle definition signals are available, and (b) BRDY#--driven by the system logic to indicate that the current transfer within a burst cycle or the current single-transfer bus cycle can be terminated.
In addition, for data transfer cycles, the CPU drives byte enable signals BE#&lt;7:0&gt; onto eight byte enable signal lines. The byte enable signals provide a byte enable code designating the valid data bytes within the 64-bit (8 byte) data transfer.
The 32-bit VL bus supports 4 byte (dword) transfers, and provides a direct connection to the processor local bus--the current principal application for this bus is to provide a local bus video interface. The 16-bit ISA bus supports byte and word (2 byte) transfer, and is the bus interface for a wide class of industry-standard peripherals (keyboard, disks, add-on cards, etc.)--a VL/ISA converter (bridge) chip interfaces VL to ISA, controlling data transfers between ISA peripherals and CPU-Memory over the VL bus.
DMA is supported for both VL masters and ISA peripherals. In ISA-only systems, an ISA DMA controller and the memory/bus controller are tightly coupled--the memory/bus controller runs the DMA bus cycles. In VL bus systems, the VL masters are granted (through arbitration) direct access to the local bus for running VL master bus cycles--if the system includes a VL/ISA converter, it typically functions as a VL master.
The x86 bus architecture currently supports two bus arbitration protocols for DMA accesses to system memory: (a) HOLD/HLDA (Hold Acknowledge), and (b) BOFF# (Back-Off). For the HOLD/HLDA protocol, HOLD is asserted by the memory/bus controller to the CPU, which completes the current bus cycle, and then returns HLDA, relinquishing control of (tristating) the local bus. The BOFF# protocol is used to obtain immediate access to the local bus--in response to BOFF# from the memory/bus controller, the CPU aborts the current bus cycle, and relinquishes local bus control (an aborted bus cycle must be restarted in its entirety when BOFF# is deasserted).
For 64-bit computer systems, implementing a CPU-Peripheral bus interface necessarily involves a hardware mechanism for interfacing the 64-bit processor local bus to the 32-bit VL peripheral bus. Specifically, the VL bus is interfaced to the local bus--byte lane steering is used to multiplex 64-bit data transfers onto the 32-bit VL bus one dword at a time. The VL/ISA converter interfaces the 16-bit ISA but to the low word of the VL bus.
Current 64-bit computer systems use a multiplexer to provide the hardware interface between the processor local and VL peripheral buses. A 64/32 CPU/VL interface multiplexer includes a 64-bit interface to the local bus and a 32 bit interface to the VL bus, together with multiplexing logic to implement lane steering. Currently available 64/32 interface multiplexers require more than 160 signal pins for the 64/32 bit data buses and associated control. In addition, the I/O drivers for the data buses require tight control and increase bus loading.