1. Field of the Invention
The present invention relates to a memory device using a semiconductor.
2. Description of the Related Art
Terms used in this specification will be briefly explained. First, when one of a source and a drain of a transistor is called a drain, the other is called a source in this specification. That is, they are not distinguished depending on the potential level. Therefore, a portion called a source in this specification can be alternatively referred to as a drain.
In this specification, “connection” means a structure in which effective direct current can be supplied at least temporarily. Therefore, a state of connection means not only a state of direct connection but also a state of indirect connection through a circuit element such as a wiring or a resistor, in which direct current can be supplied. It does not matter whether a circuit is actually designed so that direct current is supplied thereto.
For example, in the case where a switching element is provided between two nodes, direct current can be supplied in a certain condition (i.e., only when the switch is on); therefore, the structure can be expressed as “the nodes are connected to each other”. On the other hand, in the case where only a capacitor is provided between two nodes, effective direct current cannot be supplied through the capacitor; therefore, the structure can be expressed as “the nodes are not connected to each other”.
Similarly, in the case where only a diode is provided between nodes, direct current can be supplied when the potential of one of the nodes is higher; therefore, the structure can be expressed as “the nodes are connected to each other”. In this case, even if potentials with which current does not flow are supplied to the two nodes because of the circuit design (in which case current does not actually flow between the two nodes through the diode), the structure is expressed as “the nodes are connected to each other” in this specification.
For example, in the case where a node A is in contact with a source of a transistor and a node B is in contact with a drain of the transistor, direct current can flow between the node A and the node B depending on the potential of a gate; thus, the structure is expressed as “the node A and the node B are connected to each other”.
On the other hand, in the case where the node A is in contact with the source of the transistor and a node C is in contact with the gate of the transistor, effective direct current cannot flow between the node A and the node C regardless of the potentials of the source, drain, and gate of the transistor; thus, the structure is expressed as “the node A and the node C are not connected to each other”.
In the above description, effective direct current refers to current excluding unintentional current such as leakage current. Note that the value of effective direct current is not defined by its amount (absolute value) and sometimes depends on circuits. That is, in some cases, a low current of 1 pA can be effective current in one circuit, whereas a higher current of 1 μA is not considered as effective current in another circuit.
Needless to say, in one circuit having an input and an output (e.g., an inverter), the input and the output are not necessarily connected to each other. Using the inverter as an example, the input and the output are not connected to each other in the inverter.
When the term “connect” is used in this specification, there is a case in which a physical connection is not clear in an actual circuit and a wiring is only extended. For example, in a circuit composed of insulated-gate field-effect transistors (hereinafter simply referred to as transistors), one wiring serves as gates of a plurality of transistors in some cases. In this case, one wiring that branches into gates may be illustrated in a circuit diagram. In this specification, the expression “a wiring is connected to a gate” may be used even in such a case.
Further, in this specification, in referring to a specific row, column, or position in a matrix, a reference sign is accompanied by a sign denoting coordinates as follows, for example: “precharge transistor PTr_n_m”, “bit line BL_m” and “sub bit line SBL_n_m”. When one element has a function relating to a plurality of rows or columns, the element may be represented by, for example, “amplifier circuit AMP_n/n+1_m”.
On the other hand, when the row, column, or location of a component is not specified, when components are collectively treated, or when the location of a component is obvious, the following expressions may be used, for example: “precharge transistor PTr”, “bit line BL”, and “sub bit line SBL”, or simply “precharge transistor”, “bit line”, and “sub bit line”.
A DRAM whose memory cell includes one transistor and one capacitor can be highly integrated, has no limit on the number of write cycles in principle, and can perform write and read operations at relatively high speed; thus, such a DRAM is used in many kinds of electronic devices. In a DRAM, data is stored by accumulating electric charges in a capacitor of each memory cell and is read by releasing the electric charges to a bit line and amplifying a small potential change of the bit line (see Patent Document 1).
Capacitance (parasitic capacitance) exists between adjacent bit lines and between a bit line and a wiring (a word line and the like) intersecting with each other. The capacitance of the bit line is usually much higher than that of a capacitor. If the capacitance of the bit line is extremely higher than that of the capacitor, a potential change of the bit line when the electric charges accumulated in the capacitor is released to the bit line becomes extremely small, causing an error in amplifying a potential difference between the bit line and a reference potential. Accordingly, the capacitance of the capacitor is desirably 10% or higher of the capacitance of the bit line.
A capacitor in a miniaturized DRAM is formed to have a trench with a depth of as much as several micrometers or a stack with a height of as much as several micrometers, which increases difficulties in processing. Thus, it is necessary to reduce memory capacitance. Accordingly, an increase in the off-state resistance of a transistor of a memory cell has been suggested (see Patent Documents 2 and 3); at the same time, an error due to a decrease in the capacitance of a capacitor, described above, needs to be avoided.
Further, by miniaturization of a DRAM, variations in threshold voltages among transistors are increased. This is due to statistical fluctuation of dopant concentration. In a DRAM, a small potential change due to electric charges released from a capacitor of a memory cell to a bit line is amplified by a sense amplifier; however, when variations in threshold voltages among transistors included in the sense amplifier are increased, an error occurs at the time of amplification. The potential change of the bit line needs to be large so that the error is avoided.
To reduce power consumption and suppress short channel effect, a power supply voltage tends to be reduced; however, a potential change of a bit line at the time of reading is reduced by half if voltage for writing becomes half. On the other hand, there is also a problem in that reading accuracy is decreased with the reduction in power supply voltage since the lower limit of the potential change which can be amplified is almost fixed.
In order to solve these problems, a method is proposed in which bit lines are provided with sub bit lines and a sense amplifier of a flip-flop circuit type is connected to each of the sub bit lines so that data is read by comparison of the capacitance between the sub bit line and the capacitor (see Patent Document 4).
However, the semiconductor memory device disclosed in Patent Document 4 is applicable to folded-bit-line DRAMs, but not applicable to open-bit-line DRAMs, which are more highly integrated. In fact, the semiconductor memory device disclosed in Patent Document 4 has a problem in the degree of integration when being applied to a highly integrated device.
The sense amplifier of a flip-flop circuit type is apt to fail to work properly when the capacitance of the sub bit line is low. In general, the potential of an object with a low capacitance greatly changes because of effects of noise. A conventional DRAM has a capacitance of bit line of several hundred femtofarads; based on the simplest assumption, when the capacitance of sub bit line is several femtofarads, a potential change due to noise is increased a hundredfold.
In the sense amplifier of a flip-flop circuit type, a small potential difference of about 0.1 V is amplified in an early stage of amplification. In this case, when a potential change other than by signals becomes 0.1 V or higher, an error occurs. For example, in a conventional DRAM, the capacitance of a bit line (or a sub bit line) is high, so that a potential change other than by signals can be 1 mV; however, if the capacitance of the bit line (or the sub bit line) (plus the capacitance of one capacitor) is one hundredth or less of that in the conventional DRAM, the potential change other than by signals is 0.1 V or more.
In other words, in the semiconductor memory device disclosed in Patent Document 4, an error at the time of reading is apt to occur when the capacitance of the sub bit line is greatly reduced. In the semiconductor memory device disclosed in Patent Document 1, an extremely high off-state resistance of a transistor is not expected and the capacitance of the sub bit line and the capacitance of one capacitor are expected to be as high as several hundreds of femtofarads or more and as high as several tens of femtofarads or more, respectively; therefore, Patent Document 1 does not disclose any solution to the case where the capacitance of the capacitor is several ten of femtofarads or lower, for example.