1. Field of the Invention
The present invention relates to a sense amplifier overdriving method, and more particularly to an improved sense amplifier overdriving method for entirely restoring a bit line during a read and write operation, by overdriving a sense amplifier at a disable point as well as at an enable point thereof.
2. Description of the Prior Art
In a conventional sense amplifier, a PMOS transistor is provided with a relatively small current driving capacity compared to an NMOS transistor, but the size thereof is approximately two times larger than that of NMOS transistor.
In recent years, an ever increasing DRAM capacity has significantly decreased a chip size, and a PMOS transistor provided in a sense amplifier has accordingly decreased down to a size similar to that of NMOS transistor. As a result, a data driving characteristic of a PMOS transistor has been deteriorated, for thereby generating an undesired high bit line data signal amplified in a sense amplifier, and there is further employed a sense amplifier overdriving method for overdriving a sensing data at an enable point of the sense amplifier.
With reference to FIG. 1 illustrating a schematic circuit diagram for a general semiconductor memory structure, a pair of sense amplifiers 12, 13 are disposed above and below a memory cell 11, respectively. On corresponding sides of the respective sense amplifiers 12, 13 there are disposed sense amplifier drivers 14-17 for driving the sense amplifiers in accordance with an over drive pulse signal ODP.
As shown in FIG. 2, a sense amplifier controller 18 outputs a sense amplifier enable signal SAEN in accordance with an active row address strobe signal RAS, and an over drive pulse generator 19 outputs an over drive pulse signal ODP in accordance with the sense amplifier enable signal SAEN.
As further shown in FIG. 3A, when a word line WL becomes activated in a read operation, a cell charge (data) connected to the word line WL selected from the memory cell 11 comes to be loaded on a corresponding bit line, for thereby forming a potential difference between bit lines BL, /BL.
At this time, when a sense amplifier enable signal SAE is inputted in a state in which the potential difference is less than a minimal potential difference Vmin for reading normal data, the sense amplifier tends to output an invalid data signal.
Therefore, when the sense amplifier controller 18 outputs sense amplifier enable signal SAEN as shown in FIG. 3B in accordance with a row address strobe signal RAS, the over drive pulse generator 19 outputs the over drive pulse signal ODP as shown in FIG. 3C at a point in which the sense amplifier becomes enabled in accordance with the sense amplifier enable signal SAEN.
As a result, in an overdriving interval as shown in FIG. 3D, the sense amplifier drivers 14-17 drive the respective sense amplifiers 12, 13 using an overdriving voltage Vb, for thereby causing the sense amplifier to output a valid data signal.
Also, in a write operation, as shown in FIG. 4A, when a word line WL becomes activated, the sense amplifiers in the sense amplifier controller 18 respectively sense the data signal in accordance with the sense amplifier enable signal SAEN as shown in FIG. 4B, whereby the sensed data signal as shown in FIG. 4C comes to be written in the memory cell 11 through a corresponding bit line.
That is, an overdriving operation of the conventional bit line sense amplifier is carried out only when a sense amplifier becomes enabled in a data read operation.
However, since the conventional overdriving method is applied to read data, the bit line data signal in a data write operation does not reach a full swing level until the word line becomes disabled.
Further, an incomplete data signal that has not reached the full swing level becomes stored in a memory cell capacity, for thereby shortening a refresh interval during a refresh operation.