1. Field of the Invention
The present invention relates to a method for maintaining multi-level cache coherency in a processor with non-inclusive caches and the processor implementing the same.
2. Description of Related Art
To maintain data integrity in conventional multi-processor systems, the caches in each processor associate a memory coherency image state, e.g., MESI state, with each cache line, and the highest level cache snoops, i.e., performs a form of monitoring, commands on a system bus to continually update the memory coherency state for each cache line. Such conventional processors include inclusive caches, which means that the higher level caches store the same cache lines stored in the lower level caches as well as cache lines not stored in the lower level caches.
For instance, in a processor having a level one or L1 cache and an external level two or L2 cache, the L1 cache, by design, is disposed closer to the execution units of the processor and has a lower storage capacity than the L2 cache such that the L1 cache has a lower access time. The L2 cache, however, stores a larger number of cache lines and includes all the cache lines stored in the L1 cache. Because of this inclusivity, only the L2 cache needs to snoop commands on the system bus and generate responses thereto.
Specifically, a cache snoops a command by determining whether the real address associated with the snooped command matches the real address of a cache line stored therein. If a match is found, the cache updates the memory coherency image state for the cache line in a well-known manner, and outputs a snoop response based on the updated memory coherency image state in a well-known manner. If no match is found, the cache outputs a snoop response indicating no match found.
Using inclusive caches, however, requires higher level caches (1) to track the cache lines stored in the lower level caches, and (2) to constantly update the cache lines stored therein based on changes in the cache lines stored by the lower level caches. By using non-inclusive caches, both the tracking and updating functions can be eliminated. Because the caches are non-inclusive, each cache must be considered when snooping a command. Outputting multiple responses to one snooped command from a single processor, however, increases the complexity of maintaining data integrity.