1. Field of the Invention
The present invention relates generally to techniques for defining or describing state machines, which can then be implemented in hardware or software.
2. Background Information
Configurable architectures can consume orders of magnitude less power than conventional processors for certain applications, and are increasingly found in computation-intensive applications that have limited energy supplies (e.g., that are battery-powered). For example, portable cell phones/Web browsers can benefit by incorporating configurable, low-power-consumption architectures that can support such computational racehorses as speech recognition, encryption, channel encoding, biometrics, graphics rendering, handwriting recognition, data compression, and so forth.
Many applications can benefit from massive parallelism. For example, computational chemistry, network switching, computer holography, and other computational “Grand Challenge” problems.
One known approach is to improve algorithms for extracting parallelism from “dusty deck” sequential code. This involves the transformation of conventional application code into a parallel form. Automatic parallelization is primarily limited to regular structures, such as nested loops, because irregular structures are much more difficult to handle. Nested loops are written in a constrained style, typically requiring that array references must affine functions of the loop indices. Such “dusty deck” sequential code can often (but not always) be written to meet the constraints, but it is then no longer “dusty deck” because it uses a new programming model.
Another known approach extends a conventional programming language with a parallel programming model. Prior systems taking this approach include Handel-C, HardwareC, RL, TransmogrifierC, Spyder C++, Data Parallel C, and Picasso. Since these languages are extensions of standard languages, they are only compilable onto their respective target hardware platforms. They cannot be compiled and debugged with a standard compiler on a personal computer.
A third known approach involves using a hardware design language, for example a language such as VHDL and Verilog. Other hardware design languages include C Level, System C, Spec C and Superlog. Hardware design languages are low-level languages and are difficult to integrate with other application code. Hardware languages cannot be compiled using standard compilers onto a personal computer for execution, but must instead be simulated.