1. Field of the Invention
The present invention relates to a semiconductor device requiring high speed performance and low power consumption, and more specifically to a technique which can effectively be applied to a low-lower processor circuit used in portable devices.
2. Description of the Related Art
Recently there have been strong needs for increasingly higher processing performance and lower power consumption in semiconductor, especially in those such as processors.
Higher processing performance of a semiconductor can generally be realized by lowering a threshold voltage. In a well-known method for lowering a threshold value, a voltage is applied to a MOS transistor substrate. In this technique, as disclosed, for instance, in “A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme”, Journal of Solid-State Circuits, IEEE, 1996, Vol. 31, No. 11, p. 1770-1779, a voltage is applied to a substrate (well) of a CMOS (Refer to FIG. 2 in the document) to change the current capability.
When a threshold voltage is lowered to improve the processing performance, however, a leakage current increases and power consumption disadvantageously increases in association with an increase in leakage current.
To simultaneously realize high processing performance and low power consumption, it is required to lower a threshold voltage and also to suppress an increase in leakage current. As a method of improving current capability of a MOS type transistor and at the same time lowering a leakage current, there is a technique for changing a voltage applied to a back gate in response to the operating state of the transistor. For instance, the following configuration is known in the art: A conductive light-shielding layer covered with an insulating layer is formed as a back gate under a thin film transistor forming pixels for a liquid crystal device. Current capability of the thin film transistor is changed by applying a voltage to the back gate. Thus, the current capability is improved when a signal voltage is written in a pixel and also a leakage current is suppressed after writing. Refer to Japanese Patent Laid-open No. 2000-131713.
Also a method is known in which high processing performance and low power consumption are realized in a circuit using a bulk type MOS transistor by controlling a voltage applied to the back gate in the active state and in the standby state. Refer to Japanese Patent Laid-open No. 10-340998.