Full functionality testing is known to be carried out on semiconductor metal bump connect dies while the dies are still embodied in the silicon wafer. However, burn-in followed by the testing of semiconductor wire bond dies is generally not done at the wafer level because of inherent structural difficulties and the nature of making wire connections to external structures. Instead, burn-in and full testing of wire bond dies is generally done only after the dies have been severed from the wafer (chips) and packaged.
Typically, semiconductor wire bond dies defined on a semiconductor wafer undergo initial low-level DC testing wherein individual dies are tested for satisfactory operation. However, there are problems associated with this form of testing. External testing probes directly contacting wire bond pads can damage the wire bond pads by scratching or marking the pads such that subsequent wire bond electrical connection thereto can be difficult. In addition, electrical contact to wire bond pads may be unreliable when probe contacts must be maintained for any considerable length of time.
After DC testing, the wafer is severed between individual dies, inoperable dies are discarded, and operable dies (chips) are collected for packaging into a module. After packaging, burn-in and full functionality testing of each chip circuit is conducted under extended time and temperature conditions directed to assessing circuit reliability. If a particular wire bond chip is found inoperable after packaging, the entire module must often be discarded.
Efforts have been made to eliminate the need for two separate tests and to avoid damaging the surface of the wire bond pad. Such efforts have principally been directed toward constructing a method and structure for conducting wafer level burn-in and full functionality testing of wire bond dies. However, these methods generally require use of additional test structures and levels of interconnection in the kerf region of the wafer. Such structures typically must be removed before dicing the die from the wafer in order to prevent degradation of internal die circuitry performance. Another problem associated with the use of test structures formed in the kerf region is that the number of dies which can be defined on a wafer is limited by the amount of area the test structures require. In addition, the technology required for adding and removing temporary interconnections can contribute significantly to the wafer processing costs.
A need, therefore, continues to exist for an improved structure and method for achieving burn-in and fill functionality testing of a semiconductor wire bond die.
Current semiconductor packaging technology involves mounting chips on chip carriers like ceramic substrates or assembling the chips into plastic packages which provide the necessary pin input/output (I/O) connections. There are two principal systems for connecting chips to substrates. One system is termed the flip-chip bonding system, where metal bumps on the face of the chip are connected to metal pads formed on a chip carrier. This provides both mechanical bonding and electrical connections between the chip and carrier. The other system is a wire bonding system where wires, typically formed of aluminum or gold, are connected by ultrasonic bonding from wire bond pads on the chip to metal pads on a chip carrier or a lead frame (for plastic packages). The use of short wires from the substrate to the chip is desirable to avoid crossing. Thus, as a practical matter, wire bond pads are typically located around the periphery of a chip. In addition, this periphery location outside the region of integrated circuitry is advantageous because pressure applied to the pad during wire bonding won't damage the underlying circuitry. By contrast, metal bumps may be placed anywhere on the chip because wire bonding is not required. Thus, a greater number of electrical connections is possible to a chip using metal bumps than to a chip requiring wire bonding.
In a multi-package market manufacturers' inventory must include chips compatible with both bonding techniques so that either is available depending on whether wire bond or flip-chip/metal bump packaging is demanded. Dual design, manufacturing, and stocking processes increase the cost of chip production which in turn inflates the price of the chips in the market place.
If one chip having both metal bumps and wire bond pads facilitating electrical connection of the chip to either a wire bondable package or a flip-chip package could be produced, the cost of chip production would be significantly reduced because only one process would be necessary. This reduced production cost would then translate into a reduced selling price for semiconductor chips. A need therefore exists for a semiconductor structure and method of fabrication that provides a single chip design having both types of connectors therein for alternative external electrical connections thereto.