The present invention relates to interface circuits and in particular, but not exclusively, to interface circuits for use within simulation techniques.
It is increasingly common to test engineering systems by simulation. For instance, the operation of an electronic system such as an engine management system may be tested under a wide range of conditions by providing signals representing those conditions, and recording the response of the engine management system under those simulated conditions. This allows a very wide range of conditions to be simulated, possibly including situations which are unlikely to arise in practice, or would be dangerous or difficult to create in a real life test. Simulation signals to the system under test can readily be generated by computer or from computer based circuitry. However, the signals readily available in this form (particularly signal voltages, currents and loadings) may not be the same as those which would be experienced in real life by the system under test. In the past, the flexibility of simulation available from a computer controlled system has thus been hampered by the need to design and build an interface circuit specific to the requirements of the simulation system and the system under test. The cost and delay involved in doing so can represent a significant hindrance to the test procedure.
The present invention provides a signal interface circuit comprising circuit portions operable to provide a digital interface, and circuit portions operable to provide an analogue interface, the circuit further comprising control means operable selectively to enable or disable the said circuit portions, whereby to reconfigure the interface.
The circuit portions may be individually selectable to configure the circuit as a digital or analogue device. The circuit may comprise circuit portions operable to provide an input interface and circuit portions operable to provide an output interface.
The circuit preferably comprises a plurality of switch means operable to reconfigure the interface by connecting and disconnecting corresponding circuit portions. The switch means may comprise analogue switches. The state of the switch means is preferably determined by data supplied by the control means. The said data is preferably binary data which sets the state of the switch. The control means may comprise storage means storing data bits which set the state of the switch means. The storage means may comprise a shift register. The control means may comprise a data input port operable to receive control data for storage in the storage means. The data input port is preferably a serial data port.
The circuit may form part of an array of like circuits, each providing a respective interface channel. The storage means of the circuits are preferably connected in series to allow control data to be passed from circuit to circuit. The storage means of the circuits may alternatively be connected in parallel.
The circuit preferably comprises circuit portions operable to provide a digital input interface. The digital input interface preferably includes a threshold detector and may optionally incorporate a buffer circuit, a filter circuit or a variable gain amplifier.
The circuit preferably comprises circuit portions operable to provide an analogue input interface. The analogue input interface preferably comprises a buffer amplifier and may optionally incorporate a variable gain amplifier or a filter circuit.
Preferably the circuit further comprises a load connectable between a terminal on which an input signal is received, and a power rail. Preferably the load is connectable selectively to a high or low power rail, whereby to apply a loading to the input signal. The voltage of the power rail may be selectively configurable to be at one of a plurality of predetermined voltage levels. The power rail is preferably configurable in response to data received from the control means.
Preferably the circuit comprises circuit portions operable to provide a digital output interface to an output terminal. The circuit portions may comprise two switches connected between the output terminal and, respectively, the low and high logic levels, the switches being closable to pull the output terminal to the corresponding logic level, the switch to be closed being selected in accordance with the logic level of the signal received. The circuit portions may further comprise a load connectable between the output terminal and, selectively, the low and high logic levels, to load the output terminal. Operation of the switches may be selectively disabled by the control means, whereby the output is either pulled to a selected logic level or loaded by the said load.
Preferably the circuit comprises circuit portions operable to provide an analogue output interface. The analogue output interface may incorporate an amplifier, such as a buffer amplifier, and may optionally incorporate a variable gain amplifier and/or a filter circuit.
The invention also provides a multi-channel signal interface system comprising a plurality of circuits as aforesaid, each providing an interface between a simulation system and a system under test, the simulation system being operable to provide signals in accordance with a simulation being conducted and to receive signals indicative of the response of the system under test, the signals being provided and received through the interface circuits, and the interface circuits being individually reconfigurable as aforesaid.