(1) Field of the Invention
The present invention relates to a programmable read-only memory device, and more particularly to a bipolar semiconductor programmable read-only memory device having improved bit address decoder circuits, used in electronic equipment such as an electronic computer.
(2) Description of the Prior Art
In general, a programmable read only memory (PROM) device comprises a plurality of memory cells disposed at each cross position of the matrix which is formed by a intersection of a plurality of bit lines and a plurality of word lines. Each of the memory cells is, for example, a shorted-junction type or a fuse-blown type cell, and is connected between one of the word lines and one of the bit lines. The PROM device also comprises address buffers or address inverters which amplify and invert input address signals, decoders which decode the address signals from the address buffers, multiplexers or encoders which encode information from the memory cells, output buffers which amplify output signals from the multiplexers, and program circuits or writing-in circuits which initially write in information to the selected memory cell.
In the prior art PROM device, several kinds of decoders are used including a word address decoder for decoding word address signals in order to select one of the word lines, and bit address decoders for decoding bit address signals in order to select one of the bit lines. The bit address decoder of one kind is connected to the multiplexer and is used for reading-out of information from the selected memory cell, and the bit address decoder of the other kind is connected to the program circuit and is used for writing-in of information to the selected memory cell. These two kinds of bit address decoders are supplied with the same bit address signals. Each of the bit address decoders is composed of a plurality of AND gates, each of which consists of a plurality of diodes. Therefore, the sink current, which flows from the program circuit or multiplexer through the diodes to the bit address inverters, is relatively large. Consequently, it is necessary to use output power transistors having a large driving capability in the output stage of the bit address inverters, and it is also necessary to use different inverters for driving the two kinds of decoders.
In order to gain a large driving capability in the prior art PROM device the size of the output power transistors of the bit address inverters must be large, so that the packing density of the PROM device is reduced and the switching speed of the bit address inverters becomes low. Moreover, the prior art PROM device needs different bit address inverters for driving the two decoders, which also leads to a low packing density of the PROM device.