One aspect of manufacturing an integrated circuit chip or die is mounting the integrated circuit chip to a substrate. In today's technological environment, there is a continuously increasing desire to increase integration of circuits onto a single semiconductor chip. At the same time there is a requirement to increase performance of the chip, whether it is a memory chip, processor chip, telecommunication chip or other integrated circuit chip. As more functions are integrated into a chip, the number of interconnections to other chips and/or electrical devices increases. Often, the goal is to provide the chip with as many input/output (“I/O”) terminals as possible. But the addition of I/O terminals must be provided at a reasonable cost. Flip-chip bonding is one of various surface mounting techniques which have been developed in an effort to provide high density interconnections between the chip and the substrate.
In the flip-chip bonding process, the die containing the integrated circuit is mounted directly to the substrate. Generally, the flip-chip process entails disposing a plurality of solder bumps on the upper-surface of the die, flipping the die and mating these solder bumps with corresponding bonding pads located on the substrate, and then heating the die and the substrate so as to reflow the solder bumps. Once reflowed each bump forms a bonded joint between the die and the substrate, which functions as both an electrical and physical contact. More specifically, the flip-chip bonding process includes three basic steps: (1) pre-cleaning and deoxidation of the surface oxides; (2) solder reflow and/or reflow joining; and (3) post-soldering cleaning.
Known flip-chip bonding processes suffer from various drawbacks. For example, the controlled collapse chip connection (“C4”) flip-chip bonding process utilizes solder bumps comprising a lead-tin alloy, which require an activating flux to reduce the oxides which form on the surface of the bump. The oxides interfere with the formation of an adequate bond due to their relatively high melting points. Accordingly, oxides must be removed if an adequate bond between the die and the substrate, i.e., the solder bumps and bonding pads, is to be obtained. However, the use of flux leaves a residue. The residue must be removed in order to provide an adequate surface to which the underfill is adhered, prevent voiding, prevent corrosion or reduce the potlife of the underfill between the die and the substrate. Such removal or cleaning is a difficult process to accomplish due to the small and ever decreasing size of micro-electronic components. Additionally, there are difficulties in removing the cleaning agents, flux, or residue from the minute areas between components. Moreover, the cleaning agents may damage some components and may pose an environmental disposal problem. Some conventional residues include ionic (e.g., acidic or basic) substances. Some residues are corrosive. Some residues hydrolyze into corrosive components in the presence of moisture, which can lead to corrosion of the parts soldered or to damage to the surrounding components. Accordingly, the cleaning step adds both time and cost to the manufacturing process. Furthermore, the use of the lead-tin alloy is often unsatisfactory because of its tendency to fracture due to thermal stress. The C4 flip-chip bonding process also exhibits surface tension between the solder bump and the bonding pad, which disadvantageously functions to limit the minimum allowable distance between solder bumps.
Another drawback associated with the C4 process is that for proper operation the minimum allowable size of the solder bumps range from 3-5 mils. Notwithstanding the fact that the size of the solder bumps cannot be further reduced (a further reduction would allow more bumps per area), since the entire solder bump becomes liquid during the bonding process, the substantial size of the bump increases the probability of a bump forming a short circuit with one or more adjacent bumps during the bonding process.
Another known flip-chip bonding process can be referred to as the indium-bump process. In this process, the solder bump including indium formed on the die is brought into contact with the bonding pad on the substrate, and then heated so as to cause the solder bump to reflow and form a solder joint. While, this process does not rely on surface tension to assist in the alignment process, the materials utilized for the solder bumps still require the use of flux to remove the oxides prior to the reflow process. As such, the indium-bump process suffers from the same drawbacks as set forth above. Additionally, indium melts at 120 degrees C. and thus uses a large portion of the chip's thermal budget. Accordingly, once the reflow process is completed, further high temperature operations are prohibited. Furthermore, the indium joint, which bonds the die to the substrate, has a relatively low strength. As such, the bond is susceptible to fractures resulting from forces applied during subsequent processing techniques and/or during normal operating conditions.
In addition to the aforementioned problems, some conventional flip-chip bonding processes do not allow for the formation of a hermetic seal surrounding the integrated circuit die simultaneously with the bonding of the die to the substrate. This results from the need to remove the flux from the bonds formed during the flip-chip bonding process. However, while the C4 process allows the generation of a hermetic seal, the seal formed is undesirably large, typically on the order of 250 microns, with reference to today's emphasis on reducing package size.
Various attempts at fluxless soldering have been made but with limited success. For example, U.S. Pat. No. 4,921,157 discloses a fluxless soldering process for semiconductor devices. In this process solder surface oxides are removed using a plasma process. Solder having a surface oxide layer is deposited onto a surface and flourine-containing plasma excitation is performed on the solder. The solder is then reflowed. U.S. Pat. No. 5,407,121 discloses a method of soldering a copper layer without the use of fluxing agents by exposing the copper layer to a fluorine-containing plasma. Solder is then placed onto the surface of the copper layer and reflowed. Reflow can take place at relatively low temperatures, atmospheric pressure and in an inert or oxidizing atmosphere using standard reflow equipment. Still these attempts fall short of providing an adequate chip to substrate packaging technique. Therefore, there remains, in view of these prior attempts, a need in the art for an improved fluxless chip to substrate assembly technique or process.
Flux residues cause further drawbacks when a capillary underfill is used to fill the void between a chip and a substrate. Flux residues interfere with the adhesion of the capillary underfill to the surface of either the substrate or chip that has the flux residue. Moreover, flux residue in the presence of capillary underfill causes remnant voids between the chip and substrate due to the flux residue interfering with the capillary underfill completely filling the void between the chip and substrate. The flux residue must be completely removed to prevent these drawbacks. However, conventional residue cleaning techniques limits the use of capillary underfills to large dimension for the chip-substrate assembly. That is, adequately cleaning residue from the chip and substrate becomes difficult in small dimension chip-substrate assemblies. Moreover, cleaning small dimension assemblies takes a significantly longer time. Thus, cleaning flux residue from small dimension chip-substrate assemblies is not practical from a manufacturing viewpoint.