1. Field of the Invention
This invention relates in general to semiconductor memories such as Dynamic Random Access Memories (DRAMs) and, more specifically, to stress testing of such memories.
2. State of the Art
DRAMs are typically subjected to stress testing during manufacturing. Such testing, also referred to as margin testing, includes various procedures for identifying DRAM cells that are unable to store sufficient charge (referred to as "weak" cells) and for identifying sense amplifiers that lack sufficient sensitivity or gain (referred to as "weak" sense amplifiers).
One conventional method for stress testing DRAMs involves reducing their supply voltage during testing. This reduces the charge that can be written to their memory cells and also reduces the gain of their sense amplifiers. Weak memory cells are then identified by misreads resulting from the reduced charge written to the cells. Also, weak sense amplifiers are identified by misreads resulting from their lacking the necessary sensitivity or gain to correctly read the reduced charge written to the memory cells.
With the increasing use of 2.0 volt DRAM process technology, it is becoming clear that a new device and method for stress testing DRAMs is needed. This is because peripheral circuitry in 2.0 volt DRAMs, which is necessary for external testing equipment to interact with the DRAMs during stress testing, typically begins to shut down at a supply voltage of about 1.5 volts, so that reducing the supply voltage of such DRAMs significantly below 2.0 volts is not a viable means of stress testing the DRAMs.
Therefore, there is a need in the art for a new device and method for stress testing DRAMs and other semiconductor memories. Such a device and method should provide a viable means for testing 2.0 volt DRAMs.