1. Field of the Invention
The present invention relates to a serial access memory for writing and reading video data or similar data serially thereoutof and, more particularly, to a serial access memory capable of reading data serially thereoutof at a speed twice as high as the writing speed.
2. Description of the Prior Art
New media including satellite broadcasting and high definition television (TV) broadcasting and video apparatuses including video recording/playback apparatuses and large-size TV sets have spread during the recent years. In parallel with the spread of such media and apparatuses, digital video technologies have made long strides to implement high quality images. To make the most of the advantages of this kind of media and apparatuses, various kinds of image display systems have been proposed for displaying a video signal on, for example, a display via a memory. A serial access memory is one of conventional memories optimal for TV images and allows a video signal to be serially written in on a scanning line basis while allowing it to be serially read out and fed at high speed in the horizontal direction of a TV screen. The means for enhancing the image quality by use of such a serial access memory may be implemented as a speed doubling circuit, as disclosed in Japanese Patent Laid-Open Publication No. 165280/1989 by way of example.
A conventional serial access memory, or memory chip, for the above application includes a memory cell for storing video data. An input port receives video data serially from the outside of the memory chip and writes them in the memory cell. A write control circuit controls the input port in synchronism with a write clock also fed from the outside of the chip. An output port reads the video data out of the memory cell and delivers them serially to the outside of the chip. A read control circuit controls the output port in synchronism with a read clock further fed from the outside of the chip. Specifically, the write clock and read clock are generated by a clock generating circuit outside the chip and applied to the write control circuit and the read control circuit, respectively. The speed doubling circuit gives the read clock a frequency double the frequency of the write clock, so that data may be read out at a speed twice as high as the writing speed.
When data are serially applied to the input port from the outside of the chip and the write clock is applied to the write control circuit also from the outside, the write control circuit controls the input port in response to the write clock. Then, the input port reads the data serially in synchronism with the write clock, converts them to, for example, parallel data, and then writes the parallel data in the memory cell. On receiving the read clock from the outside, the read control circuit feeds a control signal to the output port. As a result, the output port reads data out of the memory cell, for example, in parallel in response to the write control signal. The data read out of the memory cell at a speed synchronous to the read clock, e.g., double the writing speed are serially delivered to the outside of the memory chip.
As stated above, it has been customary to double the data read-out speed on the basis of the write clock and read clock both of which are fed from the outside of the memory chip. The problem with this conventional scheme is that the read clock has to be provided with a twice higher frequency than the read clock and, in addition, has to be synchronous to the write clock. Generating such a high-speed read clock outside the memory chip and driving the serial access memory thereby is not practicable without resorting to an advanced drive capability and complicated circuitry. It follows that a display using the conventional serial access memory complicates the circuitry around the memory chip, resulting in a bulky and expensive apparatus.