In recent years, there has been demanded a high flatness level for wafers, for example, thin disk-shaped wafers, such as a semiconductor silicon single crystal wafer (hereinafter also simply referred to as a silicon wafer), a glass substrate including a quartz wafer or others, a ceramic substrate including alumina, aluminum nitride or the like. A manufacturing process for the wafers, for example, a silicon wafer, comprises: a slicing step of slicing a cylindrical semiconductor ingot with a wire saw, a circular inner diameter blade or the like, to obtain thin disk-shaped wafers; a chamfering step of chamfering a peripheral edge portion of the wafer obtained through the slicing step to prevent chipping of the periphery thereof; a lapping step of lapping both surfaces of the chamfered wafer to adjust a thickness and flatness level thereof; an etching step of immersing the lapped wafer into an etching solution to etch all the surfaces thereof for removing processing damage remaining therein; and a polishing step of mirror polishing a single surface or both surfaces of the etched wafer for improving a surface roughness level and a flatness level thereof.
Furthermore, the chamfered portion of the above chamfered wafer is usually subjected to edge polishing prior to polishing the wafer for preventing particle generation upon contact thereof by handling or the like in later steps.
The edge polishing has been performed using a known edge polisher 10 as shown in FIGS. 12(a) and 12(b) (see JP A 99-188590). The edge polisher 10 has a rotary drum 12 and is of a structure that the drum 12 rotates about a rotary shaft 14 at a high speed. A multi- or single layer polishing cloth (a polishing pad) 16A (FIG. 12(a)) or 16B (FIG. 12(b)) is fixed on all the outer surface of the rotary drum 12.
18 designates a wafer rotating device, which is installed correspondingly to the rotary drum 12 and can freely change a tilt angle relative to the rotary drum 12. The wafer rotating device 18 includes a base 20, and a rotary shaft 22 rotatably installed on the top surface of the base 20. A wafer W is held on the top end of the rotary shaft 22 and subjected to edge polishing. 24 designates a nozzle, which supplies polishing slurry 26 to a contact portion of the polishing cloth 16 with the wafer W. Edge polishing is performed by polishing the chamfered portion of the wafer W with rotating both the rotary drum 12 and the wafer W, and pressing the wafer W to the polishing cloth 16 on the rotary drum 12 at a predetermined tilt angle, for example, in the range of from 40 degrees to 55 degrees relative to a polishing surface of the rotary drum.
In the above published patent application, as the polishing cloths (polishing pads) 16A and 16B, there was disclosed as prior art not only a polishing cloth (polishing pad) 16B (FIG. 12(b)) of a single layer structure, but also a polishing cloth (polishing pad) 16A of a two layer structure, that is, a multi-layer structure (FIG. 12(a)) constituted of a sheet 16a made of at least one of synthetic resin foam, nonwoven fabric, resin-treated nonwoven fabric, synthetic leather, or composites thereof; and an elastic sheet 16b such as a synthetic rubber sheet or a sponge sheet.
In the above edge polishing method, in order to increase a pressed-down amount into the polishing cloth (polishing pad) 16A or 16B, there are disclosed techniques using soft polishing cloths (for example, Suba 400 having a thickness of 1.27 mm and an Asker C hardness of 61 used in Comparative Example of the above published patent application; Suba 400 having a thickness of 1.27 mm+synthetic rubber having a thickness of 1 mm and a rubber hardness of 50 used in Example 1 of the published patent application; and Suba 400 having a thickness of 1.27 mm+sponge sheet used in Example 2 of the published patent application).
In the case where edge polishing is performed using a polishing cloth of the above noted structure, it has been found according to experiments by the present inventor that as shown in FIG. 13 a polished portion 32 is produced extending 500 μm or more into a wafer main surface from a wafer chamfered portion 30. In this specification, hereinafter, such excess polishing is referred to as over-polish and a width of the polished portion 32 is referred to as an over-polish width. The width of the wafer chamfered portion 30 is generally on the order of 500 μm. Therefore, the sum of the wafer chamfered portion 30 (about 500 μm) and the over-polish width 32 (about 500 μm) is about 1000 μm, that is, about 1 mm.
An edge exclusion area (E. E.) for flatness measurement on a wafer surface is currently 3 mm from the periphery of the wafer; therefore, if an over-polish width is about 500 μm, an influence thereof on wafer flatness is small. However, there have recently increased demands for the smallest possible edge exclusion area (E. E.) for wafer flatness measurement. This is for improving a yield of device chips obtainable from one wafer.
Generally, there has been a tendency that while a relatively high flatness level is achieved in a central portion of a wafer, a wafer thickness decreases from an inner position of about 5 mm from the wafer peripheral edge to the chamfered portion, which is referred to as a sag in the outer peripheral portion of the wafer. While causes of the wafer peripheral sag may be considered to be a difference between polishing pressures when polishing a wafer main surface, an influence of a polishing agent and so on, especially the sag generated at the boundary portion between the chamfered portion and the main surface is considered to be due to an influence of edge polishing.
For example, in case of an edge exclusion area (E. E.) for wafer flatness measurement of 1 mm, an over-polish width of about 500 μm would influence a wafer flatness level and generate a sag in the outer peripheral portion of the wafer.