A high-speed processor system that has a CPU and a low-speed large-capacity DRAM with cache memories has been known as a system for high-speed processing of large-sized data. Such a known high-speed processor system has, as shown in FIG. 1, a CPU 1 incorporating a primary cache, and a plurality of parallel DRAMs 2 connected to the CPU 1 through a common bus line, each DRAM 2 being equipped with a secondary cache 3 which serves to enable the DRAM 2 to process at a speed approximating the processing speed of the CPU 1.
In the operation of the circuitry shown in FIG. 1, contents of one of the DRAMs 2 are read in accordance with an instruction given by the CPU 1, and writing of information into the DRAM 2 also is executed in accordance with an instruction from the CPU 1. If the reading instruction hits, i.e., if the desired content to be read from the DRAM 2 is held in the cache 3, the CPU 10 can perform high-speed data processing by accessing the secondary cache 3. However, in case of a miss-hit, i.e., when the desired content does not exist in the cache 3, the cache 3 is required to read the target content from the DRAM 2.
The described basic configuration of the high-speed processor system having a processor, DRAMs, and caches is nowadays the dominant one, because it advantageously permits the use of an ordinary programming style for the control.
This high-speed processor system employing a hierarchical arrangement of caches, however, cannot perform parallel processing because it employs only one CPU 1. In addition, ordinary programming style is not inherently intended for parallel processing and cannot easily be used for running a parallel processing system unless it is modified, thus causing an impediment in practical use.