1. The Field of the Invention
The present invention relates generally to a method for making an improved isolation trench for a semiconductor memory device. More particularly, the present invention relates to a method for fabricating a low leakage trench for a Dynamic Random Access Memory (DRAM) cell wherein trench sidewall leakage currents from the bitline contact to the storage node and from the storage node to the substrate are minimized by an isolation oxide film that is disposed within the trench.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In a capacitor used in VLSI technology, it is desirable to minimize storage cell leakage in order to reduce refresh frequency requirements and to improve storage reliability. It is also desirable to increase storage cell capacity without increasing lateral geometries and without subjecting vertical storage cells to physical destruction during fabrication.
Both stack and trench DRAM cells suffer from sidewall leakage and from node-to-substrate leakage from the bitline contact. Stack DRAM cells suffer from two additional disadvantages that can result in device destruction and shorting. The first additional disadvantage is that the raised topography of the stack subjects it to the risk of being damaged in subsequent processing such as chemical-mechanical planarization (CMP), that exposes the stack. Subsequent processing, such as rapid thermal processing (RTP), can cause unwanted diffusion of dopants. The second additional disadvantage is that the configuration of the stacked capacitor requires a high aspect ratio of contacts used in connecting the stack capacitor, such as the bit line contact corridor. As one example, metal reflow into a high aspect-ratio contact requires a high amount of heat and pressure. There is also the chance of shorting out the bitline contact into the cell plate in the bitline contact corridor because both the cell plate and the bitline contact corridor are in the same horizonal plane and must intersect without making contact.
Processing of stack DRAMs requires a large amount of thermal energy. The DRAM structure is limited in its ability to withstand the thermal energy without diffusing doped elements to an extent that is destructive. This thermal energy limit is referred to as the thermal budget and must be taken into account in DRAM fabrication. Utilizing more than the entire thermal budget translates into dopant diffusion that may exceed structure design and cause device underperformance or failure. Dealing with the thermal budget adds another dimension to processing that correspondingly decreases the processing degrees of freedom.
Given the forgoing, there is a need in the art for a robust DRAM device that has a low profile above a semiconductor substrate and a highcharge storage capacity. There is also a need in the art for a DRAM device with decreased lateral geometries, and minimized charge leakage. There is also a need in the art for a method of fabricating a robust DRAM that fabricates the DRAM with only a fraction of the thermal budget presently required for similar capacity DRAMs and that allows for optional further processing such as metallization with the unused portion of the thermal budget.