In a large electronic system having multiple sub-systems, such as in a computer system, there are generally a plurality of power supplies providing different voltage levels. The sub-systems, such as integrated circuits (ICs) and chips, often require such different power voltages. To protect the sub-systems from being damaged by the different power voltages, a mixed-voltage-tolerant input/output (I/O) buffer circuit is generally provided between the sub-systems.
Generally, in a system having a first circuit on a first chip and a second circuit on a second chip with an I/O buffer circuit coupled therebetween, the buffer circuit includes at least an input stage and an output stage. For purposes of the present description, it is assumed that a power supply of the first circuit has a higher voltage level than that of the second circuit, and the I/O buffer circuit operates at the same power supply level as that of the second circuit. For example, the first circuit may operate at 3.3V or 5V while the second circuit and the I/O buffer circuit both operate at 1.8V or 2.5V. It is also assumed that the input stage (“input circuit”) of the buffer circuit receives one or more signals from the first circuit and outputs one or more signals to the second circuit, and that the output stage (“output circuit”) of the buffer circuit receives one or more signals from the second circuit and outputs one or more signals to the first circuit.
FIG. 1 is a schematic of a conventional input circuit 100 of a mixed-voltage-tolerant I/O buffer circuit in the second chip. Input circuit 100 is coupled to a first circuit (not shown) through a node 102 and to a second circuit (not shown) through a node 104. The first circuit is powered at 3.3V, the second circuit is powered at 1.8V, and input circuit 100 is also powered at 1.8V. Input circuit 100 receives at least one signal from the first circuit at node 102 and outputs at least one signal to the second circuit at node 104. Input circuit 100 includes an NMOS transistor 106 and an inverter 108 serially coupled between nodes 102 and 104. NMOS transistor 106 has a gate (not numbered) coupled to a 1.8V power supply VDD, a substrate (not numbered) coupled to ground, a source (not numbered) coupled to node 102, and a drain (not numbered) coupled to inverter 108. Inverter 108 includes a PMOS transistor 110 and an NMOS transistor 112, each having a gate (not numbered), a substrate (not numbered), a source (not numbered), and a drain (not numbered). The gates of PMOS transistor 110 and NMOS transistor 112 are coupled to each other and further coupled to the drain of NMOS transistor 106. The source of PMOS transistor 110 is coupled to VDD. The source of NMOS transistor 112 is grounded. The drains of PMOS transistor 110 and NMOS transistor 112 are coupled to each other and further coupled to node 104.
An input signal at node 102 may have two possible logic values: 0, representing a voltage level of approximately 0V; and 1, representing a voltage level of approximately 3.3V. When the voltage of the signal at node 102 is 0V, NMOS transistor 106 is turned on and the input to inverter 108 is 0V. Inverter 108 then outputs a logic high signal to node 104, wherein the logic high signal has a voltage level of approximately 1.8V. If the voltage of the signal at node 102 is about 3.3V, the drain voltage of NMOS transistor 106 follows the gate voltage of NMOS transistor 106. Therefore, NMOS transistor 106 sends a logic high signal to the input terminal of inverter 108. Inverter 108 outputs a logic low, or 0V, signal to node 104.
A problem associated with input circuit 100 as illustrated in FIG. 1 is that, when the input signal at node 102 has a higher voltage level than VDD, PMOS transistor 110 is not completely turned off, because the voltage at the drain of NMOS transistor 106 is approximately VDD−Vth, rather than VDD, wherein Vth is the threshold voltage of NMOS transistor 106. Therefore, there exists a leakage current through inverter 108 from VDD to ground.