During the fabrication of semiconductor memory devices, each semiconductor memory device is typically tested to ensure reliability and proper functionality. Latent defects in a given semiconductor memory device may not be detected under “normal” operation conditions. Normal operating conditions may include write, read and/or erase operations executed with voltages set within a normal operating range.
In order to screen a higher number of semiconductor memory devices, the memory test may further include a “stress test”. A conventional stress test typically includes testing a given semiconductor memory device under more extreme conditions than the “normal” conditions. For example, a stress test can include a higher voltage applied to specific elements (e.g., word lines) of the semiconductor memory device, a higher or colder ambient or operating temperature, etc. As will be appreciated by one of ordinary skill in the art, stress testing further reduces the number of semiconductor memory devices that pass the testing phase, and potentially enter the market, which may improve product reliability.
Typically, latent defects within semiconductor memory devices, such as static random access memory (SRAM), are more likely to occur within memory bit cells of the semiconductor memory device. For example, one or more memory bit cells may fail due to deterioration of a gate oxidation film, a defective leakage current of an impurity diffusion region or weak via/contacts in a bit cell pull-down path, etc.
FIG. 1 illustrates a bit cell 105 and a pre-charge circuit 110 of a conventional semiconductor circuit 100. Referring to FIG. 1, the bit cell 105 includes transistors pd1, pd2, pu1, pu2, pg1, and pg2. The functionality of the bit cell 105 is well-known in the art, and will not be described further for the sake of brevity. For example, for a further description of a bit cell similar to the bit cell 105 of FIG. 1, see U.S. Pat. No. 5,424,988, entitled “Stress test for memory arrays in integrated circuits”, filed on Sep. 30, 1992 by McClure et al., and hereby incorporated by reference in its entirety.
The pre-charge circuit 110 includes three transistors, and is configured to apply a bit-line precharge voltage to each of bit lines BIT and BITB. The pre-charge circuit 110 is typically activated prior to an access of the bit cell 105 (e.g., a read access, a write access, an erase operation, etc.) during normal operation of the semiconductor circuit 100.
Conventionally, upon initiation of a stress test, one or more word lines are selected and remain activated for the duration of the stress test. Also during the stress test, one bit line BIT in the memory array is set to a higher voltage, or stress voltage. The stress voltage is then applied through the bit line BIT to gates and reverse biased pn junctions between the diffusion and substrate for the selected word lines for the duration of the test. Therefore, referring to FIG. 1, gate pg1, pg2, pd2, pu2, and junction n1 are stressed. However, the pre-charge circuit 110 is not typically activated during a stress test, and the applied stress voltage does not affect, for example, vias connected to the bit line pull down path. Thus, the bit line BITB is set to a floating voltage or low voltage level during the stress test. After a given amount of time, the stress voltage “switches” from the bit line BIT to the bit line BITB. After the switch, the bit line BIT carries a low voltage, and the bit line BITB carries the stress voltage. Thus, the bit lines BIT and BITB do not typically carry the stress voltage at the same time during the stress test.
Accordingly, only the transistor and junctions are tested, such that conventional stress test does not necessarily test or stress vias connected to the bit line (e.g., which may be relatively weak and defect-prone), and defects present therein may not be detected during the testing phase of the semiconductor circuit 100.