1. Field of the Invention
The present invention relates generally to integrated circuit manufacture; and more particularly to an apparatus and a method of manufacture for performing a nitride strip process step.
2. Description of the Related Art
The structure and the various components, or features, of a metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate dielectric and a patterned gate conductor are formed. The gate conductors' impurities that are forwarded into the substrate are self-aligned on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source and drain regions. The gate conductor typically is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs N-type junctions placed into a P-type substrate. Conversely, a typical p-channel MOS transistor comprises P-type junctions placed into an N-type substrate. The substrate comprises an entire monolithic silicon wafer.
A pocket or well of oppositely doped substrate often exists within part of the substrate. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junctions formed in the remaining areas of the substrate. Accordingly, wells are often employed when both N-type and P-type transistors (i.e., Complementary MOS, "CMOS") are needed.
A common trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source and drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features that have critical dimensions that are as small as 0.20 microns.
As feature sizes decrease, the sizes of the resulting transistors and the interconnections between transistors also decrease. Having smaller transistors allows more transistors to be placed on a single monolithic substrate. Accordingly, relatively large circuits can be incorporated on a single and relatively small die area.
Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features, in combination, allow for higher speed integrated circuits to be constructed that have greater processing capabilities and that produce less heat.
The benefits of high-density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another.
For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges and also excessive sub threshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive.
Excessive electric fields produce so called hot carriers and the injection of these carriers into the gate oxide that resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the resulting transistor. In view of these considerations, certain scaling limits are being reached.
Metal Oxide Semiconductor (MOS) transistors are typically formed in an isolated active device region of a semiconductor substrate. These active device regions are separated by field oxide regions formed of silicon dioxide and are known as isolation regions. Interconnects are used to electrically couple the MOS transistors to other devices on the semiconductor substrate.
An interconnect that overlies a field oxide between device active areas may inappropriately function as a gate electrode of a parasitic MOS transistor formed between diffused regions of two adjacent MOS devices. The parasitic transistors thus cause leakage current to flow between the adjacent devices resulting in increased power consumption and, sometimes, in device failure.
To reduce or eliminate the inadvertent operation of parasitic transistors, it is a common technique to increase the threshold turn-on voltage of the parasitic transistors to keep them from operating. Usually, increasing the threshold turn on voltage prevents the operation of the parasitic device and, therefore, eliminates the undesirable current flow.
One approach for increasing the threshold turn-on current is to thicken the field oxide. Another approach is to increase the doping beneath the field oxide. Typically, ion implantation is used to create what is known as channel-stop implants. The combination of thicker oxide and channel-stop implants usually provide adequate isolation. As may be seen, therefore, a certain thickness of the field oxide must be maintained to prevent leakage currents caused by parasitic devices.
After a field oxidation process step in which the isolation (field oxide) regions are created, a masking layer (often a nitride layer) must be stripped or removed. As a result of processing techniques, however, even the nitride strip itself often includes an outer layer of silicon dioxide and/or oxynitride. Some common processing steps chemically alter the outer layer of the nitride to convert it to silicon dioxide or oxinitride. In other common processing techniques, a layer of oxide is formed on top of the nitride during processing steps to form the field oxides. The problem can be even more challenging when the nitride to be removed is a patterned nitride layer having some oxide on its outer surface.
Accordingly, a typical wet etch nitride strip process step includes removing the silicon dioxide and/or oxynitride plus the nitride itself. Because silicon dioxide and nitride are selective, either two process steps must be used (one for the oxide and one for the nitride) or a process step must be performed that is adapted to remove both the oxide layer and the nitride layer. A combined process step to remove the nitride and the oxide is often preferred for many reasons including efficiency.
One problem, however, of removing the oxide and the nitride in a combined step is that the field oxide may also be excessively removed thereby lowering the threshold turn-on voltages of the parasitic devices. On the other hand, if too little oxide is removed, the chemicals that are selective to the nitride may not remove enough of the nitride layer thereby resulting in a potentially ruined wafer.
Accordingly, having a wet etch chemical composition that is sufficiently strong to remove the outer oxide layer is very important. This outer oxide layer must also be removed, however, in a time that is quick enough to allow the nitride to be stripped completely within the specified period for the strip process. On the other hand, it cannot be so strong that excessive amounts of the field oxide are removed.
Field oxide losses from wet etch chemical processes are often a serious concern and a difficult problem to solve because the byproducts of the nitride strip affect the oxide etch rate. More specifically, the oxide etch rate in a hot phosphoric bath decreases as the silicon content of the phosphoric acid solution increases. The reason for this is that the nitride etch reaction produces dissolved silicon dioxide that, in turn, reduces the effectiveness of the wet etch chemicals that are selective to the oxide.
The increased amounts of silicon in the phosphoric solution are beneficial in that they reduce the oxide etch rate thereby advantageously resulting in thicker field oxides. Too much silicon, however, can be too much of a good thing. Excessive amounts of silicon can result in the silicon precipitating, ie., chemically coming out of the solution to form on the wafer and other undesirable places.
In other situations, for instance, in those situations where the nitride is completely covered by an oxide layer, the wet etch chemicals that are selective to the nitride and do not begin to remove the nitride until the outer layer of oxide is removed. Accordingly, a slow oxide etch reduces how much time the chemicals selective to the nitride have to do the nitride strip and can result in an ineffective nitride strip process step.
To solve these problems, the solution in wet etch chemical baths are periodically drained and replaced with fresh phosphoric acid. Typically, a chemical bath is drained once per day to insure that dissolved silicon levels stay below a specified threshold. For example, a chemical bath is often drained after a specified number of wafers have been processed in a nitride strip process step.
One problem with draining the chemical bath, however, is that it takes nearly eight hours to prepare it to continue doing nitride strip process steps.
Preparing the bath includes draining it, refilling it and bringing it up to temperature. Additionally, the bath must be seasoned to keep the phosphoric from being too strong (and from etching too much of the field oxide) Finally, the chemical bath must be recertified before being used to strip nitride.
Another problem that results from common bath drain procedures is that the oxide etch rate changes significantly between changes of solution. For example, a fresh bath may have an oxide etch rate that is approximately equal to 3.6 Angstroms per minute. After one thousand wafers, however, a typical etch rate is about 0.6 Angstroms per minute.
The differences in etch rates therefore results in the batches of wafers having field oxide layers having different thickness. As explained before, these different thicknesses result in the parasitic device threshold turn-on voltages being different from wafer lot to wafer lot.
A method and an apparatus that allow the oxide etch rates to be kept at a more constant level to allow greater device consistency, therefore, is greatly needed.
There also is a need, generally, to increase bath throughput capacity and to decrease the amount of wet etch chemicals consumed during the nitride strip process steps.