1. Field of the Invention
The present invention relates to nonvolatile memory devices and, more particularly, to flash memory devices,
2. Description of the Related Art
Electrically erasable and programmable flash memory can preserve data even when electric power is not provided. In particular, because such flash memory has a string structure in which a plurality of flash memory cells are connected in series, NAND-type flash memory may facilitate integration and can be provided at low cost. For these reasons, NAND-type flash memory has been used as data memory in diverse portable products.
A flash electrically erasable programmable read-only memory (EEPROM) cell transistor may be programmed or erased using the Fowler-Nordheim (FN) tunneling mechanism. An operation of erasing the cell transistor may be performed by applying a ground voltage of 0 V to a control gate of the cell transistor and applying a voltage (e.g., 20 V) higher than a power supply voltage to a semiconductor substrate (or bulk). According to such a bias condition, a strong electric field may be formed between a floating gate and a bulk due to a great voltage difference therebetween. As a result, electrons in the floating gate are discharged to the bulk due to an FN tunneling effect. Here, the threshold voltage of the erased cell transistor may shift to a negative value, for example, −3 V. This state is defined as data “1” and an EEPROM cell in this state is referred to as an “ON-cell.”
An operation of programming the cell transistor is performed by applying a voltage (e.g., 18 V) higher than the power supply voltage to the control gate and applying the ground voltage to a drain and the bulk. Under such a bias condition, electrons are injected into the floating gate of the cell transistor due to the FN tunneling effect. Here, the threshold voltage of the programmed cell transistor may shift to a positive value, for example, +1 V. This state is defined as data “0” and an EEPROM cell in this state is referred to as an “OFF-cell.”
FIG. 1 is a block diagram of a conventional NAND-type flash memory device. Referring to FIG. 1, the NAND-type flash memory device includes a memory cell array 10, a row selection circuit (or a row decoder circuit) 12, a page buffer circuit (or a data sensing and latching circuit) 14, and a column decoder circuit 16.
The memory cell array 10 includes a plurality of memory blocks BLK0 through BLKn (where “n” is a positive integer), each of which includes a plurality of strings. As illustrated in FIG. 1, each string includes a string selection transistor (SST) connected to a corresponding bit line, e.g., BL0, a ground selection transistor (GST) connected to a common source line (CSL), and memory cells MC15 through MC0 connected between the SST and the GST. The SST, the memory cells MC15 through MC0, and the GST are respectively connected to a string selection line (SSL), word lines WL15 through WL0, and a ground selection line (GSL). Block selection transistors BS17 through BS0 respectively corresponding to the lines, i.e., the SSL, the word lines WL15 through WL0, and the GSL are controlled in common by a block selection signal BS.
The row selection circuit 12 selects one word line (or one page) among the word lines WL0 through WL15 through the block selection transistors BS0 through BS17. The page buffer circuit 14 temporarily stores data to be stored in memory cells of the selected page or senses data stored in the memory cells of the selected page. The page buffer circuit 14 comprises a plurality of page buffers (or data sensing and latch blocks) respectively corresponding to columns, i.e., bit lines related with the selected page. Data bits sensed from the memory cells of the selected page are output through the column decoder circuit 16 in predetermined units (for example, in byte units (×8)).
FIG. 2 illustrates part of a conventional column decoder circuit. The column decoder circuit illustrated in FIG. 2 corresponds to a single data line. The same circuit structure as that illustrated in FIG. 2 may be provided to correspond to each of other data lines. In FIG. 2, a reference character “ND_LAT” denotes a latch node of the page buffer circuit 14 shown in FIG. 1. First selection signals YA0 through YA15 are sequentially activated, and simultaneously, second selection signals YB0 through YB15 are sequentially activated. For example, while each of the second selection signals YB0 through YB15 is activated, the first selection signals YA0 through YA15 are sequentially activated. As can be seen from such a structure and control method, for example, a single data bit DL0 is selected from among 256 latched data bits ND_LAT0 through ND_LAT254.
A page size may increase to meet users' demands for increase in data input/output speed. However, when the page size increases, the following problems may occur: As is known, a program/erase operation includes a verify operation for determining whether a memory cell is normally programmed or erased. During the verify operation, the memory cells, i.e., bit lines of the selected page are sequentially scanned. This scan operation is referred to as “verification scan,”“column scan,” or “Y-scan”.
The erase operation generally takes a relatively long time (e.g., 2 ms). Accordingly, the erase operation is not usually restricted by time taken for the Y-scan (hereinafter, referred to as “Y-scan time”). However, because the page program operation generally takes a relatively short time (e,g., 240 μs or less), the Y-scan time may not be ignored in the page program operation. Moreover, because a page program includes an algorithm for preventing a memory cell from being excessively programmed, the Y-scan time is not ignorable.
FIG. 3 illustrates conventional programming operations. In stage 301, a host sends data to a static random access memory (SRAM) to perform a program operation. When a command indicating sequential data input is applied to a flash memory having an array of memory cells to be programmed, the SRAM transmits the data to a page buffer of the flash memory and address data and sequential data are sequentially input to an address buffer circuit ad a page buffer circuit of a memory device in stage 302. Thereafter, when a command indicating start of a programming process is applied to the memory device, a high-voltage generation circuit operates to generate high voltage to be applied to a gate in stage 303. As described above, bit lines are set to a power supply voltage (or a program-inhibit voltage) or a ground voltage (or a program voltage) according to data loaded into the page buffer circuit in stage 304, which is referred to as a bit line setup operation. After the bit lines are set to the power supply voltage or the ground voltage, the high voltage generated by the high-voltage generation circuit is applied to a selected word line and the program operation is executed in stage 305. After a predetermined period of time under the above-described bias condition, a verify operation for reading data from selected cell transistors is performed. The verify operation includes program recovery (stage 306), verify read (stage 307), and Y-scan (stage 308). The program recovery is a process of converting a voltage of a bit line into a predetermined value for data read and includes discharging and precharging the bit line. The verify read is a process of reading and latching data of the bit line and may include development for reading the data of the bit line, bit line sensing, data latching, and bit line recovery. The Y-scan is a process of sequentially scanning and outputting data read from memory cells, i.e., bit lines of a selected page.
When at least one cell transistor among the selected cell transistors is not programmed sufficiently, the above-described programming process (including the bit line setup, the program execution, and the verify read) is repeated according to a predetermined program loop in stages 309 and 310. Here, a high voltage used in a subsequent program loop, e.g., a second program loop is set to be higher (for example, 0.4 V higher) than that used in a current program loop, e.g., a first program loop.
In the conventional programming operations, the Y-scan is executed after the verify read is completed. In this case, as described above, because the program operation is performed in a relatively short time, the Y-scan time is not ignorable. Moreover, because the verify read is repeated when the programming process is repeated, the Y-scan time may not be ignored.