A resistive memory array may be utilized to perform analog computations that exploit the fundamental relationship between row voltage and column current in a resistive mesh to realize an analog multiply-accumulate unit. The memory array is typically organized as a grid of cells interconnected by horizontal and vertical wires, referred to as word lines and bit lines. With emerging resistive memories, this may be further developed to build a powerful multiply-accumulate unit within the memory. For instance, the fundamental relationship between a row access voltage and the resulting bit line current may act as an analog multiplier of row voltage and cell conductance. Instead of accessing a single row as performed for loading and storing data, multiple rows may be activated concurrently.