1. Field of the Invention
The present disclosure relates to a Liquid Crystal Display (LCD) device, and more particularly, to an LCD device and a driving method thereof, which can prevent abnormal image data from being outputted when an abnormal signal is inputted thereto.
2. Discussion of the Related Art
LCD devices are devices that adjust the light transmittance of liquid crystal cells according to image data signals. The LCD devices are thin and light, and have low power consumption. Therefore, the LCD devices are being widely applied to various devices such as computer monitors, notebook computers, portable terminals, and wall-mounted televisions.
Generally, such LCD devices include a panel that display an image, a gate driving Integrated Chip (IC), a data driving IC, and a timing controller.
FIG. 1 is a timing diagram showing input signals and output signals of a related art timing controller, and shows the outputs of various control signals based on a dot clock DCLK and a data enable signal DE that are inputted to the timing controller.
Generally, the timing controller configuring the LCD device is connected to an external system through an interface using Low Voltage Differential Signaling (LVDS), and is connected to the data driving ICs of a data driver by using a point-to-point scheme.
The timing controller generates a gate control signal GCS and a data control signal DCS with a timing signal (for example, Vsync, Hsync, and DCLK) that is transferred from the external system, and respectively transfers the gate control signal GCS and the data control signal DCS to the gate driving IC and the data driving IC.
The timing controller aligns video data transferred from the external system to supply image data to the data driving IC.
The timing controller uses a Phase Locked Loop (PLL) for adjusting clocks and a frequency (phase) that are used in the external system or the data driving IC.
That is, an LVDS reception unit of the timing controller includes a PLL, and thus, the PLL locks the constant frequency (phase) of a signal received from the external system to the LVDS reception unit and the constant frequency (phase) of a signal outputted from the LVDS reception unit. Also, an Embedded Clock Point-Point Interface (EPI) transfer unit inside the timing controller includes a PLL, and thus, the PLL locks the constant frequencies (phases) of clocks that are used inside the timing controller. Furthermore, each of the data driving ICs uses a PLL for implementing the point-to-point scheme between the timing controller and each data driving IC.
However, due to various causes, a transition can occur in the lock of the PLL. When such an abnormal transition occurs, the timing controller transfers abnormal driver control signals (particularly, an abnormal gate control signal GCS) to the gate driving IC, and thus, the panel can output an abnormal image or cannot normally operate.
Such abnormal operations can occur in the following cases.
First, since the PLL of the LVDS reception unit of the timing controller is unlocked, an abnormal operation can occur.
For example, as shown in FIG. 1A, when the frame frequency of the dot clock DCLK is arbitrarily changed from 60 Hz to 40 Hz for switching a mode, the lock of the PLL of the LVDS reception unit is released, and thus, the frequency of a data enable signal “Output DE” outputted from the LVDS reception unit is not matched with that of a data enable signal “Input DE” inputted from the LVDS reception unit, causing a glitch. In this case, the timing controller that transfers the gate control signal to the gate driving IC outputs an abnormal gate start pulse GSP and an abnormal gate shift clock GSC, causing the abnormal driving of the panel.
Moreover, as shown in FIG. 1B, even when the timing signal (for example, DCLK or the like) transferred from the external system is abnormally inputted to the timing controller, the lock of the PLL of the LVDS reception unit is released. In this case, the timing controller that transfers the gate control signal to the gate driving IC using a Gate-In-Panel (GIP) type outputs an abnormal gate start signal VST and an abnormal gate clock GCLK, causing the abnormal driving of the panel.
Second, in switching between a signal mode and a no signal mode, the lock of the PLL in the EPI transfer unit of the timing controller is released, causing an abnormal operation.
In this case, as described above, the timing controller generates abnormal gate control signals (for example, GSP, GSC, and GOE, or VST and GCLK) to output the abnormal gate control signals to the gate driving IC, causing the abnormal output of the panel.
Third, an abnormal operation is caused even by the sudden change of an external environment such as static electricity, in which case the timing controller also generates the abnormal gate control signals (for example, GSP, GSC, and GOE, or VST and GCLK) to output the abnormal gate control signals to the gate driving IC, causing the abnormal output of the panel.
As described above, since the frequency of the timing signal DCLK transferred from the external system is changed and the timing signal DCLK is abnormally inputted to the LVDS reception unit, the related art LCD devices can perform an abnormal operation such as: that lock between the LVDS reception unit and the external system is released; that the lock of the EPI transfer unit is released by the switching of a mode or the like; or that lock between the data driving IC and the timing controller is released by an external environment or the like.
In this case, the timing controller can generate the abnormal gate control signals (for example, GSP, GSC, and GOE, or VST and GCLK) to output the abnormal gate control signals to the gate driving IC, in which case the abnormal display of the panel can be caused by the abnormal gate control signals. In the worst case, the panel itself can be damaged.
Moreover, when the above-described abnormal operations occur, the timing controller can generate an abnormal data control signal (for example, SOE, SSP, and/or SSC) to output the abnormal data control signal to the data driving IC, and generate an abnormal power control signal (for example, PWM and/or PLK) to output the abnormal power control signal to a power IC, causing the abnormal driving of an LCD device.