1. Field of the Invention
This invention is related to the field of integrated circuits, and more particularly, to driving a clock grid of an integrated circuit.
2. Description of the Related Art
Integrated circuit (IC) technology typically includes complex logic core designs that rely on one or more clocks for operational synchronization. Some of the desirable qualities for a clock signal may be an extremely small period, very short rise and/or fall times, low jitter, available everywhere on the chip with very low skew, and the ability to drive heavy loads at any point on the chip, while consuming the least possible amount of power.
One common approach to the design of clock distribution circuitry is a “tree” of buffered runs in which the number of buffers from the origin of the clock signal to any particular “leaf” node is kept constant in order to minimize skew. FIG. 1 illustrates the hierarchical organization of such a conventional buffer tree. The primary buffer fans out to a second tier of buffers, while each of the second tier buffers fans out to a third tier of buffers, etc. until the required number of drivers is achieved in the final tier. Therefore, the number of tiers of buffers between the primary driver and any leaf of the tree is constant. Additionally, the length of conductor runs between buffering levels is maintained consistent by “snaking” shorter runs to achieve equivalent characteristics to worst-case paths.
In order to assure uniform drive capability and minimize skew throughout the grid, a symmetric organization of the driving buffer tree is commonly applied. FIG. 2 illustrates one commonly applied routing pattern known as an “H-tree”. The outputs from the buffers of a given tier are applied to the centers of the cross bars of the “H's” of the corresponding tier. Using an H-tree pattern, both the number of buffers and the total conductor run length between the primary buffer and any leaf node may be held constant. The outputs of the final tier or leaf buffers may be directly connected to the closest nodes or intersection points on the clock grid. The clock skew at the input of a consuming device may be proportional to the distance from the nearest driven point on the grid.
Another common architectural technique is to have a clock tree include a final tier of buffers that drive nodes of a grid or mesh. The output of a clock source, such as an oscillator or phase locked loop (PLL) that generates a reference clock signal, may be input to a clock tree composed of tiers of buffers. The buffers included in the final tier of the clock tree may be referred to as leaf buffers since they are the endpoints of the buffer tree. FIG. 3 illustrates a conventional clock buffer tree. The clock buffer tree of FIG. 3 routes clock signals into a mesh made up of conductive traces from two metal layers, M1 and M2. The leaf buffers drive clock signals to the M2 traces, which connect to the orthogonal M1 traces at the grid nodes. Any logic that needs the clock signal may tap into one of the M1 traces of the grid at the closest point to its location on the chip. As with the other two approaches discussed above, differences in the amount of skew may be exhibited between two different points on the grid, depending upon each point's respective distance from the nearest leaf buffer.
FIG. 4 illustrates elements of a portion of a conventional clock grid as they may appear within an IC. The horizontal elements with no hatching labeled “clock tree” may represent a tree of buffers (FIGS. 1 and 2) that carry the clock signal to the inputs of leaf buffers (represented as non-shaded triangles in FIG. 4) in the final tier of a clock tree. As illustrated in FIG. 4, the outputs of the leaf buffers may be directly connected to the clock grid. Horizontal clock grid lines M1, shaded with vertical hatching, may be connected to the vertical elements at each intersection point. The actual connection between the clock grid lines and the vertical elements may be represented by the solid squares shown at each intersection point. Note that there may be clock grid lines that are hidden by the horizontal clock tree elements and that the pattern of the clock grid elements as depicted may be extended to cover a much larger section, or in some cases the entire IC.
The output of a leaf buffer may be directly connected to one of the traces forming the clock grid represented by an M2 line. Since clock consumers may only be attached to the M1 layer, the clock signal must travel along the M2 feeder element from the output of the leaf buffer to the intersecting connection with the clock grid line M1 to which the consumer is attached, and then along the M1 element to the attach point. Delay along this path may cause the edge of the clock signal at the consumer to lag that of the output of the leaf and this delay may differ between two consumers at different points on the grid. For example, the delay from the output of a leaf buffer to the input of a clock consumer at attach point 1 may be slight whereas that from output of a leaf buffer to the input of a clock consumer at attach point 2 may be several times as great. The skew thus introduced between clock signals feeding logic at various attach points may limit the operating frequency of the IC.