(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit processing and more particularly to copper interconnect processing.
(2) Description of Prior Art
As transistor devices continue to shrink in modern technology so do the feature sizes of metal interconnects. Aspect ratios of gaps, such as vias and trenches, which are filled with metal to form interconnections, tend to increase with design rule shrinking. In damascene and dual damascene processes copper, due to properties such as its low resistivity and low susceptibility to electromigration, is often the metal of choice for filling such gaps. An ECP, electro copper plating, process traditionally accomplishes filling of the gaps with copper. Good gap filling and adhesion properties are also achieved in electroless copper plating, but there is a problem in that electroless copper plating is a high-cost and low-throughput process. However, there is also a problem with ECP since it has been found, in both 0.11 and 0.13 micrometer technologies, that pinhole-like voids exist in the copper for ECP filled gaps. These pinhole-like voids are found for aspect ratios greater than about 5:1. FIG. 1 shows such a void, 32, in an ECP filled gap, 4, where the gap width is about 0.16 micrometers and the void diameter is about 0.04 micrometers. Such voids will not only result in yield loss, but also give rise to reliability concerns during electromigration or stressmigration testing.
As is well known, interconnects are formed in multiple levels. Each level containing a dielectric layer, denoted an IMD (intermetal dielectric) layer, a metal layer made up of metal filled trenches and metal vias connecting metal layers. Generally copper interconnect levels are formed by first forming gaps, such as vias and trenches, in a dielectric layer and lining the gaps with a metal barrier layer, which serves to inhibit copper migration. A copper seed layer is then formed over the metal barrier layer to promote proper adhesion. After filling the gap with copper a planarization procedure, which is usually CMP, is performed. Forming a blanket insulator capping layer completes the interconnect level.
Copper interconnects with improved electromigration resistance and low resistivity is disclosed in Woo et al., U.S. Pat. No. 6,525,425. The copper is formed in two stages. First pure copper is deposited and then the gap is filled with doped copper. A method for forming copper dual damascene is shown by Lou in U.S. Pat. No. 6,492,270, which utilizes both electroless copper plating and physical vapor deposition of copper. U.S. Pat. No. 6,472,023 to Wu et al. discloses a method for forming a copper seed layer in copper interconnects using displacement and thus eliminating the need to use CVD or PVD for forming a copper seed layer. U.S. Pat. No. 6,380,083 to Gross teaches a method for forming copper interconnects that contains a dual copper layer composed of a PVD copper layer and an ECP copper layer. U.S. Pat. No. 6,344,129, to Rodbell et al. teach a method for plating copper on electronic substrates and devices in an electroplating solution using either a one step or two step deposition process.