1. Field of the Invention
The present invention relates to a testing apparatus and a testing method for a device. More particularly, the present invention relates to a testing apparatus and a testing method compressing and memorizing a test program to be used for a test of a device.
2. Description of Related Art
A testing apparatus tests a device under test (DUT) based on a test program. The test program includes commands to be executed by the testing apparatus every command cycle and test patterns to be output to each terminal of the device under test or expectation patterns to be compared with output patterns output from each terminal of the device under test.
Conventionally, there has been used a testing apparatus that compresses the test program by means of repeated commands in order to reduce data volume of the test program. FIG. 8 shows a compression format of the conventional test program. According to the test program of FIG. 8, a NOP command (a no-operation command) is executed in a first command cycle, and each of test patterns {0, 1, 1, 0} is output to each of {terminal 1, terminal 2, terminal 3, terminal 4}.
Similarly, the NOP command is executed in a second command cycle, and each of test patterns {1, 0, 1, 0} is output to each of {terminal 1, terminal 2, terminal 3, terminal 4}. Then, an IDXI command that is a repeated command is executed in a third command cycle, and test patterns {1, 1, 1, 0} continue to be output to {terminal 1, terminal 2, terminal 3, terminal 4} during 100 cycles. In this manner, when all terminals continue to use the same patterns during a plurality of command cycles, the conventional testing apparatus reduces the size of the test program by means of repeated commands.
Now, since a related patent document is not recognized, the description is omitted.
Meanwhile, with speedup of an electronic device of recent years, transmission speed of signals input to and output from the electronic device has exponentially become high. Such an electronic device inputs data of a plurality of bits and outputs data of a plurality of bits during one cycle.
On the other hand, an electronic device of recent years is designed to previously carry a test function of the electronic device in order to improve the efficiency of a test. Such a design is referred to as DFT (Design for Testability), and is indispensable to a high level of electronic device of recent years. For example, a certain electronic device has a circuit that sets an initial state for a test in a register in the electronic device.
The test for such an electronic device has a test mode to perform an initial setup and a normal mode to input a pattern sequence to the electronic device after the initial setup. In other words, the testing apparatus firstly holds a pattern sequence for the initial setup in a register in the electronic device, and then inputs the pattern sequence for a test to an input terminal of the electronic device. In such a test, while the normal mode requires inputting a number of patterns during one command cycle, the test mode requires inputting one pattern during one command cycle.
Therefore, a utilization ratio of a memory is bad when a plurality of bits used in the normal mode is stored in association with each of all commands. On the other hand, when an operating frequency of the testing apparatus is changed according to an operation mode in order to change the length of bit stream output per unit time, the design of the testing apparatus becomes complicated. The object of the present invention is to reduce capacity of a memory storing a pattern sequence without complicating the design of the testing apparatus.