High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to reduce chip size while reducing power consumption and increasing access speed for mobile devices. As part of that effort to reduce chip size, it may be desirable to reduce a number of signal lines between dynamic random access memory (DRAM) and a controller. Along these lines, commands to the DRAM may be provided from a reduced number of address pins by dividing information of a single clock cycle into a plurality of clock cycles alternating signals in synchronization with rising and falling edges of a clock signal. For example, it has been proposed that a number of pins for command/address (CA) bus in a high-speed synchronous dynamic random access memory (SDRAM) like Low Power Double Data Rate 4 (LPDDR4) be reduced to 6-bit per die while increasing two channels per die. Thus, a total of twelve CA pins may be used for communicated with the memory. In a particular example, LPDDR4 receives a command with two or four clock cycles at six CA pins of CA0-CA5 in a CA bus. Each command in the LPDDR4 devices typically uses four clock cycles in order to transfer command, address and bank information.
JEDEC Standard No. 209-4 shows command structure in a command truth table (Table 63) and describes that a four-cycle command may be generated from two consecutive two-cycle sub commands. In this case, a two-cycle command irrelevant to the first sub command may be received. As a result, more command codes are needed to distinguish sub commands, including the first sub command and the second sub commands, thus the number of CA pins for command decoding would be increased. Moreover, four clock cycles are used for one command, and consequently, less number of commands can be conveyed during a predetermined number of clock cycles.