The present invention relates, generally, to providing a compliant interface for a semiconductor chip, and more particularly relates to a method and apparatus for providing a compliant interface to accommodate for differences in the thermal coefficient of expansion mismatch between a semiconductor chip and a support structure, such as a printed wiring board.
In attempting to use the area on printed wiring boards more efficiently, semiconductor chip manufacturers have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays (xe2x80x9cPGAsxe2x80x9d) and the perimeter leaded quad flat packs (xe2x80x9cQFPsxe2x80x9d), to smaller conventions, such as ball grid arrays (xe2x80x9cBGAsxe2x80x9d). Using BGA technology, semiconductor chips are typically interconnected to their supporting substrates using solder connections, such as with xe2x80x9cflip-chipxe2x80x9d technology. However, when solder alone is used to interconnect the chip contacts to the substrate, the columns of solder are generally designed to be short to maintain the solder""s structural integrity. This results in minimal elastic solder connection properties which further results in increased susceptibility to solder cracking due to the mechanical stress of the differential thermal coefficient of expansion (xe2x80x9cTCExe2x80x9d) of the chip relative to the supporting substrate thereby reducing the reliability of the solder connection. In other words, when the chip heats up during use, both the chip and the substrate expand; and when the heat is removed, both the chip and the substrate contract. The problem that arises is that the chip and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. As the features of semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem. This further increases the need for a highly compliant interconnection scheme for the chips.
The solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multichip module. Multichip modules continue to grow in popularity; however, as more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multichip modules, each package requires additional interconnections thereby increasing overall rigidity of the connection between the module and its supporting substrate.
An interconnection solution put forth in U.S. Pat. No. 4,642,889, entitled xe2x80x9cCompliant Interconnection and Method Thereforxe2x80x9d issued to Grabbe seeks to alleviate the aforementioned solder cracking problem by embedding wires within each solder column to reinforce the solder thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth includes providing a combination of solder and high lead solder, as found in U.S. Pat. No. 5,316,788, entitled xe2x80x9cApplying Solder to High Density Substratesxe2x80x9d issued to Dibble et al.
Still other prior art solutions make use of a underfill material disposed between the chip and the supporting substrate in an attempt to reduce the stress caused by TCE mismatch. Without the underfill material, this stress is typically concentrated at the weakest part of the solder balls. The underfill material allows this stress to be more uniformly spread out over the entire surface of the solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,194,930, 5,203,076 and 5,249,101. All of these prior art solutions are aimed at reducing the shear stress endured by the interconnections caused by thermal cycling. However, each of these solutions also encounters significant problems such as insufficient compliance and process cost.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively, but specifically differently, with the thermal cycling problem. For example, U.S. Pat. No. 5,148,266 discloses improvements in semiconductor chip assemblies and methods of making the same. As set forth in the ""266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals are provided on the second surface of the interposer, and the interposer is provided with apertures extending through it. Flexible leads extend through these apertures between contacts on the chip and the terminals on the second surface of the interposer. The terminals can be bonded to a substrate. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the ""266 patent provide excellent resistance to differential expansion of the chip relative to the substrate caused by thermal cycling. The interposer disclosed in the ""266 patent may also include a compliant layer disposed between the terminals and the chip.
Copending, commonly assigned U.S. patent application Ser. No. 08/123,882, filed Sep. 20, 1993, the disclosure of which is hereby incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is an elastomer which is cured into a resilient layer after its introduction into the gap. In another preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
The present invention provides a method and apparatus for providing a compliant interface for semiconductor chips to accommodate for the typically large thermal expansion mismatch between a chip and its support structure.
More specifically, one aspect of the present invention provides a method of fabricating a compliant interface for a semiconductor chip, typically comprised of a compliant encapsulation layer having a controlled thickness. A first support structure, such as a flexible, substantially inextensible dielectric film, having a surface is provided. A porous resilient layer, such as a layer of a plurality of compliant pads, is attached to the first surface of the first support structure, any two adjacent compliant pads defining a channel therebetween. Attaching the compliant pads to the first support structure may be accomplished a number of different ways. In one embodiment, a stencil mask having a plurality of holes extending therethrough is placed on top of the first surface of the support structure. The holes in the mask are then filled with a curable liquid elastomer. Desirably, liquid elastomer has a thick enough consistency so that the mask may then be removed before curing the elastomer. After the mask has been removed, the elastomer is at least partially cured, such as by heating or exposing to ultra-violet light. The filling step may be accomplished by screening the liquid elastomer across an exposed surface of the mask such that the elastomer is deposited into the holes of the mask. Other methods are also suitable, such as dispensing the elastomer into each of the holes individually. Thus, there is provided an assembly which includes an array of compliant pads further having channels between substantially all of the adjacent pads. At this stage of the process, the vertical height of the pads need not be extremely uniform.
In a further stage, the assembly including the array of pads is used with a second support structure. In one embodiment, the second support structure is a semiconductor chip having a plurality of contacts on a first surface. The first surface of the chip is abutted against the array of compliant pads and the contacts are electrically connected to a corresponding plurality of terminals on a second side of the support structure. Typically, the first surface of the chip is pressed against the pads to compress them, thus ensuring the chip is uniformly supported across its first surface and further ensuring the planarity of the first support structure, or flexible dielectric film, with respect to the first surface of the chip. Where the dielectric film has terminals thereon, the terminals desirably are held coplanar with one another during this step. For example, the dielectric film and the chip may be held between a pair of opposed platens, so that the terminals bear on one platen and are brought into a substantially coplanar condition. A compliant filler, such as a curable liquid elastomer, is then injected into the channels between the chip and the support structure and around the compliant pads while the chip and support structure are held in place. The elastomer may then be cured to form a substantially uniform, planar, compliant layer between the chip and the support structure.
In a further embodiment, the second support structure includes a plurality of chips. The array of compliant pads is large enough to overly several chips simultaneously. This method may be used to form a compliant interface for multiple chips which then may either be cut into individual chips or may be used as a multi chip module. The above method may also be used to form a compliant interface for a semiconductor wafer before the individual chips are separated. After the compliant interface is formed, the wafer may be cut into individual chips or into multi-chip modules.
A further embodiment provides for an array of compliant pads held in place using a holding element. The pads are then fixably placed to either a surface of the chip or the supporting substrate. The holding element is then removed and the pads are compressed between the chip and the supporting substrate. Liquid elastomer is injected into the channels between the adjacent pads, as described in the above embodiments.
The pads or the pad/injected elastomer combination provide a compliant, planar interface which effectively accommodates for the thermal coefficient of expansion mismatch between the chip and a supporting substrate thereby alleviating much of the stress on the connections therebetween. Further, the combination provides an effective encapsulation barrier against moisture and contaminants.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of Preferred Embodiments, taken together with the attached Figures.