1. Field of the Invention
This invention relates to Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistor (FET) memory devices Static Random Access Memory (SRAM) memory integrated circuit semiconductor cells and more particularly to the load transistors of SRAM devices.
2. Description of Related Art
Integrated circuit (IC) memory devices are made up of a plurality of memory cells. In general, one basic memory cell design is duplicated numerous times to form those cells. The basic cell design may be modified slightly from cell to cell, for example one cell may be a reversed image or complement of an adjacent cell, but the entire memory device can be described according to the basic cell design.
In the case of Static Random Access Memory (SRAM) devices, the basic cell is usually in one of two forms, either a six transistor (6T) cell or four transistor/two resistor (4T/2R) cell. Many conventional SRAMs using a 6T configuration have six transistors formed in a bulk semiconductor substrate such as single crystal silicon. That type of SRAM is usually embodied in a Complementary Metal Oxide Semiconductor (CMOS) technology, with four transistors being N-channel devices while the remaining two transistors are P-channel devices. A 6T SRAM device operates at relatively low power levels and the bulk transistors have good electrical characteristics, including high mobility and low threshold voltages. Also 6T SRAMs are relatively stable, having high immunity to cell errors, such as those caused by incident alpha particles. However, 6T SRAM cells formed of transistors in a bulk substrate require a large area because the transistors are formed next to one another in the substrate and are essentially in the same plane; which use of six bulk transistors imposes an undesirable lower limit on the cell size. Achieving the smallest cell size with the simplest process reduces the manufacturing costs, increases memory capacity, and increases the device performance without increasing the overall device size.
U.S. Pat. No. 5,059,554 of Spinner et al. teaches a "Method for Forming Polycrystalline Silicon Contacts" between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polysilicon is deposited and patterned.
U.S. Pat. No. 5,151,387 of Brady et al. for "Polycrystalline Silicon Contact Structure" teaches a contact structure that provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.
U.S. Pat. No. 5,084,417 of Joshi et al. for "Method for Selective Deposition of Refractory Metals on Silicon Substrates and Device Formed Thereby" describes utilizing high temperature and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures.
FIGS. 1A-1C illustrate a prior art process for manufacturing an SRAM device 10. Referring to FIG. 1A, a device 10 is formed on a dielectric layer SIO composed of a silicon oxide dielectric material. Layer SIO supports an N+ doped conductive polysilicon bottom gate electrode BG1 and an N+ doped conductive polysilicon interconnection line I1 both formed from an N+ doped (third) polysilicon layer with a thickness from about 100 .ANG. to about 1,000 .ANG..
The bottom gate electrode BG1, interconnect line I1 and dielectric layer SIO have been doped covered with gate oxide layer GX with a thickness from about 50 .ANG. to about 500 .ANG..
A first photoresist mask PR1 has been formed over device 10. A window W1 is formed through mask PR1 extending down to the surface of gate oxide layer GX above the interconnection line I1.
FIG. 1B shows the device 10 of FIG. 1A after the gate oxide has been etched away below the window W1 down to the top surface of interconnection line I1, followed by formation of a lightly doped fourth polysilicon (channel) layer PS4, with a thickness from about 100 .ANG. to about 1,000 .ANG., which reaches down through the window opened in gate oxide layer GX by the etching step to form electrical contact with interconnection line I1. The layer PS4 is doped to the low level appropriate for use in the channel of a Thin Film Transistor (TFT).
FIG. 1C shows the device 10 of FIG. 1B after a second photoresist mask PR2 has been formed covering fourth polysilicon (channel) layer PS4 above bottom gate electrode BG1 and extending to the right thereof. There is a window W2L to the left and a window W2R to the right of mask PR2.
Mask PR2 has been used during the ion implantation of P+ dopant IM1 which is implanted into the exposed portions of fourth polysilicon (channel) layer PS4 to form a source region S1 to the left of mask PR2 and a drain region D1 to the right of mask PR2 in the layer PS4. In addition, to the right of mask PR2, the layer PS4 has been converted into layer PS4' which is an interconnection line. At the intersection of P+ doped line PS4' with the N+ doped interconnection line I1, a PN junction J1 has been formed between the P doped line PS4' and N doped line I1.
The implant IM1 comprises a dose of boron P type dopant from about 1 E 14 ions/cm.sup.2 to about 1 E 16 ions/cm.sup.2 to provide P+ doped polysilicon in the source region S1, line 18, drain region D1, line 17 and interconnection layer PS4' and drain region D1 is connected to a PN junction formed between P+ doped polysilicon line 17 and the N+ doped line I1 below line 17.
FIG. 3 shows a prior art circuit diagram of a six transistor (6T) Static Random Access Memory (SRAM) cell 10, incorporating the structure of FIG. 1C which includes a first storage node N1 and a second storage node N2, a pair of load transistors TL1 and TL2 having their sources S1 and S2 (composed of P-doped polysilicon) connected through P+ doped polysilicon lines 18 and 28, respectively, to voltage source Vdd. The drain regions D1 and D2 (composed of P-doped polysilicon) of load transistors TL1 and TL2 are connected through P+ doped polysilicon lines 17 and 27 to nodes N1 and N2 where they are connected to the N+ doped interconnection lines I1 and I2, respectively, so a PN junction exists as can be seen by reference of FIG. 1C. The drain of the first latch transistor T5 is connected to the first storage node N1; and the drain of the second latch transistor T6 is connected to the second storage node N2.
The gate electrodes for the first latch transistor T5 and the first load transistor TL1 are connected through conductor line 16 and interconnection line I2 to the second storage node N2. The gate electrodes for the second latch transistor T6 and the second load transistor TL2 are connected through conductor line 26 and interconnection line I1 to the first storage node N1. The gate electrodes for the pass transistors T3 and T4 are connected through lines 14 and 24, respectively, to the word line WL.
The source regions of load transistors TL1 and TL2 connect electrically through P+ doped polysilicon lines 18 and 28 to a power supply terminal (at voltage Vdd) and to each other.
The source regions of the latch transistors T5 and T6 are electrically connected through lines 19 and 29 to ground (reference potential) and to each other.
The source/drain circuit of first pass transistor T3 is connected between the first bit line 12 (BL1) and node N1 and the source/drain circuit of second pass transistor T4 is connected between the node N2 and second bit line 22 (BL2).
The pass transistors T3, T4 and latch transistors T5, T6 are NMOS (N-channel) devices and the load transistors TL1, TL2 are PMOS (P-channel) devices.
There is a contact SC1 connected to the Node N1 and through the interconnection line I1 (buried under gate oxide layer GX) and the conductor line 26 to the gate electrodes of the second latch transistor T6 and the first load transistor TL2.
There is also a contact SC2 connected to the Node N2 and through the interconnection line I2 (buried under gate oxide layer GX) and the conductor line 16 to the gate electrodes of the first latch transistor T5 and the first load transistor TL1.
The P+ doped polysilicon lines 18 and 28 from the source Vdd to the sources S1 and S2 and the P+ doped lines 17 and 27 from drains D1 and D2 to nodes N1 and N2 respectively have substantial amounts of series electrical resistance.
Our studies of the circuit of FIG. 3 show that there are excessively high series electrical resistances of lines 17, 27, 18 and 28 and PN junction diode which exist at contacts SC1/SC2 causing a negligible voltage drop. These are substantial disadvantages of the circuit of FIG. 3.
With the continued scaling of device structures to the deep submicron level, the operating voltages are becoming lower. Thus, the voltage drop across the contacts will no longer play a negligible role in the device performance. Besides the I.sub.ON /I.sub.OFF ratio and the Subthreshold Swing and the Series Resistance of S/D region or interconnection are also major concerns in TFT SRAM devices.
However, the conventional process of forming inter-polysilicon contacts between the polysilicon 3 and polysilicon 4 layers in an SRAM device has two major disadvantages. First, it will degrade the polysilicon/SiO.sub.2 interface quality and thus cause a larger OFF state current (I.sub.OFF) and a Subthreshold Swing due to the covering of photoresist direct on the gate oxide. Second, it will also degrade the ON state current (IDSAT) of the TFT device because of the voltage drop across the contact result from the existence of PN junction diode.