Buck converters are a type of switching-type DC-to-DC voltage regulator that generate a direct current (DC) load (output) voltage that is substantially lower than an available direct current (DC) “input” voltage. In contrast, boost converters are a second type of switching-type DC-to-DC voltage regulator that generate a “stepped up” output voltage (i.e., the output voltage is higher than the applied DC input voltage). In terms of power supply efficiency switching-type regulators can operate at about 90% or better.
FIG. 4 shows an exemplary conventional asynchronous DC/DC buck converter 10 with diode including an N-type CMOS (NMOS) high-side switch (transistor) 11, an associated control signal source 12, an inductor L, and a diode D. A capacitor C and a resistor R represent an applied load. NMOS switch 11 is connected between a high input voltage supply VIN and a high-side switch output node LX, and has a gate terminal connected to receive a square-wave gate voltage VG from control signal source 12. Signal source 12 utilizes an error amplifier ERR-AMP, a pulse width modulator circuit PWM, and an oscillating oscillator OSC to generate square-wave gate voltage VG whose duty cycle causes NMOS switch 11 to intermittently connect high input voltage VIN to high-side switch output node LX such that the regulated load voltage VREG (e.g., 4V) is generated across capacitor C and resistor R.
A practical problem associated with the implementation of DC/DC buck converter 10 involves power loss in NMOS switch 11 when the switch is on. In particular, high current flow through NMOS switch 11, combined with the resistance of NMOS switch 11 in the on state, generates a significant power loss equal to I2R. Power loss on NMOS switch 11 is created during start-up process (switching power loss), and also after start-up is completed when NMOS switch 11 is “fully on” due to its rds-on resistance combined with high load DC current. High power loss occurs at the beginning of every operating period because NMOS switch 11 is subjected to a maximum drain-to-source voltage when input voltage VIN is applied to its drain terminal, but output voltage VLX at its source terminal is still at or near 0V. In order to charge high-side switch output node LX to VIN through NMOS switch 11 and reduce power loss, gate voltage VG should be equal to or greater than input voltage VIN plus the threshold voltage VT of NMOS switch 11 (i.e., VIN+VT). In order to reduce power loss, when NMOS switch 11 is fully on, gate voltage VG needs to be increased even more to decrease rds-on resistance of NMOS switch 11. Power loss when NMOS switch 11 is fully on is typically dominant power loss factor and is dependant on buck converter duty cycle. DC/DC buck converter 10 does not include a source of ideal start-up gate voltage VIN+VT or higher voltage to reduce rds-on resistance.
FIG. 5 shows a bootstrapped buck converter 20 that addresses the problems presented above utilizing a prior art bootstrap circuit solution that is taught, for example, in U.S. Pat. No. 7,046,040. Similar to buck converter 10, bootstrapped buck converter 20 includes an NMOS switch 21 and a square-wave signal source 22 (depicted for brevity as an operational amplifier) that are constructed essentially as described above in order to generate a regulated voltage VREG across output terminals “+” and “−”. Bootstrapped buck converter 20 differs from buck converter 10 in that it includes a bootstrap circuit 25 made up of a bootstrap diode DBOOT and a bootstrap capacitor CBOOT that are connected in series between a system voltage supply VDD (e.g., 5V) and a high-side switch output node LX, and serves to generate a bootstrap voltage VBOOT at a bootstrap node BOOT that is used to boost gate voltage VG when NMOS switch 21 is on. At the beginning of the operating period (i.e., when high-side switch output voltage VLX is still close to 0V), bootstrap diode DBOOT passes system voltage VDD to bootstrap capacitor CBOOT, whereby bootstrap voltage VBOOT is raised to system voltage VDD minus a voltage drop across bootstrap diode DBOOT (i.e., VBOOT=VDD−VDIODE). Because square-wave signal source 22 utilizes bootstrap voltage VBOOT to generate square-wave gate signal VG, and because bootstrap voltage VBOOT is greater than the ideal start-up gate voltage (i.e., VIN+VT), NMOS switch 21 fully turns on at the beginning of operation and its rds-on resistance is also smaller after start-up process is completed, thereby avoiding the power loss associated with buck converter 10 (discussed above).
A problem with conventional bootstrapped buck converter 20 is that bootstrap diode DBOOT must be both able to supply the necessary bias voltage without injecting significant current to the CMOS substrate while in forward bias, and be able to withstand high reverse voltages without breakdown when node LX is at VIN. That is, high-side switch output node LX toggles between 0V to VIN during operation, and boot voltage VBOOT follows these changes by way of boot capacitor CBOOT. Specifically, boot node voltage VBOOT is charged to VDD−VDIODE (i.e., voltage VDD minus voltage VDIODE) via boot diode DBOOT when output voltage VLX=0V, and when gate voltage VG charges to boot voltage VBOOT, high-side switch output node LX is charged via switch 21, causing boot voltage VBOOT to rise to VIN+VDD−VDIODE. Eventually, output voltage VLX will reach VIN level with gate voltage VG of switch 21 equal to VIN+VDD−VDIODE. Although CMOS diodes having a sufficiently high breakdown voltage may be implemented using an established CMOS process flow, this approach would inject significant current to the CMOS substrate while in forward bias, or would require additional process steps which makes fabrication more expensive.
External bootstrap diodes are sometimes used to implement bootstrap diode DBOOT of buck converter 20 to avoid issues related to the use of high voltage integrated semiconductor (e.g., CMOS) internal (on-chip) diodes, but the use of external diodes presents problems as well. The use of high voltage internal diodes is problematic because such diodes take up a large amount of chip area. Moreover, although CMOS diodes having a sufficiently high breakdown voltage may be implemented using an established CMOS process flow, this approach would inject significant current to the CMOS substrate while in forward bias, or would require additional process steps that make fabrication more expensive. A problem with the practice of using external diodes to produce the desired bootstrap characteristics is that external diodes are relatively expensive due to both the component cost and the assembly costs associated with mounting the external diodes. Further, the external diode takes up a valuable device pin, which prevents the use of that pin for other input/output signals.
What is needed is a CMOS buck converter including a bootstrap circuit that avoids the high reverse voltages produced by conventional bootstrapping approaches, thereby facilitating the use of low voltage integrated semiconductor CMOS diodes. What is also needed is a bootstrap circuit architecture that employs low cost diodes that supply the necessary bias voltage without injecting significant currents to the CMOS substrate while in forward bias.