1. Field of the Invention
The present invention generally relates to a method for fabricating a pixel structure, and more particularly, to a method for fabricating a passivation layer by a laser ablation process.
2. Description of Related Art
Among displays, as interfaces between man and information, a flat display plays a major role in development tendency of the display technology today. A flat display is mainly categorized into organic electroluminescence display (OELD), plasma display, and thin film transistor liquid crystal display (TFT LCD), wherein the TFT LCD is counted as the most popular one. In general, a TFT LCD is mainly composed of a thin film transistor array substrate, a color filter substrate and a liquid crystal layer. A TFT array substrate includes a plurality of scan lines, a plurality of data lines and a plurality of pixel structures arranged in array, and each pixel structure is respectively electrically connected to a corresponding scan line and a corresponding data line.
FIGS. 1A-1G are flowchart diagrams for fabricating a conventional pixel structure. First referring to FIG. 1A, a substrate 10 is provided and then a gate 20 is formed on the substrate 10 by using a first photolithography and etching process. Next referring to FIG. 1B, a gate dielectric layer 30 is formed on the substrate 10 to cover the gate 20. Next, referring to FIG. 1C, a channel layer 40 is formed over the gate 20 and on the gate dielectric layer 30 by using a second photolithography and etching process, wherein the channel layer 40 is usually made of amorphous silicon (a-Si). After that referring to FIG. 1D, a source 50 and a drain 60 are formed on a partial region of the channel layer 40 and a partial region of the gate dielectric layer 30 by using a third photolithography and etching process; and it can be seen from FIG. 1D that the source 50 and the drain 60 are respectively extended from both sides of the channel layer 40 onto the gate dielectric layer 30 and expose a partial region of the channel layer 40. Further referring to FIG. 1E, a passivation layer 70 is formed on the substrate 10 to cover the gate dielectric layer 30, the channel layer 40, the source 50 and the drain 60. Furthermore referring to FIG. 1F, a fourth photolithography and etching process is used to pattern the passivation layer 70 so as to form a via hole H in the passivation layer 70. As shown in FIG. 1F, the via hole H in the passivation layer 70 exposes a portion of the drain 60. Moreover as shown in FIG. 1G, a fifth photolithography and etching process is used to form a pixel electrode 80 on the passivation layer 70. Referring to FIG. 1G, the pixel electrode 80 can be electrically connected to the drain 60 through the via hole H. After completing the pixel electrode 80, the whole pixel structure 90 is completed as well.
According to the above description, a conventional pixel structure 90 is fabricated by using five photolithography and etching processes, which means a pixel structure 90 requires five photo-masks with different patterns. Since a photo-mask is very expensive and each photolithography and etching process requires photo-masks with different patterns; thus, by reducing the number of the photolithography and etching processes, the fabrication cost of the pixel structure 90 can be effectively reduced.
In addition, along with increasing size of a TFT LCD panel, the photo-mask size for fabricating the TFT LCD panel is accordingly larger. A photo-mask with large dimension even would cost much more, so that the fabrication cost of a pixel structure 90 fails to be effectively reduced.