Thin film transistors (TFTs) with better performance are required for incorporation into the next generation of mobile and high resolution displays because functional circuits, such as controller, drivers, and so on, will be integrated on the same substrate as the pixel array. The displays will require TFTs which have low power consumption, low threshold voltages, a steep subthreshold slope, and high carrier mobility. Although many researchers have focused on polysilicon TFTs to achieve these goals, Tai et al., Performance of Poly-Si TFTs fabricated by SELAX, IEEE Trans. Electron Devices, Vol. 51, No. 6, pp 934-939 (2004); and Mizuki et al., Large Domains of Continuous Grain Silicon on Glass Substrate for High-Performance TFTs, IEEE Trans. Electron Devices, Vol. 51, No. 2, pp 204-211 (2004), the common objective is to reduce the grain boundaries and hence improve the TFT performance; Walker et al., Improved Off-Current and Subthreshold Slope in Aggressively Scaled Poly-Si TFTs With a Single Grain Boundary in the Channel, IEEE Trans. Electron Devices, Vol. 51, No. 2, pp 212-219 (2004).
In order to alleviate the grain boundary problem all together, single crystalline silicon TFTs have been demonstrated, Shi et al., Characterization of Low-Temperature Processed Single-Crystalline Silicon Thin-Film Transistor on Glass, IEEE Electron Device Letters, Vol. 24, No. 9, pp 574-576 (2003). Single crystalline silicon layer on glass was obtained using an “ion-cutting” based layer transfer technique. A hydrogen implanted silicon wafer is first bond to a glass wafer. A thin silicon film is next exfoliated from the silicon wafer and transferred to glass wafer. The single crystalline silicon TFTs exhibited significantly higher electron mobility (˜430 cm2/V-sec), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias.
To further improve the TFT performance, TFTs fabricated on strained-silicon-on-glass (SSOG) wafer have been described by Maa et al., Method of Making Silicon-on-Glass via Layer Transfer, U.S. patent application Ser. No. 10/894,685, filed Jul. 20, 2004 (SLA.0864); and Maa et al., Strained Silicon-on-Insulator from Film Transfer and Relaxation by Hydrogen Implantation, U.S. patent application Ser. No. 10/755,615, filed Jan. 12, 2004 (SLA.0822). Strained silicon TFTs on glass demonstrated an effective electron mobility up to 850 cm2/V-sec. The fabrication of SSOG wafer begins with a compressively-strained, thin SiGe layer deposition on a silicon wafer. The SiGe thickness is between about 200 nm to 400 nm, and has either a fixed or a graded composition. The SiGe relaxation is achieved by hydrogen implantation and subsequent thermal annealing. Strained silicon is deposited after CMP of the relaxed SiGe surface. Hydrogen splitting ion implantation is targeted deep into the silicon region, which is far from the strained silicon layer. In addition, the Si/SiGe interface helps to retard the propagation of defects and dislocations generated deep in the silicon region. The strained silicon-on-thin-SiGe virtual-substrate is bonded to a glass wafer. After splitting, SiGe is selectively removed, resulting in a strained silicon film, having a smooth surface, directly on glass.
Devices fabricated on SSOG wafer are similar to the devices fabricated on a silicon wafer, except that the process temperature is limited to a temperature below that of the glass transition temperature. Gate oxidation is by plasma oxidation, doped polysilicon deposition is performed to avoid polysilicon depletion issues, and NiSi is formed on the source, drain and gate to reduce the transistor series resistance, as described in U.S. Pat. No. 6,689,646 B1, granted Feb. 10, 2004, to Joshi et al., for Plasma Method for Fabricating Oxide Thin Films. 