The present disclosure relates to analog-to-digital conversion and, more particularly, some embodiments relate analog-to-digital conversion that is well-suited for image sensor readout circuitry, such as image sensor readout circuitry that includes column-parallel analog-to-digital converters (ADCs).
To provide an illustrative practical context, this background discussion relates to CMOS image sensors; however, it will be understood that ADCs in accordance with the present disclosure are not limited to image sensor readout applications, and may be implemented in myriad applications.
The readout of a pixel in a CMOS image sensor requires reading two levels—the reset level and the signal level. Depending on the architecture of the image sensor, the reset level may come before or after the signal level in time. The final pixel value is determined by differencing the signal level and the reset level. This differential result eliminates the pixel-to-pixel variations in the absolute voltage offsets of the reset-level. If the pixel is 4T-type, the reset kTC noise will also be eliminated by the differencing; this is called correlated double sampling (CDS).
As sensor frame rates and resolutions increase, the row time must decrease. The row time comprises the row-wise pixel readout into column sample and hold capacitors (sample reset and sample signal), followed by an ADC conversion, as shown in FIG. 1. It becomes more and more difficult to shrink the times for the pixel readout and ADC conversion, to support shorter row times. Shrinking the pixel readout requires faster settling from the pixel outputs, which requires more power. This is further complicated by increased sensor resolution, which increases the amount of parasitic capacitance on the pixel output lines, increasing the settling time. Shrinking the ADC conversion time also requires increasing the power and area required.
One approach is to pipeline the pixel readout and ADC conversion so that each operation can use a full row time to finish, by, for example, ping-ponging between two ADCs that run at half the row-rate. This approach is expensive in terms of area, due to the duplication of the circuitry, and may effectively preclude or limit the use of certain ADC designs because of chip area limitations. In addition, differences between components of the ping-ponged ADCs (e.g., comparator characteristics; binary weighted capacitor matching for SAR ADCs) can lead to offsets between the ping-ponged ADCs.