Field
Aspects of the present disclosure relate generally to input/output (I/O) drivers, and more particularly, to an I/O driver that implements dynamic gate biasing of buffer transistors for implementing the I/O driver using low-voltage transistors.
Background
An input/output (I/O) driver receives an input voltage that varies between a high logic voltage and a low logic voltage associated with a particular core voltage domain. In response to the input voltage, the I/O driver generates an output voltage that varies between a high logic voltage and a low logic voltage associated with an I/O voltage domain.
Generally, a difference between the high and low logic voltage of the I/O voltage domain is greater than a difference between the high and low logic voltage of the core voltage domain. This may be because the core circuitry of an integrated circuit (IC) operates with smaller voltages for higher processing speed and lower power consumption purposes.
When a voltage signal processed by the core circuitry is ready to be transmitted to another IC, the core circuitry provides the voltage signal as an input voltage to an I/O driver. As discussed above, the I/O driver generates an output voltage based on the input voltage, wherein the output voltage is in a higher voltage domain suitable for transmission of the signal to another IC or external device.
Generally, I/O drivers are implemented with field effect transistors (FETs) that are much larger than FETs implemented in core circuitry. This is because the FETs of I/O drivers need to be able to withstand the larger voltages associated with the I/O voltage domain. As a result, different masks and processes are needed to manufacture IC with relatively small FETs for the core circuitry and relatively large FETs for the I/O drivers. This produces higher costs and delays associated with the manufacture of such ICs.