The present invention relates to a dynamic RAM (Random Access Memory) and a semiconductor device, and to a technology effective for application to a so-called open bit line type wherein dynamic memory cells are respectively placed at points where word lines and bit lines intersect.
According to investigations subsequent to the completion of the present invention, it has been revealed that Japanese Patent Application Laid-Open No. Sho 59(1984)-2365 (hereinafter called “prior art 1”), Japanese Patent Application Laid-Open No. Sho 60(1985)-195795 (hereinafter called “prior art 2”), Japanese Patent Application Laid-Open No, Sho 60(1985)-211871 (hereinafter called “prior art 3”), and Japanese Patent Application Laid-Open No. Hei 9(1997)-135009 (hereinafter called “prior art 4”) are related to the present invention, which is described later.
The prior arts 1 through 3 relate to a technology which makes use of even information storage capacitors which uses capacitance of MOS transistor and supplies a voltage to each of plate electrodes employed in an open bit line type (one-intersection type or system). In the publication of the prior art 1, first wires crossed in a direction orthogonal to each bit line and connected at plural points, second wires for interconnecting the first wires with one another, and third wires for connecting central portions of the second wires to their corresponding power or source lines are ‘provided to achieve the uniformity of accurate potential distributions of opposite electrodes of the information storage capacitors. In the publication of the prior art 2, a resistor is provided between two plate electrodes provided with a sense amplifier interposed therebetween to thereby delay a change in the potential of each plate electrode in association with a change in substrate voltage at the time that information stored in each memory cell is read out to a bit line, In the publication of the prior art 3, a plate electrode and wires for supplying voltages thereto are formed of a metal having a high melting point and low in resistance, or silicide of the metal and silicon. Alternatively, a plurality of metal wiring layers are provided on the plate electrode.
According to the prior art 1, a problem developed due to the fact that a source voltage changed according to the operation of a peripheral circuit is not transferred to the entirety of a plate electrode, is solved by laying out voltage-supplying power or source wires at plural points of the plate electrode and uniformizing the potential of the plate electrode on the whole of the plate electrode according to the change in potential due to the operation of the peripheral circuit. According to the prior art 2, a problem developed due to the fact that a relative potential change differs from a change in potential on the substrate side, is solved by connecting the two plate electrodes trough a resistor having time constant associated with the change in potential on the substrate side. In the prior art 3 on the other hand, the problem that a change in potential supplied to each plate electrode from its corresponding bit line through a storage capacitor would lead to the application of a voltage to the plate electrode, is solved by reducing the resistance of each wire connected to the plate electrode.