The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having clock wiring with reduced clock skew.
Some semiconductor integrated circuit devices, such as VLSIs, include a synchronous circuit having flip-flops driven by a common clock signal. To make such a synchronous circuit operate more rapidly, these semiconductor integrated circuit devices require that clock skew (i.e., differences in clock supply timing between flip-flops) be minimized for removal of signal-to-signal timing differences.
Various layout design techniques for reducing such clock skew have been proposed. One such technique involves installing tree-structure paths between a clock signal generator and a plurality of flip-flops, wherein the length of the path between the generator and each flip-flop is suitably adjusted. Another technique, which is disclosed in Japanese Published Unexamined Patent Application No. Hei 9-307069, requires inserting clock buffers where appropriate when tree-structure wiring has been established, whereby the tree structure is readjusted so that the difference between a maximum and a minimum of delays on the readjusted wiring attains a predetermined value. Where there still remains clock skew despite the provision of tree structure wiring, another technique disclosed in Japanese Published Unexamined Patent Application No. Hei 8-274260 seeks to minimize the skew by replacing appropriate drivers with small-capacity drivers so that the paths with maximum skew become equal in skew level to other tree branch paths between second stage clock drivers and block circuits.
The conventional techniques outlined above have failed to consider optimum arrangements of skew reduction for VLSIs. These techniques presuppose that on tree-structure paths between a clock generator and each flip-flop, each node is afforded wiring of an equal length. If equal-length wiring is provided ranging from a clock generator through a plurality of stages of drivers to flip-flops, alternative lines necessitated by the equal-length lines at all stages prolong the overall clock wiring. The resulting disadvantages include more delays of clock signals and higher power dissipation.
Furthermore, the conventional techniques above have disregarded an optimum clock layout for each of the functional portions or for each of a plurality of clock phases in connection with LSIs. A VLSI comprises random logic circuits and data paths reflecting various functions of the device, as well as numerous I/O pads. The conventional techniques have so far shied away from providing any optimum clock layout for the diverse internal arrangements of the LSI.