1. Field of the Invention
The present invention relates to a method of manufacturing a solid-state image sensor.
2. Description of the Related Art
A solid-state image sensor such as a CCD sensor or CMOS sensor is used as that mounted in cameras such as a video camera and digital still camera. In recent years, along with an increase in number of pixels and a reduction of a chip size, a pixel size in the solid-state image sensor is reduced. Such pixel size reduction causes transition of an element isolation method from a LOCOS (Local Oxidation of Silicon) method to an STI (Shallow Trench Isolation) method.
The STI method suffers a problem of image signal noise caused by defects at an interface between a silicon substrate and silicon oxide film in the vicinity of trenches and a neighboring portion of the interface. As a measure against such problem, a technique for forming different STI structures in a pixel region and peripheral circuit region is available. Japanese Patent Laid-Open No. 2009-272597 discloses a method of manufacturing a solid-state image sensor in which an embedding depth of an element isolation portion of an STI structure arranged in a pixel portion is shallower than that of an element isolation portion of an STI structure arranged in a peripheral circuit portion. In the manufacturing method described in Japanese Patent Laid-Open No. 2009-272597, an insulating film of the peripheral circuit portion is etched through openings of a resist mark, thereby forming trenches for the STI structure of the peripheral circuit portion. Then, after the resist mark is removed, a new resist mark is formed, and an insulating film of the pixel portion is etched through openings of the new resist mark, thereby forming trenches for the STI structure of the pixel portion.
With the manufacturing method described in Japanese Patent Laid-Open No. 2009-272597, after the trenches for the STI structure of the peripheral circuit portion are completed, the resist mask used to form the trenches is removed. As can be seen from this, in the manufacturing method described in Japanese Patent Laid-Open No. 2009-272597, the thickness of the resist mask used to form the trenches for the STI structure of the peripheral circuit portion is decided so that the resist mask is left after formation of the trenches is completed by etching. Therefore, as the peripheral circuit portion and pixel portion are further miniaturized, an aspect ratio (height/width) of the resist mask is increased, and the resist mask is readily collapsed. The resist mask can be prevented from being collapsed by reducing the aspect ratio using a thin resist mask. In this case, however, a resist film may disappear during etching for trench formation.