1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device, that has multi-layer interconnection structure, and includes a region between interconnects filled with low strength materials.
2. Description of the Related Art
In recent years, the multi-layer interconnection structure is employed to meet the needs of micro-fabrication and high integration in semiconductor devices. FIG. 23 is a cross-sectional view schematically showing a semiconductor device having the conventional multi-layer interconnection structure. As shown in FIG. 23, the surface of a semiconductor substrate 101 is formed with interconnection layers 102a to 102c. The surface of an interlayer dielectric film 103 is provided with interconnection layers 104a and 104b. The interconnection layers 104a and 104b are connected with interconnection layers 102b and 102c via connection plugs 105a and 105b, respectively.
Dielectric and conductive films constituting the semiconductor device form parasitic resistance and capacitance. Parasitic resistance and capacitance are factors generating RC delay. In order to reduce the RC delay, using interlayer dielectric films made of low dielectric constant material having a dielectric constant of about 2.5 or less has been studied. For example, porous SiOC (silicon oxide film containing carbon) is used as the low dielectric constant material.
In order to reduce the capacitance between interconnection layers, the study of a so-called air-gap interconnection structure has been conducted. In the air-gap interconnection structure, the region equivalent to the interlayer dielectric film is a vacuum or in a state enclosing gases. The air-gap interconnection structure is employed to reduce the dielectric constant of the region between interconnection layers.
The low dielectric constant material has a low strength, generally. For this reason, the following problems arise when the low dielectric constant material is used as the interlayer dielectric film.
When planarizing the surface using CMP (Chemical Mechanical Polish), the interlayer dielectric film 103 has a portion which is not durable to pressure applied from top. For this reason, as seen from FIG. 24, cracks occur in the interlayer dielectric film 103, particularly around the interconnection layer 104a not formed with a connection plug thereunder. In addition, the multi-layer interconnection structure is stacked higher, and thus, the lower layer, that is, the interlayer dielectric film 103 near to the semiconductor substrate 101 is not durable to the load from above. In this case, cracks occur in the lower interlayer dielectric film 103, likewise.
Each component of the semiconductor device is cooled after heat treatment during the manufacturing process, and thus, stresses of different directions and forces occur, depending upon material. Conventionally, the stress applied to the interconnection layer 104b has been offset by stress generated by the interlayer dielectric film 103. However, if a low strength material is used as the interlayer dielectric film 103, a sufficient stress cannot be applied to the interconnection layer 104b. For this reason, there is a possibility that the interconnection layer 104b is severed.
If the air-gap interconnection structure is employed, the strength of the region equivalent to the interlayer dielectric film 103 is lower than a low-strength interlayer dielectric film 103. For this reason, the use of the low-strength interlayer dielectric film 103 is particularly problematic.