The present invention generally relates to fabrication of semiconductor devices and more particularly to the fabrication process of a semiconductor device including a photolithographic process that uses a reticle.
Generally, semiconductor devices of these days are formed as a lamination of large number of patterns. Each of the pattern layers constituting the patterns is formed by a photolithographic process using a reticle, and the semiconductor devices are formed on a semiconductor wafer by repeating the process of forming a pattern layer in alignment with an underlying pattern layer.
In such a layered structure in which a large number of pattern layers are laminated, there can be caused the problem of misalignment between the patterns of different layers because of various reasons such as wafer alignment error, reticle alignment error, distortion of the exposure apparatus, aberration of the optical system used in the exposure apparatus, or the like. Thus, it is an important issue in the fabrication technology of semiconductor devices to suppress such pattern alignment error as much as possible. The total pattern alignment error caused by accumulation of various error factors is called “total overlay.”
Meanwhile, the tolerable error of pattern alignment is determined primarily by the design rule of the semiconductor device. Thus, the tolerable error decreases with decreasing pattern size. In the conventional trend, the tolerable error of pattern alignment is about ⅓ times the minimum pattern size in each of the layers.
The present invention addresses the problem of the reticle error originating by the error at the time of reticle manufacture and constituting one of the foregoing factors that builds up the total overlay.
While there are various estimates about the contribution of such a reticle error, a rough estimate gives the value of about ⅙ times of the total overlay for the contribution of the reticle error to the total overlay. Thus, in the case of recent ultrafine semiconductor devices designed in accordance with the design rule of 90 nm, for example, the total overlay between adjacent layers should be about 30 nm (=90×⅓) or less, while this means that the tolerable reticle error should be about 5 nm (=30×⅙) or less. In the case of the reticles formed with four times magnification (4× reticle), the corresponding tolerable error becomes 20 nm or less.
(Patent Reference 1) Japanese Laid-Open Patent Application 2001-155988