1. Field of the Invention
The present invention relates to a dynamic random-access memory (DRAM). More specifically, the present invention relates to a multi-port DRAM cell structure, as well as a circuit and method for accessing a multi-port DRAM cell.
2. Description of the Prior Art
Conventional DRAM cells have been provided in both single port and dual port configurations. In a typical single port configuration, as shown in FIG. 1, a DRAM cell 100 consists of an access transistor 101, a storage capacitor 120, a bitline 111 and a wordline 106. During a write access, a wordline enable signal is asserted on wordline 106 thereby turning on transistor 101. A data signal is provided on bitline 111. This signal is routed through transistor 101 and stored in capacitor 120. During a read access, a wordline enable signal is asserted on wordline 106 to turn on transistor 101. The data signal stored in capacitor 120 is routed to bitline 111 through transistor 101. This data signal is amplified by a sense amplifier (not shown) and then provided to the device initiating the read access. A disadvantage of a single port cell is that it does not enable dual port access.
FIG. 2 is a schematic diagram of a conventional dual-port DRAM cell 200. Cell 200 consists of write access transistor 201, read access transistor 202 and storage capacitor 220. The operation of cell 200 is similar to that of single port DRAM cell 100, except the read and write accesses are performed at two separate dedicated ports. The write port is defined by the write bitline 211 and write wordline 206. The read port is defined by the read bitline 212 and read wordline 205.
During a write access, a write wordline enable signal is asserted on write wordline 206, thereby turning on write transistor 201. A data signal is provided to capacitor 220 through write bitline 211 and write transistor 201. During a read access, a logic high wordline enable signal is asserted on read wordline 205. If a logic high data value is stored in capacitor 220, read transistor 202 turns on and the logic high wordline enable signal on read wordline 205 is transmitted to read bitline 212. If a logic low data value is stored in the capacitor 220, transistor 202 is not turned on, and read bitline 212 is left floating (i.e. a logic low value).
Another conventional dual-port DRAM cell 300, illustrated in FIG. 3, has a structure similar to dual-port DRAM cell 200 (FIG. 2). Thus, similar elements in DRAM cells 200 and 300 are labeled with similar reference numbers. However, the read access transistor 202 of DRAM cell 200 is replaced with read access transistors 302 and 303 in DRAM cell 300. The write access for DRAM cell 300 is identical to the write access of DRAM cell 200 (FIG. 2). The read access of DRAM cell 300 is carried out as follows.
A logic high wordline enable signal is asserted on read wordline 306, thereby turning on read access transistor 303 to couple read access transistor 302 to read bitline 312. If a logic high data value is stored in capacitor 320, then read access transistor 302 turns on, thereby drawing current from read bitline 312 indicating one data polarity. Conversely, if a logic low data signal is stored in capacitor 320, then read access transistor 302 is turned off, and no current will be drawn from read bitline 312 indicating a different data polarity.
The conventional dual-port DRAM cells 200 and 300 have several limitations. One limitation is that overlapping access is not allowed on a conventional dual-port DRAM cell. Overlapping access is defined as the ability to initiate either a read access or a write access at either port of the dual-port DRAM cell at any time. For example, a dual-port DRAM cell which provides for overlapping access would allow a first read access to be performed on a first port of the cell, while a second read access is performed on a second port of the cell. Because the two ports of dual-port DRAM cells 200 and 300 are dedicated read or write ports, overlapping access as described above is not permitted by dual-port DRAM cells 200 and 300.
Another limitation is that a refresh access can only be performed at one port of DRAM cells 200 and 300 (i.e., the write port). The charge stored in the storage capacitors of cells 200 and 300 can be depleted by leakage through the read and/or write access transistors. To compensate for this charge depletion, the storage capacitors must be periodically refreshed. A refresh access is performed by performing a read access followed by a write access, such that the data signal read from the cell is written back into the memory cell. In conventional dual-port DRAM cells 200 and 300, a write access can only be performed at the write port while a read access can only be performed at the read port. Thus, the refresh access must be performed using both the write port and the read port.
Another disadvantage of the conventional dual port cells is the large size on a die that a cell occupies. Conventional dual-port cells require a drain-to-gate connection. For example, in FIG. 2, a drain-to-gate connection between the drain of transistor 201 and the gate of transistor 202 is necessary. Similarly, in FIG. 3, there exists a drain-to-gate connection between the drain of transistor 301 and the gate of transistor 302. In conventional semiconductor technology, a via and a polysilicon or metal trace is typically required in order to make a drain-to-gate connection. Because the via and trace consume real estate on the die, the layout density of the resulting dual-port cell is reduced.
It would therefore be desirable to provide for a multi-port DRAM cell that overcomes these limitations of the prior art. One of the objectives of the present invention is to provide a multi-port DRAM cell which enables overlapping access. A further objective is to provide for a multi-port DRAM cell where write, read and refresh accesses can be performed on more than one port. Another objective is to provide a multi-port DRAM cell with reduced size by eliminating the transistor drain-to-gate connection. It is yet another objective of this invention to provide for a multi-port DRAM cell that provides a data access rate which is faster than the access rate of a conventional DRAM cell.