The present invention relates generally to a method of manufacturing semiconductor device by a dual damascene method.
In order to achieve the high density integration of semiconductor devices, it has been developed to provide devices, such as the scale down of patterns and the multilayering of circuits. As one of such devices, there is a technique for multilayering wiring. In order to provide a multi-layer metallization structure, a number n wiring layer and a number (n+1) wiring layer are connected to each other by means of a conductive layer, and a thin film called an interlayer dielectric film is formed in a region other than the conductive layer. This interlayer dielectric film is sometimes formed in a layer right above or further above a silicon substrate.
As one of typical interlayer dielectric films, there is a SiO2 film. In recent years, in order to more accelerate operation of devices, it has been required to reduce the dielectric constant of the interlayer dielectric film, and the material of the interlayer dielectric film has been examined. That is, the dielectric constant of SiO2 is about 4, and it has been diligently studied to dig up materials having a lower dielectric constant than that of SiO2. As one of such materials, it has been studied to put SiOF having a dielectric constant of 3.5 into practice. The inventor has taken notice of a fluorine containing carbon film (which will be hereinafter referred to as a xe2x80x9cCF filmxe2x80x9d) having a still lower dielectric constant.
By the way, as a technique for simultaneously forming a groove wiring and a via plug, there is a dual damascene process. As methods of manufacturing semiconductor device using a low dielectric constant interlayer dielectric film by this process, supposed process flows, such as a method for etching a groove, a method for previously etching a via hole and a method for simultaneously etching a groove and a via hole by self alignment, are described in Monthly Semiconductor World, February 1998, pp. 108-114.
Referring to FIGS. 17 and 18, the method for simultaneously etching by the self alignment will be briefly described. In FIG. 17(a), reference number 10 denotes a first low dielectric constant interlayer dielectric film, 11 denotes an Si3N4 layer, and 12 denotes an etching stopper layer of an Si3N4 layer of an SiO2 film. First, as shown in FIGS. 17(b) and 17(c), the etching stopper layer 12 is etched so as to have a hole pattern. In the figure, reference number 13 denotes a photoresist. Then, on the top face of the etching stopper layer 12, a second low dielectric constant interlayer dielectric film 14, in which a groove will be formed, and a hard mask 15 of an SiO2 film are deposited in that order (see FIGS. 17(d) and 17(e)).
Subsequently, as shown in FIGS. 18(a) and 18(b), the hard mask 15 is etched so as to have a groove pattern, and then, as shown in FIG. 18(c), the hard mask 15 is used as a mask for carrying out etching to form a groove 14a in the second low dielectric constant interlayer dielectric film 14. Then, the etching stopper layer 12 is used as a mask for further continuing the etching to form a via hole 10a in the first low dielectric constant interlayer dielectric film (see FIG. 18(d)). In the figure, reference number 16 denotes a photoresist.
However, the above described method requires, in total, four etching processes for the etching stopper layer 12, the hard mask 15 and the first and second low dielectric constant interlayer dielectric films 10 and 14, so that the number of processes is large. In addition, since the etching for the groove and the etching for the via hole are sequentially carried out, there is supposed a problem, such as the influence of excessive radicals due to the sudden decrease of the etched area from the groove to the via hole.
Also in the process flow for forming a via hole after forming a groove and in the process flow for forming a groove after forming a via hole, the number of etching processes is large, and it is required to carry out a process, which is not carried out in conventional etching processes, for treating a place which has been etched once, so that various problems are estimated. Thus, there are serious problems in that the dual damascene process is complicated in the present circumstances and has a bad throughput to increase costs.
The present invention has been made in such circumstances, and it is therefore a principal object of the present invention to provide a method of manufacturing semiconductor device using, e.g., a fluorine containing carbon film having a dielectric constant, as an interlayer dielectric film by a dual damascene method which is a simple technique.
Therefore, the present invention is characterized by the steps of: forming an dielectric film on an object to be treated; etching the dielectric film to form a via hole therein; forming a top dielectric film of, e.g., a fluorine containing carbon film, on a surface of the dielectric film, in which the via hole has been formed, using a thin-film deposition material having a bad embedded characteristic; and etching the top dielectric film to form therein a groove, in which a metal is embedded for forming a wiring, so that the groove contacts at least a part of the via hole. The expression xe2x80x9ca bad embedded characteristicxe2x80x9d means that the embedding of an dielectric film into a hole of an underlayer is bad since an object is the hole, although the embedding of an dielectric film into a groove is usually discussed. For example, the step of forming the fluorine containing carbon film is carried out by activating a thin-film deposition material, which includes a compound of carbon and fluorine and which has a bad embedded characteristic, e.g., hexafluorobenzene, as a plasma.
In addition, the present invention is characterized by the steps of: forming an dielectric film on an object to be treated; etching the dielectric film to form a via hole therein; forming a top dielectric film having an etch selectivity, which is different from that of the dielectric film, on a surface of the dielectric film, in which the via hole has been formed; etching the top dielectric film to form therein a groove, in which a metal is embedded for forming a wiring, so that the groove contacts at least a part of the via hole; and etching the top dielectric film for a predetermined period of time after the etching of the top dielectric film is completed, so that the top dielectric film deposited in the via hole is etched to be removed. In this case, a thin film having an etch selectivity which is different from that of the dielectric film may be formed on the surface of the dielectric film, in which the via hole is formed, to form the top dielectric film on the thin film. The top dielectric film may be a fluorine containing carbon film or a coating film.