In a digital LSI having a latch or flip-flop that samples data responsive to a clock signal, it is necessary for the setup time and hold time to be within preset time widths in order for the data to be sampled correctly by the latch or flip-flop. Prescribed values relating the setup time and hold time of a latch or flip-flop need to be taken into account in the design of an LSI. The setup time is the time interval during which a data signal to be sampled by a latch, for example, needs to be kept stabilized before the timing of an effective edge, such as a rising edge, of the clock. The hold time is the time interval during which the data signal must be retained as from the effective edge of the clock. Meanwhile, the setup time and hold time of the latch or flip-flop is prescribed with a margin to have time ranges larger than actual ones and the operation range of the latch or flip-flop is set so that the operation speed will be lowered than that corresponding to the actual performance of the latch or flip-flop.
It is necessary to measure the setup time and hold time of e.g. the latch and to suitably decide the time range to be met in the design of an LSI. Accordingly, it is desired that whether or not e.g. a latch meets the requirements for setup time and hold time can be measured with ease and more comprehensively.
As a system for measuring AC characteristics of an LSI, in particular a system for measuring the setup time and the hold time of a digital LSI, reference is made to Patent Document 1, as an example. FIG. 10 shows the configuration of a system disclosed in this Patent Document 1. Referring to FIG. 10, the system includes, outside an LSI 4 under measurement, a clock supply means 1, for supplying a clock signal CLK, a pulse generating means 2, and a pulse delaying means 3. The pulse generating means 2 repeatedly generates pulses for measurement, each of a preset pulse width, in synchronization with the clock signal. The pulse delaying means 3 operates for delaying the pulse for measurement to supply the so delayed pulse to the LSI 4 under measurement. The pulse delaying means 3 also operates for changing the amount of delay, at each repetition of the pulses for measurement, based on a changeover control signal, in a direction of decreasing the phase difference of the clock signal as compared to that at the previous repetition. There is provided, within the LSI 4 under measurement, an input latch decision means 43 for deciding whether or not an input latch circuit 41 as a device under measurement has correctly taken in the pulse for measurement, for each repetition of the pulse for measurement, and for outputting a changeover control signal for varying the amount of delay as long as the pulse for measurement is taken in correctly.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-7-84000