Once formation of semiconductor devices and interconnects on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. The packaging substrate may then be assembled on the circuit board.
Thus, the packaging substrate facilitates formation of an electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area located on a top surface of the packaging substrate. The die foot print area contains C4 pads on which a semiconductor chip may be attached by C4 bonding.
Since lead-free C4 balls are more environmentally friendly than lead based C4 balls, use of lead-free C4 balls in the semiconductor industry has been increasing recently at the expense of lead based C4 balls. Lead-free C4 balls are less malleable than lead-based C4 balls. This has a disadvantageous effect on reliability of a semiconductor package employing lead-free C4 balls. Silicon has a coefficient of thermal expansion of about 3 parts per million (ppm) per degree Celsius, and organic packaging materials have a coefficient of thermal expansion of about 15 ppm per degree Celsius. The differences in the coefficients of thermal expansion induce high shear stress on the C4 balls and the metal interconnect structure therebeneath. Highly malleable C4 balls, such as the lead based C4 balls, deform under such shear stress so that the metal interconnect structures underneath do not delaminate. However, less malleable C4 balls such as lead-free C4 balls transmit a higher fraction of the shear stress to the metal interconnect structures underneath, which induces delamination of metal lines from the dielectric layer in which the metal lines are embedded. Typically, such delamination occurs at the uppermost copper interconnect level.
At the same time, use of a low dielectric constant material in metal interconnect structures is preferred to reduce capacitive coupling between adjacent metal lines, and consequently to reduce RC delays of signals transmitted through the metal lines.
In view of the above, there exists a need for a metal interconnect structure that provides a higher adhesion strength between a metal line and a dielectric layer embedding the metal line, while at the same time minimizing capacitive coupling between the metal line and adjacent metal lines and metal vias, and methods of manufacturing the same.