1. Field of the Invention
This invention relates to level sensitive circuits fabricated in integrated circuit technology and more particularly to level sensitive circuits useful as data sense amplifiers in MOSFET Read Only Memory (ROM) array integrated circuits.
2. Description of the Prior Art
Level sensitive data sensing circuits used in ROM integrated circuit devices are designed to detect data signals resulting from the presence or absence of a selected device located within a matrix of addressable switching devices. In IGFET ROM Devices the presence or absence of an addressed IGFET causes the potential of a bit sense line either to remain at a preselection set potential or to be charged toward one of the device supply voltage levels. The time required to address a selected memory cell location and determine its effect on a bit sense line is critical to the usefulness of the ROM. This time is highly dependent upon a number of circuit parameters including device sizes, voltage supply levels, parasitic circuit capacitances and response time of data sensing circuits. Many ROM circuit designs rely on the performance of a simple inverter coupled to a precharged data bit sense, or bit line, as a sense amplifier. Other designs, for example see the article "A 4-Mbit Full-Wafer ROM", by Y. Kitano et al, IEEE Journal of Solid-State Circuits, Vol. SC-15, pp. 686-693, August 1980, use a clock-responsive inverter circuit in which a pre-charged data line must be discharged from a drain supply voltage level to the threshold voltage of an IGFET. More complicated designs avoid the relatively long discharge time of the bit lines by using an inverter having a high logic threshold switching point so that the bit line is not required to fully discharge prior to sensing. See, for example, FIG. 4. of the article "A 65 mW 128K EB-ROM", by K. Kiuchi et al, IEEE Journal of Solid-State Circuits, Vol. SC-14, pp. 855-859, October 1979. This high threshold inverter circuit, although potentially reducing the time required to sense changes in the data bit line, uses a number of clock signals requiring critical sequencing in order to avoid erroneous reading of data. In addition, the transistion time of the enabling pulse is also critical, since if it rises too quickly, a high level signal will be read regardless of the voltage on the data bit line. Yet another level sensitive ROM array sensing circuit is taught in the article, "High Noise Immunity Column Select/Sense Amplifier Circuit", by H. L. Kalter et al, IBM Technical Disclosure Bulletin, Vol. 23, pp. 2250-2254, November 1980. Here a level sensitive Schmitt-Trigger circuit is combined with a logic enabling clock pulse which must be coincident with the appearance of the data input signal to provide proper operation of the circuit.
Various additional level sensitive circuits are known in the art. U.S. Pat. No. 3,873,856 to Gerlach is of interest as it teaches a number of equivalent circuits, all of which include the use of feedback of an inverted input signal to the source electrode of an input IGFET which tends to increase the gate to source voltage, and thus increase the rate of change in drain current, in response to an increasing input signal and to decrease the gate to source voltage in response to a decreasing input signal. Feedback to the source electrode of an input device may be implemented in various ways. Maeder et al, in U.S. Pat. No. 4,071,784, teaches the use of a depletion mode source follower or a resistor to provide continuous feedback for all levels of input voltage. Such circuits tend to provide little choice in the point at which the input signal causes the output to change.
U.S. Pat. No. 3,882,331 to Sasaki teaches a level sensitive trigger circuit in which a voltage divider is provided between the input and output of a hysteresis circuit so that the input level switching point is a function of both the input and output voltage.
U.S. Pat. No. 4,048,524 to Laugesen et al is also of interest as it teaches a level sensitive circuit in which multiple trip points are used to sense power supply variations. U.S. Pat. No. 4,063,119 to Odell is of interest as it teaches the use of two independent output-responsive feedback circuits for separately establishing the circuit trip point and the levels of the output signal. U.S. Pat. No. 4,242,604 to Smith is of interest as it teaches a level sensitive circuit which includes compensation for changes in device parameters so that the trip point is a fixed value.
It is the purpose of the subject invention to avoid the problems of the prior art and to provide a level sensitive circuit which has the ability to sense voltages at various levels with improved switching speed without the requirement of complicated clocking schemes.