In many digital logic applications it is desirable to present data at the input/output ports of an integrated circuit device (IC) employing as high a data rate as the IC device can tolerate. This high data throughput rate is important in applications such as network communications, cell phone base stations, and others.
Different approaches have been used in the past to maximize data input and output rates. Principal among these has been to speed up the clock rate at which a device is capable of operating. These approaches have focused on improving the process or manufacturing tolerances of the materials and tools used to make IC devices. However, whatever process or device improvements are made, for any given technology there is a maximum clock rate which sets the data rate.
Reprogrammable logic devices, such as field programmable gate arrays (“FPGA”), are commonly used in all types of digital logic applications. Consequently, FPGAs are used in many applications that require high data throughput. The data throughput rate of an FPGA, as with other ICs is also limited by its maximum clock rate.
FPGAs typically include an array of logic function generators or configurable logic elements, input/output ports, and a matrix of interconnect lines. The matrix of interconnect lines generally surrounds the configurable logic elements and connects logic data signals between the configurable logic elements and between the configurable logic elements and the input/output ports. FPGAs are configured by programming memory elements, such as static RAM cells, anti-fuses, EPROM cells, and EEPROM cells, which control configuration of the device. Depending on the programming of the memory elements, the configurable logic elements will perform different logic functions and be connected to each other and to the input/output ports in a variety of ways. In general, FPGA's also provide programmable memory cells to configure other features on the IC. For instance, the routing of clock signals and use of multiple clock nets on an FPGA is often programmably selectable by the user.
It is desirable then to implement a logic circuit design which, regardless of the limitations of the process used to manufacture an integrated circuit device, is capable of increasing the rate of data throughput at the device output for any given manufacturing process. It is further desirable to incorporate such a logic circuit design into an FPGA to capitalize on the throughput capabilities of the logic circuit and to provide programmable features to the logic circuit design that cannot be provided in a non-configurable device.