1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory) semiconductor memory device having a multiport memory or a content addressable memory.
2. Description of the Background Art
In multiport memory cells, bit lines or word lines of each port are often arranged adjacent to each other. Therefore, the coupling capacitance between interconnections may cause crosstalk, resulting in a malfunction.
Japanese Patent Laying-Open No. 2000-12704, for example, proposes a method of avoiding interference of word lines with each other by providing GND interconnections for write word lines and read word lines. Similarly, Japanese Patent Laying-Open No. 2000-236029 proposes a method of avoiding interference between word lines by providing a GND interconnection between rows of memory cells adjacent to each other.
Both of these approaches require a sufficient space between a word line and a word line, since a shielding interconnection is provided between word lines. If there is originally a gap between word lines in memory cells, provision of the shielding interconnection does not increase the area. In a layout configuration of a two-port memory cell that is long in a lateral direction, as shown in Japanese Patent Laying-Open Nos. 2002-43441 and 2002-237539, for example, the word lines connected to each port are arranged adjacent to each other, and if the space therebetween is small, there is no room to be provided with the shielding interconnection.
In view of the forgoing, if the shielding interconnection is inserted in the layout configuration of the laterally long two-port memory cell, the memory cell area is inevitably increased, accordingly.
If the shielding interconnection is not provided, the increased coupling capacitance between word lines as described above increases the coupling noise, which causes a malfunction.