1. Field of the Invention
The present invention relates to nonvolatile semiconductor memories with NAND structured cells, and more particularly, to a method and apparatus for programming nonvolatile semiconductor memories with NAND structured cells.
2. Description of the Related Art
NAND structured cells have been developed for nonvolatile semiconductor memories, such as electrically erasable and programmable read only memories (EEPROMs), to reduce the on-chip area occupied by memory cells. The NAND structured cell (hereinafter, referred to as a "cell unit") typically includes a first selection transistor whose drain is connected to a corresponding bit line via a contact hole, a second selection transistor whose source is connected to a common source line and a plurality of memory transistors whose channels or drain-source paths are connected in series between the source of the first selection transistor and the drain of the second selection transistor. Such cell units are formed on a p-type well in a semiconductor substrate. Each memory transistor includes a floating gate formed on a gate tunnel oxide disposed over a channel region between the source and drain regions of the transistor and also includes a control gate formed on an intermediate insulating film disposed over the floating gate. Since such cell units reduce the number of selection transistors required per cell and the number of contact holes needed for ohmic contact with a bit line, EEPROMs using them may achieve a high density of memory capacity without increasing chip area.
A memory cell array for such an EEPROM is comprised of a multiplicity of cell units arranged in a matrix form of rows and columns. Gates of first selection transistors in a row of cell units are connected in common to a first selection line. Control gates of each series-connected memory transistor in the row are respectively connected to word lines. Gates of second selection transistors in the row are connected in common to a second selection line. The cell units in each row constitute a row block. Bit lines are connected to data latches providing a page buffer.
Before programming the memory transistors connected to a selected word line, all memory transistors within a row block associated with the selected word line, or the entire memory cell array, must be erased. Erasure is performed by applying an erase voltage of about 20 volts to the p-type well region, while applying 0 volts to the word lines of the row block or the memory cell array. Then, erased memory transistors are changed into depletion mode transistors with negative threshold voltages by extracting electrons from their floating gates by Fowler-Nordheim tunnelling. It is assumed that the erased memory transistors store data "1".
After the memory transistors are erased, programming is executed. To perform programming at high speeds, page programming is used, wherein data is written into all of the memory transistors connected to a selected word line at once. After loading data input via external data input terminals into the data latches respectively connected to the bit lines, page programming is used to write the data stored therein into all the memory transistors connected to the selected word line at one time.
FIG. 1 is a circuit diagram for illustrating conventional page programming in connection with a row block.
Assume that programming is to be performed for memory transistors M21.about.M2n connected to a word line WL2. For simplicity of explanation, assume also that the selected memory transistors M21 and M2n are to be programmed to data "1" and data "0", respectively. Accordingly, the data latch connected to the bit line BL1 stores data "1" and the data latch connected to the bit line BLn stores data "0".
During programming, a bit line connected to a memory transistor which must maintain data "1", i.e. erased data, is defined as an "unselected" bit line, and a bit line connected to a memory transistor which must be changed into data "0" is defined as a "selected" bit line.
In the programming operation, the bit lines BL1 and BLn are respectively connected to data "1" (power supply potential Vcc) and data "0" (ground potential of 0 volts) Stored in the data latches associated therewith. The power supply potential Vcc is applied to the first selection line SSL. A pass potential Vpass, for example, 10 volts, is applied to unselected word lines WL1 and WL3.about.WL16, and a programming potential Vpgm, for example, 18 volts, is applied to the selected word line WL2. The ground potential of 0 volts is also applied to the second selection line GSL, thereby turning off the second selection transistors GT11.about.GT1n.
Then, the potential corresponding to data "0", i.e. the ground potential, is applied to the selected bit line BLn, and the power supply potential Vcc is applied to the gate of the first selection transistors ST1n, thereby causing the transistor ST1n to be turned on. The pass potential Vpass and the programming potential Vpgm are applied to the control gates of memory transistors M1n.about.M16n connected to the selected bit line BLn via the word lines as explained above. Therefore, the memory transistors M1n.about.M16n are all turned on, and their drains, sources and channels go generally to ground potential. At the same time, the programming potential Vpgm applied to the control gate of the memory transistor M2n connected to the selected word line WL2 causes the programming potential Vpgm to apply across its control gate and drain, source and channel, and thereby electrons tunnel into the floating gate of the memory transistor M2n. Consequently, the memory transistor M2n is changed into an enhancement mode transistor with a positive threshold voltage, i.e. it stores data "0".
On the other hand, the power supply potential Vcc, which corresponds to data "1", is applied to the unselected bit line BL1 from the data latch connected thereto in order for memory transistor M21 to maintain the erased data, i.e. data "1". Since the power supply potential Vcc is applied to the first selection lines SSL, the potential Vcc applies to the gate and drain of the first selection transistor ST11. Thereafter, the potential of control gates of memory transistors M11.about.M161 connected to the source of the first selection transistor ST11 increases from 0 volts to the pass potential Vpass and the programming potential Vpgm. Accordingly, the drains, sources and channels of the transistors M11.about.M161 are charged by capacitive coupling to a boost potential of Vbt. This potential is higher than the potential of Vcc-Vth, where Vth is a threshold voltage of the first selection transistor ST11, and may be expressed by the following equation: ##EQU1## where C1 is a capacitance between the control gate of each memory transistor and the source, drain and channel thereof, C2 is a capacitance between the channel, source and drain thereof and the p-type well, a coupling coefficient r is ##EQU2## and n is the number of memory transistors within each cell unit.
Once the drains, sources and channels of memory transistors M11.about.M161 charge up to Vcc-Vth, the first selection transistor ST11 is turned off and then the drains, sources and channels of memory transistors M11.about.M161 uniformly charge to the boost potential Vbt. Therefore, the difference between the potential of the control gate and the potential of the drain, source and channel of the selected memory transistor M21 goes to Vpgm-Vbt. Because this potential difference is not high enough for F-N tunneling to occur, programming of the memory transistor M21 is inhibited. Therefore, the memory transistor M21 maintains the negative threshold voltage caused by its erasure. This self-program inhibition scheme is disclosed in U.S. Pat. No. 5,473,563 which is assigned to the assignee of the present invention, and which is incorporated herein by reference.
However, the self-program inhibition scheme as mentioned above has several problems. For example, when the pass potential Vpass is increased, the threshold voltages of nonselected memory transistors M1n and M3n.about.M16n within the cell unit associated with the programmed memory transistor M2n can increase due to the increased potential applied between control gates and drains, sources and channels of the nonselected memory transistors M1n and M3n.about.M16n. Therefore, it is desirable to lower the level of the pass potential Vpass. However, this lowers the value of Vbt, and hence increases the potential difference Vpgm-Vbt between the control gate and the drain, source and channel of the selected memory transistor M21. This in turn increases the threshold voltage of memory transistor M21 so that its ability to maintain erased data, i.e. data "1" is deteriorated. Therefore, an appropriate value for the pass potential Vpass must be determined such that the threshold voltages of both selected and nonselected memory transistors are not increased.
FIG. 2 is a diagram showing a variation of threshold voltages of nonselected memory transistors within cell units associated with selected bit lines (shown by curve A) and threshold voltage variations of selected memory transistors which are associated with nonselected bit lines, and which must maintain erased data when the pass potential Vpass is increased (shown by curve B). The curves of FIG. 2 represent measured values where the coupling coefficient r is about 0.6, and where a programming potential Vpgm of 18 volts is applied after erasure such that threshold voltages of programmed memory transistors go to -3 volts.
As can be seen in the drawing, the dependencies of the two curves A and B on the pass potential Vpass are inversely related to each other. Therefore, the allowed range of the pass potential Vpass can determined, in which its influence on both the threshold voltages represented by curve A and the threshold voltages represented by curve B is acceptable. For example, assume that read operations for erased memory transistors are possible even if their threshold voltages increase up to -2 volts. In this case, the acceptable range of the pass potential Vpass is 9.5 to 12 volts, as can be seen in FIG. 2.
However, since the threshold voltages of memory transistors still vary with any pass potential Vpass within the above-mentioned range, data stored in nonselected memory transistors within cell units associated with data "0" programmed memory transistors or in selected memory transistors which must maintain erased data can still be changed. Specifically, where one memory transistor connected to a selected word line is to be programmed to data "0", the programming operation for this memory transistor must be repeated if it does not have a desired threshold voltage, for example, a threshold voltage of 1 volt, after the completion of a program verifying operation. In fact, the programming operation is performed repeatedly until it has the desired threshold voltage. This makes it more likely that the threshold voltages of nonselected memory transistors within the cell unit associated therewith, or that the threshold voltages of selected memory transistors which are connected to the same word line but which have to maintain erased data, can be changed to the extent that their data is inverted.
Erasure is conventionally performed for each row block. Thereafter, memory transistors connected to selected word lines within the row block are programmed. However, even memory transistors connected to word lines which do not need to be programmed, must be reprogrammed after they are erased. The reason why programming is not performed by each word line is as follows. Programming is performed for memory transistors connected to a selected word line after they have been erased. After programming, reprogramming is performed when any one of those memory transistors does not have the desired threshold voltage. Therefore, the programming potential and pass potential may be applied to both selected word lines and nonselected word lines repeatedly. Therefore, as discussed above, the threshold voltages of memory transistors on the selected word line which must maintain erased data are likely to be changed, and erroneous data may occur.
Furthermore, when the memory transistors are multi-state memory cells which store information having more than two bits, the difference between threshold voltages of successive states is very small. For example, when each memory transistor is a four-state memory cell storing four-bit information, the memory cell must maintain threshold voltages of, for example, -2 volts and -1 volts, representing the two-state information between the most and least significant bits, and, for example, a threshold voltage of -3 volts for the least significant bit and a threshold voltage of 0 volt for the most significant bit. Accordingly, the difference between the threshold voltages of successive states is only 1 volt. Although threshold voltage variations caused by the programming potential Vpgm and the pass potential Vpass can theoretically be controlled to less than a 0.5 volts during normal operations, in practice they must be substantially controlled to less than about 0.1 volts in consideration of various factors, such as process variations, circumferential temperature and so on. Therefore, as can be seen in FIG. 2, since there is no range of the pass potential Vpass in which the variation of threshold voltages is equal to or less than 0.1 volts, memory transistors within each cell unit can not be used as multi-state memory cells.