FIG. 1 illustrates one representative prior art linear regulator 10, which is a negative voltage regulator, although the invention applies equally to positive linear regulators. The term “linear regulator” is generally synonymous with a “low dropout (LDO) regulator.” The term “low dropout” refers to the small minimum voltage differential that can occur between the input voltage terminal and the regulated output voltage terminal while still achieving regulation.
LDO regulators operate by varying the conductivity of a pass (or series) transistor, connected between the input terminal and the output terminal, to achieve a predetermined output voltage. The output level of a transconductance amplifier, which is a type of differential amplifier, controls the conductivity of the pass transistor. The amplifier is referred to herein as an error amplifier. Typically, the regulator's output voltage is fed back into one input terminal of the error amplifier, and the conductivity of the pass transistor is controlled to match the output voltage to a reference voltage applied to the other input of the error amplifier. The user selects the reference voltage. Alternatively, a divided output voltage is fed back and matched to a fixed reference voltage, where the user selects resistors for the divider to achieve the desired output voltage. The invention applies equally to either type of feedback.
In FIG. 1, a fixed reference voltage Vref may be generated by the user connecting resistor (not shown) between a Set pin (not shown) of the regulator IC and ground to set the output voltage Vout provided at the Vout terminal 12. An on-chip current source (not shown) draws a fixed current through the resistor, and the voltage drop across the resistor is Vref.
A load (Rload) is typically connected between the Vout terminal 12 and ground. The input voltage Vin (a negative voltage in this example, usually Vee) is applied to the Vin terminal 14, so Vout will be somewhere between Vin (minus the dropout voltage) and ground. The reference voltage Vref is applied to the inverting input of the error amplifier 16. The output voltage Vout is applied to the non-inverting input of the error amplifier 16. The terms inverting and non-inverting simply refer to the two branches of the differential amplifier in the error amplifier 16.
The “error” output of the error amplifier 16 charges and discharges a capacitor Cea, connected to the output of the error amplifier 16 via a resistor Rea, to create a control voltage Vc. The control voltage Vc is that required to keep Vout equal to Vref at the inputs of the error amplifier 16. The values of Rea and Cea are optimized to ensure stability within the specified bandwidth of the regulator 10.
A driver 18 (a buffer) generates the required current to control the bipolar transistor Q1, which may be a high power transistor.
A relatively large output capacitor Cout is connected to the Vout terminal 12 to hold the output voltage steady during fast load transients, and the value of Cout is optimized to ensure stability under varying operating conditions, such as temperature, load current, etc.
Since the transistor Q1 may be large, its parasitic base capacitance Cb may be significant.
The circuit of FIG. 1 has three poles (Pole 1, Pole 2, and Pole 3), where a capacitance causes the voltage to lag the current by 90 degrees. Since the regulator 10 uses negative feedback (180 degrees out of phase), the feedback signal cannot be an additional 180 out of phase at the input of the error amplifier 16 while the feedback loop has a gain of unity, or else the negative feedback will turn into positive feedback and there will be instability. A good design rule is to have at least 45 degrees phase margin when the overall gain of the feedback loop crosses unity at the unity gain frequency (also referred to as the bandwidth frequency). The parasitic pole frequencies should occur well outside of the unity gain frequency.
FIG. 2 illustrates a simple one-pole circuit consisting of a resistor and a capacitor in series. Vin is applied between the ends of the resistor and the capacitor, and Vout is the voltage across the capacitor. The pole frequency is the frequency at which the impedance of the capacitor equals the value of the resistor, such that Vout equals Vin/2 (the −3 dB point). This is represented by the equation f=1/(2πRC).
One problem with the conventional regulator 10 is that the size of the output capacitor Cout is designed for worst case conditions that occur at the highest load current. At this high load current, transistor Q1 is generally highly conducting, causing the Pole 3 frequency to be relatively high, giving the feedback loop a good phase margin. Typically, the value of the capacitor Cout is selected to provide the desired phase margin (e.g., greater than 45 degrees) at the bandwidth frequency at the maximum specified load current. However, at lighter load currents, when transistor Q1 is lightly conducting, the Pole 3 frequency drops significantly, reducing the phase margin of the feedback loop, such as to below 45 degrees.
Given that the capacitors in the regulator 10 are optimized for the high load current, it would be beneficial to somehow offset the decreased Pole 3 frequency at the lighter load current to maintain approximately the same phase margin at both high and low load currents.