Voltage regulator circuits are often required to synchronize to an external clock signal. The primary reason for the synchronization is to prevent beat frequencies from existing within the voltage regulator. These beat frequencies can cause significant data corruption and cause circuitry to emit electromagnetic interference (EMI) at undesired frequencies. Complexity is added when the synchronizing input signal is not a clean clock signal and additional complexity is provided when the signal is applied after the voltage regulator has already been activated. The synchronization feature must be provided over the entire operating range of the voltage regulator. When the voltage regulator goes into and out of synchronization, this should not cause a disturbance to the voltage loop of the regulator. Additionally, the voltage regulator must be able to provide a phase delay with respect to the input clock signal to enable staggering of output switching, thereby reducing the effect of simultaneously switching phases in case of multi-phase operation.
The external clock signal provided for the voltage regulator, is frequently not a clean signal. Unfortunately, the majority of existing voltage regulators do not provide a good clock signal as a standard output. As a result, the least functional voltage regulator on a circuit board will frequently be used as the master clock by providing its LG signal for the remaining voltage regulators to synchronize with.
The range of operation of a voltage regulator is critical as customers will often operate from a very low frequency of approximately 200 KHz for high efficiency requirements up to 2 MHz for small size considerations. As a result, a phase locked loop (PLL) must operate successfully over this range. In extreme cases, a design may even be required to start out a 2 KHz and synchronize to a 2 MHz clock input.
Due to voltage sequencing requirements, it is often necessary for a voltage regulator to be enabled prior to the master clock signal being applied. An instantaneous change in frequency causes a voltage deviation on the output of the voltage regulator due to clock stretching or compression. Due to a potential change in the steady state operation point of the control loop, the voltage regulators PLL bandwidth is preferably sufficiently low such that no disturbances are seen on the voltage loop.
Synchronization provides multiple benefits to the voltage regulator such as reductions in the EMI and data corruption, and reduction of BOM cost from input capacitor savings. These benefits have spurred existing solutions which use analog PLLs to provide synchronization capability. Analog PLLs have significant difficulty with providing the above benefits due to the difficulty of synchronizing with noisy clocks, requiring large silicon areas to support large operating frequency ranges, adding phase delays to the system and transitioning from an initial frequency to another frequency. As a result of these challenges, customers are dissatisfied with existing analog PLL solutions and there exists a need for an improved solution.