A conventional example of a timing generation circuit, which is one type of logic circuit, is shown in FIG. 7. The timing generation circuit according to this conventional example is configured to have a level-shift circuit 101, and two flip-flops which are cascade-connected in sequence to the output thereof, that is, T-type flip-flops (hereinafter referred to as “TFFs”) 102 and 103 in this example. The level-shift circuit 101 level-shifts (level-converts) a master clock MCK of a low voltage amplitude, which is input externally, into a master clock lsmck of a high voltage amplitude. This master clock lsmck is supplied via a buffer 104 to a circuit which operates by using the master clock lsmck as a reference.
The TFF 102 generates a dot clock DCK by frequency-dividing the master clock lsmck. This dot clock DCK is supplied via a buffer 105 to a circuit which operates by using the dot clock DCK as a reference. The TFF 103 generates a horizontal clock HCK by further frequency-dividing the dot clock DCK. This horizontal clock HCK is supplied to a circuit which operates by using the horizontal clock HCK as a reference.
The TFFs 102 and 103 are reset in accordance with a reset pulse which is given externally, for example, at a 1H (H is a horizontal period) period. Here, wiring for transmitting the reset pulse to the TFFs 102 and 103 has a wiring capacity, a transistor input capacity, and a cross capacity with the other wiring. For this reason, a configuration is adopted in which the driving capability for a load capacity is increased by using a buffer 106 having a capability enough to drive such load capacities.
In the timing generation circuit having the above-mentioned configuration, in a case where each circuit part is formed by using transistors having large characteristic variations, the deviation of timings between each input clock pulse of the TFFs 102 and 103 and the reset pulse is likely to occur. When the deviation of timings becomes larger, problems arise in that a malfunction occurs, and the operation margin becomes smaller with respect to element characteristic variations.
Here, the circuit operation of the timing generation circuit having the above-mentioned configuration will be described with reference to the timing charts in FIGS. 8A and 8B.
During the normal operation, as shown in FIG. 8A, the TFFs 102 and 103 repeat the operation of their state being inverted in synchronization with the rise of the input clock pulse, thereby generating an output pulse whose period is twice as long as that of the input clock pulse. Furthermore, when a low-level reset pulse is given, the output pulse becomes a low level as a result of being reset at the timing of the fall thereof, and the output pulse shifts to a high level at the rise timing of the first input clock pulse after the reset pulse shifts to a high level. Thereafter, the TFFs 102 and 103 continue to generate the output pulse in synchronization with the input clock pulse over the period in which the next reset pulse is given.
On the other hand, during malfunction such as the relative timing relationship between the input clock pulse and the reset pulse being deviated due to element characteristic variations, for example, as shown in FIG. 8B, when the reset pulse which occurs in a period in which the input clock pulse is at a low level during the normal operation tap (FIG. 8A) occurs in a period in which the input clock pulse is at a high level, the reset operation is continued also after the rise timing of the next input clock pulse. Consequently, a malfunction of the polarity of the output pulse after the reset occurs.
The deviation of the relative timing relationship between the input clock pulse and the reset pulse occurs from the difference in the amount of delay between the circuits which generate these pulses, that is, the level-shift circuit 101 and the TFFs 102 and 103, and the buffer 107. In a case where these circuits are formed by using Thin-Film Transistors (TFTs) having large element characteristic variations and having a rough process rule (for example, 3.5 μm), the amount of delay is large, and, in particular, the difference is likely to occur.
The present invention has been made in view of the above-described problems. An object of the present invention is to provide a logic circuit capable of ensuring a large operation margin even when it is formed by using transistors having variations in characteristics and having a rough process rule, a timing generation circuit using the logic circuit, a display device using the timing generation circuit as one of peripheral driving circuits, and a portable terminal having incorporated therein the display device as a display output section.