Semiconductor chips or integrated circuits are typically used in combination with such elements as interposers and substrates facilitating connection between the chip itself and the external circuit elements. The entire circuit operation depends upon the connections between the chip, the interposer and the substrate.
Various attempts have been made to produce connections between the chip and the external elements satisfying the above discussed requirements. In this respect, U.S. Pat. No. 5,148,265, granted Sep. 15, 1992, the disclosure of which is hereby incorporated by reference, discloses an advanced method for providing the connection between a semiconductor chip and external circuit elements. According to certain embodiments discussed in this patent, a semiconductor chip is connected to a corresponding substrate through a dielectric interposer. The semiconductor chip has a plurality of peripheral contacts positioned in a peripheral area of a front surface thereof. The flat, flexible interposer is formed with a plurality of connecting terminals, each of which is connected to a bonding terminal adjacent the periphery of the interposer. The flexible interposer is supported by a compliant layer. The peripheral contacts of the semiconductor chip are connected to the terminals of the interposer by bonding a multiplicity of fine wires between the bonding terminals and the contacts of the chip.
During the wire bonding operation, when the downwardly directed forces are applied to the peripheral region of the interposer containing the bonding terminals this area of the interposer flexes downwardly. This impedes the bonding of the wires and the bonding terminals.
Thus, further improvement would be desirable.