1. Field of the Invention
The present invention relates to clock signal generating circuits and more particularly, to a clock signal generating circuit which can be suitably made in the form of a semiconductor integrated circuit and can operate with a small-amplitude signal having a high frequency, and also to a phase comparator and variable delay circuit which are used in the clock signal generating circuit.
2. Description of the Related Art
As a microprocessor or a semiconductor integrated circuit (LSI) including a semiconductor memory and so on is demanded to operate with a higher frequency, a system clock for synchronization between LSI chips or an internal clock for synchronization between circuits within the respective LSI chips has been increasingly required in recent years to have a higher frequency.
In order to synchronize such an external clock as a system clock supplied from an external LSI chip with such an internal clock for the internal circuits of the LSI chip, a phase locked loop (PLL) circuit is employed. The PLL circuit functions to control a frequency of an oscillator on the basis of a difference in phase between two frequencies. The operation of a prior art PLL circuit will be briefly explained with use of a block diagram of FIG. 1.
The illustrated PLL circuit includes an input circuit 1 for receiving an external clock signal Clkin, a phase comparator 10 for comparing the external clock signal with an internal clock signal with respect to their phase, a loop filter 8 for filtering a phase difference comparison voltage signal received from the phase comparator 10 to generate a control voltage signal, and a voltage controlled oscillator (which will be referred to merely as the VCO, hereinafter) 9 for controlling a frequency on the basis of the control voltage signal received from the loop filter 8. An internal clock signal generated by the voltage controlled oscillator 9 is applied to the phase comparator 10 as a signal PLL1.
In this case, the external clock signal Clkin received from an external clock signal input terminal 5 is first amplified by the input circuit 1 into such a signal as usable in the PLL circuit. The phase comparator 10 compares the amplified signal with the internal clock signal generated at the VCO 9 with respect to their phase and sends its comparison result to the VCO 9 via the loop filter 8.
In the phase comparison the signals Clkin and PLL1, if the signal Clkin is lagging the signal PLL1 with respect to phase, then the value of the control voltage signal generated by the loop filter 8 is increased to increase the frequency of the output signal of the VCO 9. If the signal PLL1 is leading the signal Clkin, then the frequency of the output signal of the VCO 9 is controllably decreased so as not to produce a phase shift between the signals Clkin and PLL1.
Further, a delay locked loop (DLL) circuit is used to synchronize the signal Clkin with a rising edge of the next clock delayed by one cycle. The DLL circuit, which operates in a similar manner to the PLL circuit, is provided with a delay line for delaying the input signal by just one cycle. That is, the DLL circuit is provided to provide a delay corresponding to one cycle of the synchronizing operation, and its allowable frequency range is limited.
In this way, the LSI chip is designed to correct the phase difference between the external and internal clocks with use of the PLL or DLL circuit to transmit an accurate signal. Meanwhile, as the operational frequency of the LSI is increased in these years, the amplitude of the signal has been decreased. Accordingly, when it is desired to use an external signal in an internal circuit, it becomes necessary for the input circuit 1 to perform its amplifying operation, which causes a processing delay in the input circuit 1. Further, even a signal passing through a wiring line connected from an input terminal to the input circuit will be delayed.
Furthermore, the operational speed of the LSI chip is influenced by the chip surrounding environment so that, for example, temperature or voltage value will cause the oscillation frequency of an oscillator to vary or the operation per se of the input circuit to be delayed.
It is therefore an object of the present invention to provide a clock signal generating circuit in an LSI chip operating at a high frequency, which can establish accurate synchronism between external and internal clocks to reduce a synchronization shift caused by an environmental change.
Another object of the present invention is to provide a clock signal generating circuit which set a delay in a variable delay circuit with use of a binary code to realize adjustment of a fine delay in an internal clock.
In accordance with an aspect of the present invention, the above objects are attained by a signal generation circuit which comprises an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal.
Since the signal generation circuit of the present invention is arranged as mentioned above, a phase difference between, e.g., external and internal clock signals can be compared without any intervention of the input circuit and thus the influences of delay caused by the input circuit can be eliminated.
Further, even for a signal having a high frequency and a small amplitude, its phase comparison can be carried out accurately.
The phase comparator usable in the above signal generation circuit includes differential input means including first transistors having an input clock signal applied to their gates and second transistors having a reference voltage signal applied to their gates for outputting a voltage indicative of a difference between the input clock signal and reference voltage signal; first switching transistors connected in series with the first transistors for receiving at their gates an internal clock signal for comparison with the input clock signal; and second switching transistors connected in series with the second switching transistors for receiving at their gates the internal clock signal.
In accordance with another aspect of the present invention, there is provided a signal generation circuit which comprises an input circuit for amplifying an input signal; a first variable delay circuit for delaying an output signal of the input circuit; a second variable delay circuit for delaying an output signal of the first variable delay circuit by one of first and second durations; a phase comparator circuit for finding a phase difference between the input signal and an output signal of the second variable delay circuit; and control means for controlling the second variable delay circuit to cause a delay time of the second variable delay circuit to switch between the first and second durations and also for controlling the first and second variable delay circuits to cause a phase of the input signal to always coincide with a phase of the output signal of the second variable delay circuit on the basis of an output of the phase comparator circuit.
The second variable delay circuit alternately switches between a zero delay and a one-period delay corresponding to one period of the input clock signal. Alternately applied to the phase comparator circuit are a clock signal subjected to a delay of one period by the first variable delay circuit and a clock signal delayed 2-periods by the first and second variable delay circuits. When the delay of the second variable delay circuit corresponds accurately to the zero delay or one-period delay, a shift in the input phase of the phase comparator circuit is caused only by the first variable delay circuit. For this reason, the delay of the second variable delay circuit is first set, the delay of the first variable delay circuit is controlled to adjust the phase, the delay of the second variable delay circuit is controllably set at the one-period delay to adjust the phase. The control means performs its controlling operation in such a manner that the phase of the input clock signal always coincides with the phase of the clock signal delayed one-period by the first variable delay circuit. Accordingly, even when a change in temperature, etc. causes a change of the delay of the second variable delay circuit, the delay of the second variable delay circuit is controlled to cause the above feedback loop to suppress the phase variation.
One of the variable delay circuits usable in the above signal generation circuit integrates a current supplied from a variable current supply circuit on the basis of an input clock signal to generate an output clock signal corresponding to a delay of the input clock signal; which variable delay circuit comprises a master transistor; and a group of slave transistor pairs connected in plural series including first and second slave transistors connected at their gates to the master transistor and at their sources and drains connected in series, first select transistors for complementarily short-circuiting the sources and drains of the first slave transistors, second select transistors for complementarily short-circuiting the sources and drains of the second slave transistors, for changing operational patterns of the first and second select transistor pairs to switch their output currents to thereby control a delay of the output clock signal.
In the variable delay circuit, the slave transistor pairs in the slave transistor pair group can be made associated with bits of a binary code for simply setting the delay.
Another one of the variable delay circuits usable in the above signal generation circuit comprises an integrated current control part and an integrating circuit part for integrating a current supplied from the integrated current control part on the basis of an input clock signal for generating an output clock signal corresponding to a delay of the input clock signal. In this case, the integrating circuit part includes driving transistors for receiving the current from the integrated current control part; capacitive means for storing therein electric charge by the driving transistors; and gate potential correcting means connected to gates of the driving transistors and having a capacitance corresponding substantially to one of capacities between gates and sources of the driving transistors and between gates and drains thereof, for changing a gate potential of the driving transistors in an opposite direction in response to a change in a potential at a junction point between the driving transistors and capacitive means.
Accordingly, even a small delay caused by the temperature of an LSI chip or by the internal circuit thereof can be cancelled and, in particular, in a high-speed integrated circuit, accurate synchronization can be established.