A similar rectifier arrangement is known from the book "SWITCHED CAPACITOR CIRCUITS" by P. E. Allen and E. Sanchez-Sinencio, Van Nostrand Reinhold Company, New York, 1984, pages 456 and 457.
The publication by Tietze, U.; Schenk, Ch.: Halbleiter-Schaltungstechnik, Berlin, Springer-Verlag, 5th edition 1980, pages 683 to 687, reveals a phase-sensitive rectifier. Phase-sensitive rectifiers can be understood to be amplifiers with variable amplification factor in which the sign of the amplification factor is not switched cogently with the polarity of the input voltage, but with an external control voltage. The use of a conventional analog multiplier as a phase-sensitive rectifier is also known from the aforementioned document.
A phase-sensitive rectifier is often used with a subsequent integrator, for instance in PLL circuits and demodulation circuits. Integrators with operational amplifiers, in which a capacitor is connected between the output and the inverting input of an operational amplifier and in which the signal to be integrated is supplied to the inverting input of the operational amplifier via a resistor are known from the aforementioned document, page 195. The time behaviour of such an integrator is determined by the time constant R.multidot.C of the resistance R of the resistor and the capacitance C of the capacitor.
When an arrangement consisting of a phase-sensitive rectifier and an integrator is to be realized in the form of an integrated circuit (IC), in particular as an IC with close tolerances as regards the time behaviour of the integrator, it is possible to make use of the switched capacitor (SC) technology. With this technology a resistor can be imitated by a switched capacitor.
An integrator in SC arrangement, hereinafter referred to as "switched capacitor integrator", is known from the document EP-A1-0 053 014 and depicted in attached FIG. 1. An operational amplifier OP has a capacitor C.sub.2 in the negative feedback branch. The inverting input of operational amplifier OP is connected via a CMOS semiconductor switch SW.sub.2 to a first terminal of a capacitor C.sub.1 whose second terminal has a reference potential applied thereto. The first terminal of capacitor C.sub.1 is connected furthermore to a signal source via a CMOS semiconductor switch SW.sub.1. CMOS semiconductor switch SW.sub.2 is driven by a first clock signal .phi.2. CMOS semiconductor switch SW.sub.1 is driven by a second clock signal .phi..sub.1 that is of opposite phase and non-overlapping with respect to .phi..sub.2. During operation of this arrangement, while semiconductor switch SW.sub.2 is open and semiconductor switch SW.sub.1 is closed, a charge determined by the signal voltage of the signal source is applied to capacitor C.sub.1. When semiconductor switch SW.sub.2 is closed and semiconductor switch SW is open, this charge is transferred to capacitor C.sub.2. The time behaviour of the switched capacitor integrator is determined by the ratio C.sub.2 /C.sub.1 of the capacitance of capacitor C.sub.2 and the capacitance of capacitor C.sub.1. Due to the fact that, in an integrated circuit, the ratio of two capacitances can be adjusted considerably more easily than an RC value, a switched capacitor integrator is particularly suited for implementation as an integrated circuit.
FIG. 2 shows a basic circuit diagram of a conventional phase-sensitive rectifier arrangement with integration effect. A similar rectifier arrangement, however with low-pass behaviour, is known from the aforementioned book "SWITCHED CAPACITOR CIRCUITS". The output of an analog multiplier MULT, whose first receives an input signal V.sub.in and whose second input receives a control signal T, is connected via a controllable switch means SW.sub.1 to a terminal of a capacitor C.sub.10. The second terminal of capacitor C.sub.10 is connected via a controllable switch means SW.sub.2 to the inverting input of an operational amplifier OP. Between the output and the inverting input of operational amplifier OP there is connected a capacitor C.sub.2. The first terminal and the second terminal, respectively, of capacitor C.sub.10 can be connected to a reference potential selectively via a controllable switch means SW.sub.3 and a switch means SW.sub.4, respectively. The operational cycle of the circuit comprises a first and a second half period. During the first half period the two switch means SW.sub.3 and SW.sub.4 are switched into their conducting state, while the switch means SW.sub.1 and SW.sub.2 are switched into their non-conducting state. Capacitor C.sub.10 is thus discharged. During the second half period the two switch means SW.sub.3 and SW.sub.4 are switched into their non-conducting state and switch means SW.sub.1 and SW.sub.2 are switched into their conducting state. A charge proportional to the output voltage of analog multiplier MULT is thus transferred to capacitor C.sub.2 and periodically integrated thereon. The capacitor C.sub.10 switched with the aid of switch means SW.sub.1 to SW.sub.4 then simulates an ohmic resistance.
The phase-sensitive rectifier arrangement according to FIG. 2 has the disadvantage that its realization requires many component parts. In case of very high time constants for the integrator, there is furthermore the problem that such high values are required for the capacitor ratio C.sub.2 /C.sub.10 that a circuit according to FIG. 2 can no longer be expediently realized as integrated circuit.