1. Technical Field
The invention relates to a semiconductor packaging technique and, more particularly, to a stack chip and a semiconductor package having the stack chip.
2. Description of the Related Art
Memory product development, for example DRAM development, has been focused on moving towards increased speed and capacity. One method for improving capacity is a chip stacking technique that may be used to stack semiconductor chips on a limited area of a package. The chip stacking may increase capacity of a product corresponding to the number of the semiconductor chips used.
In semiconductor packages manufactured by chip stacking, chip pads of semiconductor chips may be electrically connected to external connection terminals by, for example, wire bonding, a combination of wire bonding and flip chip bonding, or through electrodes.
Referring to FIGS. 1 and 2, a conventional dual die package 100 includes a wiring substrate 40 having an upper surface 41 and a lower surface 42, a lower semiconductor chip 12 having chip pads 14, and an upper semiconductor chip 22 having chip pads 24. The lower semiconductor chip 12 is mounted on the upper surface 41 of the wiring substrate 40. The upper semiconductor chip 22 is stacked on the lower semiconductor chip 12 with a spacer 37 interposed therebetween. Bonding wires 35 electrically connect the chip pads 14 and 24 of the semiconductor chips 12 and 22 to the wiring substrate 40. An encapsulant 50 seals the semiconductor chips 12 and 22 and the bonding wires 35. External connection terminals 60, for example solder balls, are formed on the lower surface 42 of the wiring substrate 40. The external connection terminals 60 are electrically connected to the chip pads 14 and 24 of the semiconductor chips 12 and 22.
Signals input through the external connection terminals 60 are transmitted to internal circuits 17 and 27 of the semiconductor chips 12 and 22 through the chip pads 14 and 24, and input/output buffers 16 and 26 of the semiconductor chips 12 and 22, respectively.
Compared to a semiconductor package having a single semiconductor chip (hereinafter referred to as a single die package), the dual die package 100 has double the number of semiconductor chips, but is provided with the same number of external connection terminals. Typically, input capacitive loading may increase corresponding to the number of semiconductor chips within a chip stack. Double input capacitive loading of the dual die package 100 may cause reduced speed of the package 100. Particularly, input capacitive loading may relate to the number of input/output buffers 16 and 26 configured to connect the chip pads 14 and 24 to the internal circuits 17 and 27. In the dual die package 100, each of the external connection terminals 60 may be connected to two input/output buffers 16 and 26 in parallel. As a result, input capacitive loading of the dual die package 100 may increase, thereby reducing the speed of the package 100. The increased input capacitive loading may reduce the valid window size of data at the channel and/or system level. Therefore, reduction of signal integrity may prevent high speed operation of the semiconductor package and/or the system.
Consequently, a dual die package with reduced capacitive loading is desired so that high speed operation can still be achieved when capacity is increased.