Static timing analysis (STA) is used for validating timing performance of an integrated circuit design. During static timing analysis, delays along the respective paths between each respective start point and end point (e.g., pair of flip-flops, paths to/from SRAM or other macro) is checked under corner conditions. For a given path, the delay analysis takes into account the combinatorial logic along the path, and the parasitic capacitive couplings between the conductive lines in the interconnect layers of the IC. The STA determines whether the correct data are present at the data input of each flip-flop when the clock signal input to that flip-flop changes. The STA includes both setup time analysis and hold time analysis.
To correctly capture data, the data should be held steady at the data input of the capture flip-flop for at least a “setup time” (TSU) before the clock signal transition at the clock input to the capture flip-flop. Verifying compliance with this condition is called setup time analysis. Failure to satisfy this condition results in a setup time violation.
In addition, the data should be held steady at the data input of the capture flip-flop for at least a hold time (THD) after the clock signal transition at the clock input to the capture flip-flop. Verifying compliance with this condition is called hold time analysis. Failure to satisfy this condition results in a hold time violation.
STA allows a rapid check of the timing of every path.