Modern memory devices comprise a memory array with a plurality of memory cells via corresponding column selects, bitlines and wordlines. Various operations can be performed on each individual cell by applying a pulse to the cells via the bitlines, such as a SET pulse, a RESET pulse, or a READ pulse. The READ pulse allows the current value stored in a memory cell to be read. Generally, sense amplifiers are used to perform the READ operation to determine the value of the cell.
For resistive memory, a memory cell can be in a low resistive state (LRS) or a high resistive state (HRS). A sense amplifier is an analog to digital converter that compares a current from the memory cell to a reference current to determine whether a cell is in LRS or HRS. For some memory types, resistive memories in particular, cell current is strongly dependent on the bitline voltage which must be precisely controlled. Conventionally, sense amplifiers are composed of a cascode transistor pair coupled to a reference circuit and coupled to a current mirror, with a comparator to determine whether the current across the current mirror has changed as compared to the reference current. The cascode transistor pair is used to precisely control the voltage of a bitline to sense the memory cell current.
Generally, the cascode transistors which are used in memory devices are thick oxide transistors to support a high voltage power supply (e.g., 5V). However, higher voltages at the bitlines can cause damage to the memory cells in the array and may also increase the time it takes for a bitline to charge. Additionally, thick oxide transistors have poor matching characteristics (e.g., random threshold voltage mismatches) because of their sensitivity to dopant atom fluctuation. Accordingly, it is difficult to use thick oxide transistors as cascode transistors in a sense amplifier.
Therefore, there is a need in the art for a memory device comprising double cascode sense amplifiers.