The invention relates to a process for the fabrication of a field-effect transistor comprising a semiconductor substrate with a drain region, a source region and a gate electrode for influencing a channel region. The source region and the gate electrode are so arranged in superimposed relation to each other in a projection onto the channel plane that the effective channel length becomes so small that an increase in the electron velocity in the channel is attained. Such a field-effect transistor is described in the older German Patent Application No. P 35 35 002.4, corresponding to U.S. application Ser. No. 06/914,540. In this field-effect transistor it is, above all, a question of substantially improving the high frequency characteristics, the limiting frequency and the noise behaviour of the field-effect transistor by a reduction in the effective gate length. In this case, the fact that extremely short channel lengths result in a strong increase in the saturation velocity of the electrons in the active channel is exploited. This interrelation is described in the older Patent Application.
The channel length in the aforementioned field-effect transistor is, therefore, preferably below 0.5 .mu.m. The desired value of the channel length is solely dependent on the alignment accuracy of the technology employed, with this alignment accuracy being &lt;0.1 .mu.m. The very small effective channel lengths are attained by the gate electrode slightly overlapping the source region in the projection onto the channel plane in the direction of the drain region. It is also possible for the edge of the gate electrode that faces the drain region to coincide in the projection onto the channel plane with the outer edge of the source region that faces the drain region. In this case, the extension of the space-charge zone from the edge of the source region in the direction of the drain region is exploited.