Hard-wired logic binary frequency dividers offer the advantage of being simple in structure, inexpensive to implement and occupying a low surface area of silicon. This simplicity is offset by the fact that they have various limitations. In particular, the period of the output signal they supply can only be incremented by a constant value equal to the period of the input signal that is applied thereto. Similarly, the duty cycle of the output signal is not totally constant and varies according to the value of a division setpoint that is applied thereto.
This will be better understood with reference to FIG. 1A that represents the classic structure of a binary frequency divider DIVF1. The divider is arranged here for supplying an output signal having a duty cycle of 0.5 and operates with 4 bits. It comprises a binary counter CMPT, a divider DIV2, two synchronous comparators CP1, CP2 and an RS-type asynchronous flip-flop RS1. The counter CMPT is paced by an input signal CK0 of frequency F0 and supplies a counting value VAL that is incremented upon each rising edge of the signal CK0. The counting value VAL is applied to an input of each comparator CP1, CP2. The comparator CP1 receives a threshold value REF1 at a second input and the comparator CP2 receives a threshold value REF2 at a second input. The threshold value REF1 is equal to B1/2 and is supplied by the divider DIV2 using the setpoint B1. The threshold value REF2 is equal to the setpoint B1.
As represented in FIG. 1B, the divider DIV2 is an asynchronous shift circuit that performs a division by 2 of the setpoint B1 by performing a right shift of the bits b3, b2, b1, b0 of the setpoint without any carry after the decimal point, such that the rounding error on the threshold value REF1 is equal to 1 for an odd figure and is equal to 0 for an even figure.
The comparator CP1 supplies a control signal DET1 synchronized with the falling edges of the signal CK0 and the comparator CP2 supplies a control signal DET2 also synchronized with the falling edges of the signal CK0. The signal DET1 is applied to the R input of the flip-flop RS1 (reset input for resetting to 0) and the signal DET2 applied to the S input of the flip-flop RS1 (set input for setting to 1). The signal DET2 is applied to an input IN1 of the counter CMPT as a reset signal for resetting the counter to 1. The output signal CK2, of frequency F2=F0/B1, is supplied by a Q output of the flip-flop RS1.
FIG. 2 represents the shape of the signals CK2, DET1, DET2 and the counting value VAL according to the input signal, for a setpoint B1 equal to 8 (i.e., 1,000 in binary). The signal CK2 changes to 0 when the control signal DET1 changes to 1 and changes to 1 when the control signal DET2 changes to 1, in synchronization with the falling edges of the signal CK0, while the resetting to 1 of the counting value occurs on the rising edge of the signal CK0, like its incrementation.
Due to the rounding error on the binary division, the duty cycle of the output signal CK2 is exactly equal to 0.5 for an even value of the setpoint B (example represented) but is shifted by a period T0 of the signal CK0 (T0=1/F0) for the odd values of the setpoint. Indeed, the division by 2 of an odd value without any carry after the decimal point gives the same result as the division by 2 of the previous even value. For example, the division of 4 (0100) gives 2 (0010) and the division of 5 (0101) also gives 2 (0010) since the least significant bit of the setpoint is removed by the right shift. The precision of the duty cycle therefore varies according to the period T0 of the input signal CK0 and to the division setpoint. The higher the division setpoint is, the lower the error on the duty cycle.
Furthermore, the step of the period T2 of the output signal CK2 (minimal increment) is equal to the period T0 of the input signal. Indeed if the setpoint B1 changes from a value B to a value B+1, the period T2 of the output signal CK2 changes from B*T0 to (B+1)*T0, i.e., B*T0+T0. The corresponding frequency step, equal to F0/B2+B, also depends on the input frequency F0 although not linear and varying according to the value B of the setpoint B1.
Given that the current consumption of such a divider increases in proportion to the input frequency F0, it is desirable, in practice, to choose a frequency F0 that is as low as possible for an output frequency F2 that is generally determined by specifications.
Thus, generally speaking, the minimal frequency F0 to be applied to the input of the divider is determined according to the characteristics of the output signal CK2.
For example, within the scope of the production of a passive-type RFID contactless integrated circuit conforming to the EPC™-GEN2 (“Radio-Frequency Identity Protocols Class-1 Generation-2—UHF RFID Protocol for Communications at 860 MHz-960 MHz”) industrial specification, the present inventors were confronted with the need to provide a frequency divider circuit supplying an output signal CK2 having a duty cycle between 0.4 and 0.6, the period of which can be adjusted by steps of 200 ns and having a minimal period T2 of 1.2 microseconds.
A step of 200 ns for the period of the output signal thus imposes a period T0 of the input signal of 200 ns, i.e., an input frequency F0 of 5 MHz (1/T0). The minimal period T2 of 1.2 microseconds corresponds to a frequency F2 of 833 KHz and imposes a division setpoint equal to 6. With a minimal division setpoint equal to 6, the maximal error on the duty cycle, for the odd value setpoint the closest to 6, e.g, 7, is of a half-period of the input signal over seven periods in total, e.g, a 7% error within the tolerance range defined by the specifications.
However, an input frequency F0 of 5 MHz is a very high frequency implying considerable current consumption, little compatible with an application to a passive transponder that is electrically powered using an ambient electric field sent by a contactless integrated circuit reader.