1. Field of the Invention
The present invention relates to an A/D conversion circuit and a test method.
2. Description of Related Art
In recent years, semiconductor integrated circuits have been mounted on control systems of automobiles, and the semiconductor integrated circuits are required to endure the harsh environment. In accordance with this, it is strongly demanded to test the semiconductor integrated circuits with higher level than before and to enhance the reliability of the semiconductor integrated circuits.
In order to control motors with high output and high performance such as EPS, HEV with high accuracy, it is required to sample currents (U phase, V phase, W phase) flowing in a motor control circuit to perform feedback control.
Japanese Unexamined Patent Application Publication No. 2004-328913 discloses a circuit that holds voltages according to current values of U phase, V phase, W phase by sample hold circuits and transmits each of the sample hold voltages to a control processor. When the sampling cannot be performed appropriately, an error voltage is supplied to the sample hold circuit from an error voltage source (see paragraph 0018 of Japanese Unexamined Patent Application Publication No. 2004-328913).
Japanese Unexamined Patent Application Publication No. 2007-309773 discloses a technique of reducing overhead of a diagnostic circuit when diagnosing a failure of an A/D (Analog/Digital) converter of an analog input section to an LSI or a failure of a multi-input multiplexer and malfunctions such as a break, a power supply short circuit, a ground short circuit in various kinds of sensors on a mother board of an application system. Japanese Unexamined Patent Application Publication No. 2007-309773 shows in FIG. 11 a semiconductor integrated circuit including an impedance converter (OP_Amp0, for example) and a diagnostic circuit (BIDT Cirt0, for example) in each of eight-channel analog input terminal of a multiplexer MPX.
Japanese Unexamined Patent Application Publication No. 2007-6512 discloses a fault detector of an A/D converter. Japanese Unexamined Patent Application Publication No. 2007-6512 discloses a technique of comparing an A/D converted value with an ideal value, and judging that there is a failure in the A/D converter when the difference between the both values exceeds a predetermined value.
Japanese Unexamined Patent Application Publication No. 8-56160 discloses an abnormality detector of an A/D converter. Japanese Unexamined Patent Application Publication No. 8-56160 discloses a technique of selectively supplying a first reference voltage or a second reference voltage to an A/D converter, making comparison between each of the A/D converted values with a predetermined normal output value of the A/D converter, and judging that the A/D converter is abnormal when either of them is unequal.