Processes for fabricating wafers of integrated circuits include a series of steps by which a set of geometric patterns is transformed onto the wafers. For example, a process for fabricating integrated circuits of MOS (metal-oxide-semiconductor) FET (field-effect transistors) include a series of steps for transforming geometric patterns determined by the transistors and their interconnections onto a number of superimposed layers of semiconductor, insulating, and conducting materials on a substrate. MOS transistors are semiconductor switching devices where a voltage on a gate controls a channel of conduction current from a drain to a source region of the transistors. One characteristic of the MOS transistors is the Vt (threshold voltage) which is the minimum voltage applied to the gate with respect to the substrate that would allow the conduction channel between the drain and the source to form. Since the Vt determines the gate voltage for turning the MOS transistors on or off, it has to be determined and carefully controlled through the fabrication process.
However, as the MOS transistors are scaled down to form integrated circuits with higher level of integration and faster speed, physical phenomena due to the small size of the transistors impinge on performance characteristics of the transistors. For example, the channel length between the drain and the source regions and the drain-to-source current flowing through the channel should ideally remain constant (saturation current) when the voltage on the drain (Vd) exceeds a pinch-off voltage. However, short channel effects caused by the small transistor size may expand a depletion region at the drain beyond the pinch-off voltage. The spreading depletion region causes the effective channel length to decrease. As a result, the saturation current keeps increasing beyond pinch-off. In the extreme case, current carriers may “punch through” between the drain and source, causing the gate voltage to lose its ability to control the conduction channel.
Various strategies including the introduction of implant gradients or highly doped pockets of dopants in the well implant (pocket or halo implants) are used to mitigate the short channel effects. However, pocket implants may suffer from “shadowing effects” caused by the close proximity of the polysilicon (poly) layers on the gates of adjacent transistors during the implantation step. Shadowing effects reduce the effectiveness of the pocket implants in mitigating the short channel effects. Other strategies to combat short channel effects include implanting a heavy doping concentration in the well to introduce a retrograde well profile. However, the high thermal budget required to form the gate oxide layer after well implant may result in an out-diffusion of the well dopants and a degraded retrograde well profile may result. In addition, the short channel length, the heavy doping concentration of the well implant, and the high thermal budget for oxide layer formation all tend to increase fluctuations in Vt, making Vt more difficult to control. The short channel effects and the variance in Vt are exacerbated as the gate geometry shrinks to the deep-submicron scale, reducing yields of the next generation technology nodes such as the 22 nm node and beyond. Accordingly, there is a need for a fabrication process that mitigates the short channel effects, decreases the variance in Vt, prevents the shadowing effects during pocket implant, reduces the out-diffusion of well dopants, and yields a better retrograde well profile.