The present invention relates to an information processing control system, and more particularly, relates to assisting a system required to achieve real time processing while swapping instructions stored in a cache memory.
FIG. 15 shows a configuration of an information processing control system using a general cache memory. This system includes: a main memory 400H for storing all instructions of a program; a cache memory 401H for storing only necessary instructions; a cache controller 402H for controlling the main memory and the cache memory; and a processor 403H for executing instructions stored in the cache memory.
In the information processing control system described above, when a necessary instruction exists in the cache memory 401H, the processor 403H decrypts (i.e., decodes) and executes the instruction stored in the cache memory 401H. When a necessary information does not exist in the cache memory 401H, a miss-hit (which is also known as a cache miss) occurs, and the processor 403H is halted, or polling (waiting) is performed with a kernel program. During this halt or polling, the cache controller 402H transfers a necessary instruction from the main memory 400H to the cache memory 401H. Once the instruction is available in the cache memory 401H, the processor 403H restarts the execution from the instruction at which the miss-hit has occurred.
FIG. 16 shows a flow of programs followed when a program is executed while instructions stored in the cache memory are swapped in the information processing control system described above (see David A. Patterson/John L. Hennessy, “Computer Organization and Design”, for example). In FIG. 16, the reference numeral 420 denotes a time flow, 421 denotes processing of a kernel program, and 422 denotes processing of an application program. The reference numeral 423 denotes a program flow alternating between the kernel program and the application program, 424 denotes start of downloading (which may be also be known as pre-fetching) of a necessary instruction from the main memory to the cache memory, and 425 denotes a miss hit interrupt occurring when a necessary instruction does not exist in the cache memory. Times 420t, 423t and 426t denote times at which the program processing shifts from the kernel program to the application program, times 421t and 424t denote times at which the program processing shifts from the application program to the kernel program, and times 422t and 425t denote times at which downloading of a necessary instruction from the main memory to the cache memory is started.
The program flow 423 alternating between the kernel program and the application program will be described. The program processing, started with the kernel program, shifts to the application program at time 420t. The application program is then executed until a miss hit interrupt 425 occurs. When the miss hit interrupt 425 occurs at time 421t, the program processing shifts from the application program to the kernel program. At time is 422t, at which polling with the kernel program is underway, downloading of a necessary instruction from the main memory to the cache memory is started. When the downloading is completed at time 423t, the processing shifts from the kernel program to the application program, and the application program is restarted from the instruction at which (421t) the miss hit interrupt 425 has occurred. It is noted that polling may be done with the kernel program, or execution may be halted with the application program, during the time period from the occurrence of the miss hit interrupt 425 until the completion of the downloading.
FIG. 17 shows an internal configuration of the cache controller 402H of the information processing control system described above (see Non-Patent Literature 1, for example). In FIG. 17, the reference numeral 440 denotes a cache table register showing the correspondence between the logical address in a program and the physical address.
The reference numeral 442 denotes a tag address, 443 denotes a physical address, and 441 denotes a valid flag indicating whether the correspondence between the tag address 442 and the physical address 443 is valid or invalid. The reference numeral 444 denotes the higher-order part of a logical address in a program, and 445 denotes the lower-order part of the logical address in a program. The reference numeral 446 denotes the higher-order part of a cache address, and 447 denotes the lower-order part of the cache address, which is the same as the lower-order part 445 of the logical address. The reference numeral 449 denotes a comparator circuit, and 450 denotes a miss hit flag with which a miss hit interrupt occurs.
The operation of the circuit described above is as follows. If the higher-order part 444 of the logical address in a program and the tag address 442 are found identical to each other by comparison with the comparator circuit 449 and also the valid flag 441 is valid, the higher-order part of the physical address 443 is sent to the cache memory 401H as the higher-order part 446 of the cache address, together with the lower-order part 445 of the logical address in the program as the lower-order part 447 of the cache address. If there is no item in the cache table register 440 satisfying that the higher-order part 444 of the logical address in a program and the tag address 442 are found identical to each other by comparison with the comparator circuit 449 and also the valid flag 441 is valid, the miss hit flag 450 goes active, causing occurrence of a miss hit interrupt.
The conventional information processing control system described above has problems as follows. In the conventional information processing control system, when an instruction necessary for execution of a program does not exist in the cache memory, a miss hit occurs and the application program is halted until the necessary instruction is downloaded into the cache memory. This halt situation occurs frequently, and for this reason, the system fails to guarantee real time processing while swapping instructions.
The conventional information processing control system is not provided with such a mechanism that when a miss hit occurs in a certain application program, another application program is started, and during execution of the latter application program, an instruction necessary for execution of the former application program in which the miss hit has occurred is downloaded from the main memory to the cache memory. Therefore, the serviceability of the processor decreases.
In the conventional information processing control system, the cache table register does not include flags indicating the status of DMA for downloading and the miss hit status. Therefore, it is not possible to construct an information processing control system that achieves real time processing while swapping instructions by downloading a necessary instruction in advance from the main memory to the cache memory before the processor executes the instruction and also switching an application program to another one once a miss hit interrupt occurs.
In the conventional information processing control system, only the valid flag is used as the flag indicating completion of DMA for downloading of an instruction. Therefore, an interrupt occurs every time DMA is completed. Since the program is switched at occurrence of an interrupt, a loss due to this switching arises frequently. This decreases the processing efficiency of the processor.