(a) Field of the Invention
The present invention relates to a wiring board and a method of manufacturing the same. More specifically, the invention relates to a wiring board having a structure in which terminals (pads) for mounting a semiconductor element (chip) or the like or for external connection are exposed from an outermost insulating layer, and also to a method of manufacturing the same.
The wiring board is also referred to as a “semiconductor package” in the description below, for the sake of convenience, because the wiring board has the role as a package for mounting a semiconductor element (chip) or the like thereon.
(b) Description of the Related Art
In a trend to make semiconductor devices smaller (thinner) in size and higher in performance (higher in functionality), there is a demand for package-on-package (POP) bonding for the purpose of reducing the mounting area of a semiconductor device in which electronic components such as semiconductor chips are mounted on wiring boards (in semiconductor packages). In the POP bonding, packages each including a semiconductor chip or the like mounted thereon are stacked in the vertical direction (height direction) thereof.
As a method of implementing the POP bonding, there is a method in which upper and lower packages are bonded to each other with an interposer placed between the packages. With this method, a semiconductor device is formed with a structure in which: a semiconductor chip is flip-chip bonded to the lower package (wiring board); terminals (pads) of the lower package are formed at a peripheral region around the chip on the lower package; terminals (pads) of an upper package (wiring board) are formed on the mounting surface side of the upper package at a region corresponding to the peripheral region; and the terminals of the lower and upper packages are bonded to each other via external terminals formed on both surfaces of an interposer having a thickness larger than the thickness of the chip (inclusive of the electrode terminals thereof).
In this bonding method, a process for fabricating an interposer is additionally required. The typical process for the fabrication includes the steps of: preparing a core member; forming through holes at required positions; filling the through holes with a conductor; forming resist layers on both surfaces; forming a wiring layer in a required pattern in connection with the conductor; removing the resist layer; forming an insulating layer (solder resist layer) through which external terminal formation portions of the wiring layer is exposed; and performing a required plating (nickel/gold plating or the like) on the external terminal formation portions.
In addition, as another method of implementing the above POP bonding, there is a method in which terminals (pads) of upper and lower packages are bonded to each other by use of solder. With this method, a semiconductor device is formed with a structure in which: a semiconductor chip is flip-chip bonded to the lower package (wiring board); and terminals (pads) formed at a peripheral region around the chip on the lower package are bonded via solder bumps to terminals (pads) formed on the mounting surface side of the upper package (wiring board) at a region corresponding to the peripheral region on the lower package.
An example of the techniques related to the above conventional art is described in Japanese unexamined Patent Publication (JPP) (Kokai) 2006-196860. This publication discloses a semiconductor package having: a board formed of a plurality of insulating resin layers; terminals for mounting a semiconductor element, which are formed on one of the surfaces of this board; and external connection terminals formed on the other surface of this board. In this package, each of the external connection terminals is formed as a bump protruding from the surface of the package. The inside of the bump is filled with insulating resin, and the surface of the bump is covered by metal. Moreover, each terminal for mounting a semiconductor element and corresponding pieces of metal are connected to each other through wiring including a conductive via.
As described above, in the conventional art, bonding by use of an interposer or solder is performed for implementing POP bonding. However, in the case where an interposer is used for bonding, a process (considerable manufacturing steps) for fabricating the interposer is additionally required, and a material for fabricating the interposer is required as well. Accordingly, there arises a problem in that manufacturing costs increase.
Meanwhile, in the case where solder is used for bonding, the gap between the upper and lower packages is large because of the presence of the chip mounted between the packages. Accordingly, a large amount of solder (bump) is used for bonding the packages together. In this case, there are inconveniences such as separation of the bump (separation of the solder) during reflow soldering, and formation of a bridge between adjacent bumps. This produces a problem in that the reliability of bonding between the upper and lower packages is lowered.