As semiconductor devices scale to smaller dimensions, the ability to avoid defects in device structures becomes more challenging. For example, the synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), involves many deposition and etch operations to define a gate structure and source/drain (S/D) region of a transistor. One useful feature is to generate a smaller active fin width (CD), for the purposes of improving device performance. In some applications, a target fin width of 5 nm may not be readily achievable, since the fins may not be structurally stable at such narrow dimensions, especially for high aspect ratios, such as 10/1, 20/1, and so forth. Accordingly, commercial device applications may employ wider fins, such as 10 nm, where problems such as inadequate sub-fin leakage control may be evident for narrower fins. Another approach to reduce sub-fin leakage current on devices, such as N-type FETs (NFETS) is to increase the oxide thickness along the sidewalls of fins. Thicker oxide may reduce spacing between adjacent fins, leading to gap fill problems for oxide formed between fins, including void formation and active fin height variation. The use of thinner oxide layers along fins allows better oxide gapfill, and better active fin height control, while leading to higher sub-fin leakage current, particularly for NFET devices. Moreover, known finFET device processing schemes may lead to additional recess of gap fill oxide when the oxide liners are removed, leading to active fin height variation.
With respect to these and other considerations, the present disclosure is provided.