1. Field of the Invention
The present invention relates to a floating-gate MOS transistor for producing an EEPROM-type electrically erasable and programmable memory cell.
2. Description of the Related Art
EEPROM memory cells are classically produced by means of floating-gate transistors comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate having a determined gate length.
In a classical EEPROM memory array architecture, the drain of the floating-gate transistor of the memory cell is generally linked to a bit line through an access transistor that is driven by a word line, whereas the control gate of the floating-gate transistor is generally linked to a gate control line through a gate control transistor.
One disadvantage of classical EEPROM memory cells and the corresponding architectures of EEPROM memory arrays thus lies in the presence of the access transistor. This transistor is difficult to miniaturize and limits the endurance of the memory cells, the malfunctioning the most frequently encountered being due to access transistor breakdowns.