1. Field of the Invention
This invention relates to a cascade A/D converter used for a digital measuring device such as a digital oscilloscope.
2. Description of the Related Art
In a conventional cascade A/D converter, fundamental constituent elements ADA are cascaded in plural stages, the fundamental constituent elements ADA having comparators (10a to 10f), which are first comparators for converting an analog input signal AIN to digital signals (D7 to D0), D/A converters (20a to 20f) for converting outputs (B7 to B2) of the comparators (10a to 10f) to analog signals again, and subtractors (30a to 30f) for subtracting outputs of the D/A converters (20a to 20f) from the analog input signal AIN (see, for example, Patent Document 1).
FIG. 1 is a structural view showing the conventional cascade A/D converter.
In FIG. 1, a non-inverting input of the comparator 10a is connected to the analog input signal AIN, and an inverting input of the comparator 10a is connected to a comparative voltage 0. The output B7 of the comparator 10a is connected to an error correcting circuit 110.
An input of the D/A converter 20a is connected to the output B7 of the comparator 10a. 
Moreover, an addition input of the subtractor 30a is connected to the analog input signal AIN, and a subtraction input of the subtractor 30a is connected to the output of the D/A converter 20a. 
At a comparator 9a, its non-inverting input is connected to the analog input signal AIN, and its inverting input is connected to a voltage −1LSB having polarity opposite to the polarity of a voltage corresponding to the least significant bit LSB.
Moreover, at a comparator 11a, its non-inverting input is connected to a voltage +1LSB corresponding to the least significant bit LSB, and its inverting input is connected to the analog input signal AIN.
At an AND circuit 60a, its input is connected to the output of the comparator 9a and the output of the comparator 11a, and its output W7 is connected to the error correcting circuit 110. The comparator 9a, the comparator 11a and the AND circuit 60a form a window comparator 70a. 
The comparator 10a, the D/A converter 20a, the subtractor 30a and the window comparator 70a form the first fundamental constituent element ADA.
Similarly, a non-inverting input of the comparator 10b is connected to an output A1 of the subtractor 30a, and an inverting input of the comparator 10b is connected to a comparative voltage 0. The output B6 of the comparator 10b is connected to the error correcting circuit 110.
An input of the D/A converter 20b is connected to the output B6 of the comparator 10b. 
Moreover, an addition input of the subtractor 30b is connected to the output A1 of the subtractor 30a, and a subtraction input of the subtractor 30b is connected to the output of the D/A converter 20b. 
At a comparator 9b, its non-inverting input is connected to the output A1 of the subtractor 30a, and its inverting input is connected to the voltage −1LSB.
Moreover, at comparator 11b, its non-inverting input is connected to the voltage +1LSB, and its inverting input is connected to the output A1 of the subtractor 30a. 
At an AND circuit 60b, its input is connected to the output of the comparator 9b, the output of the comparator 11b and an inverted version of the output W7, and its output W6 is connected to the error correcting circuit 110. The comparator 9b, the comparator 11b and the AND circuit 60b form a window comparator 70b. 
The comparator 10b, the D/A converter 20b, the subtractor 30b and the window comparator 70b form the second fundamental constituent elements ADA.
The first fundamental constituent element ADA and the second fundamental constituent element ADA are cascaded with each other.
Similarly, the first fundamental constituent element ADA, the second fundamental constituent element ADA, the third fundamental constituent element ADA formed by the comparator 10c, the D/A converter 20c, the subtractor 30c and a window comparator 70c, the fourth fundamental constituent element ADA formed by the comparator 10d, the D/A converter 20d, the subtractor 30d and a window comparator 70d, the fifth fundamental constituent element ADA formed by the comparator 10e, the D/A converter 20e, the subtractor 30e and a window comparator 70e, and the sixth fundamental constituent element ADA formed by the comparator 10f, the D/A converter 20f, the subtractor 30f and a window comparator 70f, are cascaded.
That is, in the conventional example of FIG. 1, the fundamental constituent elements are cascaded in six stages.
A non-inverting input of the comparator 10g is connected to an output A6 of the subtractor 30f, and an inverting input of the comparator 10g is connected to the comparative voltage 0. An output B1 of the comparator 10g is connected to the error correcting circuit 110.
At a comparator 9g, its non-inverting input is connected to the output A6 of the subtractor 30f, and its inverting input is connected of the voltage −1LSB.
Moreover, at a comparator 11g, its non-inverting input is connected to the voltage +1LSB, and its inverting input is connected to the output A6 of the subtractor 30f. 
At an AND circuit 60g, its input is connected to the output of the comparator 9g, the output of the comparator 11g, an inverted version of the output W7, an inverted version of the output W6, an inverted version of the output W5, an inverted version of the output W4, an inverted version of the output W3 and an inverted version of the output W2. Its output W1 is connected to the error correcting circuit 110.
The comparator 9g, the comparator 11g and the AND circuit 60g form a window comparator 70g. 
The error correcting circuit 110 performs calculations based on the following logical expressions (1) to (8) and outputs digital signals D7 (most significant bit MSB) to D0 (least significant bit LSB). That is, in the conventional example of FIG. 1, digital signals (D7 to D0) of an 8-bit gray code are outputted.D7=B7  (1)D6=(B7 xor B6) or W7  (2)D5={(B6 xor B5) or W6} and not (W7)  (3)D4={(B5 xor B4) or W5} and not (W7) and not (W6)  (4)D3={(B4 xor B3) or W4} and not (W7) and not (W6) and not (W5)  (5)D2={(B3 xor B2) or W3} and not (W7) and not (W6) and not (W5) and not (W4)  (6)D1={(B2 xor B1) or W2} and not (W7) and not (W6) and not (W5) and not (W4) and not (W3)  (7)D0=W1  (8)
The operation in the conventional example of FIG. 1 having the above-described structure will now be described.
The comparator 10a compares the analog input signal AIN with the comparative voltage 0 and converts (A/D conversion) the analog input signal AIN to a digital signal with respect to the digital signal D7 (most significant bit MSB).
The D/A converter 20a converts the 1-bit output of the comparator 10a to an analog signal again. The subtractor 30a subtracts the output of the D/A converter 20a from the analog input signal AIN.
Similarly, the comparator 10b compares the output A1 of the subtractor 30a with the comparative voltage 0 and converts (A/D conversion) the analog output A1 to a digital signal. Since the output A1 is the result of subtracting the output of D/A converter 20a from the analog input signal AIN, the comparator 10b performs A/D conversion of the second bit from the most significant bit MSB with respect to the digital signal D6.
Similarly, in the conventional example of FIG. 1, A/D conversion of each bit is performed sequentially.
In this manner, in the conventional example of FIG. 1, digital signals (D7 to D0) of 8-bit gray codes are outputted.
The window comparators (70a to 70g) generate mask signals to restrain occurrence of an error at a transition point from 0 to 1 and a transition point from 1 to 0 in the comparators (10a to 10g).
Patent Document 1: JP-A-9-238077
However, the conventional example of FIG. 1 has a problem that settling takes a long time because of the many stages of fundamental constituent elements ADA. Therefore, the conventional example of FIG. 1 has a difficulty in achievement of high-speed operation.