This invention relates generally to semiconductor integrated circuit devices and more particularly, it relates to an improved counter circuit formed of a plurality of substantially identical bit cells in which each bit cell is fabricated with a smaller number of components than has been traditionally available.
As is generally well known in the art, one of the most common ways to synchronize events occurring in digital logic circuitry is achieved by utilizing conventional counter circuits. These counter circuits are typically adapted to count up to a certain number of clock pulses. Further, such counter circuits may be operated on straight binary counting codes, Gray codes, or any other suitable code arrangement. Dependent upon the range of the counter circuit desired, there is determined the number of counter cells or stages to be required. Each of the counter cells corresponds to one bit of the counter circuit.
In the normal binary counting operation of an upcounter, prior to starting of the counting circuit a reset signal is supplied to each of the counter cells so that each bit will be initially set to "zero." Thereafter, at each cycle of the clock pulses the counter circuit will count up by one. For example, in the case of a 4-bit counter circuit, when the reset signal is applied the values of the four bits will be set to .0..0..0..0.. Then, after each cycle of the clock pulses following the reset signal, the values of the four bits will be changed to: .0..0..0., .0..0.1.0., .0..0.11, and so on.
At the present time, most of the prior art counter circuits employ two-phase clocking signals or pulses, with a carry chain. At each cycle of the clock pulses, the values of the carry-in signal and the current state of a particular bit are used to determine the next output state of the particular bit and to generate a carry-out signal. Generally, a logic "AND" function is used to generate the carry-out signal, and a logic "EXCLUSIVE OR" function is performed on the carry-in signal and the current state of the particular bit so as to output the new or next state of the particular bit. A prior art counter cell 2 utilizing this technique is shown in FIG. 1. As can be seen, this approach requires the use of twenty-four (24) MOS transistors. Since a relatively large number of components is used in this implementation of each counter cell, there is required the need of increased amounts of chip area, which not only increases manufacturing costs but also adds to the amount of power dissipation.
It would therefore be desirable to provide an improved counter circuit which contains a plurality of substantially identical bit cells, each cell being formed with a smaller number of components than has been traditionally required. Further, it also would be expedient to construct each bit cell to be of a regular configuration or structure so as to conform to a repeatable pattern suitable for very large scale integration (VLSI) with high packing density.