This invention concerns a method for driving dot matrix print heads in serial dot matrix printers for printing characters and graphics responsive to data transmitted from data processing equipment.
In a serial dot matrix printer, dot printing is made while the dot matrix print head is moved by a space motor, and linefeed is made by a linefeed motor. Characters and graphics are printed by repeating these operations. Of these operations, the drive of the dot print head affects the resulting print quality and print speed.
FIG. 1 is a block diagram of a dot print head control circuit in which the conventional dot print head drive method is applied. FIG. 2 is a timing chart illustrating the operation of the components in FIG. 1. In these figures, 1 denotes an instruction circuit, 2 denotes a drive time signal generation circuit, 3 a drive circuit, and 4 a dot print head.
Instruction circuit 1 is comprised of a microcomputer. For each timing signal a, instruction circuit 1 sets print pattern signal b (#b1, #b2, . . . , #bn, where n is a dot pin number) to high level "1", corresponding to the dot pins in dot print head 4 to be actuated for printing, and transmits the signals to drive circuit 3; at the same time, instruction circuit 1 transmits drive signals c, which have different effective time values depending on the number of dot pins energized, to drive time signal generator circuit 2.
Upon input of drive signal c from instruction circuit 1, drive time signal generator circuit 2 generates drive time signal T1 for releasing the dot pins P1 to Pn, which are pulled in when not in use for printing, and drive time signal T2 for maintaining the self-holding current and preventing the dot pins from being pulled in during printing, and sends these drive time signals T1 and T2 to drive circuit 3.
FIG. 3 is a circuit diagram of drive time signal generator circuit 2. Its operation will now be described. When drive signal c is input to inverter 2a capacitor C1 which has been charged is discharged at a rising edge of the drive signal c. Then capacitor C1 is charged by current from drive voltage V.sub.cc via resistor R1 at a falling edge of the drive signal c. The output d of the inverter 2a, which is called a charge/discharge signal, is input into one input terminal (+) of the comparator 2b and one input terminal (+) of another comparator 2c. The +5 V voltage is divided by resistors R2 and R3, and resistors R4 and R5. The voltage across resistor R5 is input as slice level SL1 to the other input terminal (-) of comparator 2b. Likewise, the voltage across resistor R3 is input as slice level SL2 to the other input (-) of comparator 2c. Slice level SL2 is set higher than slice level SL1. Thus, as illustrated in FIG. 2, as long as the level of charge/discharge signal d is less than slice level SL1, the output of comparator 2b, i.e., drive time signal T1 is kept at high level "1", and as long as the level of charge/discharge signal d is less than slice level SL2, the output of comparator 2c, i.e., drive time signal T2 is kept at high level "1".
Upon receipt of the input of print pattern signal b (#b1, #b2, . . . , #bn), and the input of drive time signals T1 and T2 at high level "1", drive circuit 3 (FIG. 1) generates head drive signal e (#e1, #e2, . . . , #en) corresponding to the dot pins, to drive dot print head 4.
FIG. 4 is a circuit diagram of drive circuit 3. As illustrated in FIG. 4, inverter 3a receives drive time signal T1, which is transmitted from drive time signal generator circuit 2. The output of inverter 3a is applied to the base of transistor TRn+1. AND circuits 3b-1, 3b-2, . . . , 3b-n are provided for respective dot pins. Each of the AND circuits 3b-1 to 3b-n receives drive time signal T2 from drive time signal generator circuit 2. AND circuits 3b-1 to 3b-n also reseive print pattern signals #b1 to #bn respectively of the print pattern signal b from instruction circuit 1. AND circuits 3b-1 to 3b-n perform logical product operation, and the outputs from these AND circuits are input, respectively, to the bases of transistors TR1 to TRn, provided for respective dot pins. The emitter of transistor TRn+1 is connected to power supply VMM, and its collector is connected to one end of each of head coils L1 to Ln. The other ends of head coils L1 to Ln are connected, respectively, to the collectors of transistors Tr1 to TRn. Emitters of transistors TR1 to TRn are connected to ground G. Diode Dn+1 is connected across head coils L1 to Ln and transistors TR1 to TRn with its anode grounded. Diodes D1 to Dn are connected between respective collectors of transistors TR1 to TRn and the emitter of transistor TRn+1 with their anodes connected to the collectors of transistors TR1 to TRn.
The following explains the operation of the system as configured above, and in particular the operation of dot pin No. 1 in dot print head 4.
In response to timing signal a, instruction circuit 1 raises print pattern signal #b1 to high level "1" and sends it to drive circuit 3, simultaneously sending drive signal c to drive time signal generator circuit 2 via inverter 2a. When drive signal c rises, capacitor C1 that has been charged is discharged. The level of charge/discharge signal d gradually decreases and when it becomes equal to slice level SL2, comparator 2c sets drive time signal T2 to high level "1", and sends it to drive circuit 3; likewise, when the level of charge/discharge signal d becomes equal to slice level SL1, comparator 2b sets drive time signal T1 to high level "1", and sends it to drive circuit 3. When drive time signal T1 is high transistor TRn+1 of drive circuit 3 is turned on. Further, AND circuit 3b-1 performs logical product operation of drive time signal T2 at high level "1" and character pattern signal #b1 at high level "1". As a result, transistor TR1 is turned on. As a result, head drive signal #e1, or head drive current flows as shown by X1 in FIG. 2 from power supply VMM, through transistor TRn+1, head coil L1, transistor TR1, and to ground G, in that order, This, in turn, generates from coil L1 a magnetic field cancelling the magnetic field, form a permanent magnet not shown, for pulling dot pins. Because of the cancellation of the magnetic field, dot pin No. 1 (P1), being biased by a leaf spring, not shown, is moved forward (toward printing paper 7 on the platen 6) to perform one dot of printing. When drive signal c sent from instruction circuit 1 falls, capacitor C1 in drive time signal generator circuit 2 is charged up. As the level of charge/discharge signal d gradually rises and when it exceeds slice level SL1, drive time signal T1 becomes low level "0". Transistor TRn+1 in drive circuit 3 is thereby turned off. As a result, head drive signal #e1 flows through head coil L1, transistor TR1, diode Dn+1, and head coil L1, in that order. Head drive signal #e1 therefore gradually falls, as shown by X2 in FIG. 2. Further, when the level of charge/discharge signal d in drive time signal generator circuit 2 rises higher than slice level SL2, drive time signal T2 becomes low level "0". As a result, drive signal #e1 flows from ground G, through diode Dn+1, head coil L1, diode D1, and power supply VMM, in that order. Head drive signal #e1 therefore falls quickly as shown by X3 in FIG. 2.
The same operation is performed concurrently and in a similar manner on multiple dot pins that are used for printing.
According to the above scheme, however, the dot pins P1 to Pn that are driven for printing are driven for the same length of time, since print pattern signals b have the same effective period. The drive time is set to the maximum value in order to accommodate the dot pin requiring the greatest length of print time and stroke. Consequently, dot pins that print quickly or those requiring smaller strokes remain in operation by the drive current even after expiration of time required for printing. This results in delayed return. Also, since the drive time is set to the maximum drive time of the dot pins, the power consumption tends to be higher. If the drive period is shortened the problem of missing dots occurs or ribbon 5 can be caught by the pin return of which is delayed.