This invention relates to a random access memory and more particularly to apparatus for transferring one or more bytes of a digital word to and from one or more memory locations within one memory cycle.
A computer or data processing system usually comprises a memory subsystem having a plurality of memory locations for the storage of digital words made up of a specific number of bits such as 8, 16, 24 or 32. The computer architecture for some prominent 32 bit general register machines employs variable length instructions represented by a sequence of bytes with the first byte specifying the operation to be performed and succeeding bytes specifying the operands. Each operand may be 8, 16, 32, or even 64 bits. Storage of a mixture of variable length instructions and data in a 32 bit word memory achieves maximum utilization of the memory storage space available if, for example, part of a 32 bit instruction or data word is stored in the same location as a 16 bit instruction or data word and the remainder in a subsequent memory location.
In the prior art, efficient utilization of memory space has been accomplished by a combination of hardware and software techniques. However, more than one memory cycle has been required when part of an instruction or data word was stored in one memory location and the other part stored in another memory location. The result has been that efficient utilization of memory space is accomplished, but the processing speed of the computer is reduced. Using this invention as local storage, that is storage associated with a central processing unit as opposed to the main storage of a data processing system, conventional main storage still can be used while achieving the benefits of making multi-byte accesses within one memory cycle in local storage.