Embodiments of the inventive subject matter generally relate to the field of memory caching, and, more particularly, to delayed replacement of cache entries.
Processor architectures can support multiple virtual memory page sizes. For example, the IBM® POWERS+™ processor supports 4 KB, 64 KB, 16 MB, and 16 GB virtual memory pages. Some processor architectures utilize a single translation lookaside buffer (TLB) to store address translations (i.e., mapping between virtual and physical addresses) for all the supported page sizes. TLB entries corresponding to larger pages are often more valuable than TLB entries for smaller pages because the larger pages provide more coverage of address space in a page table.