Semiconductor devices, such as diodes and transistors are essential components for electronic devices. A continuing demand exists for new, alternative, less expensive and/or improved manufacturing processes for their production. Currently, a particular interest exists in processes for the production of flexible electronics components for use e.g. in RFID tags, flexible LED and LCD displays and photovoltaics. A very promising technique for producing flexible electronics is the so-called roll-to-roll (R2R) fabrication technique (also known as web processing or reel-to-reel processing). R2R fabrications techniques include production methods wherein thin-films are deposited on a flexible (plastic) substrate and processed into electrical components in a continuous way.
In an R2R process preferably printing techniques (e.g. imprint, inkjet, or screen printing) and coating techniques (e.g. roll, slit coating or spray coating) are used in order to achieve high throughput, low-cost processing. Such techniques include the use of inks, i.e. liquid precursors, which can be deposited on the substrate using a simple coating or printing technique. This way, flexible electronics may be fabricated at a fraction of the cost of traditional semiconductor manufacturing methods. R2R processing is however a technology which is still in development.
Problems that need to be overcome in order realize flexible electronics for high-performance applications, such as UHF RFIDs and electronics for foldable phones, include the development of low-cost processes for the realization of thin-film structures with small feature size and high alignment accuracy; and, the development of ink-based processes for realizing high-mobility semiconducting thin-films on a flexible plastic substrate.
U.S. Pat. No. 6,861,365 B2 describes the realization of a three-dimensional resist structure on a thin-film semiconductor multilayer stack on a flexible substrate by imprinting a structured mold into a resist layer. Subsequent (anisotropic) etching of the 3D mask allows the formation of thin-film semiconducting structures in the multilayer stack. The minimum feature size and the alignment accuracy are determined by the 3D mask, which is further determined by the photolithography. The etching steps are based on vacuum processes thus providing a R2R process with an inefficient energy consumption and material usage. Moreover, although the 3D resist mask provides the required alignment, it introduces substantial design constrains and processing complexity.
US2012/0064302 describes a patterning method for obtaining semiconductor structures using a micro or nano-imprint process. In this method a substrate is coated with UV-exposed cyclopentasilane (CPS) layer and an imprint mold is pressed into the layer in order to transfer the structure of the imprint mold into the layer. Thereafter, the substrate with the layer having the mold pressed therein is annealed for a predetermined time so that the patterned CPS coating is transformed into amorphous silicon. After cooling down the mold may be removed. Although this method enables the formation of submicron structures on a substrate on the basis of CPS without the need of complex (vacuum) processing techniques, the method requires a relatively expensive nano-imprint mold in order to form structures with submicron features.
Hence, there is a need for in the art for improved methods for manufacture of submicron structures on a substrate using liquid precursors and small submicron structure obtainable by such methods.