A calibration circuit is provided in certain semiconductor devices in order to adjust the impedance of an output buffer resulting in adjusting the impedance of an output terminal. Japanese Patent Application Laid-Open No. 2011-61580 shows an example of such a calibration circuit. The output buffer includes multiple transistors coupled in parallel, and its impedance is adjusted by specifying the number of transistors to be activated through a selection signal generated by the calibration circuit.
For example, when five transistors that are binary-weighted are coupled in parallel, 32 stages of impedance adjustment can be performed, which include a stage of deactivating all the transistors and a stage of activating all the transistors. However, because the lengths of respective interconnects between the transistors and the output terminal are different from one another, selection of a transistor results in a change in the interconnect resistance.