In the race to improve transistor performance as well as reduce the size of transistors, transistors have been developed that do not follow the traditional planar format, such that the channel and source/drain regions are located in a fin formed from the bulk substrate. One such non-planar device is a multiple-gate FinFET. In its simplest form, a multiple-gate FinFET has a gate electrode that straddles across a fin-like silicon body to form a channel region. In this configuration, there are at least two gates, one on each sidewall of the silicon fin.
In an effort to improve the performance of the multiple-gate FinFET, stress may be generated in the channel region of the substrate between the source/drain regions by removing the fins and then regrowing the fins with a different material. However, in FinFET devices where multiple channels may share a common gate electrode, the closeness of the fins during regrowth causes voids to form in between the re-grown source/drain regions as there is not enough space between the regrown source/drain regions to allow subsequently formed layers (such as a contact etch stop layer) to fill the small regions between the re-grown source/drain regions. These voids where there is no re-grown source/drain to cause stress may decrease the overall potential performance of the device.
As such, what is needed is a structure (and method to form the structure) that allows for a larger stress level and for better control of the stress that may be applied to the channel regions of a FinFET device.