Shallow trench isolation (STI) has been the most widely used isolation structure for sub 0.25 μm CMOS generation and beyond due to its good scalability and isolation performance. The main process steps of STI, i.e., dry etching silicon for trench formation and oxide gap-filling the trench, significantly impact device performance and reliability. As transistors are continuously scaled down, the electrical behavior of narrow width transistors is influenced more significantly by STI corner profiles and manufacturing processes than that of wide width transistors.
Among promising structures that have improved device performance and reliability, vertical structures, such as FinFETs, have excellent short channel control and increased drain current, thus are widely used. One of the reasons that FinFETs (or tri-gate transistors) have high drain currents is that their channels are formed along sidewalls of a vertical structure (such as the silicon “fin” of a FinFET). This significantly increases the effective channel width.
Vertical structures, however, suffer drawbacks. Compared to planar devices, source/drain extension resistances of FinFETs are high due to greater LDD implant angles. The high resistance is an inherent limitation for further improving FinFET transistor performance. Additonally, formation processes are complex due to difficulties caused by a high aspect ratio in manufacturing steps such as etching, implanting, and lithography, etc.
Therefore, what is needed is an improved planar MOS device that can overcome some of the shortcomings of vertical devices.