This invention relates to DC to DC converters in general and in particular, to a DC to DC converter having more than one current output level including a very low current level. A prior DC to DC converter is illustrated in U.S. Pat. No. 4,355,277 issued Oct. 19, 1982. This prior art device is a pulse width modulation type of DC to DC converter that is capable of efficiently operating at two or more output current levels. The output current is controlled by the application of different levels of base bias current to the control transistors of the converter. When a lower level output current is desired, a lower base current level is supplied to the operating transistors. When a higher output current is required, additional base current is supplied to the control transistors of the converter.
This type of circuit might best be thought of as operating in a continuous mode, that is, the converter is turned on at all times, with all elements of the converter being fully operational and the current efficiency is optimized by controlling the base bias current. Thus, energy is delivered to the output load during each cycle of the fixed operating frequency that is determined by the ramp generator.
Such a circuit becomes very inefficient when an extremely low output is required in addition to the normal output levels. For example, where only a 5 or 10 microamp output current is required, the operating power consumed by the DC to DC converter will be substantially higher than the output power from the converter.
One particular application where energy efficiency is important is in portable paging radios. Such devices are commonly constructed with severe constraints on physical size and weight and must be designed to be powered by a single cell battery. Due to the limited battery capacity it is important to minimize current drain in order to maximize the operating life of a battery in the unit.
In such a device it is frequently necessary to provide an operating voltage higher than the battery voltage in order to power certain circuits as, for example, a microprocessor based decoder. Such a device is shown in FIG. 2 and is discussed in the U.S. Pat. No. 4,355,277. In this figure, a DC to DC converter designed for two output current levels is illustrated.
An OR input composed of a NOR gate and an inverter are connected to the DC to DC converter in order to selectively enable the higher current output. The NOR gate includes two inputs, one of which could be considered the state select signal input and can be controlled by a microcomputer or other control element to control the state of the DC to DC converter in normal operation. The other input of the NOR gate is provided as an override, in the event that the output voltage of the DC to DC converter drops below some predetermined value, the low voltage sensor would be triggered to switch the DC to DC converter into the higher current output mode of operation as well as actuating reset logic associated with the paging receiver.
By providing dual current level outputs, an increase in the operating efficiency over that of a single level DC to DC converter is achieved. However, in an application such as a paging receiver, a substantial portion of the operating time of the device can correspond to an extremely low current demand level. Further, recent advances in the design of microprocessor based paging decoders have led to a drastic reduction in the power drain of decoders when they are in the low power operating mode. At such low output levels, a DC to DC converter operating in a continuous low current mode will be very inefficient.