With high bandwidth applications (e.g., full band cable and satellite receivers, serial links and short range wireless communications) becoming more and more popular, there is increasing demand for high speed and high performance analog-to-digital convertors (ADCs). In the past twenty years, the impact of Moore's law on device scaling has exponentially increased the computing power of digital integrated circuits. However, the improved device scaling has not been as advantageous in analog and mixed signal circuits. As devices' scale becomes smaller, a decreased requirement in supply voltage results in smaller dynamic range of signals. In the meanwhile, analog signal processing (e.g., comparison and amplification) is limited by operational amplifier (op-amp) gain and device mismatch.
Further, the analog metrics have become even more challenging at deeply scaled CMOS technologies. For example, a limited gain of op-amps, as well as comparator mismatch, can limit the maximum number of bits in a data converter. The challenge is more severe at high frequency applications (e.g., telecommunication receivers) where op-amp and comparator accuracy is inevitably traded for higher bandwidth.