This invention is concerned with the simulation of multi-port memory array operation by means of a special purpose processor utilizing simulated access signals provided by a logic simulation machine which produces signals representative of the operation of logic surrounding the simulated memory arrays.
Simulation is extensively used in the design of electronic logic circuits. Once a logic circuit's design has been reduced, its operation can be examined indirectly by means of a logic simulation machine (LSM) that operates to represent the operation of the circuit under a set of specified test conditions. The purpose of the machine simulation is to detect design errors in a simulated logic and enable the logic designer to correct the errors before manufacture of the design.
A particular logic simulation machine is described in a series of articles found in the Proceedings of the 1983 IEEE International Conference on Computer Design. The articles are: "Introduction to the IBM Los Gatos Logic Simulation Machine," John K. Howard et al, "The IBM Los Gatos Simulation Machine Hardware," Ted Burggraff et al, "The IBM Los Gatos Logic Simulation Machine Software," Jack Kohn et al, and "Using the IBM Los Gatos Logic Simulation Machine," John K. Howard et al. The LSM described in those articles was first disclosed in U.S. Pat. No. 4,306,286 of Cocke et al, which is incorporated herein by reference.
The LSM of U.S. Pat. No. 4,360,286 is a highly parallel machine that incorporates a plurality of functionally equivalent processors, each able to simulate a portion of a logic network. The operations of the parallel processors are orchestrated and integrated by means of a control unit including an interactive processor switch that provides connectivity between the processors and a control processor that exercises overall control of the machine and provides input/output and programming capability. The operation of the prior art LSM is based upon the execution in each of the parallel processors of a series of instructions, with each instruction initiating a machine operation step that corresponds to the operation of a single logic gate. The machine operates cyclically, with each basic cycle corresponding to a single updating of all signal values in a simulated logic gate.
While extremely efficient in simulating logic circuits made up of discrete gates, the prior art LSM only awkwardly simulates memory arrays for the reason that the machine simulation operates on the individual bits involved in logic gate operation Therefore, for the prior art LSM to simulate, for example, operation on each bit of an 8.times.32K memory array, over 256,000 individual instructions would be required. Clearly, the prior art logic simulator awaits an advance whereby multi-bit memory operation can be simulated by a minimal set of instructions. Preferably, each simulated memory reference would be implemented by a single instruction.