Advances in today's System-on-Chip (SoC) technology allow embedding of hundreds of Static Random Access Memories (SRAM) on a single chip occupying more than half of the die area. A previous method of modeling defects is based on special kernels of design constructs that brings to many limitations. Also, other methods restrict themselves considering only the Poisson distribution of defects and that is also a serious restriction.
However, many problems connected with yield calculation of today's SoCs with hundreds of memory cores with different configuration remains open. The user needs urgently to understand before the design what configuration of the given memory type and size to choose, what type of memory (with or without redundant elements) to use, what amount and type of redundant elements (redundant rows only, redundant columns only, or both) to use to achieve the highest possible yield. The yield optimization problem is too difficult, especially for a memory system with a test and repair infrastructure. If repairable memories with redundant elements (rows and/or columns) are used in a memory system of a System on a Chip design then special built-in logic blocks are also embedded into the System on a Chip to test, allocate the redundant elements and repair the memories. The area of additional embedded blocks depends on each memory instance configuration, thus affecting the overall yield of both good functional chip dies fabricated and an amount of chip dies produced per silicon wafer.