In order to form electrical connections to a semiconductor element such as a MOS transistor and the like formed on a semiconductor substrate, there is known a method in which, at regions corresponding to source/drain regions of the MOS transistor, contact holes or openings are formed through an interlayer insulating film covering the MOS transistor, and the contact holes or opening are filled with conductive material to form contact plugs. Thereby, the source/drain regions are electrically coupled with upper layer wiring conductors or other electric circuit elements formed on the interlayer insulating film via the contact plugs. However, according to a recent increase in an integration degree of a semiconductor device, a gate electrode and source/drain regions of a MOS transistor become minute. Therefore, it is required that contact holes are precisely formed in an interlayer insulating film. That is, if a position of a contact hole is not correctly aligned with respect to a position of a MOS transistor, when a contact hole is formed, for example, on a source/drain region, there is a possibility that, for example, a part of a gate electrode is exposed within the contact hole. In such case, when the contact hole is filled with a conductive material, the conductive material short-circuits the gate electrode and the source/drain electrode, so that a defective element is produced. Otherwise, when the contact hole is formed, a part of an element isolation oxide film is etched, and the conductive material filling the contact hole penetrates into the etched part of the element isolation oxide film, so that there is a possibility that adjacent source/drain regions are short-circuited. Especially, if each of the contact holes on the source/drain regions is not opened enough, an electrical connection to each of the source/drain regions may become incomplete. Thus, when a contact hole is formed, an interlayer insulating film is usually slightly over-etched to open the contact hole well. Therefore, if a location of the contact hole is not aligned correctly with respect to a location of a MOS transistor, a silicon oxide film on the side portion of a gate electrode or the element isolation oxide film is etched away by the over-etching, thereby the above-mentioned defective element is produced.
Conventionally, in order to avoid such disadvantage, a technology is proposed in which a silicon nitride film having etching selectivity with respect to a silicon oxide film constituting an interlayer insulating film, that is, having an etching rate different from that of a silicon oxide film, is used. Thereby, occurrence of a defective element due to the shift of location of a contact hole is avoided. FIG. 8A through FIG. 8C show schematic cross sectional structures obtained during a process according to such technology. As shown in FIG. 8A, an SIT (Shallow Trench Isolation) 202 made of silicon oxide is formed on a silicon substrate 201, for example, a p-type silicon substrate, to define an element forming region. Then, by using a commonly used method, a gate insulating film 204 and a gate electrode 205 are formed in the element forming region. By using the gate electrode 205 as a mask, impurities are implanted into the silicon substrate 201 at a low impurity concentration and LDD regions 206 of, for example, n type are formed. Also, sidewall spacers 207 made of silicon oxide are formed on both side surfaces of the gate electrode 205. Thereafter, by using the gate electrode 205 and the sidewall spacers 207 as a mask, impurities are implanted into the silicon substrate 201 at a high concentration to form source/drain regions 208 of, for example, n.sup.+ type. In this way, a MOS transistor is formed. Then, a silicon nitride film 210 is formed on whole surface of the substrate 201 such that the MOS transistor is wholly covered thereby, and further a silicon oxide film, for example, BPSG film (boro-phospho silicate glass film) or BSG film (boro-silicate glass film), is formed on the silicon nitride film 210 as an interlayer insulating film 211 which covers the MOS transistor. Thereby, a structure shown in FIG. 8A is obtained.
As shown in FIG. 8B, by using a mask layer 212 such as a photoresist film and the like which is formed by a photolithography and the like, the interlayer insulating film 211 is selectively etched and removed, so that a contact hole 213 is formed in the interlayer insulating film 211. In this case, as shown in FIG. 8B, even if a location of the contact hole 213 is shifted, for example, toward right side with respect to the location of the source/drain region 208, the silicon nitride film 210 functions as an etching stopper film, so that the sidewall spacer 207 and the STI 202 are not etched when the interlayer insulating film 211 is over-etched. For comparison, FIG. 8C shows a cross sectional structure obtained when the contact hole 213 is formed without forming the silicon nitride film 210 in the structure of FIG. 8A. In such case, as shown in FIG. 8C, the sidewall spacer 207 or the STI 202 is etched depending on the direction and magnitude of the shift of location of the contact hole 213.
After the structure of FIG. 8B is obtained, although not shown in the drawing, the silicon nitride film 210 which is exposed at the bottom portion of the contact hole 213 is selectively etched and removed. Thereby, the contact hole 213 reaches the source/drain region 208 and also the sidewall spacer 207 and the STI 202 made of silicon oxide films are hardly etched in the contact hole 213. Therefore, it is possible to prevent the sidewall 207 and STI 202 from being etched when the interlayer insulating film 211 is over-etched, and to avoid production of a defective element.
The above-mentioned conventional technology is effective in case the interlayer insulating film is over-etched when contact holes are opened. However, in a process after forming contact holes reaching source/drain regions, and especially in a pre-treatment step of a process for forming contact plugs by filling conductive material in the contact holes, if an etching process such as cleaning process and the like is performed, the interlayer insulating film and the like is etched by such etching process at the inside surface of the contact hole.
For example, when a technology which is proposed by the applicant of this application and which is disclosed in Japanese patent application No. 9-305387 (Japanese patent laid-open publication No. 11-145283) is applied to a manufacturing of the semiconductor device shown in FIG. 8A and 8B, a manufacturing process becomes as follows. That is, as shown in FIG. 9A, a metal silicide layer 209 such as tungsten silicide and the like is formed on the upper surface of a gate electrode of a MOS transistor and on the surface of the source/drain regions 208 of a silicon substrate 201. Then, by using two time etching processes, a contact hole 213 is formed in an interlayer insulating film 211 and a silicon nitride film 210. The contact hole 213 is filled with a conductive material such as polysilicon and the like, and thereby a contact plug 215 coupling with the metal silicide layer 209 is formed. In this case, there is a possibility that, because of the surface roughness of the metal silicide layer 209, a contact resistance between the contact plug 215 and the metal silicide layer 209 becomes large. In order to avoid such disadvantage, in practice, as shown in FIG. 9B, the surface of the metal silicide layer 209 exposed at the bottom surface of the contact hole 213 is cleaned by wet etching which uses dilute hydrofluoric acid and the like, after forming the contact hole 213 in the interlayer insulating film 211 and the silicon nitride film 210. By this cleaning, the surface of the metal silicide layer 209 is slightly etched and the roughness of the surface thereof is removed. Thus, the contact resistance between the contact plug 215 formed thereafter and the metal silicide layer 209 can be reduced.
However, when the cleaning of the surface of the metal silicide layer 209, in other words, the contact surface of an element, is performed by using dilute hydrofluoric acid as shown in FIG. 9B, the interlayer insulating film 211 composed of a silicon oxide film is also etched at the same time. Especially, since the inner surface of the contact hole 213 is exposed extensively to the dilute hydrofluoric acid, etching progresses remarkably at the inner surface of the contact hole 213. Also, BPSG, BSG or the like constituting the interlayer insulating film 211 is easily etched by the dilute hydrofluoric acid. Therefore, as shown by a chain line in FIG. 9B, an inner diameter of the contact hole 213 is enlarged. As the inner diameter of the contact hole 213 is enlarged, there is a possibility that the contact hole 213 overlaps any other contact hole or contact holes adjacent to the contact hole 213, for example, a contact hole formed for another adjacent MOS transistor and not shown in the drawing. That is, there is a possibility that contact holes disposed mutually in close proximity overlap with each other and that, when the contact holes are filled with conductive material to form contact plugs, the contact plugs short-circuit with each other. Thereby, a manufacturing yield of semiconductor devices deteriorates.
Also, in case the interlayer insulating film 211 has a stacked structure which comprises a plurality of insulating films of, for example, a plasma silicon oxide film and a BSG film, since the BSG film is etched faster than the plasma silicon oxide film by dilute hydrofluoric acid, an inner side surface of the contact hole 213 is etched non-uniformly by a cleaning process of a contact surface of a circuit element exposed at the bottom surface of the contact hole, so that the inner side surface of the contact hole 213 becomes uneven. Therefore, when the contact hole 213 is filled with conductive material to form a contact plug, there is a possibility that the contact plug has void or voids and it becomes difficult to fabricate a reliable contact plug 215 having low electrical resistance. In order to avoid such disadvantage, strict control of fabrication process steps for the contact structure is required which leads to an increase in manufacturing cost and deterioration of manufacturing yield.