Phase-locked loop (PLL) circuits are frequently utilized to lock an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of synchronous data sent by a transmitter in the communication system.
A conventional PLL circuit includes a phase detector, a filter and a voltage-controlled oscillator (VCO). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output. The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
A potential problem exists, however, for a PLL circuit based on sampled phase detectors. Specifically, for large frequency errors, conventional sampled phase detectors are equally likely to generate a positive or negative phase correction signal, regardless of the actual polarity of the frequency error, since the likelihood of sampling before and after a data edge (due to the frequency error) is fifty percent (50%) each. Thus, it is necessary to ensure that large frequency errors do not occur by extending the frequency lock range of the PLL circuit.
Conventional techniques for extending the frequency lock range of a PLL circuit based on sampled phase detectors utilize a square wave as an auxiliary input to initially tune the VCO, while using an additional phase and frequency detector (PFD) to compare the frequency of the auxiliary input to the VCO output. Once the VCO is tuned to the desired frequency in this manner, the additional phase and frequency detector (PFD) is switched out of the PLL feedback loop, and the sampled phase detector is utilized to phase lock onto the incoming data. Relying on the presence of an external reference signal, such as a square wave, to extend the frequency lock range, however, may not be practical in many receiver applications where the only received signal is the incoming random data.
Improved frequency acquisition has been achieved by sweeping the frequency of the VCO output, V.sub.O, to search for the signal frequency. The PLL will lock when the frequency of the VCO output, V.sub.O, is sufficiently close to the frequency of the reference signal. A lock detector determines when the VCO locked up, and then turns off the applied voltage ramp.