1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, the invention relates to a defect address storing circuit for a semiconductor memory device.
A claim of priority is made to Korean Patent Application No. 2005-06840 filed on Jan. 25, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Memory arrays in integrated circuit (IC) memory devices often contain defective memory cells. To prevent the defective memory cells from jeopardizing the performance of the memory devices, memory arrays often provide redundant memory cells that act as substitutes for the defective memory cells. In these memory arrays, whenever a defective memory cell is detected, a redundant memory cell is assigned to replace the defective memory cell. Then, whenever an address corresponding to the defective memory cell is provided to the memory array, the redundant memory cell is accessed instead. In this written description, an address for a defective memory cell is referred to as a “defect address”.
Defect addresses are generally stored in memory devices using special defect address storing circuits. A defect address storing circuit monitors memory access operations in the memory array to detect whenever a defect address is provided to the memory array. Upon detecting a memory access operation involving a defect address, the defect address storing circuit causes a redundant memory cell to be accessed instead of the defective memory cell.
A defect address is typically stored in a defect address storing circuit by blowing fuses in the defect address storing circuit according to a particular address to be represented therein. The fuses are blown according to a specific pattern such that an output signal of the defect address storing circuit will take on a particular value only when a defect address is input to the defect address storing signal.
For example, suppose that ‘001’ has been identified as a defect address. Then specific fuses in a defect address storing circuit will be blown so that a signal output of the defect address storing circuit assumes a logic state ‘0’ only when the address ‘001’ is presented to the defect address storing circuit. Accordingly, whenever the output signal of the defect address storing circuit assumes logic state ‘0’, the memory device will access a redundant memory cell for address ‘001’ rather than a defective one.
Figure (FIG.) 1 is a circuit diagram illustrating a conventional defect address storing circuit 100 such as the one disclosed in U.S. Pat. No. 6,545,920.
Referring to FIG. 1, defect address storing circuit 100 includes three address storage blocks connected to each other in series. Each of the address storage blocks comprises a pair of fuses electrically connected to each other and a pair of N-Type metal-oxide semiconductor (NMOS) transistors respectively connected to the pair of fuses. The NMOS transistors in each address storage block are also electrically connected to each other.
A first address storage block comprises a first pair of fuses F1a and F1b electrically connected to each other at an upper node of the first address storage block. A first pair of NMOS transistors T1a and T1b respectively connected between fuses F1a and F1b and a lower node of the first address storage block. A second address storage block comprises a second pair of fuses F2a and F2b electrically connected to each other at the lower node of the first address storage block, and a second pair of NMOS transistors T2a and T2b respectively connected between fuses F2a and F2b and a lower node of the second address storage block. A third address storage block comprises a third pair of fuses F3a and F3b electrically connected to each other at the lower node of the second address storage block, and a third pair of NMOS transistors T3a and T3b respectively connected between fuses F3a and F3b and a lower node of the third address storage block.
In the above and subsequent description, the term “node” is used to denote a portion of a circuit with substantially uniform electrical potential. Two elements connected to the same node may be viewed as being electrically connected to each other. The terms “upper node” and “lower node” are used to distinguish relative positions of nodes in circuit diagrams where applicable (e.g., in FIG. 1). However, the terms “upper” and “lower” should not necessarily be read to implicate particular positions for the nodes in an actual circuit layout.
For explanation purposes, it will be assumed that the lower node of the third address storage block is connected to ground and that an output signal of defect address storing circuit 100 is read at the upper node of the first storage block. It will be further assumed that the upper node of the first storage block is connected to a power supply through a resistance such that when a current path exists between the upper node of the first storage block and the lower node of the third storage block, the voltage level of the output signal will be the same as ground, i.e., the output signal will have a logic state ‘0’.
In FIG. 1, NMOS transistors T1a and T1b are respectively controlled by complementary address signals nA0 and A0, NMOS transistors T2a and T2b are respectively controlled by complementary address signals nA1 and A1, and NMOS transistors T3a and T3b are respectively controlled by complementary address signals nA2 and A2.
To store a defect address in defect address storing circuit 100, fuses corresponding to the defect address should be blown. For example, to store the address ‘001’ in defect address storing circuit 100, fuses F1b, F2b, and F3a should be blown so that the output signal will only have logic state ‘0’ when address signals A0, A1, and A2 have respective logic states ‘0’, ‘0’, and ‘1’. In other words, with fuses F1b, F2b, and F3a blown, a current path will only be formed between the upper node of the first storage block and ground when transistors T1a, T2a, and T3b are turned on by respective signals nA0, nA1, and nA2 with values ‘1’, ‘1’, and ‘1’.
FIG. 2 is a block diagram showing a layout of defect address storing circuit 100 shown in FIG. 1. Referring to FIG. 2, defect address storing circuit 100 comprises a fuse region 110, a first transistor region 120, and a second transistor region 130.
First through third fuse pairs F1, F2, and F3 are arranged in fuse region 110, first and third transistor pairs T1 and T3 are arranged in first transistor region 120, and second transistor pair T2 is arranged in second transistor region 130.
First and third transistor pairs T1 and T3 are controlled by a first bus line BL1a, and second transistor pair T2 is controlled by a second bus line BL1b. Address signals nA0, A0, nA2, and A2 (See FIG. 1) are provided to first and third transistor pairs T1 and T3 by first bus line BL1a, and address signals nA1 and A1 are provided to second transistor pair T2 by second bus line BL1b. 
FIG. 3 is a block diagram of a semiconductor memory device 300 including a plurality of defect address storing circuits. Referring to FIG. 3, semiconductor memory device 300 comprises six defect address storing circuits. Each of the defect address storing circuits has the same or similar structure as that of defect address storing circuit 100 shown in FIG. 2. In particular, each of the defect address storing circuits includes first and second transistor regions, and a fuse region between the first and second transistor regions. The first and second transistor regions of three of the defect address storing circuits are respectively connected to bus lines BL1a and BL1b, while the first and second transistor regions of the other three of the defect address storing circuits are respectively connected to bus lines BL2a, and BL2b. 
In the conventional defect address storing circuit shown in FIG. 1, fuse and transistor pairs are alternately arranged. As a result, first and second transistor regions 120 and 130 are arranged with fuse region 110 therebetween as shown in FIG. 2.
Semiconductor memory device 300 shown in FIG. 3 has various shortcomings. First, because its layout includes two transistor regions and a fuse region, semiconductor memory device 300 occupies a large area. Second, because first and second transistor regions 120 and 130 are separated by fuse region 110, they cannot share a bus line.