The present invention relates generally to error checking and particularly to determining whether exactly one of N signal lines is active.
Implementation of state machines with one memory element per state design is often desirable. Typically. such a state machine will always have exactly one memory element set during proper operation. An error in the system can cause either more than one or none of the N memory elements to be set. When such an error occurs, data can be misdirected and errors can be propagated throughout the system. Therefore, it is beneficial to test state machines of this type to determine whether exactly one of the signal lines is active.
A number of error detection techniques have been designed for checking whether exactly one out of N signal lines is active. For example, U.S. Pat. No. 4,020,460 (hereinafter 460) teaches a complementation technique which requires redundant hardware for providing complemented signals of the signals on the N signal lines. However, most of the previous techniques, like 460, require a substantial amount of hardware, and can be slow thereby causing delays in the system.