As electronic technology continuously develops, various types of electronic products become thinner and smaller and have more and more functions. Therefore, the increasingly smaller size of a chip needs to accommodate an increasing amount of types of electronic cells to meet practical requirements of electronic products.
However, in some circuit layouts, since there are too many electronic cells in a region, i.e., a density of electronic cells of the region is too large, and routing among electronic cells in the region becomes difficult to perform thereby causing failure in design rule checking, such that the circuit layouts cannot be normally performed.
FIG. 1A and FIG. 1B show schematic diagrams of a circuit layout comprising electronic cells with a density of 75%. Since electronic cells 10 on a circuit layout 1 are not compactly arranged, i.e., there still are routing spaces among the electronic cells 10, there is no un-routable congestion region on the circuit layout 1.
However, when the density of electronic cells on the circuit layout 1 becomes higher, the foregoing situation changes. FIG. 1C and FIG. 1D show schematic diagrams of the circuit layout 1 comprising electronic cells with the density increased to 90%. Since electronic cells 10′ are inserted into many routing spaces of the circuit layout 1 shown in FIG. 1A, a plurality of un-routable congestion regions emerge on the circuit layout 1 as shown in FIG. 1C. Congestion state marks V1 to V3 (i.e., arrows) represent the congestion regions in a vertical direction of the circuit layout 1 in FIG. 1D.
Since the types and the number of electronic cells contained in a circuit layout continue to increase consistent with the development of technologies and practical applications, the congestion problem described above becomes increasingly serious. Conventional solutions for the foregoing problem may cause variations of relative positions of the electronic cells on the circuit layout such that the circuit layout cannot satisfy a time constraint or results in sacrificing partial spaces of the circuit layout thereby creating additional area penalty.
Therefore, one main object of the present invention is to provide a congestive placement preventing apparatus and method thereof to solve the foregoing problem.