1. Field of the Invention
The present invention relates to a flash memory access apparatus and method. More particularly, the present invention relates to a flash memory access apparatus and method, in which a process of a write operation gaining access to a flash memory in response to a write operation required by a processor is minimized and an occurrence of a system error is prevented through the process of a recovery operation based on the minimized process of the write operation, thereby recovering a system upon occurrence of a system error and minimizing deterioration of performance of the flash memory.
2. Description of the Prior Art
In general, since a flash memory is a nonvolatile and programmable memory that allows fast access thereto and has low power consumption, it has been widely used in embedded systems including mobile devices such as mobile phones and personal data assistants (PDAs).
In such a flash memory, data stored at specific locations can be randomly accessed in the same manner as existing RAMs, nonvolatile storage devices, magnetic devices or the like. However, when data is modified or deleted, the data is accessed on a block basis contrary to existing storage devices.
That is, in the flash memory, access is gained based on the block which written data is retrieved from or data is written in at once during read/write operations, and based on a unit which comprises a plurality of blocks and can be erased through one delete operation. As a method of efficiently managing data according to the access characteristics of the flash memory, a block (or sector) re-mapping scheme has been generally used.
The block (or sector) re-mapping scheme uses information on mapping between a physical block number (hereinafter, referred to as ‘PBN’) and a logical block number (hereinafter, referred to as ‘LBN’) of specific data written in a flash memory through a mapping table so that even though the PBN of the data is changed due to modification or deletion of the data, the data can be accessed using the same LBN.
In such existing block re-mapping schemes, flash memory state information written in the mapping table should be modified whenever write, delete and modify operations required by a processor are performed. Accordingly, there is a problem in that the performance of the flash memory is lowered due to such repeated write operations.
To solve this problem, a method of controlling a flash memory has been proposed. FIGS. 1A-1D show views of blocks of a flash memory for illustrating processes of operations according to the proposed method of controlling the flash memory.
The method is disclosed in the previously filed Korean Patent Application No. 1999-0041835 entitled “Flash Memory and Method of controlling the Same.” FIGS. 1C and 1D shows structures of a physical unit.
Each unit has a header or erase unit header (“EUH”) and a block allocation map (hereinafter, referred to as “BAM”) and actually stores data therein. A variety of meta-information on the header is stored in the header, and information (logical block numbers, state, and the like) on blocks belonging to a specific unit is written in the BAM.
If a write operation for a specific LBN 3 of a flash memory is requested initially, the logical unit number (hereinafter, referred to as “LUN”) 2 for the given LBN 3 is searched for by using an LBN-to-LUN table shown in FIG. 1A. Then, when LUN 2 is determined, a physical unit number (hereinafter, referred to as “PUN”) is searched for by using an LUN-to-PUN table shown in FIG. 1B.
When PUN 1 is determined in such a way, a currently writable PBN is searched for through a BAM corresponding to PUN 1, and data to be written through a write operation are written in the searched PBN 1. Then, LBN 3 and state information of “valid” are written in a first field of the BAM corresponding to PBN 1.
In such a way, if an operation to update the written data of LBN 3 is requested after operations for LBN 4 and 5 are performed, the data of LBN 3 that will be updated while a new PBN will be allocated thereto are written in PBN 4 that is newly allocated to the data, and LBN 3 and state information of “valid” are written in a fourth field of the BAM corresponding to PBN 4.
Then, the data previously written in PBN 1 in which the updated LBN 3 was written, and LBN 3 that was written in the first field of the BAM corresponding to PBN 1 are deleted. State information of “deleted” is also written.
If there is no available free block in PUN 1 due to such write and update operations and PUN 2 is an available free block, only valid data written in PUN 1 is copied to a new PUN 2 in order to more efficiently use the flash memory.
Furthermore, according to Korean Patent Application No. 2000-0059731 entitled “Re-mapping Control Method for Flash Memory and Structure of Flash Memory Thereof,” which was previously proposed to solve such a problem, block state information is indicated using wrap-counts so as to recover from an error upon occurrence of the error (i.e., 1111: unsettled state; 1110 (S0), 1100 (S1), 1000 (S2): effective state; and 0000: deleted), so that a system can be recovered with a minimum of classified write-operations upon the occurrence of the error by classifying previous data and new data using the order of change of the wrap-counts, as shown in FIG. 2a. 
FIG. 2b is a view showing a block structure of a flash memory according to such a re-mapping control method for the flash memory. The block structure comprises a data area in which substantial data are written, a logical sector (block) number (“lsn”) area, a wrap count (“cnt”) area, an lsn/cnt error correction code (“ecc_lsn”) area, and a data error correction code (“ecc_data”) area.
FIG. 2c illustrates processes of writing state information in respective blocks and recovering them with subsequent data upon occurrence of an error.
For example, if an error occurs after a fifth block of the flash memory, there are two valid data sets that have wrap counts of 1110 and 1100, respectively. Since 1110 is prior to 1100, the left data set would be deleted if a policy of recovery with the latest data were employed.
As described above, even the conventional flash memory control method does not provide a method of preventing the deterioration of system performance of a flash memory due to repeated write operations.
Therefore, there is a need for a flash memory access method capable of improving the performance of a flash memory system by reducing the number of write operations.