This invention relates generally to digital logic circuitry and, more particularly, to an improved current mode binary/binary coded decimal arithmetic logic unit which performs parity checking, parity carry, and parity prediction operations.
Various binary/binary coded decimal arithmetic logic units are known in the prior art. The above-referenced Current Mode Binary/BCD Arithmetic Array is directed to a binary/binary coded decimal arithmetic logic unit which performs the basic arithmetic and logic operations of the present invention. The improved current mode binary/binary coded decimal arithmetic logic unit of the present invention provides, in addition to the basic arithmetic and logic functions, necessary and useful parity prediction and parity checking operations on 4-bit plus parity binary and BCD fields. Consequently, errors generated within the arithmetic logic unit or generated during the transmission of data to such unit will be detected quite early in the processing operation, resulting in an overall savings of processing time.