This invention generally relates to data transmission. More particularly, the present invention pertains to an architecture capable of increasing the rate of data transmission within a semiconductor memory device by making use of complementary signal lines.
High-speed differential data transmission (DDT) is a key to the realization of high-performance semiconductor integrated circuits. A high-speed and low-power DDT circuit for general-purpose DRAM is shown by H. Yamauchi et al., in a paper entitled "A Circuit Technology for High-Speed Battery-Operated 16-Mb CMOS DRAM's," IEEE Journal of Solid-State Circuits, Vol. 28, No. 11, pp. 1084-1091, Nov., 1993. This technique is implemented by using a quasi-static N&PMOS cross-coupled amplifier (NPCA) unsubject to a voltage-dependant timing circuit. Data, read onto a pair of complementary data lines from a memory cell via a sense amplifier and via a column switch, are differential-amplified by the NPCA having the ability of performing high-speed and lower-power operations. Then, the data are transmitted to an output circuit through a data read bus made up of a pair of complementary signal lines and are provided outside. Note that, in the following description, a pair of complementary signal lines used for data transmission from a memory cell to a data read amplifier are called DQ/XDQ and a pair of complementary signal lines forming a data read bus used for data transmission from the data read amplifier to an output circuit are called RDB/XRDB.
The NPCA has the following: a pair of internal complementary data lines (DBI/XDBI) connected between DQ/XDQ and RDB/XRDB; first to third precharge circuits for precharging or voltage-equalizing, on the data read time, DQ/XDQ, DBI/XDBI, and RDB/XRDB to the V.sub.CC (power supply) level, to the V.sub.SS (ground) level, and to the V.sub.CC level, respectively; a first differential amplifier connected between DQ/XDQ and DBI/XDBI; and a second differential amplifier connected between DBI/XDBI and RDB/XRDB. In the first differential amplifier, a pair of P-channel MOS (PMOS) transistors with their gates connected to DQ/XDQ respectively are provided on the input side of an NMOS cross-coupled amplifier (i.e., a latch circuit) formed by a pair of N-channel MOS (NMOS) transistors. On the other hand, in the second differential amplifier, a pair of NMOS transistors with their gates connected to DBI/XDBI respectively are provided on the input side of a PMOS cross-coupled amplifier (i.e., a latch circuit) formed by a pair of PMOS transistors.
In such an NPCA as a data read amplifier, a single read cycle time is divided into two periods, the first period and the second period. In the first period, the first to third precharge circuits are simultaneously made active so as to voltage-equalize DQ/XDQ, DBI/XDBI, and RDB/XRDB. In the second period, the first to third precharge circuits are made inactive, thereby allowing the first and second differential circuits to start operating. As a result, read data from the sense amplifier is fed onto DQ/XDQ that is, DQ/XDQ are sensed. The data on DQ/XDQ are transmitted to RDB/XRDB via DBI/XDBI, that is, RDB/XRDB are sensed.
FIG. 14 schematically shows the above-described data read operation. In the first period, the voltage equalization of DQ/XDQ and the voltage equalization of RDB/XRDB are carried out. In the second period, the sensing of DQ/XDQ is carried out and thereafter the sensing of RDB/XRDB is carried out. If (1) the wiring capacitance of DQ/XDQ is about 0.5 pF, (2) the wiring resistance of DQ/XDQ is about 200 .OMEGA., (3) the wiring capacitance of RDB/XRDB is about 2 pF, and (4) the wiring resistance of RDB/XRDB is about 500 .OMEGA., then, for exact differential data transmission to be performed, a minimum of 4 nanoseconds is a required length of time to complete a series of operations from the sensing of DQ/XDQ to the sensing of RDB/XRDB, since the DQ/XDQ sensing requires 2.5 nanoseconds and the RDB/XRDB sensing requires 1.5 nanoseconds. If a length of time taken to voltage-equalize DQ/XDQ and RDB/XRDB is 2.5 nanoseconds, a single cycle time of the DRAM can be reduced down to 6.5 nanoseconds by making use of the foregoing N&PMOS cross-coupled amplifier as a data read amplifier. In other words, a general-purpose DRAM with a maximum operating frequency of 150 MHz can be realized.
Meanwhile, such semiconductor memory devices as synchronous memories and image memories are required to continuously operate in synchronism with a clock signal at high speed. For example, a synchronous DRAM (S-DRAM) is required to be capable of consecutive data read operation in synchronism with a clock signal with a frequency of about 200 MHz, and of consecutive data write operation in synchronism with the clock signal.
A 3.3 V S-DRAM responsive to a clock signal having a frequency of 125 MHz is shown by Y. Choi and the others in a paper entitled "16-Mbit Synchronous DRAM with 125-Mbyte/sec Data Rate," 1993 Symposium on VLSI Circuits, pp. 65-66. An S-DRAM which is similar in performance to the Choi S-DRAM is shown by Y. Takai and the others in a paper entitled "250-Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture," 1993 Symposium on VLSI Circuits, pp. 59-60.
A case where an NPCA structure is applied to a data read amplifier is explained. If the DDT process is kept in a standby state with DQ/XDQ and RDB/XRDB voltage-equalized, this makes it possible to permit fast response with respect to a particular column address strobe signal (CAS). A length of time taken for the response is only about 4 nanoseconds (see FIG. 14). Until the next CAS signal is received, the DDT process is kept in a standby state with DQ/XDQ and RDB/XRDB again voltage-equalized. Therefore, 150 MHz has been sufficient as a maximum operating frequency for the general-purpose DRAM.
However, for the case of the S-DRAM, a 2.5-ns equalizing period is required every time a read operation is executed (see FIG. 14). This is an obstacle to the realization of a target operating frequency. To solve this problem, the above-described S-DRAM, proposed by Y. Choiet al, employs a prefetch structure capable of simultaneously reading 2-bit data with respect to a single column address, so as to apparently accomplish a twofold operating frequency. However, the Choi S-DRAM requires the provision of a multiplexer/selector between a memory array and an external interface, thereby producing the problem that neither the burst length nor the initial address cannot be dealt with easily if they are odd.
FIG. 22a shows the structure of a conventional column decoder used in the Takai S-DRAM. In the figure, NAND circuit 401 for decoding a column address, switch 402 formed by an NMOS transistor, and inverters 403 and 404 together forming a single latch circuit are shown. CLK represents a clock signal and Y represents a column-select line. CLK is applied to the gate of the NMOS transistor forming switch 402 connected between NAND circuit 401 and inverters 403 and 404. The latch circuit, made up of inverters 403 and 404, is operable to hold a signal on a column-select line Y. Such a signal held on the column-select line Y is a signal for on-off controlling a column switch.
If the column-select line Y of FIG. 22a is in an inactive state, then a node A is HIGH and the column-select line Y is LOW. If the output of NAND circuit 401 becomes LOW in accordance with the result of the decode operation of column addresses, and if switch 402 turns on in response to the rising edge of CLK, then the node A makes a transition from HIGH to LOW (HIGH-to-LOW transition) and the column-select line Y makes a transition from LOW to HIGH (LOW-to-HIGH transition). As a result, the column-select line Y is activated. However, there occurs an interference between a low-level output signal of NAND circuit 401 and a high-level signal of the node A.
FIG. 22b is a signal waveform diagram showing the process of activation of Y of FIG. 22a. As illustrated in FIG. 22b, around 2.5 nanoseconds are taken from the moment CLK rises to the moment the column-select line Y is activated, at a 3.3 V power supply. To sum up, in a column decoder employing the FIG. 22a latch circuit, due to the foregoing signal interference, the node A makes a transition with a delay. Then the rising of the column-select line Y is delayed. Finally, the read operation of S-DRAM is delayed.
Once the column-select line Y is made active in response to the rising-edge of CLK, the column-select line Y is held active by the operation of the latch circuit, even after CLK falls. Such an activated state is cancelled by the output of NAND circuit 401 on the next rising-edge of CLK. In other words, conventionally, only transitions, accompanied with the rising of CLK, are utilized. A column-select line that has been made active last during the course of the operation of read is forced to go back to an inactive state (i.e., LOW) by a reset circuit. The reason for this is that, if any one of the column-select lines is continuously held active, then a change in the state of DQ/XDQ is transmitted to bit lines to result in data destruction.