1. Field of the Invention
The present invention relates generally to a manufacturing method of highly refractory titanium silicide, and more particularly, to highly refractory titanium silicide used, for example, for formation of conductive layers on surfaces of gate electrodes source-drain regions and of salicide transistors or highly refractory interconnections in other semiconductor devices, and a manufacturing method thereof.
2. Description of the Background Art
Titanium silicide (mainly TiSi.sub.2) has the lowest resistivity among other high melting point metal silicide such as of titanium (Ti), molybdenum (Mo), and tungsten (W). Therefore, titanium silicide is among hopeful materials for highly refractory interconnections of various types in semiconductor devices. Among the others, salicide (Self-Aligned Silicide) has attracted particular attention for its application to transistors.
A salicide transistor is constituted by forming a high melting point metal silicide film only over the respective surfaces of a gate electrode and source-drain regions of an MOS (Metal Oxide Semiconductor) field effect transistor. The salicide transistor is characterized by the feature that the metal silicide film which has been selectively formed thereon lowers resistivity where it has been applied.
A cross sectional structure of a conventional salicide transistor is shown in FIG. 1. Referring to that view, there is shown a polycrystalline silicon gate electrode (referred to as "gate electrode" hereinafter) formed on a semiconductor substrate 1 with a gate insulating film 2 interposed therebetween. On both sides of the gate electrode 3 there are provided sidewalls 4, outside of which diffusion layers 5 are formed in surface of the semiconductor substrate 1 to be source/drain regions.
At the surfaces of the gate electrode 3 and diffusion layers 5 there are formed a metal silicide film 6 made up of a compound of silicon and a refractory metal such as titanium, tungsten, molybdenum or the like. Respective device formation regions are separated by a device isolating insulating film 7 and surfaces of the formed devices are covered with an interlayer insulating films 8. The interlayer insulating film 8 is provided with contact holes 9 in the areas over the gate electrode 3 and the diffusion layers 5, immediately under which there are formed impurity diffused layers 10. Additionally, metal interconnection layers 11 as of aluminum alloy are provided in the respective contact holes 9.
It is desirable to use titanium as a referectory metal for forming the metal silicide film 6, because the resistivity of titanium silicide is very low, that is, one-tenth of or less than that of other metal silicides.
Now, a manufacturing process of the salicide transistor will be described in the case where the metal silicide film 6 is formed of titanium silicide with reference to FIGS. 2A to 2E.
Initially, with reference to FIG. 2A an MOS type LDD (Lightly Doped Drain) structure is formed according to the manufacturing process of the general MOS type LDD structure transistor. That is, a transfer gate oxide film 2 is first formed on a p-type semiconductor substrate by the so-called LOCOS (Local Oxidation of Silicon) with a device isolating insulating film 7 surrounding the same. Thereafter, polysilicon is deposited over the entire surface of the transfer gate oxide film 2 to a certain film thickness by low pressure CVD, and then formed into a gate electrode 3 by photoetching. Subsequently, n-type impurities such as phosphorus ion are implanted in surface of the semiconductor substrate 1 with the gate electrode 3 as mask to form a diffusion layer 5a of low concentration. Furthermore, an insulating film made of silicon dioxide or the like is deposited over the entire surface of the semiconductor substrate 1 by CVD and formed into sidewalls 4 by vertical anisotropic etching. Additionally, n-type impurities such as arsenic ion are then implanted in the surface of the semiconductor substrate 1 with the gate electrode 3 and the sidewalls 4 as mask to form further diffusion forming layer 5b of high concentration. Usually, heat treatment at above 900.degree. C. is done for the activation of the implanted impurities, and thus the structure shown in FIG. 2A is completed.
Secondly, a titanium film 12 of a predetermined thickness is formed over the entire surface of the resulting MOS type LDD structure by sputtering or the like (FIG. 2B). This titanium film 12 is generally formed to a thickness of 10 to 100 nm.
Following the above, heat treatment at 600.degree. C. to 700.degree. C. is done in nitrogen atmosphere. This heat treatment may also be done in vacuum or argon atmosphere. At this moment, mono-silicide or disilicide of titanium, i.e. TiSi or TiSi.sub.2 is formed in the areas where the titanium film 12 contacts with any silicon surface, or at the surfaces of the gate electrode 3 and the diffusion layers 5 which have remained uncovered by the insulating films. On the other hand, the titanium film 12 over the regions covered with the silicon oxide films, or on the surfaces of the device isolating insulating film 7 and the sidewalls 4 remains unreacted or is reacted with nitrogen to form titanium nitride (TiN). Therefore, by removing the TiN and unreacted Ti with a proper solution such as mixture of sulfuric acid and hydrogen peroxide solution, titanium silicide can be left formed only over the gate electrode 3 and the diffusion layers 5 to form source/drain regions (FIG. 2C). Meanwhile, the titanium silicide at this moment comprises TiSi as well as TiSi.sub.2.
Further heat treatment at about 800.degree. C. for a predetermined time in nitrogen atmosphere (vacuum or argon atmosphere is also possible) enables a complete titanium disilicide (TiSi.sub.2) layer 13 (referred to simply as "titanium silicide layer 13" hereinafter) to be formed.
Next, an interlayer insulating film 8 made of ailicate glass is deposited by CVD and then annealing at temperatures of 800.degree. C. to 1,000.degree. C. is done (FIG. 2D). This annealing is indispensable to planalize the interlayer insulating film 8 by reflow, for the sake of enhancing the reliability of a metal interconnectin layer 11 formed thereon.
Subsequently, contact holes are opened by, for example, etching in predetermined portions over the gate electrode 3 and the diffusion layers 5, through which impurities of the same conductivity type as that of diffusion layers 5 or n-type (such as phosphorus) are implanted into the semiconductor substrate 1.
Subsequently, further heat treatment at 800.degree. C. to 1,000.degree. C. is done to thermally diffuse the impurities implanted immediately under the contact holes 9, thereby forming impurity diffused layers 10 (FIG. 2E). This process enables the n-type impurity diffused layers 10 to be formed under the contact holes even when they have been opened in the areas a little shifted from the diffusion layers 5 to cover the device isolating insulating films 7 so that the contact resistance therein can be reduced. Also, this process has the effect to decrease the junction leakage current in PN junctions which may be a problem encountered, for example, when the concentration of the diffusion layers 5 immediately under the contact holes 9 is not sufficient. Accordingly, this process is called SAC (Self-Aligned Contact) due to the resulting self-alignment.
Finally, a metal interconnection layer 11 is formed of aluminum or the like thereby to complete the manufacturing of a salicide transistor (FIG. 2F).
In the salicide transistor formed as described above with the use of titanium silicide, when formed consistently to have good quality, the silicide film can reduce resistivity in the gate electrode 3 and the diffusion layers 5 down to one-tenth or less than that of other metal suicides due to its low resistivity. Therefore, an MOS type transistor of higher performance can be obtained.
Application of titanium silicide cannot be limited to the above mentioned salicide transistor, but also effective for interconnections of other semiconductor devices which require a heat resisting property. For example, it can be applied to formation of bit lines in a DRAM (Dynamic Random Access Memory) with stacked capacitor cells. There is further applicability of titanium silicide in the interconnections between separate devices such as a planar structure, for example, of a complementary MOS transistor and other general interconnections in semiconductor devices. Consequently, there has been an increasing demand for application of the titanium silicide in a wide range of the fields for semiconductor circuit formation where lower resistivity is required for electrodes or interconnections with the increased integration.
However, in forming a salicide transistor with the application of titanium silicide according to the above mentioned conventional manufacturing process, there has been encountered the following problems.
First, the annealing at 800.degree. C. to 1,000.degree. C. immediately after the interlayer insulating film 8 has been deposited by CVD brings about agglomeration in the titanium silicide 13 as shown in FIG. 2D. The causes of this agglomeration may be as follows. The titanium silicide film 13 heated up to elevated temperatures of 800.degree. C. or higher begins to soften and flow. This flow occurs, as indicated by arrows in FIG. 3A, in the directions of surface or interface with the diffusion layer 5 of the titanium silicide film 13. That brings about a most stable situation where the interface energy both between the titanium silicide film 13 and the interlayer insulating film 8 and between the titanium silicide film 13 and the semiconductor substrate 1 is minimized, or deformation of the titanium silicide film 13 occurs such that the surface area is reduced to a minimum. Therefore, the film gets partially agglomerated with the other remaining excessively thin parts as shown in FIG. 3B. This phenomenon may even make the titanium silicide film 13 completely discontinuous (FIG. 3C), as well as destroying consistency of the film thickness. Accordingly, conductivity of the titanium silicide film 13 is degraded while the resistance value thereof is significantly increased. Such agglomeration in annealing of the titanium silicide with the resulting resistance value increase has been described in detail, for example, in "SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 133, No. 12, p.2621-p.2625".
As an example, the changes in resistance value as a function of annealing time is shown in a diagram of FIG. 4 with respect to a case where a 200 nm thick silicon dioxide film is deposited by CVD on about 48 nm thick titanium silicide layer and then annealed at 900.degree. C. in nitrogen atmosphere. It can be understood from the diagram that the resistance value is considerably increased with the lapse of annealing time.
Such agglomeration of the titanium silicide 13 occurs again in the heat treatment to be given when the impurity diffused layer 10 is formed, with further outstanding undesirable effects. More specifically, as the flow goes ahead, the clustered agglomerations may get greater and extend through the diffusion layer 5 as shown in FIG. 3C, even encroaching upon the p-type region of the semiconductor substrate 1. When it comes to such a state, another problem of increased junction leakage current in the PN junction arises.
These phenomena not only prevent attaining the object of the salicide transistor to lower resistivity of the gate electrode 3 and the source/drain regions, but lead to malfunction of the transistor due to the leakage current.
The above mentioned agglomeration in the titanium silicide film is not limited to the case of salicide transistor formation only, but it is a common problem in forming of the above described bit lines in memory cells or general refractory interconnections using titanium silicide. This is because annealing at 800.degree. C. or higher is frequently required in those cases to diffuse the implanted impurities or lower the contact resistance in contact portions.
The agglomeration in annealing at 800.degree. C. to 1,000.degree. C. is a phenomenon characteristic of titanium silicide only and does not occur in other silicides of high melting point metals such as tungsten or molybdenum. Accordingly, this agglomeration problem has been an obstacle to effectively apply titanium silicide of low resistivity to the salicide transistor instead of tungsten silicide and the like.