1. Field of the Invention
The present invention relates to the field of semiconductor devices, and more specifically, to a MOSFET with a composite gate electrode which is compatible with standard CMOS processing.
2. Description of Related Art
Transistors are well-known in the art. Transistors are the building blocks of all integrated circuits. Modern integrated circuits interconnect literally millions of transistors together to perform a wide variety of functions. The performance and reliability of a specific integrated circuit is directly related to the performance and reliability of the transistors of which it is comprised. Thus, in order to provide better performing integrated circuits in the future, one needs to improve the electrical characteristics of transistors.
FIG. 1 shows a cross-sectional view of a well-known lightly doped drain (LDD) metal oxide semiconductor (MOS) transistor 100. Transistor 100 has a standard polysilicon gate electrode 110. Transistor 100 has in the past been a very popular and widely used transistor because of its polysilicon gate electrode 110. An advantage of the polysilicon gate electrode is that it allows the transistor to be fabricated with well-known and extremely manufacturable standard CMOS processes. For example, the polysilicon gate allows a self-aligned LDD process to be utilized since the polysilicon gate can adequately mask the channel region of the transistor from LDD implants. A self-aligned process allows the LDD region of the transistor to always be perfectly aligned with the gate of the transistor regardless of mask alignment tolerances. Another advantage of polysilicon gate 100 is that a self-aligned silicide process can be used to form silicide 112 on the source, drain, and gate of the transistor. Transistor 100 is compatible with the self-aligned silicide process because polysilicon gate 110 is not vulnerable to the etch used to remove unreacted metal, which is required in the metallic silicide process.
Unfortunately, however, the performance of the standard polysilicon gate transistor 100 is poor due to polysilicon depletion effects. Polysilicon depletion effects reduce the amount of gate voltage applied across the gate oxide. This in turn reduces the drive current of the transistor. Since speed is directly proportional to the drive current, the speed performance of the standard polysilicon gate transistor is poor. The speed performance of the standard polysilicon gate transistor 100 is poor due to polysilicon depletion effects,
FIG. 2 is a cross-sectional view of another well-known transistor 200. Transistor 200 has a metal gate electrode 210. Metal gate electrodes are beneficial because their electrical characteristics are superior to doped polysilicon gate electrodes. Unfortunately, however, such metal gates are incompatible with modern CMOS processing techniques. For example, a self-aligned source/drain implant can not be used in metal gate devices because metal gates can not adequately mask the channel region from impurity doping during the implant. Additionally, metal gate electrodes are incompatible with self-aligned silicide processes because they can be damaged by the etch, which is required to remove the unreacted metal, in the silicide process.
Thus, what is desired is a high performance semiconductor transistor which does not exhibit polysilicon depletion effects and which is compatible with a standard CMOS fabrication process.