Logic circuit design engineers continue to seek a universal integrated logic circuit design which would greatly reduce the requirement of using many different types of integrated logic circuits to implement logic functions. The ideal universal integrated logic circuit would fulfill this requirement by providing in one integrated circuit device the capability of generating any arbitrary Boolean logic function in factored or unfactored form having a single or multiplicity of outputs which can operate in combinational, sequential, or asynchronous modes.
One well-known universal integrated logic circuit arrangement called a programmable logic array (PLA) consists of one or more arrays of logic circuits having inputs and outputs which are interconnected via a mask or an electrical programmable interconnection matrix. The interconnection matrix is essentially rectangular in shape with all columns and row conductors extending the full height and width of the matrix. The number of columns and rows of the interconnection matrix is determined by the number of logic circuit elements on the PLA. Undesirably, in the larger PLAs the interconnection matrix occupies a larger percentage of the area of the PLA. Moreover, in these large PLAs only a smaller percentage of the interconnection matrix is utilized for the actual logic circuit interconnections. This increasingly inefficient utilization of the interconnection matrix in large PLAs results in a larger cost per logic circuit function.
Prior art techniques for increasing the efficient use of the interconnection matrix include splitting the rows and column lines of the interconnection matrix so that separate logic functions can be performed on the signals present on each end of the split lines.
U. S. Pat. No. 3,987,287 issued on Oct. 19, 1976 to D. T. Cox et al and U. S. Pat. No. 3,816,725 issued on June 11, 1974 to D. L. Greer are representative of such a technique. Despite the improvements resulting from the use of the above technique there is a continuing need to more efficiently utilize the interconnection matrix of a PLA.