1. Field
Various embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a stacked structure of conductive patterns.
2. Description of Related Art
A semiconductor device may include a memory device capable of storing data. The memory device may include memory cells. For a high integration of the semiconductor device, the memory cells may be arranged in three dimensions. The memory cells arranged in three dimensions may be coupled to conductive patterns that are disposed at different levels. The conductive patterns may form a stepped structure and be stacked on top of one another.
The stepped structure may be formed of one ends of the conductive patterns. The one ends of the conductive patterns that form the stepped structure may be defined as pad regions. The pad regions of the conductive patterns may be coupled to respective contact plugs.
Portions of the conductive patterns may be perforated in the pad regions by the contact plugs. In this case, the contact plug that passes through the conductive pattern in the pad region may cause a bridge failure. For example, the bridge failure may occur when a target conductive pattern among the contact patterns is electrically coupled with a lower conductive pattern disposed below the target conductive pattern. The operational reliability of the semiconductor device may deteriorate due to such a bridge failure.