The present invention relates to an instruction execution control method and information processing apparatus for monitoring information about the completion of synchronization among processors, and selectively causing a specific instruction of the subsequent group of instructions to wait until the completion of synchronization is indicated when the processors are operated in synchronism with each other for synchronous execution of their respective processes in a computer system including a plurality of processors.
The synchronized operation of the processors for synchronous execution of processes has conventionally been done between an instruction stream of a synchronization notifying processor issuing a SYNC request and an instruction stream of a processor which is subjected to synchronization.
More specifically, in response to a Store instruction (ST: instruction 1), the processor, which will subsequently issue a SYNC request, outputs data of a preliminary process or a result of a process to the main storage, and when a SYNC instruction (instn. 2) is issued, this SYNC instruction serves to ensure that writing of the above-mentioned result into the main storage is finished. Then, the completion of synchronization is notified by a Store instruction (ST) to the synchronized-side processor, to more specific, by the use of communication means between the two processors or according to a value written into the specified location in the common (shared) storage area in the main storage, for example.
On the other hand, by using an LD (Load) instruction (instn. 4), the synchronized-side processor receives information about synchronization completion through the communication means between the two processors or reads this information which is written in the above-mentioned location of the common storage, a representative one of which is the main storage, or waits for synchronization completion by monitoring the common storage by repeating the Load instruction (instn. 4) by issuing a BC (conditional Branch) instruction (instn. 5) until the completion of synchronization is notified from the synchronization notifying processor. When this information about the completion of synchronization is transferred between the two processors, the synchronized-side processor gets out of a spin loop of Load (instn. 4) for monitoring and conditional Branch (instn. 5), and performs subsequent processes.
The above-mentioned spin loop is used to wait for information about synchronization completion by repeating a condition test incessantly. In a synchronization operation for exclusive access control, a scheme for attaining synchronization is adopted in which the processors wait for information about the completion of synchronization which gives an access permission to an exclusive location, that is, a location where that information is written by a Store instruction prior to a TS instruction by using a spin-lock-wait operation, which is achieved by a combined use of a TS (Test and Set) instruction (instn. 1) to test an area where information about synchronization completion and a BC (conditional Branch) instruction (instn. 2).
More specifically, the Test and Set instruction is used to test an area where synchronization information is written and read, in other words, to test a flag area in the main storage (to be more concrete, a value is input and evaluated), and set (1 is written if the evaluated value is 0). The Test and Set instruction is an instruction with a lock to prohibit access to the flag area from another processor. As has been described, in the spin loop method or the spin-lock-wait method, waiting for information about the completion of synchronization is done by using a Load information to monitor this information and a Branch instruction to repeat the Load instruction until synchronization completion is notified.
In the conventional synchronization method mentioned above, after a Load instruction for monitoring the common storage area and a Branch instruction for repeating the Load instruction have been set, the next instruction in the remaining instructions of the program is not performed until information about the completion of synchronization is given.
In the synchronized-side processor, however, the only instruction which needs to be put in the waiting state until information about the completion of synchronization is issued is a Load instruction which is likely to transfer information from the main storage to the register or the cache storage in the synchronized-side processor before updating when the synchronization notifying processor updates the contents of the main storage by a Store instruction to store data of a preliminary process or a result of a process. In spite of this, an arithmetic instruction or a Branch instruction which is nothing to do with the Load instruction is forced to wait to no purpose.
To put differently, when information about the completion of synchronization is received, an arithmetic instruction or a Branch instruction which needs to be executed in advance regardless of the order of instructions written in the program. Accordingly, the efficiency of instruction execution in synchronized operations is decreased.