Static random access memory (SRAM) is commonly utilized in prior art computer systems for storing data. Generally, SRAM memory is a type of memory that is very reliable and very fast. Unlike dynamic random access memory (DRAM), SRAM does not need to have its electrical charges constantly refreshed. As a result, SRAM memory is typically faster and more reliable than DRAM memory. For example, while DRAM supports access times (i.e., the time a program or device takes to locate a single piece of information and make it available to the computer for processing) of about 60 nanoseconds, SRAM of the prior art may provide access times as low as 10 nanoseconds. In addition, SRAM's cycle time (i.e., a measurement of how quickly two back-to-back accesses of a memory chip can be made) is typically much shorter than that of DRAM because it does not need to pause between accesses. Unfortunately, SRAM memory is generally much more expensive to produce than DRAM memory. Due to its high cost, SRAM is typically implemented only for the most speed-critical parts of a computer, such as the memory cache. However, SRAM memory may be implemented for other memory components of a computer system, as well.
FIG. 1 illustrates a typical SRAM cell 100 of the prior art. The SRAM structure of FIG. 1 is a typical 6-T (6 transistor) SRAM cell comprising field effect transistors (FETs) 102, 104, 106, 108, 110, and 112. The SRAM structure 100 of FIG. 1 is well-known in the art and is commonly implemented in integrated circuits of the prior art. The SRAM cell 100 of FIG. 1 is a memory cell capable of storing one bit of data (i.e., a logic 1 or a logic 0). Thus, many of such SRAM cells 100 are typically implemented within a system to provide the desired amount of SRAM memory. As shown, a BIT line, WORD line, and NBIT line are typically included in the structure 100. The BIT line, which may also be referred to herein as a "data carrier," is a line on which data to be read from or written to the SRAM cell 100 is placed, and the NBIT line, which may also be referred to herein as a "complementary data carrier," is the complement (opposite voltage value) of the BIT line. Typically, the BIT line is held to a high voltage level (i.e., a logic 1), unless it is actively pulled to a low voltage level (i.e., a logic 0). For instance, when writing data to the SRAM cell 100, the BIT line is actively driven low by an outside source (e.g., an instruction being executed by the processor) if the outside source desires to write a 0 to the SRAM cell 100. Otherwise, if an outside source desires to write a 1 to the SRAM cell 100, the BIT line remains high. Thereafter, the WORD line is fired (e.g., caused to go to a high voltage level), at which time the value of the BIT line is written into the SRAM cell 100.
When reading data from the SRAM cell 100, the WORD line is fired, and the BIT line is driven by the SRAM cell. That is, the BIT line is pulled low by the SRAM cell 100 if the data stored therein is a 0, and the BIT line remains high if the value stored in the SRAM cell 100 is a 1. More specifically, when reading data from the SRAM cell 100, the BIT line is pulled to a low voltage value by N-channel FET (NFET) 102 if the data stored in the SRAM cell 100 is a 0. However, if the value stored in the SRAM cell 100 is a 1, the BIT line remains at a high voltage value.
Typically, many SRAM cells, such as SRAM cell 100, are connected to a single BIT line. For example, 256 SRAM cells are commonly connected to a single BIT line. As a result, a full rail discharge does not occur quickly on the BIT line when it is pulled to a 0. That is, when the BIT line is being pulled low for a particular SRAM cell, the other 255 SRAM cells connected to the BIT line present more capacitance (i.e., parasitic capacitance) on the BIT line, thereby preventing it from discharging quickly. Thus, for example, if one SRAM cell is attempting to drive the BIT line to a low voltage value (logic 0), the other SRAM cells connected to the BIT line may present capacitance on the BIT line thereby preventing it from fully discharging to a low voltage value quickly. Because the capacitance resulting from the many SRAM cells connected to a BIT line may effect the value that is achieved for a particular SRAM cell, circuitry is required in prior art implementations to detect whether a particular voltage level is a logic 1 or a logic 0. That is, because the BIT line can not fully discharge to provide a "true" 0, circuitry is required to determine whether a detected value on the BIT line is to be interpreted as a 0. Thus, a sense amp is typically utilized in prior art designs to detect whether the value on the BIT line is a logic 1 or a logic 0 by recognizing slight value changes in the BIT line. More specifically, such a sense amp determines whether a value on the BIT line is to be interpreted as a logic 0 or logic 1, and the sense amp then actively converts the value on the BIT line to a "true" logic 0 or logic 1 voltage value. However, implementing a sense amp to correctly detect a logic 1 and logic 0 in such a prior art design is generally a complex and time consuming task. Accordingly, the time required for implementing a sense amp to detect the correct value of the BIT line in prior art implementations effectively increases the cost associated with such prior art implementations. Additionally, the sense amp circuitry itself adds to the cost of the prior art implementation and also consumes valuable surface space within such prior art designs.
In the prior art, SRAM memory is commonly implemented in banks (or "partitions"), with each bank comprising multiple groups of SRAM memory cells. For example, a memory bank of the prior art may comprise four groups of SRAM memory with each group comprising 256 SRAM memory cells 100. Therefore, circuitry is commonly implemented in prior art designs to select a particular group of memory within a memory bank to access (e.g., in order to perform a read or write to a memory cell within the selected group). That is, circuitry is typically implemented in prior art designs to enable and disable a group of SRAM memory for read/write operations. For example, suppose an instruction desires to write data to a particular memory cell located within a first group of a memory bank that comprises four groups of memory cells. Circuitry is typically implemented to enable the first group of SRAM memory cells for read/write operations and disable the remaining three groups of SRAM memory cells.
Turning to FIG. 2A, a typical implementation for enabling/disabling a SRAM memory group is illustrated. As shown, circuitry is coupled to the BIT line of the SRAM structure 100. Even though only SRAM cell 100 is shown, it should be understood that many such SRAM cells may be connected to the BIT line to form a group of SRAM cells. A precharger P-channel FET (PFET) 20 is coupled to the BIT line to precharge the BIT line to a high voltage level. The BIT line is received by an inverter 26, which comprises PFET 10 and NFET 12. The output of inverter 26 is fed back to a PFET holder 22, which works to hold the BIT line to a high voltage level. When a read or write operation is desired for a particular group of SRAM cells, the precharger PFET 20 for that group of SRAM cells is turned off, thereby allowing the BIT line to be utilized for writing/reading data to/from SRAM cells within such group. That is, the precharger PFET 20 is turned off to enable a group of SRAM cells for read/write operations. Otherwise, for the groups of SRAM cells for which a read/write operation is not being performed, the precharger PFETs 20 for such groups remain turned on, thereby disabling such other groups of SRAM cells for read/write operations.
To further illustrate the operation of this prior art design, suppose that a processor is executing an instruction that desires to read the data of SRAM cell 100. Therefore, the precharger PFET 20 is turned off and the WORD line is fired (e.g., transitions to a high voltage value) to read the data from SRAM cell 100. When the WORD line is fired, if a 0 is to be read from the SRAM cell 100, the pull down NFET 102 begins to pull the voltage level of the BIT line down. However, as the pull down NFET 102 attempts to pull down the BIT line, the PFET holder 22 is attempting to hold the BIT line to a high voltage. Accordingly, the PFET holder 22 fights against the pull down NFET 102. This conflict between PFET holder 22 and NFET 102 slows down the speed of the BIT line falling (i.e., slows the transition of the BIT line), thereby increasing the amount of time required to perform the read instruction. Additionally, such conflict increases the power consumption of SRAM 100 because static current is dissipated through the PFET 22 going through the NFET 102 to ground.
As a further example of this prior art design, suppose that a processor is executing an instruction that desires to write data to SRAM cell 100. Because an instruction desires to write to SRAM cell 100, precharger PFET 20 is turned off to enable the group of SRAM cells containing SRAM cell 100. The data to be written to SRAM cell 100 is then placed on the BIT line. That is, the instruction actively drives the BIT line to the value to be written to SRAM cell 100 for read/write operations. Suppose that a 0 is to be written to SRAM cell 100. As the instruction attempts to drive the BIT line to a low voltage value (i.e., to a logic 0), the PFET holder 22 attempts to hold the BIT line to a high voltage. Accordingly, the PFET holder 22 fights against the instruction attempting to pull down the BIT line. This conflict between PFET holder 22 and the instruction attempting to pull down the BIT line slows down the speed of the BIT line falling (i.e., slows the transition of the BIT line), thereby increasing the amount of time required to perform the write instruction. Additionally, such conflict further increases the power consumption of SRAM 100.
It should be recognized that the implementation for the NBIT line of the SRAM structure 100 operates in a similar manner. To illustrate this point further, attention is directed to FIG. 2B. As shown in FIG. 2B, circuitry is coupled to the NBIT line of the SRAM structure 100. Even though only SRAM cell 100 is shown, it should be understood that many such SRAM cells may be connected to the NBIT line to form a group of SRAM cells. A PFET 21 is coupled to the NBIT line to precharge the NBIT line to a high voltage level. The BIT line is received by an inverter 27, which comprises PFET 11 and NFET 13. The output of inverter 27 is fed back to a PFET holder 23, which works to hold the NBIT line to a high voltage level. Accordingly, the problems discussed above for the BIT line, such as the relatively long time required to transition the BIT line to a low voltage value and the added power consumption, are also present for the NBIT line.
As an example, suppose that a processor is executing an instruction that desires to read the data of SRAM cell 100. Therefore, the precharger PFET 21 is turned off and the WORD line is fired to read the data from SRAM cell 100. When the WORD line is fired, if a 1 is to be read from the SRAM cell 100, the BIT line remains at a high voltage value and the NFET 112 begins to pull the voltage level of the NBIT line down. However, as the pull down NFET 112 attempts to pull down the NBIT line, the PFET holder 23 is attempting to hold the NBIT line to a high voltage. Accordingly, the PFET holder 23 fights against the pull down NFET 112. This conflict between PFET holder 23 and NFET 112 slows down the speed of the NBIT line falling (i.e., slows the transition of the NBIT line), thereby increasing the amount of time required to perform the read instruction. Additionally, such conflict increases the power consumption of SRAM 100 because static current is dissipated through the PFET 23 going through the NFET 112 to ground.
As discussed above, prior art designs for enabling/disabling SRAM memory are problematic because such designs require an undesirably long time for a BIT line to transition in response to the WORD line firing. As a result, an undesirably long time is required to perform a read or write instruction to the SRAM memory. Furthermore, such prior art designs for enabling/disabling SRAM memory result in an undesirably high power consumption. Furthermore, because the BIT and NBIT lines do not fully discharge to a low voltage value in prior art implementations, sense amp circuitry is typically required to receive the BIT and NBIT lines and detect the value (i.e., a logic 0 or logic 1) for each line. Such sense amp circuitry is typically complex, and therefore increases the cost of implementing prior art designs. Also, given that such sense amp circuitry is typically relatively large in size, an undesirably large amount of surface area is consumed by the required sense amp circuitry.
Additionally, prior art designs for enabling/disabling SRAM memory require an undesirably large amount of circuitry. For instance, as shown in FIGS. 2A and 2B, such prior art circuitry typically comprises two inverters (i.e., inverter 26 and inverter 27), which each comprise a PFET and a NFET. Additionally, the prior art circuitry further includes two holder PFETs (i.e., holder PFET 22 and holder PFET 21). Accordingly, such prior art design for enabling/disabling SRAM memory, requires six FETs to bold a BIT line and NBIT line for each group of SRAM memory cells implemented. Therefore, if four groups of SRAM memory cells are implemented, a total of 24 FETs are required in the enabling/disabling circuitry to hold the BIT lines and NBIT lines to the proper values. Thus, a relatively large number of components (FETs) are required to be implemented within the prior art design for enabling/disabling SRAM memory. Such a large number of components consumes an undesirably large amount of surface area of a chip and results in an undesirably high cost to implement the design.