1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, to a semiconductor memory device in which a power supply block is mounted, capable of performing a precharge operation at a high speed in a case where a precharge potential of a bit line is different from a midpoint potential of the potentials of paired bit lines in a dynamic random access memory (DRAM). The present invention also relates to a semiconductor device with such a semiconductor memory device and a logic circuit device therein.
2. Description of the Related Art
Hereinafter, the circuit configuration and operation of a semiconductor memory device in which a conventional power supply block is mounted will be described with reference to the drawings.
FIG. 13 is a functional block diagram showing a configuration of a general DRAM 1300. In FIG. 13, reference numeral 1301 denotes a memory cell array, 1302 denotes a memory cell array block, 1303 denotes a power supply block, 1304 denotes a row decoder, 1305 denotes a column decoder, 1306 denotes a control circuit, 1307 denotes an I/O buffer, CLK denotes an external clock signal, NRAS denotes a row address strobe signal, NCAS denotes a column address strobe signal, NWE denotes a writing control signal, ADDR denotes an address, REF denotes a refresh control signal, RAD denotes a row address signal, CAD denotes a column address signal, WEN denotes a writing enable signal, SE denotes an access control signal, DI denotes a data input signal, DO denotes a data output signal, VCP denotes a memory cell plate voltage, and VBP denotes a bit line precharge voltage.
The memory cell array 1301 includes a plurality of memory cell array blocks 1302. Each memory cell array block 1302 is supplied with voltages required for the memory cell array 1301, such as a bit line precharge voltage VBP, a memory cell plate voltage VCP, and the like, from the power supply block 1303.
Furthermore, each memory cell array block 1302 is controlled with a bit line precharge starting signal NEQ, sense amplifier starting signals SAN and SAP, and a word line driving signal WL [63:0] from the row decoder 1304. Furthermore, each memory cell array block 1302 is connected to the column decoder 1305.
The row decoder 1304 is supplied with the access control signal SE and the row address signal RAD from the control circuit 1306. The column decoder 1305 is supplied with the writing enable signal WEN and the column address signal CAD from the control circuit 1306.
The control circuit 1306 is supplied with the external clock signal CLK, the row address strobe signal NRAS, the column address strobe signal NCAS, the writing control signal NEW, the address ADDR, and the refresh control signal REF.
The column decoder 1305 is connected to the I/O buffer 1307. The I/O buffer 1307 receives the data input signal DI from outside, and outputs the data output signal DO to outside.
FIG. 14 is a circuit diagram of the memory cell array block 1302. In FIG. 14, reference numeral 1400 denotes a memory cell, 1401 denotes a sense amplifier, 1402 denotes a bit line precharge circuit, BL[i] (i=0, 1, 2, . . . , n) denotes bit lines, /BL[i] (i=0, 1, 2, . . . , n) denotes bit lines to be paired with BL[i], 1403 denotes an access transistor, and 1404 denotes a capacitor.
The memory cell 1400 is composed of one P-channel transistor 1403 and one capacitor 1404. A source of the P-channel transistor 1403 is connected to the bit line BL[i] or /BL[i], a drain thereof is connected to the capacitor 1404, and a gate thereof is supplied with the word line driving signal WL[i] (i=0, 1, . . . ). The other node of the capacitor 1404 is supplied with the memory cell plate voltage VCP.
The sense amplifier 1401 is a general cross-coupling type, and is connected to the bit lines BL[i] and /BL[i] to be paired. The sense amplifier 1401 is controlled with the sense amplifier starting signals SAN and SAP.
The bit line precharge circuit 1402 is composed of three P-channel transistors: a transistor having a source connected to the bit line BL[i], a drain connected to the bit line /BL[i], and a gate supplied with the bit line precharge starting signal NEQ; a transistor having a source connected to the bit line BL[i], a drain supplied with the bit line precharge voltage VBP, and a gate supplied with the bit line precharge starting signal NEQ; and a transistor having a source supplied with the bit line precharge voltage VBP, a drain connected to the bit line /BL[i], and a gate supplied with the bit line precharge starting signal NEQ (see JP 2003-157674 A).
FIG. 15 is a schematic view showing a circuit block and a power supply wiring net of the bit line precharge voltage VBP in a conventional semiconductor memory device. In FIG. 15, reference numeral 1500 denotes a memory cell array having the same configuration as that of the memory cell array 1301 shown in FIG. 13, 1501 denotes a power supply block, 1502 denotes a power supply unit (PU), 1503 denotes a charging/discharging control circuit (CDC), 1504 denotes a reference voltage generation circuit (RVG), and 1505 denotes a precharge voltage pumping circuit (PVP).
On the memory cell array 1500, power supply wires are provided for the bit line precharge voltage VBP to be supplied to the bit line precharge circuit 1402, placed in a plurality of memory cell array blocks 1302. VBP[i] (i=0, 1, 2, . . . , n−1, n) denotes bit line precharge power supply wires, which are represented as VBP[0], VBP[1], . . . , VBP[n−1], and VBP[n] from the side close to the power supply block 1501. The bit line precharge power supply wires VBP[i] are placed in a column direction on a wiring layer of an upper layer of each memory cell array block 1302 (represented by a solid line in FIG. 15). The bit line precharge power supply wires VBP[i] are connected respectively in a row direction with metal wires (represented by broken lines in FIG. 15) so as to decrease an impedance. The bit line precharge power supply wires VBP[i] are placed in a mesh shape, and the thickest possible wires are used. The bit line precharge power supply wires VBP[i] are connected to the bit line precharge voltage generation circuit 1504.
FIG. 16 is a circuit diagram showing internal configurations of the bit line precharge voltage generation circuit 1504 (for example, see JP 2000-30450 A) and the precharge voltage pumping circuit 1505 shown in FIG. 15. In FIG. 16, the precharge voltage pumping circuit 1505 is composed of a pumping capacitor 1600, a first P-channel transistor 1601, a second P-channel transistor 1602, a first N-channel transistor 1603, an inverter 1604, and a buffer inverter 1605. CPND denotes a charge accumulation node, and AP, NAP, and ACP denote transfer gate connection signals.
One electrode of the pumping capacitor 1600 is connected to drains of the first P-channel transistor 1601, the second P-channel transistor 1602, and the first N-channel transistor 1603. The other electrode of the pumping capacitor 1600 is dropped to a ground potential VSS. A capacitance Ccap of the pumping capacitor 1600 is required to accumulate (VBPREF−½ VDD)×Cbl, which is equal to the charge required for charging the potential of paired bit lines BL[n], /BL[n] to the bit line precharge reference voltage VBPREF, assuming that the total capacitance of the paired bit lines BL[n], /BL[n] to be simultaneously precharged is Cbl. During operation, considering the charge supplied from an operational amplifier 1607, the pumping capacitor 1600 having the capacitance Ccap satisfying the relationship: Ccap<(VBPREF−½ VDD)/(VDD−VBPREF)×Cbl is used.
A gate of the first P-channel transistor 1601 is supplied with a transfer gate connection signal AP, and a source thereof is supplied with a supply voltage VDD. A gate of the second P-channel transistor 1602 is supplied with a transfer gate connection signal NAP, and a source thereof is connected to the bit line precharge power supply wire VBP[0]. A gate of the first N-channel transistor 1603 is supplied with a transfer gate connection signal AP, and a source thereof is connected to the bit line precharge power supply wire VBP[0]. The inverter 1604 receives the transfer gate connection signal AP, and outputs the transfer gate connection signal NAP. The buffer inverter 1605 is composed of inverters in even-number stages connected in series. The buffer inverter 1605 receives the transfer gate connection signal ACP and outputs the transfer gate connection signal AP.
The bit line precharge voltage generation circuit 1504 is composed of a reference voltage generation circuit 1606, an operational amplifier 1607, and a P-channel transistor 1608. VBPREF denotes a bit line-precharge reference voltage, VOUT denotes a bit line precharge holding voltage, and PEN denotes a driver enable signal. The reference voltage generation circuit 1606 generates the bit line precharge reference voltage VBPREF and the bit line precharge holding voltage VOUT. The bit line precharge reference voltage VBPREF is supplied to an inversion input terminal (−) of the operational amplifier 1607, and the bit line precharge holding voltage VOUT is supplied to the bit line precharge power supply wire VBP[0]. A non-inversion input terminal (+) of the operational amplifier 1607 is connected to the bit line precharge power supply wire VBP[0]. The driver enable signal PEN is output from the operation amplifier 1607, and input to the gate of the P-channel transistor 1608. A source of the P-channel transistor 1608 is supplied with a supply voltage VDD, and a drain thereof is connected to the bit line precharge power supply wire VBP[0].
FIG. 17 is a circuit diagram showing an internal configuration of the charging/discharging control circuit 1503 shown in FIG. 15. In FIG. 17, reference numeral 1701 denotes a first delay element, 1702 denotes a second delay element, 1703 denotes an inverter, and 1704 denotes a NOR element. The first delay element 1701 delays the bit line precharge starting signal NEQ by a delay time τ1, and sends it to the second delay element 1702 and one input terminal of the NOR element 1704. The second delay element 1702 delays an input signal by a delay time τ2, and sends it to the inverter 1703. An output signal of the inverter 1703 is sent to the other input terminal of the NOR element 1704. The NOR element 1704 outputs the transfer gate connection signal ACP.
Next, the operation during precharge of a bit line in a semiconductor memory device configured as described will be described with reference to FIG. 18.
FIG. 18 is a timing chart showing a voltage and a current of a signal in each portion in FIGS. 14 to 17.
When the bit line precharge starting signal NEQ is lowered to activate the bit line precharge circuit 1402, the potentials of paired bit lines BL[n], /BL[n] set to be VDD and VSS, respectively, by the sense amplifier 1401 are equalized and attempted to be charged to the potential of ½ VDD. Simultaneously, the bit line precharge circuit 1402 connects the paired bit lines BL[n], /BL[n] to the bit line precharge power supply wire VBP[n], and attempts to charge them to the bit line precharge voltage VBP. At this time, a current is consumed, and a voltage drop occurs.
When the voltage drop occurs in the bit line precharge power supply wire VBP[n], the voltage drop is transmitted to the bit line precharge power supply wire VBP[0] through the wires connected in a mesh shape. Upon detecting the voltage drop, the operational amplifier 1607 in the bit line precharge voltage generation circuit 1504 is activated. However, it takes a time for a current ia from by the P-channel transistor 1608 to increase.
In the case where the bit line precharge starting signal NEQ is at a high level, the transfer gate connection signal AP in the precharge voltage pumping circuit 1505 is at a low level, whereas the transfer gate connection signal NAP is at a high level. Therefore, the second P-channel transistor 1602 and the first N-channel transistor 1603 are in an OFF state, and the first P-channel transistor 1601 is in an ON state. The charge accumulation node CPND is charged to a high level, and charge is accumulated in the pumping capacitor 1600.
Next, when the bit line precharge starting signal NEQ is lowered, after the delay time τ1 determined by the first delay element 1701 in the charging/discharging control circuit 1503, the transfer gate connection signal AP is turned to be high, and the transfer gate connection signal NAP is turned to be low. The first P-channel transistor 1601 is turned off, and the second P-channel transistor 1602 and the first N-channel transistor 1603 are turned on. Because of this, the pumping capacitor 1600 and the bit line precharge power supply wire VBP[0] are connected to each other electrically, and consequently, a current ib flows. The charge accumulation node CPND is charged to a high level, and the bit line precharge power supply wire VBP[0] is increased in level rapidly by the current ib.
In response to the increase in level, the operational amplifier 1607 changes the operation so as to turn off the P-channel transistor 1608. However, it takes a time for the current ia to decrease.
After the delay time τ2 determined by the second delay element 1702, the transfer gate connection signal AP is turned to be low, and the transfer gate connection signal NAP is turned to be high. The second P-channel transistor 1602 and the first N-channel transistor 1603 are turned off, and the first P-channel transistor 1601 is turned on. The charge accumulation node CPND is charged to a high level, and is provided for the subsequent precharge operation.
Herein, in order to perform a precharge operation at a high speed, it is necessary to accumulate a sufficient charge amount in the pumping capacitor 1600, and hence, a relatively large size is required for the pumping capacitor 1600.
In order to perform a subsequent reading operation stably, it is necessary to perform a precharge operation of the paired bit lines BL[n], /BL[n] within a predetermined period of time. In a conventional semiconductor memory device, it is necessary to perform a pumping operation using the pumping capacitor 1600 with a relatively large size, in order to perform a precharge operation within a predetermined period of time. This makes it difficult to reduce a chip area.