When measuring the time between two events, traditional circuits have used the occurrence of the first event to start a counter which counts clock pulses, and the occurrence of the second event to stop the counter. The value of the counter is then read to determine the time between the events. After reading the value of the counter, the circuit is reset for the next series of events. The time during which the circuit is being reset is called dead time, and during this dead time, occurrences of the events will go unnoticed. The performance of the circuit can be improved considerably if this dead time can be eliminated, thus creating a zero dead time counter. A zero dead time counter must be capable of continuously counting, and be capable of allowing an asynchronous read-out of the counter which does not interfere with counting. When reading the output of the counter asynchronously, a metastability problem occurs if a read-out is attempted at the time the counter is changing value. If the output is latched while one or more bits is changing value, the changing bits could be latched as either a one or zero, thus the output is metastable. This problem is very severe in binary counters, because many stages of the counter of may be changing value simultaneously, for example when a carry is being rippled through the counter. In a binary counter, if the higher order bits are changing at the time of the read-out, a large discrepancy may occur in the count value.
Traditionally, this metastability problem has been solved in one of two ways, as described by David C. Chu in his article "Phase Digitizing: A New Method for Capturing and Analyzing Spread Spectrum Signals", Hewlett Packard Journal, February 1989, page 28 at page 33. Two types of counters can be used for this type of circuit. A traditional binary ripple counter consists of series of cascaded divide-by-two stages. With the frequency halved after each stage, the maximum count rate is effectively determined by the first few stages. Subsequent stages do no affect the maximum count rate, so they can be slow and numerous. The problem with this type of counter is the time required for a carry to ripple through all stages of the counter. If the output of the counter is read while a carry bit is rippling through the counter, the output is metastable and will be indeterminate for all stages that are changing value. The traditional solution to this problem is to allow sufficient time for a carry to propagate through all stages before attempting a read-out, which severely limits the maximum count rate for the counter.
A synchronous counter may also be used to solve the metastability problem. With synchronous counting, a logic network adds one to the current count state so that the next event clocks the counter to the next state immediately. With careful design, the synchronous counter can be read on the fly, since all bits theoretically change at once. With long count chains, however, the logic network becomes complex and unwieldy, and processing time lengthens. Since every bit must be as fast as the fastest bit, power consumption may be severe in this type of circuit.
The approach taken by David Chu in the article referenced above, is to combine a synchronous counter and a ripple counter, and add the complexity to the latching circuit. Chu uses a synchronous counter for the first few stages, typically eight bits, and then uses a ripple counter for the remaining stages. In addition, Chu provides a delay circuit to delay any read-out for a short time after a count pulse is sent to the ripple stages. This delay is sufficiently long to allow a carry to propagate through all ripple stages. When a read-out signal occurs, the bits of the synchronous portion of the counter are read out and latched immediately, while the bits from the ripple portion of the counter are read out after the delay, and thus after the carry has propagated.
While this approach works well for bipolar circuits, it is not suitable for slower, lower power, processes such as CMOS. There is need in the art then for a synchronous counter whose outputs may be asynchronously latched. There is further need in the art for such a counter that can be implemented in a CMOS process. Still another need in the art is for such a counter that can be implemented using low power circuits. Yet another need is for such a circuit with a simplified latching method.