This invention relates to semiconductor device packages and the method of making such packages and more specifically relates to a chip-scale package and method of its manufacture.
Semiconductor device packages are well known for housing and protecting semiconductor die and for providing output connections to the die electrodes. Commonly, the semiconductor die are diced from a large parent wafer in which the die diffusions and metallizing are made in conventional wafer processing equipment. Such die may be diodes, field effect transistors, thyristors and the like. The die are fragile and the die surfaces must be protected from external environment. Further, convenient leads must be connected to the die electrodes for connection of the die in electrical circuits.
Commonly, such die are singulated from the wafer, as by sawing, and the bottom of the die is mounted on and connected to a portion of a lead frame which has identical sections to receive respective die. The top electrodes of the die are then commonly wire bonded to other portions of the lead frame, and a molded insulation housing is then formed over each lead frame section enclosing the die, and permitting lead portions of the lead frame to penetrate through the molded housing to be available for external connection.
It is desirable in many applications that packaged semiconductor devices be as small as possible to enable the mounting of many such devices on a support surface, such as a printed circuit board or an IMS (insulation-metal-substrate) support surface. Devices housed in the conventional manner occupy a much larger area than the area of the die which is housed. It would be very desirable to provide a semiconductor package which offers the same purposes of the conventional housing (of protecting the die and providing convenient external connection to the die electrodes), but which will occupy less surface area on a support surface.