1. Field of the Invention
This invention relates to methods for etching semiconductor substrates, and more particularly to gate recess etching methods used in the fabrication GaAs microwave monolithic integrated circuit (MMIC) chips.
2. Description of the Related Art
GaAs circuits are used primarily for radar and communications applications, both in power amplifiers for transmission and in receive circuitry. It has been established that a higher degree of amplification can be achieved with metal-semiconductor field effect transistors (MESFETs) if the transistor gate is recessed into the GaAs chip, rather than formed on its surface. This type of structure is illustrated in FIG. 1, in which a portion of a GaAs substrate is shown with N+ doped source and drain regions 4 and 6, respective source and drain contacts S and D, and a N-type channel region 8 between the source and drain regions. A recess 10 is formed from the upper substrate surface into the channel region, between and separated from the source and drain regions 4, 6. A metallized gate contact G is established to the floor of the recess.
The dimensions of the recess and gate contact are important factors in determining the characteristics of a power amplifier that employs such a MESFET. Specifically, the dimension "a" between the edges of the gate contact G (in the direction of channel current flow) and the adjacent edges of the recess floor influences the amplifier's operation. In general, a large dimension "a" results in a higher efficiency but lower output power, and a higher breakdown voltage level. Depending upon the ultimate application for the transistor, the dimension "a" is selected to yield an optimum tradeoff among these three performance factors.
While a high degree of accuracy has been achieved in the past in controlling the length of the gate contact G through photolithographic techniques, controlling the width of the gate recess, and thus the dimension "a", has been more difficult. This is because the gate recess is formed by etching through an opening in a photoresist mask, and the profile of the ultimate recess is dependent upon the dimensions of the photoresist opening. However, it is difficult to accurately control the size and shape of this opening. This is because the photoresist process is subject to numerous variables, such as variations in the photoresist thickness, its baking temperature, the intensity of the ultraviolet light used to expose the photoresist, and the concentration of the developer. The difficulty in controlling the "a" dimension makes it difficult to control the performance factors of a power amplifier. Furthermore, different etchants generally have different lateral etch rates relative to their vertical etch rates. It would only be by coincidence that the recess profile associated with a particular etchant would match the optimum profile for a particular application.
A prior effort to optimize the gate recess profile involves a two-step process, in which a shallow, narrow recess is etched with a first mask, followed by replacing the first mask with a second mask through which a narrow recess is etched using the same etchant. This technique is described in DiLorenzo, ed., GaAs FET Principles and Technology, Artech House, Inc., 1982, pages 286-289 and Williams, Gallium Arsenide Processing Techniques, Artech House, Inc., 1984, page 69. While it provides some improvement in the control of the recess dimensions, it is still subject to the variables described above and results in less than optimum yields.
Two types of etchants are currently in popular use for GaAs applications. Their associated etch processes are illustrated in FIGS. 2 and 3. In FIG. 2, a partially completed MESFET has been coated with a layer of photoresist 12. An opening 14 is provided in the photoresist over the intended gate recess area, with a photoresist overhang 16 extending over part of the upper portion of the opening 14 to provide a reduced diameter entrance opening 17. The amount of overhang effects the size of the gate recess, and also of the metallized gate contact that is added after the recess has been established.
FIG. 2 illustrates the type of etching achieved with an etchant such as phosphoric acid (H.sub.3 PO.sub.4). The liquid etchant is introduced into the opening and begins removing the exposed GaAs material. With this type of etchant, the width of the recessed floor is approximately equal to the width of the opening 14, regardless of the recess depth. This is illustrated by etch profiles 18a, 18b and 18c, which represent the shape of the recess at successive stages in the etching process as the recess becomes progressively deeper. It can be seen that, in each case, the recess floor is aligned with the lateral walls of the photoresist opening.
Another etching process in common use, typically employing ammonia hydroxide (NH.sub.4 OH), produces a gate recess that is narrower than the photoresist opening; this is illustrated in FIG. 3. This type of etchant produces a "V-groove" profile, in which the floor of the recess progressively contracts towards a point 20 as the etching proceeds. Three successive stages in the etch process 22a, 22b and 22c are illustrated in FIG. 3, with the floor of the recess becoming progressively narrower at each successive stage.
These two etching processes are described in Gallium Arsenide Processing Techniques, supra, pages 108-122. Unfortunately, both are subject to the variations in recess size, described above, associated with the unpredictability of the photoresist, and then will generally not produce an optimum recess profile for a given application. While the double-mask technique referred to above can be used with either etchant, it involves an extra process step and thus increases costs and gives less than optimum yields for either etchant. Furthermore, with the double-mask technique it is difficult to properly align the gate contact with the channel.
In practice, GaAs etching is conventionally performed with a solution of an etchant, hydrogen peroxide (H.sub.2 O.sub.2) and water. The hydrogen peroxide oxidizes the exposed GaAs surface, with the etchant removing this oxide. Rather than etching for a specified period of time, an initial etch is performed for a time period somewhat less than the expected full etch period. The wafer is then removed from the etching solution and the drain-source current is measured for a given drain-source voltage. Further etching is then performed, after which the wafer is again removed to measure the drain-source current. These alternating etching and measuring cycles are repeated until a desired drain-source current level is reached. This process allows for wafer-to-wafer variations in the GaAs that would not be accounted for with a fixed etch period.
Unlike GaAs, silicon is usually etched with a dry (plasma) etch process. Etching is performed with a single plasma etchant, followed by a second etchant that terminates the etching process and performs a cleanup.