Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit.
In general, packaging technology for semiconductor integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability. As demand increases for high-performing, miniature electronic products, a variety of technologies for a stack package are being developed.
In the semiconductor industry, “stack” means vertically stacking two or more semiconductor chips or packages. When a stack package is applied to a semiconductor memory device, a product having a memory capacity two or more times larger than a memory capacity which can be fabricated by a semiconductor integration process may be realized. Furthermore, the stack package not only increases the memory capacity, but also offers advantages in terms of packaging density and the efficient use of the mounting area.
The stack package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged at once. Second, packaged individual semiconductor chips may be stacked. The individual semiconductor chips of the stacked semiconductor package may be coupled through metallic wires or through silicon vias (TSV). The stack package using TSVs may have such a structure that the physical and electrical coupling between semiconductor chips is vertically achieved by TSVs formed in the respective semiconductor chips.
FIG. 1 is a perspective view illustrating the configuration of a stack package semiconductor integrated circuit.
Referring to FIG. 1, the semiconductor integrated circuit 100 includes first to third semiconductor chips 110 to 130, which are vertically stacked, and a plurality of TSVs 140 to 160, which are formed through the first to third semiconductor chips 110 to 130 and configured to transmit signals and power among the first to third semiconductor chips 110 to 130.
The first to third semiconductor chips 110 to 130 may be categorized as a master chip and slave chips, depending on their functions. For example, the third semiconductor chip 130 may serve as the master chip, and the first and second semiconductor chips 110 and 120 may serve as the slave chips. In this case, the third semiconductor chip 130 may receive signals and power from outside, transfer the signals and power to the first and second semiconductor chips 110 and 120, and control the first and second semiconductor chips 110 and 120.
The plurality of TSVs 140 to 160 configured to transmit signals and powers may be formed of a metal, for example, Cu. Each of the semiconductor chips 110 to 130 may include several hundred to several thousand TSVs formed therethrough.