The present disclosure relates to nonvolatile semiconductor memory devices, and more particularly to layout configuration and circuit configuration for solving a mismatch in drive load capacitance between a memory cell array and a reference cell array.
In recent years, with increase in demand for electronic equipment such as cellular phones (smartphones), portable music players, digital cameras, and tablet terminals, in particular, demand for nonvolatile semiconductor memory devices has been growing. Technical development has therefore been made actively for achieving increase in capacity, size reduction, high-speed rewrite, high-speed read, and low-power operation.
Currently main nonvolatile memory is flash memory. The rewrite time of flash memory is however in the order of microseconds or milliseconds, and this has become a cause of blocking improvement of the performance of set equipment incorporating nonvolatile memory.
Recently, novel nonvolatile memory devices capable of high-speed, low-power rewrite, in comparison with flash memory, have been under active development. An example of such memory devices includes resistive random access memory (ReRAM) using resistance change elements as memory elements. ReRAM is capable of high-speed rewrite having a rewrite time as high as the nanosecond order. Moreover, while a voltage of 10V or more is required at the rewrite time for flash memory, ReRAM can perform rewrite only with about 1.8 V, permitting reduction in the power consumption of nonvolatile memory.
Read circuit configurations of ReRAM are disclosed in Japanese Unexamined Patent Publication No. 2004-234707 and “A 4 Mb Conductive-Bridge Resistive Memory with 2.3 GB/s Read-Throughput and 216 MB/s Program Throughput,” 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers, P210-211. Memory cells of ReRAM are each comprised of a resistance change element and a cell transistor connected in series. The resistance change element stores data by being set to a low resistance value or a high resistance value in a resistance value range of 1 KΩ to 1 MΩ, for example, according to the stored data (“0” data, “1” data). The memory cell current is large when the resistance value of the resistance change element is low, and is small when it is high. The difference in this memory cell current is detected by a sense amplifier circuit during read operation, thereby reading the data stored in the memory cell.
In order to determine the magnitude of the memory cell current by the sense amplifier circuit, a reference cell for generating a reference current is used. The sense amplifier circuit determines the data stored in the memory cell by comparing the memory cell current with the reference cell current. The reference cell is comprised of a fixed resistance element formed of a polysilicon resistance element, for example, and a cell transistor connected in series. The resistance value of the fixed resistance element of the reference cell is set to the intermediate value between the low resistance value and the high resistance value set for the resistance change element of the memory cell. By this setting, the reference cell current during read operation is a current value intermediate between the memory cell currents corresponding to “0” data and “1” data, and thus the sense amplifier circuit can determine the data stored in the memory cell.
The memory cell and the sense amplifier are connected through a bit line, and the reference cell and the sense amplifier are connected through a reference bit line. In order to read data by comparing the cell current with the reference cell current, it is necessary to match the load resistance of the bit line with that of the reference bit line. For this, first, the wiring widths and lengths of the bit line and the reference bit line must be the same. However, since a number of memory cells are connected to the bit line while only a reference cell is connected to the reference bit line, only achieving the same wiring width and length will still generate a large deviation in load resistance. To solve this problem, generally used is a method of connecting dummy memory cells to the reference bit line to match the load resistance of the reference bit line with that of the bit line. For efficient layout, such dummy memory cells for the reference bit line are generally arranged in the memory cell array. In this case, resistance change elements are also provided in the dummy memory cells to secure the pattern uniformity in the memory cell array.
Also, in ReRAM, etc. an operation called forming is first required to make the resistance change element switchable between the high resistance state and the low resistance state. In the forming, a voltage higher than that for normal rewrite is applied to the resistance change element. By this application, the resistance change element that is in an ultra-high resistance state before the forming is rendered switchable between the high resistance state and the low resistance state.