1. Field of the Invention
The present invention relates to a clock generating circuit, and more specifically, to a method and related device for reducing electromagnetic interference associated with a clock generating circuit.
2. Description of the Prior Art
In many clocked circuits, a differential signal is used for generating clock signals. One application using differential signaling is shown in FIG. 1. FIG. 1 is a functional block diagram of a T-Configuration of RSDS™ bus structure 10 according to the prior art. As introduced in the RSDS™ Specification Revision 0.95, RSDS™ is a signaling standard and also a differential interface with a nominal signal swing of 200 mV. It defines the output characteristics of a transmitter and inputs of a receiver along with the protocol for a chip-to-chip interface between Flat Panel timing Controllers and Column Drivers. The RSDS™ data bus circuit 10 contains a timing controller 12 for controlling the timing of a plurality of driver circuits 14. For example, eight driver circuits 14 are shown in FIG. 1. The timing controller 12 provides the first driver circuit 14 with a start pulse SP, and each driver circuit 14 sends the start pulse SP to the succeeding driver circuit 14. When the driver circuits 14 receive the start pulse SP, the driver circuits 14 drive digital differential data bus signals in analog form.
Please refer to FIG. 2. FIG. 2 is a timing diagram showing how the timing controller 12 generates the start pulse SP. First of all, the timing controller 12 generates a differential pair of clock signals CLKN and CLKP. Ideally, the clock signals CLKN and CLKP should have be exactly 180 degrees out of phase with each other, have the same slew rate, and otherwise be identical to each other. A differential signal DIFF is generated from subtracting the CLKN clock signal from the CLKP clock signal. The differential signal DIFF is used for clocking data, and the start pulse SP is also generated based on the differential signal DIFF.
Please refer to FIG. 3. FIG. 3 is a diagram 20 showing common mode voltages generated from balanced and unbalanced differential clock signals. The differential clock pair at the top of FIG. 3 is balanced, with the clock signals CLKN and CLKP being identical with each other and exactly 180 degrees out of phase. Taking the instantaneous average of the clock signals CLKN and CLKP produces a common mode voltage VCM. When the clock signals CLKN and CLKP are balanced, the common mode voltage VCM is flat, having a value of zero.
On the other hand, the bottom of FIG. 3 shows a case where the clock signals CLKN and CLKP are unbalanced. The unbalance is usually attributed to different slew rates for the clock signals CLKN and CLKP or skews in the times when the clock signals CLKN and CLKP start rising or falling. When this unbalance occurs, the common mode voltage VCM is no longer flat and equal to zero. Unfortunately, the common mode voltage VCM is a leading source of electromagnetic interference (EMI) in the RSDS™ data bus circuit 10, which can affect the integrity of data in the RSDS™ data bus circuit 10 and other neighboring circuits.