1. Field of the Invention
This invention relates to a mask-ROM manufacturing method, and more particularly to the improvement of a ROM-Implantation step for storing data.
2. Description of the Related Art
Conventionally, a mask-ROM is well known as one of nonvolatile semiconductor memory devices. The mask-ROM is a memory in which data can be stored by, for example, selectively ion-implanting impurity into the channel region of memory cell transistors using a mask alignment technique in the manufacturing process so as to selectively form depletion type cell transistors. For example, the mask-ROM constitutes a logic circuit such as an NAND circuit or NOR circuit according to data stored therein.
FIG. 1 is a cross sectional view of a cell of a NAND type mask-ROM. The memory structure of the mask-ROM shown in FIG. 1 is called a two-layered gate electrode structure using two-layered polysilicon gates.
As shown in FIG. 1, a field oxide film 102 is formed in the surface area of a p-type silicon substrate 100 for element isolation, for example. In the isolated element region, n-type source/drain diffusion layers 104A and 104B are formed. The diffusion layer 104A is electrically coupled to a low potential (GND/VSS), for example, and the diffusion layer 104B functions as a bit line and is electrically coupled to a high potential (VDD), for example. First-layered polysilicon gates 108A to 108N and second-layered polysilicon gates 110A to 110C are formed over that portion of the substrate area which lies between the diffusion layers 104A and 104B with a gate oxide film 106 disposed therebetween. The first-layered polysilicon gates 108A to 108N and second-layered polysilicon gates 110A to 110C serve as word lines WL1 to WLn. In the channel region below the first-layered polysilicon gates 108A to 108N, n-type diffusion layers 112 (which are hereinafter referred to as short regions) are selectively formed by ion-implantation to selectively convert the cell transistors into the depletion type. Likewise, in the channel region below the second-layered polysilicon gates 110A to 110C, n-type diffusion layers 114 (which are referred to as short regions) are selectively formed by ion-implantation to selectively convert the cell transistors into the depletion type.
The ion-implantation step for selectively converting the cell transistors into the depletion type is generally called a ROM-Implantation step, and in this specification, it is referred to as a ROM-Implantation step or simply a ROM-Implantation.
Now, the integration density of the semiconductor device and semiconductor memory device is further enhanced and the size of the transistors and the like tends to become smaller. As a matter of course, the integration density in the mask-ROM is significantly enhanced and it is strongly required to reduce the size of the cell transistors.
With the cell structure of two-layered gate electrode type shown in FIG. 1, a distance between the gates (word lines) ca be reduced and it is preferable to enhance the integration density of the cell transistors since the second-layered gates 110A to 110C are formed between the first-layered gates 108A to 108N.
However, particularly when a short region 112 for converting the cell transistor having the first-layered gates 108A to 108N into the depletion type is formed, a problem of preventing the high integration density which is explained below occurs.
That is, since the short region 112 is formed below the first-layered gates 108A to 108N, the ROM-Implantation for forming the short region 112 must be effected before the first-layered gates 108A to 108N are formed.
Therefore, it becomes necessary to form the short region 112 larger than necessary so as to have a sufficiently large mask alignment margin so that the first-layered gates can be formed over the short region without fail.
FIG. 2 is a view for explaining an obstacle to enhancement of the integration density and shows an enlarged portion including the first- and second-layered gates.
As shown in FIG. 2, the length of the short region 112 in the gate length direction is equal to the sum of the gate length L1 of the first-layered gate 108 and the mask alignment margins M1 provided on both sides thereof. The mask alignment marging must be approximately 20-30% of the minimum lithography dimensions according to the present lithography technology (in the case of FIG. 2, the gate length L1 of the first-layered gate 108). If the object to be aligned is a diffusion layer such as the short region 112, the mask alignment margin M1 shown in the drawing is set to be 40 to 50% (which range is larger than 20-30%), since due to process fluctuation, the region may expand by the diffusion of impurities and the dimensions of the resist pattern used as a mask may be different from the intended dimensions.
As shown in FIG. 2, in the mask-ROM, the short regions 112 may be formed adjacent to each other depending on data to be stored. Therefore, it becomes necessary to separate the short regions from each other by a certain distance in order to prevent the depletion layers occurring around the short regions 112 from being made in contact with each other. The distance to be separated is set to l1 as shown in FIG. 2.
As is understood from the above description, a distance l2 between the first-layered gates 108 can be so set that l2=l1+2M1. Further, assuming that an insulation film 116 between the first-layered gate 108 and second-layered gate 110 is made sufficiently thin, then, l2 becomes substantially equal to the length L2 of the second-layered gate 110. That is, in the cell structure of second-layered gate electrode type, L1&lt;&lt;L2.
The explanation is made more concretely by using actual values.
L1 is set to 0.7 .mu.m and 11 is set to 0.5 .mu.m. The substantial mask alignment margin M1 is set to approx. 40% of L1, that is, approx. 0.3 .mu.m.
Therefore, the distance 12 between the first-layered gates is approx. 1.1 .mu.m. Further, if l2 is substantially equal to L2, L2 becomes longer than L1 by more than 50%.
Thus, in the mask-ROM having the cell structure of two-layered gate electrode type, the distance l2 between the first-layered gates becomes larger because of its manufacturing method, thereby making it difficult to enhance the integration density.