1. Field of the Invention
The present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to a monolithically integrated bipolar transistor on an SOI (Silicon-On-Insulator) substrate.
2. Description of Related Art
Bipolar transistors in SOI technologies using thin silicon layers are often designed by means of a vertical emitter-base structure and a lateral collector structure, see e.g. U.S. Pat. No. 5,087,580 to Eklund, and J. Cai et al., Vertical SiGe-Base Bipolar Transistors on CMOS-Compatible SOI Substrate, p. 215 in Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting.
Depending on the geometry, this design may be limited by base push out effects, also called the Kirk effect, as shown by Q. Ouyang et al., A Simulation Study on Thin SOI Bipolar Transistors with Fully or Partially Depleted Collector, p. 28 in Proceedings of the 2002 Bipolar/BiCMOS Circuits and Technology Meeting. The base push out is strongly affected by the oxide layer of the SOI substrate beneath the transistor. In a standard transistor the base push out would just continue down towards the collector. However the oxide interface prevents all transport and the entire collector layer becomes flooded with carriers, giving a slower transport. This is seen as a hook in a Gummel plot and as a dip in the transition frequency, fT.
As pointed out by Q. Ouyang et al., a common manner to reduce the base push out is to shrink the emitter width or to increase the doping concentration in the collector region. However, the shrinking of the emitter may be prevented by the minimum feature sizes allowable by the lithography of the particular fabrication process used.