A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having shallow trench isolation (STI) and its manufacture method.
B) Description of the Related Art
Local oxidation of silicon (LOCOS) is known as one of element isolation methods for semiconductor devices.
According to the technique of local oxidation of silicon, after a silicon oxide film is formed on a silicon substrate as a buffer layer, a silicon nitride film is formed as an oxidation preventing mask layer, and after the silicon nitride film is patterned, the surface of the silicon substrate is thermally oxidized via the silicon oxide film.
While the silicon substrate is thermally oxidized, oxidation seeds such as oxygen and moisture intrude also into the buffer silicon oxide film under the silicon nitride film so that the silicon substrate surface under the silicon nitride film is also oxidized and silicon oxide regions called bird's beaks are formed. The regions where the bird's beaks are formed cannot be used substantially as an element forming region (active region) so that an area of the element forming region becomes small.
If a substrate surface is thermally oxidized after a silicon nitride film having openings of various sizes is formed, the thickness of a silicon oxide film formed on the silicon substrate under an opening having a narrow size is thinner than that of a silicon oxide film formed on the silicon substrate under an opening having a broad size. This phenomenon is called thinning.
As semiconductor devices are made finer, the area of the region not used as the element forming region increases in the whole region of a semiconductor substrate, because of bird's beaks and thinning. Namely, a ratio of narrowing the element forming region increases, hindering high integration of semiconductor devices.
A trench isolation (TI) technique is known as the technique of forming an element isolation region. With this technique, a trench is formed under a semiconductor substrate surface, and insulator or polysilicon is buried in the trench. This method has been used conventionally with bipolar transistor LSI's which require deep element isolation regions.
In order to eliminate both the bird's beak and thinning, trench isolation has been applied widely to MOS transistor LSI's. Since a MOS transistor LSI does not require element isolation as deep as that of a bipolar transistor, element isolation can be realized by a relatively shallow trench of about 0.1 to 1.0 μm deep. This structure is called shallow trench isolation (STI).
STI forming processes will be described with reference to FIGS. 5A to 5H.
As shown in FIG. 5A, on the surface of a silicon substrate 1, a silicon oxide film 2 having a thickness of, for example, 10 nm is formed by thermal oxidation. On this silicon oxide film 2, a silicon nitride film 3, e.g., 100 to 150 nm thick is formed by chemical vapor deposition (CVD). The silicon oxide film 2 functions as a buffer layer for relaxing a stress between the silicon substrate 1 and silicon nitride film 3. The silicon nitride film 3 functions as a stopper layer in a later polishing process.
A resist pattern 4 is formed on the silicon nitride film 3. An opening defined by the resist pattern 4 defines the region where an element forming region is formed. The region of the silicon substrate under the resist pattern 4 becomes an active region where an element is formed.
By using the resist pattern 4 as an etching mask, the silicon nitride film 3 exposed in the opening, the silicon oxide film 2 under the silicon nitride film and the silicon substrate 1 under the silicon oxide film are etched by reactive ion etching (RIE) to a depth of about 0.5 μm to form a trench 6.
As shown in FIG. 5B, the silicon substrate surface exposed in the trench 6 is thermally oxidized to form a thermally oxidized silicon film, e.g., 10 nm thick.
As shown in FIG. 5C, a silicon oxide film 9 burying the trench is formed on the silicon substrate, for example, by high density plasma (HDP) CVD. In order to make dense the silicon oxide film 9 to be used as the element isolation region, the silicon substrate is annealed, for example, in a nitrogen atmosphere at 900 to 1100° C.
As shown in FIG. 5D, by using the silicon nitride film 3 as a stopper, an unnecessary silicon oxide film 9 is removed starting from the top surface thereof by chemical mechanical polishing (CMP) or reactive ion etching (RIE). The silicon oxide film 9 is left only in the trench defined by the silicon nitride film 3. Annealing may be performed at this stage in order to make dense the silicon oxide film.
As shown in FIG. 5E, the silicon nitride film 3 is removed by hot phosphoric acid. Next, the buffer silicon oxide film 2 on the surface of the silicon substrate 1 is removed by dilute hydrofluoric acid. At this time, the silicon oxide film 9 buried in the trench is also etched.
As shown in FIG. 5F, the surface of the silicon substrate 1 is thermally oxidized to form a sacrificial silicon oxide film 22 on the substrate surface. Impurity ions of a desired conductivity type are implanted into the surface layer of the silicon substrate 1 via the sacrificial silicon oxide film 22 and activated to form a well 10 of the desired conductivity type. The sacrificial silicon oxide film 22 is thereafter removed by dilute hydrofluoric acid. While the sacrificial silicon oxide film 22 is removed, the silicon oxide film 9 is also etched.
As shown in FIG. 5G, the exposed surface of the silicon substrate is thermally oxidized to form a silicon oxide film 11 having a desired thickness which is used as a gate insulating film. A polysilicon film 12 is deposited on the silicon substrate 1 and patterned to form a gate electrode.
As shown in FIG. 5H, impurity ions having the conductivity type opposite to that of the well 10 are implanted and activated to form source/drain regions S/D1. If necessary, side wall spacers SW are formed on the side walls of the gate electrode, and impurity ions having the conductivity type opposite to that of the well 10 are implanted again and activated to form high concentration source/drain regions S/D2.
As silicon oxide is buried in the trench and an annealing process is performed in order to make dense the silicon oxide film 9, the silicon oxide film 9 becomes dense and is also compressed so that the element forming region surrounded by this silicon oxide film 9 receives a compression stress.
As the compression stress is applied, the mobility of electrons in the active region of the silicon substrate 1 lowers greatly. A saturation drain current therefore lowers. As the active region becomes narrow because of finer elements, the influence of the compression stress becomes large.
As shown in FIG. 5G, if the shoulders of the element isolation region 9 are etched and divots are formed under the gate electrode, the gate electrode surrounds not only the upper surface of the element forming region, but also the side walls of the shoulders of the element forming region of the silicon substrate. When a voltage is applied to the gate electrode having this shape, an electric field concentrates upon the shoulders of the element forming region so that a transistor having a lower threshold voltage is formed. This parasitic transistor forms the hump characteristics on the IV characteristics.
As shown in FIG. 5H, an interlayer insulating film IL1 including an etch stopper layer is formed covering the gate electrode, and contact holes are formed reaching the source/drain regions S/D2. Conductive plugs PL are buried in the contact holes. In this case, if divots are being formed in STI under the contact holes, the contact holes are formed deeper than the active region surfaces. Therefore, the distance between the conductive plugs PL and the well 10 under the source/drain regions S/D2 becomes short, resulting in a possibility of leak current by tunneling or the like.
Japanese Patent Laid-open Publication No. HEI-11-297812 proposes the following method. In order to suppress the formation of divots while the stopper nitride film is etched and removed and in order to prevent the hump characteristics and leak current, a silicon nitride film is formed on a silicon oxide film formed on the inner surface of a trench, a mask material is once filled in the trench, and the mask material is etched so that the surface level of the mask material in the trench becomes lower than the surface level of the semiconductor substrate, and the exposed silicon nitride film on the upper inner surface of the trench is removed.
As the opening of a shallow trench becomes narrow, it becomes difficult to completely bury the inside of the trench with an insulating film. A seam may be formed at the interface of the insulating film or a void may be formed in the insulating film. If a seam or void exists, the void may be exposed during etching so that a morphology abnormality may occur or the manufacture yield at later processes may be lowered.
Japanese Patent Laid-open Publication No. HEI-11-297811 proposes the following method. A nitride film is deposited on the surface of a semiconductor substrate, and a trench is formed through etching using a resist mask. The exposed surface is oxidized and a nitride film is deposited thereon, and thereafter a first TEOS film is deposited in the trench. After the first TEOS film is etched back through wet etching, a second TEOS film is deposited in the trench.
Although element isolation by STI is suitable for miniaturization, there are problems inherent to STI. Various problems arise if a region is formed which has the STI surface lower than the active region surface. New technologies have been desired which can suppress the problems inherent to STI.