Manufacturing techniques in use in the semiconductor industry have continued to improve in efficiency with resulting drops in cost. This is particularly true for chip manufacturing where the cost per gate continues to drop year by year. Some of this advantage is, however, offset by the somewhat slower pace at which the cost of chip packaging has been dropping. Until recently, chip manufacture and chip packaging have been treated as essentially separate technologies and advances in the former have not necessarily added value to the latter.
Recently, wafer scale packaging has been gaining in popularity. By this we mean that the entire wafer is packaged prior to its being separated into individual chips. A good example of this has been a recent publication by M. Hou "Wafer level packaging for CSPs" in Semiconductor International, July 1998 pp. 305-308. CSPs (chip scale packages) first made their appearance around 1996. Since then there have been a number of improvements exemplified by the structure described by Hou. In the process that she discusses, assembly of individual chip packages becomes an extension of the wafer fabrication line rather than a separate operation dedicated to chip packaging.
Briefly, the process that is described by Hou involves compression molding of an encapsulant onto the top surface of the full wafer. A special molding press, custom built to fit each type of wafer that is to be used, is needed and reliance is made on the ability of the solder bumps, already present on the top surface of the completed wafer, to push through the plastic and reappear at the top surface of the package. Hou notes that this approach is suited primarily to low density packages.