It is known practice, in the field of power semiconductor components, to connect a plurality of semiconductor functional elements, for example transistors or diodes, to one another in parallel or in series and to concentrate the semiconductor functional elements (which have been connected) in one semiconductor component. This makes it possible, inter alia, to divide the load—which has been applied to the semiconductor component—among a plurality of semiconductor functional elements, with the result that, even in the case of high electric currents and voltages which have to be “processed” in the field of power semiconductors, no damage occurs in the semiconductor component.
One example of a semiconductor component containing a plurality of parallel-connected transistors will be explained in more detail below with reference to FIG. 4.
One part of a semiconductor component 1 has a first semiconductor layer 2 and a second semiconductor layer 3. The second semiconductor layer 3 has been divided into a plurality of semiconductor regions by means of insulator structures, in this case a first insulation layer 4 and a second insulation layer 5 which respectively intersect the second semiconductor layer 3 at a right angle. In this case, the part of the semiconductor component 1 in FIG. 3 exhibits a first, a second and a third functional element semiconductor region 6, 7 and 8, it being possible to see the full width of only the second functional element semiconductor region 7 and only the right-hand and the left-hand end, respectively, of the first and the third functional element semiconductor region 6, 7, respectively. In this example, the first and second insulator structures 4, 5 are provided by a p-doped material, whereas the first to third functional element semiconductor regions 6 to 7 each comprise an n-doped semiconductor material. In this example, the first semiconductor layer 2 comprises a wealdy p-doped material. The second functional element semiconductor region 7 is part of a MOS field effect transistor which furthermore has an n-doped source region 9, a p-doped body region 10—which have been impressed into the second functional element semiconductor region 7—and a drain region 11 which, inter alia, runs at a boundary between the first and second semiconductor layers 2, 3. In this case, the drain region 11 comprises a heavily n-doped material. A gate 12 can be used to induce a n-channel in the body region 10, so that an electric current can flow from the source region 9, through the second functional element semiconductor region 7 (base), into the drain region 11. D, S and G are respectively used to denote a drain, a source and a gate connection.
The problem of electrons emerging from the drain region 11, diffusing through the first semiconductor layer 2, circumventing the second insulator structure 5 and passing into the adjacent third functional element semiconductor region 8 arises when a negative drain voltage is applied to the drain region 11. Similarly, electrons which emerge from the drain region 11 may diffuse through the first semiconductor layer 2, circumvent the first insulator structure 4 and enter the first functional element semiconductor region 6. If electrons pass in such a manner into adjacent semiconductor regions or semiconductor regions which are further away (the electrons may diffuse over several mm), they may impair the way in which the semiconductor functional elements—which have been implemented in said regions—work (in this example, both the first functional element semiconductor region 6 and the third functional element semiconductor region 8 are parts of respective MOS field effect transistors which have been omitted in FIG. 3 for the sake of simplicity). Similar problems may also arise when other semiconductor functional elements, for example diodes, are used instead of the MOS field effect transistors.
In this case, the circuit diagram of a parasitic bipolar transistor T schematically symbolizes the diffusion of the electrons from the second functional element semiconductor region 7 into the third functional element semiconductor region 8.
In order to reduce the above-described parasitic parallel-path currents, particularly between adjacent semiconductor regions, it is known practice to lower a potential difference between the base and emitter of one of the parasitic pnp/npn structures by appropriately connecting a plurality of parasitic npn or pnp structures. A first exemplary embodiment of such a connection is shown in FIG. 6 and will be explained below.
Since the part of a semiconductor component which is shown in FIG. 6 closely resembles the design shown in FIG. 4, only the fundamental differences will be discussed here.
The part of a semiconductor component 1′ which is shown in FIG. 6 has a first functional element semiconductor region 6 and a second functional element semiconductor region 7, a bipolar transistor (n-p-n) being formed in the first functional element semiconductor region 6, and a MOS transistor being formed in the second functional element semiconductor region 7. Each of the functional element semiconductor regions 6, 7 is surrounded by a first and a second insulation structure 4, 5. A third insulation structure 13 having the same doping as that of the first and second insulation structures 4, 5 is provided between the second insulation structure 5 in the first functional element semiconductor region 6 and the first insulation structure 4 in the second functional element semiconductor region 7. A semiconductor structure 14 having the same doping as a collector region 19 within the first functional element semiconductor region 6 and a drain region 11 within the second functional element semiconductor region 7 is furthermore provided between the third insulation structure 13 and the first insulation structure 4 in the second functional element semiconductor region 7. The third insulation structure 13 and the semiconductor structure 14 run from a top side of the second semiconductor layer 3 to the underside of the latter, or project somewhat into the first semiconductor layer 2, and their top ends are electrically connected via a line 15. Together with the drain region 11 in the second functional element semiconductor region 7 and the intermediate part of the first semiconductor layer 2 and the first insulation structure 4 in the second functional element semiconductor region 7, that part of the semiconductor structure 14 which adjoins the first semiconductor layer 2 or that part of the semiconductor structure 14 which projects into the first semiconductor layer 2 forms a first parasitic npn structure Qn1. Similarly, the collector region 19 within the first functional element semiconductor region 6 and the drain region 11 within the second functional element semiconductor region 7 and also the intermediate part of the first semiconductor layer 2 form, together with the third insulation structure 13, a second parasitic npn structure Qn2. The parasitic structures Qn1 and Qn2 are symbolized in FIG. 6 by corresponding equivalent circuit diagrams.
The base of the second parasitic npn structure is connected to the collector of the first parasitic npn structure via the line 15. This makes it possible to reduce a base/emitter voltage of the second parasitic npn structure Qn2. The disadvantage of the semiconductor component 1′ shown in FIG. 6 is that the base/emitter voltage of the second parasitic npn structure Qn2 can be reduced, at most, to a saturation voltage of the first parasitic npn structure Qn1. It is not possible to reduce said base/emitter voltage any further, with the result that it is not possible to completely turn off the second parasitic npn structure Qn2.
An alternative embodiment for reducing the base/emitter voltage of the second parasitic npn structure Qn2 is shown in FIG. 8, which is explained below. A semiconductor structure 16 which is connected to the first insulation structure 4 in the second functional element semiconductor region 7 by means of a line 17 is provided, in one part of a semiconductor component 1″, besides the second insulation structure 5 in the second functional element semiconductor region 7 and outside the latter. In this exemplary embodiment, the first parasitic npn structure Qn1 is formed by the semiconductor structure 16, the drain region 11 within the second functional element semiconductor region 7 and also the intermediate part of the first semiconductor layer 2 and the second insulation structure 5 in the first functional element semiconductor region 7. The second parasitic npn structure Qn2 is formed by the collector region 19 within the first functional element semiconductor region 6 and the drain region 11 within the second functional element semiconductor region 7 and also the intermediate part of the first semiconductor layer 2 and the first insulation structure 4 in the second functional element semiconductor region 7. In this case, the second insulation structure 5 in the second functional element semiconductor region 7 is grounded.
The base of the second parasitic npn structure Qn2 is connected to the collector of the first parasitic npn structure Qn1 via the line 17, with the result that it is possible to lower a base/emitter voltage of the second parasitic npn structure Qn2 to the saturation voltage of the first parasitic npn structure Qn1. As in the embodiment described in FIG. 6, it is not possible to lower the base/emitter voltage any further here either.
FIGS. 5 and 7 show corresponding plan views of parts of the semiconductor components 1′, 1″ shown in FIGS. 6 and 8. It can be seen in FIG. 5 that the top ends of the third insulation structure 13 and of the semiconductor structure 14 are electrically connected to one another by means of the line 15. In this case, the part labeled with reference 18 schematically symbolizes all of the structures which are located to the right of the semiconductor structure 14 and are important for the operation of the MOS transistor formed in the second functional element semiconductor region 7. Similarly, it can be seen in FIG. 7 that the top ends of the first insulation structure 4 in the second functional element semiconductor region 7 and of the semiconductor structure 16 are connected to one another via the line 17.
FIG. 9 shows an equivalent circuit diagram which forms the basis of the semiconductor components 1′, 1″ described in FIGS. 6 and 8. In the embodiment shown in FIG. 8, Rsub1 denotes the resistance through the second insulation structure 5, Rsub2 denotes the resistance through the first semiconductor layer 2 (from an underside of the first semiconductor layer 2 to an underside of the semiconductor structure 4), Rsub3 denotes the resistance through the semiconductor structure 16, and Rmetal denotes the resistance of the line 17, for example. Similarly, in the embodiment shown in FIG. 6, Rsub1 denotes the resistance through the first semiconductor layer 2 (from an underside of the first semiconductor layer 2 to an underside of the first insulation structure 4), Rsub2 denotes the resistance through the first semiconductor layer 2 (from an underside of the first semiconductor layer 2 to an underside of the semiconductor structure 13), Rsub3 denotes the resistance through the semiconductor structure 14, and Rmetal denotes the resistance of the line 15. Rc1 is used to denote the resistive coupling between the first insulation structure 4 and the semiconductor structure 13 (FIG. 6) and the resistive coupling between the first insulation structure 4 and the second insulation structure 5 (FIG. 8). Reference 20 is used to denote a DMOS structure formed in the second functional element semiconductor region 7, and reference 21 is used to denote a reverse diode inherent in the DMOS structure.