1. Technical Field
The present invention relates to a thin film transistor used for an active matrix liquid crystal display, a liquid crystal display device using the thin film transistor, and a method of fabricating the thin film transistor.
2. Prior Art
A liquid display device employing an active matrix system, which uses a thin film transistor, comprises a TFT array substrate in which gate electrodes (Y-electrode) and data electrodes (X-electrode) are arranged in the form of a matrix and thin film transistors (TFT) are disposed at intersceting points of the matrix, and an opposite substrate located so as face the TFT array substrate with a space therebetween. By the thin film transistor, the liquid display device controls a voltage applied to a liquid crystal which is sealed between the TFT array substrate and the opposite substrate, and can performs a displaying utilizing an electro-optic effect of the liquid crystal.
Here, as a structure of the thin film transistor (TFT), a top gate type (positive stagger type) thin film transistor (TET) and a bottom gate type (reverse stagger type) thin film transistor have heretofore been known. In the top gate type thin film transistor, a light shield film is formed on an insulating substrate formed of glass and the like, and an insulating film formed of silicon oxide SiOx, silicon nitride SiNx and the like is formed on the light shield film. On the insulating film, source electrode and source electrodes formed of an ITO (indium tin oxide) film are formed so as to be apart from each other by a predetermined distance. An amorphous silicon film (a-Si film) is formed so as to cover the source and drain electrodes. A gate insulating film formed of SiOx, SiNx and the like is formed on the amorphous silicon film. A gate electrode is formed on the gate insulating film. On the other hand, in the bottom gate type thin film transistor, a gate electrode is formed by patterning a metal film deposited on an insulating substrate formed of glass and the like. A gate insulating film formed of SiNx and the like is formed on the gate electrode. An amorphous silicon film (a-Si film) is grown on the gate insulating film by a CVD method. Thereafter, an a-Si film doped with phosohorus (n+) is grown in a way that phosphine (PH3) is continuously supplied during the growth of the film, and then patterned. Moreover, a film for source and drain electrodes is formed on the a-Si film, and patterned. Thus, the source and drain electrodes are formed.
Here, since a growth rate of the amorphous silicon (a-Si) film is as slow as 500 xc3x85/min in forming the thin film transistor (TFT), acquisition of a sufficient TFT characteristic with an a-Si film of a thickness which is as thin as possible is effective to increase a productivity and to minimize a capital investment.
As prior arts paying attention to the length of a manufacturing time in forming such a-Si film, there exist Japanese Patent Laid-Open No. Hei 6(1994)-77483, No. Hei 7(1995)-45833, No. Hei 7(1995)-135319 and. No. Hei 8(1996)-255917. In these gazettes, an a-Si film formed of a low deposition rate film, which takes a long film growth time for growing it, is grown in combination with an a-Si film formed of a high deposition rate film, which takes a short film growth time. More specifically, in the thin film transistors (TFT) taking a bottom gate type structure and a top gate type structure, a good a-Si film (fine a-Si film/low defect-density a-Si film) formed of a low deposition rate film is grown on so-called a channel interface side (gate insulating film side), and a bad a-Si film (coarse a-Si film/high defect-density a-Si film) is grown close to the source and drain electrode side that is a contact portion. According to these films, a tact time can be reduced to half, compared to a length of a general manufacturing time at the time when the a-Si film is formed at a single low deposition rate by a chemical vapor deposition method. In addition, it is possible to prevent deterioration of the a-Si film on the channel interface side which has an effect on electric characteristics and physical and mechanical characteristic, thus preventing deterioration of characteristics of the thin film transistor (TFT).
However, according to these background arts, although the film growth time can surely be shortened, the prior arts are nothing else more than preventing the deterioration of the TFT characteristic such as an electrical characteristic, and the prior arts do not aim at increasing the TFT characteristic. In other words, the object of these prior arts is to shorten a working time for growing the film under a situation where the deterioration of the TFT characteristic is prevented, and disclose nothing than increasing no deposition rate of the a-Si film on the channel interface side in both of the bottom gate and top gate type TFTs.
As described above, it is required to obtain a sufficient TFT characteristic with an a-Si film of a thickness which is as thin as possible in fabricating the thin film transistor (TFT). On the other hand, in the top gate type TFT, when source and drain electrodes are formed by plasma doping technique, the a-Si film is grown on the SiOx film formed on the substrate. Accordingly, the a-Si film has a tendency to have a large defect-density due to a lattice mismatching of the a-Si film with the SiOx film. In order to acquire a sufficient ON characteristic of the thin film transistor (TFT), an a-Si film having a sufficiently thick thickness must be formed so that its film quality is further improved as a distance from the SiOx film becomes larger. In other words, as the thickness of the deposited a-Si film increases, a lower part of amorphous silicon is annealed in eventually H2 atmosphere and the film quality is improved as the dangling bond of amorphous silicon is terminated by H2. (as the thickness of the deposited a-Si film increases, an influence of lattice mismatching of the amorphous silicon with the silicon oxide on an upper part of the amorphous silicon is reduced, and so-called a hydrogen annealing effect further improving the film quality of the amorphous silicon as the deposition of the amorphous silicon is progressed is exhibited, thus tending to increase an ON current.)
FIG. 6 is a graph showing a dependency of the film thickness on the ON current in the conventional TFT structure. In FIG. 6, the axis of abscissa shows the film thickness of the a-Si film, and the axis of ordinates shows the ON current. In the case where the a-Si film formed at a high deposition rate is particularly used, the ON current increases approximately in proportion to the film thickness in a practical use as shown in FIG. 6, so that a thick thickness is required for the a-Si film to obtain a sufficient ON current to drive a liquid crystal device (LCD) including the thin film transistor.
This tendency is shown in the case where a low defect-density amorphous silicon formed at a low deposition rate is used.
However, as a result of investigations by the inventors, the inventors came to recognize the existence of the fact that the ON current decreases as the film thickness of the a-Si film becomes larger. Specifically, although the ON current tends generally to increase as the film thickness of the a-Si film becomes larger, on the contrary the ON current decreases as the film thickness of the a-Si film becomes larger depending on a position of the a-Si film formed and its state. The reason is that as the film thickness of the a-Si film becomes larger, a distance between the channel interface (the upper part of the a-Si film in the case of the top gate type thin film transistor TFT) and the source/drain electrode becomes larger, thus increasing a parasitic capacitance. Furthermore, as another reason, the following reason is given. When the Debye length defined by the depth in which electric field has effect on the amorphous silicon is nearly equal to the thickness of the amorphous silicon, the current conduction is dominated by the contact conductance not by the channel conductance, so that the thickness of the a-Si film is almost proportional to the current (current crowding effect). For this reason, employment of a thin a-Si film is sometimes more advantageous to produce a large ON current.
As described above, since the advantage in the case where the thick a-Si film is employed and the advantage in the case where thin a-Si film is employed are in a trade-off relation, in order to produce the maximum ON current, it is necessary to select the optimum position for forming the a-Si film, as well as the optimum thickness of the a-Si film.
In order to solve the above-described problems, the object of the present invention is to increase productivity of a thin film transistor and to produce a high TFT characteristic, by forming a low defect-density a-Si film formed at a low deposition rate at a contact portion.
To achieve the foregoing objects, a thin film transistor of the present invention, as shown in FIG. 1(a), comprises: an amorphous silicon film 2 formed on an insulating substrate 1; a gate insulating film 3 formed on said amorphous silicon film 2; and a gate electrode 4 formed on said gate insulating film 3, wherein said amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate, and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that for forming said low defect-density amorphous silicon layer 5, and wherein the low defect-density amorphous silicon layer 5 in said amorphous silicon film 2 is grown close to said insulating substrate 1 and said high deposition rate amorphous silicon layer 6 is grown close to said gate insulating film 3.
In the above-described structure of the thin film transistor of the present invention, the amorphous silicon film 2 is constituted by the low defect-density amorphous silicon layer 5 and the high deposition rate amorphous silicon layer 6, and a thickness of the low defect-density amorphous silicon layer 5 is set to 50 xc3x85 or less. Thus, a contact current flowing through the low defect-density amorphous silicon layer 5 is further increased and the low defect-density amorphous silicon layer 5 serves as a buffer layer for the insulating substrate 1.
On the other hand, if the amorphous silicon film 2 is formed in such manner that the low defect-density amorphous silicon layer 5 is formed at a low deposition rate and then the high-deposition rate amorphous silicon layer 6 is formed while increasing the deposition rate gradually, the productivity in forming the amorphous silicon film 2 can be increased and a stable current can be made to flow through the amorphous silicon film 2.
Furthermore, the thin film transistor of the present invention comprises: an insulating film 7 formed on a substrate 1; a source electrode 8 and a drain electrode 9, which are formed on said insulating film 7; and an amorphous silicon film 2 grown on said insulating film 7, said source electrode 8 and said drain electrode 9,
wherein said amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 in a lower portion thereof, said low defect-density amorphous silicon layer 5 serving as a buffer layer for relaxing a lattice mismatching with said insulating film 7.
Here, if the insulating film 7 is formed of silicon oxide (SiOx), it is possible to relax a tendency to increase the defect density of the amorphous silicon film 2 in growing the amorphous silicon film 2 on the silicon oxide (SiOx) film, by providing the low defect-density amorphous silicon layer 5.
Accordingly, since the film quality of the lower part of the phosphorus silicon film 2 is apt to become worse due to an influence of the film under the phosphorous silicon film 2, the lower part of the phosphorous silicon film 2 is formed at a low deposition rate.
As shown in FIGS. 1(a) and 1(b), a liquid crystal display device of the present invention is a liquid crystal display panel in which an electrode functioning as a pixel and a thin film transistor for applying a voltage to said electrode are formed. In FIG. 1(a), the top gate type thin film transistor in the liquid crystal display panel includes a substrate 1, an insulating film 7 formed on the substrate 1, source and drain electrodes 8 and 9 formed on the insulating film 7, an island-shaped amorphous silicon film 2 formed on the source and drain electrodes 8 and 9, a gate insulating film 3 formed on the amorphous silicon film 1, and a gate electrode 4. The amorphous silicon (a-Si) film 2 is composed of a plurality of layers, which are grown at different deposition rates. The layer in the a-Si film 2, which is closer to the source and drain electrodes 8 and 9, is formed of a low defect-density amorphous silicon layer 5 grown at a low deposition rate. In FIG. 1(b), the bottom gate type thin film transistor in the liquid crystal display panel includes a substrate 11, a gate electrode 12 formed on the substrate 11, a gate insulating film 13 formed on the gate electrode 12, an island-shaped amorphous silicon (a-Si) film 14 formed on the gate insulating film 13, and source and drain electrodes 15 and 16. The amorphous silicon (a-Si) film 14 is composed of a plurality of layers, which are grown at different deposition rates. The layer in the a-Si film 14, which is closer to the source and drain electrodes 15 and 16, is formed of a low defect-density amorphous silicon layer 17 grown at a low deposition rate.
When the liquid crystal display device of the present invention is described in more detail using FIG. 1(a), in the thin film transistor, the insulating film 7 is formed on the substrate 1, the source and drain electrodes 8 and 9 are grown so as to contact the insulating film 7, and the low defect-density amorphous silicon film 5 of the amorphous silicon film 2 is formed at positions which contact the insulating film 7 and the source and drain electrodes 8 and 9, whereby a film quality is improved so that the current conductance is dominated by the channel conductance not by the contact conductance.
When the liquid crystal display device of the present invention is described in more detail using FIG. 1(b), in the thin film transistor, the source and drain electrodes 15 and 16 are formed on the amorphous silicon film 14, and the low defect-density amorphous silicon film 17 in the amorphous silicon film 14 is formed at a position where the low defect-density amorphous silicon film 17 contacts the source and drain electrodes 15 and 16, so that the Debye length is made to be long and the contact current is increased.
A method of fabricating a thin film transistor of the present invention will be described with reference to FIG. 1(a). In the method of fabricating the thin film transistor in which the source and drain electrodes 8 and 9, the island-shaped amorphous silicon film 2 and the gate electrode 4 are sequentially laminated on the substrate 1, the growth of the amorphous silicon film 2 is performed in such manner that the lower layer thereof closer to the source and drain electrodes 8 and 9 and the upper layer thereof closer to the gate insulating film 3 are formed at different deposition rates. Specifically, the lower layer of the amorphous silicon film 2 closer to the source and drain electrodes 8 and 9 is grown at a low deposition rate, and the upper layer thereof is grown at a high deposition rate.
Here, in forming the amorphous silicon film 2, the lower layer of the amorphous silicon film 2, which is a low deposition rate film, is grown to be thin on the source and drain electrodes 8 and 9, and the upper layer of the amorphous silicon film 2, which is a high deposition rate film, is grown to be thick on the low deposition rate film. With such film structure of the amorphous silicon film 2, the productivity of the liquid crystal display device can be increased without degrading the TFT characteristic, and the capital investment can be minimized. Here, if the low deposition rate film is grown at a low growth rate of about 50 xc3x85/min and to a thickness of 50 xc3x85 or less, the low deposition rate film preferably can serve as a buffer layer to relax an influence of a lattice mismatching of the a-Si film with the insulating film 7.
In forming the amorphous silicon film 2, the deposition rate film is grown on the source and drain electrodes 8 and 9, and the deposition rate film is grown on the low deposition rate film while gradually increasing the deposition rate. With such film structure of the amorphous silicon film 2, an influence of the lattice mismatching of the a-Si film with the insulating film 7 is absorbed by the low deposition rate film. By growing the high deposition rate film at the high deposition rate, the film growth time can be made to be faster. Accordingly, it is possible to improve electrical characteristics and physical properties of the thin film transistor, and moreover it is possible to shorten the film growth time. This multistage film growth can be performed in multistage processes, in addition to two stage processes. For example, it is possible to increase the film growth rate gradually every time the film is grown by 50 xc3x85, thus forming the amorphous silicon film 2 of a thickness of about 500 xc3x85 in total. By adopting such film structure of the amorphous silicon film 2, as a film quality changes, it is possible to change film growth conditions, and the film growth rate can be increased, in addition to promotion of so called a channel characteristic-depending rule.