1. Field of the Invention
The present invention is related to JTAG interfaces and more specifically to communicating to a JTAG interface using an Enhanced Parallel Port.
2. Background Information
Some processors provide an interface to allow external control or input into the processor's core logic for debug or downloading of information. One such interface is a Joint Test Action Group (JTAG) interface that allows a form of communication to an external device for debugging or programming of internal memory on the processor. The JTAG interface is an Institute for Electrical and Electronic Engineers (IEEE) Standard 1149.1 interface. In the IEEE 1149.1 specification this interface is referred to as a Test Access Port (TAP). A host device may be connected to the JTAG interface of a target device (e.g., processor) using the parallel port of the host device. The simplest form of host-to-target interface is that for every bit on JTAG, one byte is transferred on a parallel port in Standard Parallel Port (SPP) mode. Generally, during JTAG interface operation a data in clock is sent along with each byte of data transmitted. Since an instruction is needed for every byte sent, to send 10 bytes of data, 10 instructions are needed. This can be problematic in that this process is slow in both a debug mode as well as in a memory programming mode.
Currently, since a parallel port in SPP mode is used to send information across to a target device's JTAG interface, in order to send a bit across the JTAG port in SPP mode, software at the host must make three port accesses.
Therefore, there is a need for a faster and more efficient way to transfer information to a JTAG interface (i.e., Test Access Port).