The present application relates to system and method for probing ultra-fine features in integrated circuits (ICs), and in particular, to optical microscopy techniques for probing sub-32 nm semiconductor integrated circuits.
To improve an integrated circuit functionality and performance, IC manufacturers have been, in the last four decades, shrinking the sizes of circuit components and at the same time, increasing the number of circuit components. It becomes necessary to reduce the size of the circuit features, that is, as shown in FIG. 1, the lines and spaces that make up the circuit elements on the semiconductor substrate. The circuit features, referring to FIG. 1, are predominantly aligned along two orthogonal X and Y directions. One direction (e.g. x) can be called the circuit horizontal direction; another direction (e.g. y) can be called the circuit vertical direction. The minimum feature size that can be accurately produced on a substrate is limited by the ability of the fabrication process to form an undistorted optical image of the mask pattern onto the substrate, by the chemical and physical interaction of the photo-resist with the developer, and by the uniformity of the subsequent process (e.g., etching or diffusion) that uses the patterned photo-resist.
The minimum feature size of an IC is defined by design rules. Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly. The most basic design rules are single layer rules. For example, a width rule specifies the minimum width of any shape in the design. A spacing rule specifies the minimum distance between two adjacent objects. The smallest rules, as defined by the International Technology Roadmap for Semiconductors (ITRS), have decreased from 65 nm in 2006, 45 nm in 2008, and 32 nm in 2010, to 22 nm in 2012 and 14 nm (˜2014) for the current and next generation CMOS IC fabrication technologies.
As electronic devices become more miniaturized and more powerful, IC devices become smaller and more devices are packed in each chip. The cost of manufacturing has increased and the yield is decreased and the new causes of yield decrease emerge as new materials used and shrinking process variation tolerances.
Probing tools are frequently utilized during testing and debugging integrated circuit (IC) designs and layouts, where efforts are focused on defect localization and accurate waveform and timing measurements of signal switching inside sub-volt devices. Signal measurements are performed through the back side of the device.
The rapidly decreasing circuit features in electronic devices present significant challenge to debug and analytical tools to discern increasingly smaller circuit features and to preform timing analysis on a given transistor node.
Accordingly, there is a need for improved analytical method to probe and analyze ultra-fine circuit features in ICs fabricated by 22 nm or smaller CMOS technologies.