1. Technical Field
The present invention relates to electronic circuits in general, and in particular to an electronic circuit for providing clock signals. Still more particularly, the present invention relates to a phase-locked loop circuit for providing external clock signals to a processor.
2. Description of the Prior Art
Electronic circuits for providing clock signals are utilized in a wide assortment of digital devices and components. For example, within a computer system, processor(s) and other components such as random access memories, utilize clock signals to synchronize various operations. As the operating frequency of processors becomes higher and higher, approaching 1 GHz and beyond, it becomes increasingly difficult to provide an external clock signal having the same frequency as the processor clock. The recent trend is to alleviate this problem by utilizing a phase-locked loop (PLL) circuit to supply an external clock signal.
In the prior art, a PLL circuit typically includes a phase/frequency detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase/frequency detector compares two input signals, namely, a reference signal (from an external system clock) and a feedback signal, to generate a phase error signal that is a measure of their phase difference. The phase error signal from the phase/frequency detector is filtered by the low-pass filter and fed into the control input of the VCO. The VCO then generates a periodic signal with a frequency controlled by the filtered phase error signal. The VCO output is coupled to the feedback input of the phase/frequency detector, thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the VCO frequency to shift toward the frequency of the reference signal, until the VCO finally locks onto the frequency of the reference signal. Phase acquisition follows in a similar manner. The output of the VCO is then utilized as a clock signal for a processor.
Although a PLL circuit allows an external clock source of a relatively low frequency to be utilized for clock signal synthesis, jitter is also added to the synthesized clock signals during the process. In fact, it is very difficult to control these high frequency PLL jitters due to the high intrinsic sensitivity of the VCO to process, environment, and noise, along with the proportionally smaller timing budget allowance. Consequently, it is desirable to provide an improved PLL design that reduces high frequency PLL jitter.