A continuing trend in semiconductor technology is to fabricate integrated circuits with more devices per unit area of die to increased performance, and lower operating voltages. This trend has resulted in shrinking of specific device features and minimum groundrule dimensions in general.
In integrated circuits having field-effect transistors (FETs), one very important feature is the gate conductor width and the attendant device channel width. In many applications the performance characteristics (e.g., switching speed) and density achievable (e.g., overall size of the FETs) are functions of the gate conductor width. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) and a smaller device. In the case of dynamic random access memories (DRAMs), in addition to the effects of gate width just noted, there is an effect of polysilicon wordlines and passing wordlines on memory cell density. Narrower polysilicon wordlines and passing wordlines allow denser cell design. In DRAMs, gate conductors and wordlines and passing wordlines are often simultaneously and integrally formed.
Limitations to existing fabrication techniques, notably lithographic tools and process, is limiting the minimum polysilicon line and polysilicon gate width. Lithography is not scaling with the decrease in device channel width, gate width and polysilicon line width. Often polysilicon line and polysilicon gate widths need to be smaller than the minimum feature size producible by the lithographic process. Accordingly, there is a need for efficient and effective fabrication methods for forming polysilicon lines and polysilicon gates that are smaller (even sub-minimum groundrule) and/or result in higher performance devices.