1. Field of the Invention
This invention relates to a high-breakdown-voltage resistance element for use in a high-power, i.e., high-breakdown-voltage semiconductor integrated circuit.
More particularly, this invention relates to a resistance element having an impurity region disposed in a surface region of a semiconductor body, and having a high-breakdown-voltage characteristic.
2. Description of the Prior Art
A diffused resistance is generally used as a resistance element in a semiconductor integrated circuit (an IC or an LSI). FIGS. 1A and 1B are a schematic plan view and a schematic sectional view respectively to show one form of such a diffused resistance in a semiconductor integrated circuit. Referring to FIGS. 1A and 1B, a silicon epitaxial-grown layer (a collector epitaxial layer) 12 of N-type conductivity is formed on a silicon substrate 11 of P-type conductivity. Diffusion layers 13 and 13' are formed in the silicon epitaxial-grown layer 12 of N-type conductivity, each of which is a base diffusion layer of P-type conductivity or an emitter diffusion layer of N.sup.+ -type conductivity and provides a resistor body. Numeral 14 designates an isolation region of P.sup.+ -type conductivity, and numeral 15 designates an insulating film of an electrical insulator such as SiO.sub.2. Numerals 16, 16' designate electrodes provided by depositing a metal such as aluminum, and numerals 17, 17' designate contact holes.
FIGS. 1A and 1B illustrate, by way of example, that two resistance elements 10 and 10' are provided in a single isolated region 12.
When such a diffusion layer 13 (13') of P-type conductivity or N.sup.+ -type conductivity is formed in the semiconductor layer 12 of N-type conductivity to function as a resistor body as shown in FIGS. 1A and 1B, a parasitic MOS transistor tends to be produced by the mobile carriers at the oxide-resin-package interface or the interface between the insulating film 15 and the semiconductor layer 12. In such a case, a conductive channel will be formed to extend between the resistor bodies 13, 13' or between the resistor body 13 and the diffusion layer 14 provided for isolation, as shown by the dotted lines in FIG. 1A, resulting in undesirable variation of the resistor value or in undesirable formation of a parasitic resistor.
The tendency of the production of such a parasitic MOS transistor appears markedly especially when the diffused resistance is supplied with a high voltage thereacross. Therefore, in an application in which a high voltage is applied across the diffused resistance, it has been a prior art practice that the electrodes 16 and 16' are extended to provide field plates 160 which cover substantial portions of the surface of the diffusion layers 13 and 13' of P-type or N.sup.+ -type conductivity.
However, a single layer electrode cannot be used to cover all the surface areas of the resistor bodies 13 and 13' because of the fact that a high-potential electrode and a low-potential electrode are required for each resistance element. Thus, resistor portions 18 and 18' not covered with the electrode layer remain as seen in FIGS. 1A and 1B, and these portions 18 and 18' will still act as a source and a drain of a parasitic MOS transistor tending to be produced by the mobile carriers at the oxide-resin-package interface.
The action of such a parasitic MOS transistor results in undesirable variation of the resistor value or in the undesirable formation of a primarily unnecessary parasitic resistor as pointed out hereinbefore. Thus, the problem of obtaining a predictable normal operation required for a resistance element in an integrated circuit has previously been unsolved, especially in high voltage.