Due to their complementary functionality, bipolar transistors and junction field effect transistors (JFETs) are often formed as part of the same integrated circuit. When the support architecture employs dielectrically isolated islands for device separation, it is common practice to form a JFET in the manner diagrammatically illustrated in FIG. 1, by using an island layer 11, which is dielectrically isolated from a surrounding substrate 13 by means of an insulator layer (e.g. oxide) 12, as a channel region 16, and a diffusion region 17 as a topside junction gate. High impurity concentration regions 18 and 20 form respective source and drain contacts for the island. The bottom 21 of channel region 16 is bounded by isolation oxide 12, with substrate 13 therebeneath acting as a bottom gate. If complete saturation of the drain characteristic or pinch-off is desired, substrate 13 must be biased at a voltage such that the topside junction gate region 17 is able to control the entire channel charge. Unfortunately, the structure of FIG. 1 suffers from several problems.
More particularly, in order to keep the pinch-off voltage V.sub.p low, it is necessary that the space or separation x.sub.d between the bottom of junction gate 17 and the bottom boundary 21 of the channel island 11 be kept small. Using a one-sided step junction model to define the pinch-off voltage, then EQU V.sub.P =x.sub.d.sup.2 qN.sub.c /2k . . . (1)
where:
N.sub.c =channel doping concentration PA1 q=channel charge, and PA1 k=dielectric constant of the semiconductor of the island.
Normally, the thickness required to achieve the desired pinch-off voltage is less than that required beneath a diffusion region of other operational purposes. Two conventional mechanisms for dealing with this problem involve the use of a special deep diffused region for the gate and the formation of special thinner islands by means of masked backside etching during the dielectric isolation fabrication process. However, each of these techniques requires an additional masking operation as well as other extra process steps, thus increasing manufacturing complexity and cost.
A second problem with the structure of FIG. 1 is the fact that channel thickness x.sub.d will vary as island thickness varies as a result of dielectric isolation fabrication process tolerances. This variation in channel thickness, in turn, leads to a large variation in pinch-off voltage, which is undesirable for most JFET circuit applications.
A third problem with the configuration of FIG. 1, which becomes especially severe when a high breakdown voltage is required, relates to control of the channel at the ends of the gate region adjacent to the dielectric sidewall boundaries of the island. As at the bottom of the channel, at the ends of the gate region there is an associated pinch-off voltage similarly defined by equation (1) above. To keep this pinch-off voltage n higher than the pinch-off voltage at the bottom of the channel, the sidewall spacing at the ends of the gate must be smaller than the bottom separation x.sub.d. Control of this spacing differential is made difficult due to the variation in location of the island edge and the fact that there must be at least one mask alignment tolerance between the gate and the island edge.
One conventional solution to this problem is to use a gate that has a closed configuration with either the drain or the source contact contained within it, which necessitates running the conductor to the enclosed region over the gate junction. As a consequence, at a high voltage the conductor acts as a field plate, thereby reducing the breakdown voltage of the junction which it crosses.