1. Field of the Invention
This invention relates to integrated circuit structures formed on semiconductor wafers. More particularly, this invention relates to integrated circuit structures having conductive interconnections formed between the electrodes of transistors at the electrode level, and a method of making same.
2. Description of the Related Art
In the conventional prior an production of integrated circuit structures such as, for example, gate array MOS structures, as illustrated in prior art FIGS. 1A, 1B, and 2, a silicon wafer 2 is masked, after formation of P-wells and/or N-wells, to define the areas or islands 10 where one or more MOS transistors will be formed, e.g., P-islands and N-islands. Field oxide 14 is then grown on the unmasked portions of wafer 2 to isolate each MOS island 10 from adjacent islands 10 or other devices on wafer 2.
After removal of the field oxide mask, a thin gate oxide layer is grown over the silicon wafer and a polysilicon layer is then deposited over the wafer from which the gate electrodes will be formed. The polysilicon layer is patterned to form single polysilicon strips 20 which comprise one or more gates in a single MOS island 10 and contact pad or "dogbone" areas 28 which extend over the field oxide 14 which surrounds that particular MOS island 10.
Source and drain regions 30 and 32 are then formed in MOS islands 10 by appropriate doping. A self-aligned silicide (salicide) layer (not shown) may then be formed over polysilicon strips 20. A layer of insulation 36, such as an oxide layer, is then formed over the structure and appropriate planarizing may then be carried out.
At this point in the conventional process, as shown in FIG. 1A, what has been formed is a genetic structure wherein the MOS device or devices beneath each polysilicon strip 20, i.e, the MOS device or devices for which polysilicon strip 20 comprises the gate electrode(s), is electrically independent from any other MOS transistors formed beneath other polysilicon strips in other islands or other wells, although electrically coupled through source/drain 32 to the adjacent strip (or strips) 20 in the same island.
Alternatively, as shown in FIG. 1B, pairs of N channel and P channel transistors in adjacent islands may be connected together in single pairs respectively by strips 20'a and 20'b. The pairs are electrically isolated from pairs in other islands, but as in FIG. 1A, the respective transistors in the pair may be electrically coupled through source/drain 32 to the adjacent strip (or strips) in the same island.
In either instance, it has become a practice, with many integrated circuit chip or die manufacturers, to form such genetic structures (usually referred to as "gate arrays") in high volume, and then to use such an inventory of partially prefabricated integrated circuit structures or "gate arrays" for the subsequent production of custom dies, i.e., integrated circuit dies with specific and specialized electrical circuitry implemented in the silicon chip by subsequently customizing the interconnections between the array of independent and unconnected MOS, bipolar, MOS/bipolar, or other active device structures formed by the genetic structure.
Depending upon the desired electrical circuitry to then be implemented in the genetic integrated circuit structure, these various electrically isolated transistors are then connected or "wired" together by formation of a wiring harness comprising one or more patterned metal layers or strips 40 formed over previously deposited insulation layer 36, with further insulation layers formed between the patterned metal layers, when more than one patterned metal layer is used.
As shown particularly in FIG. 2, the formation of such connections between the illustrated MOS gate electrodes aim involves formation of contacts or holes 50 through insulation layer 36 from metal strips 40 to each of the polysilicon contact pads 28 and as well as the filling of each such contact hole 50 with a conductive material 54 to provide the necessary electrical path between polysilicon contact pad 28 and patterned metal layer 40.
Due to the complexity of such wiring, and the need for crossover wiring, it is often necessary to provide two and even three such patterned metal layers, i.e., metal strips, to achieve the desired electrical connections between the various active devices such as the illustrated MOS devices on wafer 2. Since each such contact opening made between polysilicon contact pads 28 and the overlying metal strips 40, or vias formed between metal layers, can result in failures due to misalignment, underetching, overetching, or improper filling of the contact or via opening, an increased number of such contacts and layers of wiring strips can have a negative impact on the overall yield of chips or dies from the semiconductor wafer.
It would, therefore, be desirable if at least some of the electrical interconnections between various active devices on a substrate (i.e., MOS, bipolar, or other active devices) could be carried out in a manner which would reduce the number of contacts needed between the electrodes of conductive material and the metal harness, as well as possibly eliminating the need for at least one metal wiring layer, when multiple metal wiring layers are used to form the wiring harness, and while still permitting the initial formation of a genetic gate array type structure capable of being subsequently electrically connected together to form a variety of different electrical circuits.