Field of the Invention
The present invention relates a semiconductor memory device and, more specifically, a semiconductor memory device having data transition detector (DTD).
A static random access memory (SRAM) not requiring refreshing operation is one of volatile semiconductor memory devices. In the SRAM, input data is supplied to a write driver. The write driver is activated in response to an externally supplied write enable signal, and in write mode, writes the supplied input data to one selected memory cell. At this time, since write driver is neutralized during the write mode, it continues writing data even after the data has been written to the memory cell. Accordingly, a large amount of current for writing flows from a bit line load to the bit line, and large amount of operational current also flows to the write driver and sense amplifier and the like. Therefore, power consumption at the time of writing is considerable in the SRAM.
In order to reduce power consumption at the time of writing, an SRAM having a DTD has been proposed. An SRAM having the DTD is disclosed, for example, in Japanese Patent Laying Open No. 1-251496. The DTD generates, when input data changes, a data transition detecting signal for a prescribed time period. The DTD also generates the data transition detecting signal when write enable single changes from a read state to write state, for a prescribed time period. In the SRAM having the DTD, write driver is activated in response to the data transition detecting signal. Therefore, write driver writes the input data to the memory cell only for the prescribed time period from the change of the input data, and it does not continue writing of data after completion of writing. Therefore, the above described extra current does not flow, and power consumption can be reduced.
However, when there is a noise generated in the write enable signal, the DTD generates the data transition detecting signal in response to the noise. This leads to a problem that write driver is erroneously activated and data is written to a memory cell which has been selected for reading.
Thus, the SRAM having the DTD suffers from the problem of so-called erroneous writing, in which operation temporarily changes from the read state to the write state because of noise included in the write enable signal resulting in erroneous writing of data memory cell, though the SRAM is advantageous in view of reduced power consumption.