The present invention generally relates to a semiconductor integrated circuit device, and specifically relates to power-on clearing circuit integrated in the semiconductor device for generating a reset or clearing pulse effective to clear the device at the time of power on.
As shown in FIG. 2, the conventional power-on clearing circuit provided in a semiconductor integrated circuit device is comprised of a capacitor 1 and a current-flow regulating element 2.
The FIG. 2 power-on clearing circuit can effectively generate a reset pulse or initializing pulse when a rising rate of a power source voltage at the time of power-on is sufficiently greater than a charging rate of the capacitor 1. However, as shown in FIG. 3, when the rising rate of the power source voltage is smaller than the charging rate of the capacitor 1, the capacitor 1 can be fully charged during the rising period of the power source voltage, thereby causing a drawback that the power-on clearing circuit fails to generate a reset pulse.
There is another conventional method employing a power source voltage detecting circuit operative to generate an output signal to be used as a system clear pulse. However, such a circuit may inadvertently generate an output pulse when a varying power source voltage falls below a given reference voltage, thereby disturbing normal operation of a system utilizing such a circuit. Further, the power source voltage detecting circuit must be regularly powered to continuously monitor the power source voltage, thereby causing a drawback that a useless electric current is consumed in the detecting circuit.