Serial Rapid Input Output (SRIO) and Peripheral Component Interconnect Express (PCIe) are known to one of skill in the art as input/output (I/O) interfaces. Equally well known to one of skill in the art is that SRIO and PCIe have differing specifications, protocols, and requirements.
SRIO based End-Points (EP) rely on flowid to route, watermarks to store, and Request-Grant-Accept (RGA) type algorithm to schedule packets. When the SRIO EP is used in a bridge application, the existing packet routing and scheduling schemes cannot transfer packets while meeting both SRIO and PCIe ordering rules and may create deadlock in the system. This presents a problem.