1. Field of the Invention
This invention relates to the field of computer system architecture. More particularly, this invention relates to accessing configuration registers in a bus bridge circuit.
2. Background
In a computer system, peripheral components, such as disk drive controllers, network controllers, and graphics controllers, may be coupled to peripheral component buses separate from a host, or CPU bus. There are several reasons a system might employ peripheral component buses. For example, it may be desirable to isolate slower speed devices from higher bandwidth buses and peripherals. Also, an intelligent peripheral component may have a local peripheral component bus. Moreover, the system may have more peripheral components than can be reliably placed on the host bus, due to electrical loading effects.
In such a system, a host bridge circuit enables communication between the peripheral component bus and the host bus. The host bridge circuit enables an access request that initiates on the host bus to have a destination on the peripheral component bus, and enables an access request that initiates on the peripheral component bus to have a destination on the host bus. The host bridge circuit can also enable access to a shared resource from both buses. Typically, the host bridge circuit contains a set of configuration registers that define parameters for processing access cycles between the buses, and for controlling the shared resource. System I/O software performs reads and writes to the configuration registers in order to define the parameters.
However, integrated circuit subsystems in the host bridge circuit require enough signal lines to communicate address, data, and control information for both the host bus and the peripheral component bus. The resulting large packages sizes of the integrated circuit devices greatly increases the system cost. Moreover, the host bridge devices must process memory accesses to the shared resource as well as I/O access of configuration registers, which increases the complexity of logic implemented in the host bridge devices.
As will be described, the present method and apparatus reduces cost and complexity of devices for a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers.