1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of so-called metal oxide field effect transistors (MOSFETs or FETs). A transistor includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region that is separated therefrom by a gate insulation layer. Current flow between the source and drain regions of the FET device is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the channel length of FETs over the past decades, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. Additionally, decreasing the channel length may lead to an undesirable increase in so-called off-state leakage currents, i.e., the amount of current that flows through the transistor when it is turned “OFF.”
Transistors come in a variety of configurations. A conventional FET is a planar device, wherein the transistor is formed in and above an active region having a substantially planar upper surface. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12. The device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap layer 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. In this example, the fins 14 are comprised of a substrate fin portion 14A and an alternative fin material portion 14B. The substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion 14B may be made of a material other than the substrate material, for example, silicon-germanium. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET device, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces undesirable short channel effects. When an appropriate voltage is applied to the gate electrode 16 of a FinFET device 10, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin (for a tri-gate device), form a surface inversion layer or a volume inversion layer that contributes to current conduction. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, FinFET devices exhibit less off-state leakage currents as compared to planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. As noted above, device designers are currently investigating using alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is non-trivial due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to FIG. 1, the lattice constant of the alternative fin material portion 14B of the fin 14 may be substantially greater than the lattice constant of the substrate fin portion 14A of the fin 14. As a result of this mismatch in lattice constants, an unacceptable number of defects may be formed or created in the alternative fin material portion 14B. As used herein, a “defect” essentially refers to a misfit dislocation at the interface between the portions 14A and 14B of the fin 14 or threading dislocations that propagate through the portion 14B on the fin 14 at well-defined angles corresponding to the (111) plane.
However, FinFET devices still exhibit some performance-limiting characteristics. As noted above, one such characteristic that is detrimental to all forms of semiconductor devices, both FinFETs and planar FETs, is off-state leakage currents. Ideally, off-state leakage current is minimized to increase device performance. In the case of a bulk FinFET device, it has been noted that the so-called “punch through leakage current” densities vary along the vertical height of the fins, with the current densities being much greater at the bottom of the fins proximate the local isolation regions of the device. See, e.g., Okano et al., “Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length,” IEDM Technical Digest, pp. 721-724, 2005. Efforts have been made in the past in attempts to reduce such punch through leakage currents in FinFET devices.
FIGS. 2A-2F depict one illustrative prior art method of forming isolated fins for a FinFET semiconductor device in an attempt to reduce or eliminate such off-state leakage currents. FIG. 2A depicts the device at a point in fabrication after one or more etching processes were performed through a patterned etch mask (not shown) to define a plurality of initial trenches 13 in the substrate 12. The formation of the trenches 12 results in the formation of a fin structure 14 comprised of the substrate material. The width and height of the fin structure 14 as well as the depth of the trenches 13 may vary depending upon the particular application. FIG. 2B depicts the device after a sacrificial liner layer 22 (e.g., silicon nitride) was formed on the exposed portions of the fin 14. FIG. 2C depicts the device after another anisotropic etching process was performed to extend the initial depth of the initial trenches 13 in the substrate 12. This second etching process results in a plurality of second trenches 24. Next, as shown in FIG. 2D, the trenches 24 were overfilled with an insulating material 26, e.g., silicon dioxide, an oxygen-rich silicon dioxide, etc., or multiple layers thereof, etc. FIG. 2E depicts the device after a thermal anneal process 28 was performed on the device. The thermal anneal process 28 was performed under conditions such that substantially all of portions of the fin 14 not covered by the sacrificial layer 22 are oxidized, i.e., converted into an insulating material, e.g., silicon dioxide, as indicated within the dashed-line region 30. FIG. 2F depicts the device after a recess etching process was performed to recess the layer of insulating material 26 to a desired height such that the desired amount of the fin 14 is exposed above the surface of the layer of insulating material 26. Thereafter, one or more etching processes were performed to remove the sacrificial liner layer 22. At this point in the process flow, the final fin structure 14 has been exposed to its final desired fin height and isolation material is positioned laterally under the entire width of the final fin structure 14. At this point, traditional manufacturing operations may be performed to complete the fabrication of the illustrative FinFET device, e.g., gate formation, etc.
Several other prior art techniques have been employed in an attempt to reduce offstate leakage currents. These include, but are not limited to, (1) directly undercutting the fin and backfilling the undercut area with an insulating material; (2) forming a sacrificial fin structure, forming a layer of insulating material adjacent the sacrificial fin structure, forming final fin structures on the sidewalls of the sacrificial fin structure and on top of the layer of insulating material and removing the sacrificial fin structure; (3) forming a patterned layer of insulating material on a substrate, growing an epi material above the layer of insulating material by growing epi on the exposed portions of the substrate and patterning the fins from the epi material that is positioned above the layer of insulating material; and (4) formation of epi material on a single crystal insulating material (e.g., a rare earth oxide) and thereafter patterning the epi material to define the fins. All of these methods present significant challenges when it comes to forming FinFET devices with alternative channel materials. What is needed is an efficient and cost-effective method of forming alternative channel materials on FinFET devices that reduces or eliminates the above-described “punch through leakage currents” in such devices.
The present disclosure is directed to various methods of forming isolated fins for a FinFET semiconductor device with alternative channel materials that may solve or reduce one or more of the problems identified above.