1. Field of the Invention
The present invention is directed to techniques for fabricating solid state memories and, more particularly, to techniques used in the fabrication of ultra-dense solid state memories.
2. Description of the Background
Techniques for fabricating solid state memories have been commercially available for many years. During that time, there has been, and continues to be, pressure to shrink the size of the individual memory cell so that memories of larger and larger capacity can be fabricated. That pressure has lead to the development of unique components. For example, the trench capacitor and stacked capacitor have been developed. Those components are three-dimensional structures. By fabricating the capacitors in an upward direction, less planar surface of the chip is used thereby permitting a more dense circuit architecture. In such three dimensional components, the edge or vertical portion of the component plays an important role in determining the component's characteristics.
New fabrication techniques must often be developed to enable such unique components to be realized. Preferably, the techniques needed to fabricate such components are developed in such a manner that a manufacturer's existing fabrication equipment can be used so that the expense of purchasing costly new equipment can be avoided, or at least postponed.
The pressure to continually fit more memory cells into a given amount of space has also lead to new circuit architectures. For example, U.S. Pat. No. 5,214,603 discloses a folded bitline, dynamic random access memory cell which utilizes a trench capacitor and a planar-configured access transistor that is stacked over the capacitor.
As components become smaller and are packed closer together, leakage and second order effects become more and more significant. Current circuit architectures fabricated with commercially available techniques, while very capable of producing dense memories, are not capable of being scaled down to the levels needed to produce ultra-dense memories on the order of 256 megabits and higher. Thus, the need exists for a method and circuit architecture for enabling active devices to be fabricated in such a manner that the active devices can be packed in an ultra-dense manner using currently available fabrication equipment.