The present invention relates to a voltage level converter circuit and, more particularly, to a level converter circuit for converting a voltage level from the vicinity of an ECL (i.e., Emitter Coupled Logic) level to the vicinity of a CMOS (i.e, Complementary MOS) or TTL level.
The circuit which can operate at the highest speed of all the logic circuits used in the prior art is the ECL circuit which is composed of bipolar transistors. In case such an ECL circuit composed of bipolar transistors is made to coexist in one chip for use in a mixed circuit with either a CMOS circuit or a CMOS circuit and a bipolar transistor, a level change is required either from the ECL level to the CMOS level or between their neighborhood levels.
One example of such a level converter circuit is disclosed in Japanese Patent Laid-Open No. 50-142132.