The trend in semiconductor fabrication technology is toward the construction of smaller and smaller devices. As the feature size of individual components within a semiconductor device is reduced, the packing density of the devices can be increased. Accordingly, in addition to fabricating devices having reduced feature sizes, cell architecture plays an important role in achieving high packing densities. Electrically-erasable-read-only-memory (EEPROM) devices are particularly difficult to fabricate at high packing density because of the relatively large capacitive coupling necessary to program and erase the device. Further, EEPROM cells require high voltage and low voltage transistors for their operation. These factors lead to relatively large cell size and accompanying smaller storage capability as compared to volatile memory devices, such as dynamic-random-access-memory (DRAM) and static-random-access-memory (SRAM) devices, and the like.
EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs devices can have a two-transistor design or a three-transistor design. A three-transistor EEPROM cell, for example, includes a write transistor, a read transistor, and a floating-gate (or sense) transistor. In a two-transistor device, the functions of the read and write transistor are combined into a single transistor. Although the read and write functions can be combined into a single transistor to produce an EEPROM cell having only two transistors, a relatively large surface area must still be provided to accommodate the capacitive coupling necessary to program and erase the memory cell.
To program an EEPROM cell, a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively low voltage Vpp is applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on, allowing the voltage applied to the bit line to be transferred to the source of the write transistor. Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell. In a typical EEPROM cell, the electron path from the floating-gate electrode to the source of the write transistor can involve traversal of a relatively high resistance path in view of the relative positioning of the write transistor and the floating-gate transistor.
To erase an EEPROM cell, a voltage Vcc is applied to the gate of the write transistor, a ground potential is applied to the bit line, and a high voltage Vpp+ is applied to the control-gate electrode. Under this bias condition, the high voltage applied to the control-gate electrode is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode. The transfer of electrons during the erase cycle typically takes place through a tunnel oxide layer underlying the floating-gate electrode.
The efficient transfer of electrons to and from the floating-gate electrode is essential to high performance operation of an EEPROM cell. Notably, both two-transistor and three-transistor EEPROM cells depend on rapid transfer of charge between the floating-gate electrode and underlying substrate regions. Accordingly, the operational efficiency of various types of EEPROM cells can benefit from enhancements in the charge transfer structures within the memory cell.