1. Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, the invention relates to a system for analyzing defects on binary intensity masks, phase-shifting masks and next generation lithography (NGL) masks used in the manufacture of integrated circuits.
2. Description of Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto a template (i.e. a mask), and then to the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes, which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit is to transfer the layout onto a semiconductor substrate. One way to do this is to use the process of optical lithography in which the layout is first transferred onto a physical template, which is in turn used to optically project the layout onto a silicon wafer. Other types of wafers can be used, e.g. silicon germanium, etc.
In transferring the layout to a physical template, a mask (usually. a quartz plate coated with chrome) is generally created for each layer of the integrated circuit design. This is done by inputting the data representing the layout design for that layer into a device, such as an electron beam machine, which writes the integrated circuit layout pattern into the mask material. In less complicated and dense integrated circuits, each mask comprises the geometric shapes that represent the desired circuit pattern for its corresponding layer. In more complicated and dense circuits in which the size of the circuit features approach the optical limits of the lithography process, the masks may also comprise sub-lithographic, optical proximity correction features, such as serifs, hammerheads, bias and assist bars, designed to compensate for proximity effects. In other advanced circuit designs, phase-shifting masks may be used to circumvent certain basic optical limitations of the process by enhancing the contrast of the optical lithography process.
These masks are then used to optically project the layout onto a silicon wafer coated with photoresist material. For each layer of the design, a light (visible/non-visible radiation) is shone on the mask corresponding to that layer via a visible light source or an ultra-violet light source. This light passes through the clear regions of the mask, whose image exposes the underlying photoresist layer, and is blocked by the opaque regions of the mask, thereby leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This process is then repeated for each layer of the design.
As integrated circuit designs become more complicated, it becomes increasingly important that the masks used in photolithography are accurate representations of the original design layout. Unfortunately, the electron beam and other machines used to manufacture these masks are not error-free. Thus, in the typical manufacturing process, some mask defects do occur outside the controlled process.
A defect on a mask is anything that is different from the design database and is deemed intolerable by an inspection tool or an inspection engineer. A photolithographic mask can comprise a plurality of opaque areas (typically made of chrome) and a plurality of clear areas (typically made of quartz). In a bright field mask, the background is clear and the circuit pattern is defined by opaque areas. In a dark field mask, the background is opaque and the circuit pattern is defined by clear areas. Common mask defects that occur during a bright field mask manufacturing process include, for example, an isolated opaque pinhole defect in a clear area, an isolated clear spot defect in an opaque area, an edge intrusion defect in an opaque area, an edge protrusion defect in a clear area, a geometry break defect in an opaque area, and a geometry bridge defect in a clear area. Similar type defects can occur in a dark field mask manufacturing process. Defects may also occur in the sub-resolution optical proximity correction (OPC) features provided on the chip. These OPC features could include, for example, serifs, hammerheads, and assist lines.
FIG. 1 illustrates a known method of analyzing a mask for one or more of the above-described defects. After designing an integrated circuit 100 and creating a data file 110, the mask design data is provided to a device such as an electron beam or laser writing machine and a mask is manufactured 115. The mask is then inspected for defects as shown in step 120. In this inspection, the surface of the mask can be scanned with a high resolution microscope (e.g. optical, scanning electron, focus ion beam, atomic force, and near-field optical microscopes) and capturing images of the mask. These mask images can then be observed off-line by an engineer or on-line by a mask fabrication worker to identify defects on the physical mask. Then, a decision is made in step 125 whether the inspected mask is good enough for use in the lithography process. This decision can be made off-line by a skilled inspection engineer or on-line by a fabrication worker, possibly with the aid of inspection software. If there are no defects, or defects are discovered but determined to be within tolerances set by the manufacturer or end-user, then the mask passes inspection and can be used to expose a wafer in step 140. If defects are discovered that fall outside tolerances, then the mask fails inspection and a decision is made in step 130 as to whether the mask can be cleaned and/or repaired to correct the defects in step 135, or whether the defects are so severe that a new mask must be manufactured (returning to step 115). This process is continued until a manufactured mask passes inspection.
Once a physical mask is produced that passes inspection, the mask is further inspected to ensure that the mask will produce the desired image on a photoresist after a wafer is exposed to light through the mask. Typically, this inspection includes exposing and processing a wafer in step 140 using the inspected mask. The processed wafer is then inspected in step 145, and a decision is made in step 150 as to whether there are any defects and whether the defects fall within tolerances. If discovered defects are substantial, then, as before, a decision is made in step 130 whether the defects can be repaired or whether a new mask must be produced in step 115. This process is continued until a mask is manufactured that will produce desired wafer patterns and that will pass the wafer level inspection, thereby ending inspection in step 160. This mask is then used in the lithography process to expose the corresponding layer in the overall manufacturing process.
The goal of defect inspection is to correctly identify a defect to avoid a failed wafer processing. However, not all mask defects are important with respect to the desired result, i.e. an accurate representation of the original design layout on the photoresist material or etched into silicon. Specifically, not all mask defects will “print.” Loosely speaking, the printability of a defect is how a defect would impact the outcome of a given photolithography and/or etching process. Because the printability of a defect is mainly associated with the stepper exposure conditions, a defect can be “not printable” for a particular set of stepper exposure conditions and “printable” under a different set of stepper exposure conditions. These conditions for optics based lithography can include, for example, defect size, wavelength, numerical aperture, coherence factor, illumination mode, exposure time, exposure focus/defocus, and the reflection/transmission characteristics of the defect.
Currently, inspection tools that are in use include tools that inspect masks both on-line (i.e. within the production line) and off-line. Conventional on-line inspection tools typically scan the entire mask area looking for defect areas, and some may also compare the inspected result with the mask layout database when defects are detected. However, the defect analysis of the typical on-line inspection tools are based primarily (or solely) on the size of the defect picked up by the optics to define the severity of a particular defect. While this scheme has been somewhat successful in the past, current masks are designed with smaller and smaller features that include advanced and unconventional methods such as OPC. Due to these changes, conventional methods of inspection are rapidly proving to be inadequate because they do not address several issues.
First, whether a defect prints or not greatly depends on both its location and size, not just size or transmission/reflection/phase characteristics alone. For example, a large defective spot in an isolated area may have little or no effect on the current and subsequent process layers. On the other hand, a small spot near a corner, an edge, or a critical area should not be dismissed without closer examination. This is true for both conventional binary masks and advanced masks. Second, advanced OPC mask features can trigger false defect detections. A conventional scheme can falsely report an OPC feature or an imperfect OPC feature as a defect, when this feature actually has little impact on the end result. Although some existing mask inspection tools have a sliding scale setting to “tolerate” OPC features, this is not a robust method because defects associated with these special features may be overlooked because of this arbitrary scale. Additionally, OPC features are typically designed for a specific set of stepper parameters, whereas sliding scales are blind to these stepper parameters. Third, phase information is not properly incorporated into consideration, if at all, in conventional defect inspection methods. Therefore, phase-shifting masks are not properly inspected. Finally, even though a defect may not appear to print, the defect can affect the process latitude in a way that will decrease yield and not be detected by conventional on-line defect inspection systems.
Off-line inspection stations, which either scan for defects directly or review previously stored undetermined defect data from an on-line tool, face the same issues. In addition, an a engineer having the requisite expertise may be needed to resolve these issues, thereby diminishing throughput while significantly increasing cost. Although an engineer's judgment can greatly reduce the magnitude of the defect printability problem, still, there is not enough certainty and accuracy until the defect is viewed as it appears on an actual wafer after exposure through the mask. This is especially true in current lithography steppers using non-standard illumination modes such as annular and quadruple. Thus, using currently existing inspection systems, it is nearly impossible to judge a defect's printability without actually printing the mask onto a wafer, which is expensive and time-consuming.
Accordingly, in any mask inspection system, the important decision to be made is whether a given defect will “print” on the underlying photoresist in a lithography process under specified conditions. If a mask defect does not print or have other effects on the lithography process (such as unacceptably narrowing the lithography process window), then the mask with the defect can still be used to provide acceptable lithography results. Therefore, one can avoid the expense in time and money of repairing and/or replacing masks whose defects do not print. What is desired then, is a method and apparatus for analyzing masks used in the lithography process that solve the aforementioned problems of currently existing mask inspection systems.