1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. In particular, the present invention relates to interconnect structure that provides connection between semiconductor elements and a method for manufacturing thereof.
2. Background Art
A delay in a signal propagation through an interconnect limits a speed of an operation of a device in semiconductor devices of recent years. A delay constant through an interconnect is represented by a product of an interconnect resistance and a capacitance between interconnects. Thus, copper (Cu) having lower specific resistance is employed as an interconnect material in order to reduce the interconnect resistance to achieve faster operation of a device.
A Cu multiple-layered interconnect is formed by means of a damascene process. A damascene process typically includes: an operation of depositing an insulating film such as an interlayer insulating film; an operation of processing the insulating film to form a recessed section; an operation of depositing a barrier metal; an operation of depositing a Cu thin film, which is referred to as a Cu seed; an operation of filling the inside of the recessed section by means of a Cu plating deposition process by utilizing the Cu thin film as a cathode for an electrolytic plating process; an operation of removing portions of barrier metal and Cu deposited in sections other than the recessed section by means of a chemical mechanical polishing (CMP) process; and an operation of depositing a barrier insulating film.
FIGS. 21A to 21C are cross-sectional views of a semiconductor device, which are useful in describing operations for filling the inside of a recessed section by means of a conventional Cu deposition process. As shown in FIG. 21A, an insulating film 301 and an insulating film 302 are sequentially deposited over a substrate 30. Although detailed descriptions are not presented, the upper surface of the substrate 30 is provided with a semiconductor element such as a transistor, an interlayer insulating film for covering thereof, a contact for join the semiconductor element with the interconnect layer, and, according to the cases, an interconnect layers. A barrier metal film 203 and a Cu interconnect 304 are buried in a trench of the insulating film 301. A recessed section 315 is formed in the insulating film 302 disposed on the Cu interconnect 304, and a barrier metal film 312 and a Cu seed film 314 are sequentially deposited over a bottom surface and a side wall of the recessed section 315 and a surface of the insulating film 302. Then, as shown in FIG. 21B, an electrolytic plating film 340 composed of Cu is deposited over a surface of the Cu seed film 314 by means of a plating process by utilizing the Cu seed film 314 as a cathode electrode. FIG. 21B illustrates a cross-sectional view during the process of the Cu electrolytic plating operation.
A presence of a hollow space in a Cu interconnect in a Cu multiple-layered interconnect, which is referred to as a void, causes an increase in the resistance and a deterioration in the reliability, leading to a problem of reduced production yield of semiconductor devices (chips). Thus, it is important to carry out the Cu deposition (filling) without creating a void in the inside of the recessed section 315 formed in the insulating film 302 during the above-described electrolytic plating process. FIG. 21C illustrates a Cu interconnect after the Cu electrolytic plating process, where a hollow space referred to as a void is generated in the Cu interconnect. The characteristics of electrolytic plating is affected by an electric field intensity, and the deposition rate in an aperture of the recessed section 315, where stronger electric field intensity is present, is higher than that in the side walls of the recessed section 315, and therefore a failure in obtaining sufficiently higher growth rate on the bottom surface of the recessed section 315 causes unwanted closing of the aperture before the deposition of the plated film reaches to the aperture from the bottom surface. Such closure of the aperture causes a stop of a supply of metallic ions contained in a plating liquid into the recessed section 315 and a block of the electric field, so that the growth of the Cu plated film deposited over the bottom surface is stopped before reaching to the aperture, and thus the section in the recessed section 315 without the deposition of the plating process is remained to create a void. Thus, in order to inhibit a generation of such void, an approach of the deposition rate for filling with Cu is locally controlled to provide an increased deposition rate in the bottom surface of the recessed section 315 as compared with the deposition rates in the aperture and the side walls of the recessed section 315 by adding a deposition accelerator and a deposition suppressor to an electrolytic plating liquid. Such approach for the plating process is referred to as a bottom up fill or a super conformal fill.
Here, a polymer such as a copolymer of polyethylene glycol or polypropylene glycol is typically employed for the deposition suppressor. A sodium sulfonate is typically employed for the deposition accelerator.
Detailed mechanism of the bottom up fill is unidentified yet in the present time, and is estimated as follows.
A deposition suppressor and a deposition accelerator are contained in an ordinary electrolytic plating liquid. When a substrate having a seed formed in the inside and the outside of a recessed section is immersed in such electrolytic plating liquid, the deposition suppressor and the deposition accelerator are adsorbed on the surface of the seed with the rates that associates with the densities in electrolytic plating liquid. The actions of the deposition accelerator at the inside of the recessed section are not largely differed from those at the outside of the recessed section in the initial stage of the plating deposition process. However, the growth of the overall plated film leads to a growth of the film from the side walls of the recessed section in the inside of the recessed section, in particular the section around the bottom thereof, and therefore this provides reduced surface area of the seed in the inside of the recessed section. On the other hand, since the deposition accelerator adsorbed over the seed surface is not desorbed, the reduction of the surface area of the seed in the inside of the recessed section causes increased density of the deposition accelerator over the surface of the seed in such section. This results in relatively enhanced effect for accelerating the deposition in the inside of the recessed section, and therefore the rate of the deposition by means of the plating process over the seed in the inside of the recessed section is higher than that in the outside of the recessed section.
A bottom up growth is a process that utilizes the above-described phenomenon, and if the rate of the deposition by means of the plating process in the bottom of the recessed section is sufficiently higher than that in the aperture and the side walls of the recessed section, the plated film grown from the bottom can reach to the aperture before the aperture is closed, and thus the fill of the recessed section is achieved while generations of void in the inside of the recessed section is inhibited.
However, sufficient bottom up growth is not achieved with the conventional electrolytic plating liquids in the situation where the miniaturizations of the semiconductor device are progressed to involve the decreased dimension of the aperture of the recessed section. This is because the smaller dimension of the aperture causes insufficient increase in the concentration of the deposition accelerator over the bottom surface of the recessed section. Therefore, the aperture is closed with the plated film grown at the location of the aperture before the growth of the plated film grown from the bottom surface of the recessed section reaches to the aperture, to eventually form a void.
In order to solve such problem, for example, an approach for utilizing increased concentrations of Cu and sulfuric acid in the plating liquid and utilizing heavier polymerized materials for a plating suppressor and a leveler is disclosed by Jon Reid and Jian Zhou, entitled “Electrofill Challenges and Directions for Future Device Generations”, Advanced Metallization Conference 2007 17/Asia Session. Reid et al. discloses that the increased concentration of sulfuric acid promotes an activation of the accelerator and the increased concentration of Cu provides enhanced precipitation probability, thereby providing improved bottom up performance. Reid et al. also discloses that the uses of heavier polymerized materials for the suppressor and the leveler cause reduced diffusion rates thereof in the plating liquid to provide reduced adsorption to the recessed section at the initial stage of plating deposition process, so that the concentration of the accelerator is increased in the recessed section to allow the bottom up even in the structure of the finer dimension.
However, according to investigations of the present inventors, the following problems are found in the above-described approach. The increases in the concentrations of Cu and sulfuric acid cause increased risks of a generation of particles due to a precipitation of copper sulfate and resultant device fault. In addition, since the plating suppressor and the leveler are decomposed in the use during the process, and therefore the effects of these agents disappear for the use in longer term. In order to prevent such problem, frequent replacement of the plating liquid is required, which leads to an increase in the production cost. Furthermore, this approach is to enhance the effect of the accelerator in the recessed section and is not related to alter the mechanism of the bottom up, and therefore the bottom up growth can not achieved in further finer dimension. More specifically, the bottom up growth is difficult to be achieved for semiconductor devices with progressed miniaturization, even if the improved plating liquid is presented, and causing problem of formation of a void in the Cu plated film.
Here, problem areas for of semiconductor devices having through silicon via (TSV) structure will be described in reference to FIG. 22 and FIGS. 23A and 23B. FIG. 22 shows a semiconductor device having a fine pattern with a conventional damascene structure, which includes an insulating film 52, which is formed over a substrate 10, which includes a transistor and a multiple-layered interconnect and the like formed on an element-formation surface of a semiconductor substrate 51. The insulating film 52 includes recessed sections 53 having apertures in the surface opposite to the side of the substrate 10. FIGS. 23A and 23B show a semiconductor device having the TSV structure, including a substrate 61, which is provided with a transistor, a multiple-layered interconnect layer, and an electrode pad and the like formed over an element-formation surface of the semiconductor substrate 51. The substrate 61 includes a recessed section 66 that extends through the multiple-layered interconnect layer to reach to the inside of the semiconductor substrate 51. An insulating film 62 is formed on the recessed section 66 and the substrate 61.
Since the TSV structure as shown in FIGS. 23A and 23B has larger pattern as compared with the fine pattern of the conventional damascene structures, the following problems are caused in the process for manufacturing the semiconductor devices.
First of all, as shown in FIG. 23A, the recessed section 66 having a diameter of about several tens micrometers (μm) and a height of tens to one hundred micrometers (μm) is formed over the substrate 61. Subsequently, as shown in FIG. 23B, a barrier metal 63 and a Cu film 64 serving as a seed are sequentially deposited over the substrate 61 and the recessed section 66. Then, the inside of recessed section 66 is filled with a Cu plated film 65 by means of a Cu plating deposition process by utilizing the Cu film 64 as a cathode electrode for the electrolytic plating process. Next, the sections of the barrier metal 63, the Cu film 64 and the Cu plated film 65 formed on the field of the substrate 61 are removed by means of a CMP process to present a configuration, in which the Cu plated film is remained only in the recessed section 66. In addition, the CMP process is further conducted until the Cu plated film in the recessed section 66 is exposed from the back surface of the substrate 61. This allows forming a through-hole electrode in the substrate 61.
The fill operation with the Cu plated film by employing the above-described plating deposition of Cu utilizes the bottom up growth similarly as in the process for finer pattern to fill with the Cu plated film 65, such fill process differs from the plating process for finer pattern, in terms of requiring larger amount of the plating deposition due to the larger pattern, which, in turn, requires a rapid deposition with a higher electric current for ensuring the sufficient production capacity. An attempt to increase the rate of the plating deposition requires an increase in the electric field intensity at the pattern aperture, causing the situation where the growth of the plated film around the aperture is faster than the increased speed of the bottom up, so that the aperture is blocked with the Cu plated film 65 deposited at the aperture. This causes the stop of the supply of the metallic ion to the recessed section from the plating liquid, which leads to the stop of the growth of the plated film or the plating deposition before the Cu plated film 65 deposited from the bottom surface reaches to the aperture, and the portion of the recessed section 66 without the deposition of the plated film remains to create a void, causing a problem of easily generating a defect in the process of the fill with the Cu plated film 65.
In order to solve the problem of generation the voids, technologies for carrying out the bottom up in the condition that the seed layer formed in the recessed section is partially remained only in the bottom of the recessed section, as described in Japanese Patent Laid-Open No. 2002-020,891 and Japanese Patent Laid-Open No. 2004-214,508.
Japanese Patent Laid-Open No. 2002-020,891 discloses a technology, which involves selectively removing a seed layer from an upper surface of a substrate to leave a portion of the seed layer only in at least a bottom surface of a feature (which is a representation described in Japanese Patent Laid-Open No. 2002-020,891 for indicating a trench), and then conducting an electrolytic plating process with a metal by utilizing a section of the seed layer to fill the feature with the metal. Japanese Patent Laid-Open No. 2004-214508 discloses a technology, which involves forming a metallic film on an electrically conducting layer that is remained over a bottom surface of an interconnect trench.
In addition to above, technologies related to electrolytic plating processes for semiconductor devices including conventional damascene structures are also disclosed in Japanese Patent Laid-Open No. 2007-149,824, Japanese Patent Laid-Open No. 2005-333,153, Japanese Patent Laid-Open No. 2001-144,181 and Japanese Patent Laid-Open No. 2002-118,109.
However, according to investigations of the present inventors, it was found that the following problems are present when technologies disclosed in the above-described Japanese Patent Laid-Open No. 2002-020,891 and Japanese Patent Laid-Open No. 2004-214,508 are applied.
The technologies described in the above-described Japanese Patent Laid-Open No. 2002-020,891 and Japanese Patent Laid-Open No. 2004-214,508 involve removing the portions of the seed film which was formed on the side walls of the recessed section by means of an electrolytic polishing process or a CMP process, in order to form the seed layer only on the bottom surface of the recessed section.
Thus, the Cu surface of the seed layer is possibly contaminated with a corrosion proof material employed in the CMP process or the like. In addition, sufficient removal of the seed layer from the side walls of the recessed section may not be achieved, or uniform removal may not be achieved.
Therefore, sufficient inhibition for the creation of voids may not be achieved.
Consequently, sufficient inhibition for voids generated during the electroplating fill cannot be achieved by employing the technologies described in the above-described Japanese Patent Laid-Open No. 2002-020,891 and Japanese Patent Laid-Open No. 2004-214,508.