This invention relates to a semiconductor integrated circuit having an interface circuit which connects an integrated injection logic (I.sup.2 L) circuit with a peripheral circuit driven by a high-voltage power source.
In general, an I.sup.2 L circuit is so designed that the collector-emitter breakdown voltage (base open) (hereinafter referred to as "output withstanding voltage") BV.sub.CEO of its output transistor is limited to increase the current amplification factor .beta. of the transistor. FIG. 1 shows an example of the relationship between the current amplification factor .beta. and output withstanding voltage BV.sub.CEO of the output transistor (transistor Q2 of FIG. 2 mentioned later) of the I.sup.2 L circuit. In FIG. 1, oblique lines represent the range of variations. For example, BV.sub.CEO is approximately 10 V if we have .beta.=10; approximately 2 V if .beta.=100. A conventional I.sup.2 L circuit is so designed that the output withstanding voltage BV.sub.CEO is 2 V and below. In this case, it is impossible to obtain an output signal with a great logical amplitude from the I.sup.2 L circuit.