1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a configuration and peripheral structure of a temperature monitor element for monitoring temperature of a power IC device.
2. Description of the Prior Art
Power MOSFETs that are easily driven are widely used for controlling electric power. As a result of progress and improvements in manufacturing process technology, power IC devices are commercially available which combine on the same chip a power MOSFET with a control circuit for controlling the power MOSFET. Typically, a power block and a control circuit adjoin each other on the chip.
To protect the control circuit from excessive temperatures reached by the power block, which cause malfunction and breakdown of the control circuit, the power IC device should be provided with a protective circuit. One solution has been to mount on the chip a temperature monitor element that feeds temperature information of the power block to the protective circuit. A temperature detector for detecting the temperature of the power MOSFET is disclosed in the Conference Record, IEEE Industrial Application Society Annual Meeting (1986), pp. 429-433. A self-thermal protecting power MOSFET is disclosed in the reprint from SP-737, Sensors and Actuators, 1988, pp. 41-46, with a polysilicon thermal sensing device on the same chip as the MOSFETs.
FIGS. 4a and 4b schematically show configuration and peripheral structure of a temperature monitor element in a prior-art power IC device, where FIG. 4a is a top plan view and FIG. 4b is a sectional view taken along line A--A in FIG. 4a.
FIG. 4a shows an entire planar chip configuration of the power IC device with semiconductor substrate 3. A temperature monitor element 8 is disposed in a control circuit block (IC block) 2, near the boundary between the control circuit block 2 and a power block (power MOSFET block) 1.
FIG. 4b shows an enlarged view of the boundary portion between the power MOSFET block 1 and the IC block 2. Reference numeral 4 designates a back gate region layer (channel region) of an end portion of the power MOSFET block formed on a silicon substrate 3. Reference numeral 5 designates a source region layer in the back gate region layer 4. Reference numeral 6 designates a gate electrode. Reference numeral 7 designates an electrode wiring (source electrode) connected to the source region layer 5 and the back gate region layer 4. Reference numeral 8 designates a temperature monitor element covered by an insulating layer 9 and insulated from the other layers. The temperature monitor element 8 is located in the IC block 2 adjoining the power MOSFET block 1 for monitoring the temperature of the MOSFET block 1.
In FIGS. 4a and 4b, the power MOSFET block 1 is formed as a vertical MOS. Alternatively, the power MOSFET block 1 may be formed as a planar MOS. A drain electrode of the vertical MOS is formed on a back surface of the silicon substrate 3, and a drain electrode of the planar MOS is formed on the same side of the silicon substrate on which the planar MOS is formed. Typically, the power MOSFET block 1 comprises many unit or cell structures arranged in a row each of which comprises the gate electrode 6 formed as a planar grid or a stripe, and the corresponding back gate region layer 4 formed as a polygonal island or a stripe.
If excessive electric power is supplied to the power MOSFET, e.g., when a short circuit occurs in a load of a main circuit, the power MOSFET generates excessive heat. Heat is conducted to the temperature monitor element 8 through the silicon substrate 3 and the insulation layer 9. Temperature information detected by the temperature monitor element 8 is then fed to the protective circuit. When the temperature exceeds a predetermined level, the protective circuit switches the power MOSFET off to protect the power IC device 2.
There is a temperature gradient between the power MOSFET block 1 and the temperature monitor element 8. Temperature at the temperature monitor element 8 is considerably lower than at the power MOSFET block 1 because the temperature monitor element 8 is located on a surface of the IC block that itself generates less heat. Also, an excessive-power condition in the MOSFET block 1 is detected by the temperature monitor element 8 with a considerable time lag due to the heat capacity of the substrate portion between the power MOSFET block 1 and the temperature monitor element 8, and due to the low thermal conductivity of the insulating layer 9. During this time lag, generated excessive heat can cause circuit breakdown.
The prior-art comparison structure of FIG. 3a shows silicon substrate 3, temperature monitor element 8, a back surface at 100.degree. C., and a power MOSFET heat-generative surface portion at 160.degree. C. As shown in FIG. 3b, left-most point, the temperature monitored by the temperature monitor element 8 is lower than the power block temperature by more than 25.degree. C. In case of an accident, e.g., a short circuit fault of the load, with the temperature of the heat generative portion rising by several hundred degrees, the monitored temperature is estimated to be lower by about 100.degree. C.