1. Field
Example embodiments of the present invention may relate to a programming method and a semiconductor memory device, and more particularly, to a method of programming a multi-level semiconductor memory device and a multi-level semiconductor memory device.
2. Description of the Related Art
A non-volatile memory device may electrically erase and program data, and may retain stored data even if power is not applied thereto. A representative non-volatile memory device is a flash memory device.
Each memory cell of a flash memory device includes a cell transistor having a control gate, a floating gate, and source and drain regions. The cell transistor programs and erases by a Fowler-Nordheim (F-N) tunneling.
An erase operation is performed by applying a ground voltage to the control gate of the cell transistor and a voltage higher than a supply voltage to a semiconductor substrate (or a bulk). Under the erase bias condition, a strong electric field is formed between the floating gate and the bulk due to a substantial voltage difference therebetween, and as a result, electrons in the floating gate are discharged to the bulk due to the F-N tunneling. A threshold voltage of the erased cell transistor has a negative value.
A program operation of the cell transistor is performed by applying a voltage higher than the supply voltage to the control gate and applying a ground voltage to the drain and bulk. Under the program bias condition, electrons are injected to the floating gate of the cell transistor by the F-N tunneling. A threshold voltage of the programmed cell transistor has a positive value.
Recently, in order to further improve the integration of a flash memory device, a multi-level flash memory device capable of storing a plurality of data in a single memory cell has been researched. In the multi-level flash memory device, multi-bits (at least two bits) may be stored in each memory cell. A memory cell storing multi-bits is called a multi-level cell. A memory cell storing a single bit is called a single-level cell. Since the multi-level cell stores multi-bits, the multi-level cell has two or more threshold voltage distributions and has two or more data storage states corresponding to the two or more threshold voltage distributions, respectively. Hereinafter, an example in which 2 bits of data are stored in a memory cell of a multi-level flash memory device will be described. However, it is also possible to store three or more bits of data in the memory cell of the multi-level flash memory.
A multi-level cell storing 2 bits may have four data storage states, that is, “11”, “01”, “10”, and “00”. For example, “11” may represent an erased state, and “01”, “10”, and “00” may represent programmed states.
The four data storage states respectively correspond to threshold voltage distributions of the multi-level cell. For example, if the threshold voltage distributions of the multi-level cell are respectively “VTH1-VTH2”, “VTH3-VTH4”, “VTH5-VTH6”, and “VTH7-VTH8”, the data storage states “11”, “0”, “10”, and “00” correspond to “VTH1-VTH2”, “VTH3-VTH4”, “VTH5-VTH6”, and “VTH7-VTH8”, respectively. That is, if a threshold voltage of the multi-level cell corresponds to one of the four threshold voltage distributions, 2 bits of data corresponding to the threshold voltage among “11”, “01”, “10”, and “00” are stored in the multi-level cell.
Meanwhile, when two or more bits of data are stored in the multi-level cell, generally, the two or more bits of data are sequentially stored for each bit in the multi-level cell. In this case, when a bit (for example, a second bit) following a first bit of the data is stored in the multi-level cell, a data storage state of the second bit that is to be written is determined with reference to a data storage state of the first bit. In order to determine the data storage state of the first bit, which has been previously written, the data storage state of the first bit has to be read from the multi-level cell. However, if the data storage state of the second bit is read from the memory cell during a data write operation, a data write speed slows down.