The present application relates to semiconductor structures and methods of forming the same. More particularly, the present application relates to methods of forming a semiconductor structure having a source contact and a drain contact that exhibit reduced contact resistance.
As silicon complementary metal oxide semiconductor (CMOS) technology reaches it fundamental scaling limits, alternative materials such as, for example, high mobility III-V compound semiconductors and silicon germanium alloys have proven to be strong candidates for extending high performance logic.
In germanium containing devices, the Fermi level pins close to the valence band so most metals form negative barriers to p-type germanium, making ohmic contact formation extremely simple because there is no barrier for the majority contacts. However, ohmic contacts for n-type germanium is complicating since the barrier height is large.
For application of high mobility metal oxide semiconductor field effect transistors (MOSFETs), the source contacts and drain contacts (herein after collectively referred to as S/D contacts) require a near zero barrier height for minimal contact resistance. As such, the strong metal/semiconductor Fermi level pinning needs to be reduced.
Traditionally, metal/semiconductor layers are used to make S/D contacts. This significantly impacts performance on a silicon germanium alloy nMOS since with advanced devices the mobility is limited by the nFET contact. Specifically, direct metal contact to a silicon germanium alloy on an nMOS seriously limits current integrated circuits from a resistance perspective. Hence, there exists a need to solve the direct metal/n-silicon germanium alloy problem to ensure continuous scaling.