The present invention relates to a composite semiconductor device provided with a complementary insulated gate field effect transistor (C.MOSFET) and a bipolar transistor at input and output sides respectively, and particularly relates to such a composite semiconductor device having a structure suitable to make the production easy and to make the performance high.
FIG. 1 shows a conventional composite semiconductor device 2 in which a C.MOSFET and a bipolar transistor are formed on one and the same semiconductor substrate, as disclosed in Japanese Patent Unexamined Publication No. 57-183067.
In the composite semiconductor device 2, an n.sup.- layer 12 is formed by crystal growth on an n.sup.+ layer 11, a p layer 21 is formed in the n.sup.- layer 12, n layers 31 and 32 are formed in each p layer 21 isolated from each other, and p layers 41 are further formed in the n layer 31.
As is apparent, in one unit of the device, an n-type channel MOSFET Tr4 is formed of the n.sup.- layer 12, p layer 21 and n layer 32 and a p-type channel MOSFET Tr3 is formed of the p layer 21, the n layer 31 and the p layer 41. Respective MOS gate electrodes 54 and 56 of the MOSFET Tr4 and the MOSFET Tr3 are shorted to form a C. MOSFET.
The n layer 31 and the p layer 41 are shorted through an emitter electrode 52, and a collector electrode 51 is in low ohmic contact with the n.sup.+ layer 11. The n layer 32 and the p layer 21 are shorted through an electrode 53.
An equivalent circuit of the composite semiconductor device 2 of FIG. 1 is shown in FIG. 2.
Thus, as illustrated in FIG. 1, a current of electrons .crclbar. flowing in the MOSFET Tr4 upon application of a positive potential to a gate G is converted into a current of holes .sym. which is effective as a base current .sym. of an npn transistor Tr1 formed of the n layer 31, p layer 21 and n layer 12. By the base current, electrons .crclbar. are injected from the n layer 31 into the n.sup.- layer 12 to thereby turn on the composite semiconductor device 2.
On the other hand, if negative potential is applied to the gate G, the MOSFET Tr4 is turned off and the base current is cut off so that the injection of electrons .crclbar. from the n layer 31 is stopped. At the same time, the MOSFET Tr3 is turned on so that excess carriers stored in the p layer 21 and the n.sup.- layer 12 can be rapidly collected to the emitter electrode 52 through the MOSFET Tr3. Accordingly, the composite semiconductor device 2 can be turned off at a high speed.
Such a composite semiconductor device has features in that the power consumption at the gate is low because of the use of a MOS gate, while it has a capacity of higher power than a mere MOSFET because of the use of a bipolar transistor Tr1, and further high speed switching can be performed.
In such a conventional composite semiconductor device as described above, however, it is essential to provide a pnpn four-layer structure constituted by the n.sup.- layer 12, p layer 21, n layer 31 and p layer 41.
In forming these layers by diffusion from the emitter electrode E side, it is necessary to make the carrier concentration higher in an upper layer than a lower layer in order to assure a higher current-amplification factor of the transistor Tr1 resulting in that it is very physically difficult to make the uppermost p layer 41 having high concentration. There is a further problem that if the concentration of the n layer 31 is made higher, the threshold voltage of the MOSFET Tr3 becomes extremely higher.
Other than the method by diffusion, there is a method in which the layers are formed by crystal growth. The method by crystal growth has a problem that the process in production is extremely complicated.
Further, the composite semiconductor device 2 of FIG. 1 has another problem in that the current of the device when the device is turned on is determined by the base current flowing into the npn transistor Tr1, and therefore the current of the composite semiconductor device 2 is restricted by an on-resistance R (FIG. 1) of the MOSFET Tr4 so that it is difficult to provide an electric power capacity as high as that in a unit bipolar transistor.
Furthermore, as apparent from FIG. 1, the composite semiconductor device has a vertically formed pnpn thyristor structure and therefore there is a possibility of latch-up (turn-on) of the device. Thus, inconveniently, the gate becomes uncontrollable if the device is once latched up.