1. Field
The present disclosure relates generally to electronic circuits, and more particularly, to integrated circuits that are tolerant to process variations.
2. Background
Integrated circuits have revolutionized the electronic industry by enabling complex circuits consisting of millions of transistors, diodes, resistors and capacitors to be integrated into a chip of semiconductor material. Integration also provides other benefits such as batch manufacturing. The simultaneous manufacture of hundreds or even thousands of integrated circuits onto a single semiconductor wafer reduces cost and increases reliability of the end products.
Despite the manufacturing benefits of integrated circuits, process variations during the manufacturing process can have an impact on the electrical parameters of the chips, thereby leading to variations in performance. The nature of these process variations will be illustrated with reference to FIG. 1. FIG. 1 is a two-dimensional graph that is typically used to show the distribution of chip parameters for CMOS technology. Statistically, most of the CMOS chips will have electrical parameters that meet the nominal specifications. These CMOS chips will be plotted around the center 102 of the graph. A number of CMOS chips, however, will deviate from the nominal case towards the process corners. Referring to FIG. 1, each process corner is represented by a two-letter designation. The first letter refers to the NMOS transistors and the second letter refers to the PMOS transistors, and each letter has either an F designation for fast or an S designation for slow. The CMOS chips with both types of transistors being slow or fast will be plotted around the slow corner (SS) 104 or fast corner (FF) 106 respectively. There may also be CMOS chips that are plotted around cross corners where one type of transistor is faster and the other type of transistor is slower. By way of example, CMOS chips with slow NMOS transistors and fast PMOS transistors may be plotted around the slow-fast (SF) corner 108. CMOS chips with fast NMOS transistors and slow PMOS transistors may be plotted around the fast-slow (FS) corner 110. Preferably, all the CMOS chips manufactured on the semiconductor wafer can be plotted within the boundaries spanning the process corners. The performance of the CMOS chips that reside outside these boundaries cannot be guaranteed to operate properly under worst case conditions.
Memory is a common circuit implemented within an integrated circuit. A static random access memory (SRAM) is just one example. The SRAM is memory that requires power to retain data. Unlike dynamic random access memory (DRAM), the SRAM does not need to be periodically refreshed. The SRAM also provides faster access to data than DRAM making it an attractive choice for many integrated circuit applications. Unfortunately, chips operating at the SF corner tend to have difficulty writing to SRAM during normal operation.
The difficulty certain integrated circuits experience when operating at a process corner is of major concern to manufacturers. These concerns are not limited to the operation of SRAMs. Accordingly, there is a need in the art for circuits that are tolerant to process variations.