1. Field of the Invention
The present invention relates to a structure of a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a semiconductor device capable of suppressing disconnection of two conductors caused by a shift of superposition to obtain a capacitor having excellent electrical characteristics, and a method for manufacturing the same.
2. Description of the Background Art
FIG. 14 is a sectional view showing a structure of a semiconductor device according to the art described in Japanese Unexamined Patent Publication No. 81-306664. In FIG. 14, the reference numeral 101 denotes a semiconductor substrate, the reference numeral 102 denotes an insulation film provided on the semiconductor substrate 101, and the reference numeral 103 denotes a contact buried in the insulation film 102 with a bottom face thereof abutting on a surface of the semiconductor substrate 101. The contact 103 includes a first contact layer 104 bonded to an internal wall and a bottom face of a contact hole formed on the insulation film 102, and a plug 105 provided on the first contact layer 104 and buried in the contact hole.
Furthermore, an upper wiring 107 is formed on the contact 103 through a second contact layer 106. A protective film 108 formed of an insulating material is provided on an upper face of the upper wiring 107. A sidewall 109 formed of an insulation film is provided on side sections of the upper wiring 107 and the protective film 108. The second contact layer 106 is provided on lower faces of the sidewall 109 and the upper wiring 107.
FIGS. 15 to 18 are sectional views sequentially showing a method for manufacturing the semiconductor device shown in FIG. 14. As shown in FIG. 15, a contact hole is first formed on an insulation film 102 provided on a semiconductor substrate 101. A first contact layer 104 is provided on at least an internal wall and a bottom face of the contact hole, and a conductive film acting as a plug 105 is formed. Thus, the contact hole is filled with a conductive material. Then, a whole face is subjected to etch-back to remove the plug 105 and the first contact layer 104 which are provided on the insulation film 102. Consequently, the first contact layer 104 and the plug 105 remain only in the contact hole. Thus, a contact 103 is formed.
Thereafter, a second contact layer 106a, a conductive film 107a acting as an upper wiring 107, and a protective film 108a are sequentially provided on the contact 103 and the insulation film 102 as shown in FIG. 16.
Next, a resist pattern 110 having a width which is almost equal to a diameter of the contact 103 is formed on the protective film 108a provided above the contact 103 as shown in FIG. 17. The protective film 108a and the conductive film 107a are sequentially subjected to anisotropic etching by using the resist pattern 110 as an etching mask. Consequently, a protective film 108 and the upper wiring 107 are obtained. At this time, a shift of superposition causes a shift in a region indicated at W so that a contact area of the contact 103 and the upper wiring 107 is reduced. After this processing, the resist pattern 110 is removed.
Then, a silicon oxide film is provided on exposed faces of the second contact layer 106a, the protective film 108 and the upper wiring 107 by a CVD method as shown in FIG. 18. Thereafter, anisotropic etching is performed to form a sidewall 109 comprising an insulation film on side sections of the protective film 108 and the upper wiring 107. Subsequently, the second contact layer 106a is subjected to etching by using the sidewall 109 and the protective film 108 as etching masks. Consequently, a second contact layer 106 remains on lower faces of the sidewall 109 and the upper wiring 107. Thus, the semiconductor device shown in FIG. 14 is obtained.
In the semiconductor device thus formed which is shown in FIG. 14, the contact 103 and the upper wiring 107 cause the shift (W) of superposition. However, the second contact layer 106 provided on the lower face of the upper wiring 107 also extends over the lower face of the sidewall 109. Therefore, it is possible to solve a problem that the first contact layer 104 forming the contact 103 is subjected to over-etching when performing etching for patterning the upper wiring 107.
However, a bad influence of the shift of superposition has given much more weight with finer structures of elements such as a contact, a wiring and the like. For example, in the case where the contact 103 and the upper wiring 107 cause the shift (W) of superposition and they are not superposed at all as shown in FIG. 19, electrical connection can be obtained only through an end of the second contact layer 106 provided between the contact 103 and the upper wiring 107. Although disconnection is not caused, a resistance is increased because a thickness of the second contact layer 106 is small. Therefore, excellent electrical characteristics cannot be obtained.