FIG. 1 shows a depiction of a FinFET. A FinFET is a transistor built around a thin strip 102 of semiconductor material (referred to as the “fin”). Referring to the depiction of FIG. 1, the transistor includes the standard field effect transistor (FET) nodes: 1) a gate 104; 2) a gate dielectric 103; 3) a source region 102a; and, 4) a drain region 102b. For simplicity the drain and source contacts are not depicted so that the current transport properties of the device can be more easily described in reference to the drawing observed in FIG. 1.
The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric 103. Specifically, current runs in the + or −z direction along both “sidewalls” of the fin 102 that lie in the yz plane as well as along the top side of the fin 102 that lies in the xz plane. Because the conductive channel essentially resides along the three different outer, planar regions of the fin 102, the particular FinFET of FIG. 1 is typically referred to as a “tri-gate” FinFET. Other types of FinFETs exist (such as “double-gate” FinFETs in which the conductive channel principally resides only along both sidewalls of the fin 102 and not along the top side of the fin 102).
Although different types of FinFETs exist they all share the challenge of building a fin structure. Prior art approaches have traditionally used lithography techniques to form the fin 102. Prior to formation of the gate dielectric 103 and gate structures 104, the surface of a semiconductor substrate 100 is typically deposited with layers of materials, such as silicon nitride on pad oxide, as hardmask for patterning the fin 102. The surface of the hardmask is then coated with a layer of photoresist. The photoresist is subsequently patterned (i.e., electromagnetic radiation is propagated to a mask and then to the photoresist). The photoresist is then removed in certain areas so as to expose regions of the hardmask surface surrounding the region where the fin is to be formed while covering (and therefore protecting) the region of the hardmask surface beneath which the fin is to be formed. Etching of the exposed regions, and subsequent removal of the hardmask materials, 101a, 101b results in the formation of the fin 102.
A problem with the lithographic approach to fin formation, however, is that the sidewalls of the fin may be ill-defined owing to “edge-roughness” or “line-width” issues in the patterning of the photoresist. That is, if the edges of the photoresist used to define the fin 102 within the substrate are “rough”, then, the sidewall surfaces of the fin will also be “rough” as a direct consequence of the resist and subsequent etch process. The sidewall roughness on both sidewalls and to some extent the sidewall profile cause fin thickness variation (measured along the x axis) which may adversely affect the performance and/or operation of a FinFET.