This invention relates to a data transfer apparatus, and more particularly to an apparatus for performing the transfer of a data group continuously placed on the memory without depending on the direct operation of the CPU, or a so-called DMA (direct memory access) controller.
Generally, in data transfer between processors in a multiprocessor system not sharing a bus, or in data transfer to a device on a bus operating asynchronously, a DMA controller is usually employed. In the data transfer using a DMA controller, the task relating to the generation of the transfer data is completed in the processor, and all transfer data are generated. In the next step, the DMA controller is started by an instruction from the transfer destination (usually the processor), and the DMA transfer is effected according to the request from the transfer destination.
That is, until all transfer data are generated, the data will not be effectively utilized in the next task. Accordingly, in order to improve the efficiency of the next task by transferring the data at high speed, it is useful and thus effective to transfer part of the data being generated even in the midst of the task which is processed at the processor.
Such examples are high speed pipelined processing between processors in the multiprocessor system, or data exchange between processors in the processor array.
In such cases it is difficult to apply the conventional DMA controller directly.
Supposing that, for example, data A(l) to A(n), where n is greater than l, are processed on a task A in a certain processor to generate new data A(l) to A(n), which are used on a proceeding task B in another processing system (for example, another processor). At a time before said task A is over, the new data A(l) to A(k), where k is more than l, have been sequentially processed on the task A. Then, if it is attempted to transfer the new data A(l) to A(k) by using the DMA controller, it is difficult to distinguish the range in which the data has been renewed, that is, the address range of the memory in which the data can be used on the next task.
Accordingly, in general, there were two conventional methods used mainly as a means of generating data to a device operating asynchronously and setting in a transferrable state at the same time.
The first method is to dispose an FIFO (first-in first-out) memory between the device at the transfer destination and the bus, and transfer the data through it. In this case, the processor stores in both the memory and the FIFO memory.
In the second method, a special control circuit (a hardware semaphore) containing registers is provided between the processor and the DMA controller. The control circuit and the processor rewrites the values in the registers when transferring data, and the control circuit starts and stops the DMA controller in accordance with the value in the register. However, in the first method, it is necessary to prepare an FIFO memory of a capacity corresponding to the transfer data quantity. In the second method, it is necessary to add complicated hardware to control the memory access of the processor and the DMA controller. In general, these conventional data transfer apparatus were not necessarily compact and functional.