The present invention relates to phase-locked loops in general and more particularly to a digital phase-locked loop (DPLL).
The conventional digital phase-locked loop has a digital oscillator which generates an output signal of period T, representing the actual phase of the digital oscillator. By increasing a register word of length N successively at a predetermined clock rate of a clock generator according to a control word applied to a control input of the digital oscillator, the oscillator is caused to periodically overflow. A processor device, which is supplied with the digital oscillator output signal, adjusts the period T of the digital oscillator to a nominal period. The nominal period is determined by periodically occurring synchronizing pulses. The processor device performs a phase comparison between the actual phase of the digital oscillator and a reference phase, so that the processor device can form a phase-difference signal from the actual phase of the digital oscillator and the reference phase. This is done at a first control clock rate, which is determined by the periodically occurring synchronizing pulses. The phase-difference signal is filtered via a loop filter of the processor device, whereby, the filtered phase-differential signal is added to a frequency word whose numerical value represents the nominal period as a function of the length N of the register word (of the digital oscillator) and the predetermined clock rate (of the clock generator). During successive accumulation of the register word by the frequency word, the digital oscillator overflows in the nominal period. The control word formed from the frequency word and the phase-difference signal is then applied to the input of the digital oscillator to control the same.
Such a digital phase-locked loop (DPLL) is known in the art. It is used particularly in the horizontal deflection circuit of a television receiver to generate the horizontal frequency. For example, see U.S. Pat. No. 4,330,791, entitled "System for Processing Television Video Signals Reproduced from a Recording Medium in Special Reproduction Mode into Signals for Performing Normal Interlacing", which issued to T. Ohara, et al. on May 18, 1982 and U.S. Pat. No. 4,689,664, entitled "Circuit Arrangement for Deriving Digital Color Signals from an Analog Television Signal", which issued to W. Moring, et al. on Aug. 25, 1987. See also the European Patent Application Publication Nos. 0 62 541, 0 239 412 and 0 239 413.
In a television receiver the frequency or period of the digital oscillator must be adjusted to a nominal frequency or nominal period, respectively, which is determined by the line-periodic synchronizing pulses identifying the beginning of each line of the television picture. These line-periodic synchronizing pulses are separated from the luminance signal of the composite color signal in a sync separator which is connected ahead of the digital phase-locked loop, and then passed to a comparator in the sync separator. The comparator triggers the processor device of the digital phase-locked loop on the trailing edge of the synchronizing pulses. At this instant of triggering, the content of the register word of the digital oscillator is stored as the actual phase of the digital oscillator. The comparison between the actual phase of the digital oscillator and the reference phase, as well as the tracking of the period of the digital oscillator, is then controlled as described above. Thus, the processor device adjusts the period T of the digital oscillator to the nominal period of the line-periodic synchronizing pulses at the control clock rate, as determined by the time sequence of the line-periodic synchronizing pulses. The result is that a single adjustment is performed per line of a television picture.
Conventional digital phase-locked loops have the disadvantage of becoming unstable if the time sequence of the line-periodic synchronizing pulses is interrupted. An example of one type of interruption is due to non-line-periodic synchronizing pulses shifted by one-half line, i.e., by 180.degree., with respect to the line-periodic synchronizing pulses. This one-half line shifting is caused by the standard pre- and post-equalizing pulses that occur during reproduction of every last line of a first field and every first line of a second field of an interlaced television picture. Similarly, a half-line displacement of a synchronizing pulse occurs in certain modes of a video recorder, e.g., in the search mode. That is, the locking of the digital oscillator to the horizontal frequency is disturbed by the non-line-periodic synchronizing pulses. Since in conventional digital phase-locked loops all synchronizing pulses applied to the DPLL, including the non-line-periodic pulses, initiate the phase adjustment a sync problem arises. The processor device, designed to operate with a line-periodic clock signal, is unable to distinguish the non-line-periodic synchronizing pulses from the line-periodic pulses and, therefore, unnecessarily readjusts the digital oscillator. This unnecessary readjustment adversely affects the stability of the DPLL when locking the digital oscillator to the nominal period, since the digital phase-locked loop must readjust the digital oscillator to the nominal period after each non-line-periodic synchronizing pulse has entered into the phase control.
Besides influencing the horizontal deflection unit of a television receiver, the non-line-periodic synchronizing pulses also influence the video-signal-processing operations which take place at the horizontal rate. This is because the phase of the digital oscillator is used as the address phase for controlling the time sequence of these operations. The address phase assigned to a particular video-signal-processing operation determines the instant at which this operation has to be performed within each line of the television picture. To achieve exact synchronization of these timing marks with the video signal, the digital-oscillator is phase locked to the line-periodic synchronizing pulses and used to control the video signal processing. The consequence of a non-line-periodic synchronizing pulse is that the subsequent video signal (luminance signal and chrominance signal) of the line is shifted by 180.degree. with respect to the preceding line. Therefore, in order to correct the address of the horizontal-frequency, video-signal-processing operations, a corresponding correction of the address phase is required, i.e., the phase must be shifted by 180.degree. with respect to the phase of the digital oscillator.
It is apparent from the foregoing that with conventional phase-locked loops, the problem is one of stability. That is the phases of the digital oscillator are not to be influenced when the non-line-periodic synchronizing pulses shift by 180.degree., and further the correct addressing of the horizontal-frequency, video-signal-processing operations requires that non-line-periodic synchronizing pulses do not disturb the phase of the digital oscillator to enable correct timing control of the video processing.