In the field of electrical systems, a signal having a desired pulse width is frequently the input signal of other circuits of the electrical system.
FIG. 1 is a circuit diagram of a conventional pulse generator. In FIG. 1, the conventional pulse generator consists of a delay element 66; inverters 67, 69, 71; and NAND gates 68, 70, 72. The delay element 66 is reset in response to a reset signal RESET.sub.--, and outputs a delay signal DWL. The inverter 67 inverts an output signal of the delay element 66 and outputs a signal TOR.sub.--. The inverter 69 inverts and outputs a write enable signal WE. The inverter 71 delays an output signal of the delay element 66 and outputs a signal TOW.sub.--. NAND gate 68 performs a NAND-operation of the signal TOR.sub.--, a signal DWL, and an output signal of the inverter 69 and outputs a NAND-operated signal. NAND gate 70 performs a NAND operation of the write enable signal WE, a signal TO, and the signal TOW.sub.--, and outputs its NAND-operated signal. NAND gate 72 performs a NAND operation of the output signals of NAND gates 68, 70, and a signal SETPLS and outputs an output signal PULSE.
FIG. 2 is a detailed circuit diagram of the delay element 66 shown in FIG. 1. In FIG. 2, the delay element 66 consists of a NAND gate 80, an inverter 81, and a capacitor 82. NAND gate 80 performs a NAND operation of two input signals and outputs a NAND-operated signal. Capacitor 82 is connected between an output terminal of NAND gate 80 and a ground. Inverter 81 inverts an output signal of NAND gate 80 and outputs the inverted signal.
FIGS. 3A-G illustrate an operational timing diagram for explaining an operation of the conventional pulse generator shown in FIG. 1. The operation of the pulse generator will be explained in reference to a read mode and a write mode. The read mode and write mode are controlled by the write enable signal WE as shown in FIG. 3E. The pulse generator is operated during the write mode when the write enable signal WE is a "high" level. In contrast, during the read mode, the write enable signal is a "low" level.
When the write enable signal WE is a "low" level (the read mode), and if a reset signal RESET.sub.-- transmits from the "low" level to the "high" level as shown in FIG. 3A, the delay element 66 can be operated. At this time, if the signal TO of a "high" level is provided as input as shown in FIG. 3B, the inverter 67 inverts the signal delayed by the delay element 66 and outputs a signal TOR.sub.-- of a "low" level as shown in FIG. 3D. The inverter 71 inverts the signal delayed by the delay element 66 and outputs the signal TOW.sub.-- of a "low" level as shown in FIG. 3F. The NAND gate 70 performs a NAND operation of the signal TO of a "high" level, the write enable signal WE of a "low" level, and the signal TOW.sub.-- of a "low" level, and outputs a signal of a "high" level. The NAND gate 68 outputs a signal of a "high" level because the write enable signal WE is a "low" level. Accordingly, NAND gate 72 outputs an output signal PULSE of a "high" level as shown in FIG. 3G, regardless of the state of a signal SETPLS. The NAND gate 70 performs a NAND operation of the signal TO, the write enable signal WE, and the signal TOW.sub.-- of a "low" level, and outputs a signal of a "high" level. The NAND gate 72 performs a NAND operation of the output signals of the NAND gates 68, 70, and the signal SETPLS of a "high" level, and drives the output signal PULSE to a "low" level. By performing the above operation, the pulse generator can generate a pulse having a short pulse length in the read mode.
When the write enable signal WE is a "high" level of the write mode, and the reset signal RESET.sub.-- transits from a "low" level to a "high" level as shown in FIG. 3A, the delay element 66 delays the signal DWL for a predetermined time period and outputs the delayed signal as shown in FIG. 3C. The inverter 71 inverts the signal delayed by the delayed element 66 and outputs a signal TOW.sub.-- as shown in FIG. 3F. The NAND gate 70 performs a NAND operation of the signal TO, the write enable signal, and the signal TOW.sub.-- of a "high" level and outputs a signal of a "low" level. The NAND gate 68 outputs a signal of a "high" level while the output signal of the inverter 69 maintains a "low" level. The NAND gate 72 performs a NAND operation of the output signal of NAND gate 68 of a "high" level and the output signal of the NAND gate 70 of a "low" level, and a signal SETPLS and outputs the output signal PULSE of a "high" level as shown in FIG. 3G. By performing the above operation, the pulse generator can generate a pulse having a long pulse length in the write mode.
Conventional logic circuit design techniques contemplate increasing the throughput of a system with a "pipeline." The pipeline has a number of logic sections, each separated by a register section. Each system clock transition allows a signal to propagate from one register section, through the following logic section, and to the inputs of the following register section. Typically, new signal inputs are not fed into a logic section until the previous signal outputs are latched into the register section following that logic section. The maximum clock frequency for a logic section (i.e., the frequency with which new data can be switched into a logic section) is limited by the maximum propagation delay of a path through that logic section.
One way to increase system throughput is to break up logic sections into smaller sections (each with a shorter propagation delay) and insert pipeline register-section levels to separate the smaller logic sections. The clock speed can then be increased to take advantage of the shorter logic-section delays.
This "pipelining" technique has been used to obtain significant speed-up of a computer system. FIG. 4A illustrates conventional pipelining, showing the edges of signals propagating though small combinational-logic blocks. Conventionally, a combinational-logical-function unit is partitioned into several smaller combinational-logic blocks, and register stages are inserted between adjacent combinational-logic blocks as the synchronizers. The inserted register stages contribute to increased physical area and added clock-distribution requirements, however, and limit performance.
The increasing demand for high-speed, compact devices and systems, and the limitations of existing design methods, have prompted researchers to look for alternate techniques that can lead to high-performance digital systems. One such method is called "wave pipelining." Wave pipelining eliminates intermediate register stages in a pipeline system by using the internal capacitance of a combinational block for storage. Wave pipelined systems have strict requirements, however, on (a) the uniformity of path delays, (b) the uniformity of output-signal rise and fall times, and (c) the independence of delay from the pattern of input signal transitions.
FIG. 4B shows one embodiment of a conventional wave pipelining technique. In FIG. 4B, the internal capacitances in the combinational logic act in effect as temporary storage elements. These dynamic storage elements take the place of static registers used in the conventional pipelining method shown in FIG. 4A. Under the approach shown in FIG. 4B, new data values are latched in before the previous data values propagate to the next set of registers. In this way, there are multiple coherent data "waves" within the combinational-logic block. Hence, the system clock is much faster than the propagation delay of the combinational-logic block between adjacent system-clocked-register stages.
The significant advantages of wave pipelining are: (1) achieving very high pipeline rates that approach the physical speed limit of the technology, (2) increasing pipeline rate without significant latency increase, (3) minimizing clock loading and reducing clock-distribution problems, and (4) using fewer registers and reducing the area overhead otherwise required by conventional pipelining.
To obtain a high operating speed, each path through a given functional block must have similar path delays. This requires symmetric rise and fall times (collectively called "transition" times) of output signals and, for each component within the logical-functional block, delays that are independent of the input-signal transition patterns. Wave pipelined systems are susceptible to process and environmental variations which cause propagation-delay-variation problems.
Conventional delay circuits have a tendency to distort an original waveform and stretch or shrink the duty cycle so that the pulse ultimately vanishes. In other words, a pulse is broadened or narrowed, such that the time between a rising edge and a succeeding falling edge is increased or decreased. FIG. 5 shows each stage in a traditional wave pipe having increasing trailing edge uncertainty. Conventionally, each stage distorts the waveform slightly and a long, serial chain of delays causes significant distortion, especially with respect to the trailing edge. Moreover, conventional delay circuits do not offer a programmable pulse width adjustment.
Although the art of pulse generators is well developed, there remain some problems inherent in this technology. One particular problem is the distortion of a waveform by the delay circuit. Therefore, a need exists for a variable delay circuit for the internal clock of the chip that is easily adjustable.