1. Field of the Invention
The present invention relates generally to a circuit layout structure, more particularly, to a circuit layout structure that is able to reduce undesired capacitance charging effect.
2. Description of the Prior Art
In the semiconductor manufacturing process, the semiconductor devices, such as the transistors, are formed by multilayer process and electrically connected by wirings, which are done through multilayer metallization on top of the multilayered semiconductor devices. And during those multilayer processes, photolithography and etching processes are conventionally employed to construct the predetermined pattern in a certain layer.
Please refer to FIGS. 1-2, which are schematic drawings illustrating the conventional steps for forming a pre-determined pattern in a certain layer in the prior art. As shown in FIG. 1, a wafer 100 is provided, the wafer 100 includes a silicon substrate 110 having multilayered semiconductor devices (not shown) constructed therein. An interlayer dielectric (ILD) layer 120 is formed on the silicon substrate 110 and at least a metal contact plug 122 is formed in the ILD layer 120. It is noteworthy that during forming the metal contact plug 122, alignment marks and advanced imaging metrology (AIM) overlay marks are always needed to ensure the contact plug pattern (not shown) match up the feature designed in the lower layer, and thus the contact plug 122 formed later is able to provide interconnection successfully and satisfactorily. Therefore, a conductive alignment mark or an AIM mark 124 is left in the ILD layer 120 in a scribe line region 114, while the contact plug 122 is formed in a cell region 112.
Please refer to FIG. 1 again. Then, an inter-metal dielectric (IMD) layer 130 is disposed on and covers the contact plug 122, the conductive alignment/AIM mark 124 and the ILD layer 120. In the prior art, the IMD layer 130 can include silicon oxynitride, tetraethoxysilane-based oxide (TEOS) and/or a low-k material . . . etc. Next, a patterned hard mask 140 is formed on the IMD layer 130. The patterned hard mask 140 comprises predetermined patterns 142, such as trench patterns. Conventionally, the patterned hard mask 140 can be a metal hard mask includes titanium nitride (TiN).
Please refer to FIG. 2. Next, a suitable etchant 150 under a plasma circumstance is used to etch the underlying IMD layer 130 to transfer the predetermined pattern 142 into the IMD layer 130. Thus trench openings 132 for defining metal wires are formed and the contact plug 122 is exposed in bottom of the trench openings 132. However, it is found that not all of the trench openings 132 may successfully expose the contact plug 122 in the ILD layer 120 as expected, as shown in FIG. 2. One reason for this undesired etching result is that since the ILD layer 130, which includes dielectric material, is positioned between the two conductive elements: the conductive alignment/AIM marks 124 and the metal hard mask 140, an adverse capacitance is always generated between the metal hard mask 140 and the conductive alignment/AIM mark 124 in the scribe line region 114 during the etching step. As a result, the capacitance attracts more charged etching residues 152 to accumulate in the trench openings 132 in the cell region 112 and to block the sidewalls and the bottom of the trench openings 142, so that the result of etching the ILD layer 130 cannot be completed as desired. Accordingly, effective electrical interconnection is not constructed.
Therefore, a novel circuit layout structure is still in need to improve the yield of the etching step, in particular to avoid the accumulation of the etching residues in the predetermined openings and the failure to expose the underlying designed features.