1. Field of the Invention
The present invention relates to semiconductor packages, and more particularly, to a semiconductor package having embedded semiconductor elements and a fabrication method of the semiconductor package that can prevent displacement of the semiconductor elements during a die attachment process.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high electrical performance. Accordingly, wafer level packaging (WLP) technologies have been developed to meet the miniaturization requirement of semiconductor packages.
FIGS. 1A to 1D are schematic cross-sectional views illustrating a fabrication method of a wafer level semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a thermal release tape 11 is formed on a carrier 10.
A plurality of semiconductor elements 12 are disposed on the thermal release tape 11. Each of the semiconductor elements 12 has an active surface 12a with a plurality of electrode pads 120 and an inactive surface 12b opposite to the active surface 12a. The semiconductor elements 12 are attached to the thermal release tape 11 via the active surfaces 12a thereof.
Referring to FIG. 1B, an encapsulant 13 is formed on the thermal release tape 11 by molding so as to encapsulate the semiconductor elements 12.
Referring to FIG. 1C, a curing process is performed to cure the encapsulant 13. During the process, the thermal release tape 100 is heated and loses its adhesive property. As such, the thermal release tape 11 and the carrier 10 can be removed to expose the active surfaces 12a of the semiconductor elements 12.
Referring to FIG. 1D, a RDL (Redistribution Layer) process is performed to form a RDL structure 14 on the encapsulant 13 and the active surfaces 12a of the semiconductor elements 12. The RDL structure 14 is electrically connected to the electrode pads 120 of the semiconductor elements 12.
Then, an insulating layer 15 is formed on the RDL structure 14, and portions of the RDL structure 14 are exposed from the insulating layer 15 so as for conductive elements 16 such as solder balls to be mounted thereon.
However, the thermal release tape 11 is flexible and easily expands when being heated. Therefore, a positional deviation easily occurs to the semiconductor elements 12 due to expansion of the thermal release tape when being heated along with impact of the mold flow during the molding process. That is, the semiconductor elements 12 deviate from die areas B on the thermal release tape 11, as shown in FIG. 1D′. Further, after the carrier 10 is removed, warpage easily occurs to the encapsulant 13. Therefore, it becomes difficult for the RDL structure 14 to be aligned with the electrode pads 120 of the semiconductor elements 12. The larger the size of the carrier 10, the bigger the position error between the semiconductor elements 12 is, thereby adversely affecting the electrical connection between the RDL structure 14 and the electrode pads 120. As such, the product reliability and yield are reduced.
Further, the use of the thermal release tape 11 incurs a high fabrication cost.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described disadvantages.