1. Field of the Invention
The present invention relates to an active matrix liquid crystal display (AMLCD) and more particularly to an AMLCD including a thin film transistor (TFT) and a pixel electrode, which is connected to the TFT, and a method of manufacturing the same wherein the number of processing steps is reduced.
2. Description of the Background Art
Among display devices, cathode ray tubes (CRTs) have been widely used to display picture images. However, cathode ray tubes are being replaced with thin film type flat panel display devices because flat panel display devices are relatively thin and light weight. Also the response time, and therefore the quality, with which the moving pictures are displayed by flat panel display devices is as fast as cathode ray tubes. Thin film type flat panel displays are actively being developed and studied.
The operational principle of the AMLCD uses optical anisotropy and polarization characteristics of liquid crystal materials. The liquid crystal molecules are relatively thin and long, and have directional and polarizational characteristics. Using these characteristics, the direction in which the liquid crystal molecules are arranged can be controlled by artificially generating an electric filed. Depending on the arrangement direction of the liquid crystal molecules and using optical anisotropy of the liquid crystals, light is allowed to either pass through the liquid crystal or is prevented from passing through the liquid crystal.
Recently, active matrix liquid crystal displays which include TFTs and pixel electrodes arranged in an array have received much attention because they provide enhanced picture quality and natural colors.
The structure of a conventional liquid crystal display is described below. The conventional liquid crystal display includes two panels each having many elements therein, and a liquid crystal layer formed between the two panels. The first panel is also known as the "color filter panel" and contains elements necessary to generate color.
The color filter panel includes red(R), green(G), and blue (B) color filters sequentially arranged to correspond with an array of pixel electrodes disposed in the second panel. Between these color filters, a thin black matrix is formed. The black matrix clarifies the boundaries between different color filters and prevents the generation of a mixture of colors. On the color filter layer, a common electrode is formed. This common electrode functions as one electrode for applying an electric filed to the liquid crystal.
On the other side of the conventional liquid crystal display, the second panel includes switching elements and conductive lines for applying an electric field to the liquid crystals. The second panel is often known as the "active panel". The active panel includes a plurality of pixel electrodes corresponding to positions of pixels, formed on a transparent substrate. These pixel electrodes face the common electrode formed on the color filter panel, and function as the other electrode for applying an electric field to the liquid crystals.
In the horizontal direction of the pixel electrodes, a plurality of signal lines are arranged, whereas a plurality of data lines are arranged in the vertical direction of the pixel electrodes. At the corner of each pixel electrode, a thin film transistor is formed to apply an electric signal to the pixel. The gate electrode of the thin film transistor is connected to a corresponding one of the signal lines, and the source electrode of the thin film transistor is connected to a corresponding one of data lines. The signal line is also know as the "gate line" and the data line is also known as the "source line". The drain electrode of the thin film transistor is connected to a corresponding one of the pixel electrodes. The end portions of the gate line and source line include a terminal or pad for receiving signals applied externally thereto.
When an electrical signal from an external source is applied to the gate pad, the signal is transmitted to the gate electrodes through the gate line. The source line transmits picture data externally applied to the source pad to the source electrodes. The gate electrode controls whether the picture data from the source electrode should be transmitted to the drain electrode. Therefore, by controlling the signal applied to the gate electrode, transmission of the data signal to the drain electrode is controlled. Accordingly, the data signal can be selectively transmitted to the pixel electrode connected to the drain electrode of the thin film transistor. That is, each thin film transistor functions as a switch for operating a corresponding pixel electrode.
The above described first and second panels are separated by a predetermined distance (know as a cell gap) and a liquid crystal material is injected between the two panels into the cell gap. In the outer surface of each panel, a polarizer is formed for selectively transmitting light from the panel. This completes the formation of a liquid crystal panel which is an important component of the liquid crystal display.
The manufacturing process for the conventional liquid crystal panel is rather complicated and requires many different manufacturing steps. Particularly, the active panel containing TFTs requires many manufacturing steps such that the performance and quality of the completed product depends on how well these complicated manufacturing steps are performed. There is less likelihood of a defect occurring in the completed product if a fewer number of manufacturing steps are required. Further, the active panel contains many important elements which may be subject to defects and affect the performance of the liquid crystal display. Thus, simplifying the manufacturing process for the active panel plays an important role in producing a superior liquid crystal display.
FIG. 1 shows a partial view of an active panel of a conventional liquid crystal display, and FIGS. 2a-2g are cross sectional views for explaining a conventional method of manufacturing an active panel, taken along line II--II in FIG. 1.
As shown in FIGS. 1 and 2a, an aluminum alloy is deposited on a transparent glass substrate 1 and patterned through photolithography to form a gate electrode 11, a gate line 13, a gate pad 15, a source pad 25, and a short circuit line 45 each having a prescribed shape. The gate electrode 11 is positioned at one corner of a corresponding one of the pixel electrodes 41 arranged in a matrix form. The gate line 13 connects a plurality of gate electrodes 11 disposed in one direction. The end portion of the gate line 13 includes a gate pad 15. On the other hand, a source pad 25 is formed at the end portion of the source line 23 which is formed over the gate lines 13. The short circuit line 45 connects all of the gate pads 15 and source pads 25.
Often, however, on the surface of a metal material containing aluminum, spike-like projections known as "hillocks" are formed which cause shorts between neighboring layers. To prevent hillock formation, an anodized oxide layer 19 is formed by anodizing. The short circuit line 45, the aluminum containing gate electrode 11, data line 13, gate pad 15, and source pad 25 are used as an anode during the anodizing. However, the anodized oxide layer 19 does not transmit electricity very well. Therefore, if the anodized oxide layer 19 is formed on the surface of the gate pad 15 and the source pad 25, which receive external electrical signals, the received electrical signals are not properly transmitted. To avoid this problem, the anodized oxide layer 19 is not formed on the surfaces of the gate pad 15 and the source pad 25 as shown in FIG. 2b.
As shown in FIG. 2c, a silicon oxide layer or silicon nitride layer is deposited and patterned to form a gate insulating layer 17 on the substrate 1. On the gate insulating layer 17, an intrinsic semiconductor material such as a pure amorphous silicon and an impurity doped semiconductor material such as an impurity doped amorphous silicon are sequentially deposited and patterned by photolithograph to form a semiconductor layer 33 and impurity doped semiconductor layer 35.
As shown in FIG. 2d, using photolithography, the gate insulating layer 17 is patterned to form a first gate contact hole 51 on the gate pad 15, and a first source contact hole 61 on the source pad 25. These first contact holes 51 and 61 are formed through the gate insulating layer 17 and expose portions of gate pad 15 and source pad 25 which do not include the anodized oxide layer 19 thereon.
As shown in FIG. 2e, a metal material such as a chromium or chromium alloy is deposited and patterned to form a source electrode 21 on one side of the semiconductor layer 33, and a drain electrode 31 on the other side of the semiconductor layer 33. Here, ohmic contacts are formed between the impurity doped semiconductor layer 35 and the source electrode 21 and between the impurity doped semiconductor layer 35 and the drain electrode 31. However, if the impurity doped semiconductor layer 35 is continuously formed between the source electrode 21 and the drain electrode 31, the source and drain electrodes 21 and 31 are always in a state of an electrical connection and cannot function as a switch. Therefore, the portion of the impurity doped semiconductor layer 35 between the source and drain electrodes 21 and 31 should be removed, for example, by lithograph.
As further shown in FIG. 2e, source line 23 is formed and, as shown in FIG. 1, extends in a vertical direction to connect the source electrodes 21. The source line 23 is positioned substantially perpendicular to the gate line 13. At the end portion of the source line 23, a source pad mid-electrode 65 is formed in the first source contact hole 61 for contacting with the source pad 25. Above the gate pad 15, a gate pad mid-electrode 55 is formed in the first gate contract hole 51 for contacting with the gate pad 15.
As shown in FIG. 2f, an insulating material such as silicon oxide or silicon nitride is deposited on the overall surface of the substrate. The protective layer 37 is formed by patterning the insulating material using photolithography, and defines a second gate contact hole 53 near the gate pad 15, a second source contact hole 63 near the source pad 25, and a drain contact hole 71 near the drain electrode 31. The second gate contact hole 53 exposes a portion of the gate pad mid-electrode 55, the second source contact hole 63 exposes a portion of the source pad mid-electrode 65, and the drain contact hole 71 exposes a portion of the drain electrode 31.
The short circuit line 45 for connecting the gate pad 15 and source pad 25 is unnecessary for the final liquid crystal display. Therefore, a portion of the short circuit line 45 which connects both the gate pad 15 and source pad 25 to each other is removed or the entire short circuit line 45 may be eliminated. The removal may be performed by lithography (not shown in the FIG. 1 of 2a-2g).
As shown in FIG. 2g, indium tin oxide (ITO) is deposited and patterned to form a pixel electrode 41, a gate pad connecting terminal 57, and a source pad connecting terminal 67. The pixel electrode 41 is connected with the drain electrode 31 through the drain contact hole 71. The gate pad connecting terminal 57 connects with the gate pad mid-electrode 55 through the second gate contact hole 53. The source pad connecting terminal 67 connects with the source pad mid-electrode 65 through the second source contact hole 63.
The above described manufacturing process calls for an anodizing process and requires at least seven or eight patterning steps using a mask (or masking step). If at least one of the steps can be eliminated, the manufacturing cost and time will be substantially reduced and the production yield will increase. In an effort to reduce the number of masking steps, a method which eliminates one or two of the masking steps and does not use the anodizing process has been developed as described below.
FIG. 3 represents a partial view of a conventional liquid crystal display and FIGS. 4a-4f show cross sectional views for explaining the above simplified method, taken along line IV--IV in FIG. 3.
As shown in FIG. 4a, a metal such as an aluminum or aluminum alloy is deposited on a transparent substrate 1 and patterned by photolithography to form a low resistance gate line 13a and a low resistance gate pad 15a. The low resistance gate lines 13a are disposed between the pixel electrodes 41 formed in an array, and the low resistance gate pad 15a is formed at the end portion of the low resistance gate lines 13a.
As described above, layers using aluminum have a tendency to form hillocks on their surface. Therefore, metal material such as chromium (Cr), molybdenum (Mo), tantalum (Ta), or antimony (Sb) is deposited and patterned to form the gate line 13 and gate pad 15 over the low resistance gate line 13a and the low resistance gate pad 15a, respectively. And, as shown in FIG. 4b, a gate electrode 11 branching out of the gate line 13 is formed. The gate electrode 11 is formed at the corner of a corresponding pixel (see FIG. 3). Although, in FIG. 4b, it is shown that the metal material such as Cr, Mo Ta, or Sb completely covers the aluminum layer, only a portion of the aluminum layer may be covered.
As shown in FIG. 4c, over the substrate 1, an insulating material, such as silicon oxide or silicon nitride is deposited to form an insulating layer 17. On the insulating layer 17, an intrinsic semiconductor material, such as a pure amorphous silicon, and an impurity doped semiconductor material, such as an amorphous silicon with impurities therein, are sequentially deposited and patterned to form a semiconductor layer 33 and an impurity doped semiconductor layer 35, respectively.
As shown in FIG. 4d, a metal material such as a chromium or chromium alloy is deposited and patterned to form a source electrode 21, drain electrode 31, source line 23, and source pad 25. The source electrode 21 is formed to overlap a portion of the gate electrode 11 with the semiconductor and impurity doped semiconductor layers 33 and 35 therebetween. The drain electrode 31 is formed to overlap the other portion of the gate electrode 11 with the semiconductor and impurity semiconductor layers 33 and 35 therebetween. Here, ohmic contacts are formed between the source electrode 21 and impurity doped semiconductor layer 35 and between the drain electrode 31 and impurity doped semiconductor layer 35. Using the source electrode 21 and drain electrode 31 as masks, the impurity doped semiconductor layer 35 is selectively etched to remove the impurity doped semiconductor layer 35 between the source electrode 21 and drain electrode 31. As shown in FIGS. 3 and 4d, the source line 23 is arranged vertically and connected with the source electrode 21, and the source pad 25 is formed at the end portion of the source line 23.
As shown in FIG. 4e, an insulating material such as silicon oxide or silicon nitride is deposited over the substrate 1 having the source electrode 21 and drain electrode 31 to form a protective layer 37. The protective layer 37 and a portion of the insulating film 17 are patterned to form a drain contact hole 71, gate pad contact hole 59, and a source pad contact hole 69. The drain contact hole 71 exposes a portion of the drain electrode 31, the gate pad contact hole 59 exposes the gate pad 15, and the source pad contact hole 69 exposes the source pad 25.
As shown in FIG. 4f, on the protective layer 37 a transparent conductive material such as ITO (indium-tin-oxide) is deposited and patterned to form a pixel electrode 41, a gate pad connecting terminals 57, and a source pad connecting terminal 67. The pixel electrode 41 is connected with the drain electrode 31 through the drain contact hole 71. The gate pad connecting terminal 57 is connected with the gate pad 15 through the gate pad contact hole 59. The source pad connecting terminal 67 is connected with the source pad 25 through the source pad contact hole 69.
As described above, the active panel of conventional liquid displays are formed with or without using anodizing. However, both of these methods have problems with respect to the gate pad portion. To better explain these problems of the conventional methods, reference will be made to FIGS. 5a-5b and 6 for the method using anodizing and the method without anodizing, respectively. FIGS. 5a-5b show a cross sectional view taken along line V--V in FIG. 1, and FIG. 6 shows a cross sectional view taken along line VI--VI in FIG. 3.
In the method using anodizing, the anodized oxide layer is composed of a material highly resistant to chemical etching so that it does not react to an etchant used in forming the active panel. Referring to FIG. 5a, in the process of forming the gate insulating layer 17, the semiconductor layer 33, the impurity doped semiconductor layer 35 and the gate pad contact hole 51, the anodized oxide layer 19 formed near the outer edge of the gate pad 15 prevents the etchant near the steps, formed by the gate insulating layer 17 over the gate pad 15, from seeping into the gate pad 15. Further thereafter, as shown in FIG. 5b, when forming the gate pad mid-electrode 55, the gate pad mid-electrode 55 covers the area surrounding the gate pad 15 and protects the gate pad 15. However, using the anodizing method requires many masking steps which increase the number of errors occurring from failing to exactly position the masks.
In the second method, which does not use anodizing, the number of masking steps, errors arising therefrom and the manufacturing time are all reduced as compared to the method using the anodizing. However, in forming the semiconductor and impurity doped semiconductor layer or the source and drain electrodes, the etchant undercuts the gate pad 15 through the steps of the gate insulating layer 17 covering the gate pad 15, causing defects in the gate pad 15 (see FIG. 6).