Embedded memory devices, such as embedded dynamic random access memory (eDRAM), having deep trench capacitors have demonstrated great advantages over planar-stacked device structures. Trench capacitors have replaced the planar storage capacitors in order to meet the scaling demands for high performance dynamic random access memory (DRAM) cell production.
A trench capacitor is a three-dimensional device formed by etching a trench into a semiconductor substrate. After trench etching, a doped region is typically formed in the lower portion of the trench surrounding interior walls of the trench, which serves as an outer electrode or a buried plate electrode of the trench capacitor. A node dielectric is then formed over the outer or buried plate electrode in the trench, which serves as the insulating layer of the trench capacitor, followed by filling the trench, for example, with doped polycrystalline silicon (hereinafter poly-Si), which serves as the inner or upper electrode of the trench capacitor.
One of the major bottlenecks that eDRAM or DRAM technology faces, as the technology scales beyond the 90 nm node, is the parasitic resistance of the trench fill. For example, to write or read a logic level “high” or a state “1,” charge on a bitline is either transferred into the trench (write) or the bitline receives charge from the trench (read). The trench fill material, which forms the inner electrode of the trench capacitor, and through which the charge transfers, is typically comprised of heavily N+-doped polysilicon, which has a relatively high electrical resistivity as compared to metals. Further, the trench capacitor is typically connected to an adjacent field effect transistor (FET) in the eDRAM or DRAM device by an out-diffused buried strap that is also highly resistive. The highly resistive poly-Si trench fill material and out-diffused buried strap lead to high parasitic resistance of the trench capacitor, which in turn significantly limits the performance of the eDRAM or DRAM devices, especially on the read/write speed of such memory cells.
For a 90 nm trench capacitor, the trench resistance has been conservatively estimated to be on the order of 20-30 kohms. For a 65 nm trench capacitor, the resistance is projected to increase even further, since the trench size will decrease by approximately 40%, but the resistivity of the poly-Si electrode and the out-diffused buried strap does not scale with the remaining components of trench capacitor. Thus, if the eDRAM or DRAM devices are to be pushed into high-performance memory designs in which static random access memory (SRAM) is firmly entrenched, data access to and from the trench capacitor would have to be enhanced in order for the eDRAM or DRAM devices to qualify as SRAM cache replacement.
There is therefore a continuing need for improved trench capacitor structures that can be readily incorporated into the eDRAM or DRAM devices to reduce the parasitic resistance in such devices and to enhance the performance, especially the read/write speed, of such devices.
There is further a need for a method that can readily integrate the processing steps required for fabricating such improved trench capacitor structures into the eDRAM or DRAM device fabrication processes, with little or no deleterious impact on the performance of other logic circuitry components, such as field effect transistors (FETs), resistors, diodes, planar capacitors, etc., which are formed adjacent to the trench capacitors in the eDRAM or DRAM devices.