Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allow more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-silicon vias (TSV) are often used in 3DIC and stacked dies. FIG. 1 illustrates a conventional semiconductor package including stacked dies, wherein TSVs 4 are formed in the dies. Dies 10 and 12 each comprise semiconductor substrate 2, on which integrated circuits (not shown) are formed. TSVs 4 penetrate through semiconductor substrate 2, and are connected to the integrated circuits in the respective dies and bonding pads 6. Dies 10 and 12 are bonded through bonding pads 6. Further, bonding pads 6 of die 10 are used to connect die 10 to bumps 8, which are further connected to package substrate 14.
Compared to the conventional wire-bonding, TSVs are more effective in connecting multiple dies. However, when used for stacking memory dies, TSVs suffer shortcomings. Typically, in the process for forming memory dies, it is preferred to have low inventory, short cycle time, low fabrication cost (which means only one mask set is preferred), and full sharing of input/output (I/O) pads. Therefore, it is preferred that memory dies 10 and 12 have exactly the same design, and can be fabricated using a same set of masks.
Since memory dies need to have unique addresses in order to distinguish from each other, the identical memory dies cannot be simply stacked one on top of the other. Conventionally, different redistribution lines are formed for stacking dies. However, this method still needs different mask sets for forming the redistribution lines of the memory dies. Alternatively, interposers are designed. This way, the identical dies can be distinguished by attaching different interposers to dies, so that the memory dies and the attaching interposers in combination are distinguishable. Apparently, this method introduces extra cost for forming and attaching interposers.
Accordingly, what is needed in the art is a semiconductor structure and methods for forming the same that take advantage of stacked memory dies, while at the same time incurring as low cost as possible.