1. Field of the Invention
The present invention relates in general to a mask read-onlymemory (ROM) device having active bit-line clamp circuits. In particular, the present invention relates to a mask ROM device having active bit-line clamp circuits capable of correct and fast accessing of the data bit stored in the memory cells.
2. Technical Background
Mask ROM devices are widely used in digital electronic equipment. For example, in microprocessor-based computer systems, applications such as the storage for digital dictionary databases, as well as program code for TV games require large ROM storage spaces. Mask ROM devices are being asked to have ever increasing storage capacity, while featuring shorter turn-around time.
FIG. 1 shows the schematic diagram of a conventional mask ROM device having clamp circuits. In the mask ROM device of FIG. 1, a number of memory cells M.sub.1, M.sub.2, M.sub.3, M.sub.4, . . . are shown to form a memory cell array. A number of word lines WL.sub.i, that is, WL.sub.0, . . . , WL.sub.5, are utilized for accessing the memory cells in the mask ROM device. The mask ROM device is configured as even and odd columns, as indicated in the drawing by reference numerals OC and EC respectively, and with the SE.sub.i and SO.sub.i utilized as the even and odd select lines respectively, while CS is the column select line. BL indicates representative bit lines. MBL is a main bit line for the mask ROM device. GL.sub.1 and GL.sub.2 are first and second virtual ground lines respectively. GS.sub.1 and GS.sub.2 are logically complementary first and second virtual ground select lines. Bit-line parasitic capacitors are represented by C.sub.0, C.sub.1, C.sub.2, . . . respectively. Sense amplifier 10 is coupled to node B of NMOS FET N.sub.21. Clamp circuit 20 is coupled to node C of NMOS FET N.sub.24 and node D of NMOS FET N.sub.25.
In the mask ROM device, when the even column select line Se.sub.i, the first virtual ground select line GS.sub.1, and the word line WL.sub.0 are active, and when the first virtual ground line GL.sub.1, under control of the NMOS FET N.sub.20 strobed by the column select line CS, is coupled to the drain of the NMOS FET N.sub.23 strobed by the first virtual ground select line GS.sub.1, the memory cell M.sub.1 is then in the state of being accessed. During this stage, if the memory cells M.sub.2 and M.sub.3 are in the "ON" state, their bit-line parasitic capacitances C.sub.2 and C.sub.3 will place extra loading on sense amplifier 10 because of the effect of electric charge distribution.
In order to avoid the added loading of parasitic capacitors C.sub.2 and C.sub.3 as described above, the conventional mask ROM device of FIG. 1 has its second virtual ground line GL.sub.2, under control of the NMOS FET N.sub.22 also strobed by the column select line CS, coupled to the drain of the NMOS FET N.sub.24 strobed by second virtual ground select line GS.sub.1. The source of NMOS FET N.sub.24 is connected at node C to clamp circuit 20.
This arrangement allows for the charging of bit-line parasitic capacitors C.sub.2 and C.sub.3 while memory cell M.sub.1 of the mask ROM device is being accessed, thereby reducing the effect of capacitive loading on sense amplifier 10 placed by parasitic capacitors C.sub.2 and C.sub.3. In the mask ROM device of FIG. 1, the logic circuitry of senseamplifier 10 is shown in FIG. 2A. Clamp circuit 20 has logic circuitry similar to that of sense amplifier 10 and is shown in FIG. 2B. Their only difference is the trip voltage of the respective NOR gate 100.
One problem of clamp circuit 20 is apparent. That is, if the trip voltage of it's NOR gate 100 is set high, the charging voltage will also be high. This reduces the sensing speed of sense amplifier 10 when memory cell M.sub.1 is in its ON state. On the other hand, if the trip voltage of it's NOR gate 100 is set low, the charging voltage will therefore be low. This reduces the sensing speed of sense amplifier 10 when memory cell M.sub.1 is in its OFF state. This phenomena adds to the designing complexity of sense amplifier 10 and clamp circuit 20 of the mask ROM device, as the optimization becomes difficult to set.