1. Field
Systems, devices, and articles of manufacture consistent with the inventive concept relate to a memory device, and more particularly, to a memory device capable of decoupling an internal operation of a pair of bit lines from an internal operation of a bit line sense amplifier and re-coupling them together, a memory module including the same, and a memory system including the same.
2. Description of the Related Art
A memory cell array in dynamic random access memory (DRAM) has a plurality of bank structures to meet throughput, energy efficiency, and capacity demands. Only a single row at a time can be accessed due to the constraints of cost. Accordingly, it is necessary to deactivate a row that has been activated and to precharge a pair of bit lines in order to access another row. Time taken to precharge the pair of bit lines is similar to time taken to read data from the activated row. Therefore, determining when a row is activated and deactivated is critical to the throughput of DRAM.
With the increase of the number of banks in DRAM, the number of requests per bank decreases, which leads lack of information necessary for a DRAM controller to predict a subsequent request and determine whether to deactivate a row that has been activated. As a result, the accuracy of prediction decreases.
Widely used page management policies at present include an open-page policy, a close-page policy, and a hybrid page policy switching between the open-page policy and the close-page policy. However, each of these policies requires a memory controller to predict requests to determine whether to deactivate a row.