1. Field of the Invention
The present invention relates to a driver circuit of an image display device to which a digital image signal is input, and more particularly, to a driver circuit capable of being formed with a reduced occupied surface area, and to an image display device and to an electronic equipment using the driver circuit.
2. Description of the Related Art
Image display devices in which a semiconductor thin film is formed over a glass substrate, and in particular, active matrix image display devices using thin film transistors (hereafter referred to as TFT) have been spreading in recent years. Active matrix image display devices using TFTs have from several hundred thousand to several million TFTs arranged in a matrix shape, which control the electric charge to each pixel.
In addition to pixel TFTs structuring pixels, polysilicon TFT technology for forming driver circuits on the outside of the pixel matrix using polysilicon TFTs formed at the same time has recently been expanding.
Furthermore, not only driver circuits corresponding to analog image signals that are formed at the same time, but also driver circuits corresponding to digital image signals have been realized.
A conventional example of an active matrix liquid crystal display device, which is one type of active matrix image display device, is shown in FIG. 19. The liquid crystal display device is structured by components such as a signal line driver circuit 101, a scanning line driver circuit 102, a pixel matrix 103, a signal line 104, a scanning line 105, a pixel TFT 106, and a liquid crystal 107, as shown in FIG. 19.
FIG. 20 is a diagram for explaining in detail a structure of a conventional example of a signal line driver circuit. Further, FIG. 21 is a timing chart corresponding to FIG. 20. An example of an image display device possessing kxc3x97l (horizontalxc3x97vertical) pixels is explained here. In order to simplify the explanation, an example of a 3-bit digital signal is used, but the digital signal is not limited to a 3 bits in an actual image display device. Furthermore, FIGS. 20 and 21 are shown using a specific example with k=640.
The conventional signal line driver circuit has the following structure. A clock signal CLK and a start pulse SP are input, and a shift register shifts the pulses one by one; a first latch circuit LAT1 which inputs a shift register output signal and stores digital image signal one by one; a second latch circuit LAT2 adjusts an output of the first latch circuit with a latch pulse; and a D/A converter circuit (DAC) converts an output of the second latch circuit to an analog signal. A latch circuit is used as the memory circuit here.
The number of the above shift register stages (corresponding to the number of DFFs shown in FIG. 20) becomes k+1 stages. The shift register output signals become control signals SR-001 to SR-640 of the first latch circuit LAT1, either directly or through a buffer. The first latch circuit LAT1 latches digital image signals D0 to D2 on digital signal lines in accordance with the control signals. It is necessary to divide the first latch circuit LAT1 into 3 digital image signal lines (the number of bits) by k (the number of horizontal signal lines) here. The second latch circuit LAT2 also must similarly be divided into 3xc3x97k.
The shift register clock signal CLK, the start pulse SP, the digital image signals D0 to D2, and a latch pulse LP are input to the signal line driver circuit. First, the start pulse SP and the clock signal CLK are input and the shift register shifts the pulses in order. The shift register output (SR-001 to SR-640 in FIG. 20) becomes shifted pulses for each clock signal CLK period, as shown in FIG. 21. The first latch circuit LAT1 operates in accordance with the shift register output signal, and the digital signal image input at this time is latched. By shifting the shift register pulse by one line portion, one line portion of the digital image signal is stored in the first latch circuit LAT1. (L1-001 to L1-640 in FIG. 20. Note that, for simplification, this is shown without differentiating bits in FIG. 20.)
Next, in a retrace period, the latch pulse LP is input, and the second latch circuit LAT2 operates in accordance with the latch pulse, and the image signal (L1-001 to L1-640 in FIG. 20 and FIG. 21) stored in the first latch circuit LAT1 becomes stored in the second latch circuit LAT2. When the retrace period is completed and the next horizontal scan period begins, the shift register again begins operation. On the other hand, the digital image signal stored in the second latch circuit LAT2 (L2-001 to L2-640 in FIG. 20 and FIG. 21. Note that, for simplicity, bit differentiation is not shown.) is converted to an analog signal by the D/A converter circuit DAC. The analog signal is sent to the signal lines (S001 to S640 in FIG. 20), and is written to the pixels when the pixel TFTs turn on.
The image display device performs write-in of the image signal to the pixels, and display, in accordance with the above operations.
A digital type driver circuit like such as that explained above has a disadvantage of occupying an extremely large surface area in comparison with an analog type driver circuit. The digital method has the merit of adjusting to two signal values, xe2x80x9cHIxe2x80x9d and xe2x80x9cLOxe2x80x9d, but in exchange, the amount of data becomes enormous, and this becomes a large impediment in structuring an image display device from the standpoint of miniaturization. An increase in the surface area of an image display device invites an increase in manufacturing cost, and there is a problem of worsening profit for the manufacturing industry.
Further, along with a rapid increase in the amount of data handled in recent years, there are plans for increases in the number of pixels and in pixel definition. However, the number of driver circuits increases in accordance with the increase in number of pixels, and it is preferable to reduce the surface area of the driver circuits.
Commonly used computer display resolution examples are shown below in accordance with the name of the standard and the number of pixels.
For example, in the case of the SXGA standard, if the number of bits is set to 8, then 10,240 of the first memory circuit and the second memory circuit, respectively, becomes necessary for 1280 signal lines with the above conventional driver circuit. Further, high definition television image receiving machines such as high-vision TV (HDTV) are spreading, and high definition images have become required in not only the computer world, but also in the audio-visual field. In the United States, terrestrial digital broadcasting has started, and in Japan as well, a digital broadcasting age has begun. Images having 1920xc3x971080 pixels are strong in digital broadcasting, and therefore driver circuit miniaturization is required without delay.
However, as stated above, the surface area occupied by a signal line driver circuit is large, and this is an impediment to making image display devices smaller. In order to solve the above problems, an object of the present invention is to provide a technique advantageous in reducing the amount of surface area occupied by a signal line driver circuit, and in miniaturization.
A memory circuit and a D/A converter circuit within a signal line driver circuit are made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and by performing processing with respect to signal lines in which the memory circuit and D/A converter circuit differ in each divided period, all signal lines can be driven normally. It thus becomes possible to reduce the number of memory circuits and D/A converter circuits within the signal line driver circuit to 1/n that of a conventional example.