The present invention relates to a semiconductor integrated circuit device and a method of fabrication thereof, and the invention relates more particularly to a semiconductor integrated circuit device having multilevel metallization and a method of fabricating such a device.
The structure of a known semiconductor device is shown in FIG. 2. As can be seen from this figure, in the known semiconductor device, an isolation film 10, a gate oxide film 11 and gate electrodes 3 are formed on the silicon substrate 2. A lower metallization layer 5 is formed over the laminate via an interlayer dielectric film 4. An upper metallization layer 7 is formed over the lower metallization layer 5 via an interlayer dielectric film 6. The upper metallization layer 7 and the lower metallization layer 5 are electrically connected by electrodes 9 buried in contact holes 8. This semiconductor device is fabricated in a manner described below.
To electrically isolate individual transistors, the silicon substrate is first thermally oxidized locally to form the isolation film 10. Then, the gate oxide film 11 is formed by thermal oxidation in regions where transistors should be formed. The gate electrodes 3 are formed on the gate oxide film by a CVD process step and then by a photolithography step. Ions are implanted into the silicon substrate 2 to form a pn junction. Thus, an ion-implanted layer is formed. Thereafter, the interlayer dielectric film 4 is formed over the gate electrodes 3 by CVD. To make the surface of the interlayer dielectric film 4 as flat as possible, the interlayer dielectric film 4 is caused to reflow by annealing, or the interlayer dielectric film is deposited as a thick layer and is etched back.
The lower metallization layer 5 is formed on top of the interlayer dielectric film 4 by sputtering and then by photolithography. The interlayer dielectric film 6 and the upper metallization layer 7 are formed on the lower metallization layer 5 similar, to the lower metallization layer 5. The contact holes 8 are formed by local etching to electrically connect the upper metallization layer 7 and the lower metallization layer 5. The buried electrodes 9 are formed inside the contact holes 8. These techniques are described, for example, in Japanese Patent Laid-Open No. 291763/1992.
Semiconductor devices tend to be packaged with an increasingly larger device density year after year. Concomitantly, it is necessary to increase the depth of the contact holes 8. In particular, if the semiconductor device 1 has a minimum linewidth of less than 0.5 xcexcm, a delay in the conductor lines is a rate limiter which impedes improvement of the operating speed of the semiconductor device 1. To prevent this, the capacitance between the two metallization layers is reduced. For this purpose, the thickness of the interlayer dielectric film is increased. That is, it is necessary to increase the depth of the contact holes 8. With this trend, it is necessary to increase the depth of the contact holes 8 in devices having minimum linewidths of less than 0.5 xcexcm, typified by a 256-megabit DRAM, to accomplish higher speeds.
Where more or higher functions are to be imparted to the semiconductor device, the contact holes 8 need to be deeper, which is also the case where higher operating speeds are necessary. For example, an existing computer has been fabricated by mounting both a semiconductor chip having a single function such as a CPU and semiconductor chips acting as memories on a printed-circuit board. In recent years, however, attempts have been made to obtain improved efficiencies or more functions by fabricating a CPU and memories on one chip. This has demanded that the depth of the contact holes 8 be increased. As an example, a combination of a dynamic memory and a logic circuit such as a CPU will be considered. Tall capacitors exist on top of gate electrodes of a dynamic memory. Therefore, the metal interconnection lines are at a higher level than in the logic circuit. The logic circuit needs more metallization layers than memories and so the top metallization layer of the logic circuit must pass over the capacitors. Therefore, the contact holes 8 permitting either connection of these different metallization layers or connection of the top metallization layer and the semiconductor substrate need to be deeper than conventional.
Using a known technique, if the interlayer dielectric film is made thicker, the irregularities on the surface increase. Furthermore, when a metallization layer is patterned photolithographically, defocusing takes place. For these and other reasons, limitations are imposed on the depth of the contact holes 8.
In recent years, chemical-mechanical polishing (CMP) has permitted perfect planarization. Consequently, no limitations are placed on steps that can be planarized. Hence, application of contact holes 8 which are so deep that they have not been heretofore employed from a point of view of manufacturing yield are now being discussed.
It is considered that this technique is advantageous where a dynamic memory and a logic circuit such as a CPU are both mounted on one chip. In particular, the dynamic memory has tall capacitors on top of gate electrodes and so metallization layers exist at higher positions than the logic circuit. Therefore, in order to connect the memory and the logic circuit within one chip, it is necessary to perform a planarization step so that the interlayer dielectric films 4 and 6 in the logic circuit are thick and that the interlayer dielectric films 4 and 6 in the memory are thin. To planarize steps that are unprecedentedly large, adoption of chemical-mechanical polishing (CMP) is being discussed.
Chemical-mechanical polishing (CMP) is designed to mechanically polish interlayer dielectric films to flatten them. Therefore, it is possible to obtain interlayer dielectric films 4 and 6 having surfaces parallel to the surface of the silicon substrate surface without the sagging experienced in the known etching technique. Especially, in a multifunctional semiconductor device in which a CPU is combined with memories, deep contact holes formed by CMP are considered unavoidable.
However, our research has revealed that simply deepening the contact holes 8 to seek higher functions or higher operating speeds does not result in fabrication of the semiconductor 1 with high reliability. Specifically, if the contact holes 8 are simply deepened without taking account the dimensions at various locations, the electrodes 9 buried in the contact holes 8 peel at the locations of the contact holes 8 at which stress is concentrated. Consequently, electrical connections with a high degree of probability are not feasible.
Furthermore, we have discovered that planarization achieved by CMP increases the possibility of delamination of the buried electrodes. In particular, CMP completely flattens the whole surface of the semiconductor device chip. This increases the stress. In the known technique, different layers are slightly uneven as shown in FIG. 2 and so the stress is distributed (FIG. 4a). The stress concentrated in the corners of the contact holes 8 is mitigated. However, CMP achieves complete planarization, resulting in concentration of the stress in the corners of the contact holes 8. Hence, delamination is likely to occur.
It is an object of the present invention to provide a reliable semiconductor device which operates at a high speed or has many functions and in which delamination of buried electrodes is prevented.
We have made an intensive investigation to achieve the above-described object and have discovered the mechanism for delamination of a buried electrode. This mechanism is described below with reference to FIGS. 3-8.
The buried electrodes delaminate during the processing step for forming a film for creating the buried electrodes 9 shown in FIG. 3. Thermal stress acting on the buried electrodes is concentrated in the corners of the contact holes. The buried electrodes 9 begin to delaminate from the lower metallization layer 5. In particular, the interlayer dielectric film is made of a material having a small coefficient of thermal expansion such as a silicon oxide film. On the other hand, the buried electrodes 9 are made of a material having a large coefficient of thermal expansion such as aluminum or tungsten. Therefore, if the temperature is lowered after formation of a film creating the buried electrodes 9 at a high temperature, the buried electrodes 9 undergo a large tensile stress acting vertically upward. Since the lower metallization layer 5 is made of a material having a large coefficient of thermal expansion such as aluminum or copper, shrinkage occurs in the direction of the film thickness during a temperature drop. As a result, the buried electrodes 9 are pulled vertically. Due to these two actions, a large tensile stress acts on the buried electrodes 9. Stress is concentrated in the corners. If the stress exceeds the limit stress for delamination, then delamination does take place. Especially, where planarization is performed by CMP, stress dispersion does not take place as shown in FIG. 4b. Rather, the stress is concentrated at one point. This increases the stress at the corners further. Since the delamination occurs when the stress in the thin film exceeds the limit stress, the delamination can be prevented by holding the stress in the thin film below the limit stress.
Taking account of the above-described mechanism for producing delamination, we have analyzed the sensitivity and have found that the stress in the buried electrodes 9 causing the delamination is affected greatly by two dimensional parameters, i.e., the depth of the contact holes 8 and the thickness of the lower metallization layer 5. Since the thermal stress is a function of the lengths of the two materials, a larger tensile stress is produced if the contact holes are deeper and the lower metallization layer 5 is thicker with the structure shown in FIG. 3. Therefore, delamination of the buried electrodes 9 can be prevented even if the contact holes are deep by optimizing the dimensional parameters other than the contact hole depth.
FIG. 5 shows an example of stress analysis by a finite element method, using these two dimensional parameters. Values of stress at the corners of the contact holes normalized with the strength of the limit stress for delamination are shown in this figure, as well as the presence or absence of delamination occurring in experiments. It can be seen from these results that with the known device, stress is small, because the contact holes are not required to be deep. Hence, delamination heretofore has presented no problems. However, where portions having different heights such as memories and a logic portion are formed on one chip of a semiconductor device, the contact holes 8 are made deep. Also, where high-density devices are fabricated, using design rules of less than 0.5 xcexcm, to cope with higher operating speeds, the contact holes 8 are rendered deeper. In these cases, the dependence of the delamination on the thickness of the lower metallization layer 5, i.e., the delaminated region, becomes conspicuous. That is, it is obvious that the thickness of the lower metallization layer 5 needs to be limited for high-speed devices having such high device density or many functions.
The tensile stress also depends much on the density of the contact holes. FIG. 6 shows the relation of stress normalized with the limit strength for delamination to the contact hole spacing. The contact hole spacing is the distance between the closest contact holes as shown in FIG. 7. As shown in FIG. 8, conducting lines connected with the closest contact hole may terminate in the vicinities of the contact hole.
Where the contact hole spacing is 0.5 xcexcm, i.e., the contact holes are present at a high density, the stress is distributed among the contact holes and thus is small as shown in FIG. 6.
Where the contact holes are more sparsely distributed, the stress increases. Where the contact hole spacing is 10 xcexcm, the stress becomes almost saturated. That is, in order to prevent delamination in the semiconductor device 1, it is necessary to limit the thickness of the lower metallization layer 5 such that the stress at the corners of the contact holes is less than the limit intensity for delamination where the contact hole spacing is more than 10 xcexcm.
The present invention provides a semiconductor device comprising: a semiconductor substrate having a main surface; plural layers of metallization stacked on the main surface of the semiconductor substrate via a dielectric film; and conductive interconnects formed by said layers of metallization; and contact holes for electrically connecting desired ones of the conductive interconnects of the different layers of metallization. The layers of metallization include a lower metallization layer closer to the substrate. The lower metallization layer contains aluminum atoms. The interconnects of the lower metallization layer have a minimum linewidth R of less than 0.25 xcexcm. Conductive materials including tungsten atoms are present inside the contact holes. The depth A of the contact holes, the minimum linewidth R of the conductive interconnects of the lower metallization layer, and the thickness B of the lower metallization layer satisfy the relations given by
[Eq. 5]
(0.605/R)0.5 less than A less than 2.78xe2x88x921.02B+0.172B2 
In this structure, if tungsten atoms are contained in the conductive materials inside the contact holes, the conductive materials inside the contact holes are prevented from delamination from the conductive interconnects. Therefore, breaks in the conductive interconnects or shorts are less likely to occur. Hence, a reliable semiconductor device can be obtained.
If aluminum atoms are contained in the conductive materials inside the contact holes, the depth A of the contact holes, the minimum linewidth R of the interconnects of the lower metallization layer, and the thickness B of the lower metallization layer should satisfy the relations given by
[Eq. 6]
(0.605/R)0.5 less than A less than 3.84xe2x88x922.14B+0.25B2 
If the surface of the dielectric film in contact with the bottom surface of the upper metallization layer is planarized by CMP, or if the spacing between the adjacent contact holes is more than 10 xcexcm, the conductive materials inside the contact holes are likely to delaminate from the conductive interconnects. In accordance with the present invention, the conductive materials can be prevented from delamination from the interconnects. Hence, a reliable semiconductor device can be derived.
Where a semiconductor device comprises a semiconductor substrate having memories and a logic circuit packed on one main surface of the substrate, thus requiring deep contact holes, the present invention can prevent the conductive materials from delamination from the conductive interconnects. In consequence, a reliable semiconductor device can be manufactured.
Other objects and features of the invention will appear in the course of the description thereof, which follows.