1. Technical Field
This invention relates to digital to analog (D/A) conversion in data line driver subsystems for flat panel active matrix displays such as thin-film transistor liquid crystal displays (TFT-LCD). More specifically, it relates to the type of display which receives its pixel data in digitally encoded form and converts the digital data to analog data line signals in each data driver circuit.
2. Background Art
In the above mentioned displays the number of colors or gray levels that can be precisely displayed is limited in part by the precision and accuracy of the D/A conversion. For economic reasons, more than one hundred data driver circuits, along with associated digital circuitry, must be integrated into each monolithic silicon chip. This requirement eliminates from consideration most of the conventional means of achieving high D/A performance.
A copending application by the present inventor, U.S. patent application Ser. No. 07/968,699, filed on Oct. 30, 1992, and entitled "Pipeline Charge Metering Digital-To-Analog Data Line Driver", which is hereby incorporated by reference, teaches the application of charge metering techniques to the sampled-ramp or sampled-staircase type of data line driver. While this is an advance in the art, is retains the limitation that the speed required of the circuits scales with the precision (the number of gray levels or colors to be represented by the analog output).
A D/A converter using summing of binary weighted charge packets is the subject of U.S. Pat. No. 3,836,906 by Ando et al. The particular method used by Ando et al has the following disadvantages:
1. The output contains error contributions from the uncertainty of the threshold voltages of several MOS transistors. This is compounded by the fact that the output, including the output for analog zero, has a finite pedestal due to the necessary minimum charge contributions from each binary input. The pedestal contains threshold uncertainty which may be larger than the smallest analog outputs.
2. Multiple capacitors are used, one for each bit plus one, having sizes in binary-weighted sequence. Thus there is a large ratio of sizes between the largest and the smallest capacitor. If the smallest is large enough to make the ratio very precise, the capacitors occupy very large amounts of chip area.
3. The largest of the capacitors must be formed differently than the others. The others share a common electrode, such as the silicon substrate, but the largest must have two independent electrodes. This complicates the technology and makes its area larger than it would otherwise be.
4. The binary weighted charge packets to be summed are provided directly by the digital inputs, which are loaded by the binary weighted capacitors.
5. The output voltage dynamic range is about one-half of the largest voltage supply.