1. Field of the Invention
This invention relates to a semiconductor device which switches at a high speed from an on state to an off state and a driving method for the semiconductor device.
2. Description of the Related Art
A memory has been proposed wherein a thyristor is used such that the turn-on and turn-off characteristics of the thyristor are controlled through a gate electrode implemented thereon and the thyristor is connected in series to an access transistor. The memory of the type described is suitable for an SRAM (Static Random Access Memory) and is hereinafter referred to as T-RAM. In a memory operation of the T-RAM, the off region of the thyristor is represented by “0” and the off region of the thyristor is represented by “1”.
The thyristor has such a basic structure that a p-type region p1, an n-type region n1, another p-type region p2 and another n-type region n2 joined together in this order and, for example, n-type silicon and p-type silicon are laminated in four layers. In the following description, the basic structure described is represented by p1/n1/p2/n2. Two different structures have been proposed by T-RAM, Inc. One of the structures includes the p1/n1/p2/n2 structure formed vertically on a silicon substrate. Meanwhile, the other one of the structures includes the p1/n1/p2/n2 structure formed transversely on a silicon layer using a SOI substrate. In both configurations, a gate electrode having a MOS structure is provided on the p-type region p2 to achieve high speed operation.
For example, as seen in FIG. 7A, a semiconductor device of the thyristor configuration includes a first p-type region p1, a first n-type region n1, a second p-type region p2 and a second n-type region n2 provided in order in four layers to obtain the p1/n1/p2/n2 structure. An anode electrode A is connected to the first p-type region p1 at one end of the semiconductor device while a cathode electrode K is connected to the second n-type region n2 provided at the opposite end of the semiconductor device. Further, a gate electrode G is disposed on the second p-type region p2 disposed on the inner side. Such a thyristor as described above may have a configuration wherein the p1/n1/p2/n2 structure is provided vertically on a surface layer of a silicon substrate or another configuration wherein the p1/n1/p2/n2 structure is provided transversely.
In the semiconductor device of the thyristor configuration described above, if a forward bias is applied between the anode electrode A and the cathode electrode K as seen in FIG. 7B, then holes are supplied from the first p-type region p1 connected to the anode electrode A to the first n-type region n1 while electrons are supplied from the second n-type region n2 connected to the cathode electrode K to the second p-type region p2. Then, the holes and the electrodes are re-coupled at the joining portion between the n-type region n1 and the p-type region p2, and electric current flows thereby and the semiconductor device is placed into an on state.
On the other hand, if a reverse bias is applied between the anode electrode A and the cathode electrode K as seen in FIG. 7C, then the semiconductor device is placed into an off state. However, a period of time of approximately several ms may be required until a substantial off state is reached. In other words, if the semiconductor device is placed into an on state once, then it does not place itself into an off state spontaneously only if a reverse bias is applied between the anode electrode A and the cathode electrode K. Thus, the current is reduced to a level below the holding current or the power supply is disconnected thereby to sweep out or re-couple excessive carriers flowing to the n-type region n1 and the p-type region p2.
Therefore, in order to change over the semiconductor device from an on state to an off state, a negative voltage is applied to the anode electrode A while a positive voltage is applied to the cathode electrode K to establish a reverse bias state. However, only with this, a period of time of approximately several ms may be still required.
Here, an example of an existing cell array is described with reference to FIG. 8. As seen in FIG. 8, storage elements 102 are arrayed, for example, in a matrix on a SOI substrate 100. The storage elements 102 include a thyristor 103 having such a configuration which includes a gate electrode G as described hereinabove with reference to FIG. 7A and a field effect transistor 104 are connected in series. Now, it is assumed that, from between two storage elements 102 connected to the same bit line (not shown), one storage elements 102 (102a) corresponds to a selected bit while the other storage element 102 (102b) corresponds to a non-selected bit. Upon turning off operation, that is, upon “Write 0” operation, while a voltage in a reverse bias condition is applied simultaneously from a bit line contact of the cathode side to the storage element 102a of the selected bit connected to the bit line (not shown), no voltage is applied to the thyristor gate 113 of the storage element 102b of the non-selected bit. Therefore, the turning off speed of the non-selected bit is very low, and consequently, only the selected bit can be turned off.
As seen from a pulse timing chart of FIG. 9, a voltage is applied to the gate electrode (thyristor gate) provided on the p-type region p2 so that an electric field is generated in the p-type region p2 to cause electrons as excessive carries to be discharged compulsorily thereby to place the semiconductor device into a substantial off state as quickly as possible. In this instance, high speed operation of several ns can be achieved.
Meanwhile, also a configuration called GTO (Gate Turnoff Thyristor) wherein such a gate electrode as described above contacts directly with a p-type region is available. The configuration which includes a MOS electrode is a modification to the GTO configuration, and the role of the electrode therein is same.
However, where a bulk silicon wafer is used, since the p-type region p2 extends deeply in the depthwise direction of the substrate, the bias from the gate electrodes reaches only part of the layer of the p-type region p2. Therefore, even if a bias is applied from the gate electrode, the effect of it is restricted, and it is difficult to separate the selected bit and non-selected bit from each other to prevent disturbance.
Now, a relationship between the voltage VAK between the anode electrode A and the cathode electrode K in a semiconductor device of the thyristor configuration described above and current I flowing through the semiconductor device is described with reference to FIG. 10.
If an increasing positive voltage is applied to the anode electrode A as seen in FIG. 10, then when the voltage VAK reaches a critical voltage VFB, the pn junction between the n-type region n1 and the p-type region p2 is subject to a forward bias, and the voltage VAK drops and current higher than holding current IH begins to flow. However, before the critical voltage VFB is reached, only switching current IS lower than the holding current IH flows, and when the critical voltage VFB is exceeded, higher current than the holding current IH begins to flow.
Various configurations have been proposed wherein a gate electrode is formed in a MOS structure wherein an electrode is disposed on the p-type region p2 with an insulating layer interposed therebetween in order to speed up such switching operation as described above. Such configurations are disclosed, for example, in U.S. Pat. No. 6,462,359 (B1), Farid Nemati and James D. Plummer, “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device”, 1998 IEEE, VLSI Technology Tech. Dig., P. 66, 1998, Farid Nemati and James D. Plummer, “A Novel Thyristor-Based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories”, 1999 IEEE IEDM Tech., p. 283, 1999 and Farid Nemati, Hyun-Jin Cho, Scott Robins, Rajesh Gupta, Marc Tarabbia, Kevin J. Yang, Dennes Hayes, and Vasudenvan Gopalakrishnan, “Fully Planar 0.562 μm2 T-RAM Cell in a 130 nm SOI CMOS Logic Technology for High-Density High-Performance SRAMS”, 2004 IEEE IDEM Tech., p. 273, 2004.