The present invention relates to memory devices generally and, more particularly, to a circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports.
Multi-port memory devices are used in many different applications to communicate and share data between two or more systems. When two or more of the systems have buses of different size, some method of bus matching must be employed. One conventional approach is to use some form of external logic. Memory devices with external bus matching capability can, in a particular example, transfer four xe2x80x9cbytesxe2x80x9d (9 bits/xe2x80x9cbytexe2x80x9d) of data in the standard x36 format (e.g., xe2x80x9clong-wordxe2x80x9d) as well as x18 (e.g., xe2x80x9cwordxe2x80x9d) and x9 (e.g., xe2x80x9cbytexe2x80x9d) formats.
The present invention concerns an apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a counter address signal (to be read back), (ii) a first data signal (e.g., pipelined), or (iii) a second data signal (e.g., flow-through) as an output signal in response to one or more first control signal(s). The second circuit may be configured to generate (i) the counter address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signal(s). The third circuit may be configured to generate one or more I/O control signal(s) in response to the cycle identification signal, one or more bus matching format control signal(s), and one or more counter read-back control signal(s). The one or more I/O control signal(s) may determine the format of the output signal.
The objects, features and advantages of the present invention include providing a circuit, architecture, and method for reading an address counter and/or matching a bus width through one or more synchronous ports that may: (i) place internal address information on the I/O lines of a memory device in the same manner as data from the memory array; (ii) use the I/O multiplexer buffer to select between address information, flow-through data, and pipelined data; (iii) output the internal address information using one or two clock cycles depending on the user-controlled external I/O bus format as set by bus-matching specific external signals; (iv) internally control the number of cycles and specific multiplexing scheme for outputting internal address information; and/or (v) register the internal address information and then read the information out in subsequent clock cycles, depending on the bus-matching format and/or the active synchronous operation mode (e.g., flow-through or pipelined).