The present invention relates to a regulator circuit which supplies a predetermined source voltage to a logic circuit or the like, and particularly to a reduction in power consumption.
FIG. 2 is a configuration diagram of a conventional regulator circuit.
The regulator circuit generates a constant voltage VREG from a source potential VDD and supplies the same to a logic block 40. The regulator circuit has a reference voltage generating unit 10, a differential amplifying unit 20 and a bias voltage generating unit 30.
The reference voltage generating unit 10 comprises a P channel MOS transistor (hereinafter called “PMOS”) 11 connected between the source potential VDD and a node N1, and a PMOS 12 and an N channel MOS transistor (hereinafter called “NMOS”) 13 diode-connected in the forward direction and series-connected between the node N1 and a ground potential GND. The gate of the PMOS 11 is supplied with a bias voltage VBa from the bias voltage generating unit 30 and a reference voltage VREF is outputted from the node N1.
The differential amplifying unit 20 has NMOSs 21a and 21b whose gates are supplied with the reference voltage VREF and an adjusted or regulated voltage VREG respectively. The drains of the NMOSs 21a and 21b are respectively connected to the source potential VDD through PMOSs 22a and 22b. The sources thereof are commonly connected to a node N2. The node N2 is connected to the ground potential GND through an NMOS 23. The gates of the PMOSs 22a and 22b are connected to the drain of the NMOS 21b, and the drain of the NMOS 21a is connected to the gate of a PMOS 24.
The source and drain of the PMOS 24 are respectively connected to the source potential VDD and a node N3. The drain of an NMOS 25 is connected to the node N3, and the source thereof is connected to the ground potential GND. The gates of the NMOSs 23 and 25 are supplied with a bias voltage VBb from the bias voltage generating unit 30 so that a regulated voltage VREG is outputted from the node N3, followed by being supplied to the logic block 40.
Incidentally, the regulator circuit is used with an external stabilization capacitor 41 corresponding to the maximum load current of the logic block 40 being connected between the node N3 and the ground potential GND in addition to the logic block 40.
In the regulator circuit, a predetermined constant current flows through the PMOS 11 of the reference voltage generating unit 10 and the NMOSs 23 and 25 of the differential amplifying unit 20 according to the bias voltages VBa and VBb supplied from the bias voltage generating unit 30. Thus, a reference voltage VREF occurs in the node N1 of the reference voltage generating unit 10. The reference voltage VREF is supplied to the voltage-follower connected differential amplifying unit 20, and a voltage VREG regulated so as to assume the same potential as the reference voltage VREF is outputted from the node N3 corresponding to an output terminal of the differential amplifying unit 20. The voltage VREG is applied across the smoothing stabilization capacitor 41 and supplied to the logic block 40 as a source voltage.
The above related art refers to a patent document 1 (Japanese Unexamined Patent Publication No. 2002-268758).
In the regulator circuit, however, the constant current always flows through the PMOS 11 of the reference voltage generating unit 10 and the NMOSs 23 and 25 of the differential amplifying unit 20 according to the bias voltages VBa and VBb regardless of the load current that flows through the logic block 40. Therefore, it has interfered with a reduction in power consumption in a microminiaturized portable device such as a clock.