This invention relates, in general, to insulated gate field effect transistors, and more particularly to short channel insulated gate field effect transistors.
Semiconductor devices such as insulated gate field effect transistor (IGFET) devices are becoming increasingly important in low voltage applications. As IGFET devices are scaled to smaller and smaller dimensions, manufacturers must refine transistor designs to maintain optimum device performance. Typically, in IGFET devices having channel lengths in the sub-micron range, manufacturers must carefully fabricate drain regions to avoid performance degradation problems such as hot carrier injection, drain leakage, punch-through, and the like.
In IGFET devices having channel lengths of about one micron, many device performance problems can be corrected by forming a lightly-doped-drain (LDD) region. The LDD region acts to lower the electric field in the channel region near the drain region. This reduced electric field improves threshold voltage stability by reducing hot carrier injection into the gate oxide layer overlying the channel region. However, the LDD region causes a reduction in performance because of an increase in source resistance, which negatively impacts transconductance. Also, as the channel length approaches 0.5 microns and below, drain engineering techniques (e.g., LDD regions) are not as effective in preventing performance degradation.
Additionally, manufacturers have used counter-doped source and drain regions to reduce sub-surface punch-through in short channel devices. These counter-doped regions are often referred to as "halo" regions. Although the halo regions are effective in reducing punch-through, they decrease carrier mobility in the channel region thereby degrading drive current. Also, the halo regions increase junction capacitance, which degrades switching speed performance.
Another approach to preventing performance degradation includes placing a higher doped region in the channel region between the source and drain region and extending from the surface down into the bulk semiconductor material. This higher doped region is of the same conductivity type as the channel region. Although this approach is effective in reducing punch-through, it also decreases carrier mobility in the channel region, which degrades drive current. In an alternative but similar approach, the higher doped region is placed in the channel region below the surface and contacting both the source region and the drain region. This alternative approach improves drive current capability but suffers from reduced breakdown voltage performance and a higher junction capacitance, which in turn degrades switching performance.
As is readily apparent, structures and methods are needed that overcome at least the above problems found in the prior art. It would be advantageous to manufacture such structures in a cost effective and reproducible manner. Additionally, it would be of further advantage if such structures could operate at relatively low voltages and still offer high breakdown voltage capability.