As a method for producing a SOI (Silicon on Insulator) wafer, in particular, a method for producing a thin-film SOI wafer that can enhance the performance of a leading-edge integrated circuit, attention is given to a method of producing a SOI wafer by delaminating an ion-implanted wafer after bonding (an ion implantation delamination method: a technology which is also called SmartCut®).
The ion implantation delamination method is a technology of producing a SOI wafer by: forming an oxide film on at least one of two silicon wafers and implanting gas ions such as hydrogen ions or rare gas ions into one (a bond wafer) of the silicon wafers from the upper surface thereof to form an ion implanted layer (also referred to as a microbubble layer or an encapsulated layer) in this wafer; bringing the ion-implanted surface into close contact with the other silicon wafer (a base wafer) with the oxide film sandwiched therebetween and then performing heat treatment (delamination heat treatment) to delaminate the one wafer (the bond wafer) in the form of a thin film by using the microbubble layer as a cleavage plane; and further performing heat treatment, (bonding heat treatment) to achieve firm bonding (refer to Patent Document 1). In this stage, the cleavage plane (the delaminating plane) is the surface of a SOI layer, and a SOI wafer whose SOI film thickness is small and highly uniform is obtained relatively easily.
However, a damaged layer caused by ion implantation is present on the SOI wafer surface subjected to delamination and the degree of surface roughness is higher than that of a mirror surface of a normal silicon wafer. Thus, in the ion implantation delamination method, it is necessary to remove such a damaged layer and surface roughness.
In the past, in order to remove the damaged layer or the like, mirror polishing (stock removal: about 100 nm) with an extremely small polishing stock removal, which is called touch polish, has been performed in the final process after the bonding heat treatment. However, if polishing including a mechanical processing element is performed on the SOI layer, a nonuniform stock removal of polishing undesirably decreases the film thickness uniformity of the SOI layer achieved by implantation of hydrogen ions or the like and delamination.
As a method for solving such a problem, flattening processing that improves surface roughness by performing high-temperature heat treatment in place of the touch polish have been performed. For instance, in Patent Document 2, performing heat treatment (rapid heating/rapid cooling heat treatment (RTA)) in a reducing atmosphere containing hydrogen without polishing the surface of a SOI layer after delamination heat treatment (or bonding heat treatment) is proposed.
Here, as described in (0065) paragraph of Patent Document 2, before performing heat treatment on the SOI layer surface (the delaminating plane) subjected to delamination, performing widely-known wet cleaning called so-called RCA cleaning is required to avoid contamination by particles, impurities, or the like.
Moreover, according to (0050) paragraph of Patent Document 3, when a SOI wafer with an oxide film in a terrace portion is fabricated by the ion implantation delamination method, silicon thin pieces adhere to the oxide film in the terrace portion at the time of delamination of a bond wafer, which becomes a cause of, for example, particle contamination by subsequent epitaxial growth. Patent Document 3 describes that, in order to avoid this problem, wet cleaning such as SC1 cleaning (cleaning by a mixed aqueous solution of NH4OH and H2O2) or HF cleaning is performed before epitaxial growth as a cleaning process that removes the silicon thin pieces present in the terrace portion.
Here, of SOI wafers with an oxide film in a terrace portion, in particular, when the BOX (buried oxide film) layer thickness of a SOI wafer is large and a few μm, in order to suppress the occurrence of warpage in the wafer, a backside oxide film having a similar thickness is formed. Such a SOI wafer having a large BOX layer thickness has been recently used for various purposes in Si photonics or RF devices (radio-frequency devices).