In conventional testing of memory devices, a tester is used to supply the control signals such as RAS, CAS and WE, address signals, such as Ao-An, and data to the device under test. Outputs from the device under test are sampled by the tester to determine whether the device passes or fails. Testing of memories requires longer tester times, as device density increases. This results in escalating test cost. As the capacity of integrated circuit memory devices increases to 256 Mbits and above, testing time per device becomes a major component of cost of integrated circuit memory devices.
One way to test integrated circuit memory devices in less time per device is to apply a single test data bit to several cells concurrently by multiplexing the single bit to the several cells in parallel. Some failures, however, cannot be screened unless a single cell is accessed at a time. With limited parallelism, i.e., a number of units being tested simultaneously, high test time also translates into a long manufacturing cycle time. Testing of one batch of memory devices requires most of the other devices to be waiting in queue to be tested while some of the memory devices are actually undergoing functional test. One solution would be to get more testers, but this is not practical as it involves even higher cost. The time to deliver a batch of tested memory devices to a customer increases as a result. Another solution is to apply the test from the testers in parallel to the devices under test. The problem with this solution is that the parallel leads occasionally cause good devices to fail because of cross talk among the parallel leads.
Thus there is a problem in finding some way to efficiently test large capacity memory devices without requiring an enormous amount of time on a tester per memory device.