As electronic systems make the transition from 5 to 3 volts, some parts of the system may operate with 3-volt DC power sources, whereas other parts of the system may operate with 5-volt power sources. As one example, 3-volt IC's are needed which can interface with 5-volt busses. Standard complementary MOS (CMOS) and combined bipolar-CMOS (BiCMOS) outputs run into trouble in these applications due to the PMOS devices in their pull-up circuitry.
Three major problems are encountered with such parts when the bus to which they are connected is pulled towards 5 volts: (1) the drain of the PMOS is pulled towards 5 volts and with its back gate fixed at 3 volts (or Vcc&lt;5 volts) results in a forward biased p-n junction from output to Vcc creating very large, undesirable, output-to-Vcc currents; (2) the PMOS device, with its gate held to 3 volts (or Vcc&lt;5 volts), cannot be turned off completely because the drain at the output has become the source, and the resulting gate-to-source voltage is greater than a threshold voltage drop again resulting in large, undesirable output-to-Vcc currents; and (3) some systems allow multiple chips to pull the bus high simultaneously, meaning that the PMOS could possibly be turned on creating, again, a very large positive output-to-Vcc current.