1. Field of the Invention
This invention relates generally to semiconductor memory arrays and semiconductor storage elements and, more particularly, to memory arrays of complementary transistors and complementary transistor memory cells used therein. Most especially, the invention relates to CMOS memory arrays and the CMOS memory cells used in such arrays.
2. Brief Description of the Prior Art
CMOS (Complementary Metal Oxide Semiconductor) circuits have been widely utilized in applications where extremely low power dissipation is a necessity. Various digital logic circuits have been implemented using CMOS technology, including applications requiring random access memory storage cells. Known CMOS random access memory cells have ordinarily utilized at least five or six field effect transistors, forming two cross-coupled CMOS inverters each including a P channel MOSFET and an N channel MOSFET coupled in series and having their gate electrodes connected together. Information is stored in such a cross-coupled circuit as a "0" or a "1" depending on which inverter circuit is conducting and which is non-conducting. In order to obtain an unambiguous indication of the state of such a cross-coupled circuit, a pair of selection MOSFETs have also been required, one coupled to each one of two storage nodes defined by the cross-coupled inverters. Electrodes of the two selection MOSFETs are in turn coupled to decoding circuitry.
In the typical six-transistor cell V.sub.DD and V.sub.SS lines are supplied. However, since adjacent cells can share such power supply lines, each cell could be regarded as requiring a half line for each supply terminal. Each cell is supplied with two column lines and a row line thus causing the cell to employ a total of four lines. In the prior art five transistor cells one line is omitted to result in a three-line structure.
In addition to the line count, the prior art CMOS storage cells utilize a rather large amount of semiconductor chip area. Therefore the density of arrays of such cells has been undesirably low, and consequently the production cost per cell or bit has been rather high. There is a need for a higher density CMOS storage array and cell which requires fewer lines, less semiconductor chip area, and would be less expensive to produce.
It is possible to arrange CMOS cells in an array, each cell of which can be unambiguously sensed without providing extra transistors for this purposes in each cell and fewer lines are required.