The present invention relates to a semiconductor memory circuit, particularly to a flip-flop circuit suitable for logic circuits in high speed operation.
In conventional flip-flop circuits using a high speed GaAs semiconductor device, for example, there has been a device described in IEEE GaAs IC Symposium (1988) pp. 27-30. FIG. 20 shows a flip-flop circuit diagram on the basis of the GaAs semiconductor device described in the above-mentioned thesis. Hereinafter, a filed-effect transistor is referred to as "FET" for the sake of simplicity.
The flip-flop circuit shown in FIG. 20 comprises transfer FETs 2001 and 2002, inverters 2003 and 2004 for holding data, and inverters 2005 and 2006 for buffering. In the flip-flop circuit shown in FIG. 20, when a clock signal CKT is turned to the Low level, the transfer FETs 2001 and 2002 become the cut-off state irrelevant to levels of data signals DT and DB. Because of this, potentials of terminals 2007 and 2008 are held by the inverters 2003 and 2004, unchanging thereof. That is, when the clock signal CKT is turned to the Low level, the flip-flop circuit holds information. Also, turning the clock signal CKT to the High level turns the transfer FETs 2001 and 2002 On to determine the potentials of the terminals 2007 and 2008 of the inverters 2003 and 2004 in response to the data signals DT and DB, respectively, so that information of the flip-flop circuit is rewritten. For example, when the data signal DT is the Low level while the data signal DB is the High level, the potential of the terminal 2007 is brought down to each threshold voltage of the inverters 2003 and 2004 by the transfer FET 2001. When the potential of the terminal 2007 goes down beyond each threshold voltage of the inverters 2003 and 2004, the potential of the terminal 2007 is more decreased by the inverter 2004 to turn to the Low level. Conversely, the potential of the terminal 2008 is brought up to each threshold voltage of the inverters 2003 and 2004 by the transfer FET 2002. When the potential of the terminal 2008 goes up beyond each threshold voltage of the inverters 2003 and 2004 by the transfer FET 2002, the potential of the terminal 2008 is more increased by the inverter 2003 to turn to the high level. At this time, both inverted logical levels of the terminals 2007 and 2008 are outputted from output signals QT and QB by the inverters 2005 and 2006, respectively.
At a trailing edge of the inverted clock signal CKB, a flip-flop circuit receives the data signal DT and transfers a signal to a succeeding stage. Such flip-flop circuit is known as an edge trigger type flip-flop circuit as shown in FIG. 21. Such an edge trigger type flip-flop circuit is also disclosed on "Design and Application MOS/LSI" published by Electronics Digest Co., November 20, 1977, pp. 122-126.