Interconnect technology has become increasingly important for designing integrated circuits (ICs). Interconnects are part of the back-end-of-the-line (BEOL) processing in multi-layered semiconductor devices. On-chip interconnects distribute clock and data signals as well as power and ground signals to various functional blocks in an IC. As the IC designs become smaller and more compact, the size, dimensions, materials, and positioning of the interconnects become increasingly significant factors in overall performance.
IC designers commonly use modeling tools to estimate the electrical performance and parasitic properties of interconnects. Modeling tools perform high-level simulations of interconnect electrical properties and behavior. However, existing interconnect modeling tools do not dynamically predict the behavior of an entire multi-level interconnect system, such as an interconnect stack. As operating frequencies and the number of interconnect layers continue to increase, predicting behavior of interconnects becomes increasingly problematic. Thus, accurate modeling of interconnect behavior has become increasingly important to the process of designing smaller and faster ICs.
Moreover, as interconnects shrink, inductance effects become increasingly significant. However, existing interconnect modeling tools are largely based on resistance-capacitance (RC) parameters.
Existing modeling tools can model the on-chip interconnects of only one technology node (e.g., 45 nm or 32 nm) at a time, because existing modeling tools commonly use actual foundry data with specific interconnect pitches and isolation layer information. If the specific interconnect pitches and material layers are changed, the back end of line (BEOL) model needs to be re-simulated. Hence, a new simulation environment must be defined for each technology node. Moreover, because the existing modeling tools use actual foundry data, they can only provide results late in the development cycle.
Further, existing modeling tools are specific to a foundry's design requirements because they use data of specific foundries. Therefore, a model from foundry A is not necessarily compatible with a model from foundry B.
For the foregoing reasons, there is a need for providing a comprehensive and accurate model for predicting behavior of scaled interconnect stack configurations in advanced technology nodes to simulate on-chip interconnect performance early in the development cycle. In addition, the model should be configurable in the sense that it can predict performance of alternate interconnect stack configurations, such as configurations from a different foundry with, for example, different materials, film stacks and/or k values.