Silicon chips are built on silicon wafers and diced into chips. Known interconnection techniques include wire bonding and so-called flip chip or area array techniques, also known as C4 (controlled collapse chip connection). For flip chips, an array of solder bump interconnects is formed on a wafer before the wafer is diced into a multiplicity of discrete chips. The solder bump interconnects may be formed by plating the back side of the wafer through a resist layer. Plating is chemically dependent and can be difficult to control for complex solders. Plating has been used for high melting point solder (e.g., 97% lead, 3% tin) and can be used for some lead-free solders desirable for environmental reasons (e.g., tin-copper or tin-copper-silver). However control of exact solder composition for some lead free solders can be difficult or impossible to achieve with good solder composition uniformity and repeatability. Injection molded solder (IMS) is preferred for such materials. An injector head is employed over the top of a glass mold with cavities. Molten solder flows into the cavities and a small amount of solder is left behind. When reflowed, the molten solder in the cavities tends to assume spherical shapes, which can be transferred to the wafer by joining the wafer to the mold in a mirror-image fashion.
Additional details of IMS processes are described in, for example, P. A. Gruber et al., “Low-cost wafer bumping,” IBM Journal of Research and Development, Volume 49, Number 4/5, July/September 2005, pp. 621-639, which is incorporated by reference herein.
The integration of multiple flip chips onto a single silicon carrier has recently gained popularity because of the ability of such assemblies to achieve higher system performances. FIG. 1 shows an example of such a multi-chip assembly 100. This assembly comprises two flip chips 110 that are bonded face-down to a single silicon chip carrier 120 via a multiplicity of chip-to-carrier solder bump interconnects 130. The silicon chip carrier, in turn, comprises its own high density wiring 140 and larger C4 connectors 150. Pitches for the chip-to-carrier solder bump interconnects in multi-chip assemblies are presently about 150-200 μm. Nevertheless, pitches as small as 5-10 μm are predicted for the future. As a result, IMS processes compatible with these smaller pitches are presently undergoing intensive research.
This research has determined that, despite the fact that glass molds have been utilized successfully with IMS processes in present-day chip-to-carrier solder bump interconnect pitches, IMS processes using glass molds may not be easily scalable to smaller pitches (e.g., pitches less than about 150 μm). The cavities in a glass mold are typically formed by performing a wet chemical etching process on a glass substrate through small openings in an etch mask. Unfortunately, such processing may have several disadvantages at smaller pitches. Wet chemical etching in glass, for example, may suffer from uniformity issues mold-to-mold and across a given mold. As a result, different cavities on different glass molds, or even on the same glass mold, may have different volumes, which, in turn, results in solder bump interconnects of varying sizes. In addition, wet chemical etching tends to form cavities in glass molds with a non-ideal shape. FIG. 2 shows a cavity 210 in a glass mold 220 with an etch mask 230 still in place. Because of the isotropic nature of the wet chemical etching, a cavity is typically formed with a shallow bowl shape that is 2-3 times as wide as it is deep. This, in turn, may cause transfer issues when attempting to transfer solder bumps from the glass mold to the wafer. In FIG. 3, a solder bump 310 has become offset from the center of its cavity 320 while attempting to transfer it from a glass mold 330 to a bond pad 340 of a wafer 350. With this offset, the transfer is not likely to occur.
Accordingly, it would be desirable to overcome the limitations of the prior art approaches.