The present invention relates generally to the field of semiconductor devices, and more particularly to a system for preventing excess silicon consumption in ultra shallow junctions.
As CMOS devices scaled to the 0.1 um regime, the self-aligned silicide (SALICIDE) contact technology increasingly becomes an integrated part of the ultra-shallow junctions and Si consumption in shallow junctions due to silicide contacts becomes a critical issue. A lower Si consumption is desirable and essential to the formation of ultra-shallow source and drain junctions in deep sub-micron CMOS transistors. Although many efforts to minimize Si consumption during the silicidation process have been reported, little is know about the extra Si consumption induced by the post-silicide processes.
TiSi2, CoSi2 and NiSi are three most important silicide systems for CMOS fabrication. Although TiSi2 is widely used in 0.25 um technology node and above, the line width dependence of phase transformation limits its application for sub-0.25 um technology nodes. NiSi is independent of line width and consumes the least amount of Si for NiSi formation (the mono-silicide is a low resistivity phase as compared with low resistivity disilicide phase for Co and Ti). However, NiSi is also the least stable silicide. Temperatures of back end processing steps after NiSi formation needs to be kept below 600xc2x0 C. to prevent NiSi silicide agglomeration and transformation into the high resistivity thermodynamically stable phase of NiSi2. CoSi2 does not suffer from the line width dependence effect and is stable for the thermal budget used in most CMOS devices. It is currently the dominant silicide used in SALICDE application. The main disadvantage of CoSi2 is that it consumes the most of Si during silicide formation among the three common silicides. For every 1 nm silicide formed, Si consumption for CoSi2 is 1.04 nm, which is more than TiSi2 (0.9 nm) and NiSi (0.82 nm). Si consumption is defined as the distance between the initial silicon interface and the base of the silicide. As the source/drain junctions are getting shallower, Si consumption becomes a limiting factor for the extendibility of CoSi2 process. As a result, there is a need for a system to prevent excess silicon consumption in ultra shallow junctions.
Ti deposition and its subsequent thermal process (rapid thermal annealing (RTA) at temperatures equal to or greater than 615xc2x0 C.) induce excess Si consumption in addition to those consumed during the original silicidation process. Specifically, Ti atoms can destroy the integrity of the original CoSi2 layer by taking Si from Co to form TiSi2. The Si-poor Co atoms then diffuse to the junction to react with more Si to form CoSi2. In this process, more Si is consumed in addition to those consumed in the original silicidation process. The present invention provides a mechanism for reducing excess Si consumption using a process window where Ti layer can be used for reducing interfacial oxide to reduce contact resistance, while preventing the extra Si consumption. When optimal RTA temperature window is used between 485xc2x0 C. and 550xc2x0 C., the interfacial oxide is reduced to form low resistance contacts, while the RTA temperature is low enough to preserve the integrity of the original CoSi2 layer. This temperature window can be extended to as high as less than 615xc2x0 C. and as low as 350xc2x0 C. based on current processes or other temperature above the backend process steps with reduced effectiveness. This process may also be used in Ti/CoSi2/Si multilayer systems.
More specifically, the present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer on top of a native oxide layer above a silicide layer of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer and reduce excess silicon consumption. The temperature range can be greater than 350xc2x0 C. and less than 615xc2x0 C., but is optimal between 485xc2x0 C. to 550xc2x0 C.
Other features and advantages of the present invention will be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.