In industrial process control at manufacturing plants, sensors for sensing physical measurements for the process being run (e.g., pressure, temperature, level, or fluid flow) and instruments performing control output actions (e.g., control valves, actuators, or drive units) for the processing units in industrial plants may be located across a large geographic area. These instruments are generally referred to as “field devices” or “field instruments” (hereafter “field devices”).
Contemporary field devices are generally termed “smart” field devices because they provide valuable asset data besides the basic sensor or control function for a physical parameter. This asset data relates to the diagnostic health of the field device and the process/application with which it is involved.
Smart field devices include an analog to digital converter system (ADCS) providing sampling and quantization for converting a continuous analog sensing signal into a discrete-time and discrete-amplitude signal (i.e. a digital signal). FIG. 1 is a block diagram for a conventional ADCS 100 which can be implemented as a sigma-delta ADC, shown receiving an analog input signal on line 110. ADCS 100 includes an analog low-pass (anti-alias) filter 112 which typically has a stop-band frequency equal to Kfs/2 where K is the oversampling ratio of the modulator and fs is the sample rate at which the ADC 116 operates. The analog input signal on line 110 received by low-pass filter 112 may be output by a sensor which generally provides a transducing function. Low-pass filter 112 implements a portion of a required anti-aliasing function for the ADCS 100. The filtered analog input signal is then provided to the ADC 116 along line 114. The ADC 116 converts the analog signal to a high frequency one-bit digital data stream and also performs noise-shaping on the analog input signal including low-pass filtering the signal of interest and high-pass filtering the quantization noise of the signal. The high frequency data stream output by the ADC 116 is provided on line 120 to digital low pass filter 122.
The clock signal Kfs shown is received by the ADC 116 on line 118. The sampling rate fs of the ADC 116 is based on the sample clock which controls when the ADC 116 converts the instantaneous analog voltage to digital values. The sampling rate is the speed at which the ADC 116 converts the input signal after the signal has passed through the analog input path, to digital values.
Digital low-pass filter 122 also performs the anti-aliasing function on the digital data stream output of ADC 116, and generally has sufficient stop-band attenuation at fs/2 to achieve the desired dynamic range. The digital low-pass filter 122 reduces the shaped quantization noise that resides in the upper frequency band. The output samples of the digital low-pass filter 122 are provided on line 124 to a decimator 126 which provides a data rate reduction of the samples to fs. Decimation can be considered a method by which redundant information contained in the digital samples introduced by the oversampling process is removed.
ADCS such as ADCS 100 shown in FIG. 1 are known to tradeoff noise filtering performance with converter speed of response. This tradeoff is usually fixed in the product hardware/firmware at the lowest level of filtering by low pass (anti-alias) filter 112 in an attempt to satisfy the minimum speed of response and maximum tolerable noise.