1. Field of the Invention
The present invention relates to deep trench isolation structures and, more particularly, to a method of measuring the leakage current of a deep trench isolation structure.
2. Description of the Related Art
A deep trench isolation structure is a well-known semiconductor structure that is used to isolate laterally adjacent regions of a substrate, epitaxial layer, or well from each other. The structure is commonly formed by first etching a deep trench in the substrate or through an epitaxial layer into the substrate. Once formed, the trench is typically lined with oxide, and then filled with polysilicon. (Other processing, such as channel stop implants, is often associated with the formation of a trench.)
FIG. 1 shows a cross-sectional diagram that illustrates an example of a prior-art semiconductor structure 100 that utilizes deep trench isolation. As shown in FIG. 1, semiconductor structure 100 includes a p− substrate 110, and an n+ buried layer 112 that is formed in p− substrate 110. In addition, structure 100 includes an n− well 114 that is formed in p− substrate 110 to extend down from the top surface of p− substrate 100 to n+ buried layer 112.
As further shown in FIG. 1, semiconductor structure 100 includes a lateral region 116, and a deep trench isolation structure 118 that is formed in p− substrate 110 to isolate n+ buried layer 112 and n− well 114 from lateral region 116. Deep trench isolation structure 118 includes a trench 120, a layer of oxide 122 that contacts p− substrate 110, n+ buried layer 112 and n− well 114, and a polysilicon region 124 that fills up trench 120.
In addition, semiconductor structure 100 includes a p-type region 130 that is formed in n− well 114, a spaced-apart n+ region 132 that is formed in n− well 114, and a p+ region 134 that is formed in p− substrate 110. Further, semiconductor structure 100 has a top surface 136.
In operation, semiconductor structure 100 can represent the elements of a number of devices such as, for example, a MOS transistor (e.g., HVPMOS, isolated NMOS, LDMOS arrays) a bipolar transistor (e.g., npn, npn arrays), and a resistor (e.g., p-well, p-base). With a MOS device, p-type region 130 represents a p+ source region, n+ region 132 represents a contact region for n− well 114, and p+ region 134 represents the contact region for p− substrate 110.
Although not shown in FIG. 1, a MOS device also has a p+ drain region that is formed in n− well 114, and a channel region that is defined between source region 130 and the drain region. In addition, a layer of oxide is formed over the channel region, and a gate is formed on the layer of oxide over the channel region.
With a bipolar device, p-type region 130 represents a p− base region, n+ region 132 represents a collector contact region for n− well 114, and p+ region 134 represents the contact region for p− substrate 110. Although not shown in FIG. 1, an n+ emitter region is also formed in p− base region 130. With a resistor, p-type region 130 represents the resistor, n+ region 132 represents a contact region for n− well 114, and p+ region 134 represents the contact region for p− substrate 110.
One problem with semiconductor structure 100 is that semiconductor structure 100 is subject to a significant trench leakage current that results from deep trench isolation structure 118. When poly-filled deep trench isolation structures are utilized, the polysilicon region, such as polysilicon region 124, has a potential which is defined by the voltage on the adjacent regions and the capacitive coupling of oxide layer 122.
In some cases, the potential can be sufficient to form a parasitic channel region adjacent to the deep trench isolation structures which, in turn, provides a pathway for the trench leakage current. As shown in FIG. 1, when a channel region is present, a trench leakage current IL can flow from p-type region 130 to p− substrate 110, or from p− substrate 110 to p-type region 130, along the side walls of trench isolation structure 118, depending on the relative voltages on p− substrate 110 and p-type region 130.
The leakage current IL represents different leakage currents (or components of it) in actual devices. For example, in MOS and LDMOS devices, the leakage can appear as a sub-threshold drain-to-source leakage current Idss0. In bipolar devices, the leakage may appear as a base-to-substrate leakage current Ibs, or a collector-to-base leakage current Icbo. In arrays, the leakage can appear as a yield issue if the detected level is high.
Various steps can be taken to reduce the trench leakage current IL. For example, in a low-voltage bipolar example, the trench leakage current IL can be reduced by ensuring that p− base region 130 lies a sufficient distance X away from oxide layer 122. In a high-voltage lateral DMOS (LDMOS) example, the trench leakage current IL can be reduced by placing an n+ guard ring between oxide layer 122 and p-type region 130. In a low-voltage bipolar example, the trench leakage current IL can be reduced by the insertion of a highly-doped guard ring in between the trench and p-type region 130.
Manufactured parts which have the elements of semiconductor structure 100 can be tested to ensure that the trench leakage current IL falls within specified limits. One standard bipolar test which is often used as a measure of the trench leakage current IL is a bipolar breakdown voltage base-substrate-open (BVbso) test, which measures the current across the junction between p− substrate 110 and n+ buried layer 112.
The following Table 1 illustrates an example of a conventional bipolar BVbso test, with the rows representing the successive steps in the test.
TABLE 1Test Voltage onTest Voltage onTest Voltage onp-type region 130n+ region 132p+ region 134VbiasFloat0.0Vbias −1Float0.0Vbias −2Float0.0. . .. . .. . .Vbias −BDFloat0.0
As shown in the first row of Table 1, p− substrate 110 is grounded via p+ region 134, n+ buried layer 112 and n− well 114 (the substrate) float via n+ region 132 which is open (not connected to a voltage source), and a positive voltage Vbias is applied to p-type region 130 (the base).
After the voltages have been applied, a current is measured at p-type region 130. Following this, the voltage applied to p-type region 130 is progressively lowered and the current measured until breakdown or punchthrough occurs (at Vbias-BD), at which time the magnitude of the current measured at p-type region 130 increases substantially.
One problem with the bipolar BVbso test, however, is that the bipolar BVbso test is a poor measure of the trench leakage current, and tends to produce incorrect results which are more optimistic than is the actual case. Thus, there is a need for a method of measuring the trench leakage current of a deep trench isolation structure that provides more accurate results.