1. Field of the Invention
The present invention relates to a method of driving a ferroelectric liquid crystal displaying panel. More specifically, the present invention relates to a method of driving a ferroelectric liquid crystal displaying panel having a plurality of scanning electrodes arranged parallel to each other, signal electrodes arranged parallel to each other intersecting the plurality of scanning electrodes and a ferroelectric liquid crystal sealed between the scanning electrodes and the signal electrodes.
2. Description of the Background Art
FIG. 6 is a cross sectional view of a conventional simple matrix panel with a sealed ferroelectric liquid crystal. Referring to FIG. 6, two deflecting plates (or polarizers) 1 are provided at the top and bottom, arranged in the relation of opposing polarization characteristics with each other. A glass substrate 2 is provided on the deflecting plate 1. Further, on the glass substrate 2 the scanning electrode 3 or the signal electrode 4 is formed. An insulating film 5 is formed over the scanning electrodes 3 and the signal electrodes 4 to protect the ferroelectric liquid crystal 8. An aligning film 6 is provided on the insulating film 5 which is subjected to a process such as rubbing so as to align the molecules of the ferroelectric liquid crystal 8. Sealing member 7 is provided for preventing the ferroelectric crystal liquid in the cell from leaking outward.
FIG. 7 shows the structure of the electrodes in the simple matrix panel sealing ferroelectric crystal liquid shown in FIG. 6. The example shown in FIG. 7 is a simple matrix panel comprising 4 scanning electrodes 3 and 4 signal electrodes 4, which will be referred to as a 4.times.4 simple matrix panel (the former numeral indicating the number of the scanning electrodes 3 and the latter numeral indicating the number of the signal electrodes 4). The scanning electrodes 3 are labeled as L.sub.1, L.sub.2, L.sub.3 and L.sub.4 respectively, from the uppermost one, and the signal electrodes are labeled, from the left side, as S.sub.1, S.sub.2, S.sub.3 and S.sub.4, respectively. The intersection of the scanning electrode L.sub.i and the signal electrode S.sub.j is represented as a pixel A.sub.ij (i and j are positive integers).
FIG. 8 shows a 16.times.16 simple matrix panel displaying a letter "A". FIGS. 9a-9h are diagrams of voltage waveforms applied to the scanning electrodes when the panel of FIG. 8 is driven. FIGS. 10a-10c are diagrams of voltage waveforms applied to the signal electrodes 4 for driving the panel shown in FIG. 8. FIGS. 11A (1-4) and 11B (1-4) are diagrams of voltage waveforms applied to the pixels when the panel shown in FIG. 8 is driven.
The operation for driving the panel shown in FIG. 8 in accordance with the conventional method of driving will be described in the following. The voltage shown in FIG. 9a-h is applied to each scanning electrode Li by the scanning driver 10(a-e), and the voltage shown in FIG. 10 is applied to the signal electrode S.sub.j by the signal driver 9. Then, the voltages such as shown in FIGS. 11A 1-4 and 11B 1-4 are applied to the pixel A.sub.ij, so that the pixel A.sub.ij is set in a bright or dark memory state, thereby displaying the character "A".
The ferroelectric liquid crystal has two memory states, one of which is referred to as the dark memory state while the other is referred to as the bright memory state. In the following, the bright memory state and the dark memory state maybe interchanged. More specifically, as to the scanning electrodes L.sub.i, during the time period -t.sub.0 to 0, the voltage C (the voltage V.sub.0, and then the voltage -V.sub.0) is applied to the scanning electrodes L.sub.1 to L.sub.4 as shown in FIG. 9 (a) to (d), while the voltage G (voltage -2V.sub.0 /3, and then the voltage 2V.sub.0 /3) is applied to the scanning electrodes L.sub.5 to L.sub.9 as shown in FIG. 9 (e) to (h). During the time period 0 to t.sub.0, the voltage A (voltage -V.sub.0 and then voltage V.sub.0) is applied to the scanning electrode L.sub.1 and the voltage B (voltage 2V.sub.0 /3 and then the voltage -2V.sub.0 /3) is applied to the remaining scanning electrodes.
During the time t.sub.0 to 2t.sub.0, the voltage A is applied to the scanning electrode L.sub.2 and the voltage B is applied to the remaining scanning electrodes. During the time period 2t.sub.0 to 3t.sub.0, the voltage A is applied to the scanning electrode L.sub.3 and the voltage B is applied to the remaining scanning electrodes. During the time period 3t.sub.0 to 4t.sub.0, the voltage A is applied to the scanning electrode L.sub.4 and the voltage B is applied to the remaining scanning electrodes. Then, during the time 4t.sub.0 to 5t.sub.0, the voltage C is applied to the scanning electrodes L.sub.5 to L.sub.8 and the voltage G is applied to the scanning electrode L.sub.9 and L.sub.1 to L.sub.4. Thereafter, the similar operation is repeated.
As to the signal electrodes S.sub.j, during the time period -t.sub.0 to 0, the voltage F (voltage -V.sub.0 and then voltage V.sub.0) is applied to all the signal electrodes S.sub.j as shown in FIG. 10(a-e). During the time period 0 to 4t.sub.0, the voltage D (voltage V.sub.0 and then the voltage -V.sub.0) or the voltage E (voltage V.sub.0 /3 and then voltage -V.sub.0 /3) is applied to each of the signal electrodes S.sub.j. During the time period 5t.sub.0 to 6t.sub.0, the voltage F is applied to all the signal electrodes S.sub.j. Thereafter, the same operation is repeated.
By applying the voltages to the scanning electrodes L.sub.1 to L.sub.4 and L.sub.5 to L.sub.9 and to the signal electrodes S.sub.j in the above described manner, the voltages such as shown in FIGS. 11A (1-4) and 11B (1-4) are applied to the pixels A.sub.ij. More specifically, the voltage applied to the pixel is equal to the voltage applied to the scanning electrode Li minus the voltage applied to the signal electrode S.sub.j. For example, the voltage shown in FIG. 11A (a) is applied to the pixel A.sub.22. Namely, the voltage CF is applied to the pixels A.sub.1j to A.sub.4j including the pixel A.sub.22 during the time period -t.sub.0 to 0. By this voltage CF, the voltage 2V.sub.0 and then -2V.sub.0 are applied to the pixels including the pixel A.sub.22, which are set in the dark memory state.
The ferroelectric liquid crystal sealed in this panel has a nature to be set in the dark memory state when the voltage -2V.sub.0 is applied for t.sub.0 /2. When the voltage A is supplied to the scanning electrode L.sub.2 and the voltage E is applied to the signal electrode S.sub.2 during the time period t.sub.0 to 2t.sub.0, then the voltage AE is applied to the pixel A.sub.22, keeping the dark memory state. The ferroelectric liquid crystal sealed in this panel has a nature that it is not set to the bright memory state even if the voltage 4V.sub.0 /3 is applied for t.sub.0 /2. The voltage shown in FIG. 11A (d) is applied to the pixel A.sub.2c. Namely, the voltage CF is applied to the pixels A.sub.1a to A.sub.4j including the pixel A.sub.2c during the time t.sub.0 to 0. For application of voltage CF, the voltage 2V.sub.0 and then -2V.sub.0 are applied to the pixels including the pixel A.sub.2c, so that these pixels are set to the dark memory state. If the voltage A is applied to the scanning electrode L.sub.2 and the voltage D is applied to the signal electrode S.sub.c during t.sub.0 to 2t.sub.0, then the voltage AD is applied, so that the bright memory state is realized. The ferroelectric liquid crystal introduced in this panel has a nature that it is set to the bright memory state when the voltage 2V.sub.0 is applied for t.sub.0 /2.
The pixels A.sub.22 and A.sub.2c rewritten in this manner are kept in the bright or dark memory state until the voltage CF is applied the next time as shown in FIG. 11A (1) and (4).
Since the example shown in FIG. 8 is a 16.times.16 simple matrix panel, the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3, each set including 4 scanning electrodes 3. Generally, the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3, each set including 2 to 16 electrodes. When we represent the minimum panel time width necessary for rewriting the memory state of a ferroelectric liquid crystal with a certain applied voltage as t.sub.m (sec), then the time T.sub.a necessary for rewriting all pixels in the M.times.N simple matrix panel will be as follows, when the erasing voltage C and the non-selection voltage G are applied to a set of scanning electrodes 3 including 16 electrodes.
With a minimum integer K satisfying the condition of EQU K.gtoreq.M.div.16 (1)
the time Ta will be EQU T.sub.a =(M+K).times.2 t.sub.m (sec) (2)
Assuming that M is a multiple of 16, then, EQU T.sub.a =(17M.div.16).times.2t.sub.m (sec) (3)
Consequently, the scanning time per 1 scanning electrode provided by dividing the above value by the number of scanning electrodes m is about 2.1.times.t.sub.m (sec).
FIG. 12 is a block diagram for the display of output signal of a conventional personal computer. FIG. 13 is a diagram of waveforms showing the output signal of the personal computer and the input signal of the signal driver shown in FIG. 12.
By using the above described method of driving, the scanning time per scanning electrode can be made considerably close to 2t.sub.m (sec). However, a timing converting circuit 12 must be provided between the personal computer 11 and the control circuit 13 shown in FIG. 12. The reason for this is that although the output signal from the personal computer 11 is transmitted to the scanning electrodes L.sub.1, L.sub.2, L.sub.3, L.sub.4, L.sub.5, L.sub.6 and so on as shown in FIG. 13 (a), the actual signal to be applied to the signal driver 9 must include a signal corresponding to the timing of applying the voltage F to the signal electrode S.sub.j as shown in FIG. 13 (b). Therefore, the timing of the output signals of the personal computer 11 must be converted, so that they can be applied to the signal driver 9.