In modern memory systems, memory access requests are typically conveyed in three types of signals: command signals that indicate the nature of the access (e.g., read, write, masked write, etc.); address signals that specify memory locations to be accessed; and control signals that, in general, enable a subset of memory devices in a memory subsystem to receive the command and address signals. The memory subsystem itself is often organized as one or more ranks of memory devices (or chips), each rank consisting of memory devices that are to respond in parallel to a given memory access request, for example, by outputting read data or storing write data. In a typical arrangement, a dedicated set of control signal lines is provided for each rank of memory devices, while command and address signals are provided via one or more sets of signal lines (command/address signal lines) that are coupled in common to all the ranks in the memory subsystem. One result of this signaling arrangement is that the capacitive loading of command/address signal lines may vary depending on the number of memory ranks in the memory subsystem (which number may be expanded by addition or replacement of memory modules) and, for example, in a system having more than one memory rank, will be different from the loading of the control signal lines, resulting in skew between the relative arrival times of control signals and command/address signals. While tolerated in past systems, the skew between request signals (“request skew”) consumes a progressively larger portion of the signal eye (i.e., signal valid interval) as signaling rates increase, thus shrinking timing margins and potentially limiting maximum request signaling rates.