As one of most rapidly developing fields in a current semiconductor industry, a semiconductor memory is always a research focus in the industry. Particularly, since various consumer electronic products are widely used today, a requirement for a high performance semiconductor memory is ever-increasing. Among them, a flash memory has occupied a very large share in today's memory market due to its advantages such as a compatibility with a MOS process, an excellent storage performance and etc.
The flash memory in the current market is mainly classified into two types, according to a manner for storing charges. One of the two types is a floating gate flash memory, in which charges are stored in a conductor such as a polysilicon; and the other is a discrete-trap flash memory, in which charges are stored in a silicon nitride trap layer.
In the floating gate flash memory, the stored charges are continuously distributed in the polysilicon floating gate. If there is a leakage path existed in a tunneling oxide layer, all electrons stored in the floating gate may be leaked out through the path. Therefore, in a case that the oxide layer is usually thin in a small size memory, the flash memory having such structure may be faced with a serious problem in terms of reliability.
Meanwhile, in the discrete-trap flash memory, since the charges stored therein are not continuous but localized, when a leakage path occurs in a certain region, only charges located at the path are leaked out, while charges in other regions may be maintained well. Thus, the reliability of the entire memory device is improved to some extent. Particularly, in the case of a small size thin oxide layer, such improvemnet of the reliability is more significant.
In addition to the improvement on the reliability, considering that the charges are not continuously stored in the silicon nitride trap layer, the charges may be stored at both ends of the trap layer to achieve a function of two-bit storage so that a storage density may be increased. However, as a continuous shrink of a process node, an effective channel length of the conventional discrete trap flash memory is increasingly reduced. Since the charges stored at both ends of the channel are close to each other, a very serious problem of crosstalk is existed. To this end, devices having new structures have been proposed to solve the problem. For example, a flash memory with a splitting trench gate disclosed in a Chinese invention patent titled “flash memory having splitting trench gate and method for fabricating the same” (ZL200710105964.2) is one of such devices. The flash memory having the splitting trench gate is a planar structure, as shown in FIG. 1. In this structure, a tunneling oxide layer 206, a silicon nitride trap layer 205, a blocking oxide layer 204 and a polysilicon control gate 203 (or a metal gate) are sequentially disposed over a channel. Two trenches having an identical structure each is disposed between a source 209 and the channel 202 and between a drain 210 and the channel 202, respectively. One side of each of the trenches is contacted with the channel, and the other side of each of the trenches is contacted with the source or the drain, thus the splitting trench gate structure is formed in the channel. The entire channel of the device is formed by a planar channel in middle and two non-planar channels corresponding to the trenches. The trenches and the channel are completely covered by the control gate and the gate stack structure. The control gate has two protruding portions corresponding to the trenches. Under the same number of process nodes, the effective channel length is increased by this device, and the problem of crosstalk between two storage bits is effectively solved.