1. Field of the Invention
The present invention relates to a memory device, and a method of manufacturing the same. More particularly, the present invention relates to a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device including the same, and a reading circuit for the same.
2. Description of the Related Art
Nonvolatile memory devices include read only memory (ROM), which can be categorized as a mask ROM, which is programmed during manufacture, an electrically erasable and programmable read only memory (EEPROM), and others. A flash memory, which is also a nonvolatile memory device, is a modification of a conventional EEPROM, and includes a cell array in which erasing is performed in block units, sector units, or chip units and programming is performed in bit units.
The architecture of a flash memory can be divided into a NOR type and a NAND type. Cells of a NOR type flash memory are arrayed in parallel between a bit line and a ground line. Cells of a NAND type flash memory are arrayed in series.
In more detail, a NOR type flash memory can be classified into an AND type, a DINOR type, and a virtual ground array (VGA) type. In a NOR type flash memory, since address decoding required for reading and programming is similar to that for a DRAM, a peripheral circuit may be simple and access time may be shortened. On the other hand, each and every cell requires a contact electrode of a bit line, thus increasing cell area and lengthening time for erasing and programming as compared with a NAND type flash memory.
In a NAND type flash memory, erasing and programming are faster than in a NOR type flash memory. However, reading speed may be relatively slow, since a pertinent block must be selected before being read and serial connection of cells leads to an increase in operating resistance.
A conventional flash memory is typically an N-type memory that can store only one bit per cell on the principle that the threshold voltage of a channel depends upon injection or emission of electrons into or from nitride. That is, the number of bits to be stored per cell may be restricted. Also, since the conventional flash memory operates in such a manner that previous data may be entirely erased and new data may be rewritten irrespective of previous memory state, resulting in significant power dissipation.
Particularly, in a read operation, data “0” or “1” may be detected depending on a current difference measured at a reading voltage using a current displacement according to a shift in threshold voltage. If the number of bits per cell is two or more, a current difference measured at the reading voltage may be high and a large current may be supplied, thus dissipating a large amount of power. Thus, a continuous bit scale-up may be difficult.
To overcome this drawback, data may be read using a method of measuring a threshold voltage when reaching a reference current. However, this method is a current detecting method and typically requires complicated circuit construction including comparators and sense amplifiers.