The present invention relates to non-volatile memory, and, more specifically, to intra-block wear leveling of non-volatile memory to increase the endurance of the memory.
Solid-state, non-volatile memory (for example, flash memory or EPROM), whether embodied in stand-alone devices (solid-state devices or “SSDs”) or as a portion of other circuitry (e.g., processor, volatile memory, etc.), is faced with certain challenges. One is endurance, which is generally defined as the maximum number of write/erase cycles that can be performed on each memory cell before the physical properties of the cell wear out and the cell can then no longer be programmed or erased. Another challenge is data retention, which generally refers to the maximum time period during which the stored data can be read out, possibly with correctable errors. Endurance is typically specified assuming a ten-year data retention period.
Wear leveling is a technique that is widely used to deal with the problem of memory cell wear-out in non-volatile memory. Its goal is to increase memory endurance by distributing program and erase cycles more uniformly throughout the entire non-volatile memory. On the other hand, error-correction codes (“ECC”) are used for data retention purposes, specifically, to protect the stored data from corruption (i.e., random bit errors). One wear leveling technique is based on a counter of write-erase cycles per block. This technique aims to balance write/erase cycles among the memory blocks such that no block receives excessive write/erase cycles.