The present invention relates generally to the testing of system designs by software simulation, and more particularly, to a verification process incorporating stimuli generated by scripting and modelling languages.
Integrated circuit development generally includes a design phase and a verification phase for determining whether a design works as expected. The verification phase typically uses a software simulator (or testbench) whose functions include accepting software written in a hardware description language such as SystemVerilog, which models a circuit design. The model is used to simulate the response of the design to stimuli that are applied by a test case. The results are observed and used to debug the design. A test case is generally a set of test conditions and characterised by a known input and an expected output. The most time consuming part is creating the tests and then modifying them when the design changes. SystemVerilog is currently a popular language for a testbench and test case. Scripting languages such as TCL (Tool Command Language), and/or modelling languages can be useful for test case emulation.
Hence it would be advantageous to be able to incorporate verification components that have been coded by a scripting language into a SystemVerilog testbench.