This application is related to the following co-pending, commonly assigned U.S. patent applications: entitled xe2x80x9cStatic Pass Transistor Logic with Transistors with Multiple Vertical Gates,xe2x80x9d Ser. No. 09/580,901; and xe2x80x9cVertical Gate Transistors in Pass Transistor Logic Decode Circuits,xe2x80x9d Ser. No. 09/580,860, both filed on May 30, 2000 and which disclosures are herein incorporated by reference. This application is further related to the following co-pending, commonly assigned U.S. patent application: xe2x80x9cVertical Gate Transistors in Pass Transistor Programmable Logic Arrays,xe2x80x9d Ser. No. 09/643,296, which is filed on even date herewith and also incorporated herein by reference.
This invention relates generally to integrated circuits and in particular to double pass transistor logic with vertical gate transistors.
Many integrated circuits include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the integrated circuit is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the integrated circuit. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given integrated circuit is dependent upon the number of logical inputs which is, in turn, dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the programmable logic array.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative article by L. A. Glasser and D. W. Dobberpuhl, entitled xe2x80x9cThe design and analysis of VLSI circuits,xe2x80x9d Addison-Wesley, Reading, Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Articles which outline such use include articles by J. M. Rabaey, entitled xe2x80x9cDigital Integrated Circuits; A design perspective,xe2x80x9d Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled xe2x80x9cHigh-speed design styles leverage IBM technology prowess,xe2x80x9d MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled xe2x80x9cA 0.5V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic,xe2x80x9d Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled xe2x80x9cTop-down pass-transistor logic design,xe2x80x9d IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled xe2x80x9cA 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logicxe2x80x9d, Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 Oct., vol. 2, pp. 1037-40, 1996.
In another approach, double pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled xe2x80x9cCMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design,xe2x80x9d 13th National Radio Science Conf., Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled xe2x80x9cDifferential and pass-transistor CMOS logic for high performance systems,xe2x80x9d Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., xe2x80x9cPass-transistor CMOS collaborated logic: the best of both worlds,xe2x80x9d Dig. Symp. On VLSI Circuits, Kyoto, Japan, June 12-14, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled xe2x80x9cLow-power logic styles: CMOS versus pass transistor logic,xe2x80x9d IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., xe2x80x9cPerformance comparison of differential static CMOS circuit topologies in SOI technology,xe2x80x9d Proc. IEEE Int. SOI Conference, October 5-8, FL, pp. 123-4, 1998.
Thus, static pass transistor CMOS logic circuits, as shown in FIG. 5A, have been used in CMOS technology and integrated circuits. The main problem with static pass transistor logic circuits is the threshold voltage drop at the input across a pass transistor. If as shown in FIG. 5A the input is high at VDD then if the pass transistor is a normal enhancement mode device the input voltage will rise only to VDDxe2x88x92VTN, where VTN is the threshold voltage of the NMOS transistor. Worse still, it will, in theory, take an infinite amount of time to reach this voltage since the NMOS pass transistor has a final state which has infinite resistance. If, as shown in FIG. 5B, the output of one pass transistor is used to drive the gate of another transistor then the capacitor at the input to the inverter will charge only to VDDxe2x88x922 VTN. This is, in particular, unacceptable in low power supply circuits and this possibility must be precluded by design rules.
Various techniques have been used to overcome some of the threshold voltage drop problem. One is the use of level restore circuits. The level restore circuits such as shown in FIG. 6A and FIG. 6B are essentially equivalent. If the inverter input is switching high then the output is going low, this low output is used in a feedback circuit to drive the gate of the extra PMOS device low and pull the input up. This is a positive feedback circuit which tends to latch the input high regardless of how slowly the original input signal was rising. In this manner the level restore circuits overcome the threshold voltage drop at the input in pass transistor logic circuits.
Another technique is the development of differential pass transistor logic, as shown in FIGS. 7A and 8A. In differential pass transistor logic both NMOS and PMOS transistors are used as pass transistors and the threshold voltage drop does not occur, one of these transistor is always on in a high conductivity state. FIGS. 9A and 9B illustrate conventional application of differential pass transistor logic in the form of an XOR logic gate and a one bit full adder, sum circuit, respectively.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on programmable logic arrays by the limits of the minimum lithographic feature size and the deficit in the available chip surface space in combination with the threshold voltage drop issue.
An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: xe2x80x9cProgrammable Logic Arrays with Transistors with Vertical Gates,xe2x80x9d Ser. No. 09/583,584, xe2x80x9cHorizontal Memory Devices with Vertical Gates,xe2x80x9d Ser. No. 09/584,566, and xe2x80x9cProgrammable Memory Decode Circuits with Vertical Gates,xe2x80x9d Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having vertical floating gates and vertical control gates above a horizontal enhancement mode channel region. In those disclosures one or more of the vertical floating gates is charged by the application of potentials to an adjacent vertical gate. The devices of those disclosures can be used as flash memory, EAPROM, EEPROM devices, programmable memory address and decode circuits, and/or programmable logic arrays. Those applications, however, are not framed to address overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space for purposes of double pass transistor logic in other integrated circuit applications.
Therefore, there is a need in the art to provide improved double pass transistor logic in a wide range of integrated circuit applications which do address and resolve the above mentioned problems.
The above mentioned problems with double pass transistor logic in various integrated circuit applications and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Circuits and methods are provided for double pass transistor logic with vertical transistors in a multitude of additional integrated circuit applications. In the present invention, multiple vertical gates per a single MOSFET serve as multiple logic inputs. The multiple vertical gates are edge defined such that only a single transistor is required for multiple logic inputs. Thus, a minimal surface area is required for each logic input. Further, the invention incorporates double-pass pass and complementary double-pass transistor logic (DPL) in order to provide more noise immunity than pass and complementary pass transistor logic (CPL). Accordingly, the present invention obviates the need for level restore circuits. In circuits with very low power supply voltages it is a good choice in implementing logic functions. According to the teachings of the present invention, the compatibility of DPL with the novel array type structure of novel transistors with multiple vertical gates should allow a very efficient realization of logic circuits and functions.
In one embodiment of the present invention, an integrated circuit is provided. The integrated circuit includes a number of input lines for receiving input signals and at least one output line for providing output signals. One or more arrays of transistors are coupled between the number of input lines and the at least one output line. According to the teachings of the present invention, each transistor includes source region and a drain region in a horizontal substrate. A depletion mode channel region separates the source and the drain regions. A number of vertical gates located above different portions of the depletion mode channel region. At least one of the vertical gates is located above a first portion of the depletion mode channel region and is separated from the channel region by a first thickness insulator material. Further at least one of the vertical gates is located above a second portion of the channel region and is separated from the channel region by a second thickness insulator material. The number of vertical gates each have a horizontal width which has sub-lithographic dimensions. In the invention, the number of vertical gates are independently coupled to a number of gate input lines. Thus, the number of vertical gates provide logic inputs such that a minimal area in each logic cell is used for each logic input.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.