1. Field of the Invention
The present invention relates to a method of controlling a pipeline Analog-to-Digital Converter (ADC), and more particularly, to a pipeline ADC without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling a point in time for sampling to minimize sampling mismatch occurring in the pipeline ADC.
This work was supported by the IT R&D program of MIC/IITA. [2006-S-006-02, Components/Module technology for Ubiquitous Terminals].
2. Discussion of Related Art
Recently, the speed of ADC has increased in systems requiring high-speed information processes and in apparatuses for recording and replaying optical-discs, such as compact discs (CDs) and digital versatile discs (DVDs). Since a full flash ADC has a resolution limit and consumes a lot of power due to its structure, it is difficult to implement a high resolution at high speed with low power. Therefore, a pipeline ADC that can implement a high resolution at high speed is preferred in many application fields.
FIG. 1 is a block diagram of a conventional pipeline ADC.
Referring to FIG. 1, the pipeline ADC comprises a front-end SHA 110, a plurality of stages 120, a flash ADC 130 and a digital correction circuit 140. Each of the stages 120 comprises a Multiplying Digital-to-Analog Converter (MDAC) 121 and a flash ADC 122. Here, the flash ADC 122 serves as an ADC that quantizes and converts an analog input signal into an N-bit digital code. The MDAC 121 serves as a residual signal generator that converts the digital code converted by the flash ADC 122 back into an analog value, subtracts the converted analog value from the input signal, amplifies the result to generate a residual signal, and transfers the generated residual signal to a next stage. Therefore, it is possible to repeat the same analog-to-digital conversion process using the transferred residual signal in the next stage. The final stage does not need to transfer a residual signal to the next stage and thus consists of the flash ADC 130 alone. For example, an analog input signal Vin may be converted into N-bit digital codes by the K stages 120 and the flash ADC 130, and each of the N-bit digital codes may be finally converted into a (K(N−1)+N)-bit digital signal by the digital correction circuit 140.
In the analog-to-digital conversion process of each stage, the front-end SHA 10 positioned at the fore part of the pipeline ADC samples an input signal during a half of an operating clock, holds the sampled input signal during the other half, and simultaneously supplies the sampled input signal to the MDAC 121 and the flash ADC 122 constituting a first stage, thereby serving to minimize sampling mismatch that may occur between the MDAC 121 and the flash ADC 122.
In spite of such an advantage, with the increase in the operating speed and the resolution of the ADC, the front-end SHA 110 comprising an amplifier and a plurality of capacitors consumes a lot of power due to the bandwidth of the amplifier and a limit in direct current (DC) gain, and occupies a large area due to large capacitors. In addition, since the front-end SHA 110 is positioned at the fore part of the pipeline ADC, the noise and the non-linear characteristic of the capacitors and the amplifier included in the front-end SHA 110 may affect the entire ADC and may deteriorate the performance of the ADC. To solve this problem, a pipeline ADC without the front-end SHA 110 has been suggested.
FIG. 2 is a block diagram of a pipeline ADC without a front-end SHA.
Referring to FIG. 2, the pipeline ADC without a front-end SHA comprises a plurality of stages 210, a flash ADC 220 and a digital correction circuit 230. Like the conventional pipeline ADC, each of the stages 210 comprises an MDAC 211 and a flash ADC 212. In other words, the pipeline ADC without a front-end SHA has the same structure as the conventional pipeline ADC shown in FIG. 1, except that the SHA 110 at an input end is removed. However, as mentioned above, a front-end SHA serves to minimize sampling mismatch between an MDAC and a flash ADC constituting a first stage. Thus, the structure of the pipeline ADC without a front-end SHA may cause serious sampling mismatch and drastically deteriorate the performance of the pipeline ADC.
FIG. 3A is a timing diagram showing a conventional stage-operating clock, and FIG. 3B is a circuit diagram of a stage operating according to the conventional clock.
Referring to FIGS. 3A and 3B, an analog input signal Vin is directly applied to an MDAC 310 and a flash ADC 320 constituting a first stage. The MDAC 310 samples the analog input signal Vin that is applied when a Q2P clock goes low, and stores the sampled signal in a capacitor CMS 311.
At the same time, the analog input signal Vin applied to the flash ADC 320 is processed by a preamp 321 and a latch 322 constituting the flash ADC 320. The preamp 321 compares and amplifies the analog input signal Vin with a reference voltage REF1 sampled in a capacitor CFS 323 while a previous Q1 clock is high. Subsequently, the latch 322 samples a preamp output value when a Q2PB clock, which has a phase difference of 180 degrees with respect to the Q2P clock, goes high, i.e., when the Q2P clock goes low, and determines a digital code corresponding to the analog input signal Vin. The digital code determined by the latch 322 is transferred to the MDAC 310 when a Q1 clock is high, and the MDAC 310 generates a residual signal using the digital code and transfers the generated residual signal to a next stage.
In this operation, the digital code transferred from the latch 322 to the MDAC 310 is converted from the preamp output signal at a point in time when the Q2P clock changes. Thus, the digital code substantially transferred to the MDAC 310 is converted from the analog input signal Vin at the point in time calculated by subtracting a preamp delay time Δ·τ, caused by the preamp 321, from the point in time when the Q2P clock changes.
That is, the MDAC 310 samples the analog input signal Vin at the point in time when the Q2P clock changes, and the flash ADC 320 samples the analog input signal Vin at the point in time (Q2P−Δ·τ) preceding the point in time when the Q2P clock changes by the preamp delay time Δ·τ and transfers a processed result to the MDAC 310. Therefore, the values of the analog input signal Vin sampled by the MDAC 310 and the flash ADC 320 may be different from each other. A sampling aperture error Ve due to sampling mismatch between the MDAC 310 and the flash ADC 320 may be expressed by a formula given below, and the sampling aperture error Ve increases with increase in an input frequency fin.Ve=2π·finVREF(Δ·τ)  [Formula 1]
Here, Δ·τ denotes a preamp delay time, fin denotes an input frequency, and VREF denotes an input voltage magnitude. Such an aperture error may have influence on determining a residual signal to be transferred from an MDAC to the next stage, and thereby may seriously deteriorate the performance of an entire ADC.