Advancement in the integrated circuit technology has lead to vast improvements in the speeds of integrated circuits. Increasing integrated circuit speed has resulted in faster rise and fall times of output voltages in response to new inputs. Similarly, the fast rise and fall times of the output voltages have resulted in abrupt transitions of output current.
While faster speeds are very desirable, the abrupt transitions of output current create serious problems. The drive capability of circuits is measured by the DC output current which can be sourced or sunk at specific voltages. The circuit must meet this current under worst-case or weak processing conditions, which in CMOS are low supply voltage, high temperature, or weak device models. A problem with standard circuit designs is that excessive DI/DT is generated under best-case or strong conditions, which in CMOS are high supply voltage, low temperature, and strong device models. Furthermore, under best-case processing conditions, levels of current provided by the circuit commonly are substantially higher than minimum levels required by product specifications.
Differences between weak process circuits and strong process circuits in levels of current and in DI/DT have resulted in timing disparities between and within electronic circuits, along with increased signal noise when DI/DT is high or when higher levels of current are used to drive an output.
Therefore, it may be seen that a need has arisen for a method and apparatus for controlling current to reduce timing disparities between and within electronic circuits and for controlling current to reduce signal noise by lowering unnecessary amounts of current driving an output and/or by lowering unnecessarily high DI/DT rates of change in the current driving an output, in response to environmental conditions such as temperature, overall voltage levels in an electronic circuit, and manufacturing process tolerances.