This invention relates to a CMOS, and more particularly, to a power supply switching circuit.
In an LSI using an EPROM and the like, it is necessary to apply a potential which is higher than a power supply potential (V.sub.DD) for writing while in the write mode, and to use the standard potential and a potential which is higher than the standard potential as power supplies and to switch them.
Heretofore, as a circuit for switching power supplies as described above, there is, for example, a power supply switching circuit shown in FIG. 4.
This conventional circuit includes a first p-channel MOS transistor P1 and a second p-channel MOS transistor P2 which are connected in series, and a high potential V.sub.PP is supplied from IN2 to the source of the first p-channel MOS transistor P1, and a standard potential (V.sub.DD) is supplied from a terminal 10 to the drain of the second p-channel MOS transistor P2.
An input terminal IN1, to which control signals are input, is connected to the input of a level shifter 8, through which the gate of the first p-channel MOS transistor P1 is connected. The input terminal IN1 is also connected to the gate of an inverter circuit 7 which comprises a p-channel MOS transistor P4 and an n-channel MOS transistor N5.
An output terminal OUT1 is connected to a connection point of the drain of the first MOS transistor and the source of the second MOS transistor, and grounded at GND0 via the p-channel MOS transistor P4 and is the n-channel MOS transistor N5. The gate of the second MOS transistor P2 is connected to a connection point of the p-channel MOS transistor P4 and the n-channel MOS transistor N5.
Now, the operation of this power supply switching circuit of the prior art will be explained.
An input signal is applied to the input terminal IN2 at the potential level V.sub.PP which is higher than the standard potential (V.sub.DD).
The level shifter 8 is inserted for completely turning off the first p-channel MOS transistor P1 when the level "V.sub.DD " is input to the input terminal IN1, and is a circuit which outputs the level IN2 when the level "V.sub.DD " is input to the input terminal IN1, and outputs the level "GND" when the level "GND" is input.
First, when the level "GND" is input to the input terminal IN1, the level "GND", which is an output of the level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned on. Accordingly, a connection point 6 (node) of the drain of the first MOS transistor P1 and the source of the second MOS transistor P2 comes to the level "V.sub.PP ".
Furthermore, since the level "GND" is applied to the qate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned off. The level "GND" is also applied to the gate of the p-channel MOS transistor P4 connected to the input terminal IN1, and since the node 6 is at the level "V.sub.PP ", the p-channel MOS transistor P4 is turned on. The gate of the secOnd MOS transistor P2 comes to the level "V.sub.PP " via the turned-on p-channel MOS transistor P4, and the second MOS transistor P2 is completely turned off. Consequently, the level "V.sub.PP " is output from the output terminal OUT1.
When the level "V.sub.DD " is input to the input terminal IN1, the level "V.sub.PP ", which is an output of the level shifter 8, is applied to the gate of the first p-channel MOS transistor P1, and the first p-channel MOS transistor P1 is turned off. Furthermore, since the level "V.sub.DD " is applied to the gate of the n-channel MOS transistor N5 of the inverter 7 connected to the input terminal IN1, the n-channel MOS transistor N5 is turned on. The gate of the second p-channel MOS transistor P2 then becomes at the level "GND", and the second p-channel MOS transistor P2 is turned on. Hence, the node 6 comes to the level "V.sub.DD ". Since the gate and the source of the p-Channel MOS transistor P4 are both at the level "V.sub.DD ", the p-channel MOS transistor P4 is turned off. Hence, the level "V.sub.DD " of the node 6 is output as it is from the output terminal OUT1.
As described above, in the power supply switching circuit of the prior art shown in FIG. 4, the level "V.sub.PP " is output when the level "GND" is input to the input terminal IN1, and the level "V.sub.DD " is output from the output terminal OUT1 when the level "V.sub.DD " is input to the input terminal IN1.
When a potential applied to the high-potential input terminal IN2 is at a level equivalent to or higher than the level "V.sub.DD ", no forward-direction bias is applied to a parasitic diode D1 which exists between a source diffusion region (p-type) and an n-well of the first p-channel MOS transistor P1 as shown in FIG. 5, and so no current flows.
However, when a potential applied from the input terminal IN2 is lower than the level "V.sub.DD ", although the first p-channel MOS transistor P1 is turned off, a forward-direction bias is applied to the parasitic diode D1 to conduct it. Hence, a current path is formed between the V.sub.DD and the IN2 via the first and second p-channel MOS transistors P1 and P2, and the output level from the output terminal OUT1 decreases.
Since there exists the above-described inconvenience when a potential applied from the input terminal IN2 is lower than the level "V.sub.DD ", a high-potential input signal and other input signals can not use the terminal IN2 in common, and it is necessary to provide exclusive terminals for respective inputs.