FIG. 1 shows the typical CMOS active pixel image sensor 100. The basic component of the image sensor 100 is the array of photosensitive pixels 130. The row decoder circuitry 105 selects an entire row of pixels 130 to be sampled by the correlated double sampling (CDS) circuitry 125. The analog-to-digital converter 115 scans across the column decoders and digitizes the signals stored in the CDS 125. The analog-to-digital converter 115 may be of the type which has one converter for each column (parallel) or one high-speed converter to digitize each column serially. The digitized data may be directly output from the image sensor 100 or there may be integrated image processing 120 for defect correction, color filter interpolation, image scaling, and other special effects. The timing generator 110 controls the row and column decoders to sample the entire pixel array or only a portion of the pixel array.
FIG. 2 shows one of many different possible schematics for a CMOS image sensor. Four pixels 130 (only one is labeled for clarity) are shown of the pixel array. Each pixel 130 has circuitry that is shared between two photodiodes 150 and 151. This type of pixel along with other variations may be found in U.S. Pat. Nos. 5,625,210; 5,841,159; 5,949,061; 6,107,655; 6,160,281; 6,423,994; and 6,657,665.
The photodiodes 150 and 151 are connected to a common shared floating diffusion 155 respectively by transfer gates 152 and 153. The process of sampling the photodiode 150 begins by turning on the power supply (VDD) 158 and also turning on the reset transistor 154 to set the floating diffusion 155 voltage to the voltage of the power supply 158. The reset transistor 154 is then turned off, and the signal level sampled by the output transistor 156 is driven onto the output signal line 157. Next, the transfer gate 153 is turned on to transfer photo-generated signal charge from photodiode 150 to the floating diffusion 155. Now the output transistor 156 will drive the signal level voltage onto the output signal line 157. The difference of the first signal just after reset minus the signal after the transfer gate 153 was pulsed is proportional to the number of electrons that was in the photodiode 150.
The second photodiode 151 is sampled in the same manner through transfer gate 152. This pixel 130 is shown as a two-shared pixel because two photodiodes 150 and 151 share a common floating diffusion 155. An example of how a two-shared pixel might physically be manufactured on a silicon substrate is shown in FIG. 3. The numbered components in FIG. 3 correspond to the schematic symbols in FIG. 2. The polysilicon transistors transfer gates are 152 and 153; the reset transistor gate is 154 and the output transistor gate is 156. The floating diffusion contacts 155 are connected together by a metal wire. The reset 154 and output 156 transistors share a common diffusion connection 158 to the power supply line.
The drawback with the pixel layout of FIG. 3 is how to reduce the size of the pixel. The gap 160 between two adjacent pixels cannot be shrunk further without risking leakage of electrons between to adjacent pixels. The size of the transistor gates 154 and 156 cannot shrink because the operating voltage of the power supply determines their size. Reducing the power supply voltage is not an attractive option because that also will reduce the maximum number of photo-electrons that can be collected by the photodiodes.
The present invention will address this shortcoming and others as it discloses a way to reduce the pixel size without having to reduce the size of the reset and output transistor gates.