1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a damascene process.
2. Description of Related Art
A damascene process is one kind of interconnect process. The damascene process is to form a trench in a dielectric layer. A metal layer is formed in the trench to form a conductive line as an interconnect. A dual damascene process is one kind of multilevel interconnect process. In the dual damascene process, a contact or a via is additionally formed as an interconnect.
FIGS. 1A through 1C are schematic, cross-sectional views showing a conventional damascene process.
As shown in FIG. 1A, a semiconductor substrate 100 is provided. A dielectric layer 102 is formed over the substrate 100. A chemical-mechanical polishing (CMP) process is performed to planarize the dielectric layer 102. A patterned photoresist layer 104 is formed on the dielectric layer 102.
As shown in FIG. 1B, using the photoresist layer 104 as a mask, the dielectric layer 102 is etched by dry etching to form a trench 106.
As shown in FIG. 1C, the photoresist layer 104 (FIG. 1B) is removed by oxygen plasma. A metal plug 108 is formed in the trench 106, thus completing the damascene process. If a dual damascene process is performed, the process is more complicated.
In the conventional method, oxide with a low dielectric coefficient is used as a material for the dielectric layer 102. The oxide layer includes spin-on polymer (SOP) having a polymer-like structure. While removing the photoresist layer by oxygen plasma, the SOP layer with the polymer-like structure is easily damaged by the oxygen plasma. Therefore, the process is not suitable for removing the photoresist layer by oxygen plasma. Another improved process is to form a cap oxide layer between the dielectric layer and the photoresist layer, as shown in FIGS. 2A through 2B. FIGS. 2A through 2B are schematic, cross-sectional views showing another conventional damascene process. For the convenience of description, the same reference numbers are used in the FIGS. 1A through 1C and FIGS. 2A through 2B to refer to the same or like parts.
As shown in FIG. 2A, a dielectric layer 102 is formed over the substrate 100. A cap oxide layer 103 is formed on the dielectric layer 102. A patterned photoresist layer 104 is formed on the cap oxide layer 103. The cap oxide layer 103 is defined.
As shown in FIG. 2B, the photoresist layer 104 (FIG. 2A) is removed by oxygen plasma. Using the cap oxide layer 103 as a hard mask, the dielectric layer 102 is etched to form a trench 106.
In the conventional method, due to the cap oxide layer 103, the process is more complicated. In addition, while etching the dielectric oxide layer with a low dielectric coefficient to form the trench, a gas with oxygen is commonly used as an etching gas source. The dielectric layer is easily damaged during the etching process. Therefore, the trench profile is not easily controlled and a trench with a bowed profile is often formed. Adhesion between the cap oxide layer and the dielectric oxide layer with a low dielectric layer is poor so that while performing a cleaning step after the etching process, peeling occurs on the cap oxide layer. Moreover, the cap oxide layer formed on the dielectric oxide layer leads to an increased dielectric coefficient for the dielectric layer.