1. Field of the Invention
The present invention relates to priority encoders.
2. Discussion of the Related Art
Priority encoders are circuits that serve to acknowledge the request having the highest priority from among a plurality of requests arriving as active signals to the encoder. A request acknowledgement includes enabling a circuit (often a microprocessor) so that the circuit, for example, executes the task corresponding to the request.
A priority encoder may receive one or a plurality of simultaneous requests on respective request lines assigned with respective ranks, for example from 1 to n. The priority encoder acknowledges one request at a time through acknowledgement lines. In some encoders, the acknowledgement lines directly correspond to request lines, and the encoder transmits on the acknowledgement lines the acknowledged request only. In some other encoders, the acknowledgement lines provide the binary rank of the acknowledged request.
There are two types of priority encoders: so-called "linear" encoders and so-called "circular" encoders.
In linear encoders, the priorities assigned to the request lines are distinct, the priorities being, for example, assigned by decreasing order to the ranks of the request lines. Linear encoders always acknowledge the request of lowest rank, and a request of a determined rank is not acknowledged as long as there remains requests of lower ranks.
Linear encoders are conventionally implemented as a non-sequential logic circuit, of the carry propagation type, that acknowledges the request of the lowest rank shortly after any change in the states of the request lines. The actual delay depends on the carry propagation time of the circuitry.
In circular encoders, the request lines are each assigned a same priority level. Such an encoder must ensure, when several requests are active at the same time, that each of these requests is acknowledged at a given time.
To achieve this purpose, conventional circular encoders are formed by a sequential logic circuit that circularly polls the request lines at a predetermined clock rate. At each clock cycle, the sequential circuit polls one request line. If the request line that is polled is active, the corresponding acknowledgement is transmitted, and the polling of the request lines then continues from the last line that was polled. When the request line of last rank, n, is polled, polling is resumed from the request line of rank 1, and so on.
Thus, a drawback of the above-mentioned circular encoders is that they process only one request line at each clock cycle. In other words, if the circuit polls the line of rank i whereas the next active request is of rank j (j&gt;i), the request of rank j is acknowledged only j-i clock cycles later.