With improvement in performance of information processors such as apparatuses and servers intended for communication trunk, the data rate of signal transmitting/receiving inside and outside the apparatus needs to be increased. The receiver circuit performs reproduction (CDR: Clock and Data Recovery) of the clock and data from data of a high data rate in order to absorb the difference in clock frequency with respect to the transmitter circuit. As a CDR method in a transmitter/receiver circuit at such a high speed as exceeding 10 Gbps, there is known CDR in a two-times over sampling method of performing sampling two times in 1 unit interval (UI) section of data and setting one sampling to the center of data and the other sampling to the transition point of data.
Further, a closed loop clock correction method is known which includes a step of adjusting two or more input signals including at least one in-phase clock and at least one quadrature phase clock, and a step of applying the adjusted quadrature phase clock signal to a device capable of generating a 4-quadrant interpolated output clock phase (refer to, for example, Patent Document 1). First, an interpolated output clock phase is delayed so as to form a clock for measurement device, and two or more adjusted input signals to the measurement device are measured over a range of the interpolated output clock phase. Then, an error between the in-phase clock and the quadrature phase clock is decided using sample information from the measurement device, and the in-phase clock and the quadrature phase clock are adopted using the decided error information in a closed loop feedback configuration.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2011-10296
The receiver circuit can sample a center and a transition point of data using a first clock signal and a second clock signal. If the phase difference between the first clock signal and the second clock signal is constant, the center of data can be sampled at all times. However, if the receiver circuit has a function of shifting the phase of the first clock signal, there occurs variation in the phase difference between the first clock signal and the second clock signal. In this case, it is impossible to sample the center of data to cause a problem of increasing the occurrence rate of data error.