1. Field of the Invention
The present invention relates to a logic circuit and its fabrication method, and more particularly to a circuit structure for implementing a low power consumption CMOS logic circuit.
2. Description of Related Art
A CMOS circuit structure is widely employed in fields such as mobile telecommunication systems that consist of low power consumption LSIs with a supply voltage of one volts or less.
FIG. 22 is a circuit diagram showing a conventional CMOS logic circuit. In FIG. 22, a CMOS logic circuit C11 is composed of a high threshold voltage pMOS transistor 81, a low threshold voltage pMOS transistor 82, and a low threshold voltage NMOS transistor 83. In other words, the CMOS logic circuit C11 is composed of MOS transistors with the high threshold voltage and low threshold voltage.
The conventional CMOS logic circuit C11 has a high operating speed because it uses low threshold voltage MOS transistors 82 and 83. In addition, smaller leakage current flows through the low threshold voltage MOS transistors 82 and 83 in a sleeping mode than in an operating mode, since the pMOS transistor 81 is kept OFF. This can reduce power consumed by the low threshold voltage MOS transistors 82 and 83 in the sleep mode.
In the CMOS logic circuit C11, however, a leakage current flows through the MOS transistors 82 and 83, since the pMOS transistor 81 is turned on in the operation mode, and the leakage current causes power loss. Thus, the conventional CMOS logic circuit C11 has a problem in that it cannot prevent a power loss in an operation mode.