Co-pending application Ser. No. 780,251, filed Oct. 21, 1991, entitled "SOI/SOS CMOS DEVICE HAVING BODY EXTENSION FOR PROVIDING SIDEWALL CHANNEL STOP AND BODYTIE" by R. Cherne et al, assigned to the assignee of the present application and the disclosure of which is herein incorporated, addresses parasitic channel/leakage problems associated with thin co-planar integrated circuits that employ silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS architectures. As described in that application, such structures are typically characterized by the use of either air or oxide dielectric to provide lateral isolation between adjacent `mesa` transistors which are formed atop an insulating dielectric (e.g. silicon oxide or sapphire).
In particular, as diagrammatically illustrated in the top view of FIG. 1 and the side view of FIG. 2, a conventional N-channel SOI/SOS thin film MOS transistor structure is typically comprised of a semiconductor (silicon) mesa layer 11, which is disposed atop a substrate-supported dielectric (silicon dioxide) layer 12 and the sidewall perimeter of which is bounded by air or an oxide dielectric layer, shown at 13. This semiconductor mesa structure contains a P-type body/channel region 14 disposed between and immediately contiguous with respective N+ source and drain regions 16 and 18. Overlying the (P-type) channel/body region 14 and extending onto the surrounding support substrate, either co-planar with the top of the mesa as shown in FIG. 2 in the case where the mesa is bounded by an oxide dielectric layer 13, or stepped down to the surface of dielectric layer 12 in the case where the mesa is bounded by air isolation, is a doped polysilicon gate layer 21, insulated from the semiconductor material of the mesa by a thin dielectric layer (e.g. oxide) 22.
In dielectric bounded architectures, a backside MOS parasitic device is formed where the drain and source regions terminate at the underlying insulator layer. Since the insulator layers are normally considerably thicker than the active gate oxide, for relatively similar doping levels the voltage necessary to cause inversion at the surface of the dielectric is typically large enough, so that under normal ambient operating conditions there is little problem of parasitic leakage.
However, when the device is required to operate in an environment where large quantities of ionizing radiation (e.g. X-rays or gamma rays) are present, electron-hole pairs are generated in the underlying dielectric. Although most of these electron-hole pairs quickly recombine and the highly mobile remaining electrons are rapidly drawn away from the insulator, slower moving holes remain trapped so as to add positive charge, which reduces the N-channel threshold voltage of the device. As the thick oxide threshold voltages are reduced to approach the value of the circuit's power supply, source-to-drain leakage increases, thereby degrading the integrated circuit's performance and, eventually, the circuit may even be rendered non-functional.
Thus, in the device shown in FIGS. 1 and 2, the surface of P-doped material (here the P-type channel/body region 14) is susceptible to inversion in the presence of ionizing radiation, so that there is the danger of a leakage path or `parasitic` channel being induced along the body/channel sidewalls 23, 24 between the source and drain regions 16, 18. Moreover, regardless of the potential for exposure to ionizing radiation, the inability of some manufacturing processes to accurately control the channel doping along the edges of the device (beneath the polysilicon gate overlay 21), and the lack of control of electrostatic charge build-up along surface portions 25, 27 of dielectric layer 13 that is immediately adjacent to P-type silicon body 14, may cause the device to suffer extraordinary current leakage in its OFF state.
Several methods have been employed to harden SOI thick oxides and other dielectric materials against total dose radiation. For example, the back gate N-channel can be heavily doped by high energy implantation of dopants to produce retrograde well impurity profiles. In more advanced technologies having a mesa thickness less than a half micron, it becomes increasingly more difficult to obtain the necessary back-to-front concentration gradient and keep the active device decoupled from the backside doping, which severely limits the effectiveness of a well dopant retrograding approach in then SOI transistor architectures.
Applying a large negative bias voltage (greater or equal to negative 5 volts) to the substrate can also help keep the backside interface in an accumulation state. However, the most universally accepted biasing scheme involves grounding the substrate. This constraint is due to the lack of a power supply rail in most digital military and aerospace electronic subsystems.
Heavily doped P-type channel stops and guard rings, source and/or drains diffusions spaced apart from the device side edge, and edgeless or circular gate circuit layouts have been used to reduce or eliminate sidewall leakage. These techniques either require considerably greater layout area to implement the circuit, or they limit the transistor to unidirectional current flow by permanently linking the device source to its body.
In accordance with the invention described in the above-referenced co-pending application, the above discussed leakage problems of conventional SOI/SOS thin film MOS mesa architectures may be effectively obviated by extending the body/channel region to form a `tab` channel stop. In accordance with one embodiment of the `tab` channel stop configuration, diagrammatically illustrated in the respective top and side views of FIGS. 3 and 4, respectively, the conventional thin mesa transistor structure of FIGS. 1 and 2 is modified such that the body/channel region 14 extends beyond its interfaces with each of the source and drain regions, as shown by body/channel extension regions or segments 31, 32. Regions 31, 32 have a prescribed width x and a length y within the dimensions of the gate layer 21 and serve to increase the effective channel width of body/channel region 14 to a value greater than the case where the body/channel region terminates `flush` with source and drain regions 16, 18 (as shown in FIG. 1). The respective channel/body extensions 31, 32 at both ends of the body/channel region beneath the polysilicon gate, by increasing the `net edge length` (2x+y), can be expected to reduce OFF state leakage due to the attenuation of parasitic transistor short channel effects.
The channel extension tab configuration may be enhanced by increasing the doping concentration of the tabs at their outer extremities, as diagrammatically illustrated in FIGS. 5 and 6, which show respective top views of a channel tab extension architecture, in which respective high impurity concentration implants 41, 42 overlap end, channel stop, portions 43, 44 of (P-type) body/channel extension regions 31, 32, whereby the impurity concentration of these end portions of the extension regions is increased relative to the impurity concentration of that portion 17 of the body/channel region 14 disposed between the source and drain regions, thereby forming a pair of P+ channel stops. This relatively high impurity concentration of the channel stop regions 43, 44 insures that the parasitic sidewall threshold is higher than any possible negative threshold shift which might be induced by ionizing radiation. These more heavily doped (P+) channel stop regions 43, 44 of the extension regions 31, 32 are spaced apart from the endwall edges of source and drain regions 16, 18 by respective portions 51, 52 of the extension regions 31, 32 of the same doping concentration as the body/channel region 14 itself, so that the more heavily doped (P+) channel stop regions 43, 44 do not form (very low breakdown voltage) P+/N+ junctions with the source and drain regions 16, 18. The source and drain regions may be formed by an N+ implant using an implant mask the geometry of which overlaps polysilicon gate layer 21, shown at 55 in FIG. 6.
Now although the incorporation of channel extension tabs is very effective in eliminating the problem of sidewall leakage, it has been found to contribute to a reduction in radiation hardness of the back gate extension. With reference to the extended channel architecture shown in perspective in FIG. 7 and in plan in FIG. 8, the buried dielectric layer 12 underneath the intermediate or buffer portion 51 of the channel extension has been found to exhibit a total ionizing dose response, which is degraded compared with SOI transistor structures that do not have an extended channel configuration. A localized reduced threshold voltage and an increased post irradiation threshold voltage shift, consequently, an earlier onset of a secondary radiation-induced leakage has been observed along this interface.