1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and more particularly to a NAND flash memory in which data can be read out from cells with negative threshold voltages, for example.
2. Description of the Related Art
A NAND flash memory is well known in the art as a nonvolatile semiconductor memory device in which data can be electrically rewritten (written and erased) and which is suitably formed with high integration density and large memory capacity. In the NAND flash memory, the voltages of select gates are instantly raised to approximately 4V at the start time of the read operation in the conventional read system (read system for cells with positive threshold voltages (positive potential read)/Positive Level Sense system) in which the voltages of a source line and well line are set to 0V.
On the other hand, in the read system for cells with negative threshold voltages (negative potential read)/Negative Level Sense system), the voltages of a source line and well line are biased to a positive voltage (for example, 1V) at the read time (for example, refer to U.S. Patent Application Publication No. 2006/0133150 A1). That is, in the case of a NAND flash memory in which cells with a negative threshold voltages are present, the voltage of a selected word line (WL) is set to approximately 0V (the voltages of non-selected word lines are set to approximately 6V) by writing multivalue data (for example, data of eight or more values/data of three or more bits). In this state, the voltages of the source line and well line are biased to a positive voltage. As a result, the read and verify operations for the cell with the negative threshold voltage can be performed.
Thus, in recent years, a study is made to stably perform the read and verify operations for the cell with the negative threshold voltage by biasing the voltages of the source line and well line to the positive voltage at the read time and verify time. However, in the case of the NAND flash memory in which the voltage of the select gate is set to 4V at the read time for the cell with the positive threshold voltage, it is necessary to set 4V or more as the voltage of the select gate at the read time and verify time for the cell with the negative threshold voltage. However, an effective method for controlling the voltage of the select gate in the read and verify operations for the cell with the negative threshold voltage is not yet provided.
As described above, in the NAND flash memory, an attempt is made to perform the read and verify operations for the cell with the negative threshold voltage. It is therefore desired to develop an effective voltage control circuit that controls the voltage of the select gate at the read time and verify time for the cell with the negative threshold voltage so that the read and verify operations for the cell with the negative threshold voltage can be stably performed.