The present invention relates to semiconductor integrated circuit devices, and more particularly to techniques which are effective when applied to a semiconductor integrated circuit device adopting a gate array scheme wherein a plurality of layers of wiring are formed by a DA (Design Automation) system.
A logic LSI (Large-Scale Integrated Circuit) which adopts the gate array scheme is formed by a semiconductor manufacturing process to be stated below:
First, a semiconductor substrate on which basic cells each bearing a basic design are regularly arrayed is prepared beforehand. Each of the basic cells is constructed of built-in basic elements, for example, bipolar transistors, resistors and capacitors.
Subsequently, connections are done on the basis of a logic design within the basic cells and among the basic cells (among logic circuits) arrayed on the surface of the semiconductor substrate, whereby a desired logic function is attained. The connections are effected by the use of a plurality of layers of aluminum signal wiring.
The logic LSI of this type adopting the gate array scheme has the feature that the period of time for the completion of a product can be shortened. Besides, it has the feature that another logic function can be attained merely by altering a connection pattern.
In the logic LSI, as the gate count increases more, the occupation area of the basic cells tends to become larger, and that of wiring regions (wiring channel regions) where the connections formed among the basic cells are arranged tends to become smaller. Therefore, a logic LSI under development is constructed of a four-layer wiring structure in which spaces between basic cells and on them are effectively used as wiring regions, though this technique is not known. The first layer of wiring, the second layer of wiring and the third layer of wiring are chiefly configured of signal wiring lines. The fourth layer of wiring is chiefly configured of signal wiring lines and power source wiring lines. The first layer of wiring is arranged as the signal wiring lines which connect logic circuits among the basic cells, and also as intracellular wiring lines which connect various semiconductor elements within each of the basic cells. The second layer of wiring and the third layer of wiring are respectively arranged as the signal wiring lines which connect the logic circuits.
The connection pattern of the logic LSI under development is formed by a DA (Design Automation) system of two-dimensional processing which utilizes a computer. The DA system can automatically allocate the information items of the logic circuits subjected to logic designs, and it can also automatically allocate connection information (wiring information) items for connecting the logic circuits, into an X-Y latticed wiring channel region which is imaginarily set in a memory space. In the DA system, the wiring information items of the first layer of wiring and those of the third layer of wiring are allocated in the X-direction of the X-Y latticed wiring channel region. The wiring information items of the second layer of wiring are allocated in the Y-direction of the X-Y latticed wiring channel region. The connections between the first layer of wiring and the second layer of wiring and those between the second layer of wiring and the third layer of wiring are respectively done at the predetermined lattice points of the X-Y latticed wiring channel region.
When the wiring information items are automatically allocated by the DA system, a semiconductor manufacturing mask is produced on the basis of these wiring information items. The semiconductor manufacturing mask has the pattern of the connections which are to be formed in the logic LSI. A semiconductor wafer process is performed using the semiconductor manufacturing mask, whereby the logic LSI of the multilayer wiring structure described above can be manufactured.
By the way, the logic LSI which adopts the gate array scheme is stated in, for example, "VLSI DEVICE HANDBOOK", pp. 371-372, issued by Kabushiki Kaisha Science Forum on Nov. 28, 1983.