1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a ferro-electric capacitor and a bit line capacitance adjusting method using the device and, more particularly, to a semiconductor integrated circuit device which optimizes the bit line capacitance and a bit line capacitance adjusting method using the device.
2. Description of the Related Art
Ferro-electric memories (FeRAMs) using ferro-electric capacitors have recently been receiving a great deal of attention as nonvolatile semiconductor memories.
A memory cell of an FeRAM is formed from a cell transistor Trc and a ferro-electric capacitor Cf, as shown in FIG. 6. One of the source and drain of the cell transistor Trc is connected to a bit line BL, and the other is connected to one electrode of the ferro-electric capacitor Cf. The other electrode of the ferro-electric capacitor Cf is connected to a plate line PL. The bit line BL has a parasitic bit line capacitance Cb.
In this FeRAM, data is written or read by using the hysteresis characteristic of the ferro-electric material that forms the ferro-electric capacitor Cf.
FIG. 7 shows the hysteresis characteristic of the ferro-electric capacitor Cf. The abscissa of this graph indicates a voltage Vf applied to the ferro-electric capacitor Cf. The ordinate indicates a charge amount Q. Straight lines L1 and L2 indicate the characteristic of the bit line capacitance Cb. As the value of the bit line capacitance Cb decreases, the gradient of the straight lines L1 and L2 becomes small.
In the ferro-electric capacitor Cf, even when the applied voltage Vf is 0V, polarization remains at points A and C. Point A indicates the polarization state for data “0”. Point C indicates the polarization state for data “1”.
Data written in the memory cell can be read by checking the polarization state of the ferro-electric capacitor Cf.
First, the bit line BL is set in a floating state. Then, a read potential is applied to the plate line PL. The voltage generated across the ferro-electric capacitor Cf at this time is measured.
When the ferro-electric capacitor Cf is in the polarization state at the point A, it is shifted to the state at a point E in consideration of the bit line capacitance Cb by the straight line L1. The voltage Vf generated across the ferro-electric capacitor Cf is V0. On the other hand, when the ferro-electric capacitor Cf is in the polarization state at the point C, it is shifted to the state at a point F in consideration of the bit line capacitance Cb by the straight line L2. The voltage Vf generated across the ferro-electric capacitor Cf is V1. When a reference voltage Vref is set in advance, the polarization state of the ferro-electric capacitor Cf can be checked by comparing the reference voltage Vref with the voltage Vf generated across the ferro-electric capacitor Cf in the read. In the above-described way, “1” and “0” data are discriminated.
The value of the bit line capacitance Cb indicated by the straight lines L1 and L2 is decided by the cell array structure (circuit arrangement) and manufacturing process of each device. That is, once the cell array structure and manufacturing process are decided, and a chip is manufactured, its bit line capacitance Cb cannot be optimized further. In addition, the device incorporates no circuit capable of changing the bit line capacitance Cb after manufacturing. Conventionally, since the bit line capacitance Cb after manufacturing is not changeable, the following problems are posed.
FIG. 8 shows the relationship between the bit line capacitance Cb and a signal margin Vm. The signal margin Vm is the voltage difference |V1−V0| between “1” and “0” data. The signal margin Vm is also called a “bit line signal window”.
The relationship between the bit line capacitance Cb and the signal margin Vm changes depending on the size or hysteresis shape of the ferro-electric capacitor Cf. The “designed curve” shown in FIG. 8 is a curve when a typical hysteresis shape and a certain size of the ferro-electric capacitor Cf are assumed. In actually, for example, the “actual curve” shown in FIG. 8 is obtained because the curve changes depending on the product or lot.
As shown in FIG. 8, the signal margin Vm generally takes a maximum value at a certain bit line capacitance Cb. Normally, the optimum value of the bit line capacitance Cb is roughly predicted on the basis of the size of the ferro-electric capacitor Cf to be used for a product or predicted hysteresis shape. The cell array is assembled such that the optimum value is obtained. However, the manufacturing process has some fluctuation. For this reason, in an actually manufactured chip, the bit line capacitance Cb does not always have the predetermined optimum value.
When a chip is manufactured in consideration of the optimally designed bit line capacitance Cb in FIG. 8, the signal margin Vm of about 1,000 mV should be ensured. Actually, however, the signal margin Vm is only about 500 mV.
As described above, in the prior art, the bit line capacitance Cb cannot be optimized after manufacturing a device. For this reason, some chips may be unable to ensure the signal margin Vm that should be obtained. They may be defective or cannot ensure long-term reliability.
Prior art related to this application is, for example, Jpn. Pat. Appln. KOKAI Publication No. 6-342597.