This invention relates to a semiconductor device comprising charge storage capacitor cells and to a method of manufacturing the semiconductor device or a like semiconductor device.
At present, on the market are very large scale integrated circuits (VLSI's) of a design rule of 0.8 micron, such as four-megabit dynamic random access memories (DRAM's) and one-megabit static random access memories (SRAM's). Research and development are in progress in connection with ultra large scale integrated circuits (ULSI's) of a closer design rule of 0.5 to 0.6 micron, such as sixteen-megabit dynamic random access memories and four-megabit static random access memories. Studies are carried on as regards practical use of such ultra large scale integrated circuits.
On giving a high package density, a large memory capacity, and a large capacitance to, for example, a dynamic random access memory, it is necessary to stack the charge storage capacitor cells three-dimensionally. For use as the capacitor cells of either the above-mentioned sixteen-megabit dynamic random access memories or 64-megabit dynamic random access memories of a stricter design rule, a fin structure is proposed by T. Ema and eight others to the IEDM Tech. Dig., 1988, pages 592 to 595. Furthermore, a cylindrical structure is proposed by W. Wakayama and four others in the VLSI Symp., 1989, pages 69 to 70.
On commercially manufacturing a semiconductor device comprising the capacitor cells, the fin and the cylindrical structures have not been used because of the following problems. One is the fact that it is very difficult to uniformly form a capacitor dielectric film on electrode side and top surfaces of a patterned electrode of each capacitor cell and to similarly uniformly form a covering or counter electrode on the dielectric film. This is because the patterned electrode has a complicated structure. Another problem is the fact that it is also difficult to render an interlayer insulator layer flat enough for subsequent wiring. This is because the patterned electrode has a pattern of a great aspect ratio.
In the manner which will later be described more in detail, a conventional semiconductor device is manufactured as follows to comprise charge storage capacitor cells. An insulator film for cell separation is first formed on a substrate surface of a semiconductor substrate. Openings or holes are selectively formed through the insulator film. In order to form the capacitor cells on the insulator film, heavily doped patterend electrodes of the respective capacitor cells are patterned on the insulator film to fill the respective openings and to leave an exposed insulator area around the patterned electrodes. Each patterned electrode has electrode side and top surfaces. A dielectric film is deposited on the electrode side and top surfaces of each patterned electrode and on the exposed insulator area. A heavily doped covering or counter electrode is grown on the dielectric film over each patterned electrode. An interlayer insulator layer is formed on the covering electrodes to have a flat layer surface. Wirings are finally formed on the flat layer surface of the interlayer insulator layer.
The following problems have become clear on making such a semiconductor device have a small size, a high package density, and a large capacitance. When each opening is made to have a small diameter, the openings become to have a great aspect ratio. This renders it difficult to make the patterned electrodes fill the openings if the patterned electrodes are doped with an impurity. When the dielectric film is given a thin film thickness, each patterned electrode is subjected to reversal at an interface contiguous to the dielectric film. This reduces the capacitance. Reduction in the capacitance can be avoided if the patterned electrodes were heavily doped. A compromise is therefore necessary between complete filling of the openings and an increase in the capacitance. If a desired capacitance should be insured with the high package density attained, the patterned electrodes must have a wide total surface area per unit area of the substrate surface. It has, however, been difficult to reduce a distance between one of the capacitor cells and another capacitor cell or a different element of the integrated circuit.
On the other hand, it is an important problem to raise quality, such as an insulating capability, and reliability of the insulator film and/or the dielectric film. In this connection, it has been confirmed that the substrate surface has a micro-roughness or, more particularly, undulations of the order of 10 .ANG. and that this roughness adversely affects the insulating capability and the reliability of the insulator film particularly when the insulator film is as thin as 100 .ANG.. It has furthermore been confirmed that the electrode side and top surfaces are rough surfaces having undulations of the order of 1000 .ANG. and that such a rough surface adversely affects the insulating capability and the reliability of the dielectric film particularly when the dielectric film is as thin as 50 .ANG..