Monolithic integrated circuit semiconductor devices using bulk CMOS technology inherently contain parasitic PNPN structures which form bipolar transistors that produce an undesired silicon controlled rectifier (SCR) action commonly known as the "latchup". This phenomena occurs when an unwanted trigger current turns on two back-to-back bipolar transistors in the device. Once turned on, the device will remain "on" even after the signal which produced the forward biasing is removed, in time shorting the power supply to ground and eventually causing destruction or malfunction of the device.
For a four layer PNPN structure to latchup, the following conditions must be met in a n-well type CMOS device:
1. Both of the parasitic bipolar transistors formed within the CMOS device must be biased into active state (emitter-base junctions forward biased). This can happen if lateral currents of sufficient magnitude are present to cause the required voltage drops across the substrate and the n-well resistances. Such currents can be caused by ionizing radiation such as X-rays, alpha particles or gamma rays; overvoltage stress in the applied terminal voltage (V.sub.CC -V.sub.SS) resulting in an avalanche current from the reverse biased n-well to substrate junction; voltage transients on the power supply line resulting in a displacement current from the n-well to substrate depletion layer capacitance, CdV.sub.CC /dt; hot electron substrate current from short channel devices (p-channel devices typically exhibit 3 orders of magnitude less substrate current than comparable n-channel devices).
2. The parasitic bipolar current gain product B.sub.N * B.sub.P must be sufficiently high to allow regeneration. For a CMOS inverter this condition is: ##EQU1## where I.sub.cc is the maximum current available from the power supply and R.sub.S and R.sub.W are the substrate and n-well resistances, respectively. For R.sub.S and R.sub.W .fwdarw.infinity, the condition reduces to B.sub.N * B.sub.P &gt; or=1 which makes latchup very likely. The higher the values of resistances R.sub.S and R.sub.W, the easier it is for a trigger current to forward bias the transistor junctions, and hence the easier to latchup. From this it is obvious that a sufficient condition to prevent latchup would be to ensure that B.sub.N * B.sub.P &lt;1. This, however, is difficult to implement in practice.
3. The bias supply must be capable of sourcing current equal to or greater than the holding current. This current depends on R.sub.S and R.sub.W. As R.sub.S, R.sub.W or both approach zero, the supply current necessary to sustain latchup becomes infinite and latchup becomes impossible.
Heretofore various methods to control latchup in CMOS devices fell into one of the following categories: (a) layout techniques to prevent the emitter base junctions from becoming forward biased (e.g. by proper placement of V.sub.SS and V.sub.CC contacts), (b) minimizing the current gain product of the parasitic bipolar transistor by either layout techniques (such as use of guardings) or lifetime reduction techniques and (c) process architecture (e.g., use of buried layer or retrograde wells) to reduce the current gains.
Another approach that has been suggested for solving the latchup problem in bulk CMOS is the use of backbias. Using backbias, the p-substrate of a CMOS device is at a negative potential (V.sub.BB) e.g., -3 volts, as a result of either an externally applied voltage or an on-chip backbias generator. This results in the emitter base junction of the lateral n+ p n transistor being reverse biased at -3 volts. Since this junction needs to be forward biased for latchup to take place, this extra margin of -3 volts would help deter the latchup. The use of backbias also is desirable from several other considerations. It helps in achieving higher speeds by reduced junction capacitances as a result of reversed biased junctions. Also, it allows required active and field threshold values to be obtained with smaller dopings which indirectly results in lower capacitances. Other advantages such as reduced body effect of n-channel devices and better punchthrough control would also be obtained by using backbias.
However, despite its advantages, backbias heretofore has not been used in the industry for CMOS processes because of a so-called "hot-socket" latchup condition which can be explained as follows. An on-chip backbias generator (which is the only convenient way to incorporate backbias without the chip requiring an extra pin/supply devoted to V.sub.BB) results in a higher "internal" source impedance. During the powerup of the circuit, the substrate takes a finite amount of time to charge to the potential V.sub.BB. During this duration, the parasitic SCR structure has a large equivalent resistance, R.sub.BB, from the n+ p n parasitic transistor base to V.sub.BB. Also, there exists a transient current due to the depletion junction capacitance, CdV.sub.CC /dt which can help the emitter-base junctions get forward biased. Both of the above can make latchup due to the internal circuit quite probable. Also, if the field thresholds without backbias are low, any subthreshold field leakage that may exist can also contribute to trigger latchup.
This situation becomes significantly worse when a current is being drawn from one of the outputs of the circuit by an external source during the powerup phase of the device. Under this condition, the p-substrate is at a negative potential determined by the external source, -5.3 volts. Since the V.sub.CC terminal of the circuit is floating before the power is applied, all the n-wells in the circuit which are normally connected to V.sub.CC terminal, follow the substrate potential (less a diode drop). Thus all the n-wells would be at a nominal potential of -6 volts. As soon as V.sub.CC is applied, the p+ diffusion areas in the n-wells which form the sources of the p-channel transistor and are connected to V.sub.CC, start to inject minority carriers into the n-well causing the base-emitter junctions to become forward biased. This happens despite the fact that the n-wells connected to V.sub.CC supply themselves are moving towards V.sub.CC in potential, because only a local forward biasing is requiring for the above injection to take place. Once the p+ n p bipolar transistor is in an active region, and starts to inject a collector current into the substrate, the circuit may go into latchup depending on the magnitude of the current being drawn from the output, since it is relatively easy to forward bias the other n+ p n transistor due to its high R.sub.BB during powerup and the absence of V.sub.BB. In the preceding discussion, it is assumed that all the three conditions required for latchup described previously for the non-backbias situation are also satisfied, which is typically the case in practice.
The threshold of latchup is specified by the minimum current that is required to be drawn from the output for the above "hot-socket" latchup condition to take place. Typically, this current can be as low as 20 mA which is unacceptable for reliable parts. The present invention solves this latchup problem and provides a solution that raises the latchup threshold to several magnitudes of the aforesaid minimum current level, thereby eliminating the the problem in CMOS devices.