Many radio receivers such as FM receivers for receiving radio waves at relatively high frequencies, such as frequencies expressed in megahertz (MHz) or gigahertz (GHz), employ a frequency synthesizer for deriving, with stability and high precision, individual ones of a plurality of signals having mutually discrete frequencies (i.e. frequencies spaced from each other). In general, in such a frequency synthesizer, an oscillation frequency of a voltage-controlled oscillator (VCO) is frequency divided by means of a two-modulus variable frequency-divider circuit, an output of the frequency-divider is further frequency divided by means of a programmable frequency-divider circuit, and the VCO is controlled so that the frequency of the output of the programmable frequency-divider circuit becomes equal to a reference frequency. In such an arrangement, the frequency dividing factor of the programmable frequency divider circuit is properly selected such that a signal having a desired one of said plurality of discrete frequencies can be selectively derived from the VCO. A two-modulus frequency-divider circuit is a frequency-divider which has two frequency dividing factors selectable by a control signal and which can operate at a relatively high speed. Accordingly, in a PLL, it is usually disposed in a stage preceding a low-speed programmable frequency-divider circuit which is poorly responsive to high frequencies (e.g. frequencies of several hundred megahertz) supplied from a VCO, so that the oscillation frequency of the VCO is applied to the programmable frequency-divider circuit after it is divided by the two-modulus frequency-divider circuit.
FIG. 1 shows a typical example of conventional PLL frequency synthesizers. The frequency synthesizer of FIG. 1 comprises a two-modulus variable frequency-divider circuit (2-modulus V.F.D.) 1 which can divide the frequency of an input signal by either one of two factors, N and N+K, a programmable frequency-divider circuit (programmable F.D.) 2 having a variable frequency dividing factor M, a phase comparator circuit 3, a reference signal generator 4, and a voltage controlled oscillator (VCO) 5. f.sub.0 is an oscillation frequency of the VCO 5. f.sub.1 is an output frequency of the two-modulus variable frequency-divider 1. f.sub.2 is an output frequency of the programmable frequency-divider 2. f.sub.r is a reference frequency which is equal to the frequency of an output signal of the reference signal generator 4. V.sub.c is an output voltage of the phase comparator 3. MOD is a signal which is used to switch the frequency dividing factor of the two-modulus variable frequency-divider circuit 1 between N and N+K. Usually, a loop filter is disposed between the phase comparator 3 and the VCO 5, but it is not shown in FIG. 1 for simplicity.
Next, the operation of the PLL frequency synthesizer of FIG. 1 is explained. The oscillation frequency f.sub.0 of the VCO 5, which is the frequency of the output signal of the PLL frequency synthesizer, is divided by N or N+K in the two-modulus variable frequency-divider circuit 1 to form the frequency f.sub.1, which in turn is divided by M in the programmable frequency-divider circuit 2 which provides the frequency f.sub.2. The output f.sub.2 is applied to one input of the phase comparator 3, where it is compared with the reference signal frequency f.sub.r applied to the other input from the reference signal generator 4. When f.sub.0 is lower than a desired preset frequency, f.sub.2 becomes lower than f.sub.r and the output voltage V.sub.c of the phase comparator 3 rises accordingly. Then, the output frequency f.sub.0 of the VCO 5 which is controlled by the output voltage V.sub.c rises accordingly. On the other hand, when f.sub.0 is higher than the desired frequency, f.sub.2 becomes higher than f.sub.r and the output voltage V.sub.c of the phase comparator 3 becomes lower accordingly, which decreases the oscillation frequency f.sub.0 of the VCO 5. When f.sub.0 becomes equal to the desired preset frequency through the process as stated above, f.sub.2 and f.sub.r become substantially equal so that the output voltage V.sub.c of the phase comparator 3 becomes stable. Thus, the oscillation frequency f.sub.0 of the VCO 5 also becomes stable.
Next, the operations of the above-stated two-modulus variable frequency-divider circuit 1 and the programmable frequency-divider circuit 2 are explained. First, the functions of the two frequency-divider circuits are considered. Let it be assumed that the two-modulus variable frequency-divider circuit 1 has frequency dividing factors of N and N+1 (i.e. K=1). In the PLL frequency synthesizer of FIG. 1, the output frequency f.sub.0, which is the oscillation frequency of the VCO 5, is an integral multiple of the reference frequency f.sub.r. Thus, if f.sub.0 can be expressed by the following equation, in which L is an integer, a frequency equal to f.sub.r can be obtained by dividing f.sub.0 by L. EQU f.sub.0 =f.sub.r .times.L (1)
This means that the PLL frequency synthesizer must be able to divide f.sub.0 by a desired integer. L can be expressed by two positive integers M1 and M2, where M1&gt;M2, and N (a frequency dividing factor), as EQU L=M1.times.N+M2 (2)
The equation (2) can be transformed into EQU L=(M1-M2).times.N+M2.times.(N+1) (3)
From the equation (3), it is seen that the frequency division by N (.div.N frequency division) is equivalent to frequency dividing by means of two frequency dividers which respectively have frequency dividing factors N and (M1-M2), switching these factors to (N+1) and M2, respectively, and further frequency dividing by means of the same frequency dividers with their respective factors (N+1) and M2. The two-modulus variable frequency-divider circuit and the programmable frequency-divider circuit serve as the above-stated two frequency dividers. In practice, an input frequency is divided by the frequency dividing factor N in the two-modulus variable frequency-divider circuit and then its output is counted to a count 1 (M1-M2) by the programmable frequency divider. When the programmable frequency divider reaches (M1-M2), the frequency dividing factor of the two-modulus variable frequency-divider circuit is switched to (N+1) and its output is counted further by the programmable frequency divider. When the count of the programmable frequency divider reaches M2, an output is developed. The result is the desired frequency division. When the programmable frequency-divider counts (M1-M2) for the output of the two-modulus variable frequency-divider circuit, it immediately produces an MOD signal shown in FIG. 1 so as to switch the frequency dividing factor of the two-modulus variable frequency-divider circuit from N to (N+1). Thus, these two frequency-divider circuits can divide the input signal frequency by any desired integer, and, accordingly, this frequency synthesizer can produce an output frequency of any desired multiple of the reference frequency.
Next, a two-modulus variable frequency-divider circuit is described. FIG. 2 shows an example of a two-modulus variable frequency-divider circuit, which has a frequency dividing factor switchable between sixteen (16) and seventeen (17). In FIG. 2, the two-modulus variable frequency-divider circuit comprises a dual-mode frequency-divider 11 having frequency dividing factors of 4 and 5, two divide-by-two (.div.2) frequency dividers 12 and 13 which form a divide-by-2.sup.N (.div.2.sup.N) frequency divider-arrangement where N is an integer and two (2) in this case, an OR circuit 14, an output buffer circuit 16, a signal input terminal IN, an input terminal MOD for receiving a frequency dividing factor switching signal, and an output terminal OUT. N1 is an output of the dual-mode frequency divider circuit section 11. N2 and N3 are outputs of the .div.2 frequency-dividers 12 and 13, respectively. N4 is an output of the OR circuit 14. T's are clock input terminals of the respective frequency-dividers. Q's are output terminals of the respective frequency-dividers. MD is a terminal of the dual-mode frequency-divider 11 to which a frequency dividing factor setting signal is applied.
In operation, the dual-mode frequency-divider 11 operates as a divide-by-five (.div.5) frequency-divider when the signal N4, which is the frequency dividing factor setting signal applied to the terminal MD, is "LOW", while it operates as a divide-by-four (.div.4) frequency-divider when the signal N4 is "HIGH". In terms of inputs and an output to and from the OR circuit 14, only when the signal MOD, which is applied to the OR circuit 14 from a succeeding programmable frequency-divider circuit (not shown in FIG. 2), is LOW and both N2 and N3 are LOW, the output signal N4 of the OR circuit 14 is LOW and the dual-mode frequency-divider 11 performs .div.5 frequency dividing operation. In this case, the two-modulus frequency-divider circuit as a whole divides the input frequency by (5+4.times.3)=17. On the other hand, when the signal MOD is HIGH, the output N4 of the OR circuit 14 is always HIGH, so that the dual-mode frequency divider 11 performs .div.4 frequency dividing operation and, accordingly, the two-modulus frequency-divider circuit as a whole frequency divides the input signal by (4.times.4)=16 . In other words, the two-modulus frequency-divider circuit acts as a .div.16 frequency-divider circuit.
The above-described operation is further explained with reference to waveforms illustrated in FIG. 3. FIG. 3 shows the timing relationship between the output signal of the two-modulus variable frequency-divider circuit (FIG. 2) and the output signals of the respective constituent circuits, where each of the frequency-divider circuits 11, 12 and 13 comprises a master-slave flip-flop which produces a transition in its output when an input thereto changes to HIGH. In FIG. 3, a waveform IN is of the input signal and waveforms N1, N2 and N3 are of the output signals of the respective constituent circuits 11, 12 and 13, and the output N3 is substantially the same as the output OUT of the two-modulus variable frequency-divider circuit. N4 is the output signal of the OR circuit 14. T1 is a time interval from a time when the output OUT changes from HIGH to LOW to a time when both of the output signals N2 and N3 of the constituent circuits 12 and 13 go LOW, and T2 is a time interval from a time when the signal OUT changes from LOW to HIGH to a time when both of the output signals N2 and N3 become LOW. As stated previously, when the signal MOD is HIGH, N4 is always HIGH and, therefore, the two-modulus variable frequency-divider circuit provides .div.16 frequency division. In this case, the duration of each of HIGH and LOW states of the output signal OUT corresponds to eight (8) periods of the input signal IN. When MOD is LOW, the two-modulus variable frequency-divider circuit provides .div.17 frequency division. However, because N4 assumes the LOW state when the output signal OUT is in the LOW state, the duration when OUT is HIGH is eight periods of the input signal IN and the duration when OUT is LOW is nine periods of the input signal IN. Whether the two-modulus variable frequency-divider circuit acts as a .div.16 frequency-divider circuit or as a .div.17 frequency-divider circuit is determined by whether the MOD signal applied to the OR circuit 14 is HIGH or LOW when the signals N2 and N3 are both LOW.
In order for the MOD signal to be able to switch the frequency dividing factor of the two-modulus variable frequency-divider circuit between 16 and 17, the MOD signal must be applied to the OR circuit 14 before both of the signals N2 and N3 change to LOW. As shown in FIG. 1, the MOD signal is provided by the succeeding programmable frequency-divider circuit. The programmable frequency-divider circuit changes the state of the MOD signal after it has counted the output signal OUT of the two-modulus variable frequency-divider circuit. Accordingly, if the programmable frequency-divider circuit is of the type which detects a transition of the output signal OUT from the HIGH state to the LOW state, the switching of the state of the MOD signal must be done within the time interval of T1. On the other hand, if the programmable frequency-divider circuit is of the type which detects a transition from LOW to HIGH of the output signal OUT, the switching of the state of the MOD signal must be done within the time interval of T2.
In a conventional two-modulus variable frequency-divider circuit employing the arrangement shown in FIG. 2, the time intervals T1 and T2 available for switching the state of the MOD signals when the above-stated two types of the programmable frequency-divider circuits are used are considerably different from each other. For example, one may be more than twice as long as the other. In applications where the operation frequency of the two-modulus variable frequency-divider circuit is high, the time intervals available for the MOD signal state switching are also shorter, as a matter of course. Accordingly, in high frequency applications, the time intervals available for the MOD signal state switching are very important. For example, in the combination of the two-modulus variable frequency-divider circuit shown in FIG. 2 and the programmable frequency-divider circuit of the type which detects the change of from HIGH to LOW of the output signal OUT, the time interval available to the programmable frequency-divider circuit for switching the state of the MOD signal is the shorter time interval T1. Therefore, if a PLL frequency synthesizer is constructed by a two-modulus variable frequency-divider circuit and a programmable frequency-divider circuit of the above-stated type which cannot switch the state of the MOD signal at a high speed, the MOD signal state switching within the time interval of T1 may, disadvantageously, not be reliably done, which causes the two-modulus variable frequency-divider circuit not to have a correct frequency dividing factor and the frequency-divider output frequency deviates from a desired one.