1. Field of the Invention
The present invention relates to a master-slave multiplex communication system which allows a master communication device to synchronize with a slave communication device, bit multiplex the output of both the devices, and transmit the multiplexed output to another station at a high transmission rate, and particularly to the system having a function of changing over master and slave to each other.
2. Description of the Related Art
Also, the present invention relates to a PLL (phase synchronous loop) circuit utilized in the above-mentioned master-slave multiplex communication system, and particularly to the circuit capable of supplying a stable clock even if an interruption or sharp variation of an inputted clock occurs.
Heretofore, in some case, the output of two communication devices is bit multiplexed and communicated at a higher transmission rate. In this case, with one communication device set at master state, and the other communication device set at slave state, the clock on the slave side is allowed to synchronize with that on the master side, and the master and slave are changed over to each other as required. The configuration of such a conventional master-slave multiplex communication system is shown in FIG. 1. In FIG. 1, the broken line indicates a data signal, while the solid line indicates an input/output of a clock signal.
In FIG. 1, data signals outputted from a first, a second communication equipment 11, 12 are inputted into a multiplex processor (MUX) 13, in which the signals are bit multiplexed and outputted at a high transmission rate. With respect to clock signals, the first communication device 11 becomes a master state locked to a primary external reference clock (hereinafter called PE clock), and the second communication device 12 becomes a slave state locked to a P clock supplied from the first communication device 11, thereby keeping a synchronous state.
Now, if a trouble occurs in the PE clock, the second communication device 12 becomes a master state locked to a secondary external reference clock (hereinafter called PE clock), and the first communication device 11 becomes a slave state locked to an S clock supplied from the second communication device 12, thereby continuing to keep a synchronous state.
That is, the above-mentioned multiplex communication system can keep a synchronous relationship even when a clock trouble occurs by changing over the master and slave to each other between the first, the second communication devices 11, 12.
However, in the above-mentioned conventional multiplex communication system, when the master and slave are changed over, a sharp phase variation of clock occurs by the input of the MUX 13. The sharp phase variation causes a LOS (Loss of Frame) and an 00F (Out of Frame) in the MUX 13, which provides a problem. The state is shown in FIGS. 2A and 2B.
FIG. 2A shows a case where the first communication device 11 is in the master state, the second communication device 12 is in the slave state, and a phase difference Ts is 4/T. Also, FIG. 2B shows a case where the first communication device 11 is in the slave state, the second communication device 12 is in the master state, and a phase difference Ts' is 4/T. In this case, where the first communication device 11 is changed over from the master to slave, the first communication device 11 is delayed by the phase difference Ts' behind the second communication device 12 and locked, so that a phase variation of T/2 occurs.
As described above, in the conventional multiplex communication system, there has been a problem that when the master and the slave are changed over to each other, the multiplex processing inputs cause a sharp clock phase variation, thereby leading to a trouble of LOS and OOF in a multiplex processing part.
Now, in the above-mentioned multiplex communication system, respective master and slave communication devices have the PLL circuits, by which an internal clock in synchronism with an input clock is generated.
The PLL circuit used here is required to continue to generate a stable clock even if the input clock is interrupted or a sharp variation occurs due to the changeover of the master and the slave. For this reason, heretofore, the PLL circuit having a holdover function is widely used.
However, the configuration of the holdover function in the conventional PLL circuit has problems that fundamentally the accuracy is poor, and depending on the timing at which the clock is interrupted, the frequency of the output clock changes before and after the clock interruption is generated, and that it is easily affected by power voltage variation and temperature change. Also, depending on the device, there is a case where the holdover function cannot be loaded on the PLL circuit.
Although some PLL circuit uses a digital processing technique, in a conventional digital PLL circuit, because of the arithmetic processing delay of a digital filter, a change in control voltage may not follow a change in phase comparison output, whereby the synchronous pull-in may become difficult. That is, a sufficient capture range has not been obtained.
Also, although a problem does not exist relatively where the oscillating frequency of a voltage control oscillator is relatively low and the allowable range of a control voltage can be made relatively wide, a highly accurate synchronous pull-in processing becomes necessary where a oscillator having a high oscillating frequency and a narrow allowable range of a control voltage is used.
Also, in the PLL circuit, generally a reference clock signal employs a redundant configuration to obtain reliability. In this case, the transient response characteristics of a loop must be delayed to pull in a lock at the changeover of the signal. However, when the characteristics of a loop filter is made delayed, the response thereof in a steady-state operation also becomes delayed.