Insulated gate field effect transistors and, more particularly, metal-oxide-semiconductor (MOS) field effect transistors are voltage-controlled devices and have high input impedance. Because of their features, including the above-stated ones, which are advantageous over bipolar transistors, they are widely used as discrete devices or IC constituent devices which are operated in low frequency regions or in high frequency regions.
FIG. 1 shows a cross-section of a major portion of a conventional insulated gate field effect transistor (IGFET) having the most conventional structure. The IGFET 20 includes a substrate, for example, a P.sup.+ -type silicon (Si) substrate 10, a P-type silicon epitaxial layer 11 deposited on one surface of the substrate 10, and an insulating layer 12 of, for example, silicon oxide, overlying the surface of the epitaxial layer 11. The epitaxial layer 11 includes therein a source-side N-type lightly-doped-drain (hereinafter referred to as LDD) region or source region 16, and a N-type drain-side LDD region or drain region 17 spaced from the source-side LDD region 16 by a small distance l. On that portion of the insulating layer 12 which is above the portion of the layer 11 between the regions 16 and 17 having a length l, a gate electrode 13 is disposed. A passivation coating 18 is disposed on the insulating layer 12 and the gate electrode 13. For reasons attributable to a manufacturing process, which will be described later, the edges of the two LDD regions 16 and 17 facing each other extend beyond the edges of the gate electrode 13 into portions of the epitaxial layer 11 beneath the gate electrode 13. Thus, the regions 16 and 17 overlap the gate electrode 13 by lengths l.sub.1 and l.sub.2, respectively.
A manufacturing process for the IGFET with the above-described structure is now described with reference to FIG. 2.
First, the p.sup.+ -type Si substrate (not shown) is prepared. On a surface of the substrate, the P-type Si epitaxial layer 11 is deposited by, for example, CVD (chemical vapor deposition). On the surface of the Si epitaxial layer 11, the insulating layer 12 is formed by, for example, thermal oxidation. A metal film 13a for the gate electrode is deposited on the layer 12 by sputtering or vapor deposition. Next, a resist is applied over the metal film 13a, and, then, any known patterning technique is used to define a resist layer 14 at a location where the gate electrode is to be formed. Thus, a structure shown in FIG. 2(a) results.
Next, the resist layer 14 is used as a mask to etch the metal film 13a, which results in the gate electrode 13 having a desired length L (see FIG. 2(b)). Thereafter, the resist layer 14 on top of the gate electrode 13 is removed. Then, another resist layer 15 is deposited covering the exposed top surface of the gate electrode 13 and the exposed surface of the insulating layer 12. The resist layer 15 is patterned to remove that portion on the left hand side of the center of the gate electrode 13. Next, using the remaining right hand side portion of the resist layer 15 and the exposed portion of the gate electrode 13 as a mask, a conductivity determining impurity producing a conductivity type, N-type in this case, opposite to that of the epitaxial layer 11, is implanted to form the source-side LDD region 16, as shown in FIG. 2(c). Then, the resist layer 15 is completely removed, and an impurity producing the same conductivity type (N-type) as that used for the source-side LDD region 16 is implanted to a much lower amount (i.e. to a low concentration) to form the drain-side LDD 17.
Thereafter, annealing is carried out to stabilize the structure. The dopant impurity injected in the first implantation is diffused in the epitaxial layer 11 not only in the depth direction but also in the lateral direction into a portion beneath the gate electrode 13 during the implantation steps and in the succeeding annealing step, and the impurity injected in the second implantation step is diffused in the epitaxial layer 11 not only in the depth direction but also in the lateral direction into a portion of the layer 11 beneath the gate electrode 13, during the second implantation step and the annealing step. Thus, the overlapping portions having lengths l.sub.1 and l.sub.2 are formed (FIG. 2(d)).
Thereafter, a passivation coating 18 is deposited over the gate electrode 13 and the insulating layer 12, which results in the device shown in FIG. 1. In both of FIGS. 1 and 2, illustration and explanation of components, such as a source electrode, a drain electrode and electrode leads, which are not directly pertinent to the invention are omitted.
A high frequency cutoff frequency f.sub.T, which is one of indices indicative of high frequency characteristics of the IGFET of the above-described structure, is expressed as follows. EQU f.sub.T =gm/2.pi.Cgs
where gm is a transconductance of the IGFET and Cgs is the gate-source capacitance of the IGFET.
As is well known, the higher the high frequency cutoff frequency f.sub.T, the better the IGFET characteristics in high frequency regions. In the conventional structure of an IGFET shown in FIGS. 1 and 2, because the edge of the source-side LDD region 16 extends into the portion of the layer 11 beneath the gate electrode 13, the gate-source capacitance Cgs is large. As a result, the cutoff frequency f.sub.T is lowered, and the high frequency characteristics of the IGFET are degraded.
In order to improve the high frequency characteristics of the IGFET of the above-described structure, the dimensions of the gate electrode 13 should be reduced as much as possible. In order to minimize the dimensions of the gate electrode 13, a highly precise masking technique must be employed in manufacturing the gate electrode 13. In addition, after the formation of the gate electrode 13 of such small dimensions, in order to form the source-side and drain-side LDD regions 16 and 17 by diffusing different amounts of impurities for the respective regions, a highly precise patterning and masking technique has to be employed to define the edge of the resist layer 15 on the gate electrode 13 (FIG. 2c). For higher operating frequencies, the dimensions of the gate electrode 13 become smaller so that higher precision is required for the two masking steps, which makes the manufacturing process complicated and requires a high degree of skill and much care. Accordingly, the manufacturing yield is significantly reduced.
Therefore an object of the present invention is to provide a semiconductor device with improved high frequency characteristics.
Another object of the present invention is to provide an insulated gate field effect transistor which has a small gate-source capacitance and, hence, good high frequency characteristics.
Still another object of the present invention is to provide an insulated gate field effect transistor having a significantly small gate length and having no overlap between a gate electrode and a source-side LDD region so that the gate-source capacitance is very small, which significantly improves high frequency characteristics.
A further object of the present invention is to provide a novel method of fabricating a semiconductor device having improved high frequency characteristics.
A still further object of the present invention is to provide an improve method of fabricating an insulated gate field effect transistor having a small gate-source capacitance and, hence, improved high frequency characteristics.