Field programmable gate arrays (FPGAs) include logic blocks connectable through a programmable interconnect structure. The interconnect structure typically provides for connecting each logic block to each other logic block.
Several U.S. Patents show such structures for interconnecting logic blocks in FPGAs. Freeman in U.S. Reissue Patent Re 34,363, Carter in U.S. Pat. No. 4,642,487, Greene et al in U.S. Pat. No. 5,073,729, Kean in U.S. Pat. No. 5,469,003, Pierce et al in U.S. Pat. No. 5,581,199 and pages 4-32 through 4-37 of the Xilinx 1996 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, incorporated herein by reference all describe interconnect structures. Tavana et al in commonly assigned, co-pending U.S. application Ser. No. 08/618,445 also describes a routing interconnect structure.
In addition to the routing structures discussed above, FPGAs have also included structures for performing special functions, in particular fast carry lines for connecting the carry output of one bit generated in one logic block to the carry input of the next bit generated in the next logic block, and cascade lines for allowing wide functions to be generated by combining several adjacent logic blocks. Carry structures are discussed by Hsieh et al. in U.S. Pat. No. 5,267,187 M-1230-1F! and by New in U.S. Pat. No. 5,349,250 M-2565!. Cascade structures are discussed by Goetting et al in U.S. Pat. No. 5,365,125 docket M-1743-1! and by Chiang et al. in U.S. Pat. No. 5,357,153 docket M-2183!. These patents are also incorporated herein by reference. Some of the fast carry architectures also include dedicated XOR gates for generating the sum when arithmetic functions are being implemented. The cascade architectures allow wide AND, NAND, OR, and NOR functions to be generated but do not allow wide XOR and XNOR functions to be generated. Since wide XOR and XNOR functions are desirable for such applications as parity checking and generation used widely in PCI and many other applications, it would be advantageous to be able to generate these functions as well.