1. Field of the Invention
The disclosed technology generally relates to photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions.
2. Description of the Related Technology
Photovoltaic devices comprising interdigitated back contact (IBC) cells can improve efficiency of the photovoltaic devices by having electrical contacts formed at the rear side of the cell. By having the electrical contacts formed at the rear side of the cell, shading effects that can result from electrical contacts formed in the front side of the cell can be reduced or eliminated, thereby increasing the overall photovoltaic conversion efficiency. In an IBC cell, interdigitated n+ regions (e.g. forming a back surface field region) and p+ regions (e.g. forming an emitter region) and corresponding interdigitated n-type contacts and p-type contacts are typically used at the rear side of the cell.
In silicon heterojunction IBC cells, the emitter regions and the back surface field regions are formed by providing an appropriately doped amorphous silicon layer on a crystalline silicon substrate (amorphous silicon/crystalline silicon heterostructure). The p+ regions are formed by locally providing a p+-type amorphous silicon layer on a crystalline substrate according to a first pattern, and the n+ regions are formed by locally providing an n+-type amorphous silicon layer according to a second pattern, the first pattern and the second pattern being interdigitated.
When fabricating such silicon heterojunction IBC cells, there is a need for providing a good electrical isolation and thus avoiding parasitic shunts between the patterned n+ amorphous silicon layer and the patterned p+ amorphous silicon layer.
For example, in US 2009/0293948 a method is described wherein isolation between the n-type a-Si:H (hydrogenated amorphous silicon) layer and the p-type a-Si:H layer is realized by depositing a very thin intrinsic buffer layer after patterning the n-type a-Si:H layer and before depositing the p-type a-Si:H layer. This method comprises: depositing on a crystalline silicon substrate an intrinsic a-Si:H buffer layer and an n-type doped a-Si:H layer over the whole surface of the substrate; fixing a metallic mask on which a comb shaped grid has been opened on the n-type doped a-Si:H covered crystalline silicon wafer; patterning the n-type a-Si:H layer, the patterning comprising removing the n-type a-Si:H not covered by the mask by a dry etching procedure; depositing a thin intrinsic buffer layer through the mask; and depositing a p-type doped a-Si:H layer through the same mask. In a production environment, the use of a metallic mask is disadvantageous because the metallic mask needs to be attached or fixed to the substrate, and needs to be cleaned or replaced regularly because a-Si:H layers are deposited on the mask.
In U.S. Pat. No. 7,737,357 a method is described wherein separation between the n-type a-Si:H layer and the p-type a-Si:H layer is realized by means of a silicon oxide layer that is deposited by a low pressure chemical vapor deposition process. Providing the silicon oxide layer requires an additional deposition step, which may affect the p-type a-Si:H layer on which it is deposited.