An accumulation-mode field-effect transistor, sometimes referred to herein as an "ACCUFET", is a trench-type MOSFET which requires no body region and hence no PN junctions. The region between the trenched gates, sometimes called a "mesa", is made relatively narrow, and the gate material (typically polysilicon) is normally doped in such a way that it has a work function which depletes the entire mesa region. The current path extends vertically through the mesa to the substrate. The trenches are sometimes formed entirely in an epitaxial layer which is grown on the substrate.
A cross-sectional view of a typical ACCUFET 10 is illustrated in FIG. 1, with the ACCUFET being connected as a low-side switch between a load L and ground. A trenched gate 11 is etched in a silicon material 12, which includes an N-epitaxial layer 13 grown on an N+ substrate 14. Trenched gate 11 defines a cell 10A. An N+ region 15 is formed at the surface of the inverted mesa between gate 11. In a typical ACCUFET, gate 11 would be formed of polysilicon doped with P-type dopant to a concentration of 1.times.10.sup.18 to 5.times.10.sup.19 cm.sup.-3, and the N-epitaxial layer 13 would be doped to a concentration of 1.times.10.sup.14 to 1.times.10.sup.15 cm.sup.-3. For purposes of identification, unless otherwise indicated the N+ region 15 will be referred to herein as the "source" and the N+ substrate 14 will be referred to as the "drain", regardless of the polarity of the voltage applied to ACCUFET 10.
The cells of an ACCUFET may be in the form of longitudinal stripes, as shown in FIG. 15A, or they may be in the form of a closed figure such as a hexagon, square, polygon or other shape, as shown in FIG. 15B.
ACCUFET 10 is turned off when the gate voltage is equal to the source voltage (i.e., V.sub.gs =0). If V.sub.gs is increased, the depletion regions surrounding the gates (shown by the dashed lines) contract and open a current path between the source and the drain. With further increasing V.sub.gs the depletion regions continue to contract until eventually accumulation regions are formed adjacent the trenches, enhancing channel conduction and further lowering the on-resistance of the device.
This sequence of events is illustrated in FIGS. 2A, 2B and 2C, FIG. 2A showing ACCUFET 10 in the off condition; FIG. 2B showing ACCUFET 10 turned partially on, with V.sub.gs reaching a voltage somewhat analogous to the threshold voltage V.sub.t of an ordinary MOSFET; and FIG. 2C showing ACCUFET 10 turned fully on, with the accumulation regions being designated by the numerals 19. In FIGS. 2B and 2C the arrows represent the flow of electrons from the source to the drain.
Additional information concerning ACCUFETs is given in U.S. Pat. No. 4,903,189 to Ngo et al.; B. J. Baliga et al., "The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET", IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pp. 427-429; and T. Syau et al., "Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's", IEEE Electron Device Letters, Vol. 41, No. 5, May 1994, pp. 800-808, each of which is incorporated herein by reference in its entirety.
ACCUFETs can be fabricated with a very high cell density and a very low on-resistance. Nonetheless, despite these advantages, for several reasons ACCUFETs have not so far achieved widespread use in the field of power semiconductor devices. Two of the principal reasons are their inability to withstand high voltages when they are in an off condition and their inability to block voltages bidirectionally, which in turn has prevented them from being used as AC switches.
These problems are illustrated in FIGS. 3, 4A, 4B, 5A, and 5B. FIG. 3 shows ACCUFET 10 connected as a high-side battery disconnect switch between a battery B and load L. A battery charger A is also connected on the load side of ACCUFET 10. Gate 11 is grounded when ACCUFET is turned off. In this condition, gate oxide layer 11A in the vicinity of the N+ source region 15 must be able to withstand the entire battery voltage.
FIG. 4A shows battery B as a two-cell lithium ion battery whose peak voltage is 4.2V per cell or a total of 8.4V. ACCUFET 10 is turned off, with gate 11 being grounded. The source of ACCUFET 10 is tied to 8.4V and the drain of ACCUFET 10 is at 0V because load L is represented as a discharged capacitor in this case. FIG. 4B is a detailed view of the source and gate of ACCUFET 10 showing the equipotential lines squeezed together in the gate oxide 11A. Gate oxide 11A must absorb essentially the entire voltage drop between the battery (V.sub.batt) and the grounded gate.
FIG. 5A shows the situation with battery B completely discharged and battery charger operating to provide a voltage (V.sub.charger) of 12V. Again, ACCUFET 10 is turned off by grounding gate 11. Here the main voltage drop occurs between the gate and the drain, and FIG. 5B shows the equipotential lines in this region of the ACCUFET. While the total voltage drop is higher than in the situation of FIGS. 4A and 4B, in this embodiment a portion of the N-epitaxial layer lies between the bottom of the gate trench and the N+ substrate and thus part of the voltage drop is absorbed by the depleted N-epitaxial region. Therefore, the stress on the gate oxide may actually be lower than in the case shown in FIG. 4A. Nonetheless, in either of the cases illustrated in FIGS. 4A and 5A, there is a significant risk that the gate oxide will be exposed to excessive voltages and will be damaged or ruptured as a result. This is particularly true in the commonplace situation where the load has inductive components that generate voltage spikes as it is switched. The inability of ACCUFETs to withstand these voltage spikes has seriously limited their use in the power MOSFET field.