1. Technical Field
Various embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device for reducing a standby current.
2. Related Art
In general, various attempts have been made to reduce power consumption of a semiconductor memory device, or particularly, a power required during a standby mode as well as an operating voltage during an active mode of a semiconductor memory device in the case of a mobile product. Therefore, technologies for stably reducing an operating voltage of a memory module inside a chip have been proposed. Examples of the technologies may include a technology which converts an external voltage into an internal voltage and uses the internal voltage.
FIG. 1 is a conceptual block diagram of a conventional semiconductor memory device which generates and uses an internal voltage.
Referring to FIG. 1, an internal voltage generator 1 receiving an external voltage VCCE generates first and second internal voltages VCCI and VDC_PB having a voltage level reduced by a predetermined amount from the external voltage VCCE.
Between the first and second internal voltages VCCI and VDC_PB, the first internal voltage VCCI may be used in a logic data path unit 2, an analog peri circuit unit 3, and a high voltage pump circuit unit 7 of an internal circuit 8, and the second internal voltage VDC_PB may be used as power for a page buffer 6 coupled to a cache buffer 4 and a main buffer 5.
The reason to use the first and second internal voltages VCCI and the VDC_PB without directly using the external voltage VCCE is to reduce the entire operating current and provide a constant internal voltage to secure the stability of operation even though the external voltage VCCE is changed. Furthermore, the first and second internal voltages VCCI and VDC_PB may have substantially the same level. However, the internal voltages are separately used for a specific circuit unit (for example, page buffer) to prevent a peak current from occurring during operation or prevent the influence of the peak current.
FIG. 2 is a simple block diagram of the internal voltage generator 1.
Referring to FIG. 2, the internal voltage generator 1 includes a bandgap voltage generator 11, a Widlar voltage generator 12, a VCCI active driver 13, a VCCI standby driver 14, a VDC_PB active driver 15, and a standby control unit 16.
The bandgap voltage generator 1 is a reference voltage generator to generate a constant voltage for PVT (Process/Voltage/Temperature) variations. For example, the bandgap voltage generator 1 generates a first reference voltage VREF1 in response to an active enable signal ACTEN. The first reference voltage VREF1 generated by the bandgap voltage generator 1 is provided to the VCCI active driver 13 and the VDC_PB active driver 15.
The VCCI active driver 13 and the VDC_PB active driver 15, receiving the first reference voltage VREF1, may provide a regulated voltage through an operational amplifier provided therein. Thus, the VCCI active driver 13 provides the first internal voltage VCCI, and the VDC_PB active driver 15 provides the second internal voltage VDC_PB.
During an active mode, the active enable signal ACTEN is activated to operate the bandgap voltage generator 1, the VCCI active driver 13, and the VDC_PB active driver 15. During the other modes, the active enable signal ACTEN is deactivated to disable the bandgap voltage generator 1, the VCCI active driver 13, and the VDC_PB active driver 15.
The Widlar voltage generator 12 operates in response to a standby enable signal STBYEN, and generates a second reference voltage VREF2.
The second reference voltage VREF2 is provided to the VCCI standby driver 14.
The VCCI standby driver 14 is a small-sized driver that consumes a relatively small amount of current when operating. Since only a minimum voltage required for retaining data may be provided during the standby mode, the VCCI standby driver 14 has a small driving ability.
The reason to use the Widlar voltage generator 12 is that the Widlar voltage generator 12 is a reference voltage generator which is driven by a smaller amount of current than the bandgap voltage generator 11.
During the standby mode, the VCCI standby driver 14 and the standby control unit 16 are enabled.
The standby control unit 16 includes an inverter IV1 and a PMOS transistor P1.
The PMOS transistor P1 is turned on in response to the standby enable signal STBYEN.
Thus, during the standby mode, the voltage provided through the VCCI standby driver 14 may be commonly applied as the first and second internal voltages VCCI and VDC_PB.
During the standby mode, the Widlar voltage generator 12 is used to reduce a larger amount of current than during the active mode, and one common VCCI standby driver 14 is used to apply the same voltage level as the first and second internal voltages VCCI and VDC_PB, without using individual standby drivers. However, as the technology is gradually advanced and mobile applications require a very small standby current, there is a demand for reducing a current.