A circuit having a relatively high output impedance will be excessively loaded if it drives a circuit having a relatively low input impedance. To circumvent this problem, it is conventional to isolate the low input impedance through a voltage buffer or driver. The voltage driver typically includes a differential amplifier that has a relatively high input impedance so that the high-output-impedance circuit can readily drive the voltage driver without excessive loading. Through negative feedback from the driver output to the differential amplifier, the voltage driver then maintains an output node voltage equaling (or proportional to) the driver input node voltage despite the diverse impedances. One common form of a voltage buffer or driver is a push-pull driver 100 shown in FIG. 1. An NMOS source-follower output transistor M2 and a PMOS source-follower output transistor P2 provide a low output impedance at their sources, which also comprise a driver output node 120. In contrast, a push-pull driver input node 125 has a high input impedance as it couples to the positive input of a differential amplifier 105. Output node 120 couples back to the negative input of differential amplifier 105 to set up the desired negative feedback. Differential amplifier 105 drives the sources of an NMOS diode-connected bias transistor M1 and a PMOS diode-connected bias transistor P1.
A current source 115 drives the drain of diode-connected bias transistor M1. Similarly, a current source 110 biases the drain of diode-connected bias transistor P1. Suppose that an output voltage (Vout) on output node 120 has drifted lower than an input voltage (Vref_in) on input node 125. The negative feedback through differential amplifier 105 will then increase the source voltage for diode-connected bias transistor M1, which in turn causes its drain voltage to increase. This increased drain voltage drives source-follower output transistor M2 to source more charge to output node 120 (the push in the push-pull configuration) to restore the output voltage Vout to equal the input voltage Vref_in. Conversely, if the output voltage Vout rises higher than the input voltage Vref_in, differential amplifier 105 will lower the source voltage for diode-connected bias transistor P1, which in turn causes its drain voltage to decrease. This decreased drain voltage causes source-follower output transistor P2 to conduct more current, withdrawing charge from output node 120 (the pull in a push-pull configuration). In this fashion, the output voltage Vout follows the input voltage Vref_in despite the divergent impedances.
Although push-pull driver 100 advantageously maintains the output voltage Vout at the desired value despite the different impedances, it presents some design problems with regard to satisfying all process corners. For example, note that the drain-to-source voltage (Vds) for diode-connected bias transistor M1 is its threshold voltage (Vt) as well as its gate-to-source voltage (Vgs). This drain-to-source voltage is in turn controlled by the bias current from current source 115. But the drain-to-source voltage Vds for corresponding source-follower output transistor M2 is the power supply voltage VDD minus the output voltage Vout. Because of this mismatch between their drain-to-source voltages, there is a wide static current variation across the various process corners for source-follower output transistor M2 as compared to diode-connected bias transistor M1 due to, for example channel-length modulation effects. A similar mismatch exists between diode-connected bias transistor P1 and source-follower output transistor P2.
This mismatch is plainly undesirable as one must design for the worst-case process corner. For example, suppose that one designs for a current of I conducted by the source-follower output transistors at the worst-case process corner. At another process corner, these same transistors may conduct a current of 2I, which then wastes power. Accordingly, there is a need in the art for improved push-pull buffers with reduced static current variation.