Steep increases in speeds in communication channels, along with lower bit error rate tolerances, impose tighter jitter requirements for most circuit blocks in a transceiver system. Time domain jitter has a direct impact on the bit error rate and eye closure in a transmitter. One of the sources of jitter is the clock path. The clock generator or clock recovery Phase Locked Loop (PLL) circuits contribute to that. Minimizing clock jitter can greatly reduce eye closure and help achieve higher bit error rates. In case of standard parts, the system is designed for a broad variety of reference clock oscillators as an input to the PLL, and the PLLs are not customized for a particular application. The bandwidth of the PLL has a direct impact on the clock jitter. If the PLL bandwidth can be adaptive, it can reduce the overall system jitter. This application discusses a technique for measuring the phase noise of the oscillator clock and using that as a figure of merit to modulate the PLL bandwidth to reduce the overall system jitter and, hence, enhancing the system performance.
In a charge pump based PLL, the bandwidth is controlled by the value of the current output of the charge pump, the value of the zero (adding) resistor in the loop filter and the gain of the oscillator. In this application, a technique is provided wherein the phase noise of the oscillator clock is measured and the output is manipulated to alter the current of the charge pump in order to achieve an optimal PLL bandwidth. This, in turn, helps reduce overall clock path and system jitter. Commonly owned patent application Ser. No. 10/707,121, filed Nov. 21, 2003, entitled VARIATION OF EFFECTIVE FILTER CAPACITANCE IN PLL LOOP FILTERS, incorporated by reference, explains in greater detail the procedure and benefit of changing the charge pump current inside a PLL.