This invention applies to the field of power conversion, and, more particularly, to the field of DC-to-DC conversion, such as may be used for relatively low voltage and relatively high current applications generally requiring substantially high efficiency.
For isolated low voltage high current power supply circuits that generally use semiconductor devices such, as power transistor rectifiers, diodes, e.g. Schottky diodes, etc., the power loss in the rectifiers is usually dominant. As will be appreciated by those skilled in the art, synchronous rectification is generally necessary when the output voltage is below about 5 V, because the voltage drop (e.g., 0.3 V) of even the best of Schottky diodes takes or consumes an excessive percentage of the output voltage. The poor efficiency caused by using such Schottky diodes may also increase the thermal stress in the primary side semiconductor devices, the power components of the front-end converters (ac/dc, etc.), and the power distributing paths, because the input power of the low voltage power supply increases substantially. Therefore, using a Schottky diode may increase thermal stress on both the rectifier itself and the overall power converter system.
A presently available state-of-the-art low-voltage power transistor, such as a metal oxide semiconductor field effect transistor (MOSFET) may provide as low as 4 mohm of on-resistance when it is properly driven. If, for example, the current stress on each rectifier device is below about 30 A, synchronous rectification using such low on-resistance MOSFETs will in general yield a performance superior to that of a Schottky diode. Consequently, synchronous rectification is generally a well-desired technique of power conversion for low voltage, high current power conversion applications.
FIGS. 1(a)-1(c) collectively show a representative prior art power conversion system 10, using a transformer core 12 electromagnetically coupled to respective primary and secondary windings 14 and 16 respectively. Primary winding 14 may have a respective number of turns (Np) and is generally coupled to receive an input waveform, such as input waveform 17 to induce a switching signal Vs across secondary winding 16 having a respective number of turns (Ns). Two synchronous rectifiers (SR) or power transistors Q3 and Q4 are electronically coupled in a common-source configuration, as shown in FIG. 1, to facilitate the respective gate driving of power transistors Q3 and Q4. As used herein the terminology of synchronous rectifiers and power transistors will be used interchangeable, unless otherwise indicated. FIG. 1(a) shows the arrangement of SRs Q3 and Q4 in a two-inductor output circuit as represented by output inductors 18 and 20, while FIG. 1(b) describes the case with a one-inductor output circuit, as represented by single inductor 18. It will be appreciated that secondary winding 16 could be a center-tapped winding and thus output inductor 18 could be connected to a suitable center-tap connecting point in lieu of connecting point C. The common architecture of these two circuits cases is shown in FIG. 1(c). In the following discussion, the diagram shown in FIG. 1(c) will be used to describe various known driving schemes of SRs Q3 and Q4. As will be readily appreciated by those skilled in the art, each SR has respective terminals such as gate, drain and source terminals, designated by the letters G, D and S, respectively.
As shown in FIG. 2 and FIG. 3, respectively, there are two prior-art driving schemes for SRs Q3 and Q4. The two schemes are generally known as external driving and direct self-driving, respectively. Although an external driving circuit, such as shown in FIG. 2, may be able to provide a somewhat adequate driving or gating voltage on the respective gates of SRs Q3 and Q4, unfortunately, as explained below, there are several limitations in this technique. For example, it will be appreciated that SRs Q3 and Q4 are generally low voltage high current MOSFETs, which generally have excessively large gate capacitance. Thus, SR MOSFETs having lower values of static drain-source on-state resistance, (R.sub.ds,on) tend to have higher gate drive loss. Further, presently available MOSFET drivers, such as MOSFET drivers 22 and 24, are generally not able to provide the required driving current at high switching frequency. The external drive scheme also requires delicate control on the gate driving timing. To maximize the conduction time of the two SRs without losing zero-voltage turn-on and causing cross-conduction between one another, the gate timing has to be very accurately controlled. Therefore, a practical switching frequency when employing an external driving technique is usually limited to about 30-40 KHz. This relatively low switching frequency increases the overall size of the power converter.
A direct self-driving circuit is shown in FIG. 3 and since a respective body diode of the SRs will generally conduct before its respective MOSFET portion, zero-voltage turn-on of each SR may be achieved without undue difficulty in such self-driving circuit. Further, since most of the energy stored in a respective gate capacitor of each SR is recovered, the driving loss is somewhat reduced. Thus, the switching frequency for most silicon-based synchronous rectifiers using the direct self-driving technique can be pushed to around 500 KHz. Unfortunately, as described below, there are still substantial limitations in the direct self-driving technique. By way of illustration such technique:
i) may only be suitable for circuit topologies whose secondary voltage amplitude has only two states: positive and negative. For circuits whose transformer winding provides substantially zero voltage amplitude during a certain interval of the switching period, e.g., a two-switch forward, a resonant reset forward or a standard half-bridge (H-B) converter, this technique is not suitable. Thus, in a forward converter configuration, a cumbersome active-clamp reset scheme would be necessary for applying this gate drive scheme; conversely, in HB circuits, it is believed that only an asymmetrical duty cycle control would be capable of implementing a direct self-driven synchronous rectification technique; PA0 ii) may be unsuitable for very high or very low output voltage because the transformer secondary side voltage will generally be out of range for driving the MOSFET gate. The output voltage range for applying this technique is usually limited to a voltage range of about 2.5 V.about.7.5 V; PA0 iii) does not provide over-voltage protection on the SR's gate. This may cause reliability problems and increased operational costs; and PA0 iv) does not allow for building flexible power converter architectures, such as modular architectures, since power converter modules having directly self-driven SRs cannot be paralleled. As shown in FIG. 4, for example, if a second power converter module 26 is powered up before a first power converter module 28, the output bus voltage will be coupled the respective gates of SRs Q3 and Q4 in module 28. When the output bus voltage is large enough, both SRs in module 28 will be biased on, and thus resulting in a highly undesirable short circuit on the output side.
It will be appreciated that power converters capable of being expanded through a modular architecture, such as with parallel coupling, are very important to high current applications, which may require thousands of amperes of current. Thus, the direct self-drive scheme is not suitable for many such applications.