1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more specifically to a structure for deselecting broken select lines in memory arrays.
2. Background of the Invention
Many memory devices with a redundancy scheme have broken select lines in the memory array. Memory devices that are subject to broken select lines include static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable read only memories (EEPROMs), Flash EEPROMs, and other specialty memory devices such as tag RAMs and Zeropower.RTM. devices. A recent trend in the memory device field is to use more redundancy as the density of such devices increases. As the density of memory devices having broken select lines increases, problems associated with these broken select lines increase as well.
In SRAM technology, the select lines for a memory array are connected to a large number of memory cells, or local row decoders, in the array. Typical select lines may include a row line, a master row line, a word line, or an X-Line. These lines select, in a parallel fashion, the memory cells or local row decoders necessary to access a particular portion of the memory array. When that portion of the memory array is not to be selected, the select lines are held in a deselect state to disable all connected cells or local row decoders.
In the DRAM prior art, word select lines perform the same function as outlined above. Word lines are held at a low logic level at both ends by devices, often called holding devices, which are capable of maintaining this low logic level on unselected word lines in the presence of strong capacitive coupling from a selected word line and from bit lines--half or more of which have positive-going transitions during the cycle. DRAM row lines are high impedance such that a holding transistor placed on one end of the row line is not sufficient to hold the entire length of the row line in a deselected state. A quite word flip-flop or other deselect scheme is often used to provide clamping means which prevent bouncing of word lines or row lines. Later improvements in the development of DRAMs provided precharge, such as V.sub.cc /2, that balances this coupling for selection, separation and equilibration of bitlines to the word lines, thus making holding devices less important.
In contrast, traditionally the number of SRAM bit lines driven during any given cycle is small, so that problems are not encountered with coupling of these bit lines to the word lines in the memory array. Thus, select lines have been held deselected at one end only, and holding devices have not been needed on both ends of a SRAM select line. However, there can be a problem with sections of broken select lines in the memory array. When the array is repaired by substituting spare or redundant elements for broken select lines, the end of each of these broken select lines near the driver is held deselected, but the far end of a broken select line may not be held deselected and may float. Floating broken select lines may drift in a selected direction, causing high standby current, and, in extreme cases, of may produce enough bit line current from connected cells to disrupt the operation of some of the connected bit lines. Unlike the DRAM, however, there is no strong coupling which drives these lines positive.
Therefore, it would be desirable in the art to prevent the charging of floating select lines in memory arrays with little or no adverse effect on the speed or selection of select lines. Prevention of high standby current or bitline current is especially desirable as memory devices become more dense and use more redundancy. Additionally, it would be desirable in the art that any approach taken to prevent the charging of floating select lines in memory arrays use as little additional layout area as possible. This is especially desirable as memory devices become more dense.