It is well known that the correct operation of synchronous digital circuits requires that, for example, data signals should not exhibit signal transitions within the set up or hold times of circuits which are governed by clock signals that define synchronous operation. If this operational condition is not observed, the phenomenon of metastability arises, wherein for example a bistate circuit does not reach a well-defined logical state (zero or one) within a normal time but instead lingers in an indetermined or metastable state which cannot be unambiguously interpreted by a subsequent circuit. The nature and possible duration of this state is well discussed in the literature, for example by Peter A. Stoll in VLSI Design, November/December 1982, pages 56 to 59 and by Kleeman et al., IEEE Design & Test of Computers, December 1987, pages 4 to 18. As the aforementioned references explain, synchronizers are particular susceptible to metastability by virtue of the particular task they perform, by converting asynchronous data into synchronous data. It is known, for example, to employ a D-flip-flop as a synchronizer. Such a flip-flop is susceptible to a metastable condition if a transition in the asynchronous data occurs at substantially the same time as a relevant clock signal transition.
Various expedients have been proposed to mitigate the incidence of metastability. They include the use of fast devices, extended decision times, a pausable clock, a Schmitt synchronizer and redundancy and masking. These proposals are fully discussed in the references aforementioned and they all have attendant disadvantages.
The object of the present invention is to mitigate the effect of metastability in digital circuits, particularly synchronizers, so as to increase substantially the mean time between failures due to the occurrence of a metastable condition. It is a further object of the present invention to provide specific circuit means which are applicable to CMOS synchronizers and which render those synchronizers less susceptible to metastable failure.
These and other objects of the invention are achieved by a technique which involves level shifting either within a synchronizer stage or between synchronizer stages. In a particular implementation of the invention, this level shifting is achieved by altering the relative proportions of at least one complementary pair of devices in a synchronizer in order to shift the level of a metastable voltage outside the range of a fatal voltage window possessed or exhibited by an adjacent or following part or stage of the synchronizer. By this means, although the occurrence of a metastable condition cannot be avoided, the likelihood of propagation of the metastable condition throughout the synchronizer may be very significantly reduced.