The present invention relates to a level converter circuit and a liquid crystal display device employing the level converter circuit, and in particular to a level converter circuit formed by polysilicon transistors.
Liquid crystal display modules of the STN (Super Twisted Nematic) type or the TFT (Thin Film Transistor) type are widely used as a display device for a notebook personal computer and the like. Some driver circuits for driving such liquid crystal display panels need a level converter circuit external to the liquid crystal display panel. Such a level converter circuit is disclosed in Japanese Patent Application Laid-open No. Hei 6-204,850 (laid-open on Jul. 22, 1994), for example.
FIG. 13 is a circuit diagram of an example of a prior art level converter circuit. The level converter circuit shown in FIG. 13 is formed by MOS transistors using single crystal silicon for their semiconductor layers, and is of the same circuit configuration as that shown in FIG. 4 of Japanese Patent Application Laid-open No. Hei 6-204,850.
The level converter circuit shown in FIG. 13 has a CMOS inverter INV1 to which a low-voltage input signal Ø1 is supplied and a CMOs inverter INV2 to which an output signal Ø2 from the CMOS inverter INV1 is supplied.
The CMOS inverter INV1 is formed by a p-channel MOS transistor (hereinafter referred to as a PMOS) M5 and an n-channel MOS transistor (hereinafter referred to as an NMOS) M6 which are connected in series between a low voltage VCC and a reference voltage (or ground potential) Vss.
The CMOS inverter INV2 is formed by a PMOS M7 and an NMOS M8 which are connected in series between the low voltage VCC and the reference voltage (or ground potential) Vss.
Further, the level converter circuit includes a series combination of a PMOS M9 and an NMOS M11 and a series combination of a PMOS M10 and an NMOS M12, which are connected between a high voltage VDD and the reference voltage VSS.
An output signal Ø3 from the CMOS inverter INV2 is supplied to a gate electrode of the NMOS M11, and an output signal Ø2 from the CMOS inverter INV1 is supplied to a gate electrode of the NMOS M12. A gate electrode of the PMOS M9 is connected to a drain electrode of the PMOS M10, and a gate electrode of the PMOS M10 is connected to a drain electrode of the PMOS M9.
The input signal Ø1 supplied via an input terminal VIN has an amplitude between the low voltage VCC and the reference voltage VSS, and is converted into the low voltage outputs Ø2 and Ø3 each having amplitudes between the low voltage VCC and the reference voltage VSS.
The low voltage output signals Ø2 and Ø3 are supplied to gate electrodes of the NMOS M11 and the NMOS M12, respectively, and outputs from output terminals VOUT1 and VOUT2 are two level-converted signals, that is, two complementary output signals Ø4 and Ø5 having amplitudes between the high supply voltage VDD and ground potential VSS, respectively.
For example, suppose that the low voltage output signal Ø2 is at a high level (hereafter referred to merely as an H level) and the low voltage output signal Ø3 is at a low level (hereafter referred to merely as an L level). Then the NMOS M12 is ON, PMOS M9 is ON, NMOS M11 is OFF, and PMOS M10 is OFF, and therefore the output terminal VOUT2 outputs the ground potential VSS and the output terminal VOUT1 outputs the high voltage VDD.
Next, suppose that the low voltage output signal Ø2 is at the L level and the low voltage output signal Ø3 is at the H level. Then the NMOS M12 is OFF, the PMOS M9 is OFF, the NMOS M11 is ON, and the PMOS M10 is ON, and therefore the output terminal VOUT2 outputs the high supply voltage VDD and the output terminal VOUT1 outputs the ground potential VSS.
FIG. 14 is a circuit diagram of another example of a prior art level converter circuit. The level converter circuit shown in FIG. 14 is also formed by MOS transistors using single crystal silicon for their semiconductor layers, and is of the same circuit configuration as that shown in FIG. 1 of Japanese Patent Application Laid-open No. Hei 6-204,850.
The level converter circuit shown in FIG. 14 differs from that shown in FIG. 13, in that the CMOS inverter INV2 is omitted, the output signal Ø2 from the CMOS inverter INV1 is supplied to the source electrode of the NMOS M11, and the gate of which is supplied with the low voltage VCC.
In the level converter circuit shown in FIG. 13, when the level-converted output signals Ø4, Ø5 from the output terminals VOUT1, VOUT2 change from the H level to the L level, or from the L level to the H level, all of the PMOS MS, the NMOS M11, the PMOS M10 and the NMOS M12 are turned ON simultaneously, and consequently, currents flow through a series combination of the PMOS M9 and the NMOS M11 and a series combination of the PMOS M10 and the NMOS M12, respectively. The level converter circuit shown in FIG. 14 is configured so as to prevent such currents from flowing through the series combination of the PMOS M9 and the NMOS M11 and the series combination of the PMOS M10 and the NMOS M12.
The level converter circuit shown in FIG. 13 needs a total of eight MOS transistors comprising four MOS transistors M5 to M8 in the low-voltage circuit and four MOS transistors M9 to M12 in the high-voltage circuit, the level converter circuit shown in FIG. 14 needs six MOS transistors, and therefore the prior art level converter circuits had the problem in that many MOS transistors are needed.
It is known that mobility in MOS transistors using as their semiconductor layers, single crystal silicon, polysilicon and amorphous silicon are 1,000 to 2,000 cm2/(V·s), 10 to 100 cm2/(V·s), and 0.1 to 10 cm2/(V·s), respectively. MOS transistors using as their semiconductor layers, polysilicon and amorphous silicon are capable of being fabricated on a transparent insulating substrate made of quartz glass or glass having a softening temperature not higher than 800° C., and therefore electronic circuits can be fabricated directly on a display device such as a liquid crystal display device.
FIG. 15 is a graph showing an example of switching characteristics of an n-channel MOS transistor having a semiconductor made of single crystal silicon, and FIG. 16 is a graph showing an example of switching characteristics of an n-channel MOS transistor having a semiconductor layer made of polysilicon.
In FIGS. 15 and 16, curves A represent characteristics for a standard threshold VTH, curves B represent characteristics for a threshold voltage VTH shifted by −1 V from the standard threshold voltage, and curves C represent characteristics for a threshold voltage VTH shifted by +1 V from the standard threshold voltage.
As is understood from FIGS. 15 and 16, in the case of the polysilicon MOS transistor (a polysilicon thin film transistor, for example) using as a semiconductor layer a polysilicon obtained by a solid phase epitaxy method crystallizing at a temperature of 500° C. to 1,100° C., or a polysilicon obtained by crystallizing by laser-annealing amorphous silicon produced by a CVD method, when a gate-source voltage VGS is small (5 V or less), drain currents ID of the polysilicon MOS transistor is smaller than those of the MOS transistor having the semiconductor layer of single crystal silicon, and drain currents ID of the polysilicon MOS transistor vary greatly with variations of the threshold voltages VTH.
As a result, when the level converter circuits shown in FIGS. 13 and 14 are formed by MOS transistors having semiconductor layers made of single crystal silicon, satisfactory operation can be guaranteed, but when the level converter circuits shown in FIGS. 13 and 14 are formed by polysilicon MOS transistors having semiconductor layers made of polysilicon, there was a disadvantage that sufficient driving capability could not be obtained in a case where the supply voltage is the low voltage VCC.
FIG. 17 is a graph showing DC transfer characteristics of a CMOS inverter.
In general, in a CMOS inverter, threshold voltages VTH are determined in the p-channel MOS transistors and the N-channel MOS transistors forming the CMOS inverter such that, when an input signal exceeds the middle between the H level and the L level of the input signals, the p-channel and N-channel MOS transistors forming the CMOS inverter change from ON to OFF, or from OFF to ON. Curve A in FIG. 17 represent the DC transfer characteristic in this state.
Curve B in FIG. 17 represents a DC transfer characteristic in a case where the threshold voltages VTH of the p-channel and N-channel MOS transistors forming the CMOS inverter is shifted to the left of the curve A, and curve C in FIG. 17 represents a DC transfer characteristic in a case where the threshold voltages VTH of the p-channel and N-channel MOS transistors forming the CMOS inverter is shifted to the right of the curve A.
FIGS. 18A to 18D are schematic illustrations for explaining input and output waveforms of the CMOS inverter.
FIG. 18A represents a waveform of an input signal to the CMOS inverter, FIGS. 18B to 18D represent waveforms of output signals from the CMOS inverters having DC transfer characteristics corresponding to the curves A to C of FIG. 17, respectively.
If the DC transfer characteristic of the CMOS inverter is represented by the curve A of FIG. 17, the output signal starts to fall delayed by a time tDA from the time the input signal starts to rise, but a duration LHA of the H level and a duration LLA of the L level of the output signal are the same as durations of the H and L levels of the input signal, respectively, as shown in FIG. 18B.
But, if the DC transfer characteristic of the CMOS inverter is represented by the curve B of FIG. 17, the output signal starts to fall delayed by a time tDB which is shorter than the time tDA, from the time the input signal starts to rise, a duration LHB of the H level of the output signal is shorter than the duration of the H level of the input signal and a duration LLB of the L level of the output signal is longer than the duration of the L level of the input signal, as shown in FIG. 18C.
And, if the DC transfer characteristic of the CMOS inverter is represented by the curve C of FIG. 17, the output signal starts to fall delayed by a time tDC which is longer than the time tDA, from the time the input signal starts to rise, and a duration LHC of the H level of the output signal is longer than the duration of the H level of the input signal and a duration LLC of the L level of the output signal is shorter than the duration of the L level of the input signal, as shown in FIG. 18D.
In general, threshold voltages VTH of polysilicon MOS transistors vary more greatly than those of MOS transistors having single crystal silicon layer, and as is apparent from FIG. 16, drain currents ID vary greatly with variations of threshold voltages VTH of the polysilicon MOS transistors.
As a result, if the prior art level converter circuit is formed by polysilicon MOS transistors, the DC transfer characteristics of the CMOS inverters INV1, INV2 (see FIG. 13) vary greatly mainly due to the variations of the threshold voltages VTH of the polysilicon MOS transistors of the CMOS inverters INV1, INV2, and consequently, there was a problem in that a delay time (or a phase difference) of the output signal with respect to the input signal and a variation of a duration of the H or L level of the output signal increase.
For example, FIG. 19 shows waveforms of input and output signals of the level converter circuit of FIG. 13 formed by n-channel MOS transistors using polysilicon having mobility of about 80 cm2/(V ·s) and p-channel MOS transistors using polysilicon having mobility of about 60 cm2/(V·s).
In FIG. 19, curve Ø5 represents an output of the level converter circuit having standard threshold voltages VTH, curve Ø5-1 represents an output of the level converter circuit in a case where threshold voltages VTH of the NMOS and PMOS transistors shift by −1 V, and curve Ø5-2 represents an output of the level converter circuit in a case where threshold voltages VTH of the NMOS and PMOS transistors shift by +1 V.
As is apparent from FIG. 19, the delay time of the output signal with respect to the input signal and a variation of a duration of the H level of the output signal vary greatly with the variations of the threshold voltages VTH of the MOS transistors.
In a liquid crystal display module of the analog-sampling active-matrix type using polysilicon MOS transistors, such variations of the delay time of the output signal from the level converter circuit and the duration of the H level of the output signal cause a degradation in picture quality such as a picture defect in the form of a vertical line, when a half tone picture is displayed.
FIG. 20 is an illustration for explaining a principle of displaying by the liquid crystal display module of the active matrix type using polysilicon MOS transistors.
In the liquid crystal display module of the active matrix type using polysilicon MOS transistors, during one horizontal scanning period, a gate electrode line G1, for example, is selected by a scanning circuit and during this period analog video signals Øsig are sampled and supplied to, . . . an (n−1)st drain electrode line, an nth drain electrode line, an (n+1)st drain electrode line, . . . , sequentially by shift scanning of shift registers SR of a horizontal scanning circuit, and this horizontal scanning is repeated the number of times equal to the number of the gate electrode lines to form a picture.
The operation of sampling the analog video signals Øsig for the (n−1)st, nth and (n+1)st drain electrode lines will be explained by referring to time charts in FIG. 21.
First, voltage levels of complementary clock input signals ØPL and ØNL are level-converted by level converter circuits LV1 and LV2, respectively, to produce level-converted mutually complementary signals ØNH and ØPH.
The signal ØPH and an output from one shift register SR are supplied to a NAND circuit NA1 to produce a sampling pulse ØN, and the signal ØNH and an output from another shift register SR are supplied to a NAND circuit NA2 to produce a sampling pulse ØN+1.
The inverted pulses /ØN and /ØN+1 (A slant “/” is used instead of the bar “  ” to indicate an inverted signal.) of the sampling pulses ØN and ØN+1 drive sample-and-hold circuits SH1 and SH2 to sample time-varying analog video signals Øsig sequentially and supply video signal voltages Øm−1, Øm and Øm+1 to the (n−1)st, nth and (n+1)st drain electrode lines.
As a result, if the threshold voltages VTH of the MOS transistors of the level converter circuits LV1 and LV2 vary, the phases and the durations of the H level of the complementary signals ØNH and ØPH level-converted by the level converter circuits LV1 and LV2 vary, and consequently, the phases and the durations of the H level of the sampling pulses ØN and ØN+1 vary.
The variations of the phases and the durations of the H level of the sampling pulses ØN and ØN+1 cause shortening of the sampling time, sampling of a portion of the analog video signal Øsig different from a portion of the analog video signal Øsig intended to be sampled, or overlapping of the sampling times of the two sampling pulses ØN and ØN+1. These produce a ghost in an image displayed on a liquid crystal display panel, and therefore deteriorate display quality of the displayed image extremely.
In a digital-signal-input type liquid crystal display module of the active matrix type using polysilicon MOS transistors, if such level converter circuits are employed before a digital-analog converter (a D/A converter), variations of delay times occur in level converter circuits corresponding to respective data bits and consequently, a false picture is produced because some data bits are digital-to-analog converted in a state where they are inverted.