1. Field of the Invention
The present invention relates to electronic design automation in the integrated circuit industry. Various embodiments relate to testing and diagnosis of integrated circuits and more particularly to test response compaction used in test data volume and test application reduction for integrated circuits.
2. Description of Related Art
Electronic design automation EDA is applied in the semiconductor industry for virtually all device design projects. After an idea for the product is developed, EDA tools are utilized to define a specific implementation. The implementation defined using EDA tools is used to create mask data used for production of masks for lithographic use in the production of the finished chips, in a process referred to as tape-out. The masks are then created and used with fabrication equipment to manufacture integrated circuit wafers. The wafers are diced, packaged and assembled to provide integrated circuit chips for distribution.
An exemplary procedure for design using EDA tools begins with an overall system design using architecture defining tools that describe the functionality of the product to be implemented using the integrated circuit. Next, logic design tools are applied to create a high level description based on description languages such as Verilog or VHDL, and functional verification tools are applied in an iterative process to assure that the high-level description accomplishes the design goals. Next, synthesis and design-for-test tools are used to translate the high-level description to a netlist, optimize the netlist for target technology, and design and implement tests that permit checking of the finished chip against the netlist.
A typical design flow might next include a design planning stage, in which an overall floor plan for the chip is constructed and analyzed to ensure that timing parameters for the netlist can be achieved at a high level. Next, the netlist may be rigorously checked for compliance with timing constraints and with the functional definitions defined at the high level using VHDL or Verilog. After an iterative process to settle on a netlist and map the netlist to a cell library for the final design, a physical implementation tool is used for placement and routing. A tool performing placement positions circuit elements on the layout, and a tool performing routing defines interconnects for the circuit elements.
The components defined after placement and routing are usually then analyzed at the transistor level using an extraction tool, and verified to ensure that the circuit function is achieved and timing constraints are met. The placement and routing process can be revisited as needed in an iterative fashion. Next, the design is subjected to physical verification procedures, such as design rule checking DRC, layout rule checking LRC and layout versus schematic LVS checking, that analyze manufacturability, electrical performance, lithographic parameters and circuit correctness.
After closure on an acceptable design by iteration through design and verify procedures, like those described above, the resulting design can be subjected to resolution enhancement techniques that provide geometric manipulations of the layout to improve manufacturability. Finally, the mask data is prepared and taped out for use in producing finished products.
This design process with EDA tools includes circuitry that allows the finished product to be tested. Efficient testing of integrated circuits often uses structured design for testability (DFT) techniques. In particular, these techniques are based on the general concepts of making all or some state variables (memory elements like flip-flops and latches in the circuit) directly controllable and observable. The most-often used DFT methodology is based on scan chains. This approach assumes that during testing all (or almost all) memory elements are connected into one or more shift registers, as shown in U.S. Pat. No. 4,503,537. As a result, the designed logic circuit has two or more modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift test data into the circuit under test and shift out test responses. Applying a test pattern consists of scanning in the test stimulus, applying one or more functional clocks, and then scanning out the captured response. The test responses are then compared to fault-free test responses to determine whether the circuit under test (CUT) works properly.
Scan design methodology has been widely used in order to simplify testing and diagnosis. From the point of view of automatic test pattern generation (ATPG), a scan circuit can be treated as a combinational or partially combinational circuit. Today, ATPG software tools are able to generate a complete set of test patterns based on different fault models including stuck-at, transition, path delay, and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells must be specified and a single scan cell needs to be observed in order to detect the particular fault. Usually, the remaining scan cells are filled with random values. In this way, the test pattern is fully specified and could detect some additional untargeted faults.
Although just a few scan cells need to be observed to detect some set of target faults for each test pattern, full operability of all scan chains is a quite desirable property for both testing and diagnosis in order to achieve high test coverage of unmodeled defects as well higher accuracy and precision in defect localization during diagnosis.
The number of test patterns and scan chains are limited by such factors as available chip I/O, available tester channels and memory, and on-chip routing congestion. Because of the growing complexity and density of the integrated circuit, reducing test data volume and test application time has become a key issue for increasing quality and reducing test costs. By utilizing decompressor circuitry at the scan chain inputs and compressor circuitry at the scan chain outputs, these testing limitations are partly alleviated. Some of the DFT techniques for test data volume and test application time reduction use a compressor design based on linear code theory and convolutional code theory to compress the test responses from the scan chains. For example, linear compactors are built of exclusive-OR (XOR) or exclusive-NOR (XNOR) gates to reduce the number of test outputs of the integrated circuit. However, compactors may also mask errors in test responses from an integrated circuit. For example, the basic characteristic an XOR (parity) tree is that any combination of odd number of errors on its inputs propagates to their outputs, and any combination of even number of errors remains undetected.
Accordingly, a goal of compressor design is for a combinational block to meet the following requirements: (1) easy to specify and implement, (2) low area overhead with low impact on the integrated circuit, (3) logarithmic compression ratio, and (4) simple and reliable mechanism for error detection and location. However, satisfying all these requirements is quite challenging. In particular, it is difficult to ensure that the compressed test responses obtained from a faulty circuit are not the same as that of a fault-free circuit. This phenomenon is known as error masking or aliasing. An example of error masking occurs when the compactor reads multiple errors at the same time. The multiple errors could mask one another, resulting in a compressed test response that is the same as the compressed test response for a fault-free circuit.
Unknown values also add some complexity in error detection and location. For example, an unknown value on one or more inputs of an XOR tree generates unknown values on its output, and consequently masks propagation of errors on other inputs. This phenomenon is known as x-masking.
Thus, compressor design is challenging because of these conflicting requirements. It would be desirable, therefore, to provide an efficient compressor that generates a valid compressed test response even when unknown values or multiple errors exist on its inputs, and allowed for efficient and reliable detection and location of multiple errors in the test response for the purposes of testing and diagnosis.