This invention relates to power semi conductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor.
Computational power of digital processing circuitry is related to the conversion of input DC power to waste heat. As digital computational powers increase, the associated power consumption and heat generated by processing devices also increase. Power supply voltages of logic circuits have been reduced from 5 Volts to 1.2 Volts or less to alleviate excessive generation of heat and power consumption. However, reduction of power supply voltages has complicated other issues of power supply and distribution to logic circuits. For example, electrical resistance between power supplies and logic circuits has a more significant impact upon efficiency as supply voltages continued to be reduced.
Some designs have provided power to PC boards at high voltages (e.g., 48 Volts) and then utilize on-board converters to convert the received high voltage energy to 1.2 Volt or other low voltage supply energy for application to logic circuits. To minimize the size of such converters, the stored energy requirements in the magnetics and capacitors can be reduced by increasing the switching frequency of the converter. However, conventional power semiconductor configurations utilized in converters and capable of handling relatively large currents can not typically switch efficiently at the desired switching speeds.
FIG. 1 depicts a conventional vertical geometry power MOSFET device having a plurality of n+ source contact regions 3 which lie within p (body) regions 3P (typically formed as hexagonal islands), where both the p (body) regions 3P and the n+ source contact regions 3 are electrically connected to the upper source contact metal 3M. The gate conductors 2 are insulated from source contact metal 3M under which they lie by the insulator 3I and from the silicon substrate by the thin gate insulator 2I. The gate conductors 2 cover the regions between the p (body) regions 3P, extending across the edge (surface channel) portion of the perimeter of the p (body) regions 3P to the n+ source regions 3. When the gate conductors 2 are biased more positively than the threshold voltage of this conventional n-channel power MOSFET, electron flow through these surface channel regions is induced which results in electron flow along indicated paths 4. Electron paths 4 are formed from the adjacent n+ source regions 3 horizontally through the surface channel, vertically through the nxe2x88x92 drain drift region 5N to the n+ drain region 5 to the bottom drain metallization contact 6 shown in FIG. 1. This current flow path leads to values of source-drain ON resistance that are higher than desired for efficient low voltage power conversion applications.
The equivalent circuit of a conventional power MOSFET illustrated in FIG. 1 is depicted in FIG. 2. A p-n body diode 7 is provided from the source 3 to the drain 6 and comprises the p body region 3P and the nxe2x88x92 and n+ drain regions 5N and 5 shown in FIG. 1. The body diode 7 is a relatively large pxe2x88x92nxe2x88x92xe2x88x92n+ diode with a very large diffusion charge storage capacity Qd. Accordingly, when the body diode 7 is first reversed biased after heavy forward conduction, a large transient reverse current ir flows for a substantial period of time tr=Qd/ir which can limit usable switching frequencies.
There exists needs for improved semiconductor devices and methodologies which overcome problems associated with conventional arrangements.