Programmable logic devices are utilized in a wide variety of applications. A typical programmable logic device (PLD, such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)) may include a is number of logic blocks, memory blocks (e.g., embedded blocks of random access memory (RAM)), and input/output (I/O) blocks interconnected generally through a programmable routing architecture (also referred to as the interconnect architecture).
The logic blocks (also referred to in the art as programmable logic cells, logic array blocks, or configurable logic blocks) and memory blocks are conventionally coupled through the interconnect architecture to the I/O blocks through a corresponding common routing interface block (also referred to as a common interface block or CIB) and the CIB also couples the I/O blocks to the interconnect architecture. For example, FIG. 1 shows a conventional PLD 100 having logic blocks 120 organized in a row and column fashion (e.g., a three-by-three arrangement of rows R1-R3 and columns C1-C3). Each row includes a corresponding horizontal routing resource 130 and each column includes a corresponding vertical routing resource 140 as part of the interconnect architecture.
PLD 100 also includes I/O blocks 150 (which communicate through pins 160 to external devices (not shown)) and common interface blocks (CIBs) 170 through which horizontal and vertical routing resources 130 and 140 are coupled to I/O blocks 150. As an interface, CIB 170 can be implemented in any number of ways, such as a distinct switch matrix or other I/O element (IOE) or as an integral part of I/O block 150.
One CIB 170 may be located at the end of each row and column and serve as the interface between I/O blocks 150 and logic blocks 120 and the interconnect architecture. For example, CIB 170a located at the end of the row R1 may couple to and serve as the interface to the corresponding horizontal routing resource 130a for row R1, to the corresponding vertical routing resource 140a for column C1, and to adjacent CIBs 170.
One drawback of the generic CIB approach for the blocks (e.g., logic, memory, and I/O blocks) is that the CIB must be designed to interface with logic blocks, memory blocks, and I/O blocks (e.g., designed for the lowest common denominator). This may be an advantage in terms of symmetry or ease of use, but typically results in silicon and resource inefficiencies. For example, the CIBs may represent significant overhead and a significant percentage of the silicon area relative to the corresponding blocks.
Another drawback of the conventional PLD architecture is that optional embedded memory blocks are typically arranged in dedicated rows of memory blocks, which cannot be mixed with the logic blocks and generally divides up the logic blocks into discrete sections. For example, logic blocks 120 of the row R2 may be replaced with a row of the memory blocks. As illustrated in FIG. 2, for example, one or more memory blocks 202 may be situated between rows of logic blocks 204 (e.g., logic blocks 120 with at least a portion of the interconnect routing structure included), with memory blocks 202 having corresponding CIBs 170. I/O blocks 150 (e.g., PIC or programmable I/O cells) are also provided with corresponding CIBs 170. As illustrated further in FIG. 3, one or more separate and independent generic CIBs 170 are provided for memory blocks 202, I/O blocks 150, and/or logic blocks 204.
Thus, the memory blocks typically are coupled within the logic block array, which restricts the designer's mixing and matching of the number of memory blocks and logic blocks for particular design requirements or targeted applications (e.g., memory blocks to logic blocks ratio) and also limits the placement of the memory blocks and logic blocks within the PLD (e.g., relative to the interconnect architecture to avoid unacceptable routing congestion). As a result, there is a need for improved PLD architectures, such as for the interface block architectures.