This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit in which dummy-gate electrode layers are arranged to reduce the size variation of the gate electrode layers of MOSFETs.
In recent years, semiconductor elements have been made smaller and smaller. Technique of forming fine elements has therefore become increasingly important.
Integrated circuits known as ASICs and full-custom LSIs, in particular, have a circuit pattern (i.e., element layout) on the chip. The circuit pattern is irregular in most cases to meet users' demands, unlike memory cell arrays and gate arrays which have repeated regular patterns. Being irregular, the circuit pattern results in a variation in size of transistors, manufactured.
Due to electro-loading effect, metal wiring layers cannot have same size as is desired. This causes problems such as disconnection of wires and reduction in width of the wires.
The electro-loading effect is an adverse influence a non-uniform pattern imposes on the diffraction of light when exposure is performed by using a mask having portions densely arranged and portions sparsely arranged.
If the gate electrode layers, in particular, are not formed with high precision to have the design size, they will increase the leakage current of the transistors and will change the operating frequency and other various characteristics of the transistors. Consequently, the yield of the LSIs will decrease. In the worst case, flawless LSIs cannot be manufactured at all.
To prevent electro-loading effect resulting from a irregular circuit pattern which is composed of elements densely arranged and elements sparsely arranged, the circuit pattern should be re-designed. For example, a dummy pattern made of polysilicon may be formed on that part of a substrate on which no semiconductor elements are provided, as is disclosed Jpn. Pat. Appln. KOKAI Publications Nos. 4-322460 and 5-13722. The whole circuit pattern on the substrate is thereby rendered uniform in density, thus suppressing the electro-loading effect.
Recently, the integration density of semiconductor chips have been increasing. Therefore, multi-layer wiring technique is now used widely to manufacture semiconductor chips of high integration density. This technique consists in forming an insulting film on a dummy pattern and providing a power-supply wiring layer on the insulating film. The power-supply wiring layer not only covers the insulating film, but also fills the contact holes made in the film. The power-wiring layer is therefore electrically connected to the dummy pattern. Hence, the dummy pattern does not constitute stray capacitance, though it is made of polysilicon.
However, signal lines, formed on the insulating film and located above the dummy pattern, cannot be electrically connected to the dummy pattern by using the contact holes made in the insulting film. This is because the currents flowing through the signal lines are extremely small, inevitably increasing the impedance.
FIG. 1 is a schematic representation of a conventional semiconductor chip 320. A plurality of bonding pads 310 are mounted on the edge portions of the top surface of the chip 320, for supplying power to function blocks 300 including a CUP, a ROM, a timer, a RAM, an SIO and the like. A plurality of dummy patterns 330 made of polysilicon are arranged on that top surface area of the chip 320, where neither the pads 310 nor the blocks 300 are provided.
FIG. 2 is an enlarged perspective view of the area A shown in FIG. 1. As can be understood from FIG. 2, signal lines 350 are provided above the dummy patterns 330. Hence, as mentioned above, the signal lines 350 cannot be electrically connected to the dummy patterns 330. Parasitic capacitance C1 is generated between he dummy patterns 330 and the signal lines 350, and parasitic capacitance C2 between the chip 320 and the signal lines 350. Both parasitic capacitances C1 and C2 affect the characteristics of the integrated circuit. When the dummy patterns 330 extend parallel to the signal lines 350 and are located below the signal lines 350, the parasitic capacitances are so great as to cause the integrated circuit to malfunction.
As described above, the conventional integrated circuit has the problem in that parasitic capacitances will be generated if dummy patterns are formed to suppress the electro-loading effect.