A) Field of the Invention
The present invention relates to a semiconductor integrated circuit device and its manufacture, and more particularly to a semiconductor integrated circuit device capable of being designed with automatic layout and its manufacture.
B) Description of the Related Art
It is desired to develop in a short time semiconductor integrated circuit devices of various types and small quantity. A semiconductor integrated circuit device can be designed by automatic layout using a computer. In a standard cell method, patterns of basic gates and frequently used logic circuits are registered beforehand as standard cells. Automatic layout design is performed by disposing standard cells and wirings between cells in accordance with an equivalent circuit of a semiconductor integrated circuit device to be manufactured. Wiring regions are prepared in each cell. Some of interconnect wirings and power supply wirings in a cell may be prepared beforehand.
In automatic layout for a CMOS integrated circuit, n-type active regions for n-channel MOS transistors and p-type active regions for p-channel MOS transistors are disposed in column along a width direction. Each cell has a constant height along a direction perpendicular to the width (column) direction. If the height is fixed, wasteful space is likely to be formed so that the effective use of a substrate area may be hindered.
Japanese Patent Laid-open Publication No. 6-85062 proposes an optimum cell layout by using variable height of wiring regions for inter-cell wirings in the cells. Wiring regions are disposed above a semiconductor active region, above the semiconductor active region and isolation region and the like. This Publication also proposes a broad wiring region formed by connecting wiring regions above the p- and n-type active regions and common wirings formed in the broad wiring region.
Japanese Patent Laid-open Publication No. HEI4-263059 proposes that circuit information is developed into wiring information, single transistor cell information, serial cell information on a serial connection of a plurality of transistors and parallel cell information on a parallel connection of a plurality of transistors, respectively for n- and p-channel transistors. In a central area of a semiconductor chip, columns of n-type active regions and columns of p-type active regions are alternately disposed and a wiring region is disposed between adjacent active regions. Peripheral circuits are disposed in chip peripheral areas. Transistors having different channel lengths are distinguished from each other, making the size (channel length) of the column variable.
By making variable the height of a column of aligned cells, the substrate area can be used effectively. However, a wasteful space is formed in the substrate area if the numbers of wirings in cells along a column are large in some cells and small in some cells or by other reasons.