This invention relates to testing of semiconductor dies disposed on a semiconductor substrate.
After a semiconductor wafer has been fabricated, a number of the dies on the wafer are inoperable. Manufacturers of semiconductor devices typically test the individual dies for functionality prior to singulation into individual dies, to evaluate various electrical parameters of the integrated circuit components contained on each die, and verify that certain standards are met. Integrated circuits (IC) devices typically undergo three separate test cycles: (1) in-process testing and monitoring of sheet resistivities, junction depths, and device parameters such as current gain and voltage breakdown; (2) wafer-probe testing of electrical parameters prior to die separation; and (3) final testing of reliability and performance after die packaging is completed. Testing of ICs is expensive and time consuming, and it is desirable to keep testing costs low since these add directly to the cost of producing the parts.
Semiconductor wafers are typically subjected to test probing tested prior to singulation into individuals dies using a wafer-level test system. As illustrated in FIG. 1, a typical test system 10 includes a wafer handler 12 for handling and positioning the wafers 14, a test circuit 16 for generating test signals, a probe card (probe head) 18, and a probe interface board 20 for routing signals from the test circuit electronics to the probe card 18. The wafer probe card 18 typically includes multiple probe elements 22, typically in the form of probe pins or needles, for making temporary electrical connections with contacts on the dies disposed on the wafer 14, the contacts typically in the form of bond pads, fuse pads or test pads arranged in a dense area array. The wafer handler 12 typically includes a wafer chuck 24 configured to move in X and Y directions (i.e., horizontally backward-forward and side-to-side) to align the wafer 14 with the probe card 18, and in the Z direction (vertically up-down) to move the wafer into contact with the probe pins 22. Exemplary prior art test systems are described, for example, in U.S. Pat. Nos. 6,300,786 (Doherty, et al.) and U.S. Pat. No. 6,246,245 (Akram et al.), both assigned to Micron Technology, Inc.), the disclosures of which are incorporated herein.
An example of a prior art semiconductor wafer 14 is illustrated in FIGS. 2-3. The wafer 14 includes multiple semiconductor chips or dies 26 fabricated using processes that are well known in the art. The dies 26 are typically singulated by use of a wafer saw, which grinds the wafer 14 along wafer scribe lines 28, usually referred to xe2x80x9cstreetsxe2x80x9d or xe2x80x9cavenuesxe2x80x9d, that separate the dies 26 from each other. As shown in FIG. 3, each die 26 includes multiple die pads 30. The die pads 30 are in electrical communication with integrated circuits contained on the die 26. For illustrative purposes, each die 26 includes eight die pads 30, which is merely exemplary. The die pads 30 are illustrated as bond pads, but can also be dedicated test pads or fuse pads, disposed on the dies 26 or on other portions of the wafer 14.
Conventionally, each die on a wafer is tested by placing the probe elements 22 of a probe card connected to a test system on the pads 30 of the die. The test system supplies the proper power levels and signals to the pads on the die.
An example of a prior art probe card 18 is illustrated in FIG. 4, and typically comprises an insulating substrate 21, such as a glass filled resin, that includes electric traces (not shown) in electrical communication with the contacts or probe pins 22. The probe pins 22 on the probe card 18 are arranged in patterns corresponding to the patterns of the die pads 30. The probe pins 22 can be configured to make electrical connections with the die pads 30 on a specific die 26 or, as in the illustration in FIG. 4, with a group of dies (i.e., four dies) on the wafer. The probe pins 22 on the probe card 18 are arranged in groups 32a-d and configured on the substrate to correspond to the pattern of the die pads 30 on the die 26 to be contacted. Each group 32a-d of probe pins 22 represents a single test site. Typically, two or more test sites are included on the probe card 18 to accommodate testing of multiple dies at the same time. The probe card 18 can be formed with any desired number of test sites. The probe card 18 can also be configured to test a complete semiconductor wafer 14, or a portion of the dies 26 in a partial wafer. In the illustrated example in FIG. 4, the probe card 18 includes four test sites such that four dies 26 on the wafer 14 can be tested simultaneously. During a test procedure using a probe card, stepping techniques can be used to step the wafer 14 or the probe card 18, and test a number of dies 26 within a section on the wafer until all the dies 26 on the wafer have been tested. In those cases where dies 26 are positioned along the peripheral edge of a round wafer 14 (not shown), some of the probe pin groups 32a-d may not have an associated die under test, and the software that controls the stepping process is typically programmed to register valid test sites.
Manufacturers of semiconductor memory devices typically perform several operations on each device to examine various electrical parameters of the device and verify that certain minimum standards are met. A full range of functionality and timing characteristics of the memory devices are tested in order to determine if there is a defect in the array of cells that may fail over time. The test system 16 can transmit specific combinations of voltages and currents and/or signals to the probe interface board 20 and through the probe pins 22 of the probe card 18 to dies 26 under probe on the semiconductor wafer.
Bum-in stressing of dies is typically performed to accelerate failure using elevated voltage and temperature levels to stress, and determine operable voltages, currents, and temperatures. The test system can also run diagnostic tests on the memory device(s), which includes furnishing a sequence of commands (e.g., address, data and control signals) to the memory device for storing first data in memory cells of the memory device. The memory device can perform operations in response to the commands, and the operations synchronized to a clock signal. After the sequence, second data can be read from the memory cells and the first and second data can be compared to detect memory speed, timing, failures, and so forth. The integrated circuits that do not meet specification can be marked or mapped in software. Following testing, defective circuits can be repaired by actuating fuses (or anti-fuses) to inactivate the defective circuitry and substitute redundant circuitry.
In addition to the use of an external test system, memory testing can also be performed by means of a built-in self-test (BIST) circuit, which incorporates test circuitry and test data into the die 26 itself. In a BIST operation, the die is run in a way similar to how it is ultimately meant to be run. Activating BIST circuitry requires a Vcc power source, GND ground potential, and can also require signals from a test system. On a wafer level, the BIST circuitry can be disposed in the scribe lines (xe2x80x9cstreetsxe2x80x9d) 28 between dies 26 or in the unused edge portions along the periphery 34 of the wafer 14, or can be included within the dies 26 themselves.
Because each memory cell or bit of the memory device must be tested, the time and equipment necessary for testing memory devices represents a significant portion of the overall manufacturing cost of such devices. The more chips that can be tested simultaneously, the greater the savings in testing time and manufacturing cost per chip. Still more time could be saved if different testing protocols could be performed on a plurality of memory devices simultaneously.
The present invention provides a semiconductor substrate, a probe card, and a method for stressing and/or testing dies on a semiconductor substrate.
In one aspect, the invention provides a semiconductor substrate structured for testing and/or stressing a semiconductor die. In one embodiment according to the invention, the semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a metal layer (redistribution layer (RDL)) for re-routing the requisite power, ground, and signals from a test system into dies on the wafer substrate that are not in contact with probe elements of the test system. The RDL layer enables a path into a die from a location other than the original die pad currently being probed. The semiconductor substrate can comprise a plurality of die sets, and each die can comprise one or more pads for contact with an element (e.g., probe pin) of a probe card.
Two or more look-ahead pads or contacts (probe contacts) are associated with each die set in addition to the pads on the dies themselves. The look-ahead contacts can be positioned on the semiconductor substrate or on a die itself, such that when the pads of the dies of a die set are probed, the look-ahead contacts associated with that die set are also probed. Each look-ahead contact is electrically connected through a trace to a contact (pad) that is electrically connected to at least one die of a die set not currently being probed. A look-ahead contact can be electrically connected to one or more dies of a die set. When the look-ahead contact is probed, the requisite power, ground, and signals from a test system are routed through the traces to the die(s) of the die set not currently being probed. For example, the look-ahead contacts can include a power supply voltage (Vcc) contact and a ground potential (GND) contact and any number of signal contacts for receiving signals from an external source. The number of signal contacts can vary from one to as many as can be accommodated in a particular application.
In embodiments of the semiconductor substrate, the dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit, and/or the semiconductor substrate can comprise a BISS and/or BIST circuit disposed thereon that is associated with a die set and electrically connected to at least one die of the die set. The BISS and/or BIST circuit can be electrically connected to look-ahead contacts through traces.
In another embodiment of the semiconductor substrate, the dies can be connected through traces to look-ahead contacts to gain access to the circuitry of the dies, and provide the required Vcc power, GND ground, and signals for running the die according to a product data sheet or for running an accelerated operation for stressing or testing, among other operations.
In another aspect, the invention provides a probe card for electrically probing pads of dies of a die set disposed on a semiconductor substrate and two or more look-ahead contacts that are associated with the die set. Each look-ahead contact is connected by a trace to at least one die of a die set not currently under probe to re-route the appropriate power, ground, and signals from a test system to the dies. In one embodiment, the probe card comprises a substrate having a first set of probe elements disposed thereon for contact with pads of dies of a die set, and a second set of two or more probe elements disposed thereon for contact with the look-ahead contacts associated with the die set. The probe elements can be in the form, for example, of pins, needles, bumps, among other constructions.
In yet another aspect, the invention provides a method of stressing/testing dies on a semiconductor substrate. In one embodiment, the method comprises the steps of:
providing a semiconductor substrate having at least a first set and a second set of dies disposed thereon, and two or more look-ahead contacts proximal to the first die set; each die comprising two or more pads for contact with elements of a probe tester; and each look-ahead contact electrically connected through a trace to at least one die of the second die set;
providing a test system comprising a test circuit and a probe device; the probe device comprising a substrate having a first set of probe elements disposed thereon for contact with the pads of the dies, and a second set of probe elements for contact with the look-ahead contacts; and
contacting the probe elements with the pads of the dies of the first die set and the look-ahead contacts proximal to the first die set, to transmit the required Vcc power, GND ground potential, and signals from the test system to the dies of the first die set and through the look-ahead contacts and the traces to the dies of the second die set.
The method can further comprise initially stepping the probe card through the positions of the wafer to test the dies for opens/shorts.
In an embodiment of the method, required power, ground, and signals are transmitted from the test system to activate a built-in self-stress (BISS) circuit on or electrically connected to the dies and initiate a BISS operation on the dies. In another embodiment, the test system furnishes required power, ground, and signals to activate a built-in self-test (BIST) circuit and initiate a BIST operation in the dies. In yet another embodiment of the method of the invention, pads on the die necessary to operate the die for stressing or testing, for example, in a native or normal operation of the die (e.g., according to data sheet specifications), for accelerated operation, for testing a defined parameter, among others, are probed or connected through traces to look-ahead contacts, and the test system furnishes required power, ground, and signals to the pads on the die and the look-ahead contacts necessary stress or operate (WRITE and READ) the dies for testing.
In an embodiment of a method of probe testing dies of a semiconductor substrate according to the invention, in an optional first step, a probe card can be initially stepped through positions on the substrate to test the dies on the substrate for opens/shorts. A stress sequence can then be performed on the dies of a first die set under probe and the dies of a second die set (not under probe) that are electrically connected to the look-ahead contacts associated with the first die set. Subsequently, a test sequence (write and read) can be conducted on the dies of the first die set in contact with the probe elements. To test additional die sets, the probe card can then be moved to position the probe elements in contact with the dies and the look-ahead contacts of the next (second) die set, the look-ahead contacts connected through traces to dies of a third die set. A test of the dies of the second die set can then be conducted by furnishing required power, ground, and signals from the test system through the probe head elements into the dies of the second die set, while stressing the dies of the third die set by conducting required power, ground, and signals from the test system into the look-ahead contacts and through the traces to contacts of the dies of the third die set. The probe card is then moved to place the probe elements in contact with the die pads and the look-ahead contacts of the third die set and the foregoing stress/test operations are repeated on dies of the third and fourth die sets. The probe card is stepped through the remaining die sets, and stressing/testing proceeds until all the dies on the wafer have been stressed/tested.
Advantageously, the invention provides an apparatus and method for wafer probe stressing and testing whereby testing/stressing of dies in contact with elements of a probe card of a wafer test system and dies not currently under direct probing can overlap or be performed substantially simultaneously. By conducting concurrent or overlapping testing of at least two die sets, for example, a memory test of dies under probe and stressing the dies located previous to and/or ahead of the current probe position and not currently under probe, significant savings are realized in the overall time required for burn-in stressing and testing of the dies on the wafer. The probe step of the present method using a look-ahead contact can also run at higher than ambient (80xc2x0 C.) temperature in certain part or die modes, which can reduce or eliminate the need for burn-in stress once the dies are singulated, thus reducing costs and problems that can affect the functioning of the die and conserving the life expectancy of the die. Stressing can be used in addition to burn-in testing as a preliminary level of testing to identify and eliminate marginal defective devices. This can significantly reduce the failure rate at a subsequent burn-in test phase. In addition, as a result of early detection of defective failed or weak components, redundant components can be engaged prior to singulation and individual packaging, or if not, the defective die can be discarded before additional costs are incurred during packaging.