In accordance with an exemplary scenario, leakage power consumption is a factor that is considered while designing Integrated Circuits (ICs), such as System on Chips (SoCs). To illustrate, in an exemplary SoC, leakage power consumption tends to increase as the number of circuit blocks in the SoC are increased. In such SoCs, leakage power contribution for circuit blocks, such as memory units, is also very high, even during the standby mode of operation of the memory. Leakage power saving schemes in such SoCs utilize PMOS/NMOS power switches to reduce the leakage during the standby mode of operation of the circuit blocks. Such power switches are configured to disconnect a power supply to the logic blocks during the standby mode of operation in order to reduce the leakage during the standby mode.