Today's integrated circuits include a vast number of electronic devices. Smaller devices are a key to enhance device performance and improve reliability. As MOSFET devices, e.g., insulated-gate field effect transistors, are being scaled down, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one device generation to the next.
Gate dielectrics are one of the main problems for field effect device scaling. This is true for both conventional silicon devices and more advanced (e.g., Ge, SiGe, GaAs, InAs, etc.) devices. In order to further enhance the performance of Si-based MOSFETs, high-permittivity (‘high-k’) dielectrics will most likely replace traditional silicon oxide or oxynitride gate insulators to reduce the gate leakage current, and hence power dissipation. The likely first material of choice in many products will be Hf-based, e.g., Hf oxide (HfO2), Hf silicate (HfSiO), or Hf silicon oxynitride (HfSiON). However, also oxides containing other metal ions such as, for example, Al, Zr, Ti, Ta, or lanthanoid elements are under consideration for the first or later device generations.
As a gate electrode material, either the traditional doped Si, or novel conducting materials (‘metals’), e.g., W, Re, TiN, or NiSi, may be implemented. While metal gates in principle allow for a higher gate stack capacitance, and hence faster device performance, much more experience is available with doped Si. Therefore, doped Si may continue to be used, in particular for low power device applications that require low gate leakage, but not necessarily very fast operation.
The situation is even more problematic for field effect devices based on semiconductors other than Si, e.g., Ge, GaAs, etc. Up to now, no reliable high-quality gate dielectric has been found.
In particular, oxidation of these materials results in poor quality oxide layers that may even be water soluble, as is the case for most germanium oxide phases. Also deposited metal oxides with sufficient quality have not yet been demonstrated on alternative substrates. This is, in part, due to interfacial reactions during oxide deposition or during post-processing. Partial success, for example, on III-V semiconductors has only been reported in two cases: (i) functional Ga2O3(+Gd2O3)/GaAs gate stacks have been fabricated by molecular beam epitaxy, see, for example, J. Kwo et al., Appl. Phys. Lett. 75, 1116 (2003); and (ii) acceptable electronic properties were also reported for atomic layer deposited Al2O3 on GaAs, see, for example, P. D. Ye et al., Appl. Phys. Lett. 83, 180 (2003). Such results remain singular and are not fully understood.
But even in the potentially simpler case of Si-based MOSFETs, not all issues with high-k implementation have been resolved, despite intense research and development activities in many laboratories worldwide. Most importantly, in pFETs incorporating Hf-based dielectrics with polycrystalline Si (‘polySi’) gate electrodes, the threshold voltage (Vt) is consistently found to be approximately 0.6 V more negative than for silicon oxide (SiO2) or oxynitride (SiON) based devices. This renders such devices unusable for integration.
There is also a Vt shift for nFETs, by about. 0.2 V towards more positive values. These shifts are probably due to Fermi level pinning at the polySi/dielectric interface. As potential causes, interfacial Hf-Si bonds [C. Hobbs et al., Symp. on VLSI Tech., p. 9 (2003)], oxygen vacancies in the Hf-based dielectric [K. Shiraishi, et al., Symp. on VLSI Tech., p. 108 (2004)], and an interaction of dopants with Hf oxide or silicate defects [A. Kaneko et al., Extended Abstracts of ISSM 2003, p. 56] have been cited. To solve this problem, gate oxide capping layers and post-deposition treatments have been attempted by many groups worldwide, to no substantial effect. While there may be some hope to find a better capping layer or to investigate in more detail the impact of dopant choice and concentration, no solution is known so far.
Also in other respects there is, in principle, room for improvement of field effect devices. For example, the finite dopant concentration and activation in polySi electrodes cause a decrease in gate stack capacitance and hence degraded MOSFET performance (‘polySi depletion’). Higher dopant activation than currently used may also be attainable using in-situ doped (and possibly also using implanted) polySi electrodes, at additional cost compared to the regular process, as extra polySi growth, lithography, and reactive ion etch (RIE) steps may be needed. An alternative is the use of metal gate electrodes in place of polySi. Such gate stacks are under development in many industrial laboratories, but are not yet ready for implementation.
Another issue concerns the thermal budget needed for dopant activation. Activating implanted dopants in polySi gate electrodes and in the source and drain regions of a field effect device requires temperatures of ca. 1000° C. or higher. In MOSFET gate stacks involving alternative dielectrics, this often causes undesirable structural changes such as interfacial regrowth of SiO2, dielectric crystallization, phase separation, and/or reactions. Device performance is adversely affected. At added cost, this problem can partially be solved via in-situ doping of polySi during chemical vapor deposition (CVD) growth or by laser annealing. However, such solutions are not yet available for production.
Multilayer dielectric gate stacks (‘nanolaminates’) have been proposed in order to, for example, optimize capacitance vs. channel mobility in MOSFETs involving novel dielectrics, or to optimize program/erase speeds in nonvolatile floating gate FET memories [J. P. Casperson et al., J. Appl. Phys. 92, 261 (2002)]. However, not all desirable layer sequences may be manufacturable with sufficient quality utilizing conventional growth techniques such as, for example, chemical vapor deposition. A major potential manufacturing issue for certain materials combinations may be insufficient nucleation in atomic layer deposition (ALD), chemical vapor deposition (CVD), or molecular beam epitaxy (MBE) of such materials, in cases in which the surface free energies are unfavorable or the concentration of active nucleation sites is insufficient. This may result in islanded, rough films, potentially of undesirable crystallinity. Surface activation treatments between growing successive layers might be considered. This field is largely unexplored in the case of gate stack films and tunnel barriers.
In view of the above, there is a need for providing a technique for at least partially fabricating a gate stack on a semiconductor substrate that will allow for implementation of various gate materials without sacrificing device performance.