The present invention relates to an electronic device used for a mobile communication unit or the like in the field of information/telecommunication technology and a method for fabricating the same.
In recent years, demand for various types of mobile communication units such as cellular phones and personal handy phone systems (PHS) has tremendously increased. In order to catch up with such rapidly increasing demand, the frequencies applied to these mobile communication units have exceeded the MHz bands to reach the GHz bands. In a frequency converter or a signal amplifier for the receiver or transmitter section of such a mobile communication unit, a gallium arsenide (GaAs) field effect transistor (FET), which can operate with high gain, low distortion and small current even in a high frequency region, is widely used.
A large number of GaAs FETs are formed on a semi-insulating substrate made of GaAs. Then, during mounting, the substrate is divided by dicing into respective chips. Each of the divided chips is mounted on a lead frame. Thereafter, the electrodes of each GaAs FET are electrically connected to the lead frame via an Au wire.
However, if an FET having such a structure is operated in a high frequency region, then the gain of the FET adversely decreases, because the Au wire contributes to the formation of parasitic inductance.
Thus, in order to solve this problem, a method for electrically connecting the electrodes of an FET formed on a GaAs substrate to a lead frame through a conductor layer filled in a via hole formed in the GaAs substrate is suggested in Japanese Laid-Open Publication No. 6-5880, for example. In accordance with this method, the distance between the electrodes of the FET and the lead frame to be connected thereto can be shortened compared with connecting the electrodes to the lead frame via an Au wire. As a result, the parasitic inductance can be considerably reduced and the decrease in gain of the FET can be prevented.
Hereinafter, a conventional method for fabricating an electronic device having a via hole as disclosed in Japanese Laid-Open Publication No. 6-5880 will be described with reference to FIGS. 12(a) through 12(d).
First, as shown in FIG. 12(a), an FET, including an active layer 12, a source electrode 13, a drain electrode 14 and a gate electrode 15, is formed on the principal surface of a substrate 11 made of GaAs and having a thickness of 600 xcexcm. Then, as shown in FIG. 12(b), the back surface of the substrate 11 is polished to have the thickness thereof reduced to several tens to one hundred and several tens xcexcm.
Next, as shown in FIG. 12(c), an etching mask 16 having an opening 16a at a site corresponding to the source electrode 13 is formed on the back surface of the substrate 11, and the substrate 11 is etched using this mask 16, thereby forming a via hole 17 in the substrate 11 so as to reach the back surface of the source electrode 13.
Subsequently, as shown in FIG. 12(d), the etching mask 16 is removed, and a plating undercoat layer 18 is formed over the entire back surface of the substrate 11 as well as the wall and bottom surfaces of the via hole 17. Then, a metal electrode 19 is formed over the plating undercoat layer 18 by electroplating technique such that the via hole 17 is filled in with the metal electrode 19. In this manner, an electronic device, which includes the substrate 11 with a reduced thickness and in which the source electrode 13 is electrically connected to the metal electrode 19, can be obtained. It is noted that the plating undercoat layer 18 improves the adhesion of the metal electrode 19 to the substrate 11.
However, in accordance with this conventional method for fabricating an electronic device, since the via hole 17 is formed by etching the thinned substrate 11 using the etching mask 16, the substrate 11 is likely to crack. The reason is as follows. In order to form the via hole 17, the thinned substrate 11 must be transported to an apparatus for forming the etching mask 16 and then to an apparatus for etching the substrate 11. That is to say, since the substrate 11, which has the mechanical strength thereof decreased because of the reduction in thickness thereof, should be transported to these apparatuses, the substrate 11 is more likely to crack during the transportation. Thus, in accordance with the conventional method for fabricating an electronic device, the production yield adversely decreases.
Also, in order to form the via hole 17 in the substrate 11, the etching mask 16 having the opening 16a at the site corresponding to the source electrode 13 should be formed over the back surface of the substrate 11. Accordingly, during this process step, the position of the source electrode 13 formed on the principal surface of the substrate 11 should be aligned with the position of the opening 16a of the etching mask 16 formed on the back surface of the substrate 11. However, in order to align the position of the source electrode 13 on the principal surface of the substrate 11 with the position of the opening 16a of the etching mask 16 on the back surface thereof, a special aligner must be used. In addition, the process step required is adversely complicated and difficult.
In view of the above-described problems, the objects of the present invention are to prevent a decrease in production yield because of cracking of a substrate during the transportation step for forming a via hole in the substrate, and to eliminate a complicated alignment step conventionally required for forming a via hole in the substrate.
In order to accomplish these objects, a first method for fabricating an electronic device according to the present invention includes the steps of: a) forming a via hole in the principal surface of a substrate, the via hole having a bottom; b) forming a conductor layer at least over a sidewall of the via hole; and c) thinning the substrate by removing a portion of the substrate such that the conductor layer is exposed, the portion of the substrate being opposite to another portion of the substrate in which the via hole is formed.
In accordance with the first method for fabricating an electronic device, a via hole having a bottom is formed in the principal surface of a substrate, a conductor layer is formed at least over a sidewall of the via hole, and then the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed. Thus, the steps of forming the via hole in the substrate and forming the conductor layer in the via hole can be performed on a substrate that has not been thinned yet and thus still retains a sufficient mechanical strength. Accordingly, the step of transporting a thinned substrate to an apparatus for forming a via hole or to an apparatus for forming a conductor layer need not be performed. As a result, it is possible to prevent the substrate from cracking during the transportation of the substrate to these apparatuses and the production yield of the electronic device can be increased as compared with a conventional method.
In addition, no etching mask for forming a via hole needs to be formed over the back surface opposite to the principal surface of the substrate. Thus, a complicated alignment step using a special aligner, which has been required by a conventional method for aligning the position of an opening of the etching mask formed on the back surface of the substrate with the position of an electrode layer formed on the principal surface of the substrate, is no longer necessary.
In one embodiment of the present invention, the method preferably further includes, prior to the step a), the step of d) forming an electrode layer on the principal surface of the substrate, the electrode layer having a through hole over a region where the via hole is to be formed. The step a) preferably includes the steps of: forming an etching mask over the principal surface of the substrate as well as over the electrode layer, the etching mask having an opening over the region where the via hole is to be formed; and etching the substrate using the etching mask to form the via hole.
In such an embodiment, an electrode layer having a via hole is formed over a region where the via hole is to be formed, the via hole is formed by etching the substrate using an etching mask having an opening over the region where the via hole is to be formed, and then a conductor layer is formed at least over a sidewall of the via hole. Thus, an interconnection layer connecting the electrode layer to the conductor layer is no longer necessary. As a result, the number of required process steps can be reduced.
In another embodiment, the step b) preferably includes the step of filling in the via hole with the conductor layer. In such an embodiment, the electrode layer formed on the principal surface of the substrate can be connected to the conductor layer with more certainty.
In still another embodiment, the step b) preferably includes the step of forming the conductor layer by electron beam evaporation technique such that the conductor layer includes a sidewall portion and a bottom portion and has a recess at the center thereof. In such an embodiment, the conductor layer can be formed in a short period of time.
In this case, the step c) preferably includes the step of removing the portion of the substrate opposite to the portion of the substrate in which the via hole is formed such that the bottom portion of the conductor layer is left.
If the bottom portion of the conductor layer is left in this manner, then the contact area between an electrode layer formed on the back surface opposite to the principal surface of substrate and the conductor layer becomes large. As a result, contact resistance between the electrode layer on the back surface and the conductor layer can be reduced.
In still another embodiment, the step b) preferably includes the steps of forming a plating undercoat layer over the sidewall of the via hole and filling in the inside of the plating undercoat layer with the conductor layer.
In such an embodiment, a metal, which is usually hard to be directly plated over the substrate, can be used as a material for the conductor layer. Accordingly, it is possible to broaden the range from which a material for forming the conductor layer is selected.
In still another embodiment, the substrate is preferably a semi-insulating substrate made of a Group III-V compound such as gallium arsenide and indium phosphide.
In general, a semi-insulating substrate made of a Group III-V compound easily cracks by nature. In accordance with the first method for fabricating an electronic device, however, even when such an easily cracking semi-insulating substrate made of a Group III-V compound is used, the substrate can be thinned without making the substrate crack.
A second method for fabricating an electronic device according to the present invention includes the steps of: a) forming an electrode layer on the principal surface of a substrate; b) forming a first plating undercoat layer over the entire principal surface of the substrate; c) depositing an insulator film over the first plating undercoat layer, the insulator film having an opening over a region where a via hole is to be formed, a surrounding region thereof and at least part of the electrode layer; d) forming an etching mask over the first plating undercoat layer and the insulator film, the etching mask having an opening over the region where the via hole is to be formed; e) forming the via hole having a bottom through the first plating undercoat layer and in the substrate by etching the substrate using the etching mask; f) forming a second plating undercoat layer over the etching mask as well as over the inside of the via hole; g) leaving the second plating undercoat layer inside the via hole by lifting off the second plating undercoat layer and the etching mask; h) forming a metal layer to cover the opening of the insulator film as well as the inside of the via hole by plating the first and second plating undercoat layers with a metal using the insulator film as a mask; and i) thinning the substrate by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the metal layer is exposed.
In accordance with the second method for fabricating an electronic device, the steps of forming the via hole in the substrate and forming the conductor layer in the via hole can be performed on a substrate that has not been thinned yet and thus still retains a sufficient mechanical strength, as in the first method for fabricating an electronic device. Accordingly, the step of transporting a thinned substrate to an apparatus for forming a via hole or to an apparatus for forming a conductor layer need not be performed. As a result, it is possible to prevent the substrate from cracking during the transportation of the substrate to these apparatuses and the production yield of the electronic device can be increased as compared with a conventional method.
In addition, no etching mask for forming a via hole needs to be formed over the back surface opposite to the principal surface of the substrate. Thus, a complicated alignment step using a special aligner, which has been required by a conventional method for aligning the position of an opening of the etching mask formed on the back surface of the substrate with the position of an electrode layer formed on the principal surface of the substrate, is no longer necessary.
In particular, in accordance with the second method for fabricating an electronic device, metal plating is performed by using, as a mask, an insulator film having an opening over a region where a via hole is formed, a surrounding region thereof and at least part of the electrode layer, thereby forming a metal layer to cover the opening of the insulator film as well as the inside of the via hole. Thus, since the metal film connected to the electrode layer formed on the principal surface of the substrate reaches the region surrounding the region where the via hole is formed, the electrical characteristics of the electronic device can be tested by connecting a tester electrode to the metal film reaching the surrounding region. Accordingly, the electrical characteristics of the electronic device already including the via hole can be performed while the substrate has not been thinned yet and thus still retains a sufficient mechanical strength. Moreover, the substrate of an electronic device having defective electrical characteristics is not thinned in vain.
In one embodiment of the present invention, the step h) preferably includes the step of forming the metal layer in such a shape as including a sidewall portion and a bottom portion and has a recess at the center thereof. The step i) preferably includes the step of removing the portion of the substrate opposite to the portion of the substrate in which the via hole is formed such that the bottom portion of the metal layer is left.
In such an embodiment, the contact area between an electrode layer formed on the back surface opposite to the principal surface of the substrate and the conductor layer becomes large. As a result, contact resistance between the electrode layer on the back surface and the conductor layer can be reduced.
A first electronic device according to the present invention includes: an electrode layer formed on a substrate; a via hole formed in the vicinity of the electrode layer in the substrate; and a conductor layer formed at least over a sidewall of the via hole and electrically connected to the electrode layer. The via hole has a cross-sectional shape, at least part of which has an interior angle equal to or larger than 180 degrees.
In the first electronic device of the present invention, at least part of the cross section of the via hole has an interior angle equal to or larger than 180 degrees. Thus, the contact area between the conductor layer formed at least over the sidewall of the via hole and the substrate is larger. As a result, the adhesion between the conductor layer and the substrate increases and the conductor layer is less likely to peel off the substrate.
A second electronic device according to the present invention includes: an electrode layer formed on a substrate; a via hole formed in the vicinity of the electrode layer in the substrate; and a conductor layer formed at least over a sidewall of the via hole and electrically connected to the electrode layer. The conductor layer has an area with which a probe needle is able to make electrical contact.
In the second electronic device, the conductor layer has an area with which a probe needle is able to make electrical contact. Thus, the electrical characteristics of the electronic device can be tested by connecting a probe needle to an exposed part of the conductor layer on the back surface of the substrate. Since the electrical characteristics of the electronic device can be tested before a metal electrode is formed on the back surface of the substrate, the metal electrode is not formed in vain for an electronic device having defective electrical characteristics.