The present invention relates to a technology of reducing cross talk in a semiconductor integrated circuit and a technology effectively applicable to a signal-processing LSI (or a large-scale semiconductor integrated circuit) for receiving and processing signals in a plurality of different frequency bands. More particularly, the present invention relates to a technology effectively applicable to a radio-communication LSI employed typically in a hand phone for processing a signal received by adoption of a super-heterodyne technique.
As a radio-communication system adopted in a hand phone, there is known a radio-communication system embracing the super-heterodyne technique as shown in FIG. 11. In the radio-communication system shown in FIG. 11, reference numeral 100 denotes an antenna for receiving a signal wave and reference numeral 101 denotes a reception/transmission changeover switch. Reference numeral 110 denotes a reception-system circuit for amplifying the signal received by the antenna 100 and demodulating the amplified signal. Reference numeral 120 denotes a transmission-system circuit for modulating a signal to be transmitted through the antenna 100 and converting the frequency of the signal. Reference numeral 130 is an oscillation-system circuit for generating a local oscillation signal required by the reception-system circuit 110 and the transmission-system circuit 120. Reference numeral 140 denotes a base-band-signal-processing circuit for carried out processing such as extraction of audio data from a signal received by the antenna 100 and conversion of the audio data into a train of voltage pulses. Reference numeral 150 is a system controller including a microcomputer for totally controlling the entire radio-communication system. The transmission/reception changeover switch 101 is controlled by a control signal TX/RX output by the system controller 150 to switch the mode of the radio-communication system from reception to transmission and vice versa.
The reception-system circuit 110 comprises a band-limiting filter (FLT) 111, a low-noise amplification circuit (LNA) 112, a down-conversion mixer (MIX) 113, a band-pass filter (BPF) 114, a programmable-gain amplifier (PGA) 115 and a demodulator (DeMOD) 116. The FLT 111 is typically an SAW filter for removing unnecessary waves from a signal received by the antenna 100. The LNA 112 is an amplifier for amplifying a signal passing through the band-limiting filter (FLT) 111. The MIX 113 is a converter for down-converting the frequency of the signal amplified by the amplification circuit (LNA) 112 into an intermediate frequency by mixing the signal with the local oscillation signal generated by the oscillation-system circuit 130. The BPF 114 is a filter for passing through a signal having the frequency corresponding to a difference in frequency between the signal amplified by the amplification circuit (LNA) 112 and the local oscillation signal. The programmable-gain amplifier (PGA) 115 is an amplifier capable of controlling a gain at which a signal output by the band-pass filter (BPF) 114 is amplified thereby to a desired level. The DeMOD 116 is a demodulator for modulating the signal with the amplitude thereof adjusted by the programmable-gain amplifier (PGA) 115 to a desired level into a base-band signal (I/Q).
The transmission-system circuit 120 comprises a modulator (MOD) 121, an up-conversion mixer (U-MIX) 122 and a power amplifier (PA) 123. The MOD 121 is a modulator for modulating a signal to be transmitted into an RF (radio frequency) signal. The signal to be transmitted is received from the base-band-signal-processing circuit 140 as a base-band signal (I/Q). The mixer (U-MIX) 122 is a converter for up-converting the frequency of the signal obtained as a result of modulation by the modulator (MOD) 121 into a desired transmission frequency by mixing the modulated signal with the local oscillation signal generated by the oscillation-system circuit 130. The PA 123 is an amplifier for amplifying the power of the signal to be transmitted after the frequency conversion prior to a transmission by way of the antenna 100.
The oscillation-system circuit 130 comprises a radio-frequency voltage-controlled oscillation circuit (RFVCO) 132, an intermediate-frequency voltage-controlled oscillation circuit (IFVCO) 131, a synthesizer (SYN) 133 and a buffer (BFF) 134. The RFVCO 132 is a voltage-controlled oscillation circuit for generating an RF (radio frequency) signal used in the down-conversion mixer (MIX) 113 and the up-conversion mixer (U-MIX) 122. On the other hand, the intermediate-frequency voltage-controlled oscillation circuit (IFVCO) 131 is a voltage-controlled oscillation circuit for generating an IF (intermediate frequency) signal, that is, a signal with a fixed frequency, required by the demodulator (DeMOD) 116 and the modulator (MOD) 121. The SYN 133 is a synthesizer for generating control voltages applied to the radio-frequency voltage-controlled oscillation circuit (RFVCO) 132 and the intermediate-frequency voltage-controlled oscillation circuit (IFVCO) 131 respectively. The control voltage applied to each of the VCO 131 and VCO 132 is generated in accordance with a difference in phase between a feedback signal generated by the VCO 131 and VCO 13 and a reference signal TCXO generated by an oscillation circuit employing a crystal oscillator exhibiting characteristics of high frequency precision and little temperature dependence. The difference in phase is obtained as a result of comparing the feedback signal with the reference signal TCXO. The BFF 134 is a buffer for supplying an oscillation signal generated by the RFVCO 132 to the down-conversion mixer (MIX) 113 employed in the reception-system circuit 110 and the up-conversion mixer (U-MIX) 122 employed in the transmission-system circuit 120 by proper distribution. It should be noted that the synthesizer (SYN) 133 and the radio-frequency voltage-controlled oscillation circuit (RFVCO) 132 constitute a closed-loop circuit known as a PLL (Phase Locked Loop) circuit. Similarly, the synthesizer (SYN) 133 and the intermediate-frequency voltage-controlled oscillation circuit (IFVCO) 131 constitute another closed-loop circuit also known as a PLL (Phase Locked Loop) circuit.