This invention relates generally to the clocking of synchronous digital systems. More particularly, this invention relates to clock distribution systems for synchronous digital data transport systems such as backplanes and integrated circuits where clock skew is an important performance parameter.
In many synchronous digital bus transport systems, three types of signals are often provided, including a clock signal at some frequency F.sub.1, a synchronization signal (sync pulse) which provides frame references, and one or more data signals. Sometimes, only the clock and data signals are used, where the data signals include sync, data, and address information. In these systems, clock crossing information, i.e., clock timing, is used by the data sources to change the data and by the data sinks to sample the state of the data. In other words, the data is sampled and changed at a time related to an instant when the clock signal crosses a predetermined threshold. The waveform of the data in such systems is not of great importance as long as the data signal is properly above or below the data signal discrimination level for a sufficient time around the sampling instant. On the other hand, the ability of all data sinks and data sources to accurately and uniformly obtain clock crossing information is of extreme importance. The clock crossing information is typically dependent, at least in part, on the clock waveform, the discrimination level accuracy, the intrinsic delay between any two points in the system, and the relative location of the clock source or sink on the bus, where the intrinsic delay is the theoretical minimum propagation time for information between two points.
In the past, for simplicity and uniformity, designers of digital system buses have typically used square wave clocks using the same digital drivers and receivers used in transmitting data. Terminated and unterminated (open) buses have been designed. An illustrative representation of a prior art backplane system is shown in FIG. 1, where a common card 12 broadcasts clock and sync information over buses 14 and 16 to a plurality of Q-1 access nodes which are typically equally spaced over bus length L. The access nodes other than common card 12 only receive the clock and sync information. M data buses 18a, 18b, . . . , 18m, are also shown, with the Q-1access nodes being able to transmit or receive data onto the buses. Using the timing information broadcast by common card 12, the data sinks and sources 20 can exchange data on the data buses. Of course, if desired, the data buses can be unidirectional rather than bidirectional as shown, and the buses can be either nonterminating or terminating.
The idealized timing diagram of FIG. 2 illustratively corresponds with the prior art backplane system of FIG. 1. The clock signal of FIG. 2 as shown is idealized in that it is a perfect square wave with sharp edges and a fifty percent duty cycle. Such a perfect clock signal allows perfect, unambiguous extraction of the crossing information. The data sources use the crossing information to put data onto data lines 18 at the crossing instant, while the data sinks use the crossing information to take data off of data lines 18 after the crossing instant, as indicated. Implicit in the idealized timing diagram of FIG. 2 is that the discrimination or threshold levels for the clock, sync and data signals are between the [0] and [1] amplitudes shown.
As implied above, the clock signals of the prior art are never the perfect square waves which are represented. To make perfect square waves, an infinite bandwidth, with the fundamental frequency and all its harmonics, would be required. Thus, the idealized waveform does not take into account the reality of relatively unknown source impedances of the driver, the typically lumpy characteristic impedance of the bus transmission line, the total electrical length of the bus, etc. These realities, unless carefully addressed, cause serious waveform distortion as suggested by FIG. 3 where a clock edge is shown with a transient which causes the double crossing of the discrimination level. With such distortions, clock glitches can result, as shown. While the double crossing is due to bus reflections, it is useful to think of the distortions as intersymbol interference, undesirable phase displacement, and gain or loss of the harmonics of the clock fundamental frequency. These harmonics are in principle not required, since the clock signal only needs to indicate a threshold crossing event (i.e., a timing event), and not true "information" (i.e., data).
One of the manners of addressing the impedance problems which can cause distortion and clock glitches is to terminate both ends of the bus with an impedance as close as possible to the characteristic impedance of the bus, thereby minimizing reflections. The IEEE "Futurebus" standard utilizes this approach, by transmitting a large number of lined-up harmonics. In practice, termination to prevent reflections has a number of shortcomings and problems. A first shortcoming is that a significant amount of power is wasted. A second shortcoming is that in synchronous bus systems which are terminated, the clock transition is propagated along the bus at a limited velocity, thereby causing a delay between any two nodes on the bus. In other words, clock skew is introduced. This delay or clock skew is of significant consequence as it places an upper bound on the clock rate of a synchronous system depending upon the electrical length of the system. Another problem with using a terminated bus is that the impedance of the bus must be matched at the termination. However, the effective impedance of the bus, or any particular portion thereof, is dependent on the type and density of equipment coupled to the nodes. Therefore, in many systems, the impedance is uncertain. In fact, in Futurebus, a great deal of care and expense is expended in controlling the bus impedance, controlling access node loading, terminating the bus accurately, and keeping power within reasonable bounds.