1. Field of the Invention
This invention relates to field effect transistors (FETs) and, more specifically, to power and low noise FETs.
1. Brief Description of the Prior Art
Gallium Arsenide (GaAs) FETs are generally formed by providing a substrate of semi-insulating GaAs having a doped region at a surface region thereof with metallization on the doped surface region which makes an ohmic contact with the doped region to form source and drain regions and further metallization on the doped surface region which forms a Schottky barrier diode with the doped region to form the gate region, the channel extending between the source and drain in the doped region of the substrate and under the gate.
The layout topology of the FET and its effect on device performance is an area that is very weakly addressed in the literature. The interdigitated and pi gate feed structures have been industry standards for the last ten years with only minor modifications. The interdigitated FET has served well in low noise and power applications where a large gate periphery is required in a compact form. The pi FET has typically served in low noise designs where a small gate periphery is desired. In the pi configuration, the source is formed as many separate spaced apart segments with the gate being a thin line between the source segments and drain, the gate also including fingers extending therefrom between the source segment. In the interdigitated configuration, both the source and drain are formed as many separate spaced apart segments, the source and drain segments being interleaved or alternating and the gate being a thin line having fingers which extend between each opposing pair of source and drain elements. Both of these topologies limit the size of the FET periphery on MMIC chips and have parasitic components that increase the noise figure and limit the high frequency performance of the FET. The spider FET allows more FET area on the MMIC chip and allows the parasitics to be minimized by its topology.
A standard technique used in prior art FETs to minimize noise and improve gain has been the reduction of gate length. However, a simple reduction of gate length to lower the gate to source capacitance (Cgs) and to improve transconductance (gm) results in a greatly increased gate resistance (Rg) from the thin gate line and very little noise figure reduction.