In modem high density memories, such as random access memories (RAMs) having 2.sup.20 bits of memory or more, the time and equipment required to test functionality and timing of all bits in the memory constitutes a significant portion of the manufacturing cost. Accordingly, as the time required for such testing increases, the manufacturing costs also increase. Similarly, if the time required for the testing of the memory can be reduced, the manufacturing cost of the memories is similarly reduced. Since the manufacturing of memory devices is generally done in high volume, the savings of even a few seconds per device can result in significant cost reduction and capital avoidance, considering the high volume of memory devices produced.
Random access memories (RAMs) are especially subject to having significant test costs, not only because of the necessity of both writing data to and reading data from each of the bits in the memory, but also because as the density of RAM devices increases, the time required to test each bit of each device in production increases at a rapid rate.
Imbedded in these high density memories are logic circuits which are difficult to test for the same reasons. Imbedded logic circuits are gating or switching circuits which perform such logical operations as AND, NAND, NOR, and OR on the memory cells. The logic cells or circuitry are interweaved within the memory arrays to control access to the memory.
Very large and complex process/logic chip designs require the ability to test and observe the output of partitioned logic blocks. A known solution to the problem of testing imbedded arrays includes testing the imbedded array logic blocks sequentially. Also, a solution which has been used in the past to reduce the time and equipment required for the testing of logic designs is the use of special "test" modes, where the circuit enters a special operation different from its normal or functional operation.