The present invention relates to the realization of AND logic circuits in emitter-coupled logic circuits (ECL).
ECL logic modules are distinguished by particularly high speed because there is no saturation of the transistors. The principle of the circuit is that a constant emitter current is fed into a differential amplifier and the base of the first of the transistors has a bias between a low and a high level. Depending on the potential of the base of the second transistor, the latter or the first transistor takes over the current which causes a voltage drop determining the output condition at the associated collector resistor. AND logic arrangements can be realized very simply by series-gating, wherein several such stages lie on top of each other, i.e., the collectors of the lowest level plane are respectively connected to the emitters of the differential stage belonging to the next-higher potential plane, and only the topmost plane has collector resistors. In OR gates, the collectors of the topmost potential plane lead to a node and from there to the collector resistor.
The number of input variables in AND logic circuits is limited by the number of possible series gating stages, the levels of which differ by a diode voltage each. To assure sufficient signal excursion, a maximum of three stages can be on top of each other with supply voltages of 4.5 to 5.2 V, taking the required current sources into consideration.
According to the state of the art, more than three input variables in an AND gate are realized by connecting in series several series-gating gates, in which respective partial interconnections are carried out. From three input variables, an (auxiliary) output signal is generated which addresses an input of the next-following gate. Four input variables, for instance, require three series-gating stages of the first and two stages of the second gate as is shown in FIG. 1 by the example of a circuit of a 4-bit multiplexer with latching.
The logic function belonging to the circuit example of FIG. 1 reads: EQU Q(t)=A.multidot.B.multidot.C.multidot.D1+A.multidot.B.multidot.C.multidot.D 2+A.multidot.B.multidot.C.multidot.D3+A.multidot.B.multidot.C.multidot.D4+Q (t-1).multidot.C.
The maximally four input variables of the AND gates require two series-connected series-gating gates. The first gate realizes the logic function M=A.multidot.B.multidot.D1+A.multidot.B.multidot.D2+A.multidot.B.multidot. D3+A.multidot.B.multidot.D4 and the second gate, the logic function Q(t)=M.multidot.C+Q(t-1).multidot.C. On the lowest level plane VSI there are constant-current sources I1 to I7, with their emitter resistors RI1 to RI7, supplying the circuit. The two differential amplifiers DA and DC of the lowest series-gating stage with the base bias VB3 are controlled by the emitter followers TA and TC and their inputs A and C. The diodes DIA and DIC serve for matching the level to the next-higher stage with a bias VB2 for the differential stages DB1, DB2, DM and DQ(t-1) which are controlled by the emitter followers TB, TM and T1Q(t-1) with the inputs B and M and, in connection with the series base resistor RE3, by Q. Superimposed on this plane is the third series gating stage with the differential amplifiers DE1 to DE4 and the inputs D1 to D4. The corresponding bias VB1 is present at the bases of the two-emitter transistors, the collectors of which are tied together and form an OR logic circuit in conjunction with the common collector resistor RE1. Its collector potential controls the input M of the second series-gating gate via the transistor TM. The gate is connected in series and the output states Q and Q of the gate are present at the collectors of the differential stages DM and DQ(t-1) and the load resistors RE2, RE4 and RE5 of the differential stages DM and DQ (t-1) form the output of the circuit.
A disadvantage of this method are the relative long gate propagation times which depend on the number of the series-gating stages to be traversed. The gate propagation times are, for instance, for the circuit according to FIG. 1, typically, for the signal Di after Q, 1.07 ns, for A after Q, 1.33 ns and for B after Q, 1.20 ns; the relatively large amount of power required due to the large amount of circuitry, and the frequently not optimal utilization of the series-gating stages.
It is an object of the invention to further increase, by circuitry measures having only two series-gating stages, the number of the input variables, and to shorten the signal propagation time.