1. Field of the Invention
This invention relates to a driving method for an organic electroluminescence light emitting section.
2. Description of the Related Art
In an organic electroluminescence display apparatus, (herein after referred to simply as organic EL display apparatus) wherein an organic electroluminescence device (hereinafter referred to simply as organic EL element) is used as a light emitting element, the luminance of the organic EL element is controlled by the values of current which flows through the organic EL element. Then, similar to a liquid crystal display apparatus, and also in an organic EL display apparatus, the use of a simple matrix and the active matrix method are well known driving methods. While the active matrix method has a drawback due to its complicated structure when compared to the simple matrix method, the active matrix method has such various advantages that allows the luminance of an image to be increased.
As a circuit for driving an organic electroluminescence light emitting section (hereinafter referred to simply as light emitting section) which forms an organic EL element, a driving circuit (hereinafter referred to as 5Tr/1C driving circuit) composed of five transistors and one capacitor section is well known and disclosed, for example, in Japanese Patent Laid-Open No. 2006-215213. Referring to FIG. 1, the existing 5Tr/1C driving circuit mentioned is shown. The 5Tr/1C driving circuit includes five transistors of an image signal writing transistor TSig, a driving transistor TDrv, a light emission control transistor TEL—C, a first node initialization transistor TND1, a second node initialization transistor TND2, and one capacitor section C1. Here, the other end of the source/drain regions of the driving transistor TDrv forms a second node ND2, and the gate electrode of the driving transistor TDrv forms the first node ND1.
The Transistors and the capacitor section are hereinafter described in detail.
For example, the transistors are individually formed from an n-channel thin film transistor (TFT), and a light emitting section ELP is provided on an interlayer insulating layer, or the like, formed so as to cover the driving circuit. The anode electrode of the light emitting section ELP is connected to the other one of the source/drain regions of the driving transistor TDrv. A voltage VCat, for example 0 volt, is applied to the cathode electrode of the light emitting section ELP. Reference character CEL denotes parasitic capacitance of the light emitting section ELP.
A timing chart of driving is schematically shown in FIG. 17. A preprocess for carrying out a threshold voltage cancellation process is executed within a [period—TP(5)1]. In particular, if the first node initialization transistor TND1 and the second initialization transistor TND2 are placed into the on state, the potential at the first node ND1 becomes VOfs, for example 0 volt, and the potential at the second node ND2 becomes VSS, for example −10 volts. Consequently, the potential difference between the gate electrode of the driving transistor TDrv and the other end of the source/drain regions (hereinafter referred to as source region for the convenience of description) of the driving transistor TDrv becomes higher than a threshold voltage Vth of the driving transistor TDrv, placing the driving transistor TDrv into an on state.
The threshold voltage cancellation process is then carried out within the [period—TP(5)2]. In particular, the light emission control transistor TEL—C is placed into an on state, while the on state of the first node initialization transistor TND1 is maintained. As a result, the potential at the second node ND2 varies toward the potential difference between the threshold voltage Vth of the driving transistor TDrv and the first node ND1. In other words, the potential at the second node ND2 in a floating state rises. When the potential difference between the gate electrode and the source region of the driving transistor TDrv reaches the threshold voltage Vth, the driving transistor TDrv then enters an off state. In this state, the potential at the second node ND2 is approximately VOfs−Vth. Thereafter, within a [period—TP(5)3], the light emission control transistor TEL—C is placed into an off state, while the on state of the first node initialization transistor TND1 is maintained. Then, the first node initialization transistor TND1 is placed into an off state within a [period—TP(5)4].
Thereafter, a writing process for the driving transistor TDrv is executed within a [period—TP(5)5′]. In particular, during the off state of the first node initialization transistor TND1, the second node initialization transistor TND2 and the light emission control transistor TEL—C is maintained. The potential at a data line DTL is also set to a voltage corresponding to the image signal, that is, to the image signal (driving signal or luminance signal) voltage VSig for controlling the luminance of the light emitting section ELP. A scanning line SCL is then placed into a high-level state so the image signal writing transistor TSig is placed into an on state. As a result, the potential at the first node ND1 increases to the image signal voltage VSig. Charge based on the variation amount of the potential of the first node ND1 is distributed to each of the capacitor section C1, the parasitic capacitance CEL of the light emitting section ELP, and the parasitic capacitance between the gate electrode and the source region of the driving transistor TDrv. Accordingly, if the potential at the first node ND1 varies, then the potential at the second node ND2 also varies. However, the variation of the potential of the second node ND2 decreases as the capacitance value of the parasitic capacity CEL of the light emitting section ELP increases. Generally, the capacitance value of the parasitic capacitance CEL of the light emitting section ELP is higher than the capacitance value of the capacitor section C1 and the value of the parasitic capacitance of the driving transistor TDRV. Therefore, if the potential of the second node ND2 varies by a small amount, the potential difference Vgs between the gate electrode and the other end of the source/drain regions of the driving transistor TDrv is given by the following expression (A):Vgs≈VSig−(VOfs−Vth)  (A)
Thereafter, correction, that is, a mobility correction process, of the potential in the source region of the driving transistor TDrv, or at the second node ND2, is carried out within a [period—TP(5)6′] based on a characteristic, such as the magnitude of the mobility μ of the driving transistor TDrv. In particular, the light emission control transistor TEL—C is placed into an on state while the on state of the driving transistor TDrv is maintained. Then, after a predetermined time period t′0 passes, the image signal writing transistor TSig is placed into an off state to place the first node ND1, and hence the gate electrode of the driving transistor TDrv, into a floating state. As a result, where the value of the mobility μ of the driving transistor TDrv is high, the increasing amount ΔV or potential correction value of the potential in the source region of the driving transistor TDrv becomes high. Where the value of the mobility μ of the driving transistor TDrv is low, however, the increasing amount ΔV or potential correction value of the potential in the source region of the driving transistor TDrv becomes low. Here, the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv is transformed from the expression (A) into another expression (B) given below. It is to be noted that the predetermined time period, that is, the total time period t′0 within the [period—TP(5)6′] for executing the mobility correction process, may be determined in advance as a design value upon designing of the organic EL display apparatus.Vgs≈VSig−(VOfs−Vth)−ΔV  (B)
By the operation described above, the threshold voltage cancellation process, writing process, and the mobility correction process are completed. Thereafter, within a [period—TP(5)7], the image signal writing transistor TSig is placed into an off state, and the first node ND1, that is, the gate electrode of the driving transistor TDrv, is placed into a floating state. On the other hand, the light emission control transistor TEL—C maintains the on state, and one of the source/drain regions (hereinafter conveniently referred to as drain region) of the light emission control transistor TEL—C is connected to a current supplying section of a voltage VCC, for example, 20 volts for controlling light emission of the light emitting section ELP. As a result, the potential at the second node ND2 increases, and a phenomenon similar to that in a bootstrap circuit occurs with the gate electrode of the driving transistor TDrv, also increasing the potential at the first node ND1. As a result, the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv maintains a same value as obtained from the expression (B). Further, since current that flows through the light emitting section ELP is the drain current Ids, which also flows from one of the source/drain regions (hereinafter conveniently referred to as drain region) of the driving transistor TDrv to the source region, the current can be represented by an expression (C). The light emitting section ELP emits light with the luminance corresponding to the value of the drain current Ids. It is to be noted that a coefficient k is hereinafter described.
                                                                        I                ds                            =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                                        =                                ⁢                k                            ⁣                              ·                μ                ·                                                      (                                                                  V                        Sig                                            -                                              V                        ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            
The 5Tr/1C driving circuit whose outline is described above are hereinafter described in detail.