The present invention relates to an improved arbitration control scheme for a multi-processor computer system.
In a system with multiple processors accessing a shared bus, some form of bus access protocol is necessary. Current arbitration schemes for determining bus access utilize a single separate arbitration controller attached to the bus. This arbitration controller is synchronous with the system clock, often resulting in wasted clock cycles while the arbitration controller is determining which processor shall have access to the bus. In addition, such schemes for determining access operate generally on a fixed priority basis. That is, the priority of the various processors cannot be changed, with the common result that low priority processors do not receive the necessary bus access cycles.
Additionally, arbitration is not determined every clock cycle. Therefore, a processor which has a high priority and needs bus access, but has a relatively large number of unused single cycles, can prevent a lower priority processor from having bus access.
Thus, prior bus arbitration schemes result in fair bus access being denied to one or more lower priority processors and less than 100% potential bus utilization because of wasted clock cycles which cannot be transferred to other processors on a temporary basis.
Many present arbitration schemes use open-collector outputs for signalling. That is, several outputs are tied together, and a device signals a request for arbitration by pulling the common line or lines to ground. This general procedure has an important drawback for high speed systems, in that the return-to-high state is too slow unless a pull-up resistor is very small. However, if the pull-up resistor is small, high power dissippation results.
It is therefore an object of the present invention for a bus arbitration scheme to spread the arbitration controller function among the various processors. It is a further object of the present invention that arbitration mastership can be passed among the various processors. It is another object of the present invention that bus access can be determined on a cycle by cycle basis, and that bus access grants are separated from transfers of arbitration mastership. It is yet another object of the present invention to provide an arbitration system which does not use open-collectors, thus improving speed.
Therefore, according to the present invention, a bus arbitration scheme uses an asynchronous ring coupled to all processors which can be used to control bus access. One processor is the arbitration controller at any given time and operates in synchronization with the system clock, while the remaining processors operate asynchronously to determine the arbitration controller for the next cycle. Each processor has arbitration control logic incorporated thereto, and has the capability of being the arbitration controller. Arbitration mastership is determined on a cycle by cycle basis, as is bus access. Clock cycles can be granted to other processors as required on a cycle by cycle basis, and arbitration mastership can be circulated among the various processors.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereafter appear, and for purposes of illustration, but not of limitation, a preferred embodiment is shown in the accompanying drawings.