1. Field of the Invention
The present invention relates to a method and apparatus for processing an image signal captured by a solid-state imaging device and to an imaging apparatus, which may correspond to an imaging electric equipment module included in a cellular phone, a personal computer, or the like. The electric equipment module may include the solid-state imaging device, a signal processing circuit, a converging lens, and the like.
More particularly, the present invention relates to clamping technology for bringing the direct current (DC) level of a captured image signal closer to a predetermined value, the captured image signal being output from a current-output solid-state imaging device, such as a complementary metal-oxide semiconductor (CMOS) imaging sensor or an amplifier imaging device, for outputting an image signal obtained at each pixel as a current signal.
2. Description of the Related Art
In general, a typical solid-state imaging apparatus performs photo-electric conversion by photo-sensors including photodiodes, detects generated charge by a detection circuit, amplifies the detected charge, and sequentially outputs the amplified charge. In most cases, the detection circuit alternately performs detection and resetting. The detection circuit generates a noise signal referred to as reset noise. As a result, an offset component is generated at each pixel. In the case of a so-called amplifier solid-state imaging device in which each photo-sensor has a detection circuit, variations among detection circuits may cause a noise signal referred to as fixed pattern noise (FPN). The FPN signal is removed by known signal processing referred to as correlated double sampling (CDS).
A noise-removed signal from which noise is removed by a CDS circuit is subjected to signal processing by a programmable gain amplifier (PGA) and converted into a digital signal by an analog-to-digital (A/D) converter, and a digital signal is generated by digital signal processing.
In general, the DC level of a signal output from a solid-state imaging apparatus fluctuates due to various factors, such as a power supply voltage, temperature, or variation in semiconductor device manufacturing processes. As a pixel signal passes through the CDS circuit, the PGA, and the A/D converter, the signal is clamped to an arbitrary DC level using a clamp circuit within an arbitrary period of time. For example, in the case of a solid-state imaging apparatus, the DC level is clamped by adjusting an optical black (OPB) level of an imaging device to a reference level. Various configurations have been proposed to realize the clamp circuit.
FIGS. 12A to 12D are block diagrams schematically showing examples of the configuration of known solid-state imaging apparatuses. FIGS. 12A to 12D show examples of using a current-output solid-state imaging device. A current-mode captured image signal output from a solid-state imaging device 3 is converted into a voltage signal by a current-to-voltage (current/voltage or I/V) transducer circuit 902. The voltage signal passes through a CDS circuit 903, a PGA 904, a DC shifting circuit 905, and an A/D converter 906, and finally sent to a digital signal processing circuit.
A clamp circuit 900 clamps the DC level by comparing, by a differential amplifier 907 provided prior to the A/D converter 906, the output signal level with a reference voltage of a reference voltage source 908 and sending feedback to the DC shifting circuit 905 so that the difference between the output signal level and the reference voltage becomes substantially zero.
With this arrangement, a feedback signal for clamping the DC level is fed back to a stage subsequent to the PGA 904. Alternatively, an additional feedback signal may be sent to a stage prior to the PGA 904. In this case, the input signal level of the PGA 904 is controlled. Thus, a dynamic range of the PGA 904 is prevented from being reduced due to a variation in the DC level. On the other hand, sending the feedback to a stage prior to the CDS circuit 903 is not practical since a DC component is removed by subtraction by the CDS circuit 903. Although sending the feedback to the stage prior to the CDS circuit 903 is not impossible, due to the above circumstances, DC level adjustment is necessary subsequent to CDS processing. In effect, the clamp circuit portion for sending the feedback to the stage prior to the CDS circuit 903 is useless.
In contrast, FIG. 12B shows a case characterized in that an additional independent clamp circuit 901 for ensuring the dynamic range of the CDS circuit 903 is provided. Referring to FIG. 12B, a DC shifting circuit 909 is provided prior to the CDS circuit 903. A differential amplifier 910 monitors the input level of the CDS circuit 903 and sends feedback so that the input level becomes equivalent to a DC voltage of a reference voltage source 922.
The known clamp circuits shown in FIGS. 12A and 12B absorb changes in the DC level of signals to prevent a problem such as the rising black level or the falling black level of the video signal. Such clamp circuits are required to ensure the dynamic range of an analog circuit, such as the CDS circuit 903 or the PGA 904.
In the known solid-state imaging apparatuses illustrated in FIGS. 12A and 12B, a DC shifting circuit(s) is necessary to clamp the DC level. As a result, the system becomes more complicated. In general, a signal processing circuit such as a CDS circuit or PGA processes a signal in the form of voltage. In this case, the clamp circuit is realized by sending feedback to a voltage signal. The DC shifting circuits 905 and 909 are implemented using voltage adders or the like. In some cases, a large capacitive element is used to cut a DC component of the signal.
FIG. 12C shows a case in which the DC shifting circuit 905 shown in FIG. 12A is implemented using a voltage adder. The voltage adder includes resistive elements 911, 912, and 913, a differential amplifier 914, and a reference voltage source 915. The voltage adder adds the output voltage of the PGA 904 and the output voltage of the differential amplifier 907 and outputs the sum to the A/D converter 904. The input voltage of the A/D converter 906 is transferred to an input end of a switching element 917 via a buffer 916, and the switching element 917 is controlled by a clamping pulse, thus maintaining a clamp potential in a holding capacitor 918. The differential amplifier 907 monitors the input voltage of the A/D converter 906 for an arbitrary period of time controlled by the switching element 917 and feeds back an appropriate voltage to the resistive element 912, that is, the input of the voltage adder, so that the input voltage of the A/D converter 906 becomes the same voltage as the voltage of the reference voltage source 908.
FIG. 12D shows a case in which the DC shifting circuit 905 shown in FIG. 12A is implemented using a capacitive element. A capacitive element 919 receives an output signal of the PGA 904, cuts a DC component of the signal, and outputs the DC-component-removed signal via a buffer 920 to the A/D converter 906. The removed DC component is supplied by the differential amplifier 907 for an arbitrary period of time controlled by the switching element 917 and maintained by the capacitive element 919. The differential amplifier 907 monitors the input signal voltage of the A/D converter 906 and sends feedback to the capacitive element 917 so that the input signal voltage becomes the same voltage as the voltage of the reference voltage source 908.
Accordingly, the DC shift circuit for clamping a voltage signal must include a voltage adder, as shown in FIG. 12C, or a capacitive element, as shown in FIG. 12D. This may cause an increase in the circuit size and/or an increase in the layout area. In particular, a large capacitive element is difficult to provide on a semiconductor substrate because of the limited layout area. When such a large capacitive element is provided outside the semiconductor, another problem, such as an increase in the number of PAD (terminals), is caused.
As described above, a known solid-state imaging apparatus must include complicated analog signal processing circuits including a current/voltage transducer circuit, a CDS circuit, a PGA, and an A/D converter. The system requires a clamp circuit for stabilizing the DC level of a captured image signal. As shown in FIGS. 12C and 12D, additional DC shifting circuits are necessary. This may further cause complication in the system.