1 Field of the Invention
This invention relates to integrated circuits, and more particularly, the control of clock signals distributed in integrated circuits.
2. Description of the Related Art
Clock-gating is a power saving technique that is employed in a wide variety of integrated circuits (ICs). In an IC operable to perform clock-gating, extra hardware in the form of clock-gating logic is added to various points of a clock tree that is used to distribute a clock signal. A point of a clock tree used to distribute the clock signal directly to circuitry (e.g., flop circuits) may be referred to as a “leaf” node. Accordingly, clock-gating logic may be placed at the leaf node. The clock-gating logic of each leaf node may be coupled to receive an enable signal that, when asserted, enables the clock signal to be provided to the clock circuitry associated with that leaf node. The enable signal may be de-asserted to inhibit the clock signal from being provided to circuitry coupled to a corresponding leaf node when that circuitry is idle, thereby saving power.
Another power-saving technique that involves the clock signal is frequency scaling. Frequency scaling is a technique by which the clock frequency may be changed depending on a processing workload. When the processing workload is higher, a system using frequency scaling may operate at a higher clock frequency. If the workload is reduced, the clock frequency may be correspondingly reduced. Changing the clock frequency may be accomplished by momentarily suspending processing operations, changing the clock frequency at its source (e.g., at a phase locked loop), and then resuming operations once the clock signal is cycling stably at its new frequency.