The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for equalizing signals.
High speed serial communication has become popular and essential in current communication devices. Serializer/deserializer transceivers have been developed to serialize a number (P) of parallel signals each of a given bit rate (B) into a single serial signal with a rate of P*B. The single signal may then be transmitted to a receiver and subsequently deserialized into an output corresponding to the original P parallel signals with the original bit rate B. Common serializer/deserializer transceivers can transmit serial signals up to approximately 10 Gbps. At such high frequencies, channel distortion and attenuation, such as Inter Symbol Interference (ISI), crosstalk, noise, jitter, and the like becomes significant.
In some cases, signal degradation due to one or more of the aforementioned conditions has been partially mitigated in the transmitter portion of a transmitter/receiver system. For example, a common mitigation technique is to pre-emphasize high frequency components of the transmitted signal, or alternatively to de-emphasize low frequency components of the transmitted signal. In some cases, however, such an approach may increase various noise components resulting in an undesirable decrease in signal to noise ratio. Further, such emphasis/de-emphasis approaches may not be sufficient in many systems and channels to permit the receiver to recover the bit sequence.
Channel equalization is used in many systems to determine a correct bit sequence from a received transmission. To determine the correct bit value for a given bit period or a received signal, equalization processes are used to modify a current sampled value of the transmitted signal by a function of the values determined during some number of earlier and/or later bit periods. Thus, data dependencies in the transmitted signal can be used to modify a bit value for a given bit period. Alternatively, or in addition, maximum likelihood detectors may be used to determine the correct bit value during a given bit period by calculating the maximum likelihood of the bit value (e.g., either logic-0 or logic-1) based on the values determined during some number of earlier and/or later bit periods. While such maximum likelihood detectors can be very effective in determining a correct bit sequence, they typically require a great deal of semiconductor area to implement and introduce considerable latency to a data receiving process.
In some cases, analog decision feedback equalizers (analog DFEs) have been utilized in serializer/deserializer transceivers to determine the correct logic value of a sample of a analog input signal for a given bit period in the presence of inter symbol interference. Such analog DFEs are capable of high bandwidth operation, but are typically expensive in terms of both power dissipation and semiconductor area. Equivalent digital circuits are often less power and space intensive. However, existing digital equivalents offer lower bandwidth due to a variety of mathematical operations being accomplished in the digital signal domain. At least in part because of this, many high bandwidth serializer/deserializer transceivers utilize analog DFEs at the cost of higher power dissipation and semiconductor area. In some cases, such a cost is unacceptable.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for signal equalization.