1. Field
Example embodiments are directed to semiconductor integrated circuits, for example, memory diagnosis test circuits for analyzing errors in static random access memory device (SRAM) cells and test methods using the same.
2. Description of Related Art
A large scale integrated circuit (LSI) may include a plurality of circuit blocks, for example, read only memory devices (ROMs), random access memory devices (RAMs), input/output circuits, etc., as well as a central processing unit (CPU). The ROMs of the system LSI may store a program processed by the CPU or fixed data. The RAMs, for example, SRAMs, may temporally store data processed by the CPU relatively quickly. SRAMs of the system LSI may have small capacities, for example, 128K.
As the capacities of the SRAMs increase, the possibility of error occurrence may increase in the circuit blocks during manufacturing. To analyze an error of the circuit blocks, a method of inserting a test element group (TEG) pattern, which may be approximately the same as the circuit blocks, into a scribe line region of a wafer may be used. Consequently, semiconductor yield may be improved by analyzing the error of the circuit blocks while maintaining an existing net die.
FIG. 1 is a block diagram illustrating a conventional SRAM TEG pattern 100.
Referring to FIG. 1, the SRAM TEG pattern 100 may include an SRAM core block 110, a control unit 120, a row decoder 130, a column decoder 140, and/or a sense amplifier unit 150.
The SRAM core block 110 may include a plurality of rows and columns of unit SRAM cells, each including six cell transistors, for example. The control unit 120 may generate control signals in order to control the SRAM core block 110. The row decoder 130 may decode a plurality of row address signals and selectively enable a plurality of word lines of the SRAM core block 110. The column decoder 140 may decode a plurality of column address signals and selectively enable a plurality of bit lines of the SRAM core block 110. The sense amplifier unit 150 may sense-amplify data stored in a plurality of cells disposed at positions where the enabled word lines and the enabled bit lines cross each other.
If an error occurs, the above SRAM TEG pattern 100 may not be able to detect which type of error is in the cell transistors of the SRAM core block 110. For example, if a single bit error occurs in an SRAM and the error is a transistor error or a contact error, the exact position of the error may not be able to be found by the conventional SRAM TEG pattern 100. Thus, it may be unclear in which node of the six transistors connected to each other the error has occurred.