1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In recent years, semiconductor devices such as LSIs have been more and more miniaturized, and a gate length of a MOS transistor is becoming shorter than 90 nm. Along with such miniaturization, improvement in performance such as a shortened gate delay time is expected. However, in reality, some points have been noted, which include that an ON-state current is not improved as expected and that heat generated by an increase in power consumption becomes a problem. Accordingly, disadvantages have been newly caused by the miniaturization.
Consequently, in order to realize higher performance and higher integration of the semiconductor devices without miniaturization, a stacked semiconductor device including transistors stacked in three dimensions has been proposed as disclosed in Patent Documents 1 and 2.
Among these patent documents, Patent Document 1 has proposed a method for realizing a stacked semiconductor device by attaching a silicon substrate to a silicon substrate having transistors formed thereon and forming transistors on the upper silicon substrate.
Meanwhile, in Patent Document 2, a stacked semiconductor device is manufactured by sequentially stacking transistors on a silicon substrate.
Besides the methods described above, there is also a method for manufacturing a stacked semiconductor device by mounting semiconductor chips in three dimensions.
Furthermore, a technology related to the present invention is also disclosed in Patent Document 3.
[Patent Document 1]
Japanese Patent Laid-Open No. Hei 5 (1993)-198739
[Patent Document 2]
Japanese Patent Laid-Open No. Hei 5 (1993)-335482
[Patent Document 3]
Japanese Patent Laid-Open No. Hei 7 (1995)-37867
Incidentally, in the semiconductor device, it is required to form wirings for applying a voltage to gate electrodes and source and drain regions of transistors and to form interlayer insulating films. If transistors are formed on these wirings and films, the transistors have to be formed at a temperature equal to or lower than allowable temperature limits of the wirings and the interlayer insulating films.
When the wirings are made of aluminum, the allowable temperature limit of the wirings is about 400° C. that is a melting point of aluminum. Moreover, in copper wirings obtained by a damascene process or the like, when a temperature reaches about 400° C., a needle-shaped protrusion is formed on an upper surface of the copper wiring by regrowth of a copper crystal. Accordingly, the protrusion may short-circuit the upper and lower copper wirings. Moreover, the copper wirings may be disconnected.
Furthermore, in the case where a low dielectric constant insulating film is used as an insulating film which covers the wirings, since the low dielectric constant insulating film has poor heat resistance, transistors have to be formed thereon at a process temperature of 400° C. or lower.
However, in Patent Document 1 described above, as disclosed in the paragraph number 0039, a temperature as high as about 650° C. is required to attach two silicon substrates each other. Thus, such wirings and low dielectric constant insulating films as described above cannot be formed between upper and lower transistors.
Moreover, in Patent Document 2, as disclosed in the paragraph number 0013, amorphous silicon to be active regions of transistors is annealed to obtain polysilicon. However, since an annealing temperature is as high as 600° C., it is difficult to form wirings and low dielectric constant insulating films between upper and lower transistors.