The present invention relates generally to semiconductor memories, and more specifically to a method and circuit for testing an Embedded DRAM including memory and logic circuitry formed in a single integrated circuit.
Advances in the design and fabrication of integrated circuits have resulted in significant decreases in the size of transistors and other components forming such integrated circuits. Accordingly, the density of transistors and other components that may be formed in a semiconductor substrate of a given size has increased dramatically. Such dramatic increases in the density of components have enabled manufacturers to fabricate high capacity memory devices in the same size substrate previously required for much lower capacity devices. Similarly, for microprocessors and other logic circuits, such increased component density has enabled manufacturers to increase functionality by including additional circuitry on the substrate.
In addition to improving functionality and performance of existing types of integrated circuits, increased component density has enabled manufacturers to develop a new type of integrated circuit called an xe2x80x9cEmbedded DRAMxe2x80x9d in which logic circuitry and dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), or other type of memory, are formed in the same integrated circuit. In other words, the logic circuitry may be xe2x80x9cembeddedxe2x80x9d in the DRAM. FIG. 1 is a block diagram of an Embedded DRAM 11 including logic circuitry 13 and a DRAM 15 formed in a semiconductor substrate 17. The logic circuitry 13 may be designed to perform a specific function, or may be more general purpose circuitry, such as a microprocessor performing a variety of different tasks. The logic circuitry 13 is coupled to the DRAM 15 through an address bus 19, internal data bus 21, and control bus 23, and applies address, data, and control signals on these respective busses to transfer data to and from the DRAM 15. The logic circuitry 13 is further coupled to external terminals 25 on which the logic circuitry transfers information to and from external circuits (not shown in FIG. 1) coupled to the Embedded DRAM 11.
In the Embedded DRAM 11, forming the logic circuitry 13 and the DRAM 15 in the same semiconductor substrate 17 yields numerous performance benefits. First, the bandwidth of the DRAM 15 may be substantially increased by increasing the width N of the internal data bus 21, where N may be 128, 256, or 512 bits, or even wider. As understood by one skilled in the art, increasing the width N of the internal data bus 21 increases the bandwidth of the DRAM 15 by enabling more data to be transferred during each access of the DRAM 15. In a conventional DRAM, an external data bus of the DRAM has a width that is limited by a number of factors, including the number of pins that can physically be formed on a package containing the DRAM and noise generated by switching multiple data lines in parallel, as understood by one skilled in the art. In contrast, the internal data bus 21 of the Embedded DRAM 11 requires no external pins, but is instead directly connected to the logic circuitry 13 through traces formed on the substrate 17. Thus, the width N may be very wide which, in turn, dramatically increases the bandwidth of the DRAM 15.
Additional advantages of the Embedded DRAM 11 over conventional discreet interconnected devices include lower power consumption and lower electromagnetic radiation due to the shorter lengths of conductive traces comprising the internal data bus 21. Furthermore, transmission line effects such as propagation delays are likewise alleviated due to such reduced lengths of the internal data bus 21. The shorter line lengths and corresponding reduced capacitance of individual lines in the bus 21 also reduce the noise resulting when switching the N lines in parallel.
In one application of the Embedded DRAM 11, the logic circuitry 13 is a microprocessor and the DRAM 15 is directly coupled to the microprocessor via the internal data bus 21. As understood by one skilled in the art, a memory controller is typically required between a conventional DRAM and a microprocessor because the DRAM has a much lower bandwidth than the processor. Thus, a conventional DRAM creates a xe2x80x9cbandwidth bottleneckxe2x80x9d that limits the speed at which a computer system including the DRAM and the processor can execute a program. In contrast, in the Embedded DRAM 11 the internal data bus 21 provides a very high bandwidth between the processor 13 and DRAM 15, making the Embedded DRAM 11 well suited to applications requiring very high bandwidths, such as networking, multimedia, and high-resolution graphics systems.
During the manufacture of the Embedded DRAM 11, the DRAM 15 needs to be tested just as with conventional DRAMs. Testing the DRAM 15, however, presents new problems not encountered when testing conventional DRAMs. More specifically, an external memory tester (not shown in FIG. 1) must transfer test data to and from the memory cells in the DRAM 15. The memory tester must be coupled to the DRAM 15 through the external terminals 25 on the Embedded DRAM 11, and must apply address, control, and data signals on such external terminals to transfer data to and from the memory cells in the DRAM 15. Due to the wide internal data bus 21 of the DRAM 15, however, there are many fewer external terminals 25 available on the Embedded DRAM 11 than there are data lines in the internal data bus 21. For example, if the internal data bus 21 is 512 bits wide, the Embedded DRAM 11 cannot include 512 external data terminals plus address and control terminals due to the physical limitations of forming such external terminals 25. Thus, in an Embedded DRAM there is a problem in transferring data between the DRAM and the memory tester in order to test the DRAM.
There is a need for a test circuit in an Embedded DRAM that enables a memory tester to test the DRAM portion of the Embedded DRAM.
The present invention relates to a method and apparatus for testing a memory portion of an Embedded DRAM. According to one inventive aspect of the present invention, a test circuit comprises a test mode terminal adapted to receive a test mode signal and a plurality of first-stage comparison circuits. Each first-stage comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each first-stage comparison circuit compares the binary values of the read and expect data signals and develops an inactive first-stage error signal on an output when the compared signals have the same binary values. When the compared signals have different binary values, each first-stage comparison circuit develops an active first-stage error signal on the output. A storage circuit is coupled to the outputs of the first-stage comparison circuits, and latches the first-stage error signals output by the first-stage comparison circuits. The storage circuit sequentially transfers the latched first-stage error signals onto a data terminal of the Embedded DRAM. A test control circuit is coupled to the first-stage comparison circuits, the test mode terminal, and the storage circuit. The test control circuit operates responsive to the test mode signal being active to apply data from addressed memory cells respectively on the first inputs of the first-stage comparison circuits. The test control circuit also applies respective expect data on the second inputs of the first-stage comparison circuits. The test control circuit controls the storage circuit to latch the resulting first-stage error signals and thereafter sequentially transfer the latched first-stage error signals onto the data terminal.
According to another inventive aspect of the present invention, the test circuit includes a second-stage comparison circuit coupled to the storage circuit and to an external terminal of the Embedded DRAM. The second-stage comparison circuit develops an active second-stage error signal on the external terminal when at least one of the first-stage error signals stored in the storage circuit is active. A test control circuit controls the first-stage and second-stage comparison circuits and the storage circuit in response to the test mode signal. When the test mode signal is active, the test control circuit applies data from addressed memory cells respectively on the first inputs of the first-stage comparison circuits and applies respective expect data on the second inputs of the first-stage comparison circuits. The test control circuit controls the storage circuit to latch the resulting first-stage error signals and the second-stage comparison circuit to develop the second-stage error signal on the external terminal.
Another inventive aspect of the present invention includes the test circuit further having a second storage circuit coupled to an external terminal of the Embedded DRAM and to the second-stage comparison circuit. The second storage circuit latches second-stage error signals output by the second-stage comparison circuit and sequentially transfers the latched second-stage error signals onto the external terminal of the Embedded DRAM. A test control circuit controls the first-stage and second-stage comparison circuits, and the first and second storage circuits responsive to the test mode signal. When the test mode signal is active, the control circuit applies data from a group of memory cells respectively on the first inputs of the first-stage comparison circuits and applies expect data on the respective second inputs of the first-stage comparison circuits. The test control circuit controls the first-stage storage circuit to latch the resulting first-stage error signals, and the second-stage comparison circuit to develop the second-stage error signal. The control circuit then controls the second storage circuit to latch the second-stage error signal output by the second-stage comparison circuit. The test control circuit accesses a plurality of groups of memory cells such that the second storage circuit stores a plurality of second-stage error signals. The control circuit thereafter controls the second storage circuit to sequentially transfer the stored second-stage error signals onto the external terminal.