1. Field of the Invention
The present invention relates to an integrated circuit technique, and, more particularly, to a technique for testing an integrated circuit. More specifically, the present invention relates to a technique for indicating an integrated circuit to enter a scan mode.
2. Description of Related Art
A full scan operation is a critical production test feature for an integrated circuit. However, an integrated circuit needs to be able to switch from a normal operational mode to a scan mode. However, entry of an integrated circuit into scan mode must be controlled in such a way that the part is not accidentally placed into scan mode.
The simplest way of accomplishing such scan mode control is to provide a dedicated pin on the integrated circuit for such an operation. FIG. 1 shows an integrated circuit 100 with a dedicated scan mode pin 102 according to the prior art. Scan mode pin 102 is solely reserved for signaling the integrated circuit into a scan mode. Larger chips, such as a system-on-a-chip, can accommodate a dedicated scan mode pin since it has extra pins to spare. However, smaller chips, such as small mixed-signal chips, typically have pin counts in the order of eight to twenty-eight pins, generally without any pins to spare.
A technique for providing scan mode control without requiring a dedicated or additional pin is shown in FIG. 2. FIG. 2 shows an integrated circuit 200 with an N-bit bus 201 coupled to an N number of pins 202a, 202b, . . . 202N, which are already existing pins and are not dedicated to scan mode, according to the prior art, and in which N is a positive integer. Pins 202a, 202b, . . . 202N are static mode pins. Static mode pins are pins that are either typically hard tied to a supply/ground or change in value only during global reset or power-down (e.g. do not change in value during normal operation) of integrated circuit 200. The technique involves using unused or a reserved combination of pins 202a, 202b, . . . and/or 202N, which then signals integrated circuit 200 to enter into scan mode. A disadvantage of this technique is that the unused/reserved combination of pins 202a, 202b, . . . and/or 202N used for indicating integrated circuit 200 for entering scan mode can no longer be used for some other operation, feature, mode, or purpose that may be added in the future. Another disadvantage is that some level of fault coverage on the combinational logic that the input pins directly drive may be lost.
Another prior art technique for providing scan mode control without requiring a dedicated pin is shown in FIGS. 3A and 3B. FIG. 3A shows an integrated circuit 300 with a control port 304 having a control port register (REG) 306 in which one of the bits in REG 306 is the scan mode indicator according to the prior art. A microcontroller 302 for controlling control port 304 is coupled to control port 304. Integrated circuit 300 also has a reset pin RST. FIG. 3B shows a detailed diagram of control port register (REG) 306 according to the prior art. REG 306 has a number of flip flops 308A, 308B, 308C, and 308D. Flip flop 308C is designated as the flip flop to provide the scan mode indicating bit.
Each of flip flops 308A, 308B, 308C, and 308D has an input D, an output Q, and a reset input that receives the reset signal from reset pin RST. Each of flip flops 308A, 308B, and 308D also has an input SCAN—IN. As shown in FIG. 3B, flip flop 308A receives data input D and provides output Q as the input SCAN—IN to flip flop 308B. Flip flop 308B also receives respective data input D and, in turn, provides output Q as the input SCAN—IN to flip flop 308D. Flip flop 308C is the scan mode indicating flip flop. An OR gate receives as inputs the fed-back output Q of flip flop 308C and the data input D that would normally be directly fed as input D into flip flop 308C. The output of the OR gate is instead fed as the input D into flip flop 308C. Flip flop 308C provides output Q as the SCAN—MODE signal. As an example, if SCAN—MODE signal is low, then integrated circuit 300 operates in the normal mode and normally-fed data input D is provided to flip flop 308C (e.g., the data input D ORed with a low SCAN—MODE signal equals the data input D). However, if SCAN—MODE signal is high, then integrated circuit 300 is signified to operate in the scan mode (e.g., the data input D ORed with a high SCAN—MODE signal equals the high SCAN—MODE signal). The high SCAN—MODE signal is provided as input D into flip flop 308C. The output of flip flop 308C provides a signal indicating that integrated circuit 300 is to operate in the scan mode.
Since control port 304 is similar to other digital components and is also scanned in the scan mode, flip flop 308C, which is associated with providing the scan mode indicating bit, must be set up and operated in an unique, particular way. As discussed earlier, the data logic value, input D, which normally is input directly to flip flop 308C, is instead fed into an OR gate, and an OR operation is performed on this input D with the SCAN—MODE signal. The output of flip flop 308C provides the scan mode indicator. Furthermore, flip flop 308C should not be made part of the scan chain. Flip flop 308C should be operated in this particular manner in order to ensure that integrated circuit 300 stays in the scan mode regardless of what the scan chain is doing. Integrated circuit 300 is able to exit scan mode through use of a global reset or powerdown signal since flip flop 308C generally has an asynchronous reset that is connected to the global reset.
However, scan mode control through use of a control port register is limited especially in situations in which the hardware does not have a control port. Also, specific attention and effort needs to be focused on ensuring that the flip flop designated for scan mode indication is not made part of the scan chain. Furthermore, the scan tool is generally not programmed on how the integrated circuit will enter the scan mode. Thus, the correct tester pattern needs to be manually generated. The correct tester pattern writes to the control port and it is appended to the beginning of the scan pattern generated by an Automatic Tester Pattern Generation Tool. Also, since the reset pin RST can return integrated circuit 300 to the normal operational mode when in the scan mode, faults on the reset line coupled to reset pin RST cannot be detected.
Thus, the present invention recognizes the desire and need for providing a simpler and improved technique for indicating an integrated circuit to enter the scan mode. The present invention further recognizes the desire and need to provide such a technique without having to utilize designated or additional pins of the integrated circuit. The present invention also recognizes the desire and need to provide a scan mode entry technique that avoids the use of a combination of pre-existing pins. The present invention additionally recognizes the desire and need of a scan mode entry technique that avoids the use of a control port and control port register. The present invention overcomes the problems and disadvantages in accordance with the prior art.