The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to low cost fabrication of double buried oxide (BOX), back gate (DBBG) silicon-on-insulator (SOI) wafers with built in shallow trench isolation (STI).
In SOI technology, a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply a BOX. For a single BOX SOI wafer, the thin silicon layer is divided into active regions by shallow trench isolation (STI), which intersects the BOX, providing a total isolation for the active regions. Sources and drains of field effect transistors (FETs) are formed, for example, by ion implantation of N-type and/or P-type dopant material into the thin silicon layer with a channel region between the source and drain using the gate pattern to self-define the channel region. Prior to the formation of sources and drains, gates are formed on top of the channel region, for example, by deposition of a gate dielectric and conductor on the top surface of the thin silicon, followed by photolithographic patterning, and etching. Back gates can also be formed under the active region on a single BOX SOI wafer using the BOX layer as the back-gate dielectric, and can be defined by either P+ or N+ implantation. Transistors with back gates typically use relatively thin silicon and BOX layers to enable fully depleted device operation with a threshold voltage which is responsive to the back gate. Such FETs built in thin SOI technology with back gates have significant advantages such as, for example, reduced short channel effects, less threshold variability due to body doping fluctuations, and ability to use the back gate voltage to adjust the threshold.
In addition to single BOX SOI substrates, double BOX substrates may also be used in forming transistor devices having dual gate electrodes formed both above and below the transistor channel region. The conductive gate material formed below the device channel, also referred to as a back gate, is separated from the SOI active layer by a first BOX, and is separated from the substrate by a second BOX.
Typically, in order to manufacture such a double BOX wafer having an upper BOX and a lower BOX therein, at least one preformed SOI wafer is used as a starting substrate. However, the cost of preformed SOI wafer is usually several times that of device-quality bulk silicon wafers. Thus, purchasing SOI wafers as a starting substrate adds to the cost of forming a double BOX SOI wafer. Moreover, conventional double BOX back gate (DBBG) SOI wafers formed without providing well defined n-well and p-well (or n-region and p-region) isolation in the back gate layer can result in unacceptably large junction and/or current leakage during back gate device operations. Accordingly, it would be desirable to be able to fabricate a substrate such as a double BOX back gate (DBBG) SOI wafer, with or without additional structures located therein, at a lower cost with respect to conventional processes and in a manner that also provides better isolation to alleviate the current leakage problem.