The present invention is related to a fin-shaped field-effect transistor (FinFET), more particularly a method for fabricating a FinFET for improving contact resistance.
A FET is a transistor having a source, a gate, and a drain. A FET employing a fin-shaped channel structure can be referred to as a FinFET. Fin field-effect transistors (FinFET) are multi-gate transistors where the conducting channel is wrapped around a thin piece of silicon, often referred to and configured as a “fin.” The dimensions of the fin structure determine the effective channel width of the transistor. Typically, the source, drain, and gate are formed by an extension above the substrate, and the FinFET is viewed as a MOSFET device with a folded gate feature. FinFETs provide a promising candidate for small line width technology because of their short channel effect control, scalability, and higher current drive per unit width.
FinFET is an attractive device structure in terms of short channel effect control. Generally, in a FinFET an epitaxial silicon (epi) layer is deposited over the fin structures to merge the fin structures together. The epi causes yield problems due to the epi defects. The contact resistance of the FinFET is increased because of the epi. Therefore, FinFET parasitics remain a concern and therefore there is a need to improve series resistance.
There is a need for a FinFET device that does not use epitaxy to merge the fins so that there can be improved contact resistance.