1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of raised drain and source regions by means of epitaxial growth.
2. Description of the Related Art
Presently, critical feature sizes of circuit elements of sophisticated integrated circuits are approaching 0.1 μm and less, wherein, in the field of CMOS production, one important design dimension in this respect is the gate length of corresponding field effect transistor elements. A field effect transistor comprises a gate electrode formed on a gate insulation layer that electrically insulates the gate electrode from a channel region yet also provides a required capacitive coupling so as to enable proper control of the channel formation that is initiated upon applying an appropriate control voltage to the gate electrode. The channel region connects two heavily doped regions, which are referred to as the source region and the drain region, that form the required PN junction, wherein a distance between the drain and source regions is denoted as the “channel length.” The channel length roughly corresponds to the gate length, as the gate electrode is used in the presently preferred CMOS technology as an implantation mask to form the drain and source regions in a self-aligned manner. The demand for fast operating integrated CMOS circuits, or any other integrated circuits, requires the reduction in size of the involved circuit elements, especially of the field effect transistors, as these transistor elements are usually operated in a switched mode, wherein the switching speed is significantly determined by parasitic capacitances and parasitic resistances of the transistor elements. By reducing, for instance, the channel length, and thus the gate length, of the transistor elements, a significant improvement with respect to signal processing performance may be obtained along with other advantages, such as increased package density, and thus increased functionality, of the integrated circuit. The steady decrease of the transistor dimensions, however, entails a plurality of issues that have to be dealt with so as to not unduly offset the advantages achieved by the size reduction of the circuit elements. For instance, the reduced feature sizes may also lead to reduced cross-sectional areas of lines and contact regions, thereby requiring increased dopant concentrations or other measures so as to maintain a required conductivity. Another issue arises from the fact that, as a general rule, a reduced gate length of a transistor also requires a reduced thickness of the gate insulation layer and shallow dopant profiles of the drain and source regions to provide the required controllability of the inversion channel.
With reference to FIGS. 1a–1c, some of the issues associated with the extreme size reduction of field effect transistors will now be described in more detail. In FIG. 1a, a field effect transistor 100 comprises a substrate 101, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, having formed thereon a crystalline silicon region 103 that is frequently referred to as the “active region.” The active region 103 is enclosed by an isolation structure 102, which is frequently provided in sophisticated transistor elements in the form of a trench isolation structure. A gate electrode 104 is formed above the active region 103 and is separated therefrom by a gate insulation layer 105. The gate electrode 104 may be comprised of doped polysilicon 106 and a metal silicide region 107 that may be comprised of, for instance, cobalt disilicide. Adjacent to the gate electrode 104, sidewall spacers 108 are located and are formed, for instance, of silicon nitride with a liner 109, for instance formed of silicon dioxide, disposed between the sidewalls of the gate electrode 104 and the upper surface of the active region 103 and the sidewall spacers 108. The active region 103 further comprises source and drain regions 110, wherein the dopant profile towards the gate electrode becomes shallower and corresponding portions 111 are frequently referred to as “extensions.” Metal silicide regions 112, typical comprised of cobalt disilicide in modem transistor elements, are formed within the drain and source regions 110.
A typical process flow for manufacturing the transistor 100 as depicted in FIG. 1a may comprise the following processes. After formation of the trench isolation structures 102 by sophisticated lithography, etch and deposition techniques followed by a chemical mechanical polishing (CMP) sequence, an implantation cycle may be performed so as to provide a required vertical dopant profile within the active region 103. Corresponding processes are well established in the art and a detailed description is thus omitted herein. Thereafter, the gate insulation layer 105 may be formed by sophisticated oxidation and/or deposition techniques, followed by the formation of the gate electrode 104, which is typically formed by patterning a polysilicon layer by means of advanced lithography and etch techniques. A first implantation cycle may be carried out to form the extensions 111, and, subsequently, the liners 109 may be formed by, for example, an oxidation process. Next, the sidewall spacers 108 may be formed so as to serve as an implantation mask for forming the drain and source regions 110. The actually performed implantation cycles may include a plurality of implantation steps, for instance including tilted implantation sequences, so as to obtain the required complex dopant profile for the drain and source regions 110 and the extension 111. Thereafter, one or more anneal cycles are carried out so as to activate the dopants implanted into the active region 103 and to, at least partially, re-crystallize portions of the active region 103 damaged by the preceding ion implantation sequence. Since relatively high temperatures are necessary to activate the dopants, the anneal cycles are accompanied by increased diffusion of the dopants, thereby significantly affecting the finally obtained dopant profile. As the transistor dimensions are steadily reduced, the final dopant concentrations have, however, to be precisely controlled during the manufacturing process of the transistor 100 so as to assure the required transistor performance. For instance, as the channel length decreases, ie., the lateral distance of the extensions 111 in FIG. 1a, extensive lateral diffusion is to be precisely controlled. Thus, a so-called thermal budget is established that sets forth the maximum amount of heat treatments that may be applied to the transistor during fabrication without causing unacceptable diffusion of the various doped regions over time during the manufacturing process of the transistor device 100. Consequently, the thermal budget for the transistor 100 should be maintained as low as possible to not unduly “smear” the dopant profile and, hence, compromise the transistor characteristic.
Thereafter, the silicide regions 112 and 107 (see FIG. 1a) may be formed so as to significantly lower the contact resistance of the drain and source regions 110 as well as the line resistance of the gate electrode 104. As previously explained, in sophisticated transistor elements, extremely shallow dopant profiles for the extensions 111 and the drain and source regions 110 are required that, in turn, restricts the available depth to which the silicide regions 112 may be formed. Furthermore, since the silicide regions 112 and 107 are typically formed simultaneously in a self-aligned manner, the depth restriction with respect to the silicide regions 112 also affects the finally obtained depth of the region 107 in the gate electrode 104, and thus significantly influences the degree of conductivity improvement achieved in the gate electrode 104.
Typically, a cobalt layer is deposited and a heat treatment is performed so as to initiate a chemical reaction, thereby forming cobalt silicide at device regions containing silicon, whereas a reaction of cobalt with the sidewall spacers 108 and the isolation structures 102 is substantially prevented. Thereafter, the non-reacted cobalt is selectively removed and a further heat treatment is performed so as to convert the relatively high ohmic cobalt silicide into a stable and highly conductive cobalt disilicide.
As explained above, the reduced depth of the drain and source regions 110 may not allow the formation of sufficiently dimensioned metal silicide regions 112 and 107 so as to provide the required low contact resistance and sheet resistance, respectively.
As shown in FIG. 1b, a different approach is, therefore, frequently employed. Here, prior to the formation of the metal silicide regions 112, 107, an epitaxial growth process is performed so as to selectively increase the thickness of exposed silicon areas, while substantially not affecting the isolation structure 102 and the sidewall spacers 108. As shown, additional silicon regions 113 are formed above the drain and source regions 110 and a corresponding silicon region 114 may be formed on top of the polysilicon gate 104. Finally, a silicidation process is performed as is described with reference to FIG. 1a. The silicide thickness stays the same, thus enabling the silicon thickness of SOI substrate wafers to be decreased. It turns out, however, that the epitaxial growth as shown in FIG. 1b is sensitively influenced by the surface quality of the drain and source regions 110. It has been found that a moderately large amount of contamination, for instance carbon and oxygen atoms, are incorporated in a surface region 115 (see FIG. 1b) of the drain and source regions 110, which substantially prevent an effective growth process for forming the additional silicon regions 113. This is particularly true for the different substrates in CMOS technology, i.e., NMOS and PMOS areas. Conventionally, the transistor 110 is subjected to an anneal cycle at temperatures above 1000° C. in a hydrogen atmosphere so as to remove the contamination from the surface region 115, thereby improving the surface quality to a degree that allows successful growth of the regions 113. The elevated temperatures applied during the anneal cycle prior to the epitaxial growth process, however, significantly contribute to the thermal budget of the transistor 100, thereby significantly deteriorating the dopant profile of the drain and source regions 110 and the extensions 111.
The deterioration of the dopant profile may thus limit further device scaling, although the approach of raised silicide regions on the drain and source regions 110 offers the potential to significantly reduce the contact and sheet resistance of the corresponding silicon regions.
In view in of the above-identified problems, a need exists to provide an improved technique that enables the formation of raised drain and source regions without unduly deteriorating the thermal budget during the transistor fabrication.