As standard semiconductor manufacturing techniques are pushed toward shorter gate length, they approach the manufacturing limit of classic semiconductor technology. In order to further improve performances, reduce power consumption and packaging costs, integration techniques, such as 3D integration are becoming more and more common.
3D integration consists in connecting at least two modules such as a semiconductor die, an optical module, a heat dissipation module, a biological module, and a memory, by stacking them one upon each other. Such an approach has several advantages. PCB-requirements are more relaxed since the integration is performed on a vertical direction. Power consumption of the input/output interfaces as well as signal quality are improved by connecting the modules to each other without making usage of long connecting cables or lines. Costs are reduced since a single package is required instead of a multitude of packages. Such integration technique allows miniaturization of a high complexity system within a single package.
Various techniques for connecting the multitude of modules stacked one upon the other have been developed. In order to connect at least two modules one upon each other, one possible technique consists in direct bonding. In such a technique, two modules, for instance, two semiconductor dies, are placed one upon each other and pressed against each other at a relatively low temperature, so that electrical contacts at the interface between the two dies can be created.
For instance, as can be seen in FIG. 8A, a first semiconductor die 8000 having a first surface 8100 might include a connecting structure 8200 composed by a conductive layer 8220 surrounded by a diffusion barrier layer 8211. At the same time, a second semiconductor die 8700 might have a first surface 8710 and might incorporate a connecting structure 8200 including a conductive layer 8220 and a diffusion barrier layer 8211. The connecting structure 8200 of the first semiconductor die 8000 and the connecting structure 8200 of the second semiconductor die 8700 might be substantially similar.
3D integration might be performed by pressing the second semiconductor die 8700 on top of the first semiconductor die 8000 such that the first surface 8710 of the second semiconductor die 8700 presses against the first surface 8100 of the first semiconductor die 8000. During such a procedure, the first semiconductor die 8000 and the second semiconductor die 8700 should be aligned, at least along a direction 1900, so that the connecting structure 8200 of the first semiconductor die 8000 is aligned with the substantially similar connecting structure 8200 of the second semiconductor die 8700. This is illustrated in FIG. 8B and U.S. Pat. No. 6,962,835.
Due to technological limits, however, a perfect alignment as shown in FIG. 8B can be hard to achieve. Practically, a small misalignment can be present, at least in one direction. As an example, in direction 1900, as illustrated by the misalignment value M in FIG. 8A. When such a 3D integration is performed subjected to the misalignment value M, a result as illustrated in FIG. 8C can be obtained.
As can be seen in FIG. 8C, the connecting structure 8200 of the first semiconductor die 8000 might not be aligned with the connecting structure 8200 of the second semiconductor die 8700. A mismatch region 8500 can therefore be present, in which the conductive layer 8220 of the connecting structure 8200 of the second semiconductor die 8700 is placed above the diffusion barrier layer 8211 of the connecting structure 8200 of the first semiconductor die 8000 as well as being placed over a region of the semiconductor die 8000 not including the connecting structure 8200 of the first semiconductor die 8000.
In such a case, if, for example, the conductive layer 8220 of the connecting structure 8200 of the second semiconductor die 8700 is realized with copper, and the first semiconductor die is, for example, a silicon semiconductor die, there might be the possibly of the copper diffusing into the part of the first semiconductor die 8000 not corresponding to the connecting structure 8200 of the first semiconductor die 8000 through region 8500.
This problem is present in current 3D integration techniques and can therefore prevent or limit the application of such techniques in industrial manufacturing of integrated systems. Thus, improvements in this area are needed.