1. Field of the Invention
The present invention relates to an output circuit, and more particularly, to an output circuit configured to perform control of turning on/off a MOS transistor connected to high voltage using a low voltage signal, to thereby generate an output signal.
2. Description of the Related Art
Output circuits that generate an output signal for driving a load operating under a high voltage of several tens of volts are, for example, configured to turn on/off a MOS transistor connected to high voltage using a low voltage signal, to thereby obtain an output signal at high voltage from the MOS transistor.
As an example of such output circuits, a related-art output circuit 600 is illustrated in a circuit diagram of FIG. 6.
The related-art output circuit 600 includes a power supply terminal 601, a ground terminal 602, an input terminal 615, an NMOS transistor 616, resistors 611 and 613, a Zener diode 610, a PMOS transistor 612, and an output terminal 614.
The PMOS transistor 612 has a source connected to the power supply terminal 601, and a drain connected to the output terminal 614. The resistor 611 has one end connected to the power supply terminal 601. The Zener diode 610 has a cathode connected to the power supply terminal 601, and an anode connected to the other end of the resistor 611 and a gate of the PMOS transistor 612. The resistor 613 has one end connected to the anode of the Zener diode 610. The NMOS transistor 616 has a gate connected to the input terminal 615, a source connected to the ground terminal 602, and a drain connected to the other end of the resistor 613.
The related-art output circuit 600 is configured to perform operation of turning on/off the NMOS transistor 616 with an input signal IN at low voltage input to the input terminal 615, thereby driving the PMOS transistor 612 to output an output signal to the output terminal 614.
As a first state, a case in which the NMOS transistor 616 is turned on is assumed. Current is caused to flow through the Zener diode 610, the resistor 613, and the resistor 611, and a gate voltage VGATE of the PMOS transistor 612 is clamped by a breakdown voltage Vz of the Zener diode 610. That is, the gate voltage VGATE of the PMOS transistor 612 is a voltage obtained by subtracting the breakdown voltage Vz of the Zener diode 610 from a voltage VDD at the power supply terminal 601, which is a high voltage. Thus, the PMOS transistor 612 can be turned on with a gate-source voltage being prevented from exceeding a withstand voltage of the PMOS transistor 612. The resistor 613 is a resistor necessary for restricting current that flows through the Zener diode 610.
As a second state, a case in which the NMOS transistor 616 is turned off is assumed. The gate voltage VGATE of the PMOS transistor 612 is pulled up to the voltage VDD of the power supply terminal 601 by the resistor 611, and the PMOS transistor 612 is thus turned off.
As described above, according to the related-art output circuit 600, the PMOS transistor 612 can be switched based on a signal input to the input terminal 615 while the gate-source voltage of the PMOS transistor 612 is prevented from exceeding the withstand voltage of the PMOS transistor 612, and output can be obtained from the output terminal 614 (for example, see Japanese Patent Application Laid-open No. Hei 8-139588).
However, the related-art output circuit 600 as described above has a problem in that it is difficult to perform switching operation of the PMOS transistor 612 at high speed.
The reason is that, in turning on/off the PMOS transistor 612, a gate-source capacity of the PMOS transistor 612 is charged through the resistor 613 and is discharged through the resistor 611, and hence charging and discharging take a long time.
In FIG. 7, the wavelengths of the input signal IN and the gate voltage VGATE of the PMOS transistor 612 of the related-art output circuit 600 are shown. The maximum value of the input signal IN is 5 V and the minimum value thereof is 0 V. When the input signal IN rises at time t0, the gate-source capacity of the PMOS transistor 612 is charged through the resistor 613. As shown in FIG. 7, the voltage VGATE decreases and is clamped by the breakdown voltage Vz of the Zener diode 610 to be stabilized at VDD-Vz finally. The voltage VGATE takes a long time to be stabilized as shown in FIG. 7 although this charging time is proportional to the size of the resistor 613, and varies depending on how large the resistor 613 is.
Thus, the charging time from time t0 at which the input signal IN rises to time t1 at which the voltage VGATE reaches a steady-state value is long, and the switching operation is accordingly slow.
Meanwhile, when the input signal IN falls at time t2, the gate-source capacity of the PMOS transistor 612 is discharged through the resistor 611. As shown in FIG. 7, the voltage VGATE increases to be stabilized at the voltage VDD finally. The voltage VGATE takes a long time to be stabilized as shown in FIG. 7 although this discharging time is proportional to the resistance value of the resistor 611, and varies depending on how large the resistance value of the resistor 611 is.
Thus, the discharging time from time t2 at which the input signal IN falls to time t3 at which the voltage VGATE reaches the steady-state value is long, and the switching operation is accordingly slow.