1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more specifically to a circuit for generating an erase verify voltage and a read voltage in an erasable non-volatile semiconductor memory.
2. Description of Related Art
Conventionally, in an erasable, writable and readable non-volatile semiconductor memory such as an EPROM, EEPROM and a flash memory, after an erasing or writing is carried out, an erase verifying or a write verifying is carried out in order to ascertain whether or not the erasing or writing has been properly conducted, and thereafter, a reading operation is carried out. For this purpose, it is an ordinary practice to set and generate an erase verify voltage, a write verify voltage and a read voltage to be applied as a gate voltage of a memory cell at an erase verifying time, a write verifying time and a reading time, respectively, so that one of these set voltages is selected to be supplied to a respective word line.
For example, FIG. 4 is a circuit diagram of a circuit portion of generating the erase verify voltage in the prior art non-volatile semiconductor memory. The erase verify voltage generating circuit shown in FIG. 4 receives, as a reference voltage, a sufficiently high, stable external voltage supplied from an external device such as a data writing device used at a memory data writing time. The erase verify voltage generating circuit includes a resistor 1 connected between the externally supplied reference voltage and ground, for outputting a voltage V.sub.1 by action of a resistance division of the resistor 1, and an N-channel non-doped transistor 2 having a gate connected to receive the voltage V.sub.1, a drain connected to receive the externally supplied reference voltage and a source for outputting the erase verify voltage which is used as the memory cell gate voltage at the erase verifying time.
Namely, assuming that, as shown in FIG. 4, resistance of two resistor components obtained by dividing the resistor 1 are R.sub.1 and R.sub.2 and the externally supplied reference voltage is Vr, it becomes EQU V.sub.1 ={R.sub.2 /(R.sub.1 +R.sub.2)}.times.Vr (1)
Since the N-channel non-doped transistor 2 has a threshold voltage which is ordinarily 0V, the erase verify voltage EO at the erase verifying time becomes the same as V.sub.1. At this time, since a temperature-depending variation of the resistance of the dividing resistors R.sub.1 and R.sub.2 of the resistor 1 is the same, the erase verify voltage EO has almost zero temperature-depending variation attributable to an internal circuit of the erase verify voltage generating circuit, and therefore, has only a temperature dependency equal to that of the externally supplied reference voltage. However, the externally supplied reference voltage itself does not have a temperature dependency.
A circuit for generating a read voltage RO which is used as a gate voltage of the memory cell at a reading time, has fundamentally the same circuit construction as that of the erase verify voltage generating circuit as mentioned above, although the generated read voltage RO is different in magnitude from the erase verify voltage EO.
Referring to FIG. 5, there is shown a characteristic diagram illustrating the erase verify voltage EO, the read voltage RO and the temperature dependency of the threshold voltage VT of the memory cell in this prior art non-volatile semiconductor memory. Now, a method for setting the erase verify voltage EO and the read voltage RO will be described with reference to FIG. 5.
In general, the erase verify voltage EO and the read voltage RO are determined on the basis of a reading speed at the reading time and a maximum value of the threshold voltage of the erased memory cell. In brief, when the memory cell is in an erased condition, the threshold voltage VT of the memory cell ordinarily scatteringly lies in the range of for example 2V to 0.5V. Therefore, the erase verify voltage EO is set to be slightly higher than the maximum value of the threshold voltage range of the erased memory cell. In particular, since the threshold voltage of the memory cell has a negative temperature dependency, the erase verify voltage EO is set to be slightly higher than the maximum value of the threshold voltage of the memory cell erased at a low temperature.
On the other hand, in order to realize a satisfactory reading speed at the reading time, it is necessary to set the read voltage RO so as to fulfill the following relation: EQU EO&lt;&lt;RO (2)
At this time, since the erase verify voltage EO and the read voltage RO are determined by the ratio of the dividing resistors having the same temperature-depending variation, and since the externally supplied reference voltage itself does not have a temperature dependency, the erase verify voltage EO and the read voltage RO have no temperature-depending variation, as shown in FIG. 5. On the other hand, the threshold voltage VT of the memory cell has the temperature dependency.
In particular, with recent microminiaturization of the semiconductor device, the size of the memory cell itself becomes small. In addition, with a low power supply voltage inclination, a margin required for the reading speed also becomes small, with the result that it becomes difficult to ensure the necessary margin sufficient to cover the variation of the threshold voltage VT of the memory cell caused by the temperature variation.
Now, this problem will be described with reference to FIG. 5.
In an actual use of the prior art non-volatile semiconductor memory, when the erasing operation has been verified by executing the erasing and the erase verifying at a high temperature, there has existed the memory cell having the threshold VT which is slightly lower than the erase verify voltage EO, as indicated by the point B in FIG. 5. On the other hand, if the non-volatile semiconductor memory including this memory cell is used at a low temperature, the threshold voltage VT of the memory cell concerned becomes higher than the threshold voltage at the high temperature, so that the threshold voltage VT becomes as indicated by the point A in FIG. 5, for example. If the memory reading operation is executed in this condition, since a difference between the reading voltage RO and the threshold voltage VT is small as indicated by the margin C in FIG. 5, a memory cell current becomes small, with the result that the reading speed becomes slow, and therefore, the standard can no longer be satisfied.
In the prior art in which the microminiaturization had not yet been advanced and the power supply voltage being used was still high, it was possible to ensure a large voltage difference between the erase verify voltage EO and the read voltage RO, and therefore, it was also possible to cause this voltage difference to include the variation component of the memory cell threshold VT caused by the temperature variation. At present, however, since the power supply voltage has become low so that the shifting amount of the memory cell threshold caused by the writing also becomes small, and since the variation in the threshold voltage after the erasing becomes large, the prior art method for setting the erase verify voltage EO and the read voltage RO has become difficult to ensure a large margin required for the satisfactory reading speed, with the result that it has become difficult to obtain a non-volatile semiconductor memory meeting with the standard.