1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device including a CMOS logic circuit and a non-volatile memory cell, especially to a method for fabricating a semiconductor device including a CMOS logic circuit and a non-volatile memory cell, which includes a step of performing silicidation of a diffusion layer.
2. Description of the Related Art
In recent years, semiconductor devices fabricated with a non-volatile memory cell and a CMOS logic circuit within one chip, in order to increase integration and decrease cost, have been in the spotlight. Reductions in the number of steps and in the cost are realized by making the respective processes common type of consolidated non-volatile memory cell and CMOS circuit chip.
A first conventional example, in which a transistor diffusion layer structuring a CMOS logic circuit and a transistor diffusion layer structuring a non-volatile memory cell circuit are both silicidated, and a second conventional example, in which the two diffusion layers are not silicidated, are used in the conventional consolidation processes.
The first conventional technique is explained while referring to FIG. 27.
A transistor formed in a logic Tr region is prepared with an N-type diffusion layer 64, which becomes a source and a drain, in a P-well 45 formed inside a P-type semiconductor substrate 49, and a lightly doped drain (LDD) 63 formed in correspondence with the diffusion layer 64. A polysilicon gate electrode 65 formed through a gate insulating film 54, a tungsten silicide (WSi) 56 formed on the gate electrode 65, sidewalls 57 covering the side faces of the gate electrode 65 and the WSi 56, and a titanium silicide (TiSi) formed on the diffusion layer 64 are prepared on a channel region sandwiched by the diffusion layer 64, and there is contact to an upper layer Al wiring 60 through a contact electrode 47.
In addition, a memory cell 38 formed in a memory cell region is structured and prepared with an N-well 44 formed in order to provide separation from the P-well 45 in which the above CMOS transistor is formed, a P-well 43 formed in the N-well 44, an N-type drain diffusion layer 41 and an N-type source diffusion layer 42 formed inside the P-well 43, a TiSi 58 formed inside the drain diffusion layer 41 and the source diffusion layer 42, a polysilicon floating gate 39 formed through an insulating film 51 on a channel region formed by the drain diffusion layer 41 and the source diffusion layer 42, a polysilicon control gate 40 formed through an insulating film 53 formed on the floating gate 39, the WSi 56 formed on the control gate 40, and sidewalls 57 formed covering the side faces of the floating gate 39, the insulating film 53, the control gate 40, and the WSi 56. The drain diffusion layer 41 is connected to the upper layer A1 wiring 60 through a drain contact 46.
The realization of a high performance CMOS logic circuit is the objective in the first conventional technique, so it is necessary to form the TiSi 58 in order to reduce the resistance of the diffusion layer 64 of the CMOS transistor and increase the operating speed. However, if the TiSi is formed on the diffusion layer 64, which contains impurities of a high concentration, aggregations of silicide develop, and the layer resistance is scattered, so the diffusion layer concentration in the CMOS transistor diffusion layer 64 must be reduced. The CMOS transistor diffusion layer formation processes and the memory cell diffusion layer formation processes are common here, so the memory cell diffusion layer concentration becomes weak, a depletion develops when programming to the memory cell transistor, and the program speed drops. Therefore, the operating speed of the CMOS transistor can be increased with the first conventional technique, but on the other hand, it has a problem in which the operating speed of the memory cell transistor drops.
The second conventional technique is explained next, referring to FIG. 28.
The second conventional technique differs from the first conventional technique in the point that the TiSi is not formed in the diffusion layer 64 of the CMOS transistor, and in the diffusion layers forming the source 41 and the drain 42 of the memory cell transistor, and the point that the concentration is set high in these diffusion layers, while other points are nearly identical. The TiSi cannot be formed here because the diffusion layer concentration is set high, and because there is the problem, as stated above, that aggregation of silicide occurs. Therefore, by increasing the diffusion layer concentration of the source 41 and the drain 42 of the memory cell transistor, the memory cell programming speed can be increased, but on the other hand, there is a problem in which the operating speed of the CMOS transistor drops because its diffusion layer cannot be made low resistance.
From the first and second conventional techniques, it can be considered that by protecting the memory cell region from silicide processes, and by making the diffusion layer electrodes separately, the performance of the memory cell transistor and the CMOS transistor will be increased. However, in order to protect from normal silicide processes, two photolithography steps, and mask material growth and etching steps are necessary. In addition, apertures are formed in the diffusion layer of the CMOS transistor, so the width of the CMOS transistor sidewalls changes after removing the mask material. A detailed explanation of these processes is given below using FIGS. 29 to 31.
First, in order to form a TiSi layer, three steps are necessary. Step 1: making the diffusion layer surface amorphous by ion implantation of arsenic, etc.; step 2: sputtering titanium; and step 3: heat treatment. Of these, it is not possible to eliminate the heat treatment of step 3, so the other two are considered. Titanium is formed on the diffusion layer by step 2 by eliminating only the amorphous making step 1 by eliminating only the amorphous making step 1, so the formation of TiSi cannot be completely prevented. Furthermore, arsenic or the like is ion implanted on the diffusion layer by step 1 by eliminating only the titanium sputtering step 2, so the diffusion layer impurity distribution is broken down. Therefore, in order to prevent the formation of TiSi, it is necessary to mask process both the amorphous making step 1 and the titanium sputtering step 2.
Therefore, in order to selectively perform step 1, making the surface of the diffusion layer 64 amorphous, a photoresist 61 is selectively formed to cover the memory cell region as shown in FIG. 29, and arsenic ion implantation is performed. However, a through film 48 is formed from an oxide film in order to prevent undesirable destruction of the crystal structure by ion implantation, and in order to control the dose amount.
Next, in order to perform the titanium sputtering step 2, after removal of the photoresist 61, a mask oxidation film 66 which is between 500 and 1000 angstroms thicker than the through film 48 is formed as shown in FIG. 3C as a protection film corresponding to the titanium sputtering. The mask oxidation film 66 is selectively etched, and a photoresist 62 is formed in order to expose the diffusion region 64, and the mask oxidation film 66 is left on the memory cell region, as shown in FIG. 31. When etching the mask oxidation film 66, the width of the sidewalls 57 gets larger for the case of plasma etching being used, and the controllability of the width of the sidewalls 57 deteriorates for the case of wet etching being used. The use of plasma etching is explained here. The mask oxidation film 60 formed by plasma etching is used as a mask for titanium sputtering, and titanium grows on the exposed diffusion region 64. Heat treatment is performed afterward, and titanium and silicon are reacted, turning into a silicide. Un-reacted titanium is etched, forming a TiSi layer 58 selectively on the diffusion layer 64.
Thus not only is there an increase in the process steps for the case of selectively making TiSi only in the CMOS transistor source and drain, the CMOS transistor sidewalls also become wider or the controllability of the sidewall width deteriorates, so a problem develops in which the reliability of the CMOS transistor deteriorates.
An object of the present invention, therefore, is to provide a process of forming a consolidated non-volatile memory cell and CMOS transistor without deteriorating the reliability and performance of each device.
A method of manufacturing a semiconductor device according to the present invention is characterized by having:
a step of forming a semiconductor substrate having a memory cell region in which a memory cell transistor is formed, and a CMOS logic region in which a CMOS transistor is formed, and of forming a gate electrode used by the memory cell transistor in the memory cell region;
a first impurity injection step of forming a diffusion layer in the memory cell region, with the gate electrode used by the memory cell transistor as a mask;
a step of forming a gate electrode used by the CMOS transistor in the CMOS logic region;
a second impurity injection step of forming a lightly doped drain in the CMOS logic region, with the gate electrode used by the CMOS transistor as a mask;
an insulating film formation step of forming an insulating film covering the memory cell region and the CMOS logic region;
a step of forming a mask layer to cover the memory cell region, excluding the CMOS logic region;
a step of selectively etching the insulating film in correspondence with the mask layer, and forming sidewalls in the side faces of the gate electrode used by the CMOS transistor;
a third impurity injection step of forming a diffusion layer of the CMOS transistor in the CMOS logic region, with the sidewalls as a mask;
a step of depositing a metal on the entire surface after removing the mask layer; and
a step of reacting the deposited metal and the exposed diffusion layer of the CMOS transistor to form a metal silicide.
In addition, according to a second aspect of the present invention, a method of manufacturing a semiconductor device is characterized by having:
a step of forming a semiconductor substrate having a memory cell region in which a memory cell transistor is formed, and a CMOS logic region in which a CMOS transistor is formed, and of forming a gate electrode used by the memory cell transistor in the memory cell region;
a first mask step of selectively masking one region selected from a region in which a source of the memory cell transistor must be formed, and a region in which a drain of the memory cell transistor must be formed;
a first impurity injection step of forming a first diffusion layer in the non-selected region;
a step of removing the mask formed by the first mask step;
a step of forming a gate electrode used by the CMOS transistor in the CMOS logic region;
a second mask step of selectively masking the non-selected region of the memory cell region;
a second impurity injection step of forming a lightly doped drain in the CMOS logic region, with the gate electrode used by the CMOS transistor as a mask, together with forming a lightly doped drain region in the selected region of the memory cell region, with the mask formed by the second mask step as a mask;
a step of removing the mask formed by the second mask step;
an insulating film formation step of forming an insulating film covering the memory cell region and the CMOS logic region;
a step of forming a mask layer to cover the other region of the memory cell region, excluding the CMOS logic region and the selected region of the memory cell region;
a step of selectively etching the insulating film in correspondence to the mask layer, and forming sidewalls in the side faces of the gate electrode used by the CMOS transistor and in one side face of the memory cell transistor;
a third impurity injection step of forming a diffusion layer of the CMOS transistor in the CMOS logic region, and a second diffusion layer of the memory cell transistor in the other region of the memory cell region, with the sidewalls as a mask;
a step of depositing a metal on the entire surface after removing the mask layer; and
a step of reacting the deposited metal with the exposed diffusion layer of the CMOS transistor and with the exposed second diffusion layer of the memory cell transistor to form a metal silicide.
In addition, according to a third aspect of the present invention, a method of manufacturing a semiconductor device is characterized by having:
a step of forming a semiconductor substrate having a memory cell region in which a memory cell transistor is formed, and a CMOS logic region in which a CMOS transistor is formed, and of forming a gate electrode used by the memory cell transistor in the memory cell region;
a first mask step of selectively masking a portion of a region in which a drain of the memory cell transistor must be formed;
a first impurity injection step of forming a first diffusion layer in remaining regions, excluding the masked region;
a step of removing the mask formed by the first mask step;
a step of forming a gate electrode used by the CMOS transistor in the CMOS logic region;
a second mask step of selectively masking the remaining regions of the memory cell region;
a second impurity injection step of forming a lightly doped drain in the CMOS logic region, with the gate electrode used by the CMOS transistor as a mask, together with forming a lightly doped drain region in the selected region of the memory cell region, in correspondence to the mask formed by the second mask step;
a step of removing the mask formed by the second mask step;
an insulating film formation step of forming an insulating film covering the memory cell region and the CMOS logic region;
a step of forming a mask layer to cover the remaining regions of the memory cell region, excluding the CMOS logic region and the selected region of the memory cell region;
a step of selectively etching the insulating film in correspondence to the mask layer, and forming sidewalls in the side faces of the gate electrode used by the CMOS transistor;
a third impurity injection step of forming a diffusion layer of the CMOS transistor in the CMOS logic region, and a second diffusion layer of the memory cell transistor in the selected region of the memory cell region, with the sidewalls as a mask;
a step of depositing a metal on the entire surface after removing the mask layer; and
a step of reacting the deposited metal with the exposed diffusion layer of the CMOS transistor and with the exposed second diffusion layer of the memory cell transistor to form a metal silicide.
Thus, by covering the memory cell region with an insulating film and exposing only the diffusion layer region of the CMOS logic region, in accordance with the present invention, the deposited metal reacts with only that diffusion region, and does not impart influence to the memory cell transistor, so the reduction of the CMOS transistor source and drain resistance can be realized by adding only this insulating film masking step.
In addition, by making a metal silicide in either the source or the drain, according to the second aspect of the present invention, an increase in the operating speed of the memory cell transistor can be realized by adding only the above insulating film masking step.
Furthermore, by making a metal silicide in a portion of the drain, according to the third aspect of the present invention, an increase in the operating speed of the memory cell transistor can be realized by adding only the above insulating film masking step.