FIG. 11 shows a typical structure of a conventional demodulator. Referring to FIG. 11, this demodulator includes a quadrature detecting unit 1, an automatic amplitude controller (AGC) 3, an error detection unit 3 and an amplitude error detection unit 4.
An input modulated signal is assumed to have been modulated in accordance with a quadrature modulation system, such as QPSK (quadrature phase shift keying) or QAM (quadrature amplitude modulation). The respective quadrature components (channels) are termed an in-phase component or channel (Ich) and a quadrature component or channel (Qch), respectively. A quadrature detecting unit 1 receives a quadrature modulated signal, as an IF (intermediate frequency) signal, and outputs an output signal as baseband signals Ich1 and Ich2. Meanwhile, the quadrature detecting unit 1 is made up of a known detection circuit, such as a synchronous detector, a semi-synchronous detector, or a delay detector.
The AGC 2 is fed with Ich2 and Qch2 and, using amplitude error signals Ai, Aq, fed from the amplitude error detection unit 4, corrects the amplitude errors to output signals Ich3, Qch3 each having a regular amplitude.
The error detection unit 3 uses (receives) Ich3, Qch3, output from the AGC 2, to output error signals Ei, Eq and polarity signals Di, Dq.
The amplitude error detection unit 4 uses the signals Ei, Eq, Di and Dq, output by the error detection unit 3, to output Ai and Aq as respective amplitude error signals of Ich and Qch.