The continuous shrinking in dimensions of electronic devices utilized in ultra-large scale integrated (ULSI) circuits in recent years has resulted in increasing the resistance of the back-end-of-the-line (BEOL) metallization without concomitantly decreasing the interconnect capacitances. Often interconnects are even scaled to higher aspect ratios to mitigate the resistance increases, leading to increased capacitance. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) dielectrics and particularly those with k significantly lower than silicon dioxide are being introduced to reduce the capacitance.
The low-k materials that have been considered for applications in ULSI devices include polymers containing Si, C, and O, such as methylsiloxane, methylsilsesquioxanes, and other organic and inorganic polymers which are fabricated by spin-on techniques or, Si, C, O and H containing materials (SiCOH, SiOCH, carbon-doped oxides (CDO), silicon-oxycarbides, organosilicate glasses (OSG)) deposited by plasma enhanced chemical vapor deposition (PECVD) techniques.
The incorporation of the low-k dielectrics in the interconnect structures of integrated circuits (IC) often requires the use of other dielectric materials as diffusion barrier caps or etch-stop and chemo-mechanical polishing (CMP) hardmasks. The adhesion among the different layers in the complex structures of an IC device is often too low, resulting in delaminations during the processing of the device, or reduced reliability in response to thermomechanical stresses imposed by typical chip packaging materials.
FIG. 1 shows a typical prior art interconnect structure 10 that includes a lower level chemical vapor deposited (CVD) low-k SiCOH dielectric 12 and an upper level CVD low-k SiCOH dielectric 20. Each of the dielectric levels 12 and 20 includes metal wiring regions 14 formed therein. The metal wiring regions 14 are capped with a diffusion barrier capping dielectric 18 that is comprised of a dielectric containing C, Si, N and H (i.e., CSiNH).
Due to the CSiNH pre-cleaning process, which includes a NH3 pretreatment, each of the SiCOH surfaces form a thin layer of SiON 16. The SiON layer 16 includes the following three regions: an upper region which is near the interface of the CSiNH capping dielectric 18 that is nitrogen rich SiON, a middle region that is oxygen rich SiON, and a lower region that is carbon depleted. The carbon depleted region extends continuously into an upper surface region of each SiCOH dielectric.
In the packaging process, a crack typically forms between the CSiNH capping dielectric 18 and the upper SiCOH dielectric 20, which indicates that the interface 19 between the CSiNH capping dielectric 18 and the upper SiCOH dielectric 20 is weak. Moreover, under stress, delamination of the CSiNH capping dielectric 18 and the upper SiCOH dielectric 20 may occur at interface 19. Adhesion tests show that the interface 19 between the CSiNH capping layer 18 and the upper level SiOCH dielectric 20 has a poor adhesion coefficient; the same test show that the adhesion coefficient between the lower dielectric 12 and the CSiNH capping layer 18 is improved due to the presence of the SiON layer. The current adhesion between the upper level SiCOH dielectric 20 and the underlying CSiNH capping layer 18 is in the range of 2 to 4 J/m2, which is below the value of the cohesive strength of SiCOH material (6 J/m2).
In view of the problems mentioned above with the current interconnect structure shown in FIG. 1, there is a need for providing an interconnect structure in which the adhesion between the upper level low-k dielectric and the underlying diffusion barrier capping dielectric is improved.