1. Technical Field
The present invention relates to a semiconductor device, and a method of manufacturing the same, and more particularly to a three-dimensional stacked semiconductor device having a through-silicon via, and a method of manufacturing the same.
2. Background Art
As an electronic device has a variety of functions and high performance in recent years, various developments have been made to realize a high-performance and highly integrated semiconductor device used for such an electronic device. Especially, a technique of three-dimensionally stacking semiconductor chips having a through-silicon via has been proposed, and this technique has been developed more actively. In the three-dimensional stacking technique, a through-silicon via penetrating through a semiconductor substrate and a bump connected to the through-silicon via are formed on one semiconductor chip, which is to be stacked, while a bump is also formed on the other semiconductor chip that is to be stacked. The chips are stacked by bonding both bumps.
FIG. 8A is a sectional view illustrating a stacked chip having a through-silicon via for a conventional three-dimensional stacking technique. FIGS. 8B, 9A, and 9B are sectional views illustrating a method of forming a stacked chip including a through-silicon via for a conventional three-dimensional stacking technique.
FIG. 8A illustrates a sectional view after a memory chip and a logic chip having a through-silicon via are stacked. The stacked semiconductor device includes memory chip 23, logic chip 24, through-silicon via 25, microbump 26, and filling material 27 between chips.
The sectional view illustrating a process of manufacturing the chip involved with the through-silicon via and its surrounding region is illustrated next.
As illustrated in FIG. 8B, elements (not illustrated) such as a transistor or a resistor are formed on semiconductor substrate 11, first interlayer insulating film 12 made of a silicon oxide film and including the elements and a wiring layer is formed, and then, contact plug 13 is formed in first interlayer insulating film 12.
Next, as illustrated in FIG. 9A, through-silicon via hole 14 penetrating through first interlayer insulating film 12 and semiconductor substrate 11 is formed by using a lithography technique and a dry etching technique. FIG. 9A illustrates that through-silicon via 14 does not reach a back surface of the semiconductor substrate. Thereafter, insulating film 15 such as a silicon oxide film is formed on first interlayer insulating film 12 along an inner wall face of through-silicon via hole 14, and then, a tantalum (Ta) film, for example, is formed as barrier film 16 that becomes a diffusion barrier of copper (Cu) that is a embedding material. Next, copper is filled in through-silicon via 14 as conductive film 17 for embedding the through-silicon via by using a plating technique, and then, an annealing process is carried out.
Next, as illustrated in FIG. 9B, conductive film 17 for embedding the through-silicon via, barrier film 16, and insulating film 15 that remain on first interlayer insulating film 12 on semiconductor substrate 11 are removed by using a CMP (Chemical Mechanical Polishing) technique, in order to form through-silicon via 18. A diameter of through-silicon via 18 generally ranges from several μm to a few dozen μm, and a depth thereof generally ranges from a few dozen μm to a few hundred μm. Finally, a bottom surface of semiconductor substrate 11 is etched or polished to expose the back surface of through-silicon via 18, and a bump connected to through-silicon via 18 is formed, although this process is not illustrated.
When the annealing process is carried out after through-silicon via 18 is formed, thick copper in through-silicon via 18 expands and contracts by the annealing process. In this case, stress is generated on semiconductor substrate 11 due to a difference in a thermal expansion coefficient between copper and silicon forming semiconductor substrate 11, so that a problem that the stress varies a performance of a transistor close to through-silicon via 18 might arise (e.g., see A. Mercha et al., Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias Induced stress on High-k/Metal Gate CMOS performance, IEDM, 2010).
Some proposals have been conventionally made in order to relax the stress caused by the through-silicon via. For example, there is a method (e.g., see Unexamined Japanese Patent Publication No. 11-163228) of forming a new layer between a metal in a through-silicon via and a semiconductor substrate for relaxing stress, as a method of relaxing stress to the semiconductor substrate due to the metal in the through-silicon via. There is another method (for example, see Unexamined Japanese Patent Publication No. 2008-085126) in which a metal in a through-silicon via is formed in two or more layers, and a heat treatment for relaxing stress is carried out after at least the first layer close to the semiconductor substrate is formed.