Processors used in smartphones, tablets, laptops, and other mobile devices enter sleep modes to reduce power consumption and extend the time between battery recharging. When a sleep mode is entered, the power supply to circuitry is temporarily disconnected from the power network by “gating off” the circuitry. When the sleep mode is exited, the power supply is restored to the circuitry by disabling the “gating off” and reconnecting the circuitry to the power network.
When the power supply is disconnected from storage circuitry such as static random access memory (SRAM), the data stored in the SRAM is typically not retained. Therefore, power gating is sometimes not applied to storage circuitry so that the data is retained through the sleep mode and can be read after the sleep mode is exited. In other situations, the data stored in an on-chip SRAM is saved to external memory prior to entering the sleep mode and the data is restored to the on-chip SRAM from the external memory after the sleep mode is exited. The save and restore approach has latency and power overhead which may cause that approach to be deemed unacceptable when the amount of time spent in the sleep mode is short. Thus, there is a need for addressing the issue of data retention and/or other issues associated with the prior art.