1. Field of the Invention
The present invention relates to non-volatile memory devices, and more particularly, to a non-volatile memory device in which a step height in a structure is reduced, which has a floating gate pattern/Oxide-Nitride-Oxide pattern (hereafter called as “ONO pattern”)/control gate pattern formed by burying the floating gate pattern and a tunnel insulating film below a semiconductor substrate surface, and an entire edge of the floating gate pattern is induced to make natural and extensive contact with the tunnel insulating film; and a method for fabricating the same.
2. Discussion of the Related Art
Recently, as demands increase sharply for non-volatile memories, such as flash memories, which can electrically program or erase data, geometries of structures of the non-volatile memory undergo many changes.
Referring to FIG. 1, a conventional non-volatile memory generally includes a tunnel insulating film 3 on an entire surface of a semiconductor substrate 1 having an active region defined by a device isolating film 2, a floating gate pattern 4 on the tunnel insulating film 3, an ONO pattern 5 on the floating gate pattern 4, and a control gate pattern 6 on the ONO pattern 5. In this instance, there are source/drain diffusion layers 7, and LDD (Lightly Doped Drain) regions on both sides of a structure composed of the floating gate pattern/the ONO pattern/the control gate pattern 4, 5, and 6.
As described before, in above configuration, a non-volatile memory device has a memory block having the structure in which the floating gate pattern/the ONO pattern/the control gate pattern 4, 5, and 6 are stacked in succession. However, different from the memory block, a logic block gate pattern (not shown) in the vicinity of the memory block of the same semiconductor substrate 1 has a different (and generally fewer) series of steps, typically omitting the floating gate/ONO patterns 4 and 5. That is, under the related art configuration, as far as no extra measures are taken, the structures on the semiconductor substrate 1 are generally involved in an unbalanced topology due to differences in the numbers of layers in the different gate patterns in the memory block and the logic block.
Of course, if no extra measures are taken under this situation, upper structures of the memory block, and the logic block may exhibit unstable operation due to the topology imbalance, which may lead to failure of the completed device in regular operations (e.g., such as erasure, programming, and reading).
Moreover, in the related art configuration, the floating gate pattern 4 has the tunnel insulating film 3 only on an underside of the floating gate pattern 4 itself, limiting an effective charging area of the device to only the underside area of the floating gate pattern 4 where the tunnel insulating film 3 is in substantial contact. If no extra measures are taken in this situation, the completed device may fail in regular operations.