1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a CMIS device that forms a silicon super-integrated circuit for performing advanced information processing and a method for manufacturing the CMIS device.
2. Related Art
“Silicon large-scale integrated circuit” is one of the fundamental technologies that will support the highly sophisticated information society in the future. To obtain a high-performance integrated circuit, it is necessary to develop high-performance CMIS devices that constitute such an integrated circuit. The performance of each device has been improved generally by the scaling rule. In recent years, however, it has been difficult to attain high performances by minute devices and to operate such devices, due to various physical limitations. One of the problems here is the increase in parasitic resistance in the source and drain regions that exists in series with the channel resistance. Particularly, the increase in contact resistance at the interface between the silicide and the silicon has become a serious problem. The contact resistance increases as the contact size becomes smaller with the reduction in device size. In the 32-nm technology generation and later, the contact resistance is considered to account for 50% of the parasitic resistance. To reduce the parasitic resistance, the active impurity in the diffusion layer that serves as the source and drain needs to have high concentration, and the Schottky barrier height needs to be smaller.
However, impurities cannot be made active beyond the solid solubility limit. In a case where a CMIS device is to be produced, the Schottky barrier height cannot be made smaller for both an n-type MISFET and a p-type MISFET at the same time. Therefore, two different types of contact materials are required for the n-type MISFET and the p-type MISFET. This leads to a more complicated manufacturing process.
Attempts have been made to reduce the Schottky barrier height by forming the source and drain with a semiconductor having a narrow band gap, such as SiGe or Ge (see JJAP 28(1989) L544-L546, H. Kanaya et al., for example). Such attempts have reduced the barrier height with respect to holes, but have not reduced the barrier height with respect to electrons. As a result, there has been a demand for a technique for reducing the contact resistance for both an n-type MISFET and a p-type MISFET at the same time through a simple manufacturing process.
Meanwhile, a technique for reducing the Schottky barrier height by segregating a nonmetal element to be a dopant for silicon at the interface has been known. In a case of a CMISFET, however, it is necessary to segregate different elements for an n-type MISFET and a p-type MISFET. The difference in silicide formation speed during the segregation makes integration difficult (see JP-A 2005-101588 (KOKAI), for example).
As described above, the electric resistance (contact resistance) at the interface between the diffusion layer to be the source and drain of each MISFET and the silicide layer formed on the diffusion layer needs to be lowered so as to operate the device at a high speed. Attempts have been made to reduce the interfacial resistance (or the Schottky barrier height) by forming the diffusion layer with a semiconductor having a narrow band gap, but have failed to reduce the contact resistance of a MISFET, especially the contact resistance of the source and drain of an n-type MISFET.