1. Field of the Invention
The present invention relates to a high frequency flip chip package process of a polymer substrate and a structure thereof, and more particularly to a one-layer high frequency flip chip package for overcoming the shortcomings of a conventional two-layer high frequency flip chip package process by enhancing the issues such as the return loss, high cost, manufacturing yield rate and reliability of the package structure.
2. Background of the Invention
As the semiconductor industry advances rapidly, present electronic products tend to be designed with a small size, a light weight and a variety of functions, and package processes tend to be developed with a larger number of inputs/outputs and a smaller interval, so as to provide electronic components with a more stable signal transmission channel and a better heat dissipating path, while protecting the internal electronic components from being affected by external environments. Regardless of traditional electronic products, light emitting diodes (LEDs), mobile phones or other high-frequency wireless communication products, a package process plays an important role.
At present, the package process traditionally used in the semiconductor industry is a wire bonding process. As an operating frequency becomes increasingly higher, a lager parasitic effect results, and thus the wire bonding package has faced its bottleneck, and the two-layer high frequency flip chip package process is considered as a package process with the most potential.
With reference to FIG. 1 for a structure of the so-called two-layer high frequency flip package, a bump 24 is provided for connecting a chip 25 with a ceramic substrate 23 (which is the first-layer package), and then a ball grid array (BGA) 22 is used for connecting the ceramic substrate 23 with a polymer substrate 21 (which is the second-layer package), so as to complete a two-layer high frequency flip package structure 2.
However, the conventional two-layer high frequency flip chip package process and its structure 2 have the following drawbacks:
1. The conventional two-layer high frequency flip chip package process goes through two-layer package, and the high-frequency characteristics of the manufactured high frequency flip chip package structure 2 bring out additional insertion loss and return loss.
2. The conventional high frequency flip chip package process uses the two-layer package, and thus the package incurs a high cost and a complicated manufacturing process.
3. Since the polymer substrate 21 of the high frequency flip package structure 2 comes with a larger coefficient of thermal expansion (CTE), therefore there is a reliability issue.
4. The manufacturing process of the ceramic substrate 23 in the high frequency flip package structure 2 still has the issues of a low yield rate and a high cost.
In summation of the aforementioned drawbacks, the conventional two-layer high frequency flip chip package process still has many issues that require further improvements.