As the computer industry evolves, demands for memory have out-paced the technology of available memory devices. One of these demands is high speed memory compatibility. Thus, in a computer system, such as a personal computer or other computing system, memory subsystems have become an influential component toward the overall performance of the system. Emphasis is now on refining and improving memory devices that provide affordable, zero-wait-state operations.
Generally, volatile memories are either DRAM or static RAM (“SRAM”). Each SRAM cell includes plural transistors. Typically the data stored in a SRAM cell is stored by the state of a flip-flop formed by some of the transistors. As long as power is supplied, the flip-flop keeps its data: it does not need refreshing. In a DRAM cell, on the other hand, there typically is one transistor, and data is stored in the form of charge on a capacitor that the transistor accesses. The capacitor dissipates its charge and needs to be refreshed.
These two types of volatile memories have respective advantages and disadvantages. With respect to memory speed, the SRAM is faster than the DRAM due, partially at least, to the nature of the cells. The disadvantage, however, is that because there are more transistors, the SRAM memory is less dense than a DRAM of the same physical size. For instance, static RAMs traditionally have a maximum of one-fourth the number of cells of a DRAM which uses the same technology.
While the DRAM has the advantage of smaller cells and thus higher cell density (and lower cost per bit), one disadvantage is that the DRAM must refresh its memory cells whereas the SRAM does not. While the DRAM refreshes and precharges, access to the memory cells is prohibited. This creates an increase in access time, which drawback the static RAM does not suffer.
However, the speed and functionality of current DRAMS are often emphasized less than memory size (storage capacity) and cost. This is evidenced by the fact that DRAM storage capacity density has increased at a rate an order of magnitude greater than its speed. While there has been some improvement in access time, systems using DRAMs generally have had to achieve their speed elsewhere.
In order to increase system speed, cache memory techniques have recently been applied to DRAM main memory. These approaches have generally been implemented on a circuit board level. That is, a cache memory is frequently a high-speed buffer interposed on the circuit board between the processor chip and the main memory chip. While some efforts have been made by others to integrate a cache with DRAM, we first address the board level approach.
FIG. 1 indicates a prior art configuration (board-level) wherein a processor chip 10 is configured with a cache controller 12 and a cache memory 14. The main purpose of the cache memory is to maintain frequently accessed data for high speed system access. Cache memory 14 (sometimes called “secondary cache static RAM”) is loaded via a multiplexer 16 from DRAMs 20, 22, 24 and 26. Subsequently, data is accessed at high speeds if stored in cache memory 14. If not, DRAMs 20, 22, 24 and/or 26 load the sought data into cache memory 14. As seen in FIG. 1, cache memory 14 may comprise a SRAM, which is generally faster than DRAMS 20-26.
Various approaches have been proposed for cache memory implementation. These approaches include controlling external cache memory by a controller, such as cache memory 14 and cache controller 12 in FIG. 1, or discrete proprietary logic. Notwithstanding its benefits, cache memory techniques complicate another major problem that exists in system design. Memory components and microprocessors are typically manufactured by different companies. This requires the system designer to effectively bridge these elements, using such devices as the cache controller 12 and the multiplexer 16 of FIG. 1. These bridge components are usually produced by other companies. The different pin configurations and timing requirements of these components makes interfacing them with other devices difficult. Adding a cache memory that is manufactured by yet another company creates further design problems, especially since there is no standard for cache implementation.
Exacerbating the system design problems is the disadvantage that the use of external cache memory (such as cache memory 14) compromises the main storage access speed. There are mainly two reasons for this compromise. First, and most significant, the main storage access is withheld until a “cache miss” is realized. The penalty associated with this miss can represent up to two wait states for a 50 MHz system. This is in addition to the time required for a main memory access. Second, the prioritized treatment of physical routing and buffers afforded the external cache is usually at the expense of the main memory data and address access path. As illustrated in FIG. 1, data from DRAMs 20, 22, 24 and 26 can be accessed only through cache memory 14. The actual delay may be small, but adds up quickly.
A third problem associated with separate cache and main memory is that the time for loading the cache memory from the main memory (“cache fill”) is dependent on the number of inputs to the cache memory from the main memory. Since the number of inputs to the cache memory from the main memory is usually substantially less than the number of bits that the cache memory contains, the cache fill requires many clock cycles. This compromises the speed of the system.
A memory architecture that has been used or suggested for video RAMs (“VRAMs”) is to integrate serial registers with a main memory. VRAMs are specific to video graphics applications. A VRAM may comprise a DRAM with high speed serial registers allowing an additional access port for a line of digital video data. The extra memory used here is known as a SAM (serially addressed memory), which is loaded using transfer cycles. The SAM's data is output by using a serial clock. Hence, access to the registers is serial, not random. Also, there is continuous access to the DRAM so refresh is not an issue as it is in other DRAM applications.
Another implementation that is expected to come to market in 1992 of on-chip cache memory will use a separate cache and cache controller sub-system on the chip. It uses full cache controllers and cache memory implemented in the same way as it would be if external to the chip, i.e. a system approach. This approach is rather complicated and requires a substantial increase in die size. Further, the loading time of the cache memory from the main memory is constrained by the use of input/output cache access ports that are substantially fewer in number than the number of cache memory cells. A cache fill in such a manner takes many clock cycles, whereby system access speed suffers. Such an approach is, in the inventors' views, somewhat cumbersome and less efficient than the present invention.
Still another problem in system design arises when the system has both (a) interleaved memory devices together with (b) external cache memory. Interleaving assigns successive memory locations to physically different memory devices, thereby increasing data access speed. Such interleaving is done for high-speed system access such as burst modes. The added circuitry for cache control and main memory multiplexing usually required by external cache memory creates design problems for effective interleaved memory devices.
Another problem with the prior art arises when memory capacity is to increase. Adding more memory would involve adding more external SRAM cache memory and more cache control logic. For example, doubling the memory size in FIG. 1 requires not only more DRAM devices required, but also another multiplexer and possibly another cache controller. This would obviously add to system power consumption, detract from system reliability, decrease system density, add manufacturing costs and complicate system design.
Another problem concerns the cost of manufacturing a system with an acceptable cache hit probability. When using external cache memory, manufacturers allocate a certain amount of board area for the main memory. A smaller area is allocated for the external cache. Usually, it is difficult to increase the main memory and the external cache memory while maintaining an acceptable cache hit probability. This limitation arises from the dedication of more board area for the main memory than for external cache.
A further problem with system speed is the need for circuitry external to the main memory to write “post” data. Post data refers to data latched in a device until it is needed. This is done because the timing requirement of the component needing the data does not synchronize with the component or system latching the data. This circuitry usually causes timing delays for the component or system latching the data.
As stated supra, access to the DRAM memory cells during a precharge and refresh cycle was prohibited in the prior art. Some prior art approaches have tried to hide the refresh in order to allow access to DRAM data. One DRAM arrangement maintained the data output during a refresh cycle. The drawback of this arrangement was that only the last read data was available during the refresh. No new data read cycle could be executed during the refresh cycle.
A pseudo-static RAM is another arrangement that attempted to hide the refresh cycle. The device was capable of executing internal refresh cycles. However, any attempted data access during the refresh cycle would extend the data access time, in a worst case scenario, by a cycle time (refresh cycle time plus read access time). This arrangement did not allow true simultaneous access and refresh, but used a time division multiplexing scheme to hide the refresh cycle.
Another way to hide the refresh cycle is to interleave the RAM memory on the chip. When a RAM memory block with even addresses is accessed, the odd memory block is refreshed and vice-versa. This type of implementation requires more timing control restraints which translate to a penalty in access time.
Another type of problem arises when considering the type of access modes to the main memory. One type of access is called page mode, in which several column addresses are synchronously applied to an array after a row address has been received by the memory. The output data access time will be measured from the timing clock edge (where the column address is valid) to the appearance of the data at the output.
Another type of access mode is called static column mode wherein the column addresses are input asynchronously. Access can occur in these modes only when RAS is active (low), and a prolonged time may be required in the prior art.
When manufacturing chips that support these access types, only one of these access types can be implemented into the device. Usually, one of the last steps in the making of the memory chip will determine if it will support either type of access. Thus, memory chips made this way do not offer both access modes. This induces an added expense in that the manufacturer must use two different processes to manufacture the two types of chips.
To overcome these problems, small modifications added to a component, such as a DRAM, may yield an increase in system performance and eliminate the need for any bridging components. To successfully integrate the modification with the component, however, its benefit must be relatively great or require a small amount of die space. For example, DRAM yields must be kept above 50% to be considered producible. Yields can be directly correlated to die size. Therefore, any modifications to a DRAM must take into account any die size changes.
In overcoming these problems, new DRAM designs have become significant. The greatest disadvantage to caching within DRAMs has been that DRAMs are too slow. The present invention in one of its aspects seeks to change the architecture of the DRAM to take full advantage of high caching speed that may now be obtainable.
One way to meet this challenge is to integrate the functions of the main storage and cache. Embedding the cache memory within localized groups of DRAM cells would take advantage of the chip's layout. This placement reduces the amount of wire (conductive leads) used in the chip which in turn shortens data access times and reduces die size.
U.S. Pat. No. 5,025,421 to Cho is entitled “Single Port Dual RAM.” It discloses a cache with typical DRAM bit lines connected to typical SRAM bit lines through pass gates. Reading and writing the SRAM and DRAM arrays occurs via a single port, which requires that input/output busses communicate with the DRAM bit lines by transmitting data through the SRAM bit lines. Using SRAM bit lines to access the DRAM array precludes any access other than refresh to the DRAM array while the SRAM array is being accessed, and conversely precludes access to the SRAM array while the DRAM array is being accessed, unless the data in the SRAM is the same data as in the currently accessed DRAM row. This is a functional constraint that is disadvantageous.
Moreover, the SRAM cells of Cho FIG. 1 are full SRAM cells, although his FIG. 4 may disclose using only a single latch (FF11) rather than an entire SRAM cell. However, the use of a single port with a simple latch raises a severe problem. Such an architecture lacks the ability to write data into the DRAM without corrupting the data in the SRAM latch. Hence, the FIG. 4 configuration is clearly interior to Cho's FIG. 1 configuration.
Another effort is revealed by U.S. Pat. No. 4,926,385 to Fujishima, Hidaka, et al., assigned to Mitsubishi, entitled, “Semiconductor Memory Device With Cache Memory Addressable By Block Within Each Column.” There are other patents along these lines by Fujishima and/or Hidaka. This one uses a row register like Cho FIG. 4. Two ports are used, but two decoders are called for. While this overcomes several of the problems of Cho, it requires a good deal more space consumed by the second column decoder and a second set of input/output switch circuitry. (Subsequent Fujishima/Hidaka patents have eliminated the second access port and second decoder and have reverted to the Cho FIG. 1 approach, despite its disadvantages.) Nevertheless, in this patent, the “tag” and data coherency control circuitry for the cache is external to the chip and is to be implemented by the customer as part of the system design. The “tag” refers to information about what is in the cache at any given moment. A “hit” or “miss” indication is required to be generated in the system, external to the integrated circuit memory, and supplied to the chip. This leads to a complicated and slower system.
Other Fujishima, Hidaka, et al. U.S. patents include U.S. Pat. Nos. 5,111,386; 5,179,687; and 5,226,139.
Arimoto U.S. Pat. No. 5,226,009 is entitled, “Semiconductor memory device supporting cache and method of driving the same.” This detects whether a hit or miss occurs by using a CAM cell array. The basic arrangement is like the approach of Cho FIG. 1 but modified to collect DRAM data from an “interface driver,” which is a secondary DRAM sense amplifier, rather than from the primary DRAM sense amplifiers. This architecture still accesses the DRAM bit lines via the SRAM bit lines and is plagued with the single port problem. Circuitry is provided to preserve coherency between the DRAM and the SRAM. A set of tag registers is discussed with respect to a system-level (off-chip) implementation in a prior art drawing. Arimoto implements his on-chip cache tag circuitry using a content addressable memory array. That approach allows N-way mapping, which means that a group of memory devices in the cache can be assigned to any row in any of N subarrays. For example, if an architecture is “4-way associative,” this means that there are four SRAM blocks, any of which can be written to by a DRAM. This method results in a large, expensive, and slow implementation of mapping circuitry. Using a CAM array for tag control has an advantage of allowing N-way association. However, the advantage of N-way association seems not to outweigh the disadvantage of the large and slow CAM array to support the N-way SRAM array.
Dye U.S. Pat. No. 5,184,320 is for a “Cached random access memory device and system” and includes on-chip cache control. The details of the actual circuitry are not disclosed, however. This patent also is directed to N-way association and considerable complication is added to support this.
Another piece of background art is Matick et al. U.S. Pat. No. 4,577,293 for a “Distributed on-chip cache.” It has 2-way associative cache implemented using a distributed (on-pitch) set of master-slave row register pairs. Full flexibility of access is provided by dual ports that are not only to the array but also to the chip itself. The two ports are totally independent, each having pins for full address input as well as data input/output. The cache control is on-chip.
Thus it should be appreciated that the art has heretofore often directed efforts in achieving N-way association. While this has led to complications, the art has thought that N-way association is the approach to follow.
The present invention, according to one of its aspects, rejects this current thinking and instead provides a streamlined architecture that not only includes on-chip cache control, but also operates so fast that the loss of N-way association is not a concern.
Therefore, it is a general object of this invention to overcome the above-listed problems.
Another object of the present invention is to isolate the cache memory data access operation from undesirable DRAM timing overhead operations, such as refresh and precharge.
A further object of the present invention is to eliminate the need for a external static RAM cache memory in high speed systems.
Still another object of the present invention is to insure cache/main memory data coherency.
Another object of this invention is to insure such data coherency in a fashion which minimizes overhead, so as to reduce any negative impact such circuitry might have on the random data access rate.