1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which employs a delayed write (also called late write) technique.
2. Description of the Related Art
Recently, the performance of components used to construct computers and other information processing apparatuses has improved greatly and, with these improvements, there has developed a need to increase the operating speed and data transfer rate of semiconductor memory devices such as synchronous dynamic random access memories (SDRAMs). To improve the data transfer rate, it is essential to increase the efficiency of bus utilization, and a technique called delayed write is proposed as one method of achieving this.
However, the semiconductor memory device employing the delayed write technique offers the effect of increasing the data transfer rate, but requires the provision of a data register for holding write data and an address register for holding the write data address.
In recent semiconductor memory devices, with increasing data transfer rate, the data bus width has been increasing and this, coupled with the development of DDR (Double Data Rate) technology, causes the amount of data that can be written in a single write operation to become larger than ever before. Accordingly, the provision of registers, required when employing the above-described delayed write technique, not only leads to increased chip area but also becomes a factor that increases the cost.
The above problem is not limited to SDRAMs or DDR DRAMs, but is also an issue with various other semiconductor memory devices such as direct Rambus DRAMs and non-DRAM devices such as SRAMs (Static Random Access Memories).
The prior art and its associated problem will be described in detail later with reference to accompanying drawings.
An object of the present invention is to provide a semiconductor memory device in which data transfer rate is increased without having to provide a register for holding write data.
According to the present invention, there is provided a semiconductor memory device, having a read data line and a write data line, comprising a data writing circuit and a data holding circuit included in the data writing circuit, the data holding circuit holding write data on the write data line until inputting the next write command.
The semiconductor memory device may further comprise a sense amplifier/write switch, including a sense amplifier section, connected to the read data line, for reading data from the memory cell, and a write switch section, connected to the write data line, for writing data into the memory cell. The sense amplifier/write switch may be provided within a memory core, and the read data line and the write data line may be separated from each other within the memory core. The semiconductor memory device may further comprises a write amplifier driving the write data line, the write amplifier outputting write data on the write data line and holding the write data.
The semiconductor memory device may further comprise a mask information holding section for receiving mask information indicating enable/disable of the write data, and for holding the mask information therein. The mask information may be input together with the write data. The mask information holding section may be provided within a write amplifier which drives the write data line. The semiconductor memory device may further comprise an open condition control section for controlling the write data line to an open condition when disabling the write data.
The write data line may be constructed as complementary signal lines, and the semiconductor memory device may include an equal potential control section for controlling the complementary signal lines to equal potentials when disabling the write data. The mask information held in the mask information holding section may be supplied to the sense amplifier/write switch, and a write control to the memory cell may be carried out based on the mask information. The mask information held in the mask information holding section may be supplied to a decoder provided within the memory core, and a write control to the memory cell may be carried out based on the mask information.
The decoder, in which the write control is carried out based on the mask information, may be a column decoder. A write amplifier, which outputs write data on the write data line and holds the write data, may control the enable/disable of the write data held in the write amplifier, in accordance with the mask information and a data disable signal.
The mask information holding section may disable the write data held in the write amplifier, in accordance with the data disable signal, when the write data held on the write data line is written to the memory cell. The semiconductor memory device may be a dynamic memory, and the data disable signal may be issued in connection with a refresh operation of the dynamic memory. The data may be write data that is input in accordance with a write command; the data holding circuit may hold first write data that is input in accordance with a first write command; and the data writing circuit may write the first write data into the memory cell when a second write command to be input following the first write command is input.
Further, according to the present invention, there is provided a semiconductor memory device having a read data line and a write data line, comprising an address information holding circuit holding address information that is input in relation to write data, and wherein, when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.
The semiconductor memory device may further comprise a write amplifier outputting write data on the write data line, and holding the write data; an address comparator T comparing received address information with the address information held in the address information holding circuit; and a data selector selecting the data output from the memory cell or the data output from the write amplifier, based on the result of the comparison supplied from the address comparator. The data selector may select the data output from the memory cell or the data output from the write amplifier, based on mask information indicating enable/disable of the write data.
The semiconductor memory device may further comprise a write amplifier outputting write data on the write data line, and holding the write data; and an address comparator comparing received address information with the address information held in the address information holding circuit, wherein based on the result of the comparison supplied from the address comparator, the data held on the write data line may be written into the memory cell. Based on the result of the comparison supplied from the address comparator, the data held on the write data line may be written into the memory cell, while at the same time, the data is transferred onto the read data line.