A semiconductor device, such as an integrated circuit chip, is produced by a sequence of hundreds of process steps, many of which require a lithographic mask through which a design pattern is imprinted on a photoresist layer. So-called hotspots of a design pattern are the areas which are likely to be printed incorrectly due, for example, to certain geometrical parameters of the design and their interaction with optical phenomena taking place during the exposure of the mask. Many of the hotspots can be predicted and solved by design software, such as litho pattern simulation software and OPC (Optical Proximity Correction) software. However, it is not possible to predict all possible defects, which makes it necessary to apply actual defect detection on a printed wafer.
An important factor in the appearance of defects on a printed wafer is the quality of focus of the lithographic tool used in the device manufacturing process. This quality of focus is expressed as a tolerance with respect to perfect focus (i.e. zero de-focus), expressed, for example, as a range of de-focus values on either side of the zero de-focus state. For example, a lithographic tool may have a focus tolerance of [−40 nm, +40 nm], meaning that the focus may unpredictably vary within this range due to inaccuracies in the tool, wear of the tool, environmental changes, etc.
Many hotspots identified on a mask design defining a given pattern do not appear as actual defects in the printed pattern unless the defocus of the lithography tool exceeds a given limit value. For this reason, it is customary to make a ranking of defects based on their sensitivity to the degree of de-focus. Defects appearing at the lowest de-focus values are ranked highest. These defects are likely to occur in a production process where the tolerance of the focus is higher than the focus error at which the defects occur. For example, a defect occurring at +10 nm de-focus is likely to occur when using a tool with the above-described tolerance of [−40 nm, +40 nm]. Hence these hotspots are most critical and most in need of correction.
In order to make the ranking, the so-called modulated focus wafer technique may be used, in which a pattern is printed multiple times on a wafer, on multiple separate semiconductor die areas of the wafer, with the focus changing in steps of, for example, +/−10 nm, from zero de-focus to gradually more out-of-focus values. Each printed die area is then inspected, and where repeating defects are detected, i.e., defects appearing in successively more de-focused prints, these hotspots are ranked in the above-described way. One example of this approach is shown in WO/2006/063268.
As the dimensions of printed features decreases with the evolution towards sub 32 nm nodes in semiconductor processing, the criticality of the above-described design and inspection processes becomes ever greater. One problem is that the modulated focus wafer technique assumes that a uniform focus applies to the totality of the printed surface of a particular die, but fails to take into account focus variations within each die. When these variations approach values that are in the same order of magnitude as the incremental steps used in the test procedure, ranking errors are likely to occur.