Communication systems are designed to transfer information between two devices over a medium in the presence of disturbing influences. Intersymbol interference (ISI) is one well-known disturbing influence in which transmitted symbols become elongated and interfere with adjacently transmitted symbols. This spreading or “smearing” of symbols is generally caused by bandwidth limitation and interference associated with all communication mediums and/or multipath propagation within those mediums. Because ISI has the same effect as noise, communication is made less reliable.
One of the most basic solutions for mitigating the effects of ISI is slowing down the speed at which symbols are transmitted over a medium. More specifically, the transmission speed can be slowed down such that a symbol is only transmitted after allowing previously transmitted symbol pulses to dissipate. The time it takes for a symbol pulse to dissipate is called delay spread, whereas the original time of the symbol pulse (including any time before the next symbol pulse is transmitted) is called the symbol time. No ISI will occur if the delay spread is less than or equal to the symbol time.
Although slowing down the bit rate can eliminate the effects of ISI, it is generally an unacceptable solution for many of today's communication applications. In fact, many of today's communication applications require speeds in the multi-gigabit per second range. At such high speeds, ISI can completely overwhelm a signal transmitted over a few inches of printed circuit board trace, a few feet of copper cable, or a few tens of meters of multimode optical fiber. To further compound the problem, ISI can change over time with temperature, positioning, and the impedance of the communication medium, for example.
Therefore, an adaptive filtering process, referred to as equalization, is often used to flatten the frequency response of a communication medium and mitigate the effects of ISI. One common filtering architecture used to flatten the frequency response of a communication medium is the Decision Feedback Equalization (DFE) architecture. The performance of the DFE architecture is generally limited by non-idealities such as frequency response, noise, nonlinearity, and mismatch associated with its data path and the data it operates on. As a result, DFE architectures are conventionally implemented with several different circuit elements to compensate for non-idealities, such as mismatch between devices used to implement the DFE. However, these compensation circuit elements increase the load of the data path and, as a result, decrease the speed at which the DFE architecture can operate. Any decrease in speed limits the usefulness of the DFE architecture in many of today's high-speed applications.
Therefore, what is needed is a DFE architecture that can compensate for one or more non-idealities, such as mismatch between devices used to implement the DFE, while limiting additional loading.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.