Internal to many network devices, e.g., switches and routers, there is often a processor responsible for processing packets used in the network device's global operation. These packets may arrive from across the network to any external network port on the network device, e.g., to an external port provided by a network chip installed on the network device. A given network device may have multiple network chips installed thereon with each network chip having multiple external ports. The network chips may be application specific integrated circuits (ASICs). The above described packets received to any of these external ports should be routed to the above mentioned processor in an efficient manner. Additionally, the packets from this processor should be capable of being sent out any appropriate external port or to local processing on any network chip.
The multiple network chips on a network device may be interconnected to one another via a high speed interconnect, e.g., a crossbar or internal switching fabric chip. In the past, one approach to providing packets received at the external network ports to a processor on the network device, i.e., the processor responsible for processing the packets used in the network device's global operation, was to put the processor access in a central place such as in the switching fabric. This approach introduces complex port forwarding logic into an otherwise straightforward crossbar switching fabric. Additionally this approach introduces two sets of code to keep in step with one another. Moreover, the approach is not available in a small network chip configuration which may not use a switching fabric chip.
Another approach to providing packets received at the external network ports to the processor responsible for processing those packets has been to wire up a special management blade, e.g., processor and memory chip dedicated to handling the exchange of those packets. In this approach the network device is hard coded so that all of this particular processor traffic goes through the management blade. The main disadvantage to this approach is that if the management blade fails or needs to be removed, the entire network device is down.
Yet another approach has been to wire up simultaneous connections from each network chip to the particular processor responsible for processing these packets. The disadvantage to this approach is cost. That is, the particular processor will have as many media access control-physical layer (MAC-PHY) ports as there are network chips on the network device which does not scale particularly well. Moreover, this approach becomes more cumbersome when the network device endeavors to provide redundancy among the processors responsible for processing the packets in the event a given processor is busy or down.