Junction field effect transistors (JFETs) are majority carrier devices that conduct current through a channel that is controlled by the application of a voltage to a p-n junction. JFETs may be constructed as p-channel or n-channel and may be operated as enhancement mode devices or depletion mode devices.
The most common JFET type is the depletion mode type. The depletion mode device is a normally “on” device that is turned off by reverse biasing the p-n junction so that pinch-off occurs in the conduction channel. P-channel depletion mode devices are turned off by the application of a positive voltage between the gate and source (positive Vgs), whereas n-channel depletion mode devices are turned off by the application of a negative voltage between the gate and source (negative Vgs). Since the junction of a depletion mode JFET is reverse biased in normal operation, the input voltage can be relatively high. Devices are available with input voltages with a magnitude greater than 100 volts.
Enhancement mode, or normally “off” JFETs are characterized by a channel that is sufficiently narrow such that a depletion region at zero applied voltage extends across the entire width of the channel. Application of a forward bias reduces the width of the depletion region in the channel, thereby creating a conduction path in the channel. P-channel enhancement mode JFETs are turned on by the application of a negative Vgs, and n-channel enhancement mode JFETs are turned on by the application of a positive Vgs. The input voltage of an enhancement mode JFET is limited by the forward breakdown voltage of the p-n junction.
Historically, JFETs have been used for analog switches, radio frequency devices, current regulators and high input impedance amplifiers, while logic circuits such as microprocessors have been the domain of metal oxide semiconductor field effect transistors (MOSFETs) as exemplified by complementary metal oxide semiconductor (CMOS) technology.
Traditionally, JFETs have been used as discrete devices or as input stages on integrated circuits such as operational amplifiers. However, as circuit complexity, operating frequency, and power management requirements have increased for CMOS devices such as microprocessors, it has become desirable to integrate power management and conditioning functions on the same die with the logic. JFETs are candidates for performing these functions
A transistor structure that is integrated on a logic circuit for the purpose of power management and conditioning will be faced with a requirement for high frequency operation and low power consumption. For field effect transistors (FETs), parasitic capacitances between the gate and source (Cgs) and gate and drain (Cgd) are significant factors affecting performance in this regard. In general, a low gate capacitance is desirable for transistors used in both analog and digital circuits. A low capacitance provides faster switching, higher frequency response and lower current and power requirements.
Although the characteristics of JFETs qualify them as candidates for integration with high speed logic circuits having sophisticated power management requirements, the conventional JFET device structures and processes are not optimized for such integration. The structures and processes that have heretofore been used to produce discrete devices or analog integrated circuits were not designed for integration with CMOS structures and processes.
Thus, a need exists for a JFET with minimal parasitic capacitances Cgs and Cgd. There is also a need for method for producing an optimal JFET structure that is compatible with the process flow used for logic integrated circuits.