Various interconnection systems provide for communication of data and some also provide for power delivery The Universal Serial Bus Type-C specification provides for communication and power delivery using a single-ended receiver circuit to communicate data. This data is provided with an embedded clock signal, which operates at 600 kilohertz (kHz). However, this communication suffers from jitter, frequency drift and ground shifting in the data. As such, it is difficult for a receiver to recover the clock and retime the received data, since a general-purpose receiver is focused on instruction speed, low power and small area, rather than providing the USB Type-C reference clock. Thus, a conventional phase locked loop (PLL) or delay locked loop (DLL)-based clock and data recovery circuit (CDR) cannot work properly without the reference clock. In addition, a conventional CDR does not have fast phase track capability and is affected by fast events, for example, cycle-to-cycle jitter, fast frequency drift and ground shifting.