Logic designers manually generate test code that exercise critical timing paths of the electronic hardware, for speed characterization of the electronic hardware. The test code is generally handwritten based on a gate-level static timing report associated with the electronic hardware. The logic designer attempts to pick instructions, and, if necessary, operands that they believe will exercise the portions of the electronic hardware with critical timing paths. Thereafter, the test code is executed on a hardware simulation tool to verify the timing path was exercised. This trial-by-error method requires numerous iterations to identify a single critical timing path, and requires extensive visual inspection to determine if the critical timing path is exercised.
Accordingly, the inventors herein have recognized a need for automatically generating timing path software monitors that can identify test cases that exercise critical timing paths of electronic hardware.