The present invention relates to a semiconductor device such as a flash memory capable of setting a threshold voltage corresponding to multi-value information of 2 bits or more to one electrically rewritable non-volatile memory cell, and further a data processing system using the semiconductor device and a memory card.
An electrically rewritable or programmable flash memory has memory cell transistors each having, for example, a floating gate (flotage gate), a control gate, a source and a drain. When electrons are injected into the floating gate of the memory cell transistor, the memory cell transistor rises in threshold voltage. On the other hand, when the electrons are extracted or drawn from the floating gate, the threshold voltage thereof is reduced. The memory cell transistor serves so as to store information corresponding to the magnitude or high and low levels of a threshold voltage relative to a word line voltage (voltage applied to control gate) for reading data. Although not restricted in particular, the state in which the threshold voltage of the memory cell transistor is low, is called an xe2x80x9cerase statexe2x80x9d, and the state in which the threshold voltage thereof is high, is called a xe2x80x9cwrite statexe2x80x9d.
If one state is capable of being selected from, for example, an erase state and first through third write states respectively different in threshold voltage from the erase state, then four-value information can be stored in one memory cell transistor.
The present applicant has previously filed a multi-valued flash memory wherein four-value information can be stored in one nonvolatile memory cell transistor (see Unexamined Patent Publication No. Sho 11(1999)-345494 (U.S. Pat. No. 6,078,519) and Unexamined Patent Publication No. Sho 11(1999)-232886 (U.S. Pat. No. 6,046,936)). According to this, assuming that an erase operation is performed before a write operation, the storage of four-value information can be performed by determining whether all the first through third write states are unselected or any write state is selected. A write operation therefor needs write control information for determining whether write voltage applying operations for individually obtaining the first through third write states should be selected. In order to hold such write control information, a sense latch connected to each bit line is used.
The sense latch comprises a static latch, for example. One ends of bit lines are respectively connected to a pair of differential input/output terminals of the sense latch. Data latches are connected to the other ends of the bit lines. The drain of the memory cell transistor is connected to its corresponding bit line. When writing is supposed in units of word lines to which control gates are commonly connected, a distinction between selection and non-selection of the application of a write voltage to each memory cell can be made by an increase or decrease in drain voltage. In this case, the sense latch latches therein data corresponding to the selection and unselection of the application of the write voltage. This latched data corresponds to the write control information. When, for example, the sense latch latches a logic value xe2x80x9c0xe2x80x9d therein, the corresponding bit line is brought to a ground voltage and hence the write voltage is applied to the corresponding memory cell. When the sense latch latches a logic value xe2x80x9c1xe2x80x9d therein, the bit line is brought to a source voltage so that the application of a write voltage to the corresponding memory cell is inhibited.
In order to produce such write control information, 2 bits of write data are latched in the corresponding pair of data latches every memory cells intended for writing in the preceding application. The held 2-bit write data indicate whether the corresponding one memory cell is allowed to hold an erase state or caused to select any of the first through third write states. Whether it means any state, is analyzed by a logic combining circuit on its corresponding bit line. This analyzing process is carried out in accordance with the application of a write voltage to the first through third write states and a verify process. Further, write control information for allowing the sense latch to select the write-voltage application in required timing is set (data latch processing). When the write-voltage application is selected according to the write control information latched in the sense latch, the write voltage is stepwise applied in parts plural times, and a verify operation for determining whether it has reached an intended threshold voltage, is carried out for each write-voltage application. In the verify operation, data reading is effected on each memory cell intended for writing at a word line select level corresponding to an intended threshold voltage. Until the intended threshold voltage is reached, the corresponding bit line is discharged for each read operation. When the intended threshold voltage is reached, the bit line is maintained at a precharge level upon the read operation. This state inversion inverts the data latched in the sense latch and subsequently to it, the application of the write voltage is regarded as unselected.
However, in order to set the write control information to the sense latch, operations such as precharge, discharge and internal transfer, etc. must be repeatedly effected on the write data of the latches by using the logic combining circuits on the bit line to analyze the write data. It has been clarified that time is required to no small extent for this purpose and a write operating time becomes long.
Therefore, the present inventors have discussed means that makes it unnecessary to generate write control information by the logic combining circuits on the bit line. Even in such a case, however, data latched in a sense latch is subjected to logic-value inversion according to the completion of writing upon a write verify operation. In short, write control information for the sense latch changes as a write/write verify operation proceeds. Thus, when the data initially latched in the sense latch is required to check whether an upper limit of a threshold voltage distribution subsequent to the formation of a memory threshold distribution with the formation of a write voltage for each memory cell is distinguishable from a threshold voltage distribution placed thereabove, it is necessary to take into consideration even the restoration of the initially latched data. This situation is similar even in the case where a write operation is retried in response to the generation of write abnormality and in the case of a recovery read for returning write data sent from outside to a host system in response to write abnormality.
An object of the present invention is to provide a semiconductor device capable of shortening a processing time required to set write control information to a sense latch to thereby achieve an improvement in the efficiency of a write operation.
Another object of the present invention is to provide a semiconductor device capable of, even if initially-latched write control information is lost in the course of a write/write verify operation, restoring it and assuring an upper-limit check for a threshold voltage distribution, write retry and recovery read.
A further object of the present invention is to provide a data processing system capable of improving the efficiency of data processing with access to each nonvolatile memory cell.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows
 less than  less than Input Decode of Write Data greater than  greater than 
A semiconductor device such as a multi-value flash memory, which allows one electrically erasable and programmable nonvolatile memory cell to store multi-valued information therein, includes a sense latch (SL) having a pair of input/output terminals, bit lines (G-BLR, G-BLL) provided in association with the respective input/output terminals of the sense latch, a plurality of nonvolatile memory cells (MC) selectively connected to the bit lines and capable of electrically performing erasure and writing, data latches (DLR, DLL) respectively connected to the bit lines, a first logic combining circuit (200) connected to the data latches and the sense latch, and a control circuit (18) connected to the sense latch, the data latches and the first logic combining circuit. The first logic combining circuit generates control data used to define to which threshold voltage state a threshold voltage state of one nonvolatile memory cell is set, every plural bits of write data and to supply the generated data to the corresponding sense latch and data latches respectively on a parallel basis. The control circuit is capable of performing program control so as to control the operations of the sense latch, the data latches and the first logic combining circuit to thereby bring each volatile memory cell to a predetermined threshold voltage state according to a logic value of the control data supplied from the first logic combining circuit to the sense latch and successively bring volatile memory cells to predetermined threshold voltage states according to logic values of control data supplied from the data latches to the sense latch.
Attention will be focused on a specific configuration wherein each of memory cells for performing four-value information storage is specialized. A semiconductor device such as a flash memory or a microcomputer in which a flash memory is on-chipped together with a CPU (Central Processing Unit), includes a first latch (SL) having a pair of input/output nodes, a first bit line (G-BLR) connected to one input/output node of the first latch and connected with a plurality of electrically rewritable nonvolatile memory cells MC), a second bit line (G-BLR) connected to the other input/output node of the first latch and connected with a plurality of electrically rewritable nonvolatile memory cells, a second latch (DLR) connected to the first bit line, a third latch (DLL) connected to the second bit line, a first logic combining circuit (200) connected to the first through third latches, a second logic combining circuit (30L, 31L) connected to the first bit line, a third logic combining circuit (30L, 31L) connected to the second bit line, and a control circuit (18) connected to the first through third latches and the first through third logic combining circuits. The first logic combining circuit generates control data used to define to which of first through third threshold voltage states (e.g., first through third write states) one nonvolatile memory cell is set with respect to a fourth threshold voltage state (e.g., erase state) and to supply the generated data to the corresponding first through third latches. The control circuit is capable of performing program control so as to control the operations of the first through third latches and the first through third logic combining circuits to thereby bring each volatile memory cell to a first threshold voltage state according to a logic value of the control data supplied from the first logic combining circuit to the first latch, bring each volatile memory cell to a second threshold voltage state according to a logic value of the control data supplied from the second latch to the first latch, and bring each volatile memory cell to a third threshold voltage state according to a logic value of the control data supplied from the third latch to the first latch.
Decoding the write data by means of the first logic combining circuit like a decoder upon data input in this way allows a reduction in processing time required to perform data latch processing which has heretofore been carried out by the data latches, sense latch and logic combining circuits on each bit line.
As a detailed aspect of the program control, the control circuit determines whether the threshold voltage state of the corresponding nonvolatile memory cell has reached an intended threshold voltage state through the use of the second and third logic combining circuits each time a voltage is applied for varying the threshold voltage of each nonvolatile memory cell in response to the predetermined logic value of the control data supplied to the first latch under the program control, and inverts the logic value of the control data of the first latch when the threshold voltage state thereof is found to have reached the intended threshold voltage state and subsequently suppresses a change in threshold voltage state with respect to the corresponding nonvolatile memory cell. As the program operation proceeds according to the write/verify operation, the respective control data initially latched in the first latch will gradually disappear.
 less than  less than Disturb/erraticxc2x7Check greater than  greater than 
The verify operation results in a check for the lower limit of the intended threshold voltage distribution. In order to check for the upper limit of the intended threshold voltage distribution, the control circuit is capable of performing disturb check control for determining under the program control whether the threshold voltage state of the nonvolatile memory cell to be maintained at the fourth threshold voltage state is distinguishable from an adjacent threshold voltage state (third threshold voltage state) higher than that in threshold voltage, first erratic check control for determining under the program control whether a threshold voltage state of a nonvolatile memory cell, which is to be changed to the adjacent threshold voltage state (third threshold voltage state), is distinguishable from a further adjacent threshold voltage state (second threshold voltage state) higher than that in threshold voltage, and second erratic check control for determining under the program control whether a threshold voltage state of a nonvolatile memory cell, which is to be changed to the further adjacent threshold voltage state (second threshold voltage state), is distinguishable from a still further adjacent threshold voltage state (first threshold voltage state) higher than that in threshold voltage.
For example, the disturb check control is a process for allowing the control circuit to determine through the use of the second and third logic combining circuits whether each memory cell should be maintained at the fourth threshold voltage state, based on the control data held in the second and third latches and data read from the corresponding memory cell, and for allowing the control circuit to set control data having a predetermined logic value prior to the logic value inversion to the first latch only with respect to the memory cell to be held in the fourth threshold voltage state thereby to determine whether the threshold voltage state of the memory cell is distinguishable from the adjacent threshold voltage state higher than that in threshold voltage.
For example, the first erratic check control is a process for allowing the control circuit to transfer the control data held in a predetermined one of the second latch and the third latch to the first latch through the use of the second and third logic combining circuits thereby to determine whether the threshold voltage state of the memory cell is distinguishable from the further adjacent threshold voltage state higher than that in threshold voltage. For example, the second erratic check control is a process for allowing the control circuit to transfer the control data held in the predetermined other of the second latch and the third latch to the first latch through the use of the second and third logic combining circuits thereby to determine whether the threshold voltage state of the memory cell is distinguishable from the further adjacent threshold voltage state higher than that in threshold voltage.
 less than  less than Program Retry greater than  greater than 
Upon the disturb check control, the first erratic check control or the second erratic check control, the control circuit may perform a program try as handling for the detection of abnormality. For example, when a state undistinguishable from a predetermined threshold voltage state is detected upon the disturb check control, the first erratic check control or the second erratic check control, the control circuit restores the control data sent from the first logic combining circuit to the first latch related to a memory cell, based on the control data held in the second and third latches and data read from the memory cell through the use of the second and third logic combining circuits, thereby allowing the resumption of the program process.
When the program process is resumed, each nonvolatile memory cell intended for the program process is the same as the immediately preceding program process. In short, a write retry is carried out inside the semiconductor device.
When the program process is resumed, each nonvolatile memory cell intended for the program process is newly specified. In short, it is designated by a new write sector address or the like supplied together with a retry command sent from outside a semiconductor device such as a host device.
 less than  less than Date Recovery greater than  greater than 
Upon the disturb check control, the first erratic check control or the second erratic check control, the control circuit may perform a data recovery as handling for the detection of abnormality. For example, when a state undistinguishable from a predetermined threshold voltage state is detected upon the disturb check control, the first erratic check control or the second erratic check control, the control circuit restores the control data sent from the first logic combining circuit to the first latch related to a memory cell, based on the control data held in the second and third latches and data read from the memory cell through the use of the second and third logic combining circuits, and restores write data represented in 2-bit units, based on the restored latched data of the first latch circuit and the latched data of the second and third latches, thereby allowing the output of the restored write data to the outside through the second and third latches.
 less than  less than Data Processing System greater than  greater than 
A data processing system is configured so as to include the semiconductor device, a memory controller which access-controls the semiconductor device, and a processor which controls the memory controller. A memory card comprises a card substrate including the semiconductor device, a memory controller which access-controls the semiconductor device, and an external interface circuit connected to the memory controller, all of which are packaged thereon. The present data processing system is capable of improving the efficiency of data processing with access to each nonvolatile memory cell.