1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method for forming a pad electrode of an LCD device.
2. Discussion of the Related Art
Ultra-thin flat type display devices include display screens having a thickness of several centimeters. Liquid crystal display (LCD) devices are ultra-thin flat type display devices that attract attention because they can be widely used for notebook computers, monitors, spacecraft, aircraft, etc.
The LCD device includes a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a thin film transistor and a pixel electrode. The color filter array substrate includes a color filter layer and a common electrode. The thin film transistor array substrate is provided at a predetermined interval from the color filter array substrate. The liquid crystal layer is formed between the thin film transistor array substrate and color filter array substrates. If a voltage is applied to the pixel electrode of the thin film transistor array substrate and the common electrode of the color filter array substrate, an arrangement of liquid crystal molecules of the liquid crystal layer is changed. Thus, it is possible to control the light transmittance, thereby displaying images.
Hereinafter, a thin film transistor array substrate of an LCD device according to the related art will be described with reference to the accompanying drawings.
FIG. 1A is a plan view illustrating a unit pixel region of a thin film transistor array substrate in an LCD device according to the related art. FIG. 1B is a cross sectional view taken along line I-I′ of FIG. 1A.
As shown in FIG. 1A, a plurality of gate lines 10 are formed in a first direction on a substrate 1. Then, a plurality of data lines 20 are formed in a second direction substantially perpendicular to the first direction. That is, a plurality of pixel regions 32 are defined by the plurality of gate and data lines 10 and 20.
A plurality of thin film transistors T are formed at respective crossings of the gate and data lines 10 and 20. Each of the thin film transistors T includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.
Then, a transparent pixel electrode 30 is formed in the pixel region, wherein the transparent pixel electrode 30 is electrically connected with the thin film transistor T.
A gate pad 12 is formed at a terminal of the gate line 10. Also, a gate pad electrode 40a is formed on the gate pad 12, for connecting to a driving circuit.
In addition, a data pad 22 is formed at a terminal of the data line 20. Also, a data pad electrode 40b is formed on the data pad 22, for connecting to the driving circuit.
Referring to FIG. 1B, a gate insulating layer 15 and a passivation layer 25 are sequentially deposited on the gate pad 12. Thus, the gate pad 12 is connected with the gate pad electrode 40a by a contact hole.
Also, the passivation layer 25 is formed on the data pad 22. Thus, the data pad 22 is connected with the data pad electrode 40b by a contact hole.
A method for connecting the gate pad electrode 40a with the gate pad 12 and for connecting the data pad electrode 40b with the data pad 22 will be described with reference to FIGS. 2A to 2G.
FIGS. 2A to 2G are cross sectional views taken along line I-I of FIG. 1A, and illustrate a process for respectively connecting the gate pad electrode 40a and the data pad electrode 40b with the gate pad 12 and the data pad 22.
As shown in FIG. 2A, the gate pad 12, the gate insulating layer 15, the data pad 22, and the passivation layer 25 are sequentially formed on the substrate 1. Then, contact holes are formed on the gate pad 12 and the data pad 22.
Referring to FIG. 2B, a material layer for a pad electrode 40 is formed on an entire surface of the substrate 1.
As shown in FIG. 2C, a photoresist layer 50 is formed on the material layer for the pad electrode 40.
Then, as shown in FIG. 2D, after the gate pad 12 and the data pad 22 are covered with a mask 60, the entire surface of the substrate 1 is exposed to light.
Referring to FIG. 2E, the photoresist layer 50 is patterned by development to form photoresist pattern layers 50a and 50b on the gate pad 12 and the data pad 22. Because the portions of the photoresist layer 50 are irradiated by light are removed, the photoresist pattern layers 50a and 50b are formed only on the gate pad 12 and the data pad 22.
Then, as shown in FIG. 2F, the material layer for pad electrode 40 is etched using the photoresist pattern layers 50a and 50b as a mask, to form gate pad electrode 40a and data pad electrode 40b. 
Referring to FIG. 2G, as the photoresist pattern layers 50a and 50b are removed, the gate pad electrode 40a is connected with the gate pad 12, and the data pad electrode 40b is connected with the data pad 22.
However, the related art method of forming the pad electrode has the following disadvantages.
To form the gate pad electrode 40a and the data pad electrode 40b, it is necessary to perform photolithography with exposure and development. However, the photolithography requires an additional light-irradiation device for providing light. Thus, process costs increase. In addition, the process is complicated.