1. Field of the Invention
The present invention relates to a technology for regenerating a processing timing for performing a high-accuracy bit demodulation on a received signal after an inverse spread processing in a spread spectrum communication system.
2. Description of the Related Art
In a spread spectrum communication system, a communicating apparatus on the transmitting side (transmitting apparatus) performs spread spectrum processing by performing primary modulation on data to be transmitted and multiplying the primary-modulated data with a spread code. Subsequently, the transmitting apparatus converts the signal obtained by spread spectrum processing to a radio-frequency band and sends the radio-frequency band to a corresponding communication apparatus on the receiving side (receiving apparatus). Upon receiving a signal from the transmitting apparatus, the receiving apparatus performs inverse spread processing on the received signal. For that, the receiving apparatus synchronizes a spread code, identical to the spread code used for multiplication at the transmitting apparatus, to an intended timing and multiplies the received signal with that spread code. Moreover, the receiving apparatus integrates the signal energy of the inversely-spread signal in spread code periods and performs bit determination based on the addition of integration results.
A data decoding circuit disclosed by Japanese Patent Application Laid-open No. H05-327657 is an example of a conventional technology applicable to a receiving apparatus in a spread spectrum communication system. The data decoding circuit identifies spread code periods by using cross-correlation values, performs accurate bit determination by obtaining correlation values of bit data in periods identical to the spread code periods, and demodulates a received signal.
However, the data decoding circuit is configured with a synchronous system in mind in which bit data cycles (bit periods of data) and spread code periods are in a relation of integral multiples (including the case of being identical). In other words, the data decoding circuit is not configured for an asynchronous system in which bit data cycles and spread code periods are not in a relation of integral multiples.
Thus, if the data decoding circuit is implemented for an asynchronous system in which bit data changes in mid-course of spread code periods, the amount of energy obtained by integrating the signal energy of the received signal and adding the integration results is sometimes less than the ideal amount of energy thereby causing decline in the bit determination accuracy.
To use the conventional data decoding circuit in a spread spectrum communication system while curbing decline in the bit determination accuracy, the system design needs to make sure that bit data cycles and spread code periods are in a relation of integral multiples. However, in such a system design, it is not possible to freely set the bit data cycles (bit rate).