(C) Copyright 1989 Texas Instruments Incoporated. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
This application is related to coassigned applications Ser. No. 08/265,977 filed Jun. 27, 1994 now U.S. Pat. No. 5,410,652 Ser. No. 08/326,677 filed Oct. 20, 1999, now U.S. Pat. No. 5,594,914, Ser. No. 07/590,372 filed Sep. 28, 1990, now U.S. Pat. No. 5,390,304 and Ser. No. 08/420,932 filed Apr. 12, 1995 now U.S. Pat. No. 5,535,348 incorporated herein by reference. In addition, the applicants hereby incorporate by reference the following co-assigned patent documents.
a) U.S. Pat. No. 4,713,748
b) U.S. Pat. No. 4,577,282
c) U.S. Pat. No. 4,912,636
d) U.S. Pat. No. 4,878,190
e) U.S. application Ser. No. 347,967 filed May 4, 1989
f) U.S. application Ser. No. 388,270 filed Jul. 31, 1989
g) U.S. application Ser. No. 421,500 filed Oct. 13, 1989
1. Field of the Invention
This invention generally relates to data processing devices, systems and methods and more particularly to communication between such devices, systems and methods.
2. Background Art
A microprocessor device is a central processing unit or CPU for a digital processor which is usually contained in a single semiconductor integrated circuit or xe2x80x9cchipxe2x80x9d fabricated by MOS/LSI technology, as shown in U.S. Pat. No. 3,757,306 issued to Gary W. Boone and assigned to Texas Instruments Incorporated. The Boone patent shows a single-chip 8-bit CPU including a parallel ALU, registers for data and addresses, an instruction register and a control decoder, all interconnected using the von Neumann architecture and employing a bidirectional parallel bus for data, address and instructions. U.S. Pat. No. 4,074,351, issued to Gary W. Boone, and Michael J. Cochran, assigned to Texas Instruments Incorporated, shows a single-chip xe2x80x9cmicrocomputerxe2x80x9d type device which contains a 4-bit parallel ALU and its control circuitry, with on-chip ROM for program storage and on-chip RAM for data storage, constructed in the Harvard architecture. The term microprocessor usually refers to a device employing external memory for program and data storage, while the term microcomputer refers to a device with on-chip ROM and RAM for program and data storage. In describing the instant invention, the term xe2x80x9cmicrocomputerxe2x80x9d will be used to include both types of devices, and the term xe2x80x9cmicroprocessorxe2x80x9d will be primarily used to refer to microcomputers without on-chip ROM; both terms shall be used since the terms are often used interchangeably in the art.
Modern microcomputers can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microcomputers and microprocessors. General purpose microprocessors, such as the M68020 manufactured by Motorola, Inc., are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit in equipment such as personal computers. Such general-purpose microprocessors, while having good performance for a wide range of arithmetic and logical functions, are of course not specifically designed for or adapted to any particular one of such functions. In contrast, special-purpose microcomputers are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microcomputer. By knowing the primary function of the microcomputer, the designer can structure the microcomputer in such a manner that the performance of the specific function by the special-purpose microcomputer greatly exceeds the performance of the same function by the general-purpose microprocessor regardless of the program created by the user.
One such function which can be performed by a special-purpose microcomputer at a greatly improved rate is digital signal processing, specifically the computations required for the implementation of digital filters and for performing Fast Fourier Transforms. Because such computations consist to a large degree of repetitive operations such as integer multiply, multiple-bit shift, and multiply-and-add, a special-purpose microcomputer can be constructed specifically adapted to these repetitive functions. Such a special-purpose microcomputer is described in U.S. Pat. No. 4,577,282, assigned to Texas Instruments Incorporated. The specific design of a microcomputer for these computations has resulted in sufficient performance improvement over general purpose microprocessors to allow the use of such special-purpose microcomputers in real-time applications, such as speech and image processing.
The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, systems and methods of operation. These demands have lead to increasing the performance of single-chip devices and single systems as state-of-the-art silicon processing technologies allow. However, some performance-hungry applications such as video conferencing, 3D graphics and neural networks require performance levels over and above that which can be achieved with a single device or system. Many such applications benefit from parallel processing.
However, performance gains from parallel processing are improved when communication overhead between processors is minimized. Thus, improvements are desirable which enhance interprocessor communications, and thus software and system development.
In general, the summary of the invention is a data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit, operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address.