1. Field
Example embodiments relate to semiconductor memory devices, and more particularly, to refresh methods and refresh circuits, which may be included in a semiconductor memory device having a bank group.
2. Description of Related Art
A Dynamic Random Access Memory (DRAM), which may be included in various semiconductor memory devices, requires a refresh operation to maintain data stored therein. Conventionally, a DRAM having a bank group includes a refresh counter for each bank group and the bank groups operate independently of each other.
In a DRAM having a bank group, a refresh operation may be classified into three different categories referred to herein as a bank refresh, a bank group refresh and an all-refresh.
A bank refresh is used herein to refer to a refresh performed for a specific bank requiring a refresh. A bank group refresh is used herein to refer to a refresh performed for a specific bank group requiring a refresh. The bank refresh and the bank group refresh have in common the characteristic of performing a refresh only when a specific bank and specific bank group, respectively, require refreshing.
Meanwhile, an all-refresh is a refresh performed for all of bank groups included in a DRAM. A counter allocated to a bank group may be used in an all-refresh. Further, in the all-refresh, a refresh in each bank group is performed in the same manner as a refresh in a preceding bank group.
FIG. 1 is a block diagram illustrating a semiconductor memory device having a conventional bank group. In FIG. 1, a plurality of conventional bank groups BG0, BG1, BG2 and BG3 and a conventional peripheral circuit 10 are shown.
Although there are four conventional bank groups BG0, BG1, BG2 and BG3 shown in FIG. 1, the number of the bank groups may vary. Each of the bank groups may include a plurality of banks. For example, the bank group BG0 shown in FIG. 1 includes banks bank01, bank02, bank03 and bank04, and the bank group BG1 includes banks bank11, bank12, bank13 and bank14. Likewise, the bank group BG2 includes banks bank21, bank22, bank23 and bank24, and the bank group BG3 includes banks bank31, bank32, bank33 and bank34. The number of banks in each bank group may vary.
The conventional peripheral circuit 10 may include circuits used and/or required for operation of a semiconductor memory device having the plurality of bank groups, for example, various drivers, circuits required for input/output of data, etc.
As described above, a refresh may be classified into three categories including bank refresh, bank group refresh and all-refresh. The bank group refresh may be used in a conventional semiconductor memory device having a structure including four banks as shown in FIG. 1. An all-refresh operation, which may be used in the conventional semiconductor memory device shown in FIG. 1, includes a bank group refresh operation that is performed for each of the bank groups of a device. Each of the bank group refresh operations performed in an all-refresh operation requires a refresh interval as further explained below with reference to FIG. 2.
FIG. 2 illustrates a refresh timing diagram of a conventional semiconductor memory device having the configuration shown in FIG. 1. In FIG. 2, a bank group refresh command is applied to the conventional semiconductor memory device, and then, an all-refresh command is applied to the conventional semiconductor memory device.
Referring to FIG. 2, a bank group refresh command Fg is applied to the first bank group BG0 of the semiconductor memory device and a bank group refresh operation is performed for the first bank group BG0. To perform the refresh of the first bank group BG0 in response to the bank group refresh command Fg, a bank group refresh time tFg is required.
Still referring to FIG. 2, after the bank group refresh command Fg is applied to the first bank group BG0 and the bank group refresh operation is performed on the first bank group BG0, an all-refresh command Fa is applied after a time duration equal to or greater than the group refresh time tFg. As such, there should be a time duration equal to or greater than the bank group refresh time tFg between the bank group refresh command Fg and the all-refresh command Fa. In other words, an all-refresh operation triggered in response to an all-refresh command cannot begin while one of the bank groups of a conventional semiconductor memory device is undergoing a bank group refresh.
The timing diagram in FIG. 2 also illustrates internal commands int_Fg_BG0, int_Fg_BG1, int_Fg_BG2 and int_Fg_BG3 of a conventional semiconductor memory device. As shown by the first internal command int_Fg_BG0 of the applied bank group refresh command Fg, a bank group refresh command Fg is applied and then after a given time tFg, an active command Act is applied to the first bank group BG0 and the first bank group BG0 is refreshed. As shown in FIG. 2, the group refresh time includes a tRAS_Fg time duration and Precharge time duration tRPg. The beginning of the Precharge time duration may be triggered by a group precharge command Pg as shown in FIG. 2.
In light of the above, applying all-refresh command Fa to the conventional semiconductor memory device can only trigger an all-refresh operation to begin immediately if the conventional semiconductor device does not include a bank group currently undergoing a bank group refresh operation. Further, in a conventional semiconductor memory device, if an all-refresh command Fa is received, the performance of the all-refresh operation always begins with a bank group refresh of the first bank group BG0 and proceeds sequentially performing bank group refresh operation on the remaining bank groups BG1, BG2 and BG3.