This invention relates to byte shifting functions carried out within a computer system. Still more particularly, this invention relates to a system for consecutively reordering of multi-byte word blocks when such are transferred between memory and CPU or CPU and memory.
The arithmetic logic unit (ALU) in a computer system which has the capability to handle multi-byte words in one clock cycle requires that the individual bytes be presented to the ALU in a particular order. Consider a 32-bit machine handles data words consisting of four 8-bit bytes which must be presented to the ALU in a specific order. Normally this is done with the most significant byte (MSB) first and the least significate byte (LSB) presented last, right-justified with the LSB having the highest memory address of the four bytes in the word. However, the end bytes of a 32-bit word block do not necessarily fall, when in memory, into the memory's double word boundary byte positions. In other words, a four-byte data word will usually fall into a position in the memory wherein it overlaps the double word boundaries in the memory. If this is so, the information will be read in an order which is not directly usable by the ALU. This being the case, the data word must somehow be reordered such that the individual bytes are consecutively reordered in proper fashion for their further processing by the ALU. Prior art computer systems which employ eight and sixteen bit processing schemes have handled any necessary reordering of data bytes by rotating either one or two bytes as necessary, one at a time, or rotating a full word one bit at a time on each firware clock cycle. The system of this invention provides the capabilty to rotate 4 byte data by any amount on byte intervals, in one firmware clock cycle.