Within integrated circuits, semiconductor devices such as memory cells and their components are becoming smaller. In a static random access memories (SRAMs), decreased cell size often enhances device performance. For example, as the size of a SRAM cell decreases the operational speed of the SRAM typically increases while the power consumption typically decreases. However, small SRAM cells likewise have some drawbacks. One such drawback is related to a decrease in storage node capacitance. The amount of charge at a storage node is about the product of the capacitance of the storage node and the voltage difference between the plates of the storage node capacitor. Smaller SRAM cells typically have less capacitance because the area of the storage node capacitor typically decreases with the SRAM cell size. The decrease in capacitance may allow alpha particles to cause soft errors.
Incorporating additional capacitors within a SRAM cell is one way to increase the storage node capacitance, which typically reduces the soft error rate of the SRAM cell. Capacitors that are connected to the storage nodes are discussed in many patents and technical articles. A dynamic-random-access memory (DRAM) typically has a storage capacitor such as a fin capacitor. Many DRAM storage capacitors including fin capacitors are complex and would require many additional processing steps to an existing SRAM process. In another attempt to reduce soft error rates, an SRAM cell may have its storage nodes capacitively coupled to a relatively constant voltage supply such as Vss or Vdd. One problem with coupling the storage nodes to these constant voltage supplies is that additional conductive layers are often required, making processing more complex and restricting use of the cell area for other circuitry. Accordingly, there is a need to increase capacitance of memory storage nodes to decrease soft error rates while at the same time keeping cell size and process complexity to a minimum.