Due to the rapid development of a three-dimensional (3D) package technique of mounting a plurality of semiconductor chips in a single semiconductor package, a through-silicon via (TSV) technique for forming a vertical electrical connection through a substrate or a die is being discussed. To improve performance and reliability of a 3D package, a device forming technique for reducing the likelihood that a TSV structure and elements located around the TSV structure will be damaged or degraded during the formation of the TSV structure so as to obtain stable operating characteristics and high reliability is being discussed.