The present invention relates to a semiconductor device including metal interconnects having an air gap and a method for fabricating the same.
A semiconductor device including metal interconnects having an air gap and a method for fabricating the same according to a first conventional example will now be described with reference to FIGS. 11A through 11C, 12A through 12C, 13A through 13C and 14A through 14C.
First, as shown in FIG. 11A, a lower interlayer insulating film 11 of an insulating material is formed on a semiconductor substrate 10 by chemical vapor deposition (CVD) or spin coating. Thereafter, although not shown in the drawing, a plug connected to the semiconductor substrate 10 or an interconnect formed on the semiconductor substrate 10 is formed in the lower interlayer insulating film 11.
Next, a first barrier metal layer 12, a first metal film 13 and a second barrier metal layer 14 are successively deposited on the lower interlayer insulating film 11. The first barrier metal layer 12 and the second barrier metal layer 14 are deposited by sputtering, and the first metal film 13 is formed by the sputtering, CVD or plating. Thereafter, an insulating film 15 is formed on the second barrier metal layer 14 by the CVD or spin coating.
Then, as shown in FIG. 11B, after forming a first resist pattern 16 on the insulating film 15 by lithography, the insulating film 15 is dry etched by using the first resist pattern 16 as a mask. Thus, plug openings 17 are formed in the insulating film 15 as shown in FIG. 11C.
Next, as shown in FIG. 12A, a second metal film 18 is deposited on the insulating film 15 so as to fill the plug openings 17 by the sputtering, CVD or plating.
Then, as shown in FIG. 12B, an unnecessary portion of the second metal film 18 present on the insulating film 15 is removed by chemical mechanical polishing (CMP), thereby forming contact plugs 19 from the second metal film 18. Thereafter, as shown in FIG. 12C, the insulating film 15 is dry etched so as to reduce the thickness thereof. Thus, upper portions of the contact plugs 19 protrude from the insulating film 15.
Subsequently, as shown in FIG. 13A, a second resist pattern 20 is formed on the insulating film 15 by the lithography. Then, as shown in FIG. 13B, the insulating film 15 is dry etched by using the second resist pattern 20 as a mask, thereby forming a patterned insulating film 15A in the pattern of interconnects.
Next, as shown in FIG. 13C, the second barrier metal layer 14, the first metal film 13 and the first barrier metal layer 12 are dry etched by using the second resist pattern 20, the patterned insulating film 15A and the contact plugs 19 as a mask, thereby forming metal interconnects 21 composed of a patterned second barrier metal layer 14A, a patterned first metal film 13A and a patterned first barrier metal layer 12A. In this manner, a remaining resist 22 in the shape of ridges with facets inclined at approximately 45 degrees is formed on the patterned insulating film 15A and facets are also formed in top portions of the patterned insulating film 15A.
In the first conventional example, the metal interconnects 21 are formed by dry etching the second barrier metal layer 14, the first metal film 13 and the first barrier metal layer 12 with the second resist pattern 20, the patterned insulating film 15A and the contact plugs 19 used as the mask. Instead, the metal interconnects 21 may be formed by dry etching the second barrier metal layer 14, the first metal film 13 and the first barrier metal layer 12 with the patterned insulating film 15A and the contact plugs 19 used as the mask after removing the second resist pattern 20 by ashing. In this case, the patterned insulating film 15A is sputtered during the dry etching for forming the metal interconnects 21, and hence, facets are also formed in the top portions of the patterned insulating film 15A.
Next, as shown in FIG. 14A, portions of the lower interlayer insulating film 11 between the metal interconnects 21 are trenched by the dry etching. Thus, the remaining resist 22 is removed but is transferred to the patterned insulating film 15A, resulting in enlarging the facets of the patterned insulating film 15A.
Then, as shown in FIG. 14B, an upper interlayer insulating film 23 is formed over the contact plugs 19, the metal interconnects 21 and the lower interlayer insulating film 11 by the CVD and air gaps 24 are formed in the upper interlayer insulating film 23 between the metal interconnects 21.
Subsequently, as shown in FIG. 14C, the upper interlayer insulating film 23 is planarized by the CMP. Thus, the interconnects having the air gaps are completed. Thereafter, the aforementioned sequence is repeated, so as to fabricate a semiconductor device having a multi-layer interconnect structure.
Since the upper interlayer insulating film 23 is formed with the facets formed in the top portions of the patterned insulating film 15A in the first conventional example, the upper interlayer insulating film 23 tends to enter the portions between the metal interconnects 21. Therefore, the top portion of the air gap 24 (a portion with a triangular cross-section) is positioned at substantially the same level as the metal interconnect 21.
A semiconductor device including metal interconnects having an air gap and a method for fabricating the same according to a second conventional example will now be described with reference to FIGS. 15A through 15C, 16A through 16C, 17A through 17C, 18A and 18B.
First, as shown in FIG. 15A, a lower interlayer insulating film 31 of an insulating material is formed on a semiconductor substrate 30 by the CVD or spin coating. Thereafter, although not own in the drawing, a plug connected to the semiconductor substrate 30 or an interconnect formed on the semiconductor substrate 30 is formed in the lower interlayer insulating film 31.
Next, a first barrier metal layer 32, a first metal film 33 and a second barrier metal layer 34 are successively deposited on the lower interlayer insulating film 31. The first barrier metal layer 32 and the second barrier metal layer 34 are deposited by the sputtering, and the first metal film 33 is formed by the sputtering, CVD or plating. Thereafter, an insulating film 35 is formed on the second barrier metal layer 34 by the CVD or spin coating.
Then, after forming a first resist pattern 36 on the insulating film 35 by the lithography as shown in FIG. 15B, the insulating film 35 is dry etched by using the first resist pattern 36 as a mask so as to form a patterned insulating film 35A in the pattern of interconnects as shown in FIG. 15C. Thereafter, the first resist pattern 36 is removed by the ashing.
Next, as shown in FIG. 16A, the second barrier metal layer 34, the first metal film 33 and the first barrier metal layer 32 are dry etched by using the patterned insulating film 35A as a mask, thereby forming metal interconnects 37 composed of a patterned second barrier metal layer 34A, a patterned first metal film 33A and a patterned first barrier metal layer 32A. Thus, the patterned insulating film 35A is sputtered during the dry etching for forming the metal interconnects 37, and hence, facets are formed in the top portions of the patterned insulating film 35A.
Then, as shown in FIG. 16B, portions of the lower interlayer insulating film 31 between the metal interconnects 37 are trenched by the dry etching. Thus, the patterned insulating film 35A is reduced in its thickness with the facets formed in the top portions thereof.
Subsequently, as shown in FIG. 16C, an upper interlayer insulating film 38 is formed over the metal interconnects 37 and the lower interlayer insulating film 31 by the CVD and air gaps 39 are formed in the upper interlayer insulating film 38 between the metal interconnects 37.
Next, after planarizing the upper interlayer insulating film 38 by the CMP as shown in FIG. 17A, a second resist pattern 40 is formed on the upper interlayer insulating film 38 as shown in FIG. 17B.
Then, as shown in FIG. 17C, the upper interlayer insulating film 38 is dry etched by using the second resist pattern 40 as a mask, thereby forming plug openings 41 in the upper interlayer insulating film 38. Thereafter, the second resist pattern 40 is removed by the ashing.
Subsequently, as shown in FIG. 18A, a second metal film 42 is deposited on the upper interlayer insulating film 38 by the sputtering, CVD or plating so as to fill the plug openings 41.
Next, as shown in FIG. 18B, an unnecessary portion of the second metal film 42 present on the upper interlayer insulating film 38 is removed by the CMP, so as to form contact plugs 43 from the second metal film 42. Thus, the interconnects having the air gaps are completed. Thereafter, the aforementioned sequence is repeated so as to fabricate a semiconductor device having a multi-layer interconnect structure.
Since the upper interlayer insulating film 38 is formed with the facets formed in the top portions of the patterned insulating film 35A in the second conventional example, the upper interlayer insulating film 38 tends to enter the portions between the metal interconnects 37. Therefore, the top portion of the air gap 39 (a portion with a triangular cross-section) is positioned at substantially the same level as the metal interconnect 37.
If a potential difference is caused between the adjacent metal interconnects 21 or 37, an electric field is collected at the upper and lower ends of each metal interconnect 21 or 37. This results in a problem that the capacitance between the interconnects is increased.
Therefore, in the first or second conventional example, the portions of the lower interlayer insulating film 11 or 31 between the metal interconnects 21 or 37 are trenched before forming the upper interlayer insulating film 23 or 38. Thus, the lower ends of the air gaps 24 or 39 are positioned to be lower than the lower ends of the metal interconnects 21 or 37, so as to reduce the capacitance between the interconnects.
However, the top portions of the air gaps 24 are positioned at substantially the same level as the metal interconnects 21 as shown in FIGS. 14B and 14C in the first conventional example and the top portions of the air gaps 39 are positioned at substantially the same level as the metal interconnects 37 as shown in FIG. 18B in the second conventional example. Therefore, the volume of each air gap 24 or 39 is reduced in a region of the upper interlayer insulating film 23 or 38 between the upper ends of the metal interconnects 21 or 37.
Accordingly, in the first or second conventional example, since the volume of each air gap 24 or 39 is thus reduced in the region between the upper ends of the metal interconnects 21 or 37 where the electric field is collected, the capacitance between the interconnects cannot be sufficiently reduced. In other words, although the first or second conventional example employs the metal interconnect structure having an air gap and the portions of the lower interlayer insulating film 11 or 31 between the metal interconnects 2137 are trenched before forming the upper interlayer insulating film 23 or 38 so as to reduce the capacitance between the interconnects, the capacitance between the interconnects cannot be sufficiently reduced by these conventional techniques.
In consideration of the aforementioned conventional problem, an object of the invention is definitely reducing capacitance between interconnects in a semiconductor device having a metal interconnect structure including an air gap.
In order to achieve the object, the semiconductor device of this invention comprises a plurality of metal interconnects formed on a lower interlayer insulating film provided on a semiconductor substrate; and an upper interlayer insulating film covering the plurality of metal interconnects and having an air gap between the plurality of metal interconnects, and a top portion of the air gap is positioned at a level higher than the plurality of metal interconnects.
In the semiconductor device of this invention, since the top portion of the air gap is positioned at a level higher than the metal interconnects, a main portion of the air gap, namely, a portion with a rectangular cross-section, is positioned at the same level as the metal interconnects. Therefore, the volume of the air gap in a region between the upper ends of the metal interconnects where an electric field is collected can be increased, so as to sufficiently reduce the capacitance between the interconnects. As a result, the performance and the reliability of the semiconductor device can be improved.
In the semiconductor device, it is preferred that portions of the lower interlayer insulating film between the plurality of metal interconnects are trenched by etching, that a second insulating film made from a different material from the lower interlayer insulating film is formed on the plurality of metal interconnects with a first insulating film sandwiched therebetween, and that the lower interlayer insulating film has an etching rate higher than an etching rate of the second insulating film in the etching of the lower interlayer insulating film.
Since the portions of the lower interlayer insulating film between the plural metal interconnects are thus trenched by the etching, the lower end of the air gap is positioned at a level lower than the lower ends of the metal interconnects, and hence, the volume of the air gap in a region between the lower ends of the metal interconnects where an electric field is collected can be increased. Therefore, the capacitance between the interconnects can be further reduced.
Furthermore, since the second insulating film made from a different material from the lower interlayer insulating film and having an etching rate lower than that of the lower interlayer insulating film in etching the lower interlayer insulating film is formed on the plural metal interconnects with the first insulating film sandwiched therebetween, no facet is formed in a top portion of the first insulating film when the lower interlayer insulating film is etched. Therefore, the upper interlayer insulating film minimally enters the portions between the metal interconnects, and hence, the top portion of the air gap can be definitely positioned at a level higher than the metal interconnects.
In the semiconductor device, it is preferred that the lower interlayer insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent and including neither nitrogen nor carbon, or a hybrid insulating material including an organic component and an inorganic component, and that the second insulating film is made from an inorganic insulating material including an inorganic material as a principal constituent and including nitrogen or carbon.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that of the second insulating film in etching the lower interlayer insulating film.
In the semiconductor device, it is preferred that the lower interlayer insulating film is made from an organic insulating material including an organic component as a principal constituent, and that the second insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent or a hybrid insulating material including an organic component and an inorganic component.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that the second insulating film in etching the lower interlayer insulating film.
In the semiconductor device, it is preferred that the lower interlayer insulating film is made from an inorganic or organic porous insulating material, and that the second insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent or a hybrid insulating material including an organic component and an inorganic component.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that of the second insulating film in etching the lower interlayer insulating film.
The first method for fabricating a semiconductor device of this invention comprises the steps of depositing a first metal film on a lower interlayer insulating film formed on a semiconductor substrate; forming a second insulating film made from a different material from the lower interlayer insulating film on the first metal film with a first insulating film sandwiched therebetween; forming a contact plug opening in the second insulating film and the first insulating film; forming a contact plug by filling the contact plug opening with a second metal film; forming a transfer pattern composed of a patterned second insulating film, a patterned first insulating film and the contact plug by etching the second insulating film and the first insulating film with a mask pattern formed on the second insulating film in an interconnect pattern used as a mask; forming metal interconnects from the first metal film by etching the first metal film with the transfer pattern used as a mask; trenching portions of the lower interlayer insulating film between the metal interconnects by etching the lower interlayer insulating film under conditions in which the lower interlayer insulating film has an etching rate higher than an etching rate of the second insulating film; and forming an upper interlayer insulating film on the lower interlayer insulating film, whereby covering the patterned second insulating film and forming an air gap between the metal interconnects.
In the first method for fabricating a semiconductor device of this invention, the lower interlayer insulating film is etched under conditions in which the etching rate of the lower interlayer insulating film is higher than that of the second insulating film so as to trench the portions of the lower interlayer insulating film between the metal interconnects. Therefore, no facet is formed in a top portion of the first insulating film, and hence, the upper interlayer insulating film minimally enters the portion between the metal interconnects. Accordingly, the top portion of the air gap can be positioned at a level higher than the metal interconnects so as to increase the volume of the air gap in a region between the upper ends of the metal interconnects where an electric field is collected. As a result, the capacitance between the interconnects can be sufficiently reduced.
The second method for fabricating a semiconductor device of this invention comprises the steps of depositing a first metal film on a lower interlayer insulating film formed on a semiconductor substrate; forming a second insulating film from a different material from the lower interlayer insulating film on the first metal film with a first insulating film sandwiched therebetween; forming a transfer pattern composed of a patterned second insulating film and a patterned first insulating film by etching the second insulating film and the first insulating film with a mask pattern formed on the second insulating film in an interconnect pattern used as a mask; forming metal interconnects from the first metal film by etching the first metal film with the transfer pattern used as a mask; trenching portions of the lower interlayer insulating film between the metal interconnects by etching the lower interlayer insulating film under conditions in which the lower interlayer insulating film has an etching rate higher than an etching rate of the second insulating film; and forming an upper interlayer insulating film on the lower interlayer insulating film, whereby covering the patterned second insulating film and forming an air gap between the metal interconnects.
In the second method for fabricating a semiconductor device of this invention, the lower interlayer insulating film is etched under conditions in which the etching rate of the lower interlayer insulating film is higher than that of the second insulating film so as to trench the portions of the lower interlayer insulating film between the metal interconnects. Therefore, no facet is formed in a top portion of the first insulating film, and hence, the upper interlayer insulating film minimally enters the portion between the metal interconnects. Accordingly, the top portion of the air gap can be positioned at a level higher than the metal interconnects so as to increase the volume of the air gap in a region between the upper ends of the metal interconnects where an electric field is collected. As a result, the capacitance between the interconnects can be sufficiently reduced.
In the first or second method for fabricating a semiconductor device, it is preferred that a top portion of the air gap is positioned at a level higher than the metal interconnects.
Thus, the volume of the air gap in the region between the upper ends of the metal interconnects where an electric field is collected can be definitely increased, resulting in definitely reducing the capacitance between the interconnects.
In the first or second method for fabricating a semiconductor device, it is preferred that the lower interlayer insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent and including neither nitrogen nor carbon, or a hybrid insulating material including an organic component and an inorganic component, and that the second insulating film is made from an inorganic insulating material including an inorganic material as a principal constituent and including nitrogen or carbon.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that of the second insulating film in etching the lower interlayer insulating film.
In the first or second method for fabricating a semiconductor device, it is preferred that the lower interlayer insulating film is made from an organic insulating material including an organic component as a principal constituent, and that the second insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent or a hybrid insulating material including an organic component and an inorganic component.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that of the second insulating film in etching the lower interlayer insulating film.
In the first or second method for fabricating a semiconductor device, it is preferred that the lower interlayer insulating film is made from an inorganic or organic porous insulating material, and that the second insulating film is made from an inorganic insulating material including an inorganic component as a principal constituent or a hybrid insulating material including an organic component and an inorganic component.
Thus, the lower interlayer insulating film can easily attain an etching rate higher than that of the second insulating film in etching the lower interlayer insulating film.