1. Field of the Invention
The present invention relates to a CDMA system, and more particularly to an interleaver memory access apparatus and method of a CDMA system.
2. Description of the Background Art
FIG. 1 is a schematic block diagram of a general CDMA system in accordance with a conventional art. As shown in the drawing, the conventional CDMA system includes a frame quality indicator 10 for attaching a frame quality indicator indicating a data rate to a source data, a trail bit attaching unit 20 for attaching a 8 bit encoder trail bit to an output of the frame quality indicator 10, a convolutional encoder 30 for receiving the data bit from the trail bit attaching unit 20 and generating three code symbols (a serial data) per each data bit, a code symbol repeating unit 40 for repeating a symbol for the convolutional encoder 30 to make the same data size as the full rate, an interleaver memory 50 for storing the code symbols outputted from the code symbol repeating unit 40 according to a row and a column addresses outputted from an address generator 60, an orthogonal modulator 70 for receiving the code symbols from the interleaver memory 50, generates one Walsh index for 6 code symbols and outputs 64 Walsh codes, and a radio frequency processor 80 for spread-modulating the 64 Walsh chips outputted from the orthogonal modulator 70 and transmits a radio frequency signal.
The operation of the CDMA system constructed as described above will now be explained. For explanation's sake, it is assumed that the data rate is 4800 bps.
When a source data, an analog voice signal, is inputted to the CDMA system, the inputted source data is PCM-modulated and inputted through a VOCODER (not shown) to the frame quality indicator (FQI) 10.
Then, the frame quality indicator 10 attaches a predetermined bit of frame quality indicator indicating 4800 bps to the inputted source data and outputs a 4.4 kbps data bit. The trail bit attaching unit 20 attaches 8 bit of encoder trail bit to the 4.4 kbps data bit and outputs a 4.8 kbps data bit.
The convolutional encoder 30 generates three code symbols for each data bit outputted from the trail bit attaching unit 20 and outputs a 14.4 ksps code symbol.
The code symbol repeating unit 40 repeatedly outputs by one time the code symbols inputted from the convolutional encoder 30 and generates a 28.8 ksps code symbol, to make the same data size as that of the full rate (9600 bps).
In case that the data rate is 2400 bps, the code symbol repeating unit 40 repeats 3 times of code symbols. In case that the data rate is 1200 bps, the code symbol repeating unit 40 repeats 7 times of code symbols. Thus, the rate of the code symbols outputted from the code symbol repeating unit 40 has the same data size as that of the full rate.
As shown in FIG. 2, the interleaver memory 50 includes 32 row and 18 columns and writes and reads the code symbols outputted from the code symbol repeating unit 40 according to the row and the column address outputted from the address generator 60.
The orthogonal modulator 70 decodes the code symbols, which are inputted from the interleaver memory 50, by six ones to generate one Walsh index, and selectively outputs one of the 64 Walsh codes by using the generated Walsh index. Therefore, the ratio frequency processor 80 spread-modulates the 4.8 Ksps Walsh chip outputted from the orthogonal modulator 70 and converts it to a radio frequency signal and transmits the converted radio frequency signal.
The access operation of the interleaver memory 50 will now be described in detail.
Generally, the CDMA system supports a variable data rate. Accordingly, the code symbol repeating unit 40 repeats the code symbols (the serial data) for the data rates except for the full rate (9600 bps), that is, a half rate (4800 bps), a quarter rate (2400 bps) and an eight rate (1200 bps), to process easily the data.
The CDMA system transmits a data through a radio interface. However, when a data is transmitted through the radio interface, a data loss (an error) may unexpectedly occur due to various noise. Thus, before modulating and transmitting of the code symbol, a data interleaving is performed to prevent a burst error.
In the conventional CDMA system, the data interleaving is implemented by the interleaver memory 50 and the address generator 60.
The interleaver memory 50 sequentially writes the code symbols outputted from the code symbol repeating unit 40 at the position of a normal interleaver memory map as shown in FIG. 2 according to the row and the column addresses outputted from the address generator 60. Consequently, 1˜576 code symbols (one frame data) are written in the interleaver memory 50.
FIG. 3 illustrates an example of interleaver memory map for each data rate.
Once the data writing operation is completed, the reading operation of the interleaver memory 50 is performed according to the order determined in a CDMA mobile communication standard, that is, according to the order of the following row address in the normal interleaver memory map of FIG. 2.
Fullrate: 1 2 3 4 5 6 7 8 9 10 . . . 25 26 27 28 29 30 31 32
Halfrate: 1 3 2 4 5 7 6 8 9 11 . . . 25 27 26 28 29 31 30 32
Quarterrate: 1 5 2 6 3 7 4 8 . . . 25 29 26 30 27 31 28 32
Eight rate: 1 9 2 10 3 11 4 12 . . . 21 29 22 30 23 31 24 32
For example, on the assumption that the code symbols of the full rate are stored in the interleaver memory 50 in the form as shown in FIG. 4, the address generator 60 changes the column from 1˜12 in a state that it has outputted one row address, so that the 12 code symbols are sequentially read from the interleaver memory 50.
Code symbols of other data rates also read according to the same raw address and the column address order as that of the full rate.
As described above, in the conventional CDMA system, the access (the reading and writing) operation of the interleaver memory is repeatedly performed by code symbols.
In this respect, however, in order to read and write the code symbols of one frame, the serial data, since the address (the row and the column) generation and the access operation of the interleaver memory should be performed so frequently, causing a disturbance to the rapid data processing and a low power consumption.
In addition, in the conventional CDMA system, the orthogonal modulator 70 receives 6 code symbols, the serial data to generate one Walsh index. However, in order to generate one Walsh index, the orthogonal modulator 70 should wait for 6 code symbols to be received from the interlever memory 50, causing a problem that the data processing time is increasingly extended.
Thus, the conventional CDMA system fails to cope suitably with the rapid data processing and the minimum power consumption required for the mobile communication system.