An integrated circuit (IC) device can have an input/output (I/O) controller that simultaneously provides multiple threads with access to one or more processor cores of the IC device. The I/O controller can be divided into multiple partitions with each of the multiple threads being allocated a respective partition. When an error is detected in one of the threads, a processor core may determine that the thread needs to be reset. Typically, this reset is implemented as a global reset of the entire I/O controller, including all of the partitions and threads. During the global reset all of the resources are de-allocated from the threads, and the I/O controller flushes out and drops all outstanding transactions associated with the one or more processor cores. Thus, a failure of one thread in a multi-threaded system results in an inefficient reset of all of the threads.