1. Technical Field
The present invention relates to a power-saving circuit for a digital video display device, and more particularly to a power-saving circuit for a digital video display device for detecting whether a transmission minimized differential signaling (TMDS) clock signal is input and performing a power-saving mode according to the detection result.
2. Description of the Related Art
In general, an analog video display device employing a cathode ray tube (CRT) and a digital video display device employing a liquid crystal display (LCD) are widely used for a desktop computer and a portable computer, respectively, wherein the digital video display device employs an analog interface mode and a digital interface mode.
The digital video display device of the analog interface mode has an advantage capable of being directly substituted for the existing analog video display device, whereas the digital video display device of the digital interface mode has an advantage capable of being simple and facilitating the impedance match, so that most portable computers employ the digital video display device of the digital interface mode.
With reference to FIG. 1, FIG. 1 illustrates a power saving circuit 100 of a conventional digital video display device. Operation of the digital video display device of a conventional digital interface mode will be schematically described with reference to FIG. 1 as follows.
In general, graphic card built in a computer main body compresses and encodes horizontal/vertical synchronous signals and a digital video signal into a TMDS data signal and outputs the TMDS data signal to the digital video display device together with a TMDS clock signal. A TMDS driving unit 10 of the digital video display device decompresses the TMDS data signal Data received on line 6, along with a clock signal Clock on line 2 and outputs the horizontal/vertical synchronous signals Hsync and Vsync and the digital video signal DE.
A TMDS signal conversion method is a technology of decoding high-speed serial data received at a receiving side as parallel data and then encoded into the high-speed serial data to be transmitted from a transmitting side, which is widely used in the digital video display device.
The horizontal/vertical synchronous signals Hsync/Vsync and the digital video signal DE output from the TMDS driving unit 10 are input into a display driving unit 12, so that the display driving unit 12 drives a gate driver and a source driver. At this time, a controller 14 carries out a power-saving mode in accordance with whether the horizontal/vertical synchronous signals Hsync/Vsync input from the TMDS driving unit 10 exist.
Since a TMDS signal input to the TMDS driving unit 10 from outside the TMDS driving unit 10 is of a high frequency and a small amplitude, it is difficult for the controller 14 to directly recognize whether the TMDS signal is input. In general, the controller 14 receives the horizontal/vertical synchronous signals Hsync/Vsync output from the TMDS driving unit 10 and indirectly determines whether the TMDS signal is input. That is, if the controller 14 does not receive the horizontal/vertical synchronous signals Hsync/Vsync from the TMDS driving unit 10, the controller 14 enables the digital video display device to carry out a power-saving mode and the controller 14 supplies a power saving signal PS to a power supply unit 16. When the controller 14 receives the horizontal/vertical synchronous signals Hsync/Vsync, the controller 14 enables the video display device to return to a normal mode. The power supply unit 16 supplies an appropriate voltage Vcc to the TMDS driving unit 10, the controller 14 and to display driving unit 12. In order for the controller 14 to determine whether the TMDS signal is input through the TMDS driving unit 10, electric power should be supplied all the time to the controller 14 and the TMDS driving unit 14, even in a power-saving mode.
However, since, in the conventional digital video display device, such as illustrated in FIG. 1, the controller 14 and the TMDS driving unit 10 should be supplied with electric power all the time even in a power-saving mode as stated above, there is a problem in that the power consumption is increased when using the standard of the display power management system (DPMS) of the Video Electronics Standard Association (VESA) for video electronic equipment.
In order to solve the above stated problem, it is an object of the present invention, among other objects of the present invention, to provide a power-saving circuit for a digital video display device capable of satisfying the DPMS standards through the reduction of electric power consumption in a power-saving mode by detecting whether a TMDS clock signal is input, carrying out a power-saving mode according to the detection result, and stopping the driving of respective components including the TMDS driving unit during the power-saving mode operation.
In order to achieve the above object, and other objects of the present invention, an embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit and outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; a controller for outputting a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and outputting a second level of the power-saving signal when the second level of clock detecting signal is input to the controller from the clock signal detecting unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit, for cutting off the supply of the voltage except to the controller and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and for providing the supply of the voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.
In order to achieve the above object and other objects of the present invention, another embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode, the TMDS driving unit stopping driving an operation for signal converting when a first level of a power-down signal is input to the TMDS driving unit, and the TMDS driving unit starting the driving of the operation for signal converting when a second level of the power-down signal is input to the TMDS driving unit; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit, and outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; a controller for outputting the first level of the power-down signal to the TMDS driving unit and also for outputting a first level of a power-saving signal when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, and for outputting the second level of the power-down signal to the TMDS driving unit and for outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit, the power supply unit for cutting off the supply of the voltage except to the controller, the clock signal detecting unit and the TMDS driving unit when the first level of the power-saving signal is input to the power supply unit from the controller, and the power supply unit for providing the supply of the power to the TMDS driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.
In order to achieve the above object and other objects of the present invention, a further embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting a first level of a clock detecting signal when the TMDS clock signal is not input to the TMDS driving unit, and for outputting a second level of the clock detecting signal when the TMDS clock signal is input to the TMDS driving unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit, for cutting off the supply of the voltage to the TMDS driving unit and the display driving unit, but not to the clock signal detecting unit, when the first level of clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.
In order to achieve the above object and other objects of the present invention, a still further embodiment of a power-saving circuit according to the present invention includes: a TMDS driving unit for converting a TMDS data signal input together with a TMDS clock signal to the TMDS driving unit into horizontal/vertical synchronous signals and a digital video signal based on a TMDS signal conversion mode, the TMDS driving unit stopping driving of an operation for signal converting when a first level of a clock detecting signal is input to the TMDS driving unit, and the TMDS driving unit starting the driving of the operation for signal converting when a second level of the clock detecting signal is input to the TMDS driving unit; a display driving unit for driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input to the display driving unit from the TMDS driving unit; a clock signal detecting unit for outputting to the TMDS driving unit the first level of clock detecting signal when the TMDS clock signal is not input the TMDS driving unit, and for outputting the second level of the clock detecting signal to the TMDS driving unit when the TMDS clock signal is input to the TMDS driving unit; and a power supply unit for supplying a voltage to the TMDS driving unit, the clock signal detecting unit and the display driving unit, for cutting off the supply of a voltage except to the TMDS driving unit and the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the TMDS driving unit, the clock signal detecting unit and to the display driving unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.
Accordingly, the present invention promotes satisfaction of the DTMS standards through the reduction of the power consumption by detecting whether a TMDS clock signal is input to the TMDS driving unit, carrying out a power-saving mode according to the detection result, and stopping the driving of the respective components including the driving of an operation for signal converting in the TMDS driving unit during the operation in the power-saving mode.