1. Field of the Invention.
This invention relates generally to memories for digital computer systems and particularly to multilevel hierarchical memories. Still more particularly, this invention relates to a cache memory that reduces cache miss latency by tracking multiple cache data read miss address patterns and by associating each cache data read miss address pattern with the specific instruction that generated the miss address pattern to improve the probability of a correct prediction.
2. Description of the Prior Art
Modern, high-performance microprocessors have extremely high memory bandwidth requirements and very short memory latency requirements. Memory latency is defined as the time between when the processor sends out a memory read address and when it receives the data back. In such systems, if a single-level memory hierarchy is used, then the memory subsystem must be constructed using high-speed static random access memory (SRAM) integrated circuits (ICs) because no other technology can meet the memory bandwidth and latency requirements. However, implementing a large main memory system with high-speed SRAM is not practical for most applications because of cost, size, power consumption, cooling, and weight constraints. Therefore, most computers utilize a multilevel, hierarchical memory subsystem that consists of a large, but relatively slow, main memory augmented by a much smaller but very high-speed cache memory. The main memory is usually constructed with dynamic RAM (DRAM) ICs. With modem microprocessors, the cache memory is usually implemented on the microprocessor chip using high-speed static RAM technology, although an off-chip cache can be constructed using high-speed static RAM ICs.
The use of a high-performance microprocessor chip with an on-board primary cache memory leads to the problem of cache-miss latency. The read access time to data in an on-board, high-speed, cache memory is typically one clock cycle. However, the read access time to data that is not in the cache can be as high as hundreds of clock cycles. This extreme difference in access time between the cache and the main memory is very significant with modern reduced instruction set computing (RISC) microprocessors that execute instructions at a rate of at least one every clock and operate at clock rates in the hundreds of megahertz. Therefore, the latency encountered when a miss occurs in the on-board cache can become a significant portion of the average read access time, even if the cache miss ratio is small.
Second-level, off-chip, cache memories are the usual means for reducing the cache-miss latency of high-performance workstations, file servers, and main frame computers. The problem with second-level cache memories is that they require an array of power consuming, heat generating, and expensive SRAM ICs that can significantly increase the size, weight, power consumption, and generated heat. Therefore, second-level cache memories are generally unsatisfactory for embedded computers. Embedded computers are normally designed to be small, lightweight, consume small amounts of power, and generate small amounts of heat in applications where they provide control and communications, such as satellites, weapon systems, and portable, mobile, and aeronautical computing systems.