The present invention is related to an improved method for forming a capacitor. More specifically, the present invention is related to a method for forming a circuit board having capacitors formed therein.
Capacitors are utilized in virtually every electronic device. Their function in an electronic circuit is well known and further discussion is not warranted herein.
It is an ongoing desire in the electronics industry to miniaturize circuitry. This miniaturization is intended to occur without loss of capability.
There are two major approaches to miniaturization. One approach is to miniaturize each and every component of a circuit and/or to increase the density of components in a circuit. This approach has been widely exploited and great strides have been made. Unfortunately, as the component size decreases, the handling complexity increases, requiring ever more intricate pick & place equipment which often must be developed, increasing production cycle time and overall manufacturing cost. Furthermore, as parts become smaller and more densely placed, parasitics within and between components increase.
A second approach to miniaturization is to combine functionality in selected components. For example, the real estate represented by the circuit board substrate functions, by and large, as structural support and for connectivity only and it does not otherwise contribute to the electrical function of the electrical circuit. Incorporating functionality into the area occupied by the substrate would serve two functions. A component which would otherwise be surface mounted, or otherwise incorporated, could be eliminated and the substrate space which is otherwise functionless can be reclaimed. While this is straightforward in theory, actually incorporating the functionality within the substrate has been difficult to implement in many applications. Gains have been made toward incorporating individual capacitors into a circuit substrate, as presented in U.S. Pat. No. 7,126,811; however, placement of discrete devices thin enough to be incorporated in a circuit substrate requires delicate pick and place equipment in order to avoid mechanical stresses to the part which may result in electrical defects, increased rework, etc. Placement of individual devices also requires extra processing time when compared to the lamination of a single layer.
There are applications where large decoupling capacitors are required for integrated circuit performance yet there is insufficient space available on the integrated circuit to allow the inclusion of such large capacitors. In such instances, external capacitance is recommended to be added as the integrated circuit is assembled to a circuit board, but an embedded capacitance layer could be sufficiently sized to be buried within the circuit board substrate, thus eliminating the need for an external capacitance.
Incorporation in the substrate of a ceramic or polymer-based embedded capacitance layer such as that presented in U.S. Pat. No. 6,657,849, is known in the art. These layers may be formed in advance and then incorporated with other layers using lamination processes well-known in the industry, requiring less processing time and less complex assembly equipment than incorporation of discrete components. However, the attainable capacitance is limited to a few hundred picofarads per square centimeter. A different type of capacitor, such as that created from a valve metal substrate, is necessary to maximize the available capacitance in the incorporated layer and the board space savings due to incorporation of the capacitance layer.
Manufacture of a valve metal based capacitance layer for incorporation into a circuit board substrate has been described in U.S. Pat. No. 7,317,610. Here, cathode layers are formed on the surface of a dielectric anodic oxide of a sheet-like valve metal substrate. The resulting sheet-shaped capacitor forms an embedded capacitance layer having high capacitance per area (on the order of tens of microfarads per square centimeter) for incorporation into a printed circuit substrate. However, there is not presented a means for electrical isolation of the anode and cathode layers during the circuit substrate assembly process. Specifically, during the formation of plated through holes, there is no mechanism in place to prevent contact between the valve metal substrate and the solid electrolyte material, leaving a possible means for the generation of an electrical short. Katsir, et. al. present in U.S. Pat. No. 6,865,071 a method by which the valve metal and dielectric are selectively applied in the vapor phase. This allows for the formation of discrete regions of the anode substrate which have no porous dielectric coating; however, application of the solid electrolyte and subsequent cathode layers must be controlled such that the conductive cathode coatings remain electrically isolated from the anode. Costly equipment is required to control application of the cathode materials such that electrical isolation of the electrodes is maintained without deleterious effect on capacitance per area.
The present invention is directed to a simple and cost-effective method for incorporating large capacitance into a substrate during manufacture.