Single-ended readout structures can be found in memories including read-only memory (ROM), random access memory (RAM), or other multiple-port register files designed for the simplicity of readout structures. In some approaches, the single-ended readout is also free from a sense amplifier (SA) pair device mismatch associated dual-ended readout. However, the noise margin window for a read “0” operation (actively pulling low) is generally smaller than the window for a read “1” (remaining at a pre-charged state).
In order to balance the read “0” and read “1” noise margin windows, the logic gate used for sensing is usually “high skewed” (higher P/N ratio, i.e., Isat P/Isat N) to change a trip point (i.e., the input voltage level where the output is decided as either a logical 0 or a logical 1) of the sense amplifier. For example, different device sizing, PMOS parallelism, or NMOS stacking can be used to change the P/N ratio. However, the effectiveness of this approach is very limited. A trip point of a sense amplifier is a function of the threshold voltages of NMOS/PMOS devices, which cannot be simply controlled by changing the P/N ratio. Also, the PMOS parallelism causes a large area penalty, and stacking NMOS not only needs a larger area, but also can cause contention for a data line between a pull-down device and a precharge device. In one example, increasing the P/N ratio from 2 to 7 only increases the input logical 1 voltage level, i.e., the trip point, about 60 millivolts (mV).
In another approach for the readout improvement, a dual-rail structure uses a separate higher power supply voltage for a memory cell array. The dual-rail scheme for the power supply voltage needs a separate power for the whole memory array, which generates another large power domain/net that uses a large amount of power bumps and metal tracks. A large power net requires significant additional efforts to improve the voltage drop (IR) and electromigration (EM) associated with the large power net. It is impractical to do a dynamic read-write assist by manipulating a large power net, because the slow responses are not fit for memory operations. Further, cross-power domain level shifters are needed that causes certain timing skews (delays). The cross-power domain isolation also needs special care in design and fabrication.
Accordingly, new methods are desired to solve the above problem.