This invention relates to a current source circuit and more particularly to a circuit to be utilized in a monolithic circuit having I.sup.2 L to analog interfacing circuits which provides a controlled source of current to interface between the open collector gates of the I.sup.2 L circuit portion and the pull up current for the analog circuitry.
The discovery of the compatibility of I.sup.2 L techniques to linear integrated circuit techniques has added new dimensions for integration of entire linear/digital systems on a single monolithic chip. When analog and digital functions are integrated, a new degree of simplicity is achieved with corresponding cost advantages. Such systems may require many interfaces between I.sup.2 L gates and typical non-inverted linear NPN transistors. In order to interface the open collector logic gates to the base electrodes of a linear transistor it is necessary to provide a current from some source. This current may be utilized to both: source the open collectors of the I.sup.2 L gates; and to provide the base pull up current for the linear non-inverted devices.
Conventional techniques for interfacing between the aforementioned open collector I.sup.2 L gates and linear devices are just not practical for realization in large scale integrated systems. For example, a standard technique may be to utilize a multi-collector lateral PNP transistor device. The emitter electrode of the transistor is usually coupled via a resistor to a source of supply with the collector electrodes being coupled respectively to a particular I.sup.2 L gate to analog interface. This method of providing the current source to the I.sup.2 L to analog interface suffers from a serious drawback when large scale linear-digital systems are to be incorporated on a single chip. Because of the low power consumption and minimum chip area available the fan out capabilities of the aforedescribed multi-collector lateral device is severely limited such that only a few I.sup.2 L to analog interfaces can be supplied thereby. Thus, for large digital/analog systems, many such interfaces would require a corresponding number of multi-collector transistor circuits. Thus the conventional current interface technique would consume a disproportionate share of available die area; defeating the goal of designing large scale linear/digital circuits on a single monolithic chip. Therefore, a need exists for an interface circuit having multiple fan out capabilities in a minimum die area.
In addition, current sources fabricated with standard lateral PNP transistors will not compensate for injector alpha variations in the I.sup.2 L circuitry. Injection alpha is defined as the efficiency of the injector bar to source current to the inverted transistors forming the I.sup.2 L gates. Due to conventional I.sup.2 L processes the injection current can vary widely from wafer to wafer. Therefore, it is possible that the current generated by conventional interface circuits can exceed the sinking capability of the I.sup.2 L gates thereby causing the digital/analog system to become nonoperable. Thus, a need exists to provide an interface circuit for providing a control current source which tracks I.sup.2 L circuit performance characteristics.