1. Field of the Invention
Embodiments of this application relate generally to electrical circuits and input/output (“I/O”) interfaces, and, more particularly, to a method and circuit for a low-power wide-tuning range current-mode logic (“CML”) output drivers for serial interfaces.
2. Description of Related Art
Electrical circuits and data storage devices have evolved becoming faster and transmitting greater amounts of data. With the increased speed and bandwidth capabilities of electrical circuits and data storage devices, I/O interfaces must be adapted to be compatible with new product, system and technology requirements. As technologies for electrical circuits, communications and data storage devices have progressed, there has developed a greater need for efficiency, reliability and stability, particularly in the area of I/O interfaces and serial I/O interfaces. However, voltage, current and signal speed considerations introduce substantial barriers to operational efficiency. Efficient operation in a low-power mode while maintaining a common-mode voltage (VCM) is particularly problematic.
Typically, in modern implementations for I/O interfaces, either a voltage divider is used, or part of the CML output driver circuit remains enabled, to maintain an output voltage in a low-power mode. However, using either of these approaches is inadequate to provide required efficiency while maintaining a common-mode voltage, especially in view of PVT corners. That is, variations in I/O interfaces and CML circuits due to PVT corners cause low yield and inadequate performance/efficiency using state of the art solutions. Voltage dividers are inherently inefficient as they consume power when in use. Voltage dividers are weak in terms of their ability to drive current. This causes large common-mode voltage (VCM) errors due to leakage current. Voltage dividers also lack the ability to control common-mode voltages (VCM) that vary in a wide range. Partially operating CML output driver circuits dissipate power by maintaining operation of a portion of the circuit in order to pull up the data inputs to the circuit operating voltage (e.g., a VDD node of the circuit). Partially operating CML output driver circuits also require their bias circuits to remain powered on (and/or enabled) and operational. The power dissipation of such circuits may consume in excess of 3 mA at a 1.0V peak-to-peak differential output voltage.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.