1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to an electrostatic discharge protection circuit with silicon-controlled rectifier characteristics for protecting integrated circuits from being damaged by electrostatic discharge.
2. Description of the Related Art
Integrated circuits (ICs) frequently break down when a high voltage is applied. Such high voltages may be generated as a result of static electricity or the like. Therefore, in ICs, an Electrostatic Discharge (ESD) protection circuit is generally provided to protect internal circuits from potential damage caused by external static electricity. IC design has been steadily reducing power consumption as well as the area occupied by the circuit. In such circuits it is known to provide ESD protection using a silicon-controlled rectifier (SCR) as shown in FIG. 1.
With reference to FIG. 1, an SCR 1 is used as an ESD protection circuit. An anode AN of SCR 1 is connected to a signal line DQ, which in turn is connected to an IC (not shown). If an overvoltage caused by ESD appears on signal line DQ, SCR 1 allows current to flow into a peripheral ground voltage line VSSQ. As a result, the IC is protected from shocks caused by ESD.
FIG. 2 is a circuit diagram of a conventional SCR for ESD protection circuits, like SCR 1 in FIG. 1. FIG. 3 is a sectional view showing the structure of the SCR of FIG. 2. Referring to FIG. 2, if a high voltage on a signal line DQ is applied to the anode AN of the SCR, the voltage of the anode AN may increase to a trigger voltage or higher. In this case, a PNP transistor 11 turns on, and an NPN transistor 13, the base of which is connected to the collector of the PNP transistor 11, also turns on. As a result, current flows from the anode AN into a first cathode KAT1 and a second cathode KAT2. In FIG. 2, the first cathode KAT1 is connected to a main ground voltage line VSSM, and the second cathode KAT2 is connected to a peripheral ground voltage line VSSQ.
However, in the structure of the conventional SCR, the main ground voltage line VSSM is substantially connected to the peripheral ground voltage line VSSQ, as shown in FIG. 3. That is, the main ground voltage line VSSM and the peripheral ground voltage line VSSQ are connected to the same P+ region 31. This creates a problem in that the voltage of the main ground voltage line VSSM, which requires high stability, may become unstable due to the voltage of the peripheral ground voltage line VSSQ, which is influenced by noise during the operation of the IC.
For reference, in FIGS. 2 and 3, reference character Rpsub is indicated by modeling a resistance element existing between an N-well 35 and a P+ region 31. Reference character Rnwell is indicated by modeling a resistance element existing in the N-well 35 between an N+ region 41 and a P-type substrate 10.