1. Field of the Invention
This invention relates to the field of programmable logic devices and, more particularly, to reducing the time required to test such devices.
2. Description of the Related Art
A programmable logic device (PLD) is a type of integrated circuit that can be programmed to perform specified logic functions. A field programmable gate array (FPGA) is one variety of PLD which can include several different types of components. An FPGA usually includes configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. This interconnect structure typically includes large numbers of interconnect lines which can be connected through programmable interconnect points. Some FPGAs also can include specialized components such as delay-locked loops, RAMs, processors, and the like.
FPGAs typically are programmed by loading a stream of configuration data, referred to as a bit stream, into internal configuration memory cells. The configuration data can be read from memory external to the FPGA or can be written to the FPGA by an external device. Once loaded into the configuration memory cells, the configuration data effectively programs the interconnect structure, CLBs, IOBs, and other components thereby specifying the device configuration. The collective states of the individual memory cells determine the functionality of the FPGA.
Modern FPGAs can be complex and large in size. In consequence, a significant number of configuration bits is necessary to program these devices. Oftentimes, the bit stream of an FPGA can be so large that the process of configuring the device itself becomes a significant factor in initializing any system within which the FPGA is used.
With respect to testing, the size of the PLD design and the size of the bit stream required to configure the device both directly affect the cost of testing, and therefore, the cost of the device itself. Typically, PLDs are tested by formulating a collection, or suite, of different test designs. Each test design usually is targeted to testing a particular aspect or physical portion of the PLD, such as the CLBs, the IOBs, or the interconnects, also referred to as routing resources. Testing proceeds by loading a test design, running a test using the loaded design, resetting the device, and repeating the process using different test designs from the test design suite.
To test routing, for example, test designs are sequentially loaded and tested. The test designs typically are based upon a full FPGA design which supports “walking one” or “walking zero” chain methodologies. “Walking” one or zero refers to the process of initializing the entire chain or signal path through the device to logic one or zero respectively. Each segment of the chain requires one clock cycle to transfer data. Once the chain is initialized to logic zero or one, the opposite value is introduced and walked through the signal path. For example, if initialized to logic zero, a logic one is introduced and walked through the signal path. This process takes “N” clock cycles where “N” is the number of elements in the path through which the value must pass. The opposite value shows up at the output of the design after “N” clock cycles in a successful test.
As can be seen from the example above, the size of test designs can become significant in terms of the time required to test a device. Specifically, since test designs directed to testing routing resources tend to be fully populated to maximize the number of routing resources checked per test, the number of clock cycles required to complete each test can become large. Larger designs require more clock cycles to completely test. The amount of time required is further lengthened since many test designs must be run to fully test the PLD routing resources.
As the test designs grow larger, so too do the bit streams needed to program the PLD. Thus, not only does the test execution time increase, but also the time required to configure the PLD for each test design. The time required to load larger bit streams becomes more problematic when considering the number of test designs that must be loaded to test the PLD.
Though a significant number of test designs is required to adequately test a modern PLD, it is not uncommon for test designs to exhibit some degree of redundancy, particularly with respect to routing resources. That is, more than one test design within a test design suite may utilize the same PLD routing resource resulting in redundant testing of that resource. There are, however, test designs within the test design suite that uniquely test a small number of routing resources, i.e., less than 20. These test designs cannot be excluded from the test suite as each may be the only means of testing a particular routing resource. Accordingly, it is difficult to reduce the number of test designs needed to test a PLD beyond a particular threshold.
It would be beneficial to reduce the number of logic stages of test designs used for testing PLDs in order to complete tests in fewer clock cycles. It further would be beneficial to reduce the size of bit streams needed to configure PLDs, thereby reducing the configuration time and total cost associated with testing.