Reductions in semiconductor device dimensions provide higher densities and improved performance for integrated circuits. In many integrated electronic devices, millions of discrete elements, such as transistors, resistors and capacitors are built in close proximity and integrated onto a single device. The combined layers of neighboring devices can form parasitic devices. Thus, one of the important initial steps in the fabrication of semiconductor devices is to electrically isolate adjacent electronic devices on a common substrate.
Isolation structures are generally formed using the local oxidation of silicon (LOCOS) isolation process. One disadvantage of the LOCOS process is that the silicon dioxide (isolation layer) grows in an isotropic manner resulting in consumption of the surface area of the semiconductor substrate and causes adjacent electronic devices that are isolated from one another to be a fixed minimum distance apart. This limits the maximum density of the electronic devices on each microchip. Additionally, the oxidation of the silicon surface can lead to large stresses in the device area (e.g. bird's beak), which may not be conducive for higher levels on integration demanded by each generation of devices.
Another technique which can be used in creation of isolation structures is referred to as the shallow trench isolation (STI) process. FIGS. 1(a) and (b) show layer configurations before and after CMP in a conventional STI process, respectively. To form the structure immediately before CMP shown in FIG. 1(a), a thin pad oxide 106 is first grown on a semiconductor 105 after which a thin silicon nitride layer 110 is deposited on the pad oxide. The pad oxide 106 and the nitride 110 are then etched to define the area of the isolation structure, including width 102, the width 102 typically being 1 to 100 μm. Next, the semiconductor substrate (e.g. silicon) is anisotropically etched to form a trench in the substrate 105 within the area defined including width 102.
The trench is then filled with deposited silicon dioxide or other dielectric 120 to a height above that of the silicon nitride surface (FIG. 1(a)). The deposited silicon dioxide has a very rough surface topography because the size and the density of the trenches vary within the die. To make the final STI structure, the deposited silicon dioxide is polished off using CMP to produce a substantially planar surface (FIG. 1(b)).
CMP combines both chemical action and mechanical forces and is commonly used to remove metal and dielectric overlayers in damascene processes, remove excess oxide in shallow trench isolation (STI) steps, and to reduce topography across a dielectric region. Components required for CMP include a chemically reactive liquid medium and a polishing surface to provide the mechanical control required to achieve planarity. The slurry may contain nanosize to microsize inorganic particles to enhance the reactivity and mechanical activity of the process.
Typically in case of dielectric polishing, the surface may be softened by the chemical action of the slurry, and then removed by the action of the particles. CMP is the only technique currently known for producing die level flatness required for sub 0.5 μm devices and is considered a requirement for the production of sub 0.2 μm shallow device isolation structures and state-of-the-art metal interconnect schemes.
A diagram of a conventional CMP polisher 200 is shown in FIG. 2. The CMP polisher includes a polishing pad 210 disposed on a platen 220 which rotates. A wafer 230 is pressed into direct contact with the polishing pad by a force exerting structure 250. A slurry solution is provided by the slurry feed 240 to wet the polishing pad 210 which chemically and physically interacts with the surface of the wafer 230.
Conventional slurries used for oxide CMP include a plurality of solid abrasive particles, such as silica or ceria. In FIG. 2, the polishing pad 210 is shown attached to the top of the rotating platen 220, while the wafer 230 is brought in contact with the pad 210 from the top. The wafer 230 can either be rotated or kept stationary. The wafer 230 can be moved in a circular, elliptical or in a linear manner with respect to the polishing pad 210. The pressure on the wafer 230 is generally varied from 0.1 Psi to 10 Psi, and the rotation speed of the platen 220 is generally varied from 5 rpm to 300 rpm.
The polymeric pad 210 transports the slurry below the wafer surface and participates in the wafer-particle pad interaction to remove the surface layers from the wafer. Typical pads which are commonly used include IC1000 CMP pads manufactured by Rodel Corporation, Newark, Del.
The diameter of the platen wheels 220 can vary from 10 inches to 45 inches, while the size of the wafer can vary from 1 inch to 12 inches in diameter. To maintain a fixed linear velocity, either the angular velocity can be increased or the radius of the wafer from the center can be increased.
During deposition of silicon dioxide for STI formation, the surface morphology of the silicon dioxide can be extremely rough because of the wide variation in the pattern density and dimensions of the trenches. For example, the dimensions of the trenches can vary from less than 0.1 μm to 1 mm, while the spacing between the trenches can also vary by about the same amount. Additionally the density of the patterns, which is defined as the ratio of the trench area to the total area, can vary from as low as 1% to nearly 100%. These wide variations in the size, spacing, and the density of the trenches generally lead to very wide variations in the surface morphology of the silicon dioxide or other dielectric filler material to be polished.
Because of the widely varying surface morphologies across the wafer, it is difficult to use a direct CMP process to remove the overburden of silicon dioxide from the surface of a patterned STI wafer. The CMP polishing rates generally have to be determined to be a function of pattern density of the trenches, its width, and pitch spacing and as well as its location within the wafer. Thus, a direct CMP process using conventional silica based slurries will cause higher removal rate in regions where the density of the trenches is high, compared to regions which have relatively large open areas, or regions with a low density of trenches. This effect can cause damage to the thin high-density isolated regions of trenches, while sometimes not removing the oxide in the less dense regions of the substrate. Damage occurs in isolated regions because the oxide in the area with a large percentage of trenches polishes at a much higher rate than the oxide over the nitride. CMP induced damage can cause silicon defects which can significantly increase junction leakage and make the wafer unsuitable for production.
To avoid damaging the substrate during STI polishing and to reduce the non-uniformity of the oxide polishing, some methods have been developed. In one method, silicon dioxide deposited in the trenches is reverse patterned and etched before the surface is planarized by the CMP process. A reverse pattern refers to the pattern which is inverse of the standard trench pattern which was used initially to etch to make the trenches within silicon substrate. The reverse pattern step makes the density of the silicon dioxide surface uniform across the die and the wafer. Thus, during the CMP process the removal of the silicon oxide is quite uniform and a relatively planar surface may be obtained following the CMP process.
Once the planar removal of the oxide layer is accomplished using standard silica slurries which typically operate in alkaline environments, the CMP process can generally be stopped at the underlying silicon nitride layer. The nitride layer typically has a polishing selectivity of less than 5:1 when compared to silicon dioxide polishing. The low removal rate of silicon nitride compared to silicon dioxide is sufficient to stop the CMP process before significant removal of the nitride overlayer takes place and damage occurs.
However, the reverse etch process followed by CMP has many disadvantages. Typically, this process requires an extra lithographic step which generally includes resist coating, mask exposure, resist development, silicon dioxide etching, and post photo clean steps. Accordingly, the extra lithographic step increases cycle time, increases the cost of manufacturing, and adds defect density. Thus, there is a need to develop a STI process which does not require added processing, such as a reverse etch step before the CMP process.
One method to eliminate the reverse etch step which would permit a direct STI process would be a CMP slurry which provides a high selectivity for polishing silicon dioxide compared to the underlying silicon nitride layer. If high silicon dioxide to silicon nitride selectivity could be achieved, then the polishing will effectively stop upon reaching the silicon nitride underlying layer. Thus, damage to the nitride coated isolated regions, which will later comprise active device areas, will not occur.
Several attempts have been made to develop slurries which exhibit a high removal rate of silicon dioxide compared to silicon nitride. U.S. Pat. No. 5,938,505 to Morrison et al. discloses adding tetramethyl ammonium hydroxide (TMAH), hydrogen peroxide and other additives to a silicon dioxide slurry to increase the selectivity of the polishing process to as high as 30:1. The high selectivity condition typically occurs when polishing is performed in highly alkaline environments, such as a pH from 11 to 13.
Although there is an increase in selectivity, this increase in selectivity is not high enough to eliminate the non-uniformity problems in pattern dependent silicon dioxide polishing. Additionally TMAH has been known to have stability problems and degrades to trimethyl amines which may lead to the breakdown in the slurry performance with time. Because of the breakdown problem, the slurry generally needs to be used almost immediately after it is prepared.
Another method for increasing the selectivity of silicon dioxide to silicon nitride polishing is to use ceria based slurries which include specific additives, such as L-proline. Selectivity of polishing rates of greater than 100 have been reported using ceria based slurries. The selectivity of these ceria based formulations generally permits completely stopping at the nitride layer which leads to small deviations in the silicon nitride left after completion of the CMP polishing process.
However, other factors are of concern when cerium oxide based slurries are used. First, cerium oxide is a high density material and is susceptible to settling, thus leading to adhesion and scratching of the dielectric surface layer. This can lead to an increase in defectivity. Second, the additives used in ceria based slurries used to increase the oxide to nitride selectivity destabilize the ceria based slurries and make them more susceptible to settling and large variations in polishing performance as a function of time. Third, these slurries also have to be mixed at the point of use, thus making the process more cumbersome. Finally, the chemical added to increase the selectivity of oxide to nitride polishing may not still increase the planarity of the polishing process. The high selectivity slurries need to be highly planar, which requires the polishing rate for the top area to be much higher than the bottom area. Otherwise even with high selectivity, the silicon dioxide trenches can have depressed regions (or dishing) which lead to non-planarity of the surface.
Low dielectric constant materials, referred to herein as “low K dielectrics”, are materials with dielectric constants less than about 3.5, such as fluorine, carbon, and/or nitrogen doped silica, nanoporous materials, and polymeric materials such as SiLK (manufactured by Dow Chemicals). Low K materials are also used as a low K dielectric in the metallization of the semiconductor devices. These low K dielectric materials can either be used with patterned aluminum based metallization or via a damascene process with copper based interconnects.
Due to an increase in device density provided by scaling of semiconductor processes to improve circuit performance, it is no longer generally possible to utilize a single metal interconnect level. Multilevel interconnect systems utilizing aluminum, copper, silver, tungsten, titanium nitride, tantalum, tantalum nitride, as electrical conductors and silica, doped silica and low K dielectric materials have been employed.
Similarly, other metals and electrically conductive metal compounds, such as tungsten, Pt, Ta, and TiN, can be patterned using a damascene process using silicon dioxide or a low K silicon dioxide like film as a dielectric material. During associated processing, a silicon dioxide or a low K material planarization step may be necessary. Presently, although showing high removal rate, silica based slurries used for this purpose lead to removal of significant amount of silicon dioxide or low K dielectric material because of poor planarity or lack of an auto-stop feature. The low K materials used in interconnect applications may also be capped with a thin layer of silicon dioxide so that the stresses on the low K material are significantly reduced. In this case, the surface silicon dioxide layer needs to be planarized.
There may be number of emerging applications such as ferroelectric random access memory devices (FeRAM), tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) devices where copper is deposited on a metal or a dielectric structure. In a FeRAM, copper may be used as the interconnecting metal or as sandwich metal layer on a gate electrode system. In a TMR or a GMR device, copper can be used as a back terminal, front-end terminal or an electrode on a multilayer magnetic/non-low K dielectric or silicon nitride material surface with removal of the minimum amount of materials as possible.
Other applications for silicon dioxide planarization is for optical dielectric components, and photonic band-gap devices which have alternating areas of high and low refractive index materials. To form these structures, planar polishing of silicon dioxide or similar materials (variants of silicon dioxide) must generally be performed. Other examples include the formation of multilevel MEMS structures. In these cases it may be necessary to remove silicon dioxide and low K films while at the same time planarizing the surface.
Finally, several applications mentioned above may require smoothing of surfaces without substantial removal of material. To smooth surfaces, the polishing rate of the dielectric is preferably less than 500 Å/min. This process is sometimes termed surface smoothening and referred to as chemical-mechanical smoothening (CMS). Such smooth surfaces can be excellent templates to fabricate a variety of novel structures.