An embedded non-volatile memory system may receive a first supply voltage VCC and a second supply voltage VCCQ from a host. Different hosts may supply the second supply voltage VCCQ at different levels. For example, some hosts may supply the second supply voltage at 3.3 Volts or 1.8 Volts, while other hosts may supply the second supply voltage at 1.2 Volts. In order to be compatible with different hosts and the possible different levels at which a host may supply the second supply voltage VCCQ, embedded non-volatile memory systems have been configured with hard-wired configurations pins and/or different substrate designs, which are costly and difficult to manage logistically. A less costly detection mechanism that can detect various levels of the second supply voltage VCCQ and that does not require additional configuration pins or different substrate designs may be desirable.
In addition, embedded non-volatile memory systems may include analog circuitry configured to deliver power and clock signals to a core, as well as perform other functions. The analog circuitry may receive a supply voltage from a host system with which it communicates. Current configurations of the analog circuitry may be robust (i.e., their exposure to inherent noisiness of the supply voltage is minimal) as well as compatible with current levels of the supply voltage. However, due to changes in host technology, some host systems may supply the supply voltage at levels lower than the current levels. Current analog circuitry configurations may not be compatible with these lower supply voltage levels. An analog circuitry configuration that is compatible with different levels at which different hosts may supply the supply voltage to the analog circuitry may be desirable.