This invention relates to gain control cells for adjusting the gains of signle paths.
A number of different arrangements have hitherto been proposed for adjusting the gains of signal paths in analogue IC systems. One well known circuit uses a balanced multiplier arrangement having two pairs of emitter-coupled transistors coupled so as to eliminate variations in the quiescent output voltage. This arrangement, however, provides a low output impedance and no rejection of supply line signals. Consequently other arrangements are often preferred.
In one solution, the bias and signal currents passing through one of the multipliers are inverted by a current mirror and added to the bias current passing through the other multiplier so that the bias currents cancel and a high impedance output is provided.
The known arrangements described above suffer from several disadvantages, notably complexity of biassing arrangements and sensitivity to the gain of the pnp transistors used in the current mirror. In general, pnp transistors in IC technology are of relatively poor performance. However, it is not normally desirable to invert the structures described to eliminate the pnp current mirror problem since the base-emitter voltage/collector current characteristics of npn transistors are less ideal than those of the pnp transistors. The pnp devices must therefore be used for the current mirror where its low gain causes dc offsets and gain errors.