The present invention relates to flex circuits for connecting magnetic heads to read and write circuits of a magnetic recording device. More particularly, the present invention relates to a trace interconnect array manifesting controlled inductance, capacitance and high frequency resistance in order to provide increased bandwidth and a process for making the array have the desired electrical characteristics by selective etching of conductive traces and adjacent dielectric materials.
Contemporary mass storage devices such as magnetic hard disk drives present a data transducer in a confronting relationship with a relatively moving data storage medium. Magnetic flux transitions are written to, or read from the medium. Disk drives typically include a rotating rigid storage disk having at least one major surface carrying a deposition or coating of magnetic material. A head positioner, commonly referred to as an actuator, positions the data transducer at selected radial storage track locations of the disk. In-line rotary voice coil actuators are presently preferred because of their simplicity and high performance characteristics, due in substantial part to intrinsic mechanical rigidity and a characteristic of being mass balanced about an axis of rotation relative to a drive base. A closed-loop servo system within the disk drive controls a voice coil motor of the actuator in order to position the transducer head at each desired disk radial location during track following operations and to move the transducer among radial locations during track seeking operations.
The read/write transducer head of a magnetic hard disk drive is typically a dual element design and is selectively deposited by thin film deposition upon a ceramic slider having a portion defining an air bearing surface for supporting the transducer at a very small distance away from the disk surface upon an air bearing present during disk rotation. One element of the transducer is typically a thin-film inductive write element. The other element of the transducer is typically a magnetoresistive (MR) sensor. A flux transition field of a recorded data pattern proximate to the MR sensor causes a miniscule change in electrical resistance of the sensor. Change of resistance in the presence of a constant current flowing through the sensor results in a minute voltage change, on the order of 3-5 millivolts, and this voltage change, representing a data pattern, is amplified by a preamplifier. Since the sensed signal (read signal) is so small, care must be taken to reduce extraneous noise pickup along a circuit between the read sensor and the preamplifier.
A head suspension extending from the actuator includes a load beam and a gimbal or flexure. The load beam includes a spring portion which applies a desired preload force to the slider which biases the slider toward the disk surface. This preload or bias force is overcome by airflow resulting from disk rotation and the formation of the desired air bearing between the slider and the adjacent disk surface. The gimbal enables the slider to follow the contour of the disk in order to maintain constant a very small spacing, on the order of one half to several microinches, between the transducer and the storage surface.
In the past, very small diameter twisted solid copper wires have typically been used to connect head elements at the slider to other signal carrying and signal processing elements of the disk drive located on or adjacent to the actuator structure. The two-conductor twisted pair service loop is inherently self-shielding from external noise sources such as electromagnetic interference (EMI) and radio frequency interference (RFI) by virtue of the fact that the conductors are twisted around each other. Coaxial transmission line cables are also inherently self-shielding, but the center conductor is electrically unbalanced with respect to the outer cylindrical shield conductor. Two-conductor balanced coaxial transmission lines avoid this drawback but are typically too bulky and cumbersome to be used to connect to the write/read elements of the very small sliders in present use in hard disk drives. One drawback of wires and cables is that they can apply an unwanted bias force to the slider supporting structure. Another drawback of discrete wires is that their electrical characteristics are not precisely controllable.
To reduce unwanted drawbacks of discrete wire conductors and cables, head suspensions having integrated trace arrays have recently been adopted in disk drive designs. These designs have typically included a stainless steel flexure upon which conductor structures have been formed by selective deposition/removal of dielectric material and conductor material. As formed the trace conductors of a service loop extend longitudinally from the transducer element to an interconnect or a preamplifier/write driver circuit. One example of a preferred method for manufacturing a magnetic head suspension with integrated trace array wiring is described in U.S. Pat. No. 5,666,717 to Matsumoto et al., entitled: xe2x80x9cMethod for Manufacturing a Magnetic Head Suspensionxe2x80x9d, the disclosure thereof being incorporated herein by reference.
Because the conductive traces of a service loop are typically formed in a side-by-side arrangement on a dielectric layer or substrate of the trace array, the traces essentially form an open-wire or micro-strip transmission line. Micro-strip line technology teaches that the loop and inter-conductor capacitance may be changed by changing the dimensions of and/or spacing between micro strips forming a transmission line. In the case of integrated trace array wiring designs for use within, or as part of, head suspension assemblies of hard disk drives, the dimensions of conductors and dielectric substrates may be governed more by mechanical constraints rather than by desired electrical characteristics.
Disk drive technology is continually seeking ways to increase storage capacity and performance of hard disk drives. One way to increase performance, as noted above, is to make write/read elements very small, and to reduce the size of sliders and head suspension assemblies, thereby reducing overall actuator mass and reducing average seeking operation time. One way to increase capacity is to make track widths narrower, so that more tracks may be defined in a unit storage area. Yet another way to increase capacity is to increase linear data density as by increasing data transfer rates, for example. With increased data transfer rates, care must be taken to ensure that the interconnect structure and electrical service loop between head and preamplifier has sufficient bandwidth margin to support the higher data transfer rate. One parameter which limits the bandwidth of a head interconnect service loop is impedance, which in turn depends upon inductance and capacitance characteristics of the interconnect structure.
One known way to reduce losses and noise pickup caused by the interconnect is to make the interconnect as short in length as possible. This approach requires locating some or all of the preamplifier electronics as close to the read element of the head as possible. This usually means mounting and connecting an integrated circuit chip directly onto the head suspension, a so-called xe2x80x9cchip-on-suspensionxe2x80x9d or COS approach. The COS approach has its own drawbacks, such as chip heat dissipation and electrical supply requirements and characteristics, issues which have not yet been fully developed and resolved.
FIG. 1 shows a present-day trace interconnect array 10. This exemplary trace interconnect array 10 typically consists of two trace conductors for each read or write channel of the head. The FIG. 1 enlarged cross-sectional view shows that the array 10 essentially comprises two copper conductor traces 12 and 14 separated from a stainless-steel substrate 16 by a dielectric layer 18 of polyimide, epoxy resin, acrylic resin, or other suitable polymeric dielectric material. The substrate 16 is typically of thin stainless steel sheet material and is formed into a load beam or flexure portion of a head suspension. A non-conductive overcoat 20 also typically covers and encapsulates the two conductors 12 and 14 (except at terminal locations) to prevent direct electrical or ambient atmospheric contact with either conductor. The overcoat 20 may be of polyimide, epoxy resin, acrylic resin or other suitable polymeric dielectric material. The trace interconnect array 10 may be formed in accordance with the process steps outlined in the referenced U.S. Pat. No. 5,666,717, incorporated hereinabove.
Capacitive coupling of each conductor 12, 14 to the metal substrate 16 depends upon the distance each conductor is placed above the substrate, and the dielectric properties of the layer 18, as well as confronting surface areas of the conductor surfaces facing the metal substrate. Inter-electrode capacitance depends upon the height of the facing walls of each trace conductor and the gap dimension between the two trace conductor facing walls, as well as the dielectric properties of portion of overcoat 20 filling the gap between the two facing walls of conductors 12 and 14. In the FIG. 1 prior art example 10, inter-electrode capacitance has a smaller value than an electrode-to-substrate capacitance value.
Several approaches have been proposed to reduce trace conductor-to-substrate capacitance for side-by-side trace conductor arrays generally of the type shown in FIG. 1. One approach is described in U.S. Pat. No. 5,712,749 to Gustafson, entitled: xe2x80x9cReduced Capacitance of Electrical Conductor on Head Suspension Assemblyxe2x80x9d. The ""749 patent teaches placement of a trace conductor pair onto a dielectric-coated stainless steel load beam. The load beam is provided with apertures, openings or discontinuities in alignment with longitudinal sections of the trace conductor pair. By aligning the trace conductor pair with such apertures, openings or discontinuities, capacitance between each conductor and the steel load beam substrate is somewhat reduced or otherwise can be somewhat controlled.
Another prior approach to reduce trace-to-load-beam capacitance is described in U.S. Pat. No. 5,687,479 to Bennin et al., entitled: xe2x80x9cElectrical Trace Interconnect Assemblyxe2x80x9d. The ""479 approach is to form a discrete two-conductor side-by-side trace array of spring-like beryllium copper alloy and suspend the array above the stainless steel load beam upon insulator standoffs. The trace conductors thereby are suspended slightly away from the facing surface of a metal load beam, in part by an air dielectric, thereby decreasing capacitance between each conductor and the stainless-steel load beam.
Other efforts to control electrical properties of side-by-side trace conductor arrays have been described in commonly assigned U.S. Pat. No. 5,717,547 to Young, entitled: xe2x80x9cMulti-Trace Transmission Lines for R/W Head Interconnect in Hard Disk Drivexe2x80x9d; U.S. Pat. No. 5,737,152 to Balakrishnan, entitled: xe2x80x9cSuspension with Multi-Layered Integrated Conductor Trace Array for Optimized Electrical Parametersxe2x80x9d; U.S. Pat. No. 5,754,369 to Balakrishnan, entitled: xe2x80x9cHead Suspension with Self-Shielding Integrated Conductor Trace Arrayxe2x80x9d; and, U.S. Pat. No. 5,812,344 to Balakrishnan, entitled: xe2x80x9cSuspension with Integrated Conductor Trace Array Having Optimized Cross-Sectional High Frequency Current Densityxe2x80x9d.
The disclosures of the foregoing U.S. Patents are hereby incorporated by reference into this patent as pertinent background information.
Even more recently it has been proposed to increase the height-to-width ratio of integrated trace conductors of an interconnect array. An example of this later proposal is depicted in FIG. 2. A side-by-side trace array 30 includes trace conductors 32 and 34 above a stainless-steel load beam substrate 36. The conductors 32 and 34 are formed on a dielectric layer 38, and a dielectric overcoat 40 encapsulates the conductors and fills a narrow gap between the facing sidewalls of the conductors. In the FIG. 2 array 30, the trace conductors 32 and 34 have a height-to-width ratio which reduces the width dimension and the conductor-to-substrate capacitance, at the expense of increasing the height dimension and inter-conductor capacitance. The inter-electrode capacitance of the array 30 is directly a function of the surface areas, and separation distance, of the two facing sidewalls of the conductors 32 and 34, and of the dielectric properties of the overcoat material 40.
While it might be proposed to remove the dielectric overcoat 40 completely, such proposal carries a considerable risk that the trace conductors 32 and 34 will become shorted together and cease to function effectively as a service loop, or become corroded or mechanically delaminated from the underlying dielectric layer 38. Therefore, a hitherto unsolved need has remained to provide a tall electrode trace conductor array having increased bandwidth, as typically characterized by reduced inter-electrode capacitance.
The present invention provides methods and structures to increase the bandwidth characteristics of a flexible trace conductor array, for use within a data storage device having a high transfer rate, such as a magnetic hard disk drive.
One object of the present invention is to provide a tall electrode trace conductor interconnect array which manifests reduced inter-electrode capacitance while maintaining mechanical integrity within a flexible interconnect structure of a head suspension of a hard disk drive in a manner overcoming limitations and drawbacks of prior approaches.
In accordance with one aspect of the principles of the present invention, a trace interconnect array is provided for electrically interconnecting a write or read element of a data transducer head respectively to a write driver circuit or read preamplifier circuit of a storage device, such as a magnetic hard disk drive or a magnetic tape drive. The trace interconnect array includes a dielectric support substrate which may be a flexible plastic film material, or which may be formed as part of a head suspension. At least two tall-electrode trace conductors are formed e.g. by selective electrochemical deposition onto the support substrate. A dielectric support structure is also formed on the support substrate and supports outside longitudinal walls of the two tall-electrode trace conductors. The dielectric support structure is formed as not to be substantially present in a longitudinal space separating the two tall-electrode trace conductors in order to reduce and control inter-electrode capacitance and thereby increase the resonant frequency and effective electrical bandwidth of the trace interconnect array. Preferably, the dielectric support structure is formed by selective etching or another selective material removal process in order to define and provide the air-dielectric space between the two tall-electrode trace conductors.
In one example of the invention, facing walls of the two tall-electrode trace conductors are shaped to converge toward the dielectric support substrate. In another example of the invention, the two tall-electrode trace conductors have height dimensions from the dielectric support substrate greater than a height dimension of the dielectric support structure. In a further example of the invention, the two tall-electrode trace conductors include lateral portions extending over respective adjacent portions of the dielectric support structure. In one more example of the invention, the dielectric support structure is selectively formed to define longitudinally spaced apart cross-tie structural interconnect portions between the inside walls of the tall-electrode conductors which separate longitudinally extending air dielectric spaces between the two tall-electrode trace conductors.
In one presently preferred example of the present invention, the dielectric support substrate is formed on a thin metal sheet portion of a head suspension for a magnetic hard disk drive.
In accordance with another aspect of the present invention a method is provided for making a trace interconnect array for electrically interconnecting a write or read element of a data transducer head to a write driver or read preamplifier circuit. The method essentially includes the steps of: forming a dielectric support substrate; forming at least two tall-electrode trace conductors on the support substrate; forming a dielectric support structure on the support substrate for supporting outside walls of the two tall-electrode trace conductors; and, selectively defining a longitudinally extending space between the two tall-electrode trace conductors in order to reduce inter-electrode capacitance.
These and other objects, advantages, aspects, and features of the present invention will be more fully appreciated and understood upon consideration of the following detailed description of preferred embodiments presented in conjunction with the accompanying drawings.