Conventionally, trench type semiconductor devices, such as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) with which a trench is formed in a substrate and a gate electrode is formed in the trench, and a fabrication method for the same are known. In such a trench type semiconductor device, an interlayer insulating film is formed so that an apertural area of the trench may be filled up. An electrode inside the trench and an external electrode are insulated by the interlayer insulating film.
A trench type MOS transistor including a n type silicon substrate in which a trench is formed, a polysilicon gate formed in the inside of the trench, and a local oxidation film (interlayer insulating film) formed in the top surface of the n type silicon substrate is disclosed in Patent Literature 1.
A high-concentration p type bulk layer formed in the both ends sandwiching the trench, a low-concentration p type bulk layer formed between the p type bulk layer and the trench, and a n type source layer formed in the upper layer of the p type bulk layer are formed in the n type silicon substrate. A part of local oxidation film is formed also between the internal wall surface of the trench and the polysilicon gate.
In the fabrication method of the MOS transistor described in Patent Literature 1, after forming the p type bulk layer in the n type silicon substrate, a silicon nitride film and a low temperature oxidation film for forming the patterned trench are formed. Next, after forming the trench, the low temperature oxidation film is removed. Next, the polysilicon gate is formed in the trench.
Next, the local oxidation film is formed on the polysilicon gate by annealing based on a LOCOS (Local Oxidation of Silicon) method. Then, after removing the silicon nitride film, an ion implantation of a p type impurity and a n type impurity is performed to sequentially, and the low-concentration p type bulk layer and n type bulk layer are formed. In this case, since a thin thermally oxidation film remains on the top surface of the layer which forms the low-concentration p type bulk layer and n type bulk layer, the impurity ions are implanted with the accelerating energy of the level which passes through the thin thermally oxidation film. Accordingly, many of the implanted ions pass through the thick local oxidation film on the polysilicon gate, and do not remain in the inside of the local oxidation film. Accordingly, the MOS transistor described in Patent Literature 1 is completed.
However, the MOS transistor described in Patent Literature 1 performs the segregation of the top surface of the polysilicon gate and forms the local oxidation film by annealing. Accordingly, there was a subject that it is not easy to apply thickness of the level that the polysilicon gate can be insulated by the local oxidation film. In order to make the local oxidation film into the thickness which can be insulated in this way, although the method of heat treatment of high temperature or long duration can be considered, another problem of degrading the element characteristic of the fabricated MOS transistor occurs in these methods.
Furthermore, in the MOSFET, the IGBT, etc. having the trench type gate structure, when forming electric contact at a base layer and an emitter layer or a source layer between trench—trench, it was difficult to secure a contact area with the miniaturization of device structure. Accordingly, there was a problem that the on resistance increases and the breakdown capability reduces with the reduction of the contact area.