1. Field of the Invention
The present invention relates in general to a non-volatile ferroelectric memory device, and more particularly, to a non-volatile ferroelectric memory device capable of outputting a data more stably, independent of external factors and the state of a cell, by storing differential data in a memory cell array block having sub bit lines and main bit lines in a hierarchy bit line architecture, comparing the stored differential data with each other during a data read operation, and sensing the data.
2. Description of the Related Art
In general, a non-volatile ferroelectric memory, i.e., a FeRAM (Ferroelectric Random Access Memory), has a data processing speed equal to that of a DRAM (Dynamic Random Access Memory) and also is capable of preserving stored data even when the power is off.
The FeRAM and DRAM are memory devices with similar structures, but the FeRAM uses a capacitor made of a ferroelectric material to benefit a high residual polarization characteristic of the ferroelectric material. The residual polarization of the ferroelectric capacitor allows data to be maintained in an FeRAM memory cell and not erased even if an electric field applied to the memory cell is removed.
FIG. 1 is a schematic diagram of a unit memory cell of a related art 1T1C type non-volatile ferroelectric memory device.
In the memory cell shown in FIG. 1, a bit line BL is formed in one direction and a word line WL is formed in a transversal direction with respect to the bit line BL. And, a plate line PL is formed in the same direction as the word line WL and at a predetermined distance therefrom. An NMOS transistor TR is disposed in such manner that a gate thereof is connected with the word line and a source thereof is connected with the bit line. A ferroelectric capacitor FC is disposed in such a manner that the first and second terminals thereof are respectively connected to the drain of the NMOS transistor TR and the plate line PL.
FIG. 2 is a timing diagram illustrating an operation of the memory cell in FIG. 1.
When a world line WL and a plate line PL in a selected cell are activated, a charge corresponding to a data “1” or “0” stored in the ferroelectric capacitor FC is applied to the bit line BL. In other words, a voltage in different yet designated levels according to the cell data is generated in the bit line BL.
FIG. 3 is a schematic diagram of a sense amp array for sensing a cell data in a related art non-volatile ferroelectric memory device.
As shown in FIG. 3, the sense amp array includes a plurality of sense amps S/A in a one-to-one correspondence to data bus lines BUS (0)–BUS (n). Each sense amp S/A compares a sensing voltage applied through the data bus line with a pre-determined reference voltage V_REF, and senses a cell data. The sensing voltage on the respective data bus line is induced by a data stored in a selected unit cell by the activated word and plate lines WL, PL, as illustrated in FIG. 2.
However, in the above-described system where the reference voltage is compared with the sensing voltage induced by a unit cell in order to sense a data in the corresponding cell, noise due to an external impact is often generated in the reference voltage and as a result of this, a precise, accurate data sensing is not obtained. In addition, in the case the ferroelectric capacitor is in abnormal state (WEAK), the sensing voltage is reduced and thus, sensing a data in a corresponding cell cannot be done as accurately as possible. Unfortunately this problem gets worse when the driving voltage of a chip is low.