The present invention relates generally to forward error correction and, more specifically, to a method and system for providing high-speed multi-channel forward error correction in a digital receiver.
Forward error correction (FEC) technology provides a method to detect and correct errors in transmitted data. As a result, this technology helps improve communication system performance. FIGS. 1A and 1B are simplified flow diagrams illustrating conventional implementations of an FEC circuit for an encoder and a decoder respectively. The conventional FEC circuit processes data symbol-by-symbol for one channel. This conventional FEC circuit, however, has a number shortcomings when it is applied to multiple channels. For example, one main problem with this conventional FEC circuit when applied to multiple channels is significant power consumption that is incurred when switching channels. If the FEC circuits are repeated to implement multi-channel designs, the excessive number of gates on an one-chip realization would be impracticable.
Another disadvantage of the foregoing conventional FEC circuit is that all the modules (blocks) in the FEC circuit collectively process one data stream at a time in a sequential manner. In other words, one data stream is processed after another sequentially. As a result, one or more modules in the FEC circuit may become idle thereby resulting in inefficient utilization of hardware resources.
The conventional FEC circuit, as shown above, receives a data stream that is made up of a continuous stream of fixed length packets. For the purpose of achieving packet delineation, synchronized bytes can be used; alternatively, syndromes that are computed over packets can be used. The use of syndromes improves packet delineation and synchronization for a receiver and provides error detection capability.
The syndrome s(x) is computed by passing one packet through a linear feedback shift register (LFSR) with the following filter characteristics:h(x)=(1+xnb(x))/g(x)where n is the length of a packet in bit or symbol and “+” is an exclusive-OR (XOR).
FIG. 2 is a simplified block diagram illustrating a conventional LFSR syndrome generator. The receiver computes a sliding syndrome over the packets in the data stream. The potential starting point of the packets is identified if the computed syndrome is a valid code word. A locked alignment condition is established if various valid syndromes are at their respective expected locations. One conventional method is to compute a sliding syndrome over the preceding symbols that make up a potential packet when each bit or symbol is received. However, a high number of computations is needed to compute the syndromes which significantly reduce the data throughput. Another conventional method is to compute one bit or symbol for a syndrome when the bit or symbol is received. The computation is repeated until a potential packet is received. If the syndrome is not valid, another syndrome is computed for the next potential packet with a different starting point. This method requires n2 symbols or n packets in the worst case to locate the starting point of a packet. As a result, the startup latency is quite long. Existing packet synchronization techniques have their shortcomings and disadvantages.
Another disadvantage of a conventional method that is used to generate syndromes is that multiple buffers are needed to store m*n symbols for potential packets when there are multiple channels, where m is the number of channels and n is the length of a packet.
Hence, it would be desirable to provide a method and system that is capable of achieving packet synchronization with two packets without consumption of substantial computation power and requiring minimal computing resources without regard to the number of channels.