(1) Field of the Invention
The present invention relates to the structure of a memory cell in a dynamic random access memory (DRAM), and in particular to a stacked capacitor cell structure thereof.
(2) Description of the Related Art
FIG. 4 shows the structure of a stacked capacitor cell. In the figure, there are shown an element isolation region 1 formed by a selective oxidation process, a gate oxide film 2 formed by thermal oxidation, a polycrystalline silicon gate electrode 3 for a memory transistor formed by a chemical vapor deposition process, impurity diffusion layers 4, 4' formed by ion implantation and having a conductive type opposite to that of a silicon substrate 10, a layer insulation film 5 formed by a CVD process, a contact hole 6 formed by etching, a conductive polycrystalline silicon layer 7, a capacitor insulation film 8, and a conductive polycrystalline silicon layer 9. With this arrangement, a memory cell comprising one transistor and one capacitor is formed, as shown by an equivalent circuit in FIG. 3. However, the above-mentioned memory cell structure suffers a decrease in accumulated charge capacity since the capacitance of the capacitor decreases as the level of integration of the device becomes higher thus making the area of the cell extremely small. Accordingly, a problem arises in that the so-called hold time, that is, the time of holding the accumulated charge becomes shortened.