1. Field of Invention
This invention relates generally to electronic devices and more specifically to clock or timing circuitry for use in such devices.
2. Discussion of Related Art
Computer data processors are widely used in modern electronic systems. For example, most desktop computers are built around a microprocessor chip. The microprocessor chip is a computer data processor that can be programmed to perform many data processing functions. Microprocessors perform arithmetic operations or logical operations that can be combined into many types of programs, such as those used to do accounting or word processing.
Other computer data processors are designed for specialized functions. One example is a digital signal processor (DSP). A digital signal processor is kind of microprocessor that is configured to quickly perform complex mathematical operations used in processing digitized signals (e.g. audio or video signals).
FIG. 1 shows a high-level block diagram of a computer data processor. FIG. 1 could represent a general purpose computer data processor or it could represent a special purpose data processor, such as a digital signal processor. FIG. 1 illustrates a processor chip 100. Within processor chip 100 is a microprocessor core 110. In operation, microprocessor core 110 reads instructions from memory and then performs functions dictated by the instruction. In many cases, these instructions operate on data that is also stored. When an operation performed by microprocessor core 110 manipulates data, the data is read from memory and new data is generally stored in memory after the instruction is executed.
FIG. 1 shows that processor chip 100 includes an on-chip instruction memory unit 112 and an on-chip data memory unit 116. Both the instruction memory unit 112 and data memory unit 116 are controlled by a memory management unit 114. Instruction memory unit 112 and data memory unit 116 each contain memory that stores information accessed by microprocessor core 110 as instructions or data, respectively.
Integrated circuit 100 also includes a memory interface 122 that can read or write instructions or data in memory 150. Memory 150 is off-chip memory.
It is traditional for a processor chip to contain a clock generator 160 that generates a clock, CLK. The CLK signal provides timing to circuitry in the microprocessor core and related circuitry. In some instances, multiple clocks of different frequencies or phases are derived from the CLK signal to satisfy timing requirements of various components. In other instances, clock generator 160 can be programmed to change the frequency or phase of CLK signal.
Many clock generators derive timing signals from a phase locked loop. FIG. 2 shows in block diagram form circuitry that can be contained within clock generator 160. The circuitry of FIG. 2 uses a phase locked loop (PLL) 210 to generate the CLK signal. Phase locked loop 210 includes a voltage controlled oscillator (VCO) 212. Many designs for voltage controlled oscillators are known. One such design involves a ring oscillator where the delay for a signal propagating around a ring can be controlled and establishes the frequency of oscillation.
The output of VCO 212 is provided to comparator 211, which converts the output of the VCO 212 into a digital signal. The digital signal out of comparator 211 is provided to divide-by-N counter 220. The value of N is usually programmable.
The output of divide-by-N counter 220 is provided to a phase detector 218. The second input (XTAL) of phase detector 218 is obtained from an oscillator, often a crystal. Phase detector 218 compares the output of divide-by-N counter 220 with the output of the crystal oscillator. When the two signals are equal, the output of phase detector 218 is zero. In this condition, the phase locked loop is said to be “locked”.
The locked condition occurs when VCO 212 is producing an output that has a frequency N times the frequency of the crystal. By varying N, a clock of a controllable frequency can be produced.
The output of phase detector 218 is used in a negative feedback loop to drive VCO 212 to the locked condition. The output of phase detector 218 is provided to charge pump 216. Charge pump 216 produces a control voltage. The output of charge pump 216 is filtered by low pass filter 214 and then applied as a control input to voltage control oscillator 212. When the loop is not “locked,” the output of phase detector 218 should, in “normal” operating states, change the control voltage so that VCO 212 changes its output frequency and phase to more closely match the frequency and phase of the XTAL input. Eventually, the output of VCO 212 will be driven to a state where the loop should become locked.
A phase locked loop provides a convenient way to generate relatively stable timing signals of controllable frequency. However, when first turned on or when its operation is disrupted, a phase locked loop requires time to reach a locked state. The process of a loop becoming locked is sometimes called “settling.” During the settling interval, the output of the phase locked loop might not be at the desired frequency or might vary in phase. Accordingly, it is usual for a timing circuit to include a delay element that inhibits use of the phase locked loop output by other sub-circuits in the digital system until a settling time has passed.
Thus, pursuant to the prior art, FIG. 2 shows use of a level detect circuit 240 that produces an output indicating that the power supply voltage, Vdd, has risen above some level that should be acceptable for operation of the phase locked loop circuitry. In turn, the output of level detect circuit 240 is used to reset counters 242 and 244, both of which are clocked by the XTAL signal, when Vdd is acceptable. The output of counter 242 then enables the phase locked loop.
It is undesirable for the phase locked loop to run before the supply voltage exceeds an appropriate level. In normal operation, the negative feedback loop in the phase locked loop should drive the loop to “lock” in the desired stable condition. However, if the appropriate power supply level is not supplied to the phase locked loop, the loop might not operate properly and might instead “lock” in an unintended operating state. By delaying operation of the loop when power is first applied until a time when the power supply voltage should have reached an appropriate level, chances of the loop locking in an unintended state are reduced.
Circuitry of FIG. 2 provides these delays. The output of counter 242 is indicated as a signal named PURST. When asserted (e.g. placed in a logical high state), the PURST signal indicates that a predetermined amount of time has passed since detection of some minimum Vdd level. The output of counter 244 enables other circuitry in integrated circuit 100. Counter 244 produces the ENABLE output some time after the phase locked loop 210 has been enabled. Counter 244 counts long enough (i.e. an interval predetermined by the circuit designer) that the output of phase locked loop 210 should be stable at the time the remaining circuitry within integrated circuit 100 is enabled.
It would be desirable to further reduce the chances of the timing circuitry of an electronic circuit, such as an integrated circuit containing a microprocessor core, from producing unintended operating states. That is, a need exists for a clock generation circuit that performs even more reliably.