The present invention relates to a semiconductor integrated circuit in a memory LSI, a logic LSI, a microcomputer, or the like which has a memory cell array and circuits for selecting desired memory cells included in the memory cell array. More particularly, it relates to techniques for repairing the defects of memory cells in such a semiconductor integrated circuit. By way of example, the techniques are effective when applied, to a memory LSI of large storage capacity such as a DRAM (dynamic random access memory).
Semiconductor integrated circuits have had their densities of integration heightened and their circuit elements microfabricated, and some of them are furnished with redundant constituents in order to enhance the available percentages thereof. When defects are found at an inspection stage of work such as a wafer probe test, a program for selecting the redundant constituents capable of repairing the defects are set with, for example, fuses.
While the conventional defect repair based on the redundant constituents has been furthered one step, a semiconductor integrated circuit with the self-check and self-repair function of deciding the presence or absence of defects by itself and repairing any present defect for itself within the semiconductor integrated circuit has been proposed in IEEE, 1989, CUSTOM INTEGRATED CIRCUITS CONFERENCE, Built-In Self-Repair Circuit for High-Density ASMIC, p. 26. 1. 1-p. 26. 1. 4. Such a technique stated in the bulletin is one which is directed toward ASMICs (Application Specific Memory ICs), and in which a memory is internally checked and self-repaired by affording external clock pulses. It is intended to shorten a time period for testing a wafer etc. and a time period for programming repair addresses with the fuses or the likes in the conventional defect repair based on the redundancy.