As illustrated in FIG. 1, an integrated circuit 1 can be constructed as an array of processor tiles 2, each tile comprising a respective processor 4, memory 6 and communications 8. The tiles 2 are connected via interconnects 10 which transport data and control information throughout the chip 1. A small number of tiles on the chip are coupled to external devices via external connections 12. Alternatively, or additionally, processors on different chips can be arrayed together to form a circuit.
The advantage of this architecture is that, by linking together a number of smaller modular processors at the design stage, a manufacturer can easily create a chip or circuit having a particular performance depending on the processing and memory requirements for the application or device in question, as well as on their particular cost, power and area targets.
However, there is also a difficulty in routing messages throughout the array. The messages may be delayed, may not be routed by the most efficient route, or may become deadlocked. Further, in large arrays the routing protocol may be complicated and unwieldy.