Distributed memory architectures are very good at implementing data flow processing, and data flow processing is in turn what almost every DSP and related application boils down to. Ideal fit between DSP and data flow systems is further strengthened by the need for DSP application to run in real-time, i.e. they must process data with a specified throughput and/or latency requirement. Shared memory systems may have difficulties in guaranteeing latency due to the uncertainties over memory contention.
If the central processing unit (CPU) of a DSP has to stop its current task and move data on and off the chip, performance will be poor. Therefore, direct memory access (DMA) controllers are provided for executing command sequences, autoinitialization and the like. In real-time data processing systems, this allows the DMA to run independently of the CPU. DMA requires primarily that the DSP does not access the memory involved. To achieve this, the CPU may be stopped or decoupled from the bus system to assure that the CPU and the DMA controller are not attempting to access the memories concurrently. During the DMA operation, the addresses fed to the memories are those generated by the DMA controller. After the DMA operation is completed, the addresses generated by the CPU once again determine which memory word is being accessed. Thus, DMA provides a data transfer which allows data to be moved between a peripheral controller and a system memory without interaction of the host CPU. The data may be moved by the peripheral controller itself, or by a separate third party DMA controller.
The stopping or decoupling of the CPU is usually performed based on interrupt routines triggered by external circuitries which intend to access the shared memory of the DSP. Thus, high interrupt overheads and associated DSP core load are associated with frequent interrupt service routines (ISRs) triggered in case of data movements between the shared memory and external devices or circuitries connected to the DSP.
Document EP 0 908 830 A1 discloses a DSP-based communications adapter including a number of digital signal processors and network interface circuits for providing an attachment of a multi-channel telephone line. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Thereby, a number of interrupts to the host processor from a single DSP is bundled and can be handled together. The overhead for individually handling each interrupt can thus be reduced. The interrupt blocks are written by means of a DMA operation to the memory of the host processor.
However, if this prior art solution is used for bundling interrupts of data movements between a shared memory of a DSP and an external circuitry, the CPU of the DSP still has to handle each interrupt of the interrupt block in order to trigger the corresponding ISRs required for data movement. Hence, overhead would still be a problem.