1. Field of the Invention
The present invention relates to circuitry for implementing sense amplifiers and OR gates in high density programmable logic devices (PLDs) to enable a power down mode.
2. Description of the Related Art
FIG. 1 shows a block diagram for a typical high density PLD such as the MACH130 manufactured by Advanced Micro Devices, Inc. As shown, the high density PLD includes four programmable array logic (PAL) blocks 101-104 interconnected by a programmable switch matrix 106. The PAL blocks 101-104 can be viewed as independent PLD devices on the chip, each similar to the popular lower density 22V10 PAL device, also available from Advanced Micro Devices, Inc. The switch matrix 106 connects the PAL blocks to each other and to all I/O pins 111-114 enabling a device, such as the MACH130, to provide six times the logic capability of the 22V10.
FIG. 2 shows greater detail for one quarter of the PLD block diagram of FIG. 1, including one of PAL blocks 101-104, labeled 200, as connected to switch matrix 106. Note that circuit components such as switch matrix 106 carried forward from FIG. 1 are similarly labeled in FIG. 2, as will be circuit components carried forward in subsequent figures. PAL block 200 receives 26 inputs from the switch matrix 106 in input buffers 202. Input buffers 202 provide signals on lines which are connected by programmable array cells 203 to product term (PT) lines 204, the programmable array cells 203 being located at each junction of the input buffer signal lines and the PT lines. Each PT line is connected to one of 64 sense amplifiers 206.
The outputs of sense amplifiers 206 are connected in groups of four to OR gates 208. To provide wider OR gates than the four input OR gates 208, the outputs of OR gates 208 are provided to inputs C0-C15 of a logic allocator 210 which selectively connects the inputs C0-C15 to outputs M0-M15 connected to sixteen output logic macrocells 212. The OR gates 206 and logic allocator 210 together provide configurable OR gates.
The logic allocator 210 is typically provided in a high density PLD to enhance the configurability of the logic provided, but is not typically provided on a lower density device such as the 22V10. FIG. 3 is a table showing the possible combination of connections of inputs C0-C15 to outputs M0-M15 as provided by logic allocator 210.
Macrocells 212 which receive the outputs M0-M15 of logic allocator 210 are programmable to be either registered or combinatorial. The macrocells 212 may also be configured to be synchronous, or asynchronous as controlled by reset and preset product terms. The outputs of macrocells 212 are providable to I/O cells 214 and may also be fed back to the switch matrix 106.
The I/O cells 214 are tri-state output buffers which may be enabled, or disabled as controlled by a product term. The outputs of the I/O cells may be provided at I/O ports 216 of the PAL block 200 and may also be fed back to the switch matrix 106.
FIG. 4 shows conventional circuitry for one of the sense amplifiers 206 of FIG. 2. Amplification for the sense amplifier is provided by inverter 400. Inverter 400 has an input connected to a PT line and an output connected to inverter 402 which provides buffering for the sense amplifier output. To increase switching speed, clamping is provided to the PT line utilizing transistors 404 and 406 to hold the PT line voltage near the threshold of the transistors of inverter 400. A current source 408 provides current to the PT line with a reference voltage VBSPRF provided to the gate of current source 408 to control its current flow. Circles on transistors, such as transistor 408, indicate a p-channel transistor, while no circle indicates an n-channel transistor.
A product term ground line (PTG) which is provided from programmable array cells 203 to a sense amplifier along with the PT line is connected to a current sink 410. Feedback is provided from the sense amplifier output through series inverters 412 and 414 to switch 416 to turn on an additional current sink 418 to assist current sink 410 when a programmable array cell is initially turned on.
To provide a power down mode, it is desirable to reduce the amount of power required by the sense amplifiers. The most significant amount of power is consumed by inverter 400 and clamping transistors 404 and 406 of the sense amplifier.
To provide a selectable power down mode on a macrocell-by-macrocell basis, a programmable feedback would be required to power down specific sense amplifiers which are programmed to be connected to the selected macrocell. Providing such feedback would be undesirable because of the additional logic circuitry required to provide the feedback, as well as the complex routing paths required on the chip for interconnecting the logic which would be a plumber's nightmare.
FIG. 5A shows conventional logic for implementing one of the OR gates 206 of FIG. 2. As shown OR gate 500 is actually implemented by two two input NOR gates 502 and 504 followed by a NAND gate 506.
FIGS. 5B and 5C show specific circuitry for the NOR gates 502 and 504 and NAND gate 506 respectively from FIG. 5A. As shown in FIGS. 5B and 5C, the NOR gates 502 and 504 and NAND gate 506 each contain four transistors for a total of twelve transistors per OR gate 500. Because the circuitry of FIG. 2 utilizes a significant number of OR gates 206, each utilizing twelve transistors, a significant number of transistors is required for a high density PLD as shown in. FIG. 2. It is, thus, desirable to reduce the number of transistors required to implement the OR gates 206.
Further, with OR gates configured as shown in FIGS. 5A-5C, sense amplifiers driving the inputs of the OR gates should provide a rail-to-rail CMOS voltage swing of 0.0V-5.0V to prevent the OR gates from continually drawing power. However, utilizing sense amplifiers providing a 0.0V-5.0V swing reduces switching speed. It is thus, desirable to configure the OR gates to enable reduction of the 0.0V-5.0V sense amplifier output swing without increasing power consumption.
FIG. 6 shows conventional circuitry for a subset of the internal components of the logic allocator 210 of FIG. 2 as connected to sense amplifiers 204 and OR gates 206. The portion of the logic allocator 210 shown includes the C0-C2 inputs with logic provided for connecting to the M1 output. As indicated in FIG. 3, output M1 can be connected to any combination of inputs C0, C1 and C2. Pass gates 600 are provided between the outputs of OR gates 206 and the inputs of an OR gate 604 to selectively connect one or more of inputs C0-C1 to M1. Switching transistors 602 are provided to connect unselected inputs of OR gate 604 to ground. Dashed lines are provided to show that C0 and C1 connections are also provided to additional pass gates connected to an OR connected to M0, while C1 and C2 connections are provided to additional pass gates connected to an OR gate connected to M2.
The circuitry for logic allocator 210 as shown in FIG. 6 requires a large number of transistors for the pass gates 600, switching transistors 602, and OR gates such as 604 which include twelve transistors each as shown in FIGS. 5A-5C. It is, thus, desirable to reduce the transistor count of the logic allocator.