1. Field of the Invention
The present invention relates to a nonvolatile memory device and a method for manufacturing the same.
2. Background Art
A technique of stacking multiple cells is now being developed in order to achieve high-density flash memories. The technique includes the following, for example. Dielectric films and electrode films are alternately stacked on a substrate, and then through-holes are formed simultaneously. Then, a charge storage layer retaining charges is formed on the side face of the through-holes, after which columnar electrodes are buried in the through-holes. Thereby, memory cells are arranged three-dimensionally at intersections of the columnar electrodes and the electrode films. Then, a plurality of selecting gate lines extending in one direction are provided on the uppermost electrode film. Then, a plurality of bit lines extending in another direction are provided thereabove and connected to the upper ends of the columnar electrodes. Thereby, an arbitrary columnar electrode can be selected. On the other hand, the electrode films are connected to word lines different from each other and thereby an arbitrary electrode film can be selected. Consequently, an arbitrary memory cell can be selected, and writing and reading of data can be performed.
On the other hand, nonvolatile memory devices using variable resistance stats of resistance materials such as a phase-change memory and resistance-change memory are expected as a nonvolatile memory device of high density and high reliability. In this case also, a large number of phase-change memory units and resistance-change memory units are stacked on a substrate to obtain a high memory density.
Thus, in phase-change memories, resistance-change memories, and nonvolatile memory devices of charge storage type in which multiple cells are stacked, a large number of films are stacked on the substrate and this leads to an increase of distortions of the substrate and a large warpage of the substrate because films which generate a compressive stress or a tensile stress are formed only on one surface of a substrate. For example, when a stacked film of a polycrystalline silicon film and a TEOS (tetraethyl orthosilicate) film is stacked 32 times, the warpage of the substrate becomes 200 μm or more in the convex direction. Such a large warpage deteriorates manufacturing process accuracy, prevents stable operation of manufacturing equipment, and causes a broken wafer, which leads to a big problem.
JP-A 2005-26404 (Kokai) discloses a technique of reducing the warpage of a wafer.