1. Field of the Invention
The present invention generally relates to virtual storage mechanisms for data processing systems and, more particularly, to new dynamic lookaside address translation (DLAT) structures and procedures which are capable of generating multiple addresses for a processor in a single cycle.
2. Description of the Prior Art
Virtual storage organization and management for data processing systems are described, for example, by Harvey M. Deitel in An Introduction to Operating Systems, Addison-Wesley (1984), by Harold Lorin and Harvey H. Deitel in Operating Systems, Addison-Wesley (1981), and by Harold S. Stone in High-Performance Computer Architecture, Addison-Wesley (1987). In a virtual storage system, paging is a relocation and address-to-physical-location binding mechanism providing the user of the system with what appears to be a considerably larger memory space than is really available. The key feature of the virtual storage concept is disassociating the addresses referenced in a running process from the addresses available in main storage. The addresses referenced by the running process are called virtual addresses, while the addresses available in main storage are called real addresses. The virtual addresses must be mapped into real addresses as the process executes, and that is the function of the dynamic address translation (DAT) mechanism. One such mechanism employs a directory look aside table (DLAT), sometimes referred to as a translation lookaside buffer (TLB), which stores recent virtual address translations. For virtual addresses stored in the DLAT, the translation process requires only a single or, at most, a couple of machine cycles. For addresses not stored in the DLAT, the DAT process may take from fifteen to sixty cycles.
Translations from the virtual address to the real address must be made to find where the addressed instruction or data is in main memory. This is typically done on a page basis. In fact, the translations stored in the DLAT are actually only page translations, and the last bits of an address are the location in that page, so only the page address must be translated. Often, the addresses are in a specific order as in scientific computing where the addresses are at specific increments in memory. These increments are called a "stride". If all addresses are in incremental order, the stride is one, but if every other address is used, the stride is two, and so forth. This permits easy prediction of future addresses, In scientific or vector computing, an instruction specifies a starting address, the stride and number of operands in the instruction. This allows the address generation to increment the earlier address by the stride to obtain the next address.
In typical applications, a processor generates only one address per cycle. Some processors have more than one address generator going to a DLAT (or TLB), but still only one address is actually translated per cycle. As processors have evolved, there has developed a need to generate and translate more than a single address per cycle. Specifically, the processor requires more than one memory request every cycle to be fully utilized. The requests may be, for example, three separate instructions so that three addresses must be generated every cycle to make the memory requests. What is therefore needed are new dynamic address translation (DAT) structures and procedures which are capable of generating multiple addresses for the same processor in a single cycle.