1. Field of the Invention
The present invention relates to a semiconductor device fabrication method of fabricating system large scale integration (LSI) devices and the like having mixed logic and memory parts, and a semiconductor device fabricated by this method. More particularly, it relates to a fabricating method of forming a gate pattern of a metal oxide silicon (MOS) transistor in logic parts in a system LSI and a structure of the gate pattern of the MOS transistor.
2. Description of the Related Art
Recently, there is a strong demand of miniaturization and multifunction in consumer electronic products and information devices. It is, accordingly, necessary to manufacture those electronic products, for example, a system LSI based on microstructure technology.
The most important problem in the above current demand is therefore to fabricate a device pattern of a MOS transistor in a logic part with a microstructure. Although various researches and developments for exposure light sources, photo resists, ultra-resolution technology, and the like have been done, at the present time the lithography (exposure) technology does not satisfy the current demand to miniaturization.
Recently, a resist sliming method has been proposed as one of technologies to fabricate a device pattern with a dimension of not more than a limitation of lithography resolution. This method can fabricate fine patterns with a dimension of not more than the limitation of a lithography resolution by performing an isotropy etching and the like for a resist pattern after the fabrication of this resist pattern.
Hereinafter, a description will be given of an example in which the resist sliming method is applied to a MOS transistor fabrication process.
FIGS. 120A–120C through FIG. 125 are plan views of a fabrication process of a MOS transistor in a logic section and sectional views thereof along lines X–X′ and Y–Y′. That is, as shown in FIGS. 120A–120C, a gate insulating film 201 is formed over a silicon substrate 200 including an element region 200a and an element isolation region 200b by a thermal oxidation method and the like. After this process, a work material film, for example, a poly-silicon film 202 as a gate electrode material film is deposited over the gate insulation film 201 by a chemical vapor deposition (CVD) method.
Following this process, a resist is applied over the poly-silicon film 202 and then dried, and a lithography process (exposure) is performed in order to form a first resist pattern, for example, a gate resist pattern 203 with a limitation dimension of the lithography (exposure) gate resist pattern forming process. In this process, the gate resist pattern 203 is formed over the element region 200a and the element isolation region 200b. Here, the pattern section over the element region 200a is called to as a gate electrode pattern section 203a and the pattern section over the element isolation region 200b is called to as a wiring pattern section 203b. 
As shown in FIGS. 121A to 121C, the gate resist pattern 203 is processed by the isotropy dry etching using O2 series gas, and as shown by dotted lines in those figures, the sliming process is performed in order to form the gate resist pattern 203′ whose dimension is not more than the limitation of the lithography (Gate resist sliming process).
Next, as shown in FIGS. 122A to 122C, the poly-silicon film 202 is etched by a reactive ion etching (RIE) method using the gate resist pattern 203′ as a mask. This process makes the gate pattern 204 having a gate electrode pattern section 204a formed over the element region 200a and a wiring pattern section 204b formed over the element isolation region 200b (Gate electrode working process).
Next, as shown in FIGS. 123A to 123C, the gate resist pattern 203′ is removed from the surface of the gate pattern 204 by O2 ashing method and the like (Resist removing process).
Thereby, it is possible to form the gate resist pattern 203′ having a pattern width that is not more than the limitation of the lithography resolution, and then possible to form the fine gate pattern 204 having a pattern width of not more than the limitation of the lithography resolution by performing the etching process for the poly-silicon film 202 as the gate electrode material film using the gate resist pattern 203′ as the mask.
After the above processes, although not shown, an impurity is doped into the surface of the silicon substrate 200 by using the gate electrode pattern section 204a as the mask in order to form the source and drain diffusion layer (designated by the dotted lines in FIG. 123B) of the MOS transistor. Following this process, the known layer insulation formation and wiring process are performed, and the MOS transistor fabrication process is thereby completed.
However, in the resist sliming process according to the related art described above, although a fine pattern of the gate electrode pattern section 204a corresponding to a line pattern can be formed, the space section in the wiring pattern section 204b is enlarged. Therefore it is necessary to relax the design rule for the space section when compared with the case not using the sliming process because the space section in the wiring pattern section 204b is enlarged by the execution of the sliming process. That is, as shown in FIGS. 124A and 124B, the dimension “t” (the distance of the adjacent gate patterns) in the space section in the wiring pattern 204b can be reduced to the dimension “t0” of the lithography resolution limitation when no sliming process is performed. But, when the sliming process is performed, the dimension “t0” can be relaxed to the dimension “t0+2t1” that is obtained by adding the dimension “t0” (as the dimension of the lithography resolution limitation) and the dimension “2t1” (as the sliming values of both sides). As a result, although the related sliming method has the effect to improve the performance of the operation speed of the MOS transistor because the fine gate electrode pattern in the MOS transistor can be formed, it has no effect to reduce a semiconductor chip area because the design rule of the space section in the wiring pattern section should be relaxed when compared with the normal lithography process using no sliming process.
FIG. 125 shows a gate pattern in a dynamic random access memory (DRAM) cell. In FIG. 125, the dotted lines show a resist pattern before the sliming process and the solid lines show a resist pattern after the sliming process. The memory cell section requires a fine pattern pitch in order to increase the integration. However, when the related art sliming process is applied to the memory cell section, a space pattern dimension P1 after the sliming process cannot be reached to the limitation of a space resolution in a lithography process. This means that the dimension P2 of the space pattern in the lithography process should be relaxed. As a result, the gate pattern pitch in the memory cell section is relaxed, so that there is a possibility to cause a drawback in which the chip area of a system LSI having relatively large-scale memory cells is expanded.
That is, the sliming process has various drawbacks because a pattern for which no sliming process is necessary is also slimmed by performing the sliming process. For example, in a case that both a fine line pattern and a narrow-width space pattern are obtained, when the line pattern is slimmed, the dimension of the narrow-width space pattern becomes also wide. Therefore it is necessary to set the dimension of the space pattern to a narrow dimension before performing this sliming process. This causes a difficulty to perform a lithography process.
As described above, although the sliming process to form a fine line pattern is well known, it is difficult to obtain a desired pattern dimension in the entire area of a same layer including various patterns, for example, a fine line pattern and a narrow space-width space pattern.
By the way, the related art also has following problems.
In a case to form a gate layer circuit pattern of a semiconductor device in which logic sections and memory sections are mixed using a combination of the exposure using an alternating phase shift mask and the resist sliming process for the logic gate section, it is necessary to performing following three exposure processes. In the first and second exposure processes as a double exposure process, the logic gate section is exposed by using the alternating phase shift mask and a trim mask in order to form the resist pattern, and the resist pattern is then slimed by the sliming process. After this process, in the third exposure process, both the memory cell section and the wiring section are exposed. This related art method must require those three exposure processes described above. That is, this related art method should perform the exposure processes of many times.
Further, with advancing semiconductor device miniatuarization, it becomes difficult to form a fine pattern of the semiconductor devices. In order to solve this problem, a lithography process uses a thin film resist having a thin thickness. When a thin-film resist is used, it is necessary to perform a highly selective etching for a target etching material in order to avoid occurrence to disappear the thin film resist having a thin thickness. In the highly selective etching the target etching material is etched while protecting the resist pattern from an etching gas by adhering reaction products generated by the etching onto the resist. Hence, the amount of reaction products greatly affects a process accuracy of the target etching material. Specifically speaking, the amount of reaction products becomes increase according to increasing an etching area. For this reason, when a line pattern and the like is formed, a line width in an area having a rough line pattern becomes large when compared with that in an area of a dense line pattern. That is, in the etching method of this type, a dimension of a line pattern is greatly changed according to the density of the pattern.
Furthermore, when a sliming process (to slim a resist pattern by etching) is performed for a resist pattern, the amount of the sliming is also changed according to the density of the pattern.