This invention relates, in general, to decode circuits, and more particularly to configurable decode circuits for compiler applications.
A compiler is a program which generates a layout and simulation model of a circuit based on parameters input by the user. For example, a user of a static ram (SRAM) compiler inputs such parameters as word width, memory size (number of bits needed), and block size. The compiler then generates all the needed files to simulate and fabricate the SRAM with other blocks that comprise the entire integrated circuit. The key to compilers is the flexibility afforded the user to tailor the compiled circuit such as the SRAM example for a specific circuit application. Time is also a factor, compilers are extremely fast and typically do not add significant time to the design cycle of an integrated circuit.
There are tradeoffs to creating a circuit compiler and using compiler generated circuits. Compilers are extremely complex programs at best, to alleviate problems in creating a compiler, many circuit designs are simplified or modified to lend themselves to a compilable format. Generally, a compiler generated circuit does not have the equivalent performance or density of a full custom designed circuit. This is especially true for memory compilers.
A fundamental component of any memory are the decode circuits. Memory architecture's are typically broken into memory rows, columns, and blocks. Decode circuits determine which row, column, and block is accessed to read or write to the appropriate memory bit or word. It is well known by those skilled in the art that nand and nor decoders have been widely used in memory compilers. Nand and nor decoders are not easily expandable or compilable for varying address widths. Multiple stages of decoding is inherent in the nand/nor decode architecture increasing program complexity. Nand and nor decoders have high capacitance per decode stage which loads clock driver circuits reducing performance. Performance of nand and nor decoders also decreases as the number of decoder inputs increase. It would be of great benefit if a decode circuit was developed which simplifies compiler complexity and increases decode performance.