This relates to shielding structures formed in the back end of integrated circuits.
A typical integrated circuit comprises a semiconductor substrate in and on which are defined a multitude of transistors and a series of metal interconnect layers on top of the substrate. The interconnect layers are insulated from one another by intermetallic dielectric layers. Interconnection paths are defined in the metallic layers and selective connections are made between the paths in the various layers so as to connect the transistors formed in the substrate to each other and to external connections. For additional information, see, for example, Plummer et al, Silicon VLSI Technology, ch. 11 (Prentice Hall, 2000); Doering et al (ed.), Handbook of Semiconductor Manufacturing Technology (2nd ed.) (CRC Press 2008).
In recent years, the frequencies of signals transmitted on some of the interconnection paths of an integrated circuit have risen into the GigaHertz (GHz) range. At these frequencies, it becomes desirable to shield the interconnection path; and shielding structures used for many years in conventional microwave technology have been adapted for use in integrated circuits. FIGS. 1A-1F depict cross-sections of several conventional shielding structures. In the transverse section of FIG. 1A, a microstrip 10 comprises a signal line 12 located above and insulated from a ground plane 14 that provides a current return path. In other embodiments, a pair of transmission lines may be used in place of a single signal line to provide differential-type signaling. When implemented in an integrated circuit, the signal line 12 is defined in one metallization layer, the ground plane 14 is defined in a second metallization layer and the signal line and ground plane are separated by at least one intermetallic dielectric layer. Illustratively, ground plane 14 may be a continuous two-dimensional sheet with no openings in it or may comprise a plurality of metal strips connected together at each end in a ladder-like configuration as shown in the horizontal section of FIG. 1B. Other patterns of connected metallization may also be used; and in some cases the ground plane can be the silicon substrate.
In the transverse section of FIG. 1C, a co-planar waveguide (CPW) 20 comprises a signal line 22 located between two ground planes 24, 25. When implemented in an integrated circuit, the signal line and ground planes of the coplanar waveguide are all implemented in the same metallization layer and insulated from the substrate of the integrated circuit by at least one intermetallic dielectric layer. Again, each ground plane may be a continuous two-dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG. 1B. Other patterns of connected metallization may also be used.
In the transverse section of FIG. 1D, a grounded co-planar waveguide (GCPW) 30 comprises a signal line 32 located between two ground planes 34, 35 and above a third ground plane 36. The ground planes 34, 35 are electrically connected to ground plane 36 by electrically conductive sidewalls 38, 39. When implemented in an integrated circuit, signal line 32 and ground planes 34, 35 are defined in a first metallization layer, ground plane 36 is defined in a second metallization layer beneath the first layer, and the first and second metallization layers are separated by at least one intermetallic dielectric layer. Illustratively, ground plane 36 may be a continuous two-dimensional sheet with no openings or it may comprise a ladder-like array of connected strips as shown in FIG. 1B or another pattern of connected metallization. The sidewalls are formed using stacks of vias that extend between the upper and lower metallization layers. As shown in the lateral section of FIG. 1E, a first plurality of electrically conducting via stacks 138 form a sidewall that connects upper ground plane 34 to lower ground plane 36 and a second plurality of electrically conducting via stacks similar to that of FIG. 1E forms a sidewall that connects upper ground plane 35 to lower ground plane 36. Additional rows of electrically conducting vias may be connected in parallel to connect the upper and lower ground planes.
In the transverse section of FIG. 1F, a stripline 50 comprises a signal line 52 located between an upper ground plane 54 and a lower ground plane 56. Optionally, the upper and lower ground planes are electrically connected by electrically conductive sidewalls 58, 59 so that the signal line is in the center of the region enclosed by the ground planes and sidewalls. When stripline 50 is implemented in an integrated circuit, signal line 52 is defined in one metallization layer, ground plane 54 is defined in a second metallization layer above it and ground plane 56 is defined in a third metallization layer below it. Optionally, a first plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on one side of the signal line 52; and a second plurality of electrically conducting vias form a sidewall that connects upper ground plane 54 to lower ground plane 56 on the other side of signal line 52. Again, the ground planes may be continuous two-dimensional sheets with no openings or ladder-like arrays of connected strips as shown in FIG. 1B or some other pattern of connected metallization; and the vias may be similar to those shown in FIG. 1E. The advantages and disadvantages of several types of integrated circuit transmission lines are discussed, for example, at S. Pellerano et al., “A 64 GHz LNA with 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS,” IEEE J. of Solid-State Circuits, Vol. 43, No. 7. pp. 1543-52 (July 2008)