Field programmable gate arrays (FPGAs) can be programmed to implement large electronic systems. The complexity of such large electronic systems often requires the use of electronic design software such as Electronic Design Automation (EDA) tools to create, define, and verify a system design that is then programmed or implemented on a FPGA or other physical programmable target device.
In order to use an EDA design tool to design such a system on a target device such as an FPGA, a user or a system designer typically first defines, specifies, or models the system design (or user design) in a hardware description language (HDL) such as VHDL (Very high speed integrated circuit HDL) or Verilog. The system design is then entered into the EDA design tool. The EDA design tool then performs computer aided design (CAD) validation and/or verification processes or flows to realize the system design on the target device. Among the procedures performed by EDA tools in a CAD flow are logic and physical synthesis, technology mapping, clustering, placement, and routing.
The system design of the electronic system can also be specified with speed or frequency requirements. For example, a user can specify that the system design is for a memory controller with a maximum clock speed or frequency of 300 MHz while another user can specify the system design is for a memory controller operating at a maximum clock speed or frequency of 160 MHz. To increase the operation speed of the system design to reach the required frequency or speed, pipelining can be employed or introduced into the system design. To do so, the designer can insert pipeline registers into the system design along data paths to obtain more parallel operations.
However, pipeline registers also introduce latency. When a larger number of pipeline registers are used in a system design, a relatively large latency is introduced. One prior art approach of reducing latency is to manually adjust the amount of latency at various stages or places of the system design.
This prior art solution can be difficult, tedious, and time consuming. First, it is very difficult to determine the best locations in the system design to insert new pipeline registers or to remove existing pipeline registers because most user designs have complex control loops which are difficult to pipeline. Secondly, to obtain the best performance/speed and latency tradeoff, the user or human designer needs to repeatedly re-write the system design to explore various pipeline options in the system design. This is both tedious and time consuming. Also, this re-writing approach requires significant effort to develop and verify HDL design changes. Thirdly, modifying pipelining in multiple components within the system design may introduce logic error to the system design or cause undesired functional changes to the system design, and require additional functional verification effort.