Japanese patent application No.2000-98918, filed on Mar. 31, 2000, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a differential amplifier having two sets of differential amplifying circuits, a semiconductor device, a power supply circuit, and electronic equipment using the same.
2. Background
A known differential amplifier is shown in FIG. 7, which device has two, first and second differential amplifier circuits 200, 210. The first and second differential amplifier circuits 200, 210 are designed to receive first and second input voltages VIN1, VIN2 with an offset therebetween as set at a resistive voltage divider circuit 220. A P-type MOS transistor 202 is provided at the rear stage of the first differential amplifier circuit 200, which transistor is driven by a first signal S1 coming from the first differential amplifier circuit 200. Similarly an N-type MOS transistor 212 is provided at the rear stage of the second differential amplifier circuit 210, which transistor is driven by a second signal S2 from the second differential amplifier circuit 210. These PMOS transistor 202 and NMOS transistor 212 are operable to pull together thus defining an output voltage VOUT.
In this way, in the above mentioned differential amplifier, a specified output voltage VOUT is generated and issued by providing the offset to input voltages.
A differential amplifier as one embodiment comprises:
a first differential amplifier circuit having a first differential pair and operating based on a common input voltage; and
a second differential amplifier circuit having a second differential pair and operating based on the common input voltage,
wherein at least one of the first differential pair and the second differential pair is formed from a pair of transistors having a driving ability difference therebetween.