1. Field of the Invention
The present invention relates to improvement of a mixer circuit used in a receiver in digital radio communication system, in particular, relates to such a circuit which is excellent in image rejection.
2. Description of the Related Art
FIG. 6 shows in general an image rejection mixer circuit, in which a received RF (radio frequency) signal is applied to a pair of multipliers 61 and 62, each of which receives further, a local signal LO, directly or through a 90° phase shifter 63, so that a product of RF and LO is obtained. Then, each multiplier provides a pair of output frequencies FRF+FLO and FRF−FLO, where the former is an undesired frequency and the latter is a desired IF frequency. A product of each of the multipliers is applied to a low pass filter 64, 65, so that a pair of IF signals having a phase difference of 90° are obtained. Then, two IF signals are added in an adder 67 after one of the IF signals is shifted by 90° in a phase shifter 66, so that image rejection is carried out.
In a conventional image rejection mixer, a pair of multipliers and a 90° phase shifter are used, as shown in FIG. 6.
However, a prior art mixer shown in FIG. 6 has a disadvantage in that an image rejection in the GHz band is not enough as a 90° phase shifter with excellent performance in GHz band is difficult.
FIG. 7 is a conventional Gilbert-cell mixer, in which a radio frequency signal RF is applied to a pair of input transistors 71 and 72 located in a lower position in the figure. Therefore, an output signal amplitude of a Gilbert-cell type circuit depends upon a gain of input transistors 71 and 72.
In a conventional image rejection mixer circuit, an image rejection ratio (IRR) would be degraded if two IF signals (inphase component, and quadrature component) have an amplitude error between two components or a phase error from 90° between two components, and the IRR is expressed as follows (described in RF Microelectronics, Rehzad Razavi, Prentice Hall PTR, page 143).IRR≈{(ΔAIF/AIF)2+(ΔθIF)2}/4  (1) 
One of the causes of an IF signal error is an error or a dispersion of mixer circuits. For instance, if two mixer circuits have an error of 2% in amplitude with each other, IRR would be degraded by approximate 40 dB.
FIG. 8 is a prior quadrature mixer circuit which reduces affection by an amplitude error of a mixer circuit (International Conference ISSCC93-TP9.4). The circuit of FIG. 8 has two Gilbert-cell mixers of FIG. 7, and the sources of the RF signal input transistors 81, 82, 83 and 84 are coupled together with each other. The circuit shown in FIG. 8 receives a pair of local signals LO-I and LO-Q having quadrature relation, and an RF signal in balance form or differential form, and provides a pair of IF signals IF-I and IF-Q having quadrature relation, where -I means inphase component, and -Q means quadrature component.
However, the circuit of FIG. 8 has the disadvantage that amplitude error exists between IF-I and IF-Q, because RF signal input transistors have an error in gain between 81 and 82, and between 83 and 84. As a differential pair for mixing inphase component LO-I of a local signal with an RF signal is supplied an RF signal through the transistor 81, while a differential pair for mixing a quadrature component LO-Q of a local signal with an RF signal is supplied an RF signal through the transistor 82, the difference of the gain of the transistors 81 and 82 causes an error of amplitude of an output IF signal between the inphase component and the quadrature component.
FIG. 9 is the improvement of FIG. 8 for removing amplitude error between IF-I and IF-Q, by feeding an RF input signal to both differential pairs for inphase component and quadrature component by using a common differential pair (91 and 92).
However, the circuit of FIG. 9 has a disadvantage in that phase error of output IF signals is larger than phase error of local signals (LO-I, LO-Q), when a pair of local signals (LO-I, LO-Q) have phase error (ΔθLO:radian) from 90°. For instance, when a FIG. 9 circuit is constituted by using a CMOS having gate length 0.2 μm, the following result is obtained in the circuit simulation using HSPICE.ΔθIF≈1.4ΔθLO 
Thus, the FIG. 9 circuit is worse by approximately 3 dB in IF signal phase error as compared with the FIG. 8 circuit in which (ΔθIF=ΔθLO).
The reason why the phase error of an output signal is large in FIG. 9 is that a bias potential of a differential pair 2 for mixing a local signal with an RF signal cannot be independent from a bias potential of a transistor of a differential amplifier for an input RF signal. A bias potential of a differential pair affects much to phase of an output IF signal. In FIG. 9, transistors 91 and 92 of a differential amplifier are biased through a resistor connected to a gate of each transistor, and a bias transistor 93, which is used in the Gilbert-cell mixer of FIG. 7. The transistors of differential pairs 2 are biased through a resistor connected to a gate of each transistor, and a bias current in the differential amplifier 91, 92. In other words, bias current in the differential amplifier 91, 92 affects the bias current in the differential pairs 2. Therefore, it is impossible to bias the differential pairs 2 to the optimum bias potential to obtain the minimum phase error of an output IF signal.