Field of the Invention
The invention relates to an integrated dynamic memory with cells and a control circuit for controlling a refresh mode of the cells, in which the memory cells undergo a content refreshing process with a refresh frequency.
In general, an integrated dynamic memory in the form of a DRAM contains a cell field that includes word lines and bit lines. The memory cells are disposed at intersections of the bit lines and word lines. The cells can be constructed from a storage capacitor and a selection transistor, whereby the selection transistor connects the respective storage capacitor to one of the bit lines. Control terminals of the respective selection transistors are connected to each of the word lines, respectively, for purposes of cell selection. An active word line switches connected selection transistors to conduct. After the relevant word line has been selected, data signals of the memory cells along the selected word line occur at the corresponding bit lines. A data signal of a selected memory cell is evaluated and amplified in a read amplifier of the memory cell field. In a read access operation, the data signals of selected memory cells are read out for further processing; in a write operation, data signals are written into the selected memory cells.
In integrated dynamic memories in the form of DRAMs, what is known as a refresh mode is required at operating times at which the memory is not being accessed from outside, so that the memory cell contents, which can volatilize owing to leakage currents of the storage capacitor or selection transistor, are refreshed and therefore held long-term. In the refresh mode, the evaluated and amplified data signals of selected memory cells are written back directly into the relevant memory cells. This is generally controlled by a control circuit, which also specifies a refresh frequency with which a respective refreshing of memory cell contents is carried out.
The maximum achievable hold time of the contents of a memory cell (known as retention time) is decisive for determining the length of time required between two refresh cycles. The refresh frequency can be selected lower, the longer the maximum achievable retention time of the contents of a cell is, that is to say, the longer the period between two refresh cycles can be. Above all in a standby mode of an integrated dynamic memory, the power consumption is largely determined by the refresh mode. The power consumption of the memory rises as the refresh frequency increases.
It is accordingly an object of the invention to provide an integrated dynamic memory with a control circuit for controlling a refresh mode of memory cells, and a method for driving the memory that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the power consumption, particularly in a standby mode of the memory, can be optimized.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated dynamic memory. The memory contains memory cells, a control circuit for controlling a refresh mode of the memory cells in which the memory cells undergo a refreshing of their contents with a refresh frequency, and a controllable frequency generator for setting the refresh frequency with an aid of a reference value. The controllable frequency generator has a control input from which the refresh frequency can be modified, and an output connected to the control circuit. A temperature sensor circuit is provided for detecting a temperature of the integrated dynamic memory and outputs a first reference value which is received by the controllable frequency generator. An externally writable circuit is provided and outputs a second reference value that is received by the controllable frequency generator. The temperature sensor circuit and the externally writable circuit are alternatively coupled to the control input of the controllable frequency generator for setting the refresh frequency.
Besides having a control circuit for controlling a refresh mode of the memory cells, the inventive integrated dynamic memory includes a controllable frequency generator for setting the refresh frequency with the aid of a reference value. The frequency generator contains a control input by way of which the refresh frequency can be modified. An output of the frequency generator is connected to the control circuit. The inventive memory further contains a temperature sensor circuit for detecting a temperature of the memory and outputting a first reference value, which can be externally written, as well as a circuit for outputting a second reference value. The temperature sensor circuit and the externally writable circuit, namely in the form of a register circuit, are alternatively connectible to the control input of the frequency generator for setting the refresh frequency.
The inventive integrated dynamic memory is able to take into account that the retention time of the contents of the memory cells decreases as the temperature rises, because the leakage currents, which occur in the memory cells, of the storage capacitor and/or the respective selection transistor increase with rising temperatures. This can be taken into account for controlling the refresh mode of the memory cells by setting the refresh frequency in dependence on the temperature with the aid of the temperature sensor circuit or the externally writable circuit. It is possible to utilize the temperature of the memory itself, which is detected by the temperature sensor circuit, as a reference value for adjustment or to utilize an externally determined temperature, which can correspond to a system temperature and can be externally programmed in a register circuit in the form of a reference value. A temperature sensor in a system such as a mobile radiotelephone is usually more accurate than a sensor that is implemented on the memory chip.
In either case, the power consumption of the memory in the standby mode can be optimized and reduced at low temperatures to a fraction of the power demanded at higher temperatures. At lower temperatures, the selected refresh frequency is correspondingly lower. When the temperature of the memory or system rises during operation, the refresh frequency is increased by the frequency generator.
According to the inventive method for driving the memory, if the externally writable circuit is written, the second reference value is fed to the control input of the frequency generator. A reference value, i.e. temperature value, which is supplied by a connected system or user is thus utilized for setting the refresh frequency. Otherwise, the first reference value of the temperature sensor circuit is fed to the control input of the frequency generator. The refresh frequency is then controlled in dependence on the memory temperature.
As an expansion hereof, the externally programmed reference value can be utilized as soon as a reference value has been written into the externally writable circuit in the form of a register circuit. In this case, the second reference value is fed to the control input of the frequency generator as soon as the register circuit has been programmed.
With the invention, users of the memory module which are unable to measure temperature and therefore unable to program the register circuit can still optimize the required power consumption for a standby mode and reduce it at low temperatures.
In an embodiment of the inventive integrated dynamic memory, the frequency generator contains an oscillator for sending a signal with a regular frequency and, connected on load side, a programmable frequency divider for dividing the frequency of the signal of the oscillator. One output of the frequency divider is connected to the output of the frequency generator. The oscillator sends a signal with a temperature-independent and regular frequency. The oscillator frequency is divided by a downstream frequency divider down to the value that is required for the refresh frequency. The frequency divider is programmed therein by the temperature sensor circuit by way of the control input. Combining a temperature-independent oscillator with the programmable frequency divider makes it possible to set the refresh frequency as a function of the memory temperature with high precision.
In a development of the invention, the temperature sensor circuit contains a temperature sensor and, connected on a load side, an analog-digital converter for programming the frequency divider. In an embodiment, the temperature sensor contains a diode, and the temperature is detected by tapping a voltage at the diode.
In accordance with an added feature of the invention, the externally writable circuit is a register circuit. A switching unit is provided and has two inputs and one output. A first of the two inputs is connected to the temperature sensor circuit, and a second of the two inputs is connected to the register circuit. The output of the switching unit is connected to the control input of the controllable frequency generator. A check circuit is connected to and checks contents of the register circuit and further connected to and drives the switching unit in dependence on a check result.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated dynamic memory with a control circuit for controlling a refresh mode of memory cells, and a method for driving the memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.