1. Field of the Invention
The present invention relates to a metallization method for manufacturing integrated circuits. More particularly, the present invention relates to selective metallization of an interconnect in insulative layers to form void-free plugs between conducting layers, including apertures such as contacts or vias in high aspect ratio sub-half micron applications.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, troughs and other features. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, must decrease. Therefore, there is a great amount of ongoing effort being directed at the formation of smaller and smaller void-free features. One such method involves selective chemical vapor deposition (CVD) of material only on exposed nucleation surfaces as provided on the substrate surface. Selective CVD involves the deposition of a film layer when a precursor gas contacts a "nucleation site" on the substrate. The precursor gas decomposes (reacts) at nucleation sites, deposits a metal layer on which further deposition occurs, and forms various gaseous by-products that are exhausted from the chamber.
Selective CVD Al deposition is based on the fact that the decomposition of a CVD Al precursor gas usually requires a source of electrons from a conductive nucleation film. In accordance with a conventional selective CVD Al deposition process, Al should grow on the surface of an underlying conductive layer, such as a metal film, doped silicon or metal silicide, that has been exposed in the bottom of an aperture. Conversely, Al should not grow on dielectric surfaces such as the dielectric field and aperture walls. Because the underlying conductive layers supply electrons needed for decomposition of the Al precursor gas, but the dielectric field and aperture walls do not, the resulting deposition of Al is said to be "selective". Selective deposition can provide epitaxial, "bottom-up" growth of CVD Al in the apertures that is capable of filling very small dimension (&lt;0.25 .mu.m), high aspect ratio (&gt;5:1) via or contact openings.
Referring to FIG. 1, a schematic diagram of an integrated circuit structure 10 shows a metal interconnect formed in via 14 that was selectively nucleated by the conducting member 18 and uniformly grown upward towards the surface 19 of the dielectric layer 16. However, selective deposition can also occur at the location of surface defects that are almost always present on the dielectric field and aperture sidewalls. These defects can provide free electrons and thus serve as nucleation sites for CVD Al growth that forms unwanted CVD Al nodules 12 on the surface 19 and the walls of the apertures.
Various methods have been used to minimize this loss of selectivity and the formation of nodules. These methods have included, for example, preconditioning of the dielectric surface before the selective deposition process and planarization of the device, such as by chemical mechanical polishing (CMP), following selective deposition to remove the nodules 12 formed on the wafer surface 20. However, these methods complicate the processing steps required to form the desired circuit structures and significantly increase the expense of the integrated circuit manufacturing process. In addition, adding steps to the overall process increases the likelihood that defects may result in the circuit structures being formed.
Furthermore, aluminum plugs and interconnects have been found to exhibit electromigration or transport of aluminum atoms due to current flow, resulting in voids and line failure. Electromigration is a problem that gets worse as the level of integration increases and the effects of electromigration appear only after a period of use.
One method for reducing electromigration in integrated circuits is it to use copper and its alloys which have even lower resistivities than aluminum and significantly higher electromigration resistance. These characteristics are important for supporting higher current densities, such as those experienced at high levels of integration. However, the primary problem with integrating copper metal into multilevel metallization systems is the difficulty of patterning the metal using etch techniques. For devices of submicron minimum feature size, wet etch techniques for copper patterning have not been acceptable due to liquid surface tension, isotropic etch profile, and difficulty in over-etch control. Furthermore, a reliable process for selective CVD copper is not available.
It has been known that the electromigration performance of aluminum can be dramatically improved by forming a barrier or capping layer between aluminum features. However, the presence of CVD Al nodules on the dielectric field following selective CVD Al plug formation prevents the direct deposition of a smooth, uniform and continuous capping. Presently, chemical mechanical polishing must be used to remove the selective CVD Al nodules before the capping layer can be deposited. This expensive and complex process involves several additional steps, including a break in the process vacuum causing unnecessary contamination of the substrate surface.
Therefore, there remains a need for a simple method for forming a selective CVD Al via/contact plug and an PVD Al interconnect having a smooth, continuous and uniform capping layer therebetween. More particularly, there is a need for a method providing an integrated plug/interconnect metallization with improved electromigration performance. It would be desirable if this method did not require chemical mechanical polishing (CMP). It would also be desirable if the method was simple and could be performed entirely within an integrated cluster tool. It would be even more desirable if the method provided a low temperature deposition for sub-quarter micron Al plug fill.