The present invention is related to the field of binary counters. In particular, the present invention is directed to a method and apparatus for quickly and fully testing a multi-stage binary counter.
Many applications of digital logic design require the use of relatively high resolution M-bit binary counters. In some cases, the high resolution M-bit binary counter is implemented by coupling several smaller resolution N-bit counters together in several stages, in which N is equal to M divided by the number of stages. For example, a sixteen-bit resolution binary counter can be implemented by coupling four four-bit binary counters together. In such a configuration, the carry output signal (COUT) from each counter is coupled to the carry input (CIN) of counter in the next stage.
It is generally desirable to fully test the operation of the binary counter at some stage regardless of the particular application in which the binary counter is employed. Testing of an M-bit binary countdown counter can be performed, for example, by loading the counter with all logical ones, fully decrementing the counter 2.sup.M times, and then checking to see if the output of the counter is zero. The above-described testing method, however, requires an unacceptable amount of time for many digital logic applications, as the counter must always be decremented 2.sup.M times to fully test its operation.
In the case of a multi-stage counter, the testing time can be reduced by decoupling the stages and testing each stage simultaneously. For example in the sixteen-bit counter mentioned above, the four four-bit counters can be tested simultaneously by decoupling the stages with a switching mechanism, decrementing each stage 2.sup.4 times, and checking the output signal from each stage. The problem with this testing approach is that decoupling the stages requires that the carry outputs and carry inputs be disconnected between stages to permit independent operation of the counters, which would prevent the carry propagation between the four counters from being tested. Thus, overall counter operation cannot be fully tested.