The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source (S), gate (G) and drain (D). In the FET a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and the drain (D). In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 schematically illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is the “channel”. A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded, or it may be biased at a desired voltage, depending on applications.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors may be used, and are often paired with one another.
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several IC chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching. After all the chips are formed, they can be singulated from the wafer.
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As schematically illustrated in FIG. 2, floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described herein below.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor; the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate. Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”). Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate, are described herein below.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described herein below.
Normally, a floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored (or trapped) in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around, as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 schematically illustrates a basic NROM memory cell, which may be viewed as an FET with an “ONO” structure inserted between the gate and the substrate. (One might say that the ONO structure is “substituted” for the gate oxide of the FET). The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed herein below), and a channel region 320 defined in the substrate 312 between the two diffusion regions 314 and 316, and a gate 328 disposed above the ONO stack 321.        
In FIG. 3, the diffusions are labeled “N+”. This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is a p-type cell well (CW) doped with boron (or indium or both). This is the normal “polarity” for an NVM cell employing electron injection (but which may also employ hole injection, such as for erase). With opposite polarity (boron or indium implants in an n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around; they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer 324 of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide 322 and 326. Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
Memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.) Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2).
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Modes of Operation
Generally, the modes of operation for any NVM memory cell (either floating gate, SONOS, TANOS, NROM or other) include “program”, “erase” and “read”. Modes of operation for NROM are now discussed.
Program generally involves injecting electrons into the charge storage areas of the NROM cell, typically by a process known as channel hot electron (CHE) injection.
Exemplary voltages to program (by CHE injection of electrons) the right bit (right bit storage area) of an NROM cell,                The left BL (acting as source, Vs) is set to 0 volts        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to +8-10 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the drain (right BL) becomes programmed. To program the left bit storage area, source and drain are reversed—the left bitline serves as the drain, and the right bitline serves as the source.        
Erase may involve injecting holes into the charge storage areas of the NROM cell, typically by a process known as hot hole injection (HHI). Generally, holes cancel out electrons (they are electrically opposite), on a one-to-one basis. Exemplary voltages to erase (by HHI injection of holes) the right bit of the NROM cell,                the left BL (acting as source, Vs) is set to float        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to −7 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the drain (right BL) becomes erased. To erase the left bit storage area, source and drain are reversed—the left bitline serves as the drain and the right bitline serves as the source.        
Read may involve applying voltages to the terminals of the memory cell and, based on subsequent current flow, ascertaining the threshold voltage of the charge storage area within the cell. Generally, to read the right bit of the NROM cell, using “reverse read”,                the right BL (acting as source, Vs) is set to 0 volts        the left BL (acting as drain, Vd) is set to +2 volts        the gate (Vg) is set to +5 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the source (right BL) can be read. To read the left bit storage area, source and drain are reversed—the left bitline serves as the source, and the right bitline serves as the drain.“Reading” an NROM Cell, Generally        
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction, and reading is performed in what is termed the opposite or reverse direction. For example, to program the right storage area 323 (in other words, to program the right “bit”), electrons generally flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right “bit”), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 321 (in other words, to program the left “bit”), electrons flow from right (source) to left (drain). To read the left storage area 321 (in other words, to read the left “bit”), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, U.S. Pat. No. 6,768,165.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom). As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 4A schematically illustrates an array of NROM memory cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL (n), its source (left hand diffusion) is connected to BL (n), and its drain (right hand diffusion) is connected to BL (n+1). The nine memory cells illustrated in FIG. 4A are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example, that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL (n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL (n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL (n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
Operating Flash Memory
Flash is a non-volatile memory that can retain the data stored therein even after power is removed. NAND Flash, which is one type of Flash, is high-density design and has certain advantages over other types of memory, including a large storage capacity (such as one giga-bits or more), good speed for continued access, and low cost. However, NAND Flash also has several inherent drawbacks, including poor performance for random access and increased susceptibility to bit errors over the NAND Flash's operating lifetime. In particular, NAND Flash is typically accessed in units of pages, one page at a time, with each page being of a particular size (for example, 512 bytes).
Because the structure of NAND Flash is not suitable for random access, program codes cannot be executed directly from the NAND Flash. Instead, Static Random Access Memory (SRAM) or NOR Flash may be used as an intermediate storage for data and program codes that need to be accessed in a random manner by the processor. A memory architecture that incorporates both SRAM and NAND Flash or NOR and NAND Flash (with or without SRAM) may thus provide large storage capacity, reduced cost, and random access.
Conventionally, reading data from or writing data into NAND Flash requires excessive involvement and control by the processor. This can tie up the processor and prevent it from performing other functions, which can then result in overall performance degradation for the communication device. Moreover, since NAND Flash is more prone to bit errors, a mechanism is needed to ensure data integrity when loading data from or into the NAND Flash. As described in U.S. Pat. No. 6,967,896, a user wishing to write data to an NVM array may typically write the data to a cache memory, such as but not limited to, a static random access memory (SRAM). The cache memory routes or “addresses” the data to the appropriate bits in the NVM array. The data may be written to the SRAM in a byte granularity.
In a manner similar to NVM, SRAM may also be arranged in an array—for example, an N×n array of 1-bit cells, where:                n=byte width (such as 8, 16, 32 . . . )        N=number of bytesGenerally, m address bits may be divided into x row bits and y column bits (x+y=m). Address bits may be encoded such that 2m=N and the array may be organized with both vertical and horizontal stacks of bytes.An example of a typical SRAM addressing scheme is shown in the following table.        
ColumnsRowsC0C1C2C3R0Address = 0Address = 1Address = 2Address = 3Data = x0Data = x1Data = x2Data = x3R1Address = 4Address = 5Address = 6Address = 7Data = x4Data = x5Data = x6Data = x7R2Address = 8Address = 9Address = 10Address = 11Data = x8Data = x9Data = x10Data = x11R3Address = 12Address = 13Address = 14Address = 15Data = x12Data = x13Data = x14Data = x15
FIG. 4B schematically illustrates, in a general manner, the concept that data is “buffered” in cache memory (such as SRAM) prior to being written to an NVM array (such as the NROM array shown in FIG. 4A) and when being read from the NVM array. The data may be in the form of a data stream which is accumulated by the SRAM into blocks, prior to writing to the NVM array. The SRAM may also serialize chunks of data which are read from the NVM array. The cache memory may be on the same chip as the NVM array.
More on Reading The State Of The Memory Cells
A memory cell may be programmed to different states, or program levels, determined by a threshold voltage (Vt) of the cell. For a single level cell (SLC), there are two program levels, generally “erase” and “program”. For a multi-level cell (MLC) there are more than two program levels. An NVM cell's state may be defined and determined by its threshold voltage (Vt), the voltage at which the cell begins to conduct current. An NVM cell's threshold voltage level is usually correlated to the amount of charge stored in a charge storage region of the cell. Different threshold voltage ranges are associated with different states or program levels of an NVM cell.
Generally, in order to determine the state (program level) of an NVM cell, the cell's threshold level may be compared to that of a reference structure or cell whose threshold level is set, or otherwise known to be, at a voltage level associated with the specific state being tested for. Comparing the threshold voltage of an NVM cell to that of a reference cell is often accomplished using a sense amplifier or similar circuit. Various techniques for comparing an NVM cell's threshold voltage against those of one or more reference cells or structures, in order to determine the NVM cell's state, are well known.
When reading a NVM cell, to determine whether it is at a particular state, the cell's threshold voltage may be compared against that of a reference cell having a reference threshold voltage defined as a “read” level for the specific state. A “read” level is usually set lower than a program verify (PV) level and higher than an erase verify (EV) level in order to compensate for voltage drifts which may occur during operation.
In a “binary” or single level cell (SLC) capable of storing only one bit of information (a logic 1 or a logic 0), only a single read verify (RV) voltage is required, and it may be between the erase verify (EV) and program verify (PV) voltages for the cell. “Read” is generally done by measuring the Vt of a cell (or half-cell), and associating the measured Vt with a program level (such as “0” or “1”). Although the Vt's of the cells are measured on an individual basis, it is generally necessary to determine a distribution of Vt's for many cells in order to associate the measured Vt of a given cell with a program level, with confidence. For example—if only one cell were to be read, and its threshold voltage were to be found to be at or very near a Read Verify (RV) voltage between two program levels, it may be difficult to say, with certainty, at which of two program levels the single cell was programmed, since its threshold voltage may have moved slightly upward or slightly downward since it was programmed. This is a benefit of reading bits one block at a time—to obtain a statistically meaningful sample of Vt's across a number of cells.
FIG. 5A is a graph schematically illustrating two states of a “binary” or single level cell (SLC) capable of storing one bit of information per cell (or per charge trapping area with an NROM cell), and utilizes only one read verify threshold (RV). Generally, the two states are erased (represented by “1”) and programmed (represented by “0”). The horizontal axis is threshold voltage (Vt), increasing from left to right. Three voltage levels are illustrated in FIG. 5A, these are EV (erase verify), RV (read verify) and PV (program verify). As illustrated, EV is less than RV, which is less than PV. A high Vt may represent a program state of binary “0”, and a low Vt may represent an erase state of binary “1”. The binary designations are arbitrary, and may be reversed (high Vt=“1”, low Vt=“0”).
FIG. 5A is generalized, and is applicable to a typical floating gate NVM memory cell or a given charge storage area of an NROM cell. The curves represent the threshold voltages (Vts) for a number of cells at the given program level. Typically, there is a distribution, or spread, about a nominal (or average, or center) value. For example,                the center value for “1” equals approximately 3.5 volts        the center value for “0” equals approximately 6.0 volts        EV equals approximately 4.0 volts        RV equals approximately 4.5 volts        PV equals approximately 5.5 volts        
FIG. 5B schematically illustrates a situation wherein there are four possible MLC program levels (or states) 11, 01, 00, 10 for each memory cell (or, in the case of NROM, for each storage area of the memory cell). As illustrated, the program level 11 has the lowest Vt, the program level 01 has a higher Vt, the program level 00 has a yet higher Vt, and the program level 10 has a yet higher Vt. The program level 11 may be erase (ERS), which for purposes of this discussion is considered to be a program level, although it is not generally regarded as such.
There are a number of memory cells (or storage area NROM cells) being programmed, erased and read. In a given array, or on a given memory chip, there may be many millions of memory cells. Programming may typically be performed in blocks of thousands of memory cells. The different blocks of memory cells are typically located at different logical positions within the array, and at different physical positions on the chip. During (or before) programming, a check sum indicative of the number of cells programmed to each level may be stored in the block, in the array, on the chip, or external to the chip.
At each program level (and this is also true for the SLC cell of FIG. 5A), there is typically a distribution of threshold voltages within a range (a statistical spread). In other words, for a given program level, the threshold voltage is not likely to be exactly a unique, precise voltage for all of the memory cells being programmed to that level. Initially, in the act of programming the cell, the voltage may be off a bit, for example, as a result of the state of neighboring cells (or the other charge storage area in the same NROM cell), or, as a result of previous program or erase operations on the same cell, or neighboring cells, or, as a result of a variety of other factors. After programming, the threshold voltage of a cell may change, as a result of programming neighboring cells (or the other charge storage area in the same NROM cell), or a variety of other factors.
Therefore, the threshold voltage (Vt) for a given program level may be more than average in some cells, in others it may be less than average. Nevertheless, in a properly functioning group of cells (such as a block, or an array), there should be a clear distribution of four distinct program levels, such as illustrated. The distributions of Vt for each of the program levels should be separated enough from one another so that read positions (RV voltage levels) can be established between adjacent distributions of threshold voltages, such as the following:
RV01 is between EV and PV01, or higher than the highest expected Vt for a cell at state “11” and lower than the lowest expected Vt for a cell at state “01”;
RV00 is between PV01 and PV00, or higher than the highest expected Vt for a cell at state “01” and lower than the lowest expected Vt for a cell at state “00”; and
RV 10 is between PV00 and PV10, or higher than the highest expected Vt for a cell at state “00” and lower than the lowest expected Vt for a cell at state “10”.
For example,
                the center value for “11” equals approximately 4.0 volts        the center value for “01” equals approximately 4.4 volts        the center value for “00” equals approximately 4.8 volts        the center value for “10” equals approximately 5.4 volts        EV equals approximately 4.0 volts        RV01 equals approximately 4.4 volts        PV01 equals approximately 4.8 volts        RV00 equals approximately 5.4 volts        PV00 equals approximately 5.6 volts        RV10 equals approximately 6.0 volts        PV10 equals approximately 6.3 voltsAn Aside About Binary Notation, and the Labeling of Program Levels        
“Binary” generally means “two”. In binary notation, there are only two possible digits, usually referred to as “1” and “0”. Many 1s and 0s can be strung together to represent larger numbers, for example:                0000 is zero        0001 is one        0010 is two        0011 is three        0100 is four        1000 is eight        1010 is ten        
In the examples above, the binary numbers have four digits each—four “places”. For purposes of this disclosure, only two digits will be used. Two digits can represent four numbers. Counting (in binary) typically starts with zero, and counting from zero to three proceeds like this: 00 (zero), 01 (one), 10 (two), 11 (three). Notice, in the transition from 01 (one) to 10 (two), both bits change.
Since it is arbitrary which program levels represent which digits, notice in FIG. 5B that the program levels appear to be out of sequence, starting with 11 (three), then 01 (one), then 00 (zero), then 10 (two). This sequence is common, so that when moving from one program level to the next higher level, both bits do not change—as is the case with the transition from 01 (one) to 10 (two). In FIG. 5B it can be seen that when moving from one program level to another, only one of the bits changes.