Reference is now made to FIGS. 1A and 1B showing the general configuration of a conventional metal oxide semiconductor (MOS) field effect transistor (FET) 10 device. FIGS. 1A and 1B are parallel cross-sections taken at different locations along the width of the transistor gate in a direction perpendicular to the gate width. A substrate 12 supports the transistor. In this example, the substrate is of the silicon-on-insulator substrate 12 type which includes a substrate layer 14, a buried oxide (BOX) layer 16 and a semiconductor layer 18. An active region 20 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 22 that penetrates through the layer 18. Within the active region 20, the layer 18 is divided into a plurality of channel regions 30 which have been doped with a first conductivity type dopant, a plurality of source regions 32 (each adjacent a channel region 30 on one side) which have been doped with a second conductivity type dopant, and a plurality of drain regions 34 (each adjacent a channel region 30 on an opposite side from the source region 32) which have also been doped with the second conductivity type dopant. Where the MOSFET 10 device is of the p-channel type, the first conductivity type dopant is n-type and the second conductivity type is p-type. Conversely, where the MOSFET device is of the n-channel type, the first conductivity type dopant is p-type and the second conductivity type is n-type. A plurality of gate stacks 36 are provided above the channel region 30. Each gate stack 36 typically comprises a gate dielectric 38, a gate electrode 40 (for example, of metal and/or polysilicon material) and sidewall spacers 42 made of an insulating material such as silicon nitride (SiN) deposited on the sides of the gate dielectric 38 and gate electrode 40 and on top of the gate electrode. An interlevel dielectric (ILD) or pre-metallization dielectric (PMD) layer 46 is provided above the substrate and the gate stack. A top surface 48 of the layer 46 is processed with a chemical-mechanical polishing (CMP) process to define a planar surface. A set of metal contacts 50, typically formed of tungsten, extend from the top surface 48 through the ILD/PMD layer 46 in metal-filled contact openings to make electrical contact with the source region 32 and drain region 34 (shown in cross-section FIG. 1A) and gate electrode 40 (shown in cross-section FIG. 1B). A first metallization layer M1 is then provided above the ILD/PMD layer 46, with the first metallization layer M1 comprising metal lines 54 formed in metal-filled via and/or trench openings in contact with the contacts 50 and surrounded by a planarized dielectric material layer 56.
As feature sizes in integrated circuit devices continue to shrink, it is becoming more complicated and challenging to provide source, drain and gate contacts in middle of line (MOL) interconnection. The reasons for this are numerous. For example, the gate contact may need to be moved away from the active area 22 (for example, over the peripheral isolation 22 as shown in FIG. 1B) in order to avoid shorting between the gate contact and the trench silicide of the source-drain regions. This is a disadvantage because it results in an increase in chip area. To address this issue, integrated circuit designers are moving towards merged fin structure and shared source-drain structures. There is a noted drawback with this technology, however, because of increased contact resistance at the source-drain regions due to reduced contact area (as generally shown in FIG. 1A at reference 60). Misalignment of the gate and the gate contact is another concern (see, FIG. 1B at reference 62), and this can lead to concerns with shorting of the gate to the source-drain contact.
There is accordingly a need in the art for an improved MOL interconnection to source, drain and gate regions of a transistor integrated circuit.