Memory devices, such as dynamic random access memories (“DRAMs”), have a variety of performance parameters. One of the most important of these performance parameters is the speed at which memory devices are able to read and write data. Generally, memory devices capable of reading and writing data at a higher speed, known as high performance memory devices, are more expensive. Conversely, memory devices that are only capable of accessing data at a slower rate, known as low performance memory devices, must be sold at a cheaper price. In an attempt to increase the operating speed of memory devices, double data (“DDR”) rate DRAMs have been developed. DDR DRAMs are synchronous DRAMs that perform two memory operations each clock cycle—one on each transition of each clock pulse. In a typical DDR DRAM, the memory cells in two adjacent columns having the same column address are read each clock cycle.
Another performance parameter applicable to memory devices is the width of the memory device's data bus. Wider data buses operating at a given speed have a higher bandwidth, i.e., a greater number of bits/second can be accessed. The data bus of most memory devices, such as DRAMs, generally have a width of various powers of 2, i.e., 4, 8, 16, etc. bits.
The need to provide memory devices having different performance parameters generally requires memory device manufacturers to design and manufacture a wide variety of memory devices. For example, memory device manufacturers must design and fabricate relatively expensive memory devices that are capable of operating at a high-speed and different, relatively inexpensive memory devices that are only capable of operating at a relatively low-speed. Unfortunately, it is expensive to design each memory device and the processing needed to fabricate the memory device. The expense of designing and fabricating a variety of different memory devices having different performance parameters is exacerbated by the rapid obsolescence of memory devices as newer devices are introduced at an ever faster rate.
There is therefore a need for memory devices, such as DRAMs, that are capable of operating as either high-speed, narrow data bus memory devices or a low-speed, wide data bus memory devices.