The present invention relates to chip design, and more specifically, to constraint-driven pin optimization for hierarchical design convergence.
Part of the process of obtaining a physical implementation of a chip design involves pin placement. A chip is typically organized hierarchically. Pin (or wire-pin) placement is part of the physical synthesis step in chip design and refers to the placement of pins, which are boundary connections between hierarchies. The higher level hierarchy may be referred to as the unit level, and the lower levels may be referred to as macro levels (blocks) for explanatory purposes. Generally, each macro has boundary conditions that are given as inputs to physical synthesis. In the early stage of design, referred to as floor planning, pin locations may be defined. These pin locations may be iteratively changed to converge on a final design and physical implementation that meets timing and other requirements for the chip.