1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory cell array section with a reduced power consumption and an increased speed.
2. Description of the Background Art
In recent years, finer process rules for semiconductor integrated circuits are imposing problems such as an increase in the leak current of transistors on standby (e.g., the OFF leak current or the gate leak current). Moreover, the capacity of a semiconductor memory device such as an SRAM, a DRAM and a ROM has been increasing rapidly. As a result, the power consumption of memory cell arrays included in a semiconductor memory device of a semiconductor integrated circuit accounts for a large portion of the total power consumption of the entire semiconductor integrated circuit. Therefore, in order to reduce the power consumption of a semiconductor integrated circuit, it is effective to reduce the power consumption of the memory cell arrays included in the semiconductor memory device.
A conventional technique for reducing the power consumption of memory cell arrays included in a semiconductor memory device is disclosed in Japanese Laid-Open Patent Publication No. 7-211079, for example. In the semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 7-211079, a back-bias voltage is supplied to the substrate electrode of an N-type MOS transistor forming a memory cell, thereby reducing the leak current due to the subthreshold current in a standby state. Therefore, the power consumption of the semiconductor memory device is reduced.
Another conventional method is disclosed in Japanese Laid-Open Patent Publication No. 10-112188. FIG. 17 shows a configuration of a semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 10-112188. The semiconductor memory device shown in FIG. 17 includes a memory cell array 17 including m rows by n columns of complete CMOS-type memory cells 7. The memory cell 7 includes load P-type MOSFETs (hereinafter referred to as “load PMOSs”) 1 and 2, driving N-type MOSFETs (hereinafter referred to as “driving NMOSs”) 3 and 4, and transfer N-type MOSFETs (hereinafter referred to as “transfer NMOSs”) 5 and 6.
The source electrodes of load PMOSs 1 and 2, a substrate electrode 15 of the load PMOS 1 and a substrate electrode 16 of the load PMOS 2 are all connected to a power supply terminal 8 (a power supply voltage VDD). The drain electrodes of the load PMOSs 1 and 2 are connected to memory nodes 20 and 21, respectively, of the memory cell. A substrate electrode 13 of the driving NMOS 3 and a substrate electrode 14 of a driving NMOS 4 are both connected to a ground terminal 9 (a ground potential VSS). The source electrodes of the driving NMOSs 3 and 4 are both connected to a source line 23, and the drain electrodes thereof are connected to the memory nodes 20 and 21, respectively.
A substrate electrode 11 of a transfer NMOS 5 and a substrate electrode 12 of a transfer NMOS 6 are both connected to the ground terminal 9. The gate electrodes of the transfer NMOSs 5 and 6 are both connected to a word line 22, the drain electrodes thereof are connected to bit lines 18 and 19, respectively, and the source electrodes thereof are connected to the memory nodes 20 and 21, respectively. The memory node 20 is connected to the gate electrode of the load PMOS 2 and that of the driving NMOS 4, and the memory node 21 is connected to the gate electrode of the load PMOS 1 and that of the driving NMOS 3. Thus, the load PMOSs 1 and 2 and the driving NMOSs 3 and 4 in the memory cell 7 together form a latch circuit.
A switching circuit 33 is connected to the memory cell 7 via the source line 23. While the configuration of the switching circuit 33 will not be described in detail, the operation thereof will be described briefly. The switching circuit 33 supplies the ground potential VSS to the source line 23 that is connected to the memory cell 7 in an active state, and supplies an intermediate potential between the power supply voltage VDD and the ground potential VSS (the intermediate potential is set to 0.5 V in an embodiment of Japanese Laid-Open Patent Publication No. 10-112188) to the source line 23 that is connected to the memory cell 7 in an inactive state.
When the memory cell 7 is inactive, the switching circuit 33 increases the potential of the source line 23 connected to the memory cell 7 to the intermediate potential. As a result, the threshold voltage of the driving NMOSs 3 and 4 increases due to the substrate bias effect, thereby reducing the leak current due to the subthreshold current from the memory cell 7. As described above, in the semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 10-112188, the source potential of the driving NMOSs of each memory cell is controlled by the switching circuit, thus reducing the power consumption.
However, the conventional semiconductor memory device described above has the following problems. In either of the semiconductor memory devices disclosed in Japanese Laid-Open Patent Publication Nos. 7-211079 and 10-112188, the leak current from a memory cell is reduced by increasing the threshold voltage of the transistor utilizing the substrate bias effect. Therefore, with these devices, the threshold voltage of the transistor increases, thereby deteriorating the operation characteristics of the transistor at low power supply voltages. The semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 7-211079 has a problem in that it is necessary to provide a control circuit for supplying the back-bias voltage, thereby increasing the circuit area. The semiconductor memory device disclosed in Japanese Laid-Open Patent Publication No. 10-112188 also has a problem in that it is necessary to provide a switching circuit for supplying a voltage to the source line, thereby increasing the circuit area.