(a) Field of the Invention
The present invention relates to an apparatus and method for driving a plasma display panel (PDP).
(b) Description of the Related Art
In recent years, flat panel displays such as liquid crystal displays (LCD), field emission displays (FED), PDPs, and the like have been actively developed. The PDP is advantageous over the other flat panel displays in regard to its high luminance, high luminous efficiency, and wide view angle, and accordingly it is favorable for making large-scale screens of more than 40 inches as a substitute for the conventional cathode ray tube (CRT).
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images, and it includes, according to its size, more than several scores to millions of pixels arranged in a matrix pattern. Such a PDP is classified into a direct current (DC) type and an alternating current (AC) type according to its discharge cell structure and the waveform of the driving voltage applied thereto.
The DC PDP has electrodes exposed to a discharge space to allow DC flowing through the discharge space while the voltage is applied, and thus requires a resistance for limiting the current. On the other hand, the AC PDP has electrodes covered with a dielectric layer that forms a capacitance component to limit the current and protects the electrodes from the impact of ions during a discharge, and is thus superior to the DC PDP in regard to a long lifetime.
FIG. 1 is a partial perspective view of an AC PDP. Referring to FIG. 1, pairs of scan electrode 4 and sustain electrode 5 covered with dielectric layer 2 and protective layer 3 are arranged in parallel on first glass substrate 1. A plurality of address electrodes 8 covered with insulating layer 7 are arranged on second glass substrate 6. Partition walls 9 are formed in parallel with address electrodes 8 on insulating layer 7 and are interposed between address electrodes 8. Fluorescent material 10 is formed on the surface of insulating layer 7 and on both sides of partition walls 9. First glass substrate 1 and second glass substrate 6 are arranged in a face-to-face relationship with discharge space 11 formed therebetween, so that scan electrode 4 and sustain electrode 5 lie in a direction perpendicular to address electrodes 8. Discharge spaces at intersections between address electrodes 8 and the pairs of scan electrode 4 and sustain electrode 5 form discharge cells 12.
FIG. 2 shows an arrangement of the electrodes in the PDP. The PDP has a pixel matrix consisting of m×n discharge cells. More specifically, address electrodes A1 to Am are arranged in m columns, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are alternately arranged in n rows. Discharge cells 12 shown in FIG. 2 correspond to discharge cells 12 of FIG. 1.
Typically, the driving method of the AC type PDP includes a reset period, an address period, and a sustain period. In the reset period, the state of each cell is initialized so as to facilitate an addressing operation on the cell. In the address period, wall charges are accumulated in a selected cell (i.e., addressing cell) that is turned on in the panel. In the sustain period, a discharge occurs to actually display an image on the addressing cells.
In the design of the PDP driving waveform, the reset waveform is very significant. A description will now be given as to the reset waveform of the conventional AC type PDP and the driving method of the same.
Basically, the reset operation involves erasing wall charges resulting from the previous discharge and setting them up to facilitate the next addressing discharge operation. The PDP has several millions of cells, each of which has a slightly different discharge voltage. But there is the difficulty of controlling the discharge of all the cells with one defined driving voltage. It is therefore very important to overcome the difference in discharge voltage among the cells while erasing wall charges and resetting them in the reset period. The reset waveform is divided into a part involving erasing wall charges caused by the previous discharge, and a part involving solving the problem with regard to the dispersion of the discharge voltage among cells and redistributing the wall charges for facilitating the addressing.
Namely, the reset period is an interval for applying a voltage of a specific form for the purpose of facilitating the operation of the subsequent address period. A stable display operation of a plasma display panel inferior in inter-cell uniformity can be achieved according to the operational characteristics of this period.
The waveform mainly used in the reset period to stably operate display devices having poor inter-cell uniformity is the ramp waveform of FIG. 3, which is disclosed in U.S. Pat. No. 5,745,086. In the waveform of FIG. 3, a display device having poor inter-cell uniformity performs a more stable display operation when the ramp waveform has a gentler slope, of less than 15 V/μs. If the slope is set at about 2 V/μs for stable operation, then an excessive time of as long as double the time of 200 μs, i.e., 400 μs is required for a voltage of 400 V. An improvement of this waveform is illustrated in FIG. 4.
In the waveform of FIG. 4, instead of continuously changing the voltage to a required voltage level with a ramp waveform, a voltage that is high enough to not cause a discharge in the discharge cells of the PDP is changed instantaneously, and a ramp waveform is then applied. However, this method causes an intense discharge when the instantaneously varying voltage is extremely high, allowing no stable reset operation. Accordingly, too much time is required for the reset period in this case.
The conventional PDP driving apparatus is comprised of a sustain pulse circuit and a ramp waveform forming circuit. The voltage in the reset period must be high enough to guarantee stable operation of the driving apparatus, and it is much higher than the voltage in the sustain period. Accordingly, a main path switch is necessary for interrupting the ramp waveform forming circuit driven with a high voltage and the sustain circuit driven with a low voltage. The main path switch must have a high withstand voltage.
According to the conventional PDP driving circuit and method, when the reset waveform has a steep slope or when the instantaneously varying voltage is high, a stable reset operation is not guaranteed. Otherwise, when the reset waveform has a gentle slope, the reset period is prolonged but the sustain period is difficult to increase, thereby deteriorating the brightness.
Furthermore, the switches that serve to interrupt the ramp waveform forming circuit driven with a high voltage and the sustain pulse circuit driven with a low voltage must have a high withstand voltage. However, the higher withstand voltage leads to a higher price of the switches, causing a problem with regard to cost.