The present invention relates generally to the field of packaging for electronic devices, and, more specifically, to packages for large scale integrated circuits.
At the present state of the art integrated circuits are provided in rectangular dual-inline pin (DIP) packages or in rectangular surface mounting flat packs. Very large scale integrated circuits, herein referred to as VLSI, containing thousands of gate equivalents are now requiring up to forty pins, half of which are located on each side of the rectangular package.
As the number of gate equivalents per VLSI chip increases, the number of pins is expected to increase and, therefore the length of the package is also expected to increase. Large rectangular packages have a number of disadvantages. First, long packages contain long leads between the IC chip itself and the external circuit creating a large parasitic capacitance component and a large parasitic inductance component. These parasitic components are particularly troublesome in high frequency circuits where parasitic reactances approach circuit design reactances. Second, a large number of pins requires that the ratio of silicon area to packaging area increase at a drastic rate, while the most requirements are for increasing complex dense packaging. Thirdly, rectangular packages require lead placements which introduce non-symmetrical design considerations since there is little symmetry in a rectangular configuration compared, say, to a circular or spherical configuration.
A number of devices have been provided which address these problems, but none are as suitable as is the instant invention for the purposes intended.