As the function of present integrated circuits becomes more powerful and the structure of the integrated circuits becomes more complicated, the number of masks needed for fabricating the integrated circuits increases accordingly, and thus incurs a higher fabrication cost.
With reference to FIGS. 1A to 1I for a fabrication process of an N-type double-diffused metal oxide semiconductor (DMOS) structure, an N-epitaxial layer 10 and a field oxide layer 12 are grown sequentially on a silicon substrate 5 as shown in FIG. 1A, and a first mask is used for forming a first photoresist layer 14 to define a region for locating a guard ring. In FIG. 1B, the exposed field oxide layer 12 is removed by etching through the first photoresist layer 14, and then the first photoresist layer 14 is removed. The remained field oxide layer 12, which is corresponding to the location of the guard ring, defines active regions of the metal oxide semiconductor power transistors. To clearly describe the fabrication process of the N-type double-diffused metal oxide semiconductor (DMOS) structure, only a portion of the guard ring is shown in FIGS. 1C to 1H. Referring to FIG. 1C, after forming a gate oxide layer 20 and a gate electrode layer 22 sequentially on the active regions, a second mask is used to form a second photoresist layer 24 for defining gate electrodes of the DMOS cells. The exposed gate electrode layer 22 and the gate oxide layer 20 are then removed by etching so as to expose a portion of the N-epitaxial layer 10. Afterward, an ion implantation process is used for implanting P-type impurities to the exposed portion of the N-epitaxial layer 10, and a high temperature thermal process is followed to drive in the P-type impurities to form a P-well region 26. Afterward, with reference to FIG. 1D, the second photoresist layer 24 is removed, and a third mask is used for forming a third photoresist layer 32 to define source regions of the DMOS cells. Then, an ion implantation process is used for implanting N-type impurities and a high temperature thermal process is followed to drive in the N-type impurities to form N+ source regions 30. In FIG. 1E, after the third photoresist layer 32 is removed, a fourth mask is used for forming a fourth photoresist layer 42 to define a P-type heavily doped region 40. Then, an ion implantation process is used for implanting P-type impurities in the P-type heavily doped region 40.
Thereafter, referring to FIG. 1F, a silicon oxide layer 50 and a boron-phosphorus-silicon-glass (BPSG) layer 52 are formed sequentially, and a fifth mask is used for forming a fifth photoresist layer 54 to define a contact window region. The silicon oxide layer 50 and the boron-phosphorus-silicon-glass (BPSG) layer 52 with respect to the contact window region are then etched and removed to expose the P-type heavily doped region 40. Afterward, a high temperature thermal process is carried out to reflow the BPSG layer 52. Then, in FIG. 1G, a metal layer 60 is deposited over all the exposed surfaces, and a sixth mask is used for forming a sixth photoresist layer 62 to define a signal transmitting circuit. In FIGS. 1H and 1I, after the signal transmitting circuit is formed by etching, a passivation layer 70 is formed for protecting the N-type double-diffused metal oxide semiconductor (DMOS) cells 80, and then a seventh mask is used for defining a gate pad region 72 and a source pad region 74 for wire bonding.
In the fabrication method of the aforementioned N-type double-diffused metal oxide semiconductor (DMOS) structure, seven masks are used and the cost of masks is very high. Thus, it is eager for manufacturers in the industry to develop a process to simplify the lithographic steps with respect to different masks to reduce the number of masks needed in the fabrication process so as to reduce the fabrication cost.