A. Technical Field
The present invention relates generally to digital variable resistance, and more particularly, to a digital variable resistor string that provides high resolution and efficient substrate area use.
B. Background of the Invention
Various electrical devices may require that certain resistance values vary in order to change electrical characteristics of the device. A digital potential meter operating in a variable resistor mode may vary its internal resistance characteristics using a plurality of resistors that are coupled together serially by a switching network. This resistor string varies its effective resistance relative to which transmission gates within the switching array are closed or open.
A decoder-based digital-to-analog (“DAC”) converter may also comprise a serial resistor string that provides taps to create different voltage levels between high and low voltages for the conversion processes. This serial resistor string effectively operates as a voltage divider in which a voltage level is defined according to which resistors within the resistor string are electrically coupled by binary switches within the system.
FIG. 1 illustrates an example of such a serial resistor string that is controlled by a 1024 position decoder. An interface 110 provides a signal on a 10-bit data bus 115 to a position decoder 120. The position decoder is electrically coupled to a switching network 140 comprising a number of transmission gates and a serial resistor string 130. The switching network 140 may be coupled to the serial resistor string in a tree configuration in which a single path connects a particular resistor to an output node or interface. Typically, each resistor within the serial resistor string has approximately the same resistance.
The switching network 140 and serial resistor string 130 provide an effective resistance by opening and closing transmission gates which electrically couple resistors in series. For example, a resistance value of 4R may be created by coupling R0, R1, R2 and R3 (all having equal resistance values) together in series by closing the appropriate gates within the switching network 140. In turn, a corresponding voltage level is created within the system in which the resistor string is located.
Certain applications in which resistor strings are employed require a relatively high resolution. One method in which higher resolution may be achieved is by reducing the resistance values of the resistors within the resistor string. If on-chip resistors are used within the string, then this reduction in resistance value causes each resistor to increase its relative width, which also results in increasing the size of the resistor contacts. In order to maintain a preferred temperature coefficient, the ratio of contact resistance to the total unit resistance is typically less than 20%, which may limit the length of the resistor. Accordingly, if fine resolution is desired, a series unit resistor string may require a very large area.
One skilled in the art will recognize that particular problems become apparent when the width of on-chip resistors increases. The increased width in each of the resistors may result in the resistor string occupying a relatively large area of a substrate on which the string is integrated. The gradient of the substrate within this large area occupied by the resistor string may also cause performance issues. Additionally, the characteristics of the wide resistor contacts, and corresponding routing metals, may fluctuate relative to temperature variations and contribute a significant amount of resistance to the resistor itself.
The differential non-linearity of a digital variable resistor may be measured in relation to wiper resistance caused by switches adjacent to the resistor. Furthermore, these switches or wiper components may have poor temperature coefficients which may further degrade the performance of the resistor string. In order to reduce the amount of wiper resistance, larger switches are integrated within the switching network resulting in a further demand on substrate surface area.