1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular a synchronous semiconductor memory device operating in synchronization with a clock signal. More particularly, the invention relates to a control circuit for data output of the synchronous semiconductor memory device, and specifically relates to a structure for preventing output of invalid data.
2. Description of the Background Art
FIG. 21 is a timing chart representing an operation in data reading of a synchronous semiconductor memory device in the prior art. The operation of the synchronous semiconductor memory device will be described below with reference to FIG. 21.
This synchronous semiconductor memory device performs take-in of an externally supplied control signal and output of data in synchronization with an externally supplied clock signal extCLK such as a system clock. At a rising edge of external clock signal extCLK in clock cycle #1, a row address strobe signal /RAS is set to L level, and a column address strobe signal /CAS and a write enable signal /WE are set to H-level. A combination of states of these control signals is called an active command, which instructs the synchronous semiconductor memory device to perform row selection in accordance with a currently applied address signal. When a so-called RAS-CAS delay time of a standard DRAM elapses, an internal column selection is allowed.
At the rising edge of external clock signal extCLK in clock cycle #3, row address strobe signal /RAS and write enable signal /WE are set to H-level, and column address strobe signal /CAS is set to L-level. A combination of these states of control signals is called a read command, which instructs the device to perform the column selection in accordance with a currently applied address signal, and data is read from the selected memory cell.
In the data read operation, the column selection is internally performed, and data of the selected memory cell on the selected column is externally read out, and therefore a time is required for internal data transfer. Initial data is output in clock cycle #4, and output data Dout is made definite at the rising edge of external clock signal extCLK in clock cycle #5. Thereafter, column address signals are internally produced in accordance with a predetermined sequence to perform the column selection, of which start address is designated by the externally applied address signal, and data reading is continuously performed. At each of the rising edges of external clock signal extCLK in clock cycles #6, #7 and #8, data is made definite and is sampled by an external device.
The number of clock cycles from application of the read command to appearance of valid data is called a CAS latency. The number of data per data output terminal, which are successively read in response to one read command, is called a burst length. FIG. 21 shows by way of example the read operation performed with the CAS latency of 2 and the burst length of 4.
At the rising edge of external clock signal extCLK in clock cycle #9, row address strobe signal /RAS and write enable signal /WE are set to L-level, and column address strobe signal /CAS is set to H-level. A combination of these states of control signals is called a precharge command, which instructs precharging of the array. Thus, the selected row is internally driven to the unselected state, and the memory cell array returns to a predetermined precharged state so that the synchronous semiconductor memory device enters the standby state.
As shown in FIG. 21, the device takes in the external signal in synchronization with external clock signal extCLK so that a definite timing of each control signal is determined with respect to external clock signal extCLK, and it is not necessary to take into account a timing margin for a skew of each control signal or the like. Therefore, the internal operation can be performed at fast timings, and fast access is allowed. Also, fast data transfer is allowed because data Dout is output in synchronization with external clock signal extCLK.
FIG. 22 schematically shows a structure of a portion of the synchronous semiconductor memory device related to data reading in the prior art. In FIG. 22, the synchronous semiconductor memory device in the prior art shown in FIG. 22 includes a memory cell array 900 having a plurality of memory cells arranged in rows and columns, an address input buffer 902 which takes in an externally applied address signal in synchronization with the clock signal and produces internal row and column address signals, a row select circuit 904 which drives the addressed row (word line) in memory cell array 900 to the selected state in accordance with the internal row address signal received from address input buffer 902, a column select circuit 906 for selecting the addressed column (bit line pair) in memory cell array 900 in accordance with the internal column address signal received from address input buffer 902, a read circuit 908 for reading data of the memory cell on the column selected by column select circuit 906 in the data read operation, an output circuit 910 which receives and buffers read data RD supplied from read circuit 908 in synchronization with an internal clock signal CLKO for producing external data Dout when activated, a clock buffer 912 for buffering externally applied clock signal extCLK to produce internal clock signals intCLK and CLKO, a command decoder 914 for determining logical states of externally supplied control signals /RAS, /CAS and /WE in synchronization with internal clock signal intCLK, to produce a signal representing result of the determination, and a control circuit 916 for performing an operation instructed according to the output signal of command decoder 914.
Control circuit 916 includes a row-related control circuit 916a which is activated upon reception of an operation mode instruction (the active command and the precharge command) related to the row selection from command decoder 914, and controls operations of circuits related to the row selection, a column-related control circuit 916b which is activated upon reception of instructions (the read command and a write command instructing data writing) related to the column selection from command decoder 914, and to control operations of circuits related to the column selection, and an output control circuit 916c which activates output circuit 910 in accordance with a read enable signal OEMF received from column-related control circuit 916b. When an output enable signal (i.e., output buffer enable signal) OEM from output control circuit 916c is activated, output circuit 910 is activated to generate data Dout in synchronization with internal clock signal CLKO.
Row-related control circuit 916a controls address input buffer 902 and row select circuit 904 as well as a bit line precharge circuit and a sense amplifier circuit, which are not shown in the figure, but it is shown controlling only row select circuit 904 in FIG. 22. Column-related control circuit 916b activates read enable signal OEMF when an access command (the read command) is applied. While read enable signal OEMF is active, the column selection and the reading of internal data are performed. Column select circuit 906 includes a column decoder and I/O gates for connecting the selected column to the internal data line. Read circuit 908 includes a preamplifier circuit for amplifying the data on the internal data line. The read circuit may include a transfer gate, which transfers the output signal of the preamplifier circuit in synchronization with internal clock signal intCLK, as necessary according to the internal structure.
Output circuit 910 includes a gate circuit for taking in read data RD applied from read circuit 908 in synchronization with internal clock signal CLKO, and an output buffer which in turn buffers and outputs the output signal of this gate circuit when output enable signal OEM is active. Column-related control circuit 916b determines a timing for taking the column address into the address input buffer 902, but this operation is not shown in FIG. 22 for simplicity purpose.
FIG. 23 shows an example of a structure of clock buffer 912 shown in FIG. 22. In FIG. 23, clock buffer 912 includes a buffer circuit 912a for buffering external clock signal extCLK and producing internal clock signal intCLK, and a buffer circuit 912b for buffering external clock signal extCLK and producing internal clock signal CLKO for reading. Internal clock signal intCLK and internal clock signal CLKO for reading are synchronized with each other, and are always generated (if a clock enable signal is not used).
FIG. 24 shows an example of a structure of an OEMF signal generating circuit included in column-related control circuit 916b shown in FIG. 22. In FIG. 24, the OEMF signal generating circuit includes a burst length counter 920a which operates in synchronization with internal clock signal intCLK to delay a data read instructing signal /READ by a burst length time, an NAND circuit 920b which receives data read instructing signal /READ on one of its two inputs, and an NAND circuit 920c which receives a reset signal /RST from burst length counter 920a and the output signal of NAND circuit 920b. NAND circuit 920b receives the output signal of NAND circuit 920c, and generates read enable signal OEMF. Read instructing signal /READ attains L-level, i.e., the active state for a predetermined period when the read command is applied. Burst length counter 920a operates in synchronization with internal clock signal intCLK to shift read instructing signal /READ for the burst length period, and activates reset signal /RST after elapsing of the burst length period. An operation of the OEMF signal generating circuit shown in FIG. 24 will be described below with reference to a timing chart of FIG. 25.
When a read command is applied at the rising edge of external clock signal extCLK, command decoder 914 shown in FIG. 22 detects this application of the read command in synchronization with internal clock signal intCLK, and drives read instructing signal /READ to the active state of L-level for a predetermined period. In response to the activation of read instructing signal /READ, read enable signal OEMF from NAND circuit 920b attains the active state of L-level. Reset signal /RST is at H-level, and NAND circuit 920c receives signals at H-level on both inputs, and drives its output signal to L-level. Thereby, read enable signal OEMF maintains the active state of H-level even when read instructing signal /READ rises to H-level. While this read enable signal OEMF is active, selection of the memory cell column and reading of data from the selected memory cell are performed under the control by column-related control circuit 916b.
The burst length counter 920a, which counts the burst length period in synchronization with internal clock signal intCLK (FIG. 25 shows the operation with the burst length of 4), drives the reset signal /RST to the active state of L-level for a period of one clock cycle when four clock cycles (burst length period) elapses after application of the read command. When the reset signal /RST falls to L-level, the output signal of NAND circuit 920c attains H-level, and NAND circuit 920b which receives the signals at H-level on both inputs drives read enable signal OEMF to L-level. Thereby, the output signal of NAND circuit 920c is fixed to H-level, and read enable signal OEMF maintains the inactive state even when reset signal /RST returns to H-level.
By keeping read enable signal OEMF active only for the burst length period, data of the burst length is read.
FIG. 26 shows by way of example structures of output control circuit 916c and output circuit 910 shown in FIG. 22. In FIG. 26, output control circuit 916c includes a (CAS latency-1) clock shifter 916ca delaying read enable signal OEMF, which is generated from column-related control circuit 916b shown in FIG. 22, by (CAS latency-1) clock cycle(s) of internal clock signal intCLK. (CAS latency-1) clock shifter 916ca performs a shifting operation in synchronization with internal clock signal intCLK, and produces output enable signal (output buffer enable signal) OEM by delaying read enable signal OEMF by a period of (CAS latency-1) clock cycle(s).
Output circuit 910 includes a gate circuit 910a which operates in synchronization with internal clock signal CLKO to take in and latch the internal read data from read circuit 908 shown in FIG. 22, and an output buffer circuit 910b which is activated when output enable signal OEM is active, and externally outputs data DD latched by gate circuit 910a.
Gate circuit 910a includes a tristate inverter buffer 910aa which is activated to invert internal read data RD when internal clock signal CLKO is at H-level, an inverter circuit 910ab which inverts the output signal of tristate inverter buffer 910aa and applies internal data DD to output buffer circuit 910b, and an inverter circuit 910ac which inverts and transmits output data DD of inverter circuit 910ab to an input of inverter circuit 910ab. Inverter circuits 910ab and 910ac form an inverter latch.
Output buffer circuit 910b includes an inverter circuit 910ba inverting data DD, an AND circuit 910bb receiving output enable signal OEM and data DD, an AND circuit 910bc receiving the output signal of inverter 910ba and output enable signal OEM, an n-channel MOS transistor 910bd which is turned on to produce output data Dout at a power supply voltage Vcc level when the output signal of AND circuit 910bb is at H-level, and an n-channel MOS transistor 910be which is turned on to produce output data Dout at a ground voltage VSS level when the output signal of AND circuit 910bc is at H-level. Each of AND circuits 910bb and 910bc is generally formed of an NAND circuit and an inverter circuit. Now, operations of output control circuit 916c and output circuit 910 shown in FIG. 26 will be described below with reference to a timing chart of FIG. 27.
Internal clock signals intCLK and CLKO are generated in synchronization with external clock signal extCLK. Therefore, tristate inverter buffer 910aa of gate circuit 910a is always repetitively turned on and off, and repetitively takes in and latch internal read data RD.
When the read command is applied in clock cycle #0, read enable signal OEMF attains the active state of H-level in clock cycle #0. The following description will be given on the operation which is performed with the CAS latency of 2 and burst length of 4. In accordance with activation of read enable signal OEMF, a memory cell is selected and data is read from the selected memory cell under the control by column-related control circuit 916b (see FIG. 22).
In clock cycle #1, internal read data RD is taken into gate circuit 910a in response to the rising of internal clock signal CLKO, and is latched in response to the falling of internal clock signal CLKO. Since CAS latency is 2, output enable signal OEM from (CAS latency-1) clock shifter 916ca is activated in synchronization with internal clock signal intCLK in clock cycle #1. When output enable signal OEM attains the active state of H-level, output buffer circuit 910b is activated to attain the output low-impedance state, and operates to buffer and output the data applied from gate circuit 910a.
Since the burst length is 4, read enable signal OEMF is deactivated in clock cycle #4, and the reading operation of read circuit 908 (see FIG. 22) is disabled. Meanwhile, internal clock signal CLKO is always generated so that the operation of taking in and latching internal read data RD is repeated. In clock cycle #4, gate circuit 910a takes in the last burst length data in synchronization with the rising of internal clock signal CLKO, for latching in synchronization with the falling thereof.
After this last data of data of the burst length is output, output enable signal OEM is deactivated to attain L-level in clock cycle #5, and output buffer circuit 910b attains the output high-impedance state. Thereby, the data of burst length of 4 is successively output in synchronization with external clock signal extCLK.
A region hatched in the timing chart of FIG. 27 is a region of invalid data.
FIG. 28 shows another structure of a synchronous semiconductor memory device in the prior art. The synchronous semiconductor memory device shown in FIG. 28 differs from the synchronous semiconductor memory device shown in FIG. 22 in that the device shown in FIG. 28 has a function of masking the data output of output circuit 910. More specifically, the synchronous semiconductor memory device shown in FIG. 28 includes an internal mask instruction signal generating circuit 930, which is responsive to an externally applied data output mask instruction DQM to generate an internal mask instructing signal DQM0 to output control circuit 916c in synchronization with internal clock signal intCLK. Output control circuit 916c drives output enable signal OEM to the inactive state and sets output circuit 910 to the high-impedance state, when internal mask instructing signal DQM0 from internal mask instructing signal generating circuit 930 is active and indicates that the data output is to be masked. Structures other than the above are the same as those shown in FIG. 22, and the corresponding portions bear the same reference numerals.
FIG. 29 schematically shows a structure of internal mask instructing signal generating circuit 930 shown in FIG. 28. In FIG. 29, internal mask instructing signal generating circuit 930 includes an input buffer 930a which receives and buffers externally applied data mask instruction DQM, a one-shot pulse generating circuit 930b which generates a pulse signal of one shot in response to the rising of internal clock signal intCLK when the signal received from input buffer 930a is active, and a latch circuit 930c which latches a one-shot pulse signal DQM0F from one-shot pulse generating circuit 930b in synchronization with internal clock signal intCLK.
In the structure of internal mask instructing signal generating circuit 930 shown in FIG. 29, the data output in the next clock cycle is masked when externally applied mask instruction DQM becomes active.
FIG. 30 shows an example of the structure of one-shot pulse generating circuit 930b shown in FIG. 29. In FIG. 30, one-shot pulse generating circuit 930b includes an AND circuit 930ba receiving internal clock signal intCLK and output signal DQMi from the input buffer, an inversion/delay circuit 930bb which inverts the output signal of AND circuit 930ba and delays the same for a predetermined time, and an AND circuit 930bc which receives the output signal of AND circuit 930b and the output signal of inversion/delay circuit 930bb, and outputs signal DQM0F. Signal DQMi from input buffer 930a shown in FIG. 29 is at H-level when active. When the mask instruction is applied, the output signal of AND circuit 930ba rises to H-level in response to the rising of internal clock signal intCLK to H-level, and signal DQM0F attains the active state of H-level for a predetermined period.
The structure of the one-shot pulse generating circuit shown in FIG. 30 may be replaced with a set/reset flip-flop which is set when the output signal of AND circuit 930ba is at H-level, and is reset upon elapsing of a predetermined time. This set/reset flip-flop outputs signal DQM0F.
FIG. 31 shows an example of a structure of latch circuit 930c shown in FIG. 29. In FIG. 31, latch circuit 930c includes an inverter 930ca inverting signal DQM0F, an NAND circuit 930cb receiving internal clock signal intCLK and signal DQM0F, an NAND circuit 930cc receiving the output signal of inverter 930ca and internal clock signal intCLK, an NAND circuit 930cd receiving on one of its two inputs the output signal of NAND circuit 930cb, and an NAND circuit 930ce receiving the output signals of NAND circuits 930cc and 930cd. The output signal of NAND circuit 930ce is applied to the other input of NAND circuit 930cd. NAND circuit 930cd generates internal mask instructing signal DQM0.
In latch circuit 930c shown in FIG. 31, NAND circuits 930cb and 930cc operate as an inverter to pass signal DQM0F therethrough when internal clock signal intCLK is at H-level. NAND circuits 930cd and 930ce form a latch circuit, and latch the signals applied from NAND circuits 930cd and 930cc. When signal DQM0F becomes active, it is taken into this latch circuit in synchronization with internal clock signal intCLK, and is kept in the latched state for the current clock cycle. Now, an operation of internal mask instructing signal generating circuit 930 shown in FIGS. 29 through 31 will be described below with reference to a waveform diagram of FIG. 32.
In clock cycle #0, externally applied mask instructing signal DQM is driven to H-level, and is held at H-level at the rising edge of external clock signal extCLK in clock cycle #1. Internal clock signal intCLK is generated in synchronization with external clock signal extCLK, and signal DQM0F from one-shot pulse generating circuit 930b shown in FIG. 30 attains H-level for a predetermined period in response to the rising of internal clock signal intCLK. When internal clock signal intCLK is at H-level, latch circuit 930c takes in the applied signal. Therefore, signal DQM0F at H-level is taken into latch circuit 930c, and internal mask instructing signal DQM0 rises to H-level. While internal clock signal intCLK is at H-level, signal DQM0F holds H-level. When internal clock signal intCLK falls to L-level, the output signals of NAND circuits 930cb and 930cc attain H-level and latch circuit 930c attain the latch state.
In clock cycle #2, internal clock signal intCLK rises to H-level again. If externally supplied mask instruction DQM is low at the time of this rising, signal DQM0F from one-shot pulse generating circuit 930b is at L-level so that internal mask instructing signal DQM0 from latch circuit 930c is driven to L-level in synchronization with this rising of internal clock signal intCLK. Output enable signal OEM is deactivated in accordance with internal mask instructing signal DQM0. When the mask instruction is externally applied at the rising edge in clock cycle #1, data to be output in clock cycle #2 is masked.
FIG. 33 schematically shows a structure of output control circuit 916c shown in FIG. 28. In FIG. 33, output control circuit 916c includes a (CAS latency-2) clock shifter 940a which delays internal read enable signal OEMF from column-related control circuit 916b (see FIG. 28) by (CAS latency-2) clock cycle(s), an inverter 940b inverting internal mask instructing signal DQM0, an AND circuit 940c which receives the output signals of (CAS latency-2) clock shifter 940a and inverter 940b, and a one-clock shifter 940d which delays the output signal of AND circuit 940c by one clock cycle of internal clock signal intCLK. Output enable signal OEM is generated from one-clock shifter 940d.
Each of (CAS latency-2) clock shifter 940a and one-clock shifter 940d is a circuit which performs a shifting operation in synchronization with internal clock signal intCLK, and has the same basic structure as the latch circuit shown in FIG. 31.
The structure of the output circuit is the same as that shown in FIG. 26. The output circuit outputs the data in synchronization with internal clock signal intCLK when output enable signal OEM from one-clock shifter 940d is active.
FIG. 34 is a timing chart showing a data read sequence of the synchronous semiconductor memory device shown in FIG. 28. FIG. 34 shows the data read operation performed with the CAS latency of 2 and the burst length of 4. With the CAS latency of 2, (CAS latency-2) clock shifter 940a shown in FIG. 33 does not implement the delaying, so that read enable signal OEMF and output signal OEMFS of (CAS latency-2) clock shifter 940a are generated at the same timing. The data read operation of the synchronous semiconductor memory device shown in FIG. 28 will be described below with reference to FIGS. 28 to 34.
In clock cycle #0, the read command is applied. In accordance with this read command, read enable signal OEMF is driven to the active state of H-level in clock cycle #0, and is kept active for the burst length period. Concurrently, signal OEMFS from (CAS latency-2) clock shifter 940a is likewise driven to the active state of H-level. In accordance with read enable signal OEMF, selecting the column of memory cells and reading the internal data are internally performed.
At the rising edge of clock signal extCLK in clock cycle #1, externally applied mask instructing signal DQM is set to H-level to provide the instruction for masking the data output. In response to this data output mask instruction, internal mask instructing signal DQM0 rises to H-level for one clock cycle period in clock cycle #1, and the output signal of inverter 940b shown in FIG. 33 attains L-level. Output enable signal OEM becomes active in clock cycle #1. Even if internal mask instructing signal DQM0 is activated, this signal is applied to one-clock shifter 940d shown in FIG. 33 so that output enable signal OEM keeps the active state in clock cycle #1. Thereby, the output circuit produces and externally outputs internal read data DD in accordance with read data RD which is internally read by the read circuit.
In clock cycle #2, output enable signal OEM from one-clock shifter 940d shown in FIG. 33 attains the inactive state of L-level for one clock cycle period in accordance with internal mask instructing signal DQM0 so that the output circuit attains the output high-impedance state. Although internal read data RD is transferred in the output circuit, it is not externally output, and the data output is masked.
Data output mask instruction DQM is activated only at the rising edge of external clock signal extCLK in clock cycle #1. In clock cycles #2, #3 and #4, therefore, internal mask instructing signal DQM0 becomes inactive again so that, in clock cycles #3 and #4, output enable signal OEM attains the active state of H-level again, and the output circuit produces and externally outputs internal read data DD in accordance with internal read data RD.
As shown in FIG. 34, data output mask instruction DQM is activated in clock cycle #1 so that data output in the second clock cycle can be masked. Thereby, the external processor can take in only necessary data.
In the structures of the output control circuit and output circuit shown in FIG. 26, invalid data is output as can be seen from Dout2 in FIG. 27, if internal data DD from the gate circuit is not definite, i.e., if setup time tS of internal data DD with respect to output enable signal OEM is insufficient when output enable signal OEM changes from L-level to H-level. If setup time tS of internal data DD with respect to the rising of output enable signal OEM is sufficiently long and internal data DD is already definite at the time of activation of output enable signal OEM, invalid data is not output as the leading data, as can be seen from output data Dout1 in FIG. 27.
When output enable signal OEM is deactivated and changes from H-level to L-level, internal data DD must hold the fixed state. Thus, invalid data would be contained in output data Dout1 as shown in FIG. 27, if hold time tH of internal data DD with respect to the deactivation of output enable signal OEM is short. If hold time tH is sufficiently long, invalid data is not output as can be seen from output data Dout2 in FIG. 27.
Internal data DD is taken into the output circuit in synchronization with internal clock signal CLKO, and output enable signal OEM is also changes in synchronization with internal clock signal intCLK. These internal clock signals CLKO and intCLK are produced from external clock signal extCLK, and are synchronized with each other. Therefore, these output enable signal OEM and internal data DD change substantially at the same timings so that it is difficult to increase sufficiently both setup time tS and hold time tH. Therefore, the timings for generating internal data DD and output enable signal OEM are entirely shifted from each other. As a result, output enable signal OEM merely shifts forward or back with respect to internal data DD and, therefore, either setup time tS or hold time tH decreases so that output data Dout1 or Dout2 shown in FIG. 27 is obtained as the output data, and it is difficult to eliminate the invalid data.
If this invalid data satisfies specification values relating to the setup and hold times of output data Dout with respect to external clock signal extCLK as well as the access time (i.e., time from application of the read command to reading of valid data), no problem substantially arises because this invalid data is not sampled in the data processing, and valid data is correctly sampled. If the invalid data is output, however, output data Dout changes in a short period so that power supply noises occurs in the output circuit, and may cause a malfunction. Particularly, if the power supply noises occur on the system power supply, an operation power supply voltage changes in a processor sampling the data, resulting in malfunctions (e.g., failure in determination of high/low levels, and a malfunction of a circuit due to deviation of input and output timings of data from each other). Therefore, data processing cannot be performed accurately, and it is impossible to construct the system which can operate accurately. If such invalid data occurs, it is necessary to determine the access time in consideration of a margin for the invalid data, resulting in a problem that the access time cannot be reduced.
If the output control circuit shown in FIG. 33 is used for data output, problems related to output enable signal OEM arise due to the setup and hold times for the leading data and the last burst data, as already discussed with reference to FIG. 27, as well as due to the data mask.
As shown in FIG. 31, internal data mask instructing signal DQM0 changes in synchronization with internal clock signal intCLK. Therefore, output enable signal OEM also changes in synchronization with internal clock signal intCLK. Therefore, a problem arises in the setup and hold times with respect to deactivation and activation of the output enable signal at the time when the data mask instruction is applied.
As shown in FIG. 34, if hold time tH of internal data DD(0) is short with respect to deactivation of output enable signal OEM in clock cycle #2, invalid data occurs at the time of data output masking (output data Dout1). If setup time tS of third data DD(2) is short at the time of activation of output enable signal OEM in clock cycle #3, invalid data is likewise output as can be seen from output data Dout2 in FIG. 34. Therefore, the invalid data is output when the data output is to be masked, and a malfunctions occurs in circuits due to power supply noises and others.