1) Field of the Invention
The present invention relates to a multiprocessor apparatus suitable for use in a multiprocessor processing of a real time system, for example.
2) Description of the Related Art
The multiprocessor apparatus is an apparatus composed of a plurality of processors in which memory resources or the like are shared among each of the processors by using a shared bus. In this multiprocessor apparatus, jobs imposed on the multiprocessor apparatus are properly divided and assigned to each of the processors so that the job processing performance as a whole apparatus can be improved. Moreover, in this multiprocessor apparatus, components constituting the apparatus other than the processors can be shared by the processors. Thus, cost for manufacturing the apparatus can be suppressed to a relatively low level as compared with a case where a plurality of systems are prepared.
FIG. 13 is a block diagram showing a multiprocessor apparatus. As shown in FIG. 13, a multiprocessor 700 is arranged to include three processor units 100, 200 and 300, a bus arbitration circuit 500, and a shared memory 600 interconnected to one another by way of a shared memory bus 400.
The processor unit 100 is composed of a processor 110, a cache memory 120 and a snoop circuit 130. The processor unit 200 is composed of a processor 210, a cache memory 220 and a snoop circuit 230. And the processor unit 300 is composed of a processor 310, a cache memory 320 and a snoop circuit 330.
The cache memories 120, 220, 320 of the respective processor units 100, 200, 300 are each unit for storing therein a copy of partial data of the shared memory 600. Each of the snoop circuits 130, 230, 330 is a unit for monitoring the transaction on the shared memory bus 400 and controlling the invalidating processing on the same data when data stored in the cache memories 120, 220, 320 are updated.
The bus arbitration circuit 500 is a unit for effecting arbitration on the right to use the shared memory bus requested by the respective processors 110, 210, 310. The shared memory 600 is a memory commonly utilized by the respective processors 110, 210, 310 when any job is processed by the respective processors 110, 210, 310.
In the multiprocessor apparatus having the above-described construction, the cache memories 120, 220, 320 operable at a high speed for storing therein a partial copy of data stored in the shared memory 600 are disposed between the respective processors 110, 210, 310 and the shared memory bus 400. Therefore, almost all accesses to the shared memory 600 can be replaced with accesses to the cache memories, with the result that a direct access to the shared memory 600 requiring a lot of access time can be decreased in frequency. Accordingly, it becomes possible to suppress the lowering in the processor processing speed as compared with a case where the cache memories 120, 220, 320 are not provided.
Each of the snoop circuits 130, 230, 330 is a circuit for carrying out an invalidating processing on the cache memories 120, 220, 320 so that data matching property between the data stored in the shared memory 600 and the data stored in the cache memories 120, 220, 320 can be ensured.
In more concretely, each of the snoop circuits 130, 230, 330 of the respective processor units 100, 200, 300 always monitors the shared memory bus 400, and if the data in the shared memory 600 undergo any rewriting operation to make the data into a new version by any processor of other processor unit, each of the snoop circuits 130, 230, 330 examines whether or not any data of former version before the rewriting operation is left in the cache memory of its own processor unit. If it is determined that any data of former version is left in the cache memory, the subject data is made invalid. If the subject data is requested, it is determined that no data exists in the cache memory and the shared memory 600 is accessed to obtain data of the new version after the rewriting operation. In this way, the data matching property can be maintained between the shared memory 600 and the cache memories 120, 220, 320.
Japanese Patent laid-open gazette No. HEI 8-30510 discloses a technology in which snoop is carried out collectively by an external circuit, the invalidating operation is effected on only a cache memory having any data of former version before rewriting operation stored therein, whereby other processor requiring no invalidating processing is left allowed to access the cache memory in a normal manner. In this technology, a time period in which the processor ought to halt its operation is decreased.
Meanwhile, the cache memories 120, 220, 320 of the aforesaid multiprocessor apparatus 700 shown in FIG. 13 are arranged to store therein a partial copy of the contents of the shared memory 600. Therefore, all accesses to the shared memory 600 cannot be replaced with accesses to the cache memories 120, 220, 320. Accordingly, if data requested by the processors 110, 210, 310 are not prepared in the cache memories 120, 220, 320, the requested data shall be read from the shared memory 600 by way of the shared memory bus 400. This operation causes increase in frequency of direct access to the shared memory 600 which inevitably leads to a slow access speed.
For this reason, a countermeasure is taken in such a manner that data of consecutive several bytes, which are selected based on a prediction on the processor operation, are copied in advance in the cache memories 120, 220, 320 so that improvement can be achieved in a replacing ratio (hereinafter referred to as a cache hit ratio), i.e., ratio of replaceable accesses to the cache memories to the all data accesses to the shared memory. Thus, the processing speed of the processor can be suppressed from being lowered.
For example, Japanese Patent laid-open gazette No. SHO 60-183652 discloses a technology in which, in addition to an ordinary cache memory (dynamic cache), a static cache memory (static cache) is prepared so that data expected to undergo frequent accesses are fixedly assigned to the cache memory by using a special command, whereby the cache memories are managed depending on the data use frequency. In this technology, the cache hit ratio can be secured and the processing speed of the processor can be suppressed from being lowered.
However, if the multiprocessor apparatus shown in FIG. 13 is particularly obliged to do a real time system processor processing, many tasks each having a small size are processed at a time in a parallel fashion, and hence processing shall be carried out depending on occurring events. Therefore, it is almost impossible to predict a task which will be started up at the next step. In this situation, the processors 110, 210, 310 tend to make a lot of accesses to various kinds of discontinuing data, with the result that the processors tend to fail in finding a requested piece of data in the cache memories 120, 220, 320. Accordingly, the processors are forced to access the shared memory 600 for the requested piece of data.
If each of the processors 110, 210, 310 comes to make a frequent access to the shared memory 600, as described above, collision of bus use rights is frequently brought about in the shared memory bus 400, which fact leads to an overhead time due to the collision, with the result that access waiting time for the shared memory 600 tends to increase. This increased access waiting time will cause a difficulty if it is an essential target to decrease the processor processing speed.
Furthermore, in the technology disclosed in Japanese Patent laid-open gazette No. SHO 60-183652, if the data fixedly assigned to the cache memory is one that is frequently updated by other processors, invalidating processing is also frequently brought about on the subject data. Therefore, the cache hit ratio will be lowered, and transaction on the shared memory bus will be increased in order for reading the data after the updating. If transaction on the shared memory bus is increased, the access waiting time for the shared memory will also be increased correspondingly.
On the other hand, in the technology disclosed in Japanese Patent laid-open gazette No. HEI 8-30510, although the processor requiring no snoop can access the cache memory in an ordinary manner, the processor cannot cope with a problem of lowering in the cache hit ratio. Thus, transaction on the shared memory bus for reading data will also be increased.