The invention relates to the manipulation of picture data by digital techniques.
It is known from British Pat. No. 1,568,378 (U.S. Pat. No. 4,148,070) to provide an arrangement for manipulating picture data by storing the data in a frame store and giving random access to this stored video data during the video blanking time to process this data with an algorithm. FIG. 1 shows such an arrangement.
In the video processing system of FIG. 1, a composite video signal is received at input 9 and applied to video input port 12 which separates the sync pulses present on the incoming video. The incoming video is converted from analogue to an 8 bit digital word within input port 12 and the digitized output 13 is applied to a frame store and control 15. The detected sync pulses on the incoming signal are used within port 12 to provide timing information for clocking the analogue to digital converter and timing information is also provided at output 14 for the frame store and control 15. External syncs (genlock) may be provided at input 11 to provide the necessary timing information if required.
The digitized video samples (picture points) are stored in a large number of memory locations within the frame store and the addresses of these locations are accessed by the store control in time relation to the timing information from the output of video input port 14.
The digital video held in the frame store is read continuously to the input 18 of a video output port 19 which converts the digitized video data to analogue form and adds sync pulses from an internal generator to provide a composite video signal at output 20.
The sync pulses generated also provide timing control for addressing the store locations to read out the stored data. External syncs (read genlock) may be applied to port 19 if required. The composite video can be displayed on a conventional T.V. monitor 22.
The basic conversion, storage and reconversion of the video signals can be modified by means of a computer 24 and computer address and control unit 25. The output 27 of control unit 25 is received by input port 12. Control unit 25 under computer control can adjust the number of bits in a word to be used (i.e. up to 8 bits) and also decide whether the entire frame is stored. The computer 24 has access via control 25 control data line 27 to the store 15. Computer address information from control 25 is received by input 26 of the store.
The computer therefore is capable of addressing any part of the store, can read out the data and modify the data and re-insert it via video input port 12.
The computer control data line 27 is also connected to output port 19 which control can select for example the field to be displayed and the number of bits to be used. Any required computer peripheral 23 can be attached to the I/O buses of the computer 24.
Instead of using the computer to modify the data a video processor 28 is provided which contains processing hardware. The processor 28 receives the digitized video from port 12 at input 16 and the digitized video from the store at input 17. After processing, the data from output 29 can be applied to the video input port 12.
The above system is concerned therefore with storing video data in a digital form in a frame store which data is basically Raster in format. This data may be processed under software control or completely new data may be added. Instructions for the addition and processing of data come from the system computer via control 25. The asynchronous nature of the system allows operation over a very wide range of frame rates from standard T.V. through slow scan systems such as electron microscopes to line scan cameras. Non-raster type formats such as spiral and polar scans could be entered via the computer interface. The operation of the above system requires timing information which is extracted from the sync information (write genlock), contained in the composite video input. The video information is digitized by converting each picture point to an 8 bit word to give 256 possible levels (e.g. 256 shades of grey). The digitized data is written into locations, specified by an address, within the frame store. The timing information extracted from the sync information is used to define the address. This timing information gives positional information (start of line, end of field etc) to enable each picture point to be written into the frame store in its correct position.
The frame store used in this known arrangement may be of the type disclosed in British Pat. No. 1,568,379 (U.S. Pat. No. 4,183,058) which comprises sector cards each made up of N channel dynamic MOS R.A.M. integrated circuits. The store structure is related to that of the T.V. raster and may be considered as two cubes. Each cube holds one of the two fields that make up a frame. Each field consists of 256 lines, each line containing 512 picture points. Each picture point is stored as an 8 bit word so the store has 8 bit planes. Alternate lines of the frame are stored in alternate fields. The two halves of the frame store may be used independently to store two separate frames, the resolution of which will be half the normal. Depending upon the resolution required each field may also store separate pictures (up to 8 separate 1 bit resolution pictures). The frame store can accept video at 10 MHz (15 MHz max) sampling frequency and reproduce it for display at the same rate.
The reading process from the store to the display is uninterrupted by any computer demands. For the purpose of reading from or writing into the store the access time of the memory is 67 nSec therefore enabling a standard T.V. picture to be easily accommodated from the 512 samples in a line. The computer can only gain access to the frame store during the line blanking period. The computer has random access and specifies its address in an array form. The selected array may be of any size from single point to the whole store. The array selected may also be in any position within the store. Thus by merely identifying the top left hand corner of the rectangle and the length of the two sides any address area is accessible. Computer data is fed in at a slow rate (typical cycling frequency of the computer is from 500 KHz depending upon whether an array is being addressed or individual picture points) and is buffered to be fed into the frame store at the transfer rate of the system, typically 10 MHz. Thus data is speeded up for writing out into the store and slowed down to read it back to the computer.
The above system could be expanded as explained in the aforementioned patent to provide full RGB colour by the addition of two more frame stores. Such colour pictures could be either entered into the system on a frame sequential basis or alternatively three input video ports could be provided.