Field
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to data processing systems supporting multi-element comparison and then multi-element addition operations.
Prior Art
It is known to provide for “lane reduction” operations within data processing systems that return the signed or unsigned sum of elements of a vector or the minimum or maximum of all the elements in the vector. A conventional way of implementing such operations is to separately provide a carry save reduction tree to perform the addition and circuitry to perform a series of full-word length element comparisons to determine the minimum and maximum values. Such an approach consumes circuit resource due to the provision of separate circuitry implementing the different types of operation. Furthermore, the full-word length element comparisons are relatively slow to perform.