In the fairly recent past, integrated circuit (IC) manufacturers have used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it presents certain challenges, including rapid diffusion into silicon oxide where it degrades the insulating electrical properties even at very low concentrations. This and other issues have been addressed by “Damascene” processing.
In a Damascene process an interconnect pattern is first lithographically defined in a layer of dielectric and etched to form trenches and vias. Next the vias and trenches are coated with a diffusion barrier material, typically a nitride of a refractive metal such as tantalum and/or a nitride thereof such as tantalum nitride or titanium nitride. The diffusion barrier blocks diffusion of copper atoms into the dielectric layers. Copper is then deposited to fill the trenches and vias to form interconnect lines and the excess metal is removed by, for example, chemical mechanical polishing (CMP). Damascene processes can be categorized into two types: single Damascene and dual Damascene processes. A single Damascene process produces a metallization layer from two separate dielectric layers, the first being patterned to define interconnect holes or vias of the layer and the second being patterned to define interconnect horizontal line paths. In each stage, the layer in process is first patterned and then etched to define the vias or horizontal trenches. These are then coated with a diffusion barrier material and filled with copper. In a dual Damascene process, both the vias and trenches are patterned in dielectric prior to depositing the barrier material and filling with copper. It is worth noting that frequently a combination of single and dual Damascene processing is used to create an interconnect structure. For example, the first metallization layer is made by a single Damascene process, while the higher metallization layers (e.g., M2–M8) are made by dual Damascene processes.
One of the difficulties in successfully integrating either type of Damascene process involves coverage of diffusion barrier material. A variety of physical vapor deposition (PVD) techniques, such as ionized PVD, are conventionally used for depositing diffusion barrier material since these techniques provide high quality films. These PVD techniques, however, result in thick film bottom coverage in vias and trenches. Because the barrier material has a higher resistivity than copper, its thickness should be minimized at the bottoms of the vias and trenches. It is important, however, to have enough diffusion barrier material coverage at the sidewalls of the vias and trenches to sufficiently prevent copper diffusion into surrounding dielectric.
For dual Damascene processing in particular, methods for selectively etching a portion of the diffusion barrier at the via bottoms in order to expose the lower copper line have been employed. One such approach is generally described in U.S. Pat. No. 6,287,977 to Hashim et al. and U.S. Pat. No. 5,985,762 to Geffken et al. By completely etching away the barrier in the via bottom, the subsequent copper inlay can be deposited directly onto the lower copper line. These methods, however, are problematic in that they are not selective enough. That is, they remove barrier material from undesired areas as well, such as the corners (edges) of the via, trench, and field regions. This can destroy critical dimensions of the via and trench surfaces (faceting of the corners) and unnecessarily exposes the dielectric to plasma. This may lead to dielectric damage, such as critical dimension loss, increase in dielectric constant (with concomitant negative impact on device speed), and poor adhesion to the barrier layer. These problems will be encountered with the method described in the Geffken et al. patent.
To address these problems, methods that provide selective etching of via bottoms are described in U.S. Pat. No. 6,607,977 issued Aug. 19, 2003, incorporated by reference above. These methods involve etching a portion of the diffusion barrier material at the bottoms of vias without fully etching through the barrier material such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing diffusion barrier material elsewhere on the wafer, particularly on the sidewalls of the vias. U.S. Patent Application No. 60/379,874 filed May 10, 2002, also incorporated within above, describes methods to address these problems in an alternative way. These methods completely etch through the diffusion barrier material at the bottoms of vias to expose a part of the underlying metal while depositing diffusion barrier material particularly on the sidewalls of the vias. Subsequently, the process deposits another layer of diffusion barrier material to cover the bottoms of the vias. These methods are especially useful in cases where unlanded vias exist in the wafer.
While the aforementioned methods minimize the amount of diffusion barrier material on via bottoms while maintaining adequate barrier material on via sidewalls, they can be handicapped by requiring a relatively long time to etch relatively thick sections of barrier sometimes found on the via bottoms. Thick barrier sections are commonly found in features having low aspect ratios (ratio of height to width) such as the trenches employed in single Damascene processes. Generally, in Damascene processes, trenches have quite low aspect ratios in comparison to vias. For example, trench aspect ratios are frequently less than about 2:1, while via aspect ratios can be as high as 3:1 in current technology. Barrier material deposits more thickly on the bottoms of low aspect ratio features than on the bottoms of high aspect ratio features. Further, due to only the one-dimensional confinement in trenches, the deposition rate (coverage) at the trench bottoms is high, often comparable to that in the field. Often the barrier thickness at the bottom of a low aspect ratio feature (such as a trench encountered in a single Damascene process) will be >80% of the thickness found in the field region of the structure.
Unfortunately, processes that selectively etch barrier from the bottom of a feature while retaining barrier on the field regions generally etch material at the bottom rather slowly. Thus, the step of removing barrier at the trench bottoms can require a long time. This can severely impact wafer throughput and may have consequences on the tool performance.
What are therefore needed are improved methods of forming effective diffusion barriers on integrated circuits structures having low aspect ratio features, such as trench features commonly found in structures produced by single Damascene processing.