1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device as well as a reticle and a wafer used therein, in particular to a method of manufacturing a semiconductor device wherein particles caused by cutting of a conductive layer are not scattered at the time of dicing during assembly, a reticle used in the exposure steps of this process and a wafer on which patterning is carried out in such a process.
2. Description of the Background Art
A conventional method of forming a pattern on a wafer by using photolithographic technology is described. A reticle is used in a photolithographic process for transcribing a predetermined pattern to a resist. As shown in FIG. 29, a plurality of chip pattern regions 121 are formed in a reticle 120 in order to form chip products.
In addition, dicing line pattern regions 122 are formed in order to partition the plurality of chip pattern regions 121. Moreover, peripheral dicing line pattern regions 123 and 124 are formed along the outer periphery of the reticle 120.
In the dicing line pattern regions 122, a mark for adjusting the alignment or a TEG (Test Element Group), for example, for testing the electrical characteristics are arranged. These dicing line pattern regions 122 and peripheral dicing line pattern regions 123 and 124 allow dicing line regions, which are necessary for cutting off a plurality of chip products, respectively, to be patterned onto a wafer.
The widths of the dicing line regions on the wafer are required to be the widths of several tens of a xcexcm (for example, approximately 60 xcexcm) at the minimum, taking into account the dispersion of the width of a cutter blade used for the dicing, the position of the cutter blade at the time of the dicing, or the like.
Here, the widths of the peripheral dicing line pattern regions 123 and 124 are set at the widths of two major types in order to make reduce the ratio (occupying ratio) of the dicing line regions in the wafer plane. In this case, the widths of the peripheral dicing line pattern regions 123a and 123b, which are positioned around the outer periphery of the adjoining two sides are set at a narrower width than the width of the peripheral dicing line pattern regions 124a and 124b positioned around the outer periphery of the other adjoining two sides. For example, the width of the peripheral dicing line pattern region 123a is several xcexcm.
Next, exposure steps in the photolithographic process using the above reticle 120 are described. The reticle 120 is mounted in an exposure unit wherein an exposure light irradiates (is shot at) the resist formed on the wafer via the reticle 120 in sequence.
By means of one shot, a pattern corresponding to the reticle 120 is transcribed onto the wafer. Thereby, as shown in FIG. 30, the peripheral dicing line pattern region 123a part of the reticle 120 becomes a dicing line region 223a which has the width Xc. The peripheral dicing line pattern region 123b part becomes the dicing line region 223b which has the width Yc. The peripheral dicing line pattern region 124a part becomes the dicing line region 224a which has the width Ya. The peripheral dicing line pattern region 124b part becomes the dicing line region 224b which has the width Xa. The dicing line pattern region 122a part becomes the dicing line region 222a which has the width Xb. The dicing line pattern region 122b part becomes the dicing line region 222b which has the width Yb.
Next, as shown in FIG. 30, the next shot is carried out at the position wherein the outer periphery of the dicing line region 224b, which corresponds to the peripheral dicing line pattern region 124b of the reticle 120, approximately agrees with the outer periphery of the dicing line region 223a resulting from the first shot.
At this time, the width of the peripheral dicing pattern region of the reticle 120, in particular, is set so that the width gained by combining the width of the dicing line region 223a, formed through the first shot, and the width of the dicing line region 224b, formed through the next shot, becomes approximately equal to the width Xb.
The same positional relationships are used for the exposure in the next shot and in the shot after that. Here, though in FIG. 30 only the X direction is shown, the same positional relationships are used for carrying out the exposure in the Y direction. In addition, the peripheral region of the wafer wherein a chip formation region is only partially formed through the first shot does not undergo exposure processing.
In this manner, by irradiating a wafer with an exposure light (by giving a shot of an exposure light to a wafer) in sequence, chip formation regions 102 and dicing line regions are formed in the wafer 101 as shown in FIG. 31. The conventional exposure steps are carried out in the above manner.
In the above described exposure method using the reticle 120, however, the problem arises as shown in the following. At the time of transcribing chip patterns onto a wafer, as shown in FIG. 30, the next shot is carried out under the positional relationships where the outer periphery of the dicing line region 224b, which corresponds to the peripheral dicing line pattern region 124b of the reticle 120, approximately agrees with the outer periphery of the dicing line pattern region 223a resulting from the first shot.
Therefore, regions which correspond, only, to the peripheral dicing line pattern region 123a are transcribed between, for example, the last chip formation regions 102a in the X direction and the wafer peripheral region P as shown in FIG. 31. The same conditions apply to the last chip formation regions 102b in the Y direction.
In addition, as described above, since the entire chip formation region is not formed in the wafer peripheral region P, the resist, which does not undergo exposure processing and is not patterned, remains in the wafer peripheral region P.
In the case that a predetermined etching process is carried out based on such exposure processing, a dicing line region D (223a), which corresponds, only, to the peripheral dicing line pattern region 123a, is formed between the chip formation region C (102a) and the wafer peripheral region P, as shown in FIG. 32.
Then, in the wafer peripheral region P, the film formed in each step is not patterned and remains in the unchanged condition.
As described above, as for the width of a dicing line region, generally the widths of several tens of a xcexcm is required. As shown in FIG. 32, however, the width of the dicing line region D (223a) formed between the chip pattern region C (102a), positioned in the outermost periphery, and the wafer peripheral region P is approximately a few xcexcm.
The dicing line region D is not formed with the sufficient width required for dicing. Therefore, in the dicing at the time of the actual assembly process as shown by the arrow 116, the wafer peripheral region P, practically, is diced.
On the other hand, the film formed in each step remains as it is in the wafer peripheral region P. Among these films, conductive films 111 and 113 made of aluminum, for example, for forming wires are included. Therefore, when this wafer peripheral region P is diced, the conductive films 111 and 113 are also diced so that particles, resulting from the cutting of the conductive films 111 and 113, are generated.
In the case that a wire bonding is carried out in the assembly process under the condition where the particles resulting from the cutting of the conductive films 111 and 113 are included in the system, in some cases wires form an electrical short circuit due to the scattered particles resulting from the cutting of the conductive films 111 and 113. Therefore, a chip product that is free of defects becomes a defective chip, which becomes a factor leading to a lowering of the yield of the products.
In addition, it also becomes the cause of the shortening of the longevity of the cutter since the blade of the cutter is damaged through dicing.
In order to deal with such a problem, measures are considered to ensure that the patterns are transcribed onto the entire surface of the wafer including the wafer peripheral region. On the other hand, as shown in FIG. 31, a wafer identifying mark 103 is created for distinguishing the wafer. This wafer identifying mark 1031 is formed by providing unevenness on the surface of the wafer through a laser blow.
Therefore, when the patterns are transcribed onto the entire surface of the wafer, the patterns are, also, formed in the wafer identifying mark 103 part and the disadvantage that the wafer cannot be identified because the wafer identifying mark 103 cannot be read out in the case that the wafer is sorted by a semiconductor production unit or in the wafer test (WT) process or the assembly process.
In addition, in the case that the patterns are formed on the entire surface of the wafer, the patterns which are formed in the wafer peripheral region, particularly, peel off and the peeled off patterns, by becoming attached to the wafer, become a factor causing a lowering of the yield.
In addition, a method can be considered wherein, by covering the dicing line pattern regions of the reticle using a blind function of the exposure unit (stepper unit), the patterns for these regions are not formed on the wafer.
In this case, however, it becomes necessary to adjust the position of the blind for some positions of the shots to the wafer so that the throughput is lowered.
According to the above, no effective methods to solve the above described problem have been found.
In addition, at the time of the cutting off, through dicing, of the chip formation regions formed in the wafer from each other, in some cases wires form an electrical short circuit due to the scattered particles resulting from the cutting of the marks, such as a conductive alignment mark formed in the dicing region.
The present invention is provided to solve the above problems and one purpose thereof is to provide a method of manufacturing a semiconductor device wherein the conductive films can be restricted from scattering at the time of the dicing of a wafer. Another purpose is to provide a reticle used in such a process for a semiconductor device. Still another purpose is to provide a wafer gained through such a process for a semiconductor device.
A method of manufacturing a semiconductor device according one aspect of the present invention has the step of forming a conductive layer on a wafer as a semiconductor substrate, the step of resist application, the step of exposure, the step of development and the step of forming a conductive region. In the step of resist application, a resist is applied to the conductive layer. In the step of exposure, an exposure light is sequentially irradiated onto a resist positioned on a plurality of chip formation regions for forming semiconductor chips, respectively, in the wafer via a predetermined reticle. In the step of development, a development process is carried out on the resist after the step of exposure and, thereby, a resist pattern for patterning the conductive layer is formed. Conductive regions are formed by applying etching to the conductive layer by using the resist pattern as a mask. The step of exposure includes the step of carrying out a predetermined processing of preventing the resist from remaining on the regions cut through by the dicing provided in the region outside of the chip formation regions positioned in the outermost periphery among the plurality of chip formation regions.
According to this method, a predetermined process is carried out so that the resist is prevented from remaining on the region cut in the dicing provided in the region outside of the chip formation regions positioned in the outermost periphery in the step of exposure. Thereby, the conductive layer is removed in the region cut in the dicing at the time of forming conductive regions by applying etching to the conductive layer. As a result, at the time when the region cut in the dicing is diced, there is no scattering of particles, resulting from the cutting of the conductive layer, so that an electrical short circuit formed by wires can be prevented from occurring at the time of wire bonding in the assembly process.
Preferably, a negative resist is used as a resist in the step of resist application and no exposure light is irradiated, according to a predetermined process, in the step of exposure onto the region outside of the chip formation regions positioned in the outermost periphery.
Thereby, no conductive layer remains in the region outside of the chip formation regions positioned in the outermost periphery. As a result, the particles resulting from the cutting of the conductive layer can be prevented from scattering at the time of the dicing of the region cut by dicing.
In addition, preferably, as a predetermined process in the step of exposure, after an exposure light is sequentially irradiated onto the resist positioned on the plurality of chip formation regions, a spot of an exposure light is irradiated along the border between the chip formation regions positioned in the outermost periphery and the region outside of those chip formation regions positioned in the outermost periphery.
Thereby, the resist pattern is not formed in the region cut by dicing and the conductive layer is removed. As a result, particles resulting from the cutting of the conductive layer can be prevented from scattering at the time of the dicing of the region cut by dicing.
More preferably, a dummy reticle wherein no pattern is formed in the region outside of the chip formation regions positioned in the outermost periphery, is used to carry out the exposure as a predetermined process in the step of exposure.
Thereby, the conductive layer does not remain in the chip formation regions positioned in the outermost periphery. As a result, particles resulting from the cutting of the conductive layer can be prevented from scattering at the time of the dicing of the region cut by dicing.
Preferably, as a predetermined process in the step of exposure, a reticle wherein a peripheral dicing line pattern region which has a pattern width required for securing the region to be cut by dicing is formed along the outer periphery is used as a predetermined reticle and, at the time when exposure is carried out in sequence using this reticle, exposure is carried out in the position where the peripheral dicing line pattern region according to one exposure and the peripheral dicing line pattern region according to the next exposure, carried out following this exposure, overlap, at least partially, in a plane.
Thereby, a plurality of chip formation regions can be arranged at predetermined intervals and, at the same time, a region which corresponds to the peripheral dicing line pattern regions is formed in the region cut by dicing provided in the region outside of the chip formation region positioned in the outermost periphery. In this corresponding region, the conductive layer is removed through etching and this corresponding region has the width necessary for securing the region to be cut dicing and, thereby, at the time of the dicing of this corresponding region as the region cut by dicing, particles resulting from the cutting of the conductive layer do not scatter off.
In addition, preferably, in the step of exposure, the peripheral dicing line pattern regions of the reticle are formed so as to have substantially the same width and exposure is carried out so that the peripheral dicing line pattern region resulting from one exposure and the peripheral dicing line pattern region resulting from the next exposure following this exposure are positioned so as to overlap almost completely in a plane.
In this case, a region with a greater width can be secured as the region corresponding to the peripheral dicing line pattern region and, thereby, at the time when this corresponding region is diced as the region cut by dicing, particles resulting from the cutting of the conductive layer can be prevented, without fail, from scattering off.
More preferably, no substantial pattern is formed in this peripheral dicing line pattern region.
Thereby, no patterns for marks such as an alignment mark made of a conductive layer is formed and, therefore, at the time of dicing particles resulting from the cutting of such a pattern do not scatter off.
A reticle according to another aspect of the present invention is a reticle used in the photolithographic process which includes a peripheral dicing line pattern region, that is formed along the outer periphery, for gaining the pattern width that is necessary for securing the region cut by dicing through one exposure.
This reticle is a reticle used in a process for a semiconductor device according to the present invention. In this structure, as described above, the conductive layer does not remain in the region cut by dicing so that particles resulting from the cutting of the conductive layer do not scatter off at the time of dicing.
Preferably, a plurality of chip pattern regions are provided for forming a semiconductor device and the plurality of chip pattern regions are partitioned from each other by dicing line pattern regions where the width of the dicing line pattern regions and the width of the peripheral dicing line pattern region are substantially the same width.
Thereby, as described above, the width of the regions cut by dicing is broadened so that particles resulting from the cutting of the conductive layer can be prevented, without fail, from scattering off at the time of dicing.
A first wafer according to still another aspect of the present invention includes a plurality of chip formation regions for forming semiconductor devices and the regions cut by dicing. The plurality of chip formation regions, which are partitioned from each other by the dicing line regions, are formed on the surface on the wafer. The regions cut by dicing are formed in the region outside of the chip formation regions positioned in the outermost periphery among the plurality of chip formation regions. Then, substantially, conductive regions are not provided, at least, in these regions cut by dicing so that, substantially, only insulating layers are positioned.
This wafer is a wafer gained through a process for a semiconductor device according to the present invention. In this structure, conductive regions are not, substantially, provided in the regions cut by dicing. As a result, particles resulting from the cutting of the conductive regions do not scatter off at the time of the dicing of these regions and wires can be prevented from forming an electrical short circuit at the time of wire bonding.
Preferably, substantially, only insulating layers are positioned in the region outside of the chip formation regions positioned in the outermost periphery.
Thereby, particles resulting from the cutting of the conductive regions can be prevented, without fail, from scattering off at the time of the dicing of the regions cut by dicing.
A second wafer according to still another aspect of the present invention, includes a plurality of chip formation regions for forming semiconductor devices as well as a plurality of pad electrodes and conductive regions. The plurality of chip formation regions for forming semiconductor devices are formed on the surface on the wafer and are partitioned from each other by the dicing line regions. The plurality of pad electrodes are formed in the chip formation regions and are arranged at predetermined intervals. The conductive regions are formed in the dicing line regions. Further, the dimensions of those conductive regions are smaller than the predetermined intervals.
In this structure, at the time of the dicing of the dicing line regions provided between the plurality of chip formation regions, though particles resulting from the cutting of the conductive regions provided in these dicing line regions scatter off, wires bonded to the neighboring pad electrodes can be prevented from forming an electrical short circuit created by the above particles resulting from the cutting because the sizes of these conductive regions are shorter than the intervals between the pad electrodes.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.