1. Field of the Invention
Example embodiments of the present invention relate to a non-volatile memory device and to a method of manufacturing the same. More particularly, example embodiments of the present invention relate to a method of manufacturing a non-volatile memory device with increased integration by simultaneously forming a common source line and gate structures.
2. Description of the Related Art
Semiconductor memory devices may be divided into volatile memory devices and non-volatile memory devices. The volatile memory devices, e.g., dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, may have a relatively rapid response speed but may lose stored data over time. On the other hand, the non-volatile memory devices, e.g., flash memory devices or electrically erasable programmable read only memory (EEPROM) devices, may store data for a long time but may have a relatively slow response speed. The non-volatile memory devices, e.g., flash memory device, may be employed in various electronic devices, e.g., cellular phones, MP3 players, USB memory devices, and so forth.
In a conventional flash memory device data may be electrically stored in or erased from the flash memory device through Fowler-Nordheim tunneling or channel hot electron injection. The flash memory device may be classified into a NAND type non-volatile memory device and a NOR type non-volatile memory device. In the NAND type non-volatile memory device, a plurality of cell transistors may be combined to provide a unit string, so the unit string may be connected in series between a bit line and a ground line. In the NOR type non-volatile memory device, each cell transistor may be connected in parallel between a bit line and a ground line.
A conventional cell transistor of the NAND type non-volatile memory device may include a plurality of gate structures, a common source line, and a contact. The common source line and the contact, however, may have different structures, so formation thereof may not be performed simultaneously via a single process. In particular, a first insulating interlayer may be formed on a substrate to cover the gate structures, and a common source line and a second insulating interlayer may be formed sequentially on the first insulating interlayer. A contact hole may be formed through the first and second insulating interlayers, followed by deposition of a conductive material in the contact hole to form a contact.
Formation of the contact hole by etching two insulating interlayers may result in a contact hole having an increased length, thereby having an increased aspect ratio. As such, the contact may not be properly formed in the contact hole, thereby reducing reliability and electrical characteristics of the conventional non-volatile memory device. In addition, formation of the contact hole by etching two insulating interlayers may increase manufacturing process time. Further, wiring lines adjacent to the contact hole may require increased distance therebetween to facilitate formation of the contact hole between the wiring lines, thereby reducing integration degree of the non-volatile memory device and complicating processes for manufacturing the non-volatile memory device.