The present invention relates to a semiconductor device provided with a p-n junction diode and a method of forming the same, and more particularly to a semiconductor device having both a metal oxide semiconductor field effect transistor and a p-n junction diode for protecting the transistor.
The semiconductor device having the MOS field effect transistor is provided with a p-n junction diode for preventing the MOS field effect transistor particularly a gate insulation film from being broken due to electrostatic discharge or a surge current and a surge voltage. It had been known that this semiconductor device is fabricated as follows. FIGS. 1A and 1B are fragmentary cross sectional elevation views illustrative of a semiconductor device provided with both a metal oxide semiconductor: field effect transistor and a p-n junction diode in sequential steps involved in the conventional fabrication method. The semiconductor device has a metal oxide semiconductor field effect transistor region 121 and a p-n junction diode region 122.
With reference to FIG. 1A, an n+-type epitaxial layer 102 is formed on a top surface of a silicon substrate 101. An nxe2x88x92-type well region 103 is selectively formed in an upper region of the n+-type epitaxial layer 102. Device isolation layers 106 are selectively formed in upper regions of the nxe2x88x92-type well region 103 so that the device isolation layers 106 define both a metal oxide semiconductor field effect transistor region 121 and a p-n junction diode region 122. The metal oxide semiconductor field effect transistor region 121 comprises a part of the n-type well region 103 surrounded by the device isolation layers 106. The p-n junction diode region 122 also comprises another part of the nxe2x88x92-type well region 103 surrounded by the device isolation layers 106.
In the metal oxide semiconductor field effect transistor region 121, a gate insulation film 108 is selectively provided on the top surface of the nxe2x88x92-type well region 103. A gate electrode 107 is provided on the gate insulation film 108. A pair of pxe2x88x92-type lightly doped diffusion regions 113a and 113b are selectively formed in upper regions of the nxe2x88x92-type well region 103 by a self-alignment technique. Side wall insulation films 105a and 105b are formed on side walls of the gate electrode 107.
With reference to FIG. 1B, an ion-implantation process is then carried out by use of the gate electrode 107 and the side wall insulation films 105a and 105b as masks for selectively introducing a p-type impurity into both the metal oxide semiconductor field effect transistor region 121 and the p-n junction diode region 122. As a result, in the metal oxide semiconductor field effect transistor region 121, source and drain p+-type diffusion regions 104a and 104b are selectively formed in the nxe2x88x92-type well region 103 so that the source and drain p+-type diffusion regions 104a and 104b are self-aligned to the gate electrode 107 and the side wall insulation films 105a and 105b, whereby lightly doped diffusion regions 113a and 113b remain only under the side wall insulation films 105a and 105b. The source and drain p+-type diffusion regions 104a and 104b are deeper than the lightly doped diffusion regions 113a and 113b. Concurrently, in the p-n junction diode region 122, a p+-type region 104c is selectively formed in the nxe2x88x92-type well region 103. The p+-type region 104c is defined by the device isolation layers 6. The p+-type region 104c has the same depth as the source and drain p+-type diffusion regions 104a and 104b. In the metal oxide semiconductor field effect transistor region 121, a source region comprises the p+-type diffusion region 104a and the lightly doped-diffusion region 113a, whilst a drain region comprises the p+-type diffusion region 104b and the lightly doped diffusion region 113b. In the p-n junction diode region 122, the p+-type region 104c and the nxe2x88x92-type well region 103 form a p-n junction diode which has a p-n junction formed on an interface between the p+-type region 104c and the nxe2x88x92-type well region 103.
Even illustrative is omitted, an inter-layer insulator is further formed entirely which extends over both the metal oxide semiconductor field effect transistor region 121 and the p-n junction diode region 122. The inter-layer insulator not illustrated extends over the device isolation layers 106, the side wall insulation films 105, the gate electrode 107 and the source and drain p+-type diffusion regions 104a and 104b as well as over the p+-type region 104c. Contact holes not illustrated are formed in the inter-layer insulator so that the contact holes reach the gate electrode 107 and the source and drain p+-type diffusion regions 104a and 104b as well as the p+-type region 104c respectively. Metal plugs and metal interconnections not illustrated are formed, wherein the metal plugs are formed in the contact holes so that the metal plugs are in contact with the gate electrode 107 and the source and drain p+-type diffusion regions 104a and 104b as well as the p+-type region 104c, whilst the metal interconnections extend over the inter-layer insulator whereby the metal interconnections are electrically connected through the metal plugs in the contact holes to the gate electrode 107 and the source and drain p+-type diffusion regions 104a and 104b as well as the p+-type region 104c. 
In accordance with the conventional method of forming the semiconductor device, a distance xe2x80x9cdxe2x80x9d of the p-n junction of the diode or the interface between the p+-type region 104c and the nxe2x88x92-type well region 103 from a bottom of the nxe2x88x92-type well region 103 or an interface between the nxe2x88x92-type well region 103 and the n+-type epitaxial layer 102 depends on a difference of a depth of the nxe2x88x92-type well region 103 from a depth of the p+-type region 104c. The p+-type region 104c serves as an anode of the p-n junction diode. The p+-type region 104c is formed in the p-n junction diode region 122 by the same ion-implantation process for forming the source and drain p+-type diffusion regions 104a and 104b in the metal oxide semiconductor field effect transistor region 121. Namely, the depth of the p+-type region 104c in the p-n junction diode region 122 is the same as the depth of the source and drain p+-type diffusion regions 104a and 104b in the metal oxide semiconductor field effect transistor region 121. The depth of the p+-type region 104c in the p-n junction diode region 122 is decided by the depth of the source and drain p+-type diffusion regions 104a and 104b in the metal oxide semiconductor field effect transistor region 121. The depth of the source and drain p+-type diffusion regions 104a and 104b and the depth of the nxe2x88x92-type well region 103 are also decided in consideration of the required dimensions and performances of the metal oxide semiconductor field effect transistor formed in the metal oxide semiconductor field effect transistor region 121. Namely, the distance xe2x80x9cdxe2x80x9d in the p-n junction diode region 122 is decided depending upon the required dimensions and performances of the metal oxide semiconductor field effect transistor formed in the metal oxide semiconductor field effect transistor region 121. A breakdown voltage of the p-n junction diode formed between the p+-type region 104c and the nxe2x88x92-type well region 103 depends upon the distance xe2x80x9cdxe2x80x9d in the p-n junction diode region 122. Namely, the breakdown voltage of the p-n junction diode in the p-n junction diode region 122 is decided depending upon the required dimensions and performances of the metal oxide semiconductor field effect transistor formed in the metal oxide semiconductor field effect transistor region 121. Normally, the depth of the nxe2x88x92-type well region 103 is about 900 nanometers, whilst the depth of the source and drain p+-type diffusion regions 104a and 104b and the p+-type region 104c is about 300 nanometers. The distance xe2x80x9cdxe2x80x9d is large, for example, about 600 nanometers. The large distance xe2x80x9cdxe2x80x9d causes the high breakdown voltage of the diode in the p-n junction diode region 122. The reason why the p-n junction diode is formed in the p-n junction diode region 122 is to cause a breakdown of the p-n junction diode so as to prevent the metal oxide semiconductor field effect transistor from being broken due to the electrostatic discharge or the surge current and voltage. If the breakdown voltage of the p-n junction diode formed in the p-n junction diode region 122 is high as the prior art, then this allows that the p-n junction diode shows no breakdown and in place the metal oxide semiconductor field effect transistor is broken by the electrostatic discharge or the surge current and voltage applications.
In the above circumstances, it had been required to develop a novel semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode free from the above problem.
Accordingly, it is an object of the present invention to provide a novel semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode free from the above problems.
It is a further object of the present invention to provide a novel semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode which has a reduced breakdown voltage.
It is a still further object of the present invention to provide a novel semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode which has a high capability of preventing the metal oxide semiconductor field effect transistor from being broken due to the electrostatic discharge or the surge current and voltage applications.
It is yet a further object of the present invention to provide a novel method of forming a semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode free from the above problems.
It is further more object of the present invention to provide a novel method of forming a semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode which has a reduced breakdown voltage.
It is moreover object of the present invention to provide a novel method of forming a semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode which, has a high capability of preventing the metal oxide semiconductor field effect transistor from being broken due to the electrostatic discharge or the surge current and voltage applications.
It is yet more object of the present invention to provide a novel method of forming a semiconductor device having a metal oxide semiconductor field effect transistor and a p-n junction diode which has a controllable breakdown voltage.
The present invention provides a semiconductor device having: a first semiconductor region of a first conductivity type having a first area and a second area; at least a diffusion region of a second conductivity type being provided on the first area and in an upper region of the first semiconductor region; and a p-n junction diode provided on the second area of the first semiconductor region, the p-n junction diode having a p-n junction comprising an interface between the first semiconductor region and a first impurity doped region of the second conductivity type selectively provided in an upper region of the first semiconductor region, wherein a first distance defined between a first bottom level of the first impurity doped region and a bottom level of the first semiconductor region is smaller than a second distance defined between a second bottom level of the at least diffusion region and the bottom level of the first semiconductor region.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.