A conventional non-volatile memory device retains data stored in memory cells even without power. Among conventional non-volatile memory devices, a flash memory electrically erases data of a cell by a package, and thus, may be used in computers, memory cards, etc.
Conventional flash memories may be classified as a NOR type or a NAND type according to the manner in which cells and bit lines are connected. Conventional NOR type flash memories may consume more power than NAND type memories, but may also operate at higher speeds. Because of the higher power consumption, however, achieving a relatively high degree of integration may be more difficult, than in NAND type flash memories, which consume less power.
FIG. 1 illustrates an array 110 of a conventional NAND flash memory. The memory cell array 110 may constitute a storage region for storing data or information.
Referring to FIG. 1, the memory cell array 110 may include a plurality of blocks. Each of the blocks may include a plurality of cell strings. Each of the cell strings may include a plurality of floating gate transistors M0 to M31. In each string, the floating gate transistors M0 to M31 may be connected in series between a string select transistor SST and a ground select transistors GST. One of a plurality of bit lines BL1 to BLm may be connected to a terminal of a corresponding string select transistor SST.
A plurality of word lines WL0 to WL31 may be arranged to intersect the NAND strings. Each word lines WL0 to WL31 may be connected to control gates of floating gate transistors M0 to M31, respectively. When a program/read voltage is applied to word lines WL0 to WL31, data may be programmed into or read from the corresponding floating gate transistors M0 to M31. The flash memory may further include a buffer circuit (not shown) for storing data on the memory cell array 110 or reading the stored data from the memory cell.
As is well known, a memory cell of a conventional NAND flash memory utilizes Fowler-Nordheim (F-N) tunneling current to program and erase data.
FIG. 2 is a sectional view of a cell string of the conventional NAND flash memory shown in FIG. 1. Referring to FIG. 2, a cell string may include a bit line 111 connected to a drain 112, a string select transistor 113, a ground select transistor 114, and a plurality of (e.g., 32) NAND flash memory cells 115. Each cell of a NAND flash memory may include a control gate CG, a floating gate FG, a source and a drain in a bulk or a P-well. A channel between the drain and the source may be defined in the bulk or the P-well.
A dielectric layer having an oxide/nitride/oxide (ONO) structure with a relatively high storage capacity may be formed between the control gate CG and the floating gate FG. A tunnel oxide layer having a structure sufficient for F-N tunneling may be formed between the floating gate FG and the bulk. According to this cell structure, dielectric capacity CONO (via the dielectric layer) exists between the control gate CG and the floating gate FG. Tunnel capacity Ctun (via a tunnel oxide layer) also exists between the floating gate FG and the P-well. A voltage of the floating gate FG may be determined by a word line voltage VWL applied to the control gate CG and a coupling ratio of the capacities CONO and Ctun. The word line voltage VWL for a program/erase/read operation may be distributed by the above capacities.
In this example, the dielectric capacity CONO may include capacity components between the control gate CG and the floating gate FG and capacity components of adjacent transistors. Likewise, the tunnel capacity Ctun may include capacity components between the floating gate FG and the bulk and capacity components of adjacent transistors. An electric field between the floating gate FG and the bulk (or, P-well), which may cause F-N tunneling during a programming operation, depends on a word line voltage VWL distributed according to the sizes of the dielectric capacity CONO and the tunnel capacity Ctun. A voltage Vtun applied between the floating gate FG and the bulk may be expressed as Equation 1 shown below.Vtun=VWLαcouple  Equation 1
In Equation 1, αcouple represents a coupling ratio, which may be expressed as Equation 2 shown below.
                              α          couple                =                              C            ono                                              C              ono                        +                          C              tun                                                          Equation        ⁢                                  ⁢        2            
As shown in Equations 1 and 2, the size of the tunneling voltage Vtun contributing to F-N tunneling may depend on the size of a coupling ratio αcouple. But, forming memory cells with the same coupling ratio αcouple in the same string/row of a conventional NAND flash memory may be relatively difficult and/or impossible because, in each string, cells adjacent to the string select line SSL and the ground select line GSL may have a coupling ratio different from (e.g., higher or lower than) the rest of the cells.
As described above, the capacity of each cell may include a capacity component related to an adjacent cell/select transistor. According to a string structure, a capacity component between cells may be different from the capacity component between select transistors. As a result, even if the same voltage is applied to each word line, the floating gate voltage Vtun induced in cells adjacent to a string/ground select line SSL/GSL may be different from the floating gate voltage Vtun induced in the rest of the cells.
In conventional NAND flash memories, program/erase speeds of word lines (e.g., WL0 or WL31) adjacent to the string/ground select line SSL/GSL may be different (e.g., drastically or substantially different) from the rest of the word lines.