The present invention relates generally to integrated circuit fabrication, and more particularly, to fabrication of integrated circuits on both sides of a semiconductor wafer for more efficient integrated circuit fabrication and for enhanced performance of integrated circuits.
As device densities continually increase on a semiconductor wafer, the trend is to incorporate multiple circuits into a single monolithic integrated circuit. For example, current computer systems run four or eight processors, and those plurality of processors are fabricated on a single monolithic integrated circuit. In the future, a computer system will likely run an even larger number of processors in a multiprocessor system. Incorporation of a larger number of processors into a single monolithic integrated circuit increases the volume on a semiconductor wafer occupied by the plurality of processors.
Referring to FIG. 1A, an integrated circuit such as a multiprocessor system is fabricated on an area 102 of a semiconductor wafer 104. Referring to FIG. 1B, a cross sectional view of the semiconductor wafer 104 along line Axe2x80x94A of FIG. 1A shows the area 102 having the integrated circuit fabricated on a first face 106 of the semiconductor wafer 104. In the prior art, integrated circuits are fabricated on only one side of a semiconductor wafer.
In the prior art where integrated circuits are fabricated on only one side of a semiconductor wafer, as larger numbers of integrated circuits for an electronic system are incorporated into a single monolithic integrated circuit, the volume on a semiconductor wafer occupied by the plurality of integrated circuits for the electronic system increases. Thus, fewer dies of electronic systems fit onto a semiconductor wafer with larger numbers of integrated circuits. The rate of manufacture of the number of dies fabricated per semiconductor wafer decreases.
However, more integrated circuits may need to be incorporated into a die as electronic systems advance in technology. Thus, a means for compactly fabricating a plurality of integrated circuits of an electronic system on a semiconductor wafer is desired.
Accordingly, a primary object of the present invention is to compactly fabricate integrated circuits of an electronic system on a semiconductor wafer by fabricating the integrated circuits of the electronic system on both sides of a semiconductor wafer.
In a general aspect of the present invention, a first face of an area of the semiconductor wafer is processed with an integrated circuit fabrication process step to fabricate part of a first integrated circuit thereon. In addition, a second face of the area of the semiconductor wafer is processed with the integrated circuit fabrication process step to fabricate part of a second integrated circuit thereon. The first face and the second face are processed for a plurality of integrated circuit fabrication process steps until the first integrated circuit is completely fabricated on the first face and the second integrated circuit is completely fabricated on the second face. The first face and the second face of the area of the semiconductor wafer may both be processed simultaneously or may be processed one face at a time depending on the fabrication process step. That area of the semiconductor wafer is then cut from the rest of the semiconductor wafer when the first integrated circuit is completely fabricated on the first face and when the second integrated circuit is completely fabricated on the second face such that the first integrated circuit and the second integrated circuit are on a die to be used within an electronic system.
The first integrated circuit may be interconnected with the second integrated circuit such that the first integrated circuit functionally interacts with the second integrated circuit within the electronic system.
The present invention may be used to particular advantage when the first integrated circuit includes at least one processor and when the second integrated circuit includes at least one processor. In that case, the die having the first integrated circuit and the second integrated circuit is used within a multiprocessor system.
With the present invention, the first face of the area of the semiconductor wafer and the second face of the area of the semiconductor wafer may both be processed simultaneously during an integrated fabrication process step which includes a selected one of wet cleaning, wet etching, thermal film deposition, LPCVD (Low Pressure Chemical Vapor Deposition) film deposition, drive-in diffusion doping, and rapid thermal annealing. Such simultaneous processing of both faces at one time results in more efficient fabrication of a larger area of the semiconductor wafer with less time. In addition, such simultaneous processing of both faces at one time reduces variations in fabrication parameters from wafer to wafer. Such higher uniformity from wafer to wafer results in better system performance for systems with multiple dies because of better matching between the multiple dies.
Alternatively, the first face of the area of the semiconductor wafer and the second face of the area of the semiconductor wafer may be processed one face at a time during an integrated circuit fabrication process step which includes a selected one of patterning, dry etching, implantation, PVD (Physical Vapor Deposition) film deposition, and CMP (Chemical Mechanical Polish). In that case the semiconductor wafer may be placed on an edge rim vacuum chuck such that the other side of the semiconductor wafer is not damaged while one side of the semiconductor wafer is being processed.
A first CPGA (Ceramic Pin Grid Array) package may be attached to the first face of the die with a first set of pins from the first CPGA package being coupled to pads from the first integrated circuit on the first face of the die. A second CPGA (Ceramic Pin Grid Array) package may be attached to the second face of the die with a second set of pins from the second CPGA package being coupled to pads from the second integrated circuit on the second face of the die.
In this manner, integrated circuits of an electronic system are fabricated onto both sides of a semiconductor wafer. Thus, as the number of integrated circuits in an electronic system increases, the integrated circuits are fabricated compactly on the semiconductor wafer, and the volume occupied by those integrated circuits on the semiconductor wafer is minimized. With fabrication of integrated circuits onto both sides of a semiconductor wafer, a larger number of electronic systems fit onto a semiconductor wafer such that the rate of manufacture of the number of dies fabricated per semiconductor wafer increases.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.