The present invention relates to a technology of mounting an integrated circuit (IC) chip (or simply “a chip”, below) on a substrate and particularly to a chip mounting structure in which a chip is mounted on a substrate having such a shape that a stress exerted on a flip-chip-connected chip is reduced.
In these years, with size reduction of semiconductor devices, the dielectric constant (k) of a material of interlayer insulators in the back end of line (BEOL) has been decreasing. However, a material of insulators having a low dielectric constant, such as SiCOH (hydroxyl silicon carbide), is porous and is thus very brittle. The interlayer insulating layer itself thus has a low mechanical strength and becomes separated due to a stress being exerted at the time of cooling after being subjected to flip chip mounting and reflow soldering.
Since a chip and a substrate on which the chip is mounted are connected together with a lead-free solder, which is harder and less ductile than a lead solder that has been used thus far, the stress exerted on the interlayer insulating layer due to a difference in coefficient of thermal expansion between the chip and the substrate has been increasing.
In addition, thinning of printed circuit boards employing, for example, organic substrates for the purpose of an improvement of electrical characteristics or a cost reduction as a result of reduction of the number of layers increases the warpage of the substrate, leading to an increase of the stress exerted on the interlayer insulating layer.
FIG. 1 roughly illustrates the state where the interlayer insulating layer is separated from an adjacent layer. A low-k layer 105 is disposed on the surface of a semiconductor substrate 100 made of a material such as silicon, an insulating layer 110 made of a material such as an oxide is disposed on the low-k layer 105, and a protective layer 115 made of a material such as photosensitive polyimide (PSPI) is disposed on the insulating layer 110. The protective layer 115 has an opening at a position corresponding to an electrode of the low-k layer 105 and an under-bump metallurgy (UBM) layer 120 is disposed in the opening. A bump 125 such as a solder is disposed on the UBM layer 120. When a stress is exerted on the bump 125 in the direction indicated with the arrow of FIG. 1, a crack 130 develops between the low-k layer 105 and the insulating layer 110 so as to separate these layers.
Japanese Patent Application Publication No. 5-47955 describes a support board disposed between a semiconductor device and a circuit board. Electrode terminals are disposed on the surface of the support board so as to face electrode terminals disposed on the peripheral portion of the semiconductor device. Electrode terminals electrically connected with the electrode terminals on the surface of the support board are arranged in a grid form on the back surface of the support board. The electrode terminals on the surface of the support board and the electrode terminals on the back surface of the support board are respectively connected, via bumps, with the semiconductor device and the circuit board. Thus, the stress that occurs due to a difference in coefficient of thermal expansion between the semiconductor device and the circuit board is dispersed into bumps arranged in the grid form, whereby malfunctions of a circuit device due to stress concentration are minimized.
In the technology of Patent Application Publication No. 5-47955, the stress exerted on the semiconductor device is reduced by dispersing the stress that occurs due to the difference in coefficient of thermal expansion between the semiconductor device and the circuit board into bumps arranged in the grid form on the back surface of the support board disposed between the semiconductor device and the circuit board. Since this technology involves disposition of the support board between the semiconductor device and the circuit board, an arrangement of electrode terminals on the back surface of the support board is limited to the grid form and is not allowed to be changed in accordance with the design of the circuit device.
Japanese Patent Application Publication No. 2002-100699 describes a semiconductor device in which a semiconductor chip has through-holes at corner portions and a reinforcement land having a ball bump on the connection side is formed through each through-hole. When the chip is mounted on a mounting substrate, the reinforcement lands are connected to the substrate so that the thermal stress exerted on circuit connection pads adjacent to the corners of the semiconductor chip attenuates, whereby separation or electrical disconnection of the circuit connection pads is minimized.
The technology of Japanese Patent Application Publication No. 2002-100699 involves formation of a reinforcement land at each corner portion of a semiconductor chip and occupation of an area for the reinforcement land at each corner portion of the semiconductor chip, whereby the use of the corner portions of the semiconductor chip is limited and thus the corner portions are not allowed to be used freely.