The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the subject matter of the present disclosure.
For the purpose of this disclosure, the term “bus signal” may include any signal that is propagated over an entire device—e.g., clocks, reset signals, enable signals, etc.—as well any signal that is propagated over less than an entire device, but over a portion of the device that encompasses multiple functional blocks of the device, including signals transmitted between those functional blocks.
As devices become larger, the number of bus signals grows, necessitating more buses, which consume device area that could otherwise be devoted to functional circuitry. At the same time, buses become longer, requiring the addition of buffers to meet signal slew and capacitance requirements, and the addition of samplers to meet any required clock frequency, in an arrangement sometimes referred to as “pipelining.” These additional components compound the problem, further increasing the portion of the device devoted bus signals.