1. Technical Field
The present invention relates to a printing device controller and a printing device, and particularly relates to a printing device controller and printing device provided with a first computational processing unit that performs overall control of the device as a whole and a second computational processing unit that consumes less power than the first computational processing unit.
2. Related Art
From an ecological standpoint, demands with respect to power conservation are increasing, and such demands apply to printers such as printing devices as well. While past types of power-saving modes, where power distribution to the primary control circuit portions such as a CPU is maintained while stopping the supply of power to other peripheral elements, enabled easy returns from the power-saving mode, and reducing power consumption in the primary control circuit portions in order to achieve further energy conservation is also coming into consideration. However, stopping the supply of power to the primary control circuit results in a problem whereby information stored in the cache of a processing circuit such as a CPU, setting values stored in the register of an integrated circuit for controlling the various elements, and the like are lost, and returning from the power-saving mode thus takes time.
In order to address this problem, measures for holding the CPU cache, the setting values stored in the registers of the various modules, and so on are being taken. For example, JP-A-2004-112718 discloses copying, when still operating in the normal mode prior to entering a power-saving mode, all or part of an operating system, basic application programs, and the like pre-stored in a ROM into an external RAM that is not powered down, and then reading out and executing the code, data, and so on from the external RAM during the process for returning from the power-saving mode.
Meanwhile, JP-A-2003-122461, for example, discloses dividing a semiconductor integrated circuit into an internal logic block and an input/output pad cell block, continuously linking the state of the D flip-flop in the internal logic block to the RS latch of the input/output pad cell block, and saving the state of the D flip-flop in the input/output pad cell block when the supply of power to the internal logic block is stopped during the power-saving state.
In the aforementioned JP-A-2004-112718 and JA-A-2003-122461, the information necessary for returning from the power-saving state is continuously backed up. While these techniques are useful because it is always possible to enter the power-saving mode, it is necessary to steadily increase the processing for making backups, provide a separate storage medium for making backups, and so on, resulting in unavoidable cost increases due to circuitry changes, increases in the circuit scale, improvements in processing capabilities so that the primary computational processes are not strained by the additional processing, and so on.