The present invention relates to a data encoding/decoding circuit and, more particularly, to a scrambler/descrambler for inhibiting access of data by tapping or illegal data access.
A data encoding/decoding circuit of this type is arranged according to one of the following three systems.
FIG. 1 is a block diagram of a conventional data encoding/decoding circuit of the first system. Referring to FIG. 1, a data encoding circuit 1 comprises a shift register 11, a random number generator 12 and an exclusive OR gate, i.e., an adder 13 of modulo 2 (to be referred to as an adder 13 hereinafter). In the data encoding circuit 1, the random number generator 12 generates a random number as a function of a value of the content of the shift register 11. Transmission data input to a terminal 14 is added to the random number by the adder 13 and appears as a transmission data output at a terminal 15. At the same time, the sum is supplied to the shift register 11. A data decoding circuit 2 comprises a shift register 21, a random number generator 22, and an adder 23. In the data decoding circuit 2, the random number generator 22 generates a random number as a function of a value of the content of the shift register 21. The reception data input to a terminal 24 is added to the random number by the adder 23, and the sum appears as a reception data output at a terminal 25. The input reception data is also supplied to the shift register 21. Unless an error occurs on a transmission line 3, the values of the contents of the shift registers 11 and 21 in the data encoding and decoding circuits 1 and 2 are the same, and the random numbers are identical accordingly. Therefore, data corresponding to the input to the input terminal 14 of the data encoding circuit 1 appears at the output terminal 25 of the data decoding circuit 2.
FIG. 2 is a block diagram of a conventional data encoding/decoding circuit of the second system. Referring to FIG. 2, a data encoding circuit 4 comprises a frame counter 41, a random number generator 42, a frame sync inserting circuit 43, and an adder 44. A data decoding circuit 5 comprises a frame counter 51, a random number generator 52, a frame sync extracting circuit 53, and an adder 54. If one frame length consists of NF bits, the frame counters 41 and 51 are respectively counters of base-NF, each representing the current bit position in the frame. The random number generators 42 and 52 respectively generate random numbers as a function of values of the contents of the frame counters 41 and 51.
In the data encoding circuit 4, transmission data input to an input terminal 45 is added by the adder 44 to the random number output from the random number generator 42. Sum data is supplied to the frame sync inserting circuit 43. The frame sync inserting circuit 43 inserts the frame sync signal into the output from the adder 44, in response to the signal supplied from the frame counter 41. The transmission data is sent from an output terminal 46 onto a transmission line 6. The transmission data is supplied to an input terminal 55 of the data decoding circuit 5, and then to the frame sync extracting circuit 53. The frame sync signal is extracted by the extracting circuit 53. The extracted frame sync signal is supplied to the frame counter 51 to properly set its initial value. An output (excluding the frame sync signal) from the frame sync extracting circuit 53 is supplied to the adder 54, and is added to the corresponding random number. An output from the adder 54 appears as reception data at an output terminal 56. As long as the contents of the frame counters 41 and 51 in the data encoding and decoding circuits 4 and 5 coincide with each other, the random numbers from the random number generators 42 and 52 are the same. Therefore, accurate decoding can be performed.
FIG. 3 is a block diagram of a conventional encoding/decoding circuit of the third system. Referring to FIG. 3, a data encoding circuit 7 comprises a shift register 71, a random number generator 72, an adder 73, a switching circuit 74, and a multiplexer 75. A data decoding circuit 8 comprises a shift register 81, a random number generator 82, an adder 83, a switching circuit 84, and a demultiplexer 85. At the beginning of transmission, an initial value is supplied from an input terminal 76 to the shift register 71 through the switching circuit 74. The random number generator 72 generates a random number as a function of a value of the content of the shift register 71. The input data at a terminal 77 and the random number are added by the adder 73, and sum data is supplied to the multiplexer 75. The multiplexer 75 multiplexes the input data and the initial value. The multiplexed data is sent as the transmission data output onto a transmission line 9.
In the data decoding circuit 8, multiplexed data from the data encoding circuit 7 is supplied to the demultiplexer 85 through the transmission line 9 and an input terminal 86. The multiplexed data is demultiplexed by the demultiplexer 85. The initial value of the multiplexed data is supplied to the shift register 81 through the switching circuit 84 and the data signal of the multiplexed data is supplied to the adder 83. The adder 83 adds the input data and the random number supplied from the random number generator 82. The sum data is output through an output terminal 87. The random number is also supplied to the shift register 81 through the switching circuit 84. With the above arrangement, the initial value is set in the shift registers 71 and 82 at the beginning of transmission. Thereafter, the same random number is supplied to the shift registers 71 and 81.
The conventional data encoding/decoding circuits of the three systems present the following drawbacks.
In the first system, the reception data is input to the shift register and the random number is generated according to the content value of the shift register. If a data error occurs on the transmission line 3, the random numbers in the data encoding and decoding circuits 1 and 2 differ from each other while the false data is left in the shift register 21. As a result, the number of data errors tends to increase. In the second system, the same random number is used in response to the frame sync signal. The random number can be relatively easily descrambled, resulting in inconvenience. In the third system, although the problems posed by the first and second system can be solved, the initial value must be sent and received for each transmission cycle. If a wrong initial value is received or if even one clock is omitted during transmission or reception of data, all the data is lost until the next initial value is sent.