In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down (e.g., to submicron levels) device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. These features sizes include the width and spacing of interconnecting lines, and the spacing and diameter of metal contact vias.
High resolution lithographic processes are employed to define patterns for interconnecting lines and vias. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist. The film is exposed with a radiation source (such as optical light, x-rays, or an electron beam) that irradiates selected areas of the surface through an intervening master template, the mask, forming a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through the mask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process leaving the less soluble photoresist forming a patterned coating.
A typical method of employing lithography to form metal lines and vias is to form the patterned resist coating over a dielectric layer, such as a layer of silicon oxide. An anisotropic etching process can then be employed to remove the dielectric where it is left exposed by the resist coating. Thereby, the resist pattern is transfer to the dielectric layer. The photoresist is then stripped. A blanket coating of metal is applied over the dielectric layer, filling the gaps in the dielectric pattern. The metal layer is then polished or etched until only the portion metal within the pattern gaps remains. Additional steps may be taken to form multilevel interconnections.
While the existing technology for forming metal lines and vias is workable, there remains room for improvement. The existing technology involves a dielectric etch and clean that is difficult to engineer; the process contributes significantly to the overall cost of integrated circuit devices; and the dimension of the resulting lines and vias limits the state of the art for integrated circuit devices. Thus, there remains an unmet need for improved processes for forming metal lines and vias.