1. Field of the Invention
This invention relates generally to digital design and frequency synthesis and, in particular, to a numerically controlled oscillator.
2. Description of Related Art
In digital design, it is often necessary to derive an output signal from a given input signal such that the ratio of the output to the input is some specific ratio. In many cases, the ratio is in the form of 1/N, where N is an integer. Digital divider circuits for performing this "divide-by-N" function are well known in the art, such as circuits for generating one output pulse for every N input pulses. In other cases, the desired ratio is in the form of M/2.sup.N, where M is an integer, and 2.sup.N is an integer power of two (i.e., 2, 4, 8, 16, etc.) and greater than M. Many types of circuits for performing the M/2.sup.N division are also known, such as a numerically controlled oscillator (NCO).
FIG. 1 shows a conventional N-bit NCO 100, which includes of an N-bit adder 110 and an N-bit register or accumulator 120 for storing the summed outputs from adder 110. Inputs B.sub.0 to B.sub.N-1 of adder 110 are coupled to a selection circuit (not shown) for frequency selection, and inputs A.sub.0 to A.sub.N-1 of adder 110 are connected to the N outputs of accumulator 120. The output Y.sub.0 to Y.sub.N-1 of adder 110 is the sum of A.sub.i and B.sub.i, where i=0 to N-1, i.e., Y.sub.0 =A.sub.0 +B.sub.0, Y.sub.1 =A.sub.1 +B.sub.1, . . . , Y.sub.N-1 =A.sub.N-1 +B.sub.N-1, which is stored in accumulator 120 at a rate determined by an external clock coupled to accumulator 120. The most significant bit (MSB) of accumulator 120, i.e., from Y.sub.N-1, represents the output of NCO 100. NCO 100 outputs a pulse M times for every 2.sup.N clock cycles, where M is the frequency control value and N is the number of bits in the accumulator. More specifically, B.sub.N-1 B.sub.N-2 . . . B.sub.1 B.sub.0 is the binary representation of the value M.
FIG. 2 shows a 3-bit NCO 200, which will be used to illustrate the operation of an NCO. A 3-bit frequency control signal, B.sub.2 B.sub.1 B.sub.0, allows a given input clock frequency to be changed by four (2.sup.2) different ratios to provide for four different output frequencies. An NCO typically utilizes signed 2's complement arithmetic so that the MSB, i.e. bit B.sub.2 in this case, is used as the sign bit. Therefore, there are four possible frequency ratios for the input clock, 0, 1/8, 2/8, and 3/8. For example, to obtain a 3/8 division of the input signal, the frequency control signal B.sub.2 B.sub.1 B.sub.0 is set to 011. FIG. 3 shows signal waveforms for the clock and for register outputs A.sub.0, A.sub.1, and A.sub.2. Assume that signals from a 3-bit adder 210 are clocked into a 3-bit accumulator 220 on each low to high transition of the clock pulses and that accumulator 220 has been cleared so that zeros are stored in accumulator 220. After the first transition 301 of the clock pulse, the output of accumulator 220 will all be low or zero. The second low to high transition 302 of the clock signal will cause the signal on the frequency select input of adder 210 (B.sub.2 B.sub.1 B.sub.0 =011) to be added to the output of accumulator 220 (A.sub.2 A.sub.1 A.sub.0 =000) and result stored into accumulator 220. Thus, the output of accumulator 220 will now be A.sub.2 A.sub.1 A.sub.0 =011, which represents the decimal number 3. At the third low to high transition 303 of the clock signal, accumulator 220 receives an input which is the sum of the 011 frequency select signal and the 011 output from accumulator 220. The binary number for this sum is 110, which represents a decimal 6. Addition continues for a total of N or 8 clock cycles, at which time, the waveforms for the signals at A0, A1, and A2 repeat. Thus, as seen, the most significant bit (i.e., at A2) transitions or toggles high three times during the 8-pulse clock cycle for the desired 3/8 division.
General NCOs, such as in FIG. 1, distribute the output pulses as uniformly as possible for a given M/2.sup.N ratio, which is advantageous for frequency synthesis. However, there are other cases where the desired ratio expressed as M/N, where M and N are both integers, with M being less than N, and N not being a power of two. In these cases, the general NCO designs of FIG. 1 cannot generate the exact desired ratio. In order to generate an exact M/N ratio, the general NCO has been modified and varied, such as disclosed in U.S. Pat. No. 5,521,534, entitled "Numerically Controlled Oscillator for Generating a Digitally Represented Sine Wave Output Signal", to Elliott. However, these designs tend to be complex and/or slow.
Accordingly, a divider circuit for generating M/N ratios is desired that overcomes the deficiencies of conventional NCO circuits discussed above.