a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device formed with MISFETs and capacitors and its manufacture method.
b) Description of the Related Art
A conventional method of manufacturing a semiconductor device having capacitors and MISFETs will be described with reference to FIGS. 5A to 5C and FIGS. 6A and 6B.
As shown in FIG. 5A, an n-type well 102 is formed in a partial region of a surface layer of a p-type silicon substrate 100. A field oxide film 101 is formed on the surface of the silicon substrate 100 to define the region where the n-type well 102 was formed and an active region in the p-type surface layer of the silicon substrate 100. The surface layer in the active region is thermally oxidized to form a gate insulating film.
A first polysilicon film 103 is deposited on the field oxide film 101, this film 103 being doped with impurities to impart an n-type conductivity. A capacitor dielectric film 104 made of SiO.sub.2 is deposited on the first polysilicon film 103. A second polysilicon layer 105 is deposited on the capacitor dielectric film 104, this film 105 being doped with impurities to impart the n-type conductivity.
Of the surface of the second polysilicon film 105, a partial area above the field oxide film 101 is covered with a resist pattern 110. By using the resist pattern 110 as a mask, the second polysilicon film 105 is etched. Thereafter, the resist pattern 110 is removed.
As shown in FIG. 5B, an upper electrode 105a made of the second polysilicon film 105 is being left.
As shown in FIG. 5C, an SiN film 106 is deposited on the capacitor dielectric film 104 and upper electrode 105a. Of the surface of the SiN film 106, a partial area inclusive of the area above the upper electrode 105a is covered with a resist pattern 111. By using the resist pattern 111 as a mask, the SiN film 106 and capacitor dielectric film 104 are etched. Thereafter, the resist pattern 111 is removed.
As shown in FIG. 6A, an SiN film 106 covering the upper electrode 105a and a capacitor dielectric film 104a under the SiN film 106 are being left. Of the surface of the first polysilicon film 103, the areas where gate electrodes are to be formed are covered with resist patterns 108. By using the resist patterns 108 and SiN film 106a as a mask, the first polysilicon film 103 is etched. Thereafter, the resist patterns 108 are removed.
As shown in FIG. 6B, gate electrodes 103b and 103c are being left on the gate insulating film on the active regions. A lower electrode 103a made of the first polysilicon film 103 is being left under the SiN film 106a. With the above processes, a capacitor 109 is formed having the lower electrode 103a, capacitor dielectric film 104a, and upper electrode 105a.
A p-channel MISFET and an n-channel MISFET are formed respectively in the n-type well 102 and p-type active region through ordinary MISFET manufacture processes.
With the method described with reference to FIGS. 5A to 5C and FIGS. 6A and 6B, two photolithography processes are required to form the capacitor 109, by using the resist pattern 110 for the upper electrode shown in FIG. 5A and the resist pattern 111 for the lower electrode shown in FIG. 5C. These two photolithography processes are required in addition to the MISFET manufacture processes.
Another method proposed heretofore forms the capacitor lower electrode and gate electrode by one photolithography process after the upper electrode and capacitor dielectric film 104 are formed through selective etching using the resist pattern 110 shown in FIG. 5A. With this method, the capacitor can be formed by adding one photolithography process. However, the side wall of the upper electrode of the capacitor and the upper surface of the lower electrode are separated only via the side wall of the capacitor dielectric film. A lowered breakdown voltage or an increased leak current of the capacitor become easy to occur.