1. Field of the Invention
The present invention relates to the field of fabrication techniques for thin film transistors, and more particularly to techniques for self-aligned fabrication of thin film transistors.
2. Background Information
Thin film transistors (TFTs) are employed in liquid crystal displays and imagers to control or sense the state of each pixel of the display or image. At present, such thin film transistors are typically fabricated from amorphous silicon. In such display or sensor systems, system operating characteristics are optimized by making each cell or pixel have substantially identical operating characteristics. These operating characteristics include switching speed, capacitive loading of drive and sense lines, the gain of transistors and so forth.
One of the processing problems which causes variation in the characteristics of different cells within such structures is the inability to accurately align the position of a mask which defines the source and drain electrodes of thin film transistors in a manner which ensures that the source/drain electrodes are accurately aligned with respect to the gate electrodes. Misalignment results in an increase in the overlap between the gate electrode and either the source electrode or the drain electrode with a corresponding decrease in the overlap between the gate and the other of them. Since the capacitances between the gate electrode and the source or drain electrodes are direct functions of the overlap between them, such a change in overlap produces a change in device's capacitances and consequently, switching speed and loading of other circuits. The possibility of misalignment requires that the size of the gate metal be increased to ensure that all devices have acceptable overlap between the gate and the source and drain. This increases the device size and hence the total capacitance per device. The device capacitance is important because it controls the charging time of the gate electrodes, the capacitive coupling between the gate and the source and drain nodes, and the noise introduced by the defects in the amorphous silicon or at the amorphous silicon/dielectric interface. Consequently, there is a desire to provide self-alignment between the source and drain electrodes and the gate electrode in order to maintain a fixed, predictable overlap between the gate electrode and each of the source and drain electrodes across an entire wafer.
A variety of self-alignment techniques have been proposed or developed. The above-identified related applications Ser. Nos. 07/499,733 and 07/510,767 each disclose techniques for obtaining self-alignment between the gate electrode and the source and drain electrodes through the use of through-the-substrate exposure of photoresist. Such processes result in specific gate-to-source and gate-to-drain overlaps which are peculiar to those techniques and the particular manner in which they are carried out. Those overlaps may be smaller or larger than optimum. Such a through-the-substrate exposure technique is not suitable where the semiconductor itself or another device layer would absorb the light needed to expose the photoresist. Consequently, there is a need for other self-alignment techniques for thin film transistors.