1. Field of the Invention
The present invention relates to the technical field of clock data recovery and, more particularly, to a data recovery device using a sampling clock with a half frequency of data rate.
2. Description of Related Art
The first generation ATA (Advanced Technology Attachment) structure includes a clock data recovery (CDR) internally having a clock generator with a voltage-controlled oscillator (VCO). The VCO outputs eight clock signals with different phases and a same oscillation frequency of 375 MHz. Next, a quadruple clock frequency circuit receivers the 375 MHz clock signals for processing them by 4× and accordingly outputs a 1.5 GHz clock signal for reading a 1.5 GHz data signal. When the serial ATA structure advanced from the first generation to the second generation, the frequency of data signal increased from 1.5 GHz to 3 GHz and thus the operating frequency of clock signal was from 1.5 GHz to 3 GHz for latching the data. At this point, the VCO has to generate eight clock signals with different phases and a same oscillation frequency of 750 MHz. Next, a quadruple clock frequency circuit processes the 750 MHz clock signals for generating a 3.0 GHz clock signal.
However, due to the 3.0 GHz clock signal, the VCO requires driving each stage circuit in a shorter time for generating the aforementioned eight clock signals with different phases and the same oscillation frequency of 750 MHz. Thus, using an element with higher driving capability is required, which relatively increases area of the VCO and its power consumption also relatively increases with higher clock frequency.
Therefore, it is desirable to provide an improved clock data recovery device to mitigate and/or obviate the aforementioned problems.