1. Technical Field
The present invention relates generally to chip packages, and more particularly, to a chip package including a chip extension for containing thermal interface material and improving chip cooling.
2. Related Art
The drive for increasing chip performance (higher operating frequencies) is resulting in increased chip power, and the reduction of circuit size is increasing chip power density. Chip leakage power is aggravated by shrinking device size, and is strongly affected by operating temperature. As a result, as chips continue to become smaller, there is a need to continue enhancing chip cooling capability.
One common cooling mechanism is to thermally connect chips to a cooling structure, such as a lid or heat sink, via a thermal interface material (TIM). Commonly used TIMs include thermal pastes, thermal adhesives, and phase change materials; and less commonly used TIMs include liquid metals and solders. FIG. 1 shows an illustrative chip package 8 including a chip 10 coupled to a substrate 12, which is in turn coupled to a card 14 via a conventional grid array 16. A cooling structure 18 is thermally coupled by a TIM 20 to chip 10, and cooling structure 18 is coupled to substrate 12 via polymer adhesive 22. In this example, cooling structure 18 is in the form of a lid.
There is a need to improve the reliability of cooling structures 18 that utilize compliant TIMs 20 (i.e., thermal paste). One problem with conventional structures is caused by the relatively high viscosity of high performance thermally conductive pastes. High performance thermal pastes are designed to have high viscosity at elevated temperature to prevent the materials from readily flowing (i.e., sagging) off of chip 10 during normal operation. The high viscosity is also due to their high solids loading, which enhances thermal performance. Unfortunately, the high viscosity also results in “paste pumping,” which refers to the situation in which the TIM is pumped into and out of the gap between chip 10 and cooling structure 18. In particular, as shown by the arrows in FIG. 1, as power is applied to and removed from chip 10, package 8 heats and cools, i.e., it thermally cycles. During these thermal transients there is often relative movement of cooling structure 18 toward and away from back side 24 of chip 10. This movement is caused by the materials coefficient of thermal expansion and temperature differences that arise during device operation. When cooling structure 18 moves toward back side 24 of chip 10, the space for TIM 20 above chip 10 decreases and some of the paste is squeezed out the side of the gap between chip 10 and cooling structure 18. When cooling structure 18 and chip 10 move in opposite directions, i.e., away from one another, the gap increases. As the gap increases, surplus TIM 20 from around the gap flows back into the gap, maintaining the thermal integrity of the structure, while entrapped gas, typically ambient air, can enter the paste. Air moving into the gap tends to form pockets referred to as voids 26. These voids 26 have much lower thermal conductivity than TIM 20, causing chip 10 temperature to rise, and further increasing power dissipation, usually because of device leakage current. These voids 26 tend to grow with additional cycling, further degrading the cooling, degrading device reliability, and increasing the power consumption.
Another problem with conventional structures is that, in most high power flip chip packages, device cooling by heat transfer to and through substrate 12 is nearly negligible. As a result, virtually all the heat must be removed from a back side 24 (non-circuit side) of chip 10. Semiconductor devices are produced in massive quantities on a single wafer. Typically, a prototype device design is produced in a die size that is later reduced in size to increase the number of devices on a processed wafer. This chip ‘shrink’ increases the density of the power on the device since the body size is physically smaller for the same power consumption. Silicon used for devices has good thermal conductivity and will spread the heat created by the active devices to the backside of the die as well as laterally across the die surface. Specific regions of the device can become much hotter, often because these regions are where the die cores are located. Initial builds of devices on large die have the advantage of providing lateral heat spreading from these ‘hot spots’. Thus, decreasing the die size improves the die count on each wafer but also reduces the lateral heat spreading of the silicon.
In view of the foregoing, there is a need to contain TIMs when the cooling structure separates during thermal cycling, and to improve lateral heat transfer from the chip to reduce the heat flux without impacting the number of die that can be produced on a wafer.