As the operational speed of integrated circuits increases there may also be a decrease in margins associated with clock signals that operate the integrated circuits. The integrated circuits may include interface circuits that transmit and receive data to and from the integrated circuit and clock signals that are connected to subsystems in the integrated circuit which provide synchronous operation thereof. Moreover, the interface circuits may operate at speeds that exceed the operational speed of the integrated circuit, thereby further reducing the clock signal margins. For example, in some conventional systems integrated circuit memories are connected to a Central Processing Unit (CPU). Accordingly, the integrated circuit memories may be required to transmit and receive data to/from the CPU at clock signal rates that approach those of the CPU. In addition, unequal loading of the clock signals in the integrated circuit memory may further reduce the clock signal margins. Consequently, it may be difficult to test the interface circuits, particularly if the clock signals that provide for the synchronous operation of the interface circuits are unequally loaded.
FIG. 1 is a block diagram that illustrates conventional interface circuits that clock signal data into an integrated circuit. According to FIG. 1, a Receiver Delay Lock Loop (RDLL) generates two synchronous clock signals based on RxClk: RCLK and MCLK. As shown in FIG. 1, RCLK is used to operate an interface circuit 2 and an input pipeline 5 while MCLK is used to operate the input pipeline 5 into which data is input. Furthermore, MCLK is connected to fewer loads than RCLK which may cause the phase of RCLK to lag the phase of MCLK as shown in FIG. 2.
FIG. 2 is a timing diagram that illustrates data setup and hold times for the input pipeline 5 of FIG. 1. According to FIG. 2, the timing of RCLK is delayed with respect to RxClk and MCLK so that the setup and hold times (tS and tH) for the input data are delayed by .DELTA.tsh. Accordingly, the margin for clocking data into the input pipeline 5 may be reduced. In particular, the additional loads on RCLK may cause a delay in RCLK with respect to MCLK such that a falling edge of RCLK normally used to clock signal data into the input pipeline 5 is delayed almost a full cycle as shown in FIG. 2. Accordingly, the falling edge of RCLK used to clock signal data into the input pipeline 5 may correspond to a falling edge of MCLK in the next clock signal cycle.
FIG. 3 is a block diagram that illustrates conventional interface circuits that clock signal data out of an integrated circuit. According to FIG. 3, a Transmit Delay Lock Loop (TDLL) 4 generates two synchronous clock signals based on TxClk: TCLK and MTCLK. As shown in FIG. 3, TCLK is used to operate the output pipeline 6 while MTCLK is fed back to the TDLL 4 to maintain lock in the TDLL 4. Furthermore, MTCLK is connected to fewer loads than TCLK which may cause TCLK to lag MTCLK as shown in FIG. 4.
FIG. 4 is a timing diagram that illustrates data valid times for the output pipeline 6 of FIG. 3. In particular, the timing of TCLK is delayed with respect to TxClk and MTCLK so that the valid times: tQ_max and tQ_min for data output from the output pipeline 6 is delayed by .DELTA.tQ. Accordingly, the margin for clocking data from the output pipeline 6 may be reduced.
In some conventional integrated circuits, a reduction in the clock signal margin described above may be controlled by monitoring the manufacturing process of the integrated circuit and compensating for the reduced clock signal margin during the fabrication of the integrated circuit wafer. For example, the clock signal margin may change due to the structure of the integrated circuit, the integrated circuit package, and internal control signals. Therefore, the clock signal margin in the integrated circuit may be measured and compensated for during the wafer fabrication process, thereby possibly increasing the cost of the integrated circuit fabrication process. Consequently, there continues to exist a need to compensate for clock signal margins due to differential loads between clock signals in integrated circuits.