The semiconductor industry has continually improved the speed and power of integrated circuits (ICs) by reducing the size of components within the ICs. In large part, the ability to scale the size of components within an integrated chip is driven by lithographic resolution. However, in recent years tool vendors have been unable to decrease the wavelength of photolithography exposure tools (e.g., to successfully implement EUV lithography), so that developing technology nodes often have minimum feature sizes less than the wavelength of illumination used in the photolithography tools. To continue scaling, IC fabrication processes use tricks (e.g., immersion lithography, dual tone resist, etc.) that improve the resolution of existing photolithography tools in a manner that extends their usefulness.
Multiple patterning lithography (MPL) is one photolithography strategy that is used in advanced technology nodes to decrease the minimum spacing between shapes. To perform MPL, an IC layout is decomposed according to an algorithm that assigns different ‘colors’ to design shapes separated by a space less than a printable threshold. The different colors correspond to different photomasks, such that features of a same color are formed on a same mask of a multiple mask set. By separating IC layout data onto different masks, design shapes can be separated by spaces below a printable threshold since the features comprised within separate masks do not violate the printable threshold.