Dynamic devices are logic circuits that generate an output depending upon a predetermined combination of inputs for implementing a logical function. One common use for dynamic devices is for comparators. A comparator will output a unique signal only if two input words (each containing multiple data bits) are identical to one another.
Dynamic devices are characterized by two states, precharge and evaluate. In the precharge state, a storage node is charged to a known or predetermined voltage level. In the evaluate state, an array or xe2x80x9ctreexe2x80x9d of pull-down transistors configured in a basic logical function (e.g., NAND, NOR, or combination thereof) is given the opportunity to discharge the node to a second known or predetermined voltage level or to allow the charge to persist. The logical function input signals are connected, typically, to the gates of one or more of the transistors in the logical section tree. The final charge on the node may thereby be controlled by the particular values of the inputs. The final voltage at the node, high or low, serves as the device""s output, which may additionally be buffered and, perhaps, inverted.
Two basic logical section structures include stacked NAND and parallel NOR structures. In a stacked NAND logical section, two or more transistors are stacked in series with one another and to the precharge node. The precharged node is discharged if and only if all of the transistor gate inputs are active (e.g., high). With the parallel NOR configuration, two or more transistors are arranged in parallel with one another and across the precharged node. If any of the transistor gate inputs are active, the precharge node is discharged. In other words, the precharged node remains charged if and only if all of the transistor gate inputs are not activated. Of course, with the use of inverted or non-inverted inputs, any logical function may be implemented with either structure.
FIGS. 1A and 1B show a conventional multi-bit (33 bit) dynamic comparator circuit 105. Comparator circuit 105 is used for comparing two 33 bit words (A and B) with one another. Circuit 105 includes an 11 input OR gate 110 and eleven 3-bit dynamic comparator circuits C1-C11. Each of these comparators, C1-C11, compares a separate 3-bit portion of the two (A, B) input words. The output from each comparator, C1-C11, is connected to one of the eleven OR gate inputs and provides to it a low value if and only if its received 3 bit A, B input word portions are equal to one another. Thus, if all of the 3 bit A, B word portions are equal to one another, then every output from C1-C11 will be low thereby causing OR gate 110 to output a low, as well, indicating that words A and B are equal to one another.
With reference to FIG. 1A, 3-bit dynamic comparator circuit 100 is depicted. Circuit 100 corresponds to the C1 (bits 0, 1, 2) comparator from the 33-bit comparator circuit 105 of FIG. 1B. (Equivalent circuits are used for implementing the other comparators, C2-C11.) Circuit 100 includes NFET transistors, Q1-Q18, PFET transistors, Q19-Q20, and inverter U1. Comparator circuit 100 has a precharge storage node, S0, and an output at Z. Q19 serves as a precharge transistor and cooperates with Q3, Q6, Q9, Q10, Q15, and Q18, which are DNG transistors, for charging the storage node, S0, during a precharge state. Pull-down transistors, Q1, Q2, Q4, Q5, Q7, Q8, Q12, Q11, Q13, Q14, Q16, and Q17, are configured in a combination NAND stack and parallel NOR tree structure for implementing an XOR operation on each pair of received input bits (e.g., A0/B0) to be compared. If any input bit pair has unequal bits, then one of its associated NAND stacks discharges the storage node, S0, during the evaluate state. Inverter U1 together with PFET transistor, Q20, serves as a bolder circuit for xe2x80x9choldingxe2x80x9d the storage node charged during the evaluate state if it is suppose to evaluate high. It also inverts the storage node value and provides the inverted value at the output Z. In operation, during a precharge state (i.e., clock is low for this configuration), storage node, S0, charges to a high level with Q19 turned on and an DNG transistors, Q3, Q6, Q9, Q10, Q15 and Q18, turned off. If all of the A, B bit pairs have equivalent bits, then none of the pull-down stacks will turn on during the evaluate state (clock high), and the storage node, S0, stays high. Conversely, if any A, B bit pair has unequal bits, then at least one of the six pull-down stacks will turn on (i.e., both of its transistors are activated), and the storage node, S0, discharges to a low value during the evaluate state. Therefore, if the A bits are equal to their corresponding B bits, then S0 evaluates high and if they are not equal, it evaluates low.
Unfortunately, there are several problems associated with this conventional configuration. To begin with, the pull-down transistor NAND stacks add substantial capacitance to the storage node, S0, which increases the time required for it to precharge, as well as evaluate, thereby slowing down the overall speed of the multi-bit comparator. In addition, the trace or wire lengths from the outputs of the 3-bit comparators to the OR gate inputs are excessively long, especially for the outwardly distributed comparators (e.g., C1, C2, C10, C11). These excessive lengths impart substantial propagation delay, which also ads to the precharge time required for the multi-bit comparator. Thus, it can be seen that in order to increase the operating frequencies, and thus the operational performance, of dynamic comparators, their associated precharge times must be reduced.
The comparator circuit is operative on one or more devices where the devices receive multiple word bit values. The devices provide outputs indicative of whether the received word bits are equal to one another. A precharge circuit using parallel pull-down transistors connected to a common storage node where each such transistor has an input coupled to the output of associated devices for receiving a XOR value. The storage node is discharged if the word bits are not equal and is charged where the word bits are equal.