1. Field of the Invention
The present invention relates to a non-volatile memory cell of a side wall accumulation type, and more particularly to a non-volatile memory cell for an electrically erasable programmable read only memory (EEPROM).
2. Description of the Related Art
A non-volatile memory includes erasable programmable read only memories (EPROMs) and EEPROMs.
FIG. 8 shows a non-volatile memory cell of a side wall accumulation type 80 for an EPROM. Such a memory cell is disclosed in U.S. Pat. No. 5,051,793.
The memory cell 80 includes a p-type silicon substrate 81, a source region 82 and a drain region 83 formed in the substrate 81, a gate insulating film 84 with a uniform thickness formed on the substrate 81, floating gate electrodes 85a and 85b, and a control gate electrode 86 formed on the gate insulating film 84. The floating gate electrodes 85a and 85b are provided on both sides of the control gate electrode 86 as a pair of side walls. The floating gate electrodes 85a and 85a and the control electrode 86 are electrically insulated from each other by an insulating film formed therebetween. The width (T) of the control gate electrode 86 (i.e., the size in the channel length direction) is smaller than the channel length (L), and the floating gate electrodes 85a and 85b cover a part of a channel via the gate insulating film 84.
When the electric potential of the drain region 83 is made sufficiently higher than that of the source region 82, electrons emitted from the source region 82 are accelerated toward the drain region 83 in an electric field formed between the source region 82 and the drain region 83. The accelerated electrons cause an avalanche breakdown in the vicinity of the drain region 83, generating a plurality of high energy electrons (hot electrons). Part of the generated hot electrons jump over the electric potential barrier of the gate insulating film 84 to be injected into the floating gate electrode 85b on the side of the drain region 83. When hot electrons are injected into the floating gate electrode 85b, the electric potential of the floating gate electrode 85b is lowered, resulting in an increase in the inversion threshold voltage of the memory cell 80.
In this way, each memory cell takes one of two electrically stable states (i.e., logic "high" and logic "low") in accordance with the level of the inversion threshold voltage. As a result, each memory cell can store 1-bit data. For example, among a plurality of non-volatile memory cells formed in a matrix, the inversion threshold voltage of a desired memory cell is selectively set at a high level and those of the other memory cells are set at a low level, whereby the desired data can be stored.
The above-mentioned non-volatile memory cell of a side wall accumulation type has the following problems:
The read error of data can be prevented by increasing the quantity of the hot electrons to be injected into the floating gate electrode 85b. Therefore, the electric field in the vicinity of the drain region 83 should be made stronger. In order to make the electric field stronger, a higher electric potential should be applied to the drain region 83. However, in the case where such a high electric potential is applied to the drain region 83, a depletion layer formed in the vicinity of the pn junction between the n-type drain region 83 and the p-type substrate 81 deeply extends toward the source region 82. As a result, the hot electrons generated due to the avalanche breakdown are injected into a portion of the gate insulating film 84 right under the control gate electrode 86. In order to avoid the injection of the hot electrons into the gate insulating film 84, the electric potential to be applied to the drain region 83 should be decreased. However, a decreased electric potential applied to the drain region 83 decreases the quantity of hot electrons (write capacity) to be injected into the floating gate electrode 85b . This will cause a read error of data.