1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to low-temperature fabrication processes that provide sufficient polarizability and moderate coercivity in ferroelectric integrated circuit devices.
2. Statement of the Problem
Researchers have been attempting for at least 30 years to produce a commercially viable electronic memory utilizing the polarizability property of ferroelectric materials. Such a memory would be non-volatile, of high density, and have many other advantages. See, for example, U.S. Pat. No. 5,046,043 issued to William D. Miller, et al.
The layered superlattice materials disclosed in U.S. Pat. No. 5,519,234 possess superior ferroelectric properties, making it possible to fabricate commercially viable non-volatile memories. These properties include high polarizability and low fatigue.
The prior art discloses that annealing temperatures of at least 750-850.degree. C. are usually required to obtain good electrical properties in thin films. U.S. Pat. No. 5,508,226 teaches a low-temperature process for fabricating layered superlattice materials. Nevertheless, in two of its three examples, annealing was performed at 800.degree. C., while in one example annealing was at 700.degree. C., but for five hours duration. While temperatures of 750-850.degree. C. are much lower than temperatures previously used to form bulk ceramic materials, there still remains some interlayer atomic migration through the thin films at this temperature. For example, titanium used as an adhesion layer in electrodes migrates to the ferroelectric material and to the silicon. This atomic migration sometimes changes contact resistances and other properties, thus making it difficult or impossible to use the layered superlattice materials with transistors and other conventional electrical components made with conventional silicon technology.
It would be useful, therefore, if a method and a structure existed whereby integrated circuit material could be heat-treated at temperatures lower than 750-850.degree. C., yet still possess good ferroelectric properties. The lower temperatures would reduce interlayer diffusion and consequently result in less degradation of ferroelectric properties resulting from diffusion degradation.
3. Solution to the Problem
The present invention provides a fabrication process that utilizes only temperatures lower than 725.degree. C., and preferably about 650.degree. C. or less, to fabricate high quality ferroelectric integrated circuit devices.
The invention provides materials and a low-temperature method for fabricating a layered superlattice material. A liquid precursor is formed containing metal moieties in effective amounts for spontaneously yielding a ferroelectric layered superlattice material upon drying and heating of the precursor. The precursor contains a thallium moiety in an effective amount for being a superlattice generator element in the layered superlattice material. The precursor is applied to the substrate; dried to form a solid material on the substrate; and heated in oxygen at a temperature of between 600.degree. C. and 725.degree. C. to form a thin film of the layered superlattice material on the substrate.
Preferably, the step of heating includes rapid thermal processing the precursor at a temperature of 650.degree. C. The step of heating preferably includes annealing the material for about three hours, and up to five hours. Preferably, the annealing temperature is about 650.degree. C. The substrate preferably includes a first electrode and a second electrode, preferably formed on the layered superlattice material, after the step of annealing, to form a capacitor. Then, a second heating step is performed. Preferably the second heating step is a second anneal performed at a temperature lower than 725.degree. C., and preferably about 650.degree. C. Preferably, the wafer is an integrated circuit wafer, and the method further includes the step of completing the fabrication of the integrated circuit wafer to form a plurality of interconnected electrical devices on the wafer.
The present invention primarily concerns ferroelectric layered superlattice materials having the general chemical formula: EQU A.sub.m-1 S.sub.2 B.sub.m O.sub.3m+3,
in which at least a portion of the superlattice generator elements represented by S is thallium. In particular, the invention is concerned primarily with the ferroelectric layered superlattice materials represented by the general formula: EQU A.sub.m-1 (S1.sub.y-x S2.sub.x)B.sub.m O.sub.3m+3,
wherein S1 represents bismuth, S2 represents thallium, 2.ltoreq.y.ltoreq.2.4 and 0&lt;x.ltoreq.y. Preferably, the layered superlattice material comprises strontium bismuth thallium tantalate made from a precursor containing relative amounts of metalorganic compounds corresponding approximately to the following general chemical formula: EQU A.sub.m-1 (S1.sub.2.2-x S2.sub.x)B.sub.m O.sub.3m+3,
where A is the element strontium, S1 is bismuth and S2 is thallium, B is tantalum, m=2 and 0&lt;x.ltoreq.2.2. Preferably, x=0.55.
In another aspect, the invention provides an integrated circuit device containing layered superlattice material in which thallium is a superlattice generator element. In a preferred embodiment, the invention provides a capacitor including a first electrode, a second electrode and a thin film of layered superlattice material containing thallium as a superlattice generator element. Preferably, the layered superlattice material comprises strontium bismuth thallium tantalate made from a precursor containing relative amounts of metalorganic compounds corresponding approximately to the following general chemical formula: EQU A.sub.m-1 (S1.sub.2.2-x S2.sub.x)B.sub.m O.sub.3m+3,
where A is the element strontium, S1 is bismuth and S2 is thallium, B is tantalum, m=2 and 0&lt;x.ltoreq.2.2. Preferably, x=0.55.
In still another aspect, the invention provides a liquid precursor containing relative amounts of metalorganic compounds corresponding approximately to the following general chemical formula: EQU A.sub.m-1 (S1.sub.2.2-x S2.sub.x)B.sub.m O.sub.3m+3,
where A is the element strontium, S1 is bismuth and S2 is thallium, B is tantalum, m=2 and 0&lt;x.ltoreq.2.2. Preferably, x=0.55.
Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.