The invention is in the field of digital computers. In the invention, provision is made for determining result conditions of an on-going packed decimal ADD class operation prior to completion of the operation. The predetermined result conditions are used to indicate an exception interrupt or to select the sign of the ADD class operation result.
In modern computer architecture, arithmetic operations are performed on operands to produce results. The results are used to set condition codes which help control program branching during the execution of an instruction sequence. In the prior art, determination of the condition code awaited the outcome of an arithmetic operation. Upon termination, the operation results were inspected, and the condition code set appropriately, depending upon the results.
Recent modifications to computer architecture have resulted in the acceleration of fixed and floating point arithmetic operations by predetermination of condition codes before results are available. See, for example, U.S. patent application Ser. No. 07/157,500, filed Feb. 17, 1988, and entitled "CONDITION CODE PREDICTION APPARATUS". In this application, condition code predetermination is based upon manipulation of operand bits while the arithmetic operation proceeds by combining the operands.
To date, however, there has been no provision made for acceleration of result condition determination during arithmetic operations involving packed decimal numbers. This omission can be largely attributed to the complexity of packed decimal arithmetic circuitry and programming. Therefore, a clear need exists to accelerate result condition determination while packed decimal arithmetic operations are being conducted.