1. Field of the Invention
The present invention relates to a serial-to-parallel converter circuit and a parallel-to-serial converter circuit, and more specifically to a serial-to-parallel converter circuit and a serial-to-parallel converter circuit which use a signal transmission technique using dummy data (redundant data) in a data signal to be transmitted/received.
2. Description of the Related Art
There has been a known SerDes transmission scheme to perform high-speed signal transmission with use of a parallel-to-serial converter circuit and a serial-to-parallel converter circuit. With the recent rise of frequency in SerDes transmission, a PLL for generating a clock signal for serial data transmission has been requested to generate a high-frequency clock signal and have an extremely small jitter performance. To satisfy these requests for performance, necessity has been enhancing for use of a PLL having a broad frequency range and a narrow frequency setting width.
In the internal of a recent LSIs, the clock frequency is temporarily lowered, for example, to reduce the power consumption of the LSIs. Thus, a PLL is indispensable which allows the frequency setting independently from the frequency of the SerDes transmission. However, according to the conventional SerDes transmission scheme, the bit number or bit width of parallel data and the frequency conversion ratio between the parallel data and serial data are constant. Therefore, the serial transmission frequency and the internal frequency of the LSI cannot be set independently from each other.
Patent Publication JP-2002-135132A describes a serial-to-parallel converter circuit having a judgement section. The judgement section once buffers serial data, which are input in synchronously with a first clock signal and includes dummy data. The judgement section judges whether the data stored in the buffer are valid or invalid in a unit-by-unit basis, each unit including a plurality of bits. In this serial-to-parallel converter circuit, only those data cells that have been judged as being valid are output in synchrony with a second clock signal slower than the first clock signal. In this manner, the serial data signal transmitted based on the first clock signal can be received as parallel data based on the second clock signal having a lower frequency.