1. Field of the Invention
The present invention relates generally to a flip-flop circuit, and is directed more particularly to a flip-flop circuit formed of an IIL (integrated injection logic) or MTL (merged transistor logic).
2. Description of the Prior Art
A prior art IIL is fundamentally formed as shown in FIG. 1. In FIG. 1, N0 designates, for example, an N-conductivity type semiconductor substrate, P1 and P2 P-conductivity type regions, which are respectively formed on one of the major surfaces of substrate N0, and N1 to N3 N-conductivity type regions which are respectively formed in the region P2. Electrodes (terminals) I, B and C1 to C3 are connected to the regions P1, P2 and N1 to N3, respectively.
In the IIL shown in FIG. 1, the region P1-substrate N0-region P2 form a PNP-type transistor Q1 as shown in FIG. 2, and the substrate N0-region P2-regions N1 to N3 form an NPN-type transistor Q2 of a multi-collector type as shown in FIG. 2. In this case, the transistors Q1 and Q2 are connected with each other as shown in FIG. 2.
With the IIL shown in FIG. 1 or FIG. 2, when a voltage +V.sub.EE is applied to the electrode I, the transistor Q1 operates as a constant current bias source. Therefore, the transistor Q2 operates as an inverter of an open-collector type. Further, when the voltage +V.sub.EE applied to the electrode I is made ON and OFF, the transistor Q2 operates as a gate.
In the following description, the IIL described above will be symbolized as shown in FIG. 3 for the sake of brevity.
In the case where the above IILs are used to form a T-flip-flop circuit in the prior art, it is sufficient that, as shown in FIG. 4, IILs 2 to 7 are connected to make three sets of latch circuits (RS-flip-flop circuits) and an input IIL 1 is connected to the latch circuits. In FIG. 4, T designates an input terminal and Q an output terminal, respectively. In FIG. 4, though not shown, an output terminal Q is led out from the IIL 7.
The above prior art T-flip-flop circuit may be made as an IC (integrated circuit) chip, for example, as shown in FIG. 5 which is a plan view of the IC chip. As shown in FIG. 5 which is a plan view of the IC chip, the injector region P1 is formed on the semiconductor substrate N0 in the form of a straight line or band, and the regions P2 of respective IILs 1 to 7 are formed on the substrate N0 which are extended, each in the form of a straight line or band in the direction perpendicular to the common straight line region P1 and arranged along the extending direction of region P1 with a distance between adjacent ones respectively. In each of regions P2 of IILs 1 to 7, provided are some of collector regions N1 to N3. Then, the respective regions P1, P2 and N1 to N3 are connected to form a wiring pattern (shown by the thick lines in FIG. 5) in correspondence with the wiring pattern of FIG. 4. In FIG. 5, the marks.multidot.designate the ohmic contact points of the wiring pattern with the regions N1 to N3 (and P1), and the marks X designate the ohmic contact points of the wiring pattern with the regions P2 (in other words, the marks.multidot.represent the collector electrodes of transistors Q2 and the marks X the base electrodes of transistors Q2, respectively).
In the above IC chip, since the single region P1 operates as the common injector region to the IILs 1 to 7, the IILs 1 to 7 operate separately and hence, as a whole, perform the operation of the T-flip-flop circuit.
As may be clear from FIGS. 4 and 5, the number of the IILs forming the T-flip-flop circuit is large and the area occupied by the wiring pattern is also large, so that the IC chip has the disadvantage that it does not have high density and high speed.
To avoid this disadvantage, such a T-flip-flop circuit, in which delay devices 11 and 12 are provided so as to reduce the number of the IILs as shown in FIG. 6, may be considered. In this case, the delay devices 11 and 12 are used to increase the areas of the corresponding IILs 2 and 5 to increase the capacity thereof as shown in FIG. 7, and to shorten, for example, the injector length (the facing length between the injector region P1 and the regions P2 of IILs 2 and 5) so as to reduce the injection current.
The T-flip-flop circuit shown in FIGS. 6 and 7 has a smaller number of the IILs and a smaller area occupied by the wiring pattern, so that it can be made to have high density. With the circuit of FIGS. 6 and 7, the operating speed as a T-flip-flop circuit is limited by the delay devices 11 and 12, and hence lower than the inherent operating speed of the IIL so that the high speed operation cannot be obtained from the circuit.
Further, with the circuit of FIGS. 6 and 7, if the injection current is selected to be small due to the delay devices 11 and 12, it becomes unbalanced with the injection currents of the other IILs and hence the severe characteristics of the elements are required in view of the DC operation, which is not desired.