The present invention relates to nonvolatile, read-only programmable memories, and to processes for fabricating these devices.
Static, electrically programmable, nonvolatile, read-only memories, commonly referred to by the acronym EPROM, are fundamental devices for implementing microprocessor systems. These memories, formed by a matrix of memory cells arranged in rows and columns and individually addressable through row and column decoders, may belong to different "families", in terms of the particular electrophysical mechanism which is used for erasing data electrically recorded in the cells, notably EPROM, E.sup.2 PROM, and FLASH-EPROM.
Nonvolatile Memory Technologies
Several types of nonvolatile memory devices use principles of operation which exploit the properties of a floating-gate transistor. Such a transistor is different from a normal MOS transistor in that a dielectrically isolated floating gate is interposed between a control gate and the channel. Thus, the two gates are capacitively coupled to each other and to the channel. The lower gate is called a "floating" gate, because it is electrically isolated. By injecting charges into the floating gate, the effective threshold voltage of the MOS transistor (as seen from the upper gate) can be-changed. By applying an appropriate voltage to the control gate, and observing whether the transistor turns on, the state of the cell (i.e. whether charge is stored on the floating gate) can be detected.
An "electrically programmable read-only-memory" (EEPROM) can be electrically written and can be erased by ultraviolet light. EEPROMs are very commonly used, since they are cheap and their timing standards are familiar.
An "electrically erasable programmable read-only-memory" (EEPROM or E.sup.2 PROM) can be electrically written and electrically erased. EEPROMs are less commonly used than EPROMs, since they tend to be more expensive and to require even higher voltages.
A more recent modification of the EPROM is the "Flash EPROM". This device, like the EEPROM, is electrically erasable, but only in blocks. Although this device does not have the bit-by-bit erasability of the EEPROM, it is much cheaper, and is seeing incresing use in many applications.
In striving to make ever more compact devices (i.e. ULSI devices), it is necessary to reduce the dimensions of the single cells, i.e. the minimum lithographically definable width. Of course, a reduction of the cell area must be accompanied by a correlated reduction of junction depth, i.e. the depth of the diffused regions or simply of the diffusions formed in the semiconducting substrate, as well as of the thickness of the layers which are stacked over the semiconducting substrate. On the other hand, this scaling-down process must preserve the essential electrical characteristics of the integrated structure for a reliable functioning of the memory cell. In other words, beside the problems of photolithographic definition there are technological problems which are connected to a "scaling down" of the various features which form the functional integrated structure of an electrically programmable, nonvolatile memory cell.
In such memories, the dielectric used for isolating a polysilicon floating gate from an overlaying control gate structure has a decisive importance. The insulating dielectric layer between the two conducting layers of the floating gate and of the control gate, respectively, must be capable of preventing any substantial migration of electrical charge from the floating gate toward the control gate. On the other hand, the thickness of this dielectric layer must be as small as possible for determining a good capacitive coupling between the control gate and the floating gate.
Modern devices utilize two superimposed levels of polysilicon. The first (poly I) is used for patterning floating gates of single memory cells (and the gates of the transistors of the external circuitry). The second (poly II) is used for patterning control gate structures (commonly the row lines or wordlines of the cell array.
Reduction of Programming Voltages
Floating-gate memories normally require a high voltage for programmation (to get carriers into the dielectrically isolated floating gate). For example, EPROMs which can operate (in read mode) using only 5 V supply and ground, will commonly need a voltage of 10 V or more to achieve programmation; EEPROMs may need a voltage of 15 V or more to achieve programmation. Special circuit techniques are used to isolate this high voltage, and to prevent it from destroying logic devices which may also be present on the chip. However, the use of high voltage on-chip is a nuisance, and it would be desirable to reduce the needed voltage if this can be done without degrading speed or nonvolatility.
Since no voltage can be directly applied to the floating gate, the voltage between the floating gate and the channel (or source or drain) is created by applying a voltage to the control gate. This voltage will then be divided between the series capacitances: EQU V.sub.FG/C =V.sub.CG/C -V.sub.CG/FG
The voltage divides in inverse proportion to the capacitances, so that ##EQU1## where: C.sub.CG/FG is the capacitance from control gate to floating gate,
C.sub.FG/C is the capacitance from floating gate to channel, PA1 V.sub.CG/FG is the voltage from control gate to floating gate, and PA1 V.sub.FG/C is the voltage from floating gate to channel.
Since it is desirable to maximize the ratio of V.sub.FG/C to V.sub.CG/FG, it is desirable to maximize the ratio of C.sub.CG/FG to C.sub.FG/C. Since the areas of these capacitors are normally approximately equal, this criterion can be stated equivalently in terms of the specific capacitance (capacitance per unit area) C'. Therefore, we must maximize the ratio of C'.sub.CG/FG to C'.sub.FG/C. Since the specific capacitance C'.sub.FG/C is normally due to a thin gate oxide grown on the substrate, it is necessary to have a comparably high specific capacitance (small equivalent thickness) for the thin dielectric film between the floating gate and the control gate. However, it is also necessary to avoid leakage through this dielectric. This is inherently difficult, since oxidation of polysilicon tends to produce rapid growth and high defect density.
In 1980s, device technologists began using an oxide-nitride-oxide ("O--N--O") composite for the interpoly dielectric. (Typically a thin oxide would be grown to seal the polysilicon, then a nitride layer would be deposited, then a reoxidation step would be performed to seal any pinholes and provide the well-known interface characteristics of oxide). This technique provided a small and uniform thickness for the interpoly dielectric, while still preserving a desirably low leakage.
It has been found that such an O--N--O multilayer may be produced with a reduced initial defectivity as compared with an oxide layer produced by directly oxidizing polysilicon. This permits to achieve leakage current levels which are compatible with most stringent specifications of charge retention in the floating gate (i.e. nonvolatility of the stored data). Moreover, the process temperatures reached for depositing a layer of silicon nitride and the temperature for oxidizing the silicon nitride in order to form such a O--N--O multilayer are substantially lower than the temperature which is required to grow an oxide having good dielectric characteristics by direct oxidation of the surface of a doped polysilicon of first level. The possible attendant damage that the other important dielectric layer of the cell structure may be subject to during the relatively high temperature processing, i.e. of the gate oxide that isolates the floating gate from the channel region of the semiconducting substrate and which at this stage of the fabrication process has already been formed, is also considerably reduced by a lower process temperature when forming the interpoly dielectric layer.
Nothwithstanding the fact that the isolating O--N--O multilayer between two levels of polysilicon has represented a remarkable technological step forward in respect to the prior technique of forming a single dielectric layer of oxide, this technique also imposes limitations to the scaling of features, because of a residual, though reduced, density of intrinsic defects of the stacked layers. The bottom layer of oxide of the O--N--O multilayer is in fact particularly sensitive to scaling because of an intrinsic tendency to a substantial defectivity. Moreover, a reduction of the thickness of the deposited nitride layer beyond a certain limit does not ensure a sufficient imperviousness to oxygen during the subsequent thermal oxidation treatment of a top portion of the thickness of the deposited nitride layer in order to form a truly insulating dielectric layer of the floating gate from the control gate. An initial defectivity and a difficulty in preventing a growth of such a bottom oxide layer of the O--N--O structure during the subsequent thermal oxidation step for the formation of the insulating top oxide so layer, reflects negatively on the reliability of manufactured memories.
The possibility of forming a dielectric layer for integrated capacitances which ensure a degree of reliability higher than the O--N--O structure is known. According to this technique, disclosed in the Article: "Enhanced Reliability of Native Oxide Free Capacitor Dielectrics on Rapid Thermal Nitridized Polysilicon" of N. Ajika, et al., 1989 VLSI Symposium, Technology Digest, page 63, the coupling surface area between a first electrode consisting of a doped polysilicon layer is thermally nitridized for depositing on this nitridized surface a layer of silicon nitride whose surface will then be thermally oxidized in order to form a dielectric layer of silicon oxide reportedly having outstanding dielectric characteristics. This ON/RTN multilayer has been proposed as a dielectric multilayer of improved characteristics as compared with an O--N--O dielectric multilayer for making storage capacitances for high density DRAM memories. In this realm of utilization, the dielectric layer doesn't have a function of retaining the electrical charge for a substantially indefinite period of time in absence of a power supply, as is instead the case of nonvolatile, read only memories (ROM).