This invention relates to the chemical vapor deposition of metal and silicide films on a substrate. More particularly, it relates to a structure of stacked metal and silicide films useful for gate contacts in semiconductor devices.
In the development of VLSI technology, there is a continuous trend to reduce the dimensions of the integrated circuit devices to increase the speed of the devices. As the density of these devices is increased, the resistance of the interconnecting lines and gate contacts must be reduced. In both bipolar and FET devices, polysilicon has long been used as the material for the conducting layer closest to the epitaxial film. However, its relatively high resistivity in high density integrated circuits has led to a search to develop alternate materials for gate contacts.
Among the properties desired in a gate contact material are low resistivity, suitable work function, good adhesion, low stress (particularly on oxide), and process compatibility. No single material possesses all the desired properties.
Work function of a material is defined as the minimum energy necessary for an electron to escape into vacuum from an initial energy level equal to the Fermi level. By selecting the proper work function by choice of materials, the threshold voltage of the device can be adjusted without the need for channel implantation in n-channel or p-channel devices. Omitting channel implantation avoids inferior buried channel operation in PMOS and simultaneously yields high mobility and transconductance in NMOS.
Tungsten and its silicide (WSi.sub.x) are potential candidates because of their suitable work function. They also possess good adhesion, low stress on oxide, and relatively low resistivities. WSi.sub.x forms good quality silicon dioxide passivation layers or sidewall spacers when thermally oxidized, when x is greater than 2.5. However, WSi.sub.x, despite being 10 times lower in sheet resistance than polysilicon, has higher resistivity than many silicides capable of being used in the CMOS processes.
Titanium disilicide (TiSi.sub.2), for example, has a much lower resistivity than WSi.sub.x. TiSi.sub.2 can also be deposited via CVD, unlike other metal silicides with low resistance, such as cobalt disilicide. It does not, however, have the suitable work function and temperature stability required when deposited on oxide.
The desire to combine the desirable properties of potential gate materials has led some researchers to stack layers of the respective materials on one another to form a composite. In the IBM technical disclosure bulletin, "Modified Salicide- Single Gate Electrode for CMOS FET Applications", Vol. 27 No. 8, January 1985, a thin layer of tungsten or molybdenum silicide is covered by a thicker layer of titanium silicide to form the gate electrode. This structure suffers from the intermixing of the titanium silicide and tungsten silicide layers. The intermixing causes substantial increases in resistivity. Also, titanium can diffuse through the thin layer of tungsten silicide into the underlying oxide and destroy the device by causing leakage through the insulated gate.