In most operations on floating-point numbers, such as floating-point addition, the result of the operation is normalized. Normalizing a floating-point number involves shifting the mantissa until the most significant bit of the mantissa is nonzero. The exponent of the number is then adjusted accordingly by increasing or decreasing its value to compensate for the shifting of the mantissa. If the exponent adjustment causes an underflow or some other exceptional condition, an arithmetic exception is generated.
In a floating-point arithmetic circuit, such as a floating-point adder, the circuitry for normalizing the floating-point result (and associated arithmetic exception generation circuitry) typically contains a critical path that limits the speed of the arithmetic circuit. The critical path in the normalization circuitry usually includes a shift count detect circuit that generates a shift count (also called "norm count " indicating the number of bit positions that the mantissa of the floating-point result is to be shifted for normalization and an exponent adjustment circuit that adjusts the value of the exponent of the result based on the shift count. Because of its impact on the speed of a floating-point adder, it is important to minimize the delay of this critical path.
Various techniques have been used in the prior art to reduce the delay in generating the shift count, including the lead-zero-detection (LOD) and lead-zero-prediction (LOP) schemes. A detailed description of these techniques may be found in a number of references, including the background section of co-pending U.S. patent application Ser. No. 08/883,129, entitled "Norm-Count Detection Method of Floating Point Adder", which is incorporated herein by reference. The LOD and LOP schemes generate shift counts with a relatively small delay. However, since the shift count produced by these schemes is not exact, the exponent adjustment is only approximate. A second, final exponent adjustment is necessary to produce the exponent of the normalized number, thereby making the exponent adjustment circuit more complex and increasing the time required to generate the exponent of the normalized number.
In view of the shortcomings of these prior art normalization methods, it is an object of the present invention to minimize the delay incurred by exponent adjustment and exception generation for the normalization of floating-point numbers.