1. Field of the Invention
The present invention relates to the manufacture of integrated circuits and, in particular, to a method and system for determining systemic distortions of an overlay error measurement introduced by the imaging system and measurement tool used in lithographic processing of integrated circuits.
2. Description of Related Art
Semiconductor manufacturing requires the sequential patterning of process layers on a single semiconductor wafer. Exposure tools known as steppers or scanners print multiple integrated circuit patterns or fields by lithographic methods on successive layers of the wafer. These exposure tools typically pattern different layers by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. Typically, 20-50 layers are required to create an integrated circuit. In some cases, multiple masks are required to pattern a single layer.
Associated with the control semiconductor manufacturing is pattern measurement on most, if not all, of the process layers. Measurements are typically performed using “imaging” metrology tools. In the metrology context “imaging” is defined as the creation of a microscopic representation of the actual pattern on the wafer in one or more dimensions over a field of view (FOV) characteristic of the metrology tool. Typically, imaging metrology tools are optical, scanning e-beam or atomic force microscopy systems. In particular, optical microscopy tools usually provide two-dimensional (2-D) images of the patterned substrate over a circular or square FOV. Measurements are performed on images captured by the imaging tools. These measurements are usually classified as CD (critical dimension), the distance between any pair of pattern edges within the FOV, or overlay, the distance between the centroids of any pair of patterns within the FOV.
Metrology accuracy is limited by the within-FOV fidelity of the imaging system. Imaging system calibration and matching methods must distinguish between actual within-FOV pattern variation and systematic distortions introduced by the imaging system. There is a need to determine this latter factor, i.e., systemic distortions of an overlay measurement method introduced by the measurement tool used in the lithographic process. Accurate calibration is critically important in lithographic processing of integrated circuits to meet design requirements, and it would be extremely useful to be able to self-calibrate a metrology tool. “Calibration” minimizes the systematic distortions introduced by each imaging system, whereas “matching” minimizes the distribution of systematic distortions among a set of imaging systems. The purpose of self-calibration is to derive improved Cartesian coordinates for both the location of grid points on an artifact used for the target and for the coordinate system on the measuring plane of the instrument where the grid points are measured. Such self-calibration may be used to determine and correct for the distortions introduced by an imaging tool.
Prior art calibration artifacts and methods have several drawbacks. Conventional imaging system artifact structures generally have low information content and poor FOV sampling. Isolated CD patterns, with known, externally calibrated, feature geometry sample only a small subset of the FOV. Box-in-box (BiB) or one dimensional (1-D) grating overlay patterns cannot determine the tangential component of distortion. Additionally, external calibration of feature geometries is a laborious task. Prior art features that are designed to sample specific imperfections in the objective, e.g., arrangements of blazed grating structures, typically provide information that does not translate simply into in-line CD or overlay measurement performance. Accordingly, there is a need for an improved artifact and method for the comprehensive across-FOV calibration and matching of imaging systems.
U.S. Patent Application 2007/0058169, the disclosure of which is hereby incorporated by reference, discloses an improved method and target system for determining overlay or alignment error between different fields in the same lithographic level or among the many lithographic levels required to create an integrated circuit. The multi-layer overlay target disclosed therein achieves comparable or superior metrology performance to box-in-box or grating structures, at substantial reduction of metrology target real estate. This method and target has been shown to meet the requirements on current design rules, while giving some unique benefits. However, as future design rules shrink, there is a need to improve on that technology.