1. Field of the Invention
The present invention relates to an integrated circuit having one or more input buffers.
2. Description of the Prior Art
Integrated circuits that operate at CMOS logic levels, presently 0 to 5 volts, usually have a switching point near mid-voltage, about 2.5 volts. These CMOS IC's often must interface with other integrated circuits that operate at TTL logic levels (e.g., 0.8 to 2.0 volts), which have a switching point near 1.4 volts. For this purpose, the input buffers on a CMOS IC chip are designed to receive the TTL input levels and translate them to the CMOS levels used internally on the CMOS chip. However, the need also exists in many cases for one CMOS integrated circuit to interface with another CMOS integrated circuit. In that case, the input buffers are designed to receive the CMOS logic levels. In the prior art, the choice of whether the input buffers are to operate a TTL or CMOS input levels is usually made at the design stage, typically by choosing the ratio of the sizes of the p-channel and n-channel input transistors. For example, for a TTL input buffer, the size of the n-channel input transistor is typically about 10 times the size of the p-channel input transistor, to obtain a relatively low switching threshold. On the other hand, for a CMOS input buffer, the size of the p-channel input transistor is typically about 3 times the size of the n-channel input transistor, to obtain a switching threshold of about one-half the power supply voltage.
In one prior art technique, the DC operating voltage on the source of the p-channel input transistor is set to obtain the desired trigger point of the input inverter, allowing for either a TTL or CMOS input signal level; see U.S. Pat. No. 4,820,937. However, the technique described therein requires a reference voltage generator to obtain the proper voltage level for TTL operation. The reference voltage generator described therein is a relatively complicated analog circuit utilizing an operational amplifier.