1. Field of Invention
The present invention relates to an integrated circuit design system, an integrated circuit design program, and an integrated circuit design method.
2. Description of the Related Art
In order to deal with an increasing reduction in power consumption and miniaturization of processing dimensions, the power supply voltage of semiconductor integrated circuits has been reduced year by year. If the signal amplitude becomes small due to the reduction of the power supply voltage, the threshold voltages of the transistors will become relatively high with respect to the signal amplitude; therefore the ON currents of the transistors will decrease and the delays will increase. For this reason, the threshold voltages of the transistors must also be reduced along with the power supply voltage. However, if the threshold voltages of the transistors are lowered, the leakage current in the OFF state will increase, so the disadvantage will arise that the reduction of the power consumption will be obstructed.
As technology for preventing an increase of such leakage current, the “multi-threshold complementary metal oxide semiconductor (MTCMOS)” circuit technology is known. In the MTCMOS technology, a transistor having a high threshold voltage is inserted into the power supply line for each circuit block performing a specific function. When the circuit block becomes unused, this transistor switch is set OFF, so the leakage current flowing through the transistors in the circuit block is cut off. Due to this, the wasteful leakage current flowing in unused circuit blocks can be greatly reduced.
FIG. 10 is a view of an example of a circuit using MTCMOS technology. Circuit cells 1 and 2 are connected between a power supply line VDD and a ground line VSS and constantly supplied with power. Contrary to this, circuit cells 3 and 4 are connected between the power supply line VDD and a virtual ground line VSSA. These are supplied with power only when the virtual ground line VSSA and the ground line VSS are connected by a high threshold voltage transistor 5.
The high threshold voltage transistor 5 is controlled to be turned on/off in response to a control signal Sc from a not illustrated circuit block. When the circuit cells 3 and 4 become unused, this control signal Sc is set to the low level, so the high threshold voltage transistor 5 becomes OFF. Due to this, the virtual ground line VSSA and the ground line VSS are cut off, and the leakage current of the circuit cells 3 and 4 is cut off.
The circuit cut off from power by the high threshold voltage transistor (hereinafter referred to as an “MTCMOS circuit”) becomes unstable in the signal level of the internal interconnect at the time of shutting off the power. For this reason, in order to prevent the signal in this unstable state from causing a malfunction or otherwise exerting an adverse influence upon the other circuit blocks in operation, processing such as conversion of the unstable state signal to a fixed value is applied. Accordingly, in the design of a semiconductor integrated circuit using MTCMOS technology, it is necessary to correctly verify if the power is correctly turned on/off according to the specifications and whether any malfunctions due to the signal in the unstable state occur.
In a general integrated circuit design system, however, at the stage of the logic design, the power supply of the circuit is treated as being always on, i.e., the situation of the cutoff of the power is not envisioned. For this reason, a circuit turned on/off in power during operation such as an MTCMOS circuit cannot be simulated at the stage of the logic design.
Japanese Unexamined Patent Publication (Kokai) No. 2003-233635 discloses a method of preparation of a logic model by a hardware description language of a digital circuit including an MTCMOS circuit. The method of Japanese Unexamined Patent Publication (Kokai) No. 2003-233635 enables the simulation of a digital circuit, even when an MTCMOS circuit is included, by adding to a higher level of the circuit that turned off the power a description making the value of an input pin in the stand-by state a nonspecific value.
However, the description of the circuit prepared by the method of Japanese Unexamined Patent Publication (Kokai) No. 2003-233635 does not include a description clearly indicating each circuit cell including a high threshold voltage transistor for a power switch (power switch cell) and also does not include a description clearly indicating which circuit cell is cut off from power by which power switch cell. For this reason, when designing the next stage, that is, designing the layout such as the interconnects and arrangement of the circuit cells by using a net list of gate levels obtained as a result of the logic design, the information concerning the above power switch cells must be newly manually added. Accordingly, it suffers from the disadvantage that the efficiency of the design is obstructed, for example, the load of the design work becomes large and human design error easily occurs.
Further, the description added by the method of Japanese Unexamined Patent Publication (Kokai) No. 2003-233635 is only used for the verification of the circuits and is unnecessary in the layout design, so must be deleted. Accordingly, the trouble of such work occurs and becomes a cause obstructing the efficiency of design.