1. Field of the Industrial Application
The present invention relates to a phase locked loop (PLL) circuit and a signal reproducing apparatus for reproducing data with a clock signal supplied by the PLL circuit.
2. Description of the Related Art
When reproducing digital data recorded on a recording medium such as an optical disk, a magnetic disk or a magnetic tape, it is necessary to generate a reproduction clock, that is, a so-called channel clock for pulling a channel bit from a signal read out of the recording medium. For generating a clock, in general, the PLL circuit is used. This PLL circuit may take an analog type or a digital type. The digital PLL circuit basically has the arrangement as shown in FIG. 1.
In FIG. 1, an input terminal 101 is inputted with a signal read from the recording medium such as the so-called EFM (Eight-Fourteen Modulation) signal. This EFM is a modulating system adopted by the so-called CD (compact disk), which operates to modulate 8-bit data into 14-channel bits according to the predetermined modulating rules. The modulated EFM signal includes inverted intervals (inter-edge intervals) in the range of 3T to 11T, where T is a channel bit period and contains a channel clock component.
The digital PLL circuit is arranged to have a phase comparator 102 being inputted with a signal from the input terminal 101, a low-pass filter (LPF) 103, and a variable frequency oscillator (VFO) 104. The output from the VFO 104 is taken as a PLL output clock PLCK at a terminal 105 as well as sent back to the phase comparator 102. The VFO normally uses a voltage controlled oscillator (VCO) for the analog PLL, while for the digital PLL, the VFO uses an oscillator arranged to change a frequency dividing ratio according to input phase error information, such as a number controlled oscillator (NCO).
In the foregoing arrangement, the phase comparator 102 operates to compare the PLL output clock PLCK with the input signal. Then, the compared result is sent to a digital LPF 103 through which a dc signal corresponding to the phase difference is taken out. Based on the phase difference signal, the oscillating frequency of the VFO 104 is controlled so that the resulting PLL output clock PLCK takes synchronization with a channel clock of the input signal (for example, EFM signal).
The phase comparator 102 is arranged as shown in FIG. 2, for example. An input signal (for example, EFM signal) at the input terminal 101 is sent to a first-stage register 121 that is connected in series with a second-stage register 122 and an Exclusive OR gate 123. The output from the register 121 is sent to the register 122 and the Exclusive OR gates 123 and 124. The Exclusive OR gate 124 is inputted with the output from the register 122. The registers 121 and 122 are driven on the PLL output clock PLCK from the terminal 105. The register 122 is inputted with the inverted clock PLCK given by an inverter 125. The output from the Exclusive OR gate 123 is sent to an enable terminal EN of a phase difference counter 126. The output from the gate 123 is inverted by an inverter 128 and then sent to a load control terminal LD. The output from the phase difference counter 126 is sent to a phase register 127. The phase difference counter 126 and the phase register 127 are driven on a master clock MCK sent from a terminal 106. The output from the Exclusive OR gate 124 is sent to a clock terminal of the phase register 127 as a phase register clock. The phase difference data is taken from the phase register 127 through a terminal 107 and then is sent to the LPF 103.
Then, the operation of the phase comparator shown in FIG. 2 will be described with reference to signal waveforms of components shown in FIGS. 3A to 3F.
In a case that the terminal 101 is inputted with the EFM signal as an input signal shown in FIG. 3A and the terminal 105 is inputted with the PLL output clock PLCK shown in FIG. 3B, the Exclusive OR gate 123 operates to output a "H" (High-level "1") signal between a rising time t.sub.1 of the EFM signal and a rising time t.sub.2, of the PLL output clock PLCK, during which the phase difference counter 126 continues to do a counting operation and then outputs a count signal as shown in FIG. 3D. The Exclusive OR gate 124 operates to output a signal that keeps at high level between the rising time t.sub.2 and the falling time t.sub.3 of the PLL output clock PLCK as shown in FIG. 3E. The phase register 127 is inputted with the output from the phase difference counter 126 on the rising timing t.sub.2 as shown in FIG. 3E, so that the output from the phase register 127 is switched as shown in FIG. 3F at the time t.sub.2.
A value to be loaded as initial data from the terminal 108 to the phase difference counter 126 is initialized to such a value as making the counter output value zero when the phase error is zero. The value is shifted to a negative side by a count value corresponding to a half of a period of the PLL output clock PLCK. The master clock MCK supplied to the terminal 106 is normally set as such a frequency as being several times or more as large as the PLL output clock frequency.
The phase difference data from the terminal 107 of the phase comparator as shown in FIG. 2 is sent to the digital LPF as shown in FIG. 4.
The digital LPF shown in FIG. 4 is arranged to have a register 131 on an input side and registers 132 and 133. That is, the phase difference data supplied through the terminal 107 is sent to the register 132 and an adder 136 through the register 131. Then, the output from the register 132 is multiplied by a coefficient from the terminal 135 and then is sent to the adder 136. The output from the adder 136 is sent to an adder 137, the output of which passes through a register 133 and then is multiplied by a coefficient from the terminal 139 through the effect of a multiplier 138. Then, the multiplied result is fed back to the adder 137, and the output of the register 133 is taken through a terminal 140 as an LPF output. These registers 131, 132 and 133 are driven at a filter clock sent from the terminal 110. This clock corresponds to both edges of the PLL output clock PLCK, for example.
The digital LPF operates to take a low-pass component of the phase difference data or the so-called dc component and then apply it to the VFO 104 shown in FIG. 1 as a control voltage.
In case some defects are caused on a recording medium such as a disk by impairments or fingerprints, the edges of the EFM signal read from the medium may be dropped over such a long time as several hundreds micro seconds.
The phase register 127 of the phase comparator shown in FIG. 2 operates to detect the edge of the EFM signal inputted by the registers 121 and 122 and update the phase data as a clock signal. Hence, the drop of the edge of the input signal inhibits to update the phase difference data of the phase register 127. As a result, the phase difference data immediately before the edge of the input signal is dropped is held as it is. The signal level lowered near the defect disallows the edge to be normally detected. Hence, it is more likely that the output from the phase difference counter 126 and the phase difference data from the phase register are greatly disturbed.
Hence, the LPF shown in FIG. 1 is inputted with a value greatly shifted from a center value for a long time, so that the LPF keeps a dc value inside of itself and supplies a dc value. As a result, the oscillating frequency of the VFO 104 shown in FIG. 1 is greatly shifted from the center value.
Afterwards, an optical pickup is departed from the defect of the medium so that the edge of the EFM signal can be properly obtained. Then, the PLL circuit performs a pulling operation. Since the LPF has a great time constant, the PLL circuit disadvantageously needs a long time for pulling in the phase of the signal if the dc value is stored in the filter.