Semiconductor devices may include a tensile-stressed layer for a variety of reasons. For example, metal oxide semiconductor (MOS) devices may include a tensile-stressed layer, which forms part of a channel region of the devices. The tensile-stressed layer may exhibit higher carrier mobility—compared to a similar, non-stressed layer. As a result, devices formed with, for example, a tensile-stressed channel layer or region may exhibit faster switching speeds, better performance, and/or lower power consumption.
Many semiconductor devices use silicon as a semiconducting material for a channel region within MOS devices. In these cases, a tensile stress in the silicon (e.g., a silicon layer) may be created by doping a silicon layer with carbon atoms, which are smaller and have a smaller lattice constant than silicon atoms. Because the carbon atoms are smaller than silicon atoms, when the carbon atoms form part of the substantially silicon crystal lattice, the crystal lattice becomes tensile stressed.
Although doping silicon with carbon can create a tensile stress within a silicon lattice, adding carbon to the silicon lattice may reduce mobility of a carrier within the lattice structure (e.g., a channel region of a device). To compensate for the lower carrier mobility, the silicon may be doped with additional material, such as n-type dopants (e.g., phosphorous, arsenic, or antimony). While, this approach may provide a tensile-stressed silicon region, use of carbon doping may require additional processing steps, materials, and equipment to form a suitable tensile-stressed region or layer having desired carrier mobility. Accordingly, improved methods of forming tensile-stressed silicon regions or layers and structures and devices including the regions or layers are desired.