1. Field of the Invention
This invention relates to integrated circuit memory devices, and, more particularly, to a design structure for a system implementing a memory column redundancy scheme.
2. Description of Background
Existing memory architectures with column redundancy typically have two levels of multiplexing, each providing its own contribution to memory access time. FIG. 1 illustrates an existing architecture. FIG. 1 generally illustrates a simple form of column multiplexing which involves completely replicating a bit of the memory word (here, a “bit” includes a memory array, column mux, and input and output circuit) such that, for example a 2K×16 RAM becomes a 2K×17 RAM; and selecting the full extra (redundant) bit in place of one of the original bits if there is a defect in the memory array of one of the original bits. One of the drawbacks for this type of architecture is that the area overhead of this type of column redundancy is large because a full data bit is replicated. For example, in an “x16” RAM with a 32:1 column mux, 32 bit lines are replicated in the extra bit.
Advanced Static Random Access Memorys (SRAMs) require a hierarchy of local bit lines and global bit lines. The bit-line hierarchy scheme is illustrated in FIG. 2, where a global bit line is common to a number of banks. In each bank, a number of short local bit lines are associated with a global bit line driver (“GColDrvr”). The global bit line driver cannot match the local bit-line pitch. As such, a first level of multiplexing the local bit lines is essential for hierarchical bit lines, which cannot be eliminated or simplified. A 4:1 mux is common for this first stage, and is integrated into the area of the global bit line driver. A smaller number of global bit lines, on relaxed pitch, continue to the edge of the array for a second level of multiplexing. The GlColMux and GlColSel lines achieve this second state of multiplexing. In the example of FIG. 2, the GColMux block is implementing a 4:1 multiplexing, which compounds the 4:1 mux at the GColDrvr to implement a 16:1 overall bit-line multiplex. The intermediate pitch of the global bit lines makes a more efficient form of column redundancy possible: a global column with 4 local bit lines can be the redundant unit multiplexed in, rather than a full data bit with a larger number (e.g., 16 or 32) of bit lines. Existing hierarchical RAMs have separate multiplexors for the global bit line to DataOut mux and for the redundancy steering. However, these two distinct muxes add delay to the access time.
In either multiplexing scheme, the decoding for the select lines of the redundancy mux is “static”; i.e., it is done at power-on and is not part of the access delay. The data path, however, is part of the access delay.