The present invention relates to methods and apparatus for the manufacture of silicon-germanium semiconductor devices.
Complementary metal-oxide-semiconductor (CMOS) technology is widely used in integrated circuits (ICs) due to the lower power consumption of CMOS ICs, as compared to previously preferred NMOS ICs. CMOS is so named because it uses both p- and n-channel transistors in its ICs. However, one of the most fundamental and serious limitations of CMOS technology resides in the p-channel device. Generic, one-micron processes reflect such limitations in the disparate field-effect mobilities associated with n-channel and p-channel devices within a CMOS IC. In such devices, p-channel field-effect hole mobility is approximately two to three times lower than n-channel field-effect electron mobility. Thus, in order to achieve optimum symmetrical switching and driving capabilities, p-channel devices must be more than twice as large as n-channel devices, which undesirably affects packing density of an IC.
To overcome device-operational limitations in bipolar technology, as used in amplifying and switching devices, silicon-germanium (Si1xe2x88x92xGex)/Si heterojunctions were developed. Si1xe2x88x92xGex has an associated band gap that is smaller than that of the silicon. When such a material is used for the emitter material in a bipolar transistor, a higher emitter-injection efficiency is obtained due to the bandgap difference between the silicon base material and the emitter material. To form a Si1xe2x88x92xGex/Si heterojunction, molecular beam epitaxy (MBE) and ultrahigh-vacuum chemical vapor deposition (UHV CVD) are currently used.
It is desirable to adapt Si1xe2x88x92xGex/Si heterojunction technology to improving field-effect mobilities of p-channel MOS devices used in CMOS ICs. However, while MBE and UHV CVD are two methods for forming a Si1xe2x88x92xGex/Si heterojunction, both techniques are not compatible with large-scale manufacturing processes, such as commonly used to form CMOS ICs. MBE and UHV CVD are complicated and expensive. MBE and UHV CVD were developed for use in fabricating bipolar devices, which are intolerable towards microdefects and dislocations resulting from strained layers, due to their extremely small base widths, which require very sharp profiles and transitions. It was not critical to develop an efficient, high volume technique for the fabrication of Si1xe2x88x92xGex layers. Thus, it has not been possible to adapt Si1xe2x88x92xGex/Si heterojunction technology to the large volume manufacture of CMOS ICs. MOS devices are much more tolerant of microdefects and dislocations, since there is no concern about emitter-collector shorts resulting from the extremely small base widths inherent in bipolar devices.
Furthermore, conventional silicon CMOS transistor gates are formed by thermally oxidizing the silicon substrate. When a Si1xe2x88x92xGex layer is formed on a silicon substrate, by MBE or UHV CVD, stable gate oxides can not be later formed on the Si1xe2x88x92xGex layer. Oxides of Ge are not stable, thus, other ways of forming a gate oxide layer are being investigated. One way of forming a stable gate oxide over a Si1xe2x88x92xGex layer is by depositing low temperature CVD oxides. However, such oxides have a resulting undesirable higher surface state density. Another way of forming a stable gate oxide over a Si1xe2x88x92xGex layer is by reoxidation of a silicon cap layer applied over the Si1xe2x88x92xGex layer. However, using a silicon cap layer results in a buried channel structure with an undesirably large effective gate oxide thickness. Furthermore, at high gate voltages, many of the Si1xe2x88x92xGex layer carriers migrate to the silicon cap layer. The net result is a loss in device performance.
There is a need for a method of large volume manufacturing of Sixe2x80x94Ge semiconductor devices. In particular, there is a need for a method of large volume manufacturing of silicon-germanium CMOS ICs, in which a stable gate oxide layer can exist over a Si1xe2x88x92xGex transistor channel.
The present invention teaches a method and apparatus for large volume manufacturing of Sixe2x80x94Ge complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Si1xe2x88x92xGex is formed under existing gate oxide layers, eliminating the problem of forming stable gate oxides directly over a Si1xe2x88x92xGex layer. A high dose Ge layer is implanted under the gate oxide layer. Next, a Si1xe2x88x92xGex layer is grown by solid phase epitaxial (SPE) regrowth, such that lattice mismatch is minimized between the Si1xe2x88x92xGex layer and the underlying Si substrate. SPE is performed in a low temperature furnace, for approximately ten minutes. Implantation and anneal steps are commonplace in the large volume manufacture of CMOS ICs. Thus, this invention does not add significant cost or complexity to the manufacture of CMOS ICs, while providing the ability to manufacture high volume CMOS ICs with enhanced field effect hole mobility.
According to one aspect of the invention, the Si1xe2x88x92xGex layer formed in this invention has a critical layer thickness, which depends on the molar fraction, x, of germanium present in the Si1xe2x88x92xGex compound formed. As long as the critical layer thickness is not exceeded, Si1xe2x88x92xGex will form defect-free during SPE regrowth. By forming p-channels in accordance with the method of the invention, valuable chip space is conserved, enabling high density chips to be formed. P-channel transistors are able to be formed in approximately the same amount of space as n-channel transistors due to the increased field effect hole mobility, while obtaining symmetrical switching and driving capabilities.