1. Field of the Invention
Embodiments of the present invention relate to a negative drop voltage generator and a method of controlling negative voltage generation. This application claims priority under 35 U.S.C. §119 from Korean Patent Application 2003-58576, filed on Aug. 25, 2003, the contents of which are hereby incorporated by reference in their entirety.
2. Description of the Related Art
The development of volatile semiconductor memories (e.g. a dynamic random access memory (DRAM)) has increased the operating speed of the memories. Also, the development has decreased the chip size of the memories, increasing integration of the memories.
In a DRAM having a plurality of unit memory cells (each of which may include one access transistor and one storage capacitor), a bulk bias voltage generator may be employed to generate a substrate or bulk bias voltage. Since the bulk bias voltage (VBB) has a negative voltage level in relation to a power voltage (VDD), the bulk bias voltage generator is often referred to as a negative drop voltage generator.
There are at least three reasons why a bulk bias voltage (VBB) is supplied to a silicon substrate or bulk region. A first reason is to prevent a partial forward bias for a PN junction of circuit configurative devices within a semiconductor memory device (i.e. to prevent data loss or latch-up of memory cells). A second reason is to reduce a change of threshold voltage in a MOS (Metal Oxide Semiconductor) transistor through a back gate effect, to promote stabilization of the device. A third reason is to reduce the necessity for increasing a consistency of channel stop implant provided below a field oxide layer by increasing a threshold voltage of parasitic MOS transistors and to reduce a PN junction capacity of a MOS transistor by applying a reverse bias, to increase the operating speed.
In a DRAM, as one of several methods to increase a refresh performance, a negative word line drive scheme applies a negative word line voltage as a gate voltage during precharging. In the DRAM employing this driving scheme, a negative word line driving voltage VBB2 is also a bulk bias voltage VBB1. Accordingly, a single negative drop voltage generator may be employed to obtain the bulk bias voltage VBB1 and the word line driving negative voltage VBB2. Alternatively, individual negative drop voltage generators may be employed to independently obtain the bulk bias voltage VBB1 and the word line driving negative voltage VBB2.
Regardless of the bulk bias voltage and the word line driving negative voltage being generated by one negative drop voltage generator or independently through separate private-use negative drop voltage generators, it may be important to reduce ripple and generate a stabilized negative voltage by more efficiently controlling the negative drop voltage generator or generators, in order to accomplish improved performance of the semiconductor memory device.
An EDS (Electrical Die Sorting) test of semiconductor memory devices applies voltage stress or temperature stress higher than the actual use environment, during a predetermined time, in the semiconductor memory device. After the application of stress, an electrical characteristic of the semiconductor memory device is checked, and a chip involving a weak cell is screened. A determination is made, if a chip has a defect or a characteristic deviating from a normalized distribution.
In the EDS test, the bulk bias voltage VBB1 needs to be applied lower than a level of a bulk bias voltage VBB1 used in normal operation, in order for a severe test of the semiconductor memory device. In order to screen the chip under a worse condition in a tRDL (last data in to row precharge) test, concerning a refresh characteristic test, a bulk bias voltage VBB1 of a cell transistor (including a memory cell) is applied lower than a level of bulk bias voltage used in normal operation. The word line driving negative drop voltage generator may generate a negative voltage VBB2 having a level lower than the determined voltage level. In other words, when lowering the negative voltage VBB1 (generated in the negative drop voltage generator for use of bulk bias), there is a problem that the negative voltage VBB2 (which is lower than the predetermined voltage level) is generated together with the bulk bias voltage VBB1 by the word line driving negative drop voltage generator.
The bulk bias voltage VBB1 and the word line driving negative voltage VBB2 are substantially the same level in normal operating mode of the semiconductor memory device. However, in a memory test mode, the bulk bias voltage VBB1 and the word line driving negative voltage VBB2 are different levels from each other, in order to obtain test reliability. Accordingly, voltage generation for bulk bias voltage VBB1 and negative voltage VBB2 must be adequately controlled between a normal operating mode and a test mode. Further, it is also desirable to reduce ripple by more efficiently controlling a negative drop voltage generator to appropriately generate a stabilized negative voltage in conformity with a selected operating mode.
It is also desirable to provide a technology where the bulk bias voltage VBB1 and the word line driving negative voltage VBB2 can be generated together or generated separately from each other, according to an operating mode (in response to a specific external signal).