As the demands of technology have increased, both the density and the multiplicity of functions performed by a given integrated circuit have increased. In addition, the speed at which data is processed through these integrated circuits has also increased. These devices are generally referred to as Very Large Scale Integrated Circuits (VLSI). To reliably realize VLSI devices, new techniques have been developed to both fabricate the device at the semiconductor chip level and also to package the chip. There are some inherent disadvantages to this increased density and speed since the VLSI devices must still be interfaced with peripheral circuits and thus must have some output ports, control ports, etc. Due to the large number of functions that are performed by a given VLSI chip, the number of interface connections or IC pins is relatively low as compared to the number of functions that the device performs. The result is that the internal functions are relatively inaccessible for troubleshooting and failure analysis, since use of interface connections must be optimized and they are generally dedicated to the functional modes of the device rather than testing modes.
Once a system is manufactured utilizing VLSI circuits, it is important to maintain some form of built-in test for both the VLSI chip and the system in which it is incorporated. This test can be performed at many levels such as the chip level, the board level, and the system level with the chip level being the lowest level. The purpose of the built-in test is to determine if the system meets operating specifications prior to performing a desired function. Failures can be in the form of defective interconnects between connectors and the various components, defective interconnects between VLSI chips on a given circuit board, or even defective interconnects between the pins of the VLSI chip and the board itself. At the chip level, failures can be of two types, a defect in the functional portion of the chip or the interface circuits between the functional portion of the chip and the IC pins. A large percentage of chip failures are due to defects in the output interface circuits. At the board level, failures are either due to bad interconnects on the PC board or faulty contact of the IC pins with the interconnect pattern on the board. System level defects are normally in the form of faulty connections between control and signal buses.
In performing a system test, prior art systems have utilized a central processor or similar peripheral device which generates various test patterns for input to each of the devices in the system. The functions of each of the devices are also controlled such that each device can be independently tested or, alternately, the various circuits on the various boards controlled to interact in a predetermined manner and output a predetermined signal. This output signal for either type of test is compared with an expected result and a determination made as to whether the results are in the acceptable operating range. If the results are not within the acceptable range, the system is classified as a failure and it must be either repaired or replaced.
To perform built-in tests on a system at either the system level, the board level or the chip level, it is desirable to have each of the various levels perform a self-test in response to a single prompt signal. This self-testing requires built-in test circuits that are different from the normal functional circuitry. These test circuits generate test signals, process output signals and control the general test itself. Present systems for providing built-in testing of individual components require dedicated pins on the IC for allowing access to the functional portions of the IC. This is a disadvantage in that a large number of dedicated pins may be required. Dedication of an IC pin to a test feature is undesirable and should be minimized whenever possible
In view of the above disadvantages, there exists a need for self-testing VLSI circuits that do not require the use of a large number of dedicated IC pins to interface with the VLSI circuit in the test mode.