The present invention relates to an information processing unit such as a general purpose computer in which instructions are executed one by one conceptually as viewed from a program, and more particularly to a system important in the parallel execution of a plurality of instructions in a plurality of execution units to improve a processing speed.
Of computers in which instructions are executed one by one conceptually, those which are intended to improve the processing speed by parallel execution are shown in "An Efficient Algorithm for Exploiting Multiple Arithmetic Units" by R.M. Tomasulo, IBM Journal, 1967 Jan. which relates to IBM 360/91, JP-A-58-176751 entitled "Instruction Decode Unit", U.S. Pat. No. 4,626,989 (or corresponding EU-A-101,596 or JP-A-59-32045) and EU-A150,449 (or corresponding U.S. Patent application Ser. No. 682,839 or JP-A-60-129838). In those computers, since a plurality of conceptually ordered instructions are executed in different execution units, results thereof may be written in a different order than the conceptual order. Thus, when an interruption occurs, it is generally difficult to determine up to which instruction has been executed with regard to the instruction causing the interruption. Where execution based on prediction is done until branch is determined by a branch instruction, if a result of prediction is miswritten when the prediction fails, a recovery thereof is necessary.
In an information processing apparatus in accordance with the IBM 370 architecture, the reversal of the write order as described above should not be observed from the program. Accordingly, in order to comply with the instruction execution order in the 370 architecture in an information processing apparatus which has a plurality of execution units and in which instructions may be simultaneously or disorderly executed, data and addresses thereof on fields of a memory which will be lost by the writing of the result are previously buffered before the execution of the instructions, and when the instruction execution overruns and it should be invalidated, the buffered data must be returned to the original fields. This method may be used for similar purpose as disclosed in JP-B-56-40382 entitled "Information Processing Apparatus" or its corresponding U.S. Pat. No. 4,385,365. However, this method is complex in control, needs buffer registers for data and addresses and hence is expensive, needs a time to recover data and hence an overall performance of the processing apparatus is lowered if the invalidation of instruction execution frequently occurs. When write overrun occurs to a main memory in the 370 architecture, data written by overrun from other processor or channel prior to recovery of the field may occur. In this case, the order rule of the architecture is not complied with even by the order assurance system by the buffer and recovery.
Such an overrun of the instruction execution occurs when an interrupt associated with the instruction execution occurs or when misprediction is detected during predicted execution of a succeeding instruction of a branch instruction.