1. Field of the Invention
The present invention relates to a data processing apparatus that carries out processing while accessing instructions and data stored in an internal memory. Particularly, the present invention relates to a data processing apparatus capable of processing at high speed using a memory of low speed and low power consumption.
2. Description of the Background Art
In recent years, data processing apparatuses such as a CPU (Central-Processing Unit) and the like have become more widespread, and the demand to improve the processing speed of the data processing apparatus seems insatiable. In the conventional data processing apparatus such as a CPU, the instruction fetch mechanism, instruction decoding mechanism, instruction execution mechanism, and the like are set in a pipelined manner. The processing performance of the data processing apparatus is improved by increasing the frequency of the operating clock as well as reducing the access cycle of the memory to obtain memory access within one pipeline cycle time (one clock of the operating dock).
However, it is difficult to realize a memory of large capacity with a short access time. This issue was solved by building a memory of high speed and low capacity represented by a cache memory and a main memory of low speed and large capacity in a hierarchical manner to carry out operation as if there was a memory of high speed and of large capacity. The conventional data processing apparatus employing such a hierarchical memory is disclosed in many documents.
In realizing a memory of large capacity and high speed by the configuration of the hierarchical memory, a wait cycle must be inserted in the memory access cycles when the data processing apparatus is to access an instruction or data that could not be incorporated in the high speed memory of small capacity (cache miss). There was a problem that the performance of the data processing apparatus is degraded. In order to increase the operation speed of the memory, the drivability of the transistor employed in the memory must be increased. There was a problem that the power consumption of the memory is increased if a high speed memory of large capacity is incorporated in the data processing apparatus.