The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a low-leakage contact in an MOS transistor device structure. Merely by way of example, the invention has been applied to dynamic random access memory devices, commonly called DRAMs. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to transistors in other MOS circuits that are susceptible to performance degradation caused by leakage current.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. Making devices smaller is very challenging, as each process used in integrated circuit fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed.
An example of such a process is the manufacture of cell devices for DRAMs. Such process includes, among others, those for the memory array in stack based capacitors and trench based capacitors. Such process also includes forming a contact between a transistor and a memory cell. The leakage current in such contact regions can cause charge loss in the DRAM cell and shorten the time between refresh operations. Additionally, cell transistor regions are often difficult to manufacture and generally require complex manufacturing processes and structures. These and other limitations will be described in further detail throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.