This invention relates to a drive circuit for a flat display apparatus and a flat display apparatus which can be applied to a display apparatus which is configured using, for example, organic EL (Electro Luminescence) devices.
Conventionally, a liquid crystal display apparatus which is a flat display apparatus is configured such that the gamma characteristic is changed over by setting of a reference voltage to be used for a digital to analog conversion process as disclosed, for example, in Japanese Patent Laid-Open No. Hei 10-333648 (hereinafter referred to as Patent Document 1).
A typical liquid crystal display apparatus is shown in FIG. 8. Referring to FIG. 8, the liquid crystal display apparatus 1 shown includes a display section 2 in which pixels (P) 3R, 3G, 3B each formed from a liquid crystal cell, a switching element for the liquid crystal cell and a holding capacitor are arranged in a matrix. In the liquid crystal display apparatus 1, each of the pixels 3R, 3G, 3B is connected to a horizontal drive circuit 4 and a vertical drive circuit 5 through a signal line (column line) SIG and a gate line (row line) G, respectively. The vertical drive circuit 5 successively selects the pixels 3R, 3G, 3B while the horizontal drive circuit 4 sets the gradations of the pixels 3R, 3G, 3B using driving signals therefrom thereby to display a desired image. Further, the pixels 3R, 3G, 3B having color filters of red, green and blue provided therefor are arranged successively and cyclically so that a color image can be displayed.
To this end, in the liquid crystal display apparatus 1, image data DR, DG, DB of red, green and blue to be used for display are inputted simultaneously and parallelly from an apparatus body 6 to a controller 7, and the gate lines G of the display section 2 are driven by the vertical drive circuit 5 with timing signals synchronized with the image data DR, DG, DB. Further, the image data DR, DG, DB are time division multiplexed to produce a single series of image data D1 so as to correspond to driving of the signal lines SIG by the horizontal drive circuit 4, and the signal lines SIG are driven by the horizontal drive circuit 4 with the thus produced image data D1.
FIG. 9 is a block diagram showing a detailed configuration of the horizontal drive circuit 4 and the controller 7. Referring to FIG. 9, the controller 7 successively stores and outputs image data DR, DG, DB outputted from the apparatus body 6 into and from a memory 10 under the control of a memory control circuit 9 to time division multiplex and output the image data DR, DG, DB in a single system such that image data of the same color may successively appear in a unit of a line in a unit of a horizontal scanning period so as to correspond to driving of the signal lines SIG by the horizontal drive circuit 4. More particularly, the horizontal drive circuit 4 successively drives the red pixels 3R, green pixels 3G and blue pixels 3B in a unit of a line, and consequently, the controller 7 outputs the image data D1 such that the red image data DR, green image data DG and blue image data DB are repeated successively and cyclically in a unit of a line as seen from FIG. 10B.
The controller 7 produces various timing signals synchronized with the image data D1 by means of a timing generator (TG) 11 and outputs the timing signals to the horizontal drive circuit 4 and the vertical drive circuit 5. It is to be noted that the timing signals include a clock CK (FIG. 10A) for the image data D1, a start pulse ST (FIG. 10C) and a strobe pulse (FIG. 10D) indicative of timings of a start and an end of the image data DR, DG, DB of the different colors of the image data D1.
The controller 7 produces original reference voltages VRT, VB to VG, VRB, which are used as references for production of reference voltages to be used for a digital analog conversion process, by means of an original reference signal production circuit 12 and outputs them to the horizontal drive circuit 4.
The horizontal drive circuit 4 inputs image data D1 outputted from the controller 7 to a shift register 13 so that the image data D1 are successively distributed and outputted to systems of signal lines of the display section 2. The reference voltage production circuit 14 produces and outputs reference voltages V1 to V64, which correspond to different gradations of the image data D1, from the original reference voltages VRT, VB to VG, VRB inputted thereto from the controller 7.
Digital to analog conversion circuits (D/A) 15A to 15N perform a digital to analog conversion process for output data of the shift register 13 and output drive signals which are time division multiplexed drive signals of three adjacent ones of the signal lines SIG. The digital to analog conversion circuits 15A to 15N selectively output the reference voltages V1 to V64 produced by a reference voltage production circuit 14 in response to output data of the shift register 13 to perform a digital to analog conversion process of the image data outputted from the shift register 13.
Amplification circuits 16A to 16N amplify and output the output signals of the digital to analog conversion circuits 15A to 15N to the display section 2, respectively. In the display section 2, the output signals of the amplification circuits 16A to 16N are successively and cyclically outputted to the signal lines SIG for the pixels 3R, 3G, 3B of red, green and blue by means of selectors 17A to 17N, respectively.
In this manner, the reference voltages V1 to V64 produced from the original reference voltages VRT, VB to VG, VRB are selectively used to produce drive signals for the signal lines SIG. FIG. 11 shows in block diagram a configuration of the original reference signal production circuit 12 used to produce the original reference voltages VRT, VB to VG, VRB and the reference voltage production circuit 14 used to produce the reference voltages V1 to V64.
Referring to FIG. 11, the original reference signal production circuit 12 shown includes a voltage dividing circuit 21 formed from a predetermined number of resistors connected in series. The voltage dividing circuit 21 divides a reference voltage production voltage VCOM to produce the original reference voltages VRT, VB to VG, VRB. Consequently, the original reference signal production circuit 12 produces the original reference voltages VRT, VB to VG, VRB by resistor voltage division and outputs them through amplification circuits 24A to 27H. It is to be noted that, where the liquid crystal display apparatus 1 is applied to a liquid crystal display apparatus, the original reference signal production circuit 12 is configured such that the voltage to be applied to the voltage dividing circuit 21 is changed over by a selection circuit 22 and an inversion amplification circuit 23 so as to cope with line inversion or frame inversion. FIG. 10F illustrates the potential of a signal line SIG where line inversion is involved.
Meanwhile, the reference voltage production circuit 14 includes a resistor series circuit 26 formed from voltage dividing circuits R1 to R7 connected in series. Each of the voltage dividing circuits R1 to R7 includes a predetermined number of resistors having an equal resistance value and connected in series. The original reference voltages VRT, VB to VG, VRB are inputted through amplification circuits 27A to 27H to one end of the resistor series circuit 26, nodes of the voltage dividing circuits R1 to R7 which form the resistor series circuit 26 and the other end of the resistor series circuit 26, respectively. Consequently, the reference voltage production circuit 14 divides potential differences by the original reference voltages VRT, VB to VG, VRB produced by the original reference signal production circuit 12 further by means of the voltage dividing circuits R1 to R7 to produce the reference voltages V1 to V64 within the range of the original reference voltages VRT and VRB.
Since the reference voltages V1 to V64 are produced from the original reference voltages VRT, VB to VG, VRB in this manner, the numbers of resistors which form the voltage dividing circuits R1 to R7 of the reference voltage production circuit 14 are individually set to predetermined numbers, and the original reference voltages VRT, VB to VG, VRB are divided so that a plurality of reference voltages V1 to V64 corresponding to gradations of the image data D1 can be outputted.
In the original reference signal production circuit 12, the values of the resistors which form the voltage dividing circuit 21 are set so that an image may be displayed with a desired gamma characteristic by means of the reference voltages V1 to V64 corresponding to the gradations of the image data D1 in this manner. Consequently, as seen from a curve L1 in FIG. 12 where the voltage VCOM is set to 5 V, a desired gamma characteristic can be assured by polygonal line approximation depending upon setting of the original reference voltages VRT, VB to VG, VRB. Further, in the original reference signal production circuit 12, the original reference voltages VRT, VB to VG, VRB to be outputted from the voltage dividing circuit 21 can be changed over by a change of the wiring line pattern. Thus, as seen from a curve L2 shown for contrast with the characteristic indicated by the curve L1 in FIG. 12, for example, while the original reference voltages VRT and VRB which are potentials at the opposite ends are fixed, the remaining original reference voltages VB to VG can be varied within a range indicated by arrow marks to vary the gamma characteristic variously.
In the liquid crystal display apparatus 1 wherein the gamma characteristic can be changed over by setting of the original reference signal production circuit 12 which produces the original reference voltages VRT, VB to VG, VRB in this manner, while the controller 7 including the original reference signal production circuit 12 is formed from a control IC, the horizontal drive circuit 4 is formed from a driver IC. Consequently, according to the liquid crystal display apparatus 1, products of different gamma characteristics can be produced by replacing only the control IC, and consequently, upon modification to the gamma characteristic, the period of time required for the modification can be reduced. It is to be noted that reference characters CA to CH denote stray capacitances between the two ICs.
Incidentally, one of such flat display apparatuses as described above is a display apparatus which uses organic EL devices. Also with regard to a display section of such a display apparatus which uses organic EL devices as just described, a method has been proposed wherein gradations of the individual organic EL devices are set by driving of signal lines SIG similarly as in the case of the display section of the liquid crystal display apparatus described above. It is estimated that the display section of organic EL devices which uses the method just described can be applied to a configuration of a display apparatus using a control IC used in the liquid crystal display apparatus or a like apparatus.
However, where organic EL elements are used, the light emission characteristic differs among different colors and among different products, and besides it exhibits a secular change. Therefore, it is necessary to set the reference voltages V1 to V64 differently in accordance with the light emission characteristics of the organic EL devices. This gives rise to a problem that the drive circuit of the liquid crystal display apparatus described hereinabove with reference to FIG. 8 cannot be applied to an actual configuration of a display apparatus. In particular, where organic EL elements are used, it is necessary to adjust the black level and the dynamic range for each color and for each product. It is to be noted that it is known that the gamma characteristic itself of an organic EL device does not require any adjustment. Consequently, where the original reference signal production circuit 12 shown in FIG. 11 is applied, it is necessary to adjust the voltage across the voltage dividing circuit 21 for each color and for each product.
One of possible solutions to the problem just described is, for example, to configure an original reference voltage production circuit 30 in such a manner as seen in FIG. 13. Referring to FIG. 13, in the original reference voltage production circuit 30 shown, digital to analog conversion circuits (D/A) 31A to 31H produce original reference voltages VRT, VB to VG, VRB individually in response to original reference voltage setting data DV.
Of the digital to analog conversion circuits 31A to 31H, the digital to analog conversion circuits 31A and 31H used for production of the original reference voltages VRT and VRB set to the voltages at the opposite ends divide the reference voltage production voltage VCOM by means of the voltage dividing circuits 32A and 32H to produce a plurality of candidate voltages for original reference voltages. The voltage dividing circuits 32A and 32H are each formed from a series circuit of a plurality of resistors having an equal resistance value, and divide the reference voltage production voltage VCOM with a resolution corresponding to the number of bits of the original reference voltage setting data DV and outputs the divided voltages.
Selectors 33A and 33H select a plurality of candidate voltages outputted from the voltage dividing circuits 32A and 32H in response to the original reference voltage setting data DV and produce and output original reference voltages VRT and VRB in response to the original reference voltage setting data DV, respectively.
Meanwhile, the other digital to analog conversion circuits 31B to 31G except the digital to analog conversion circuits 31A and 31H produce, similarly to the digital to analog conversion circuits 31A and 31H, a plurality of candidate voltages for the original reference voltages VB to VG from divided voltages by the voltage dividing circuits 32B to 32G and selectively output the candidate voltages to the original reference voltages VB to VG in response to the original reference voltage setting data DV by means of selectors 33B to 33G. The digital to analog conversion circuits 31B to 31G are connected to the original reference voltages VRT and VRB from the digital to analog conversion circuits 31A and 31H while the voltage dividing circuits 32B to 32G used to produce candidate voltages for the original reference voltages VB to VG are connected in series between the digital to analog conversion circuits 31B to 31G.
A decoder 35 successively fetches the original reference voltage setting data DV outputted from the controller or the like and selectively outputs the fetched data to the digital to analog conversion circuits 31A to 31H at timings corresponding to changeover of contacts in the selectors 17A to 17N.
According to the configuration described above, it is possible to set the original reference voltage setting data DV for each color so as to cope with the light emission characteristic which differs among different colors. Further, the original reference voltage setting data DV can be set for each product to correct the dispersion in light emission characteristic which depends upon the product. Further, also it is possible to cope with a secular change of the light emission characteristic.
Further, as seen from FIG. 14, in the case of the original reference voltages VB to VG except the potentials at the opposite ends from among the original reference voltages VRT, VB to VG, VRB, it is difficult to vary the voltage exceeding the ranges of the candidate voltages outputted from the voltage dividing circuits 32B to 32G connected in series to each other. Therefore, as seen from FIG. 15 in comparison with FIG. 14, even if the original reference voltage setting data DV is set because of invasion of noise, outputting of a drive signal of an extreme gamma characteristic can be prevented, and significant deterioration of the picture quality by noise can be prevented.
Further, since the opposite ends of the voltage dividing circuits 32B to 32G connected in series to each other in this manner are connected to the original reference voltages VRT and VRB used as the first and second original reference voltages, if the original reference voltages VRT and VRB are varied by black level adjustment or dynamic range adjustment which is correction of the light emission characteristic, then also the original reference voltages VB to VG vary following up the variation of the original reference voltages VRT and VRB in accordance with the resistor voltage dividing ratio by the voltage dividing circuits 32B to 32G connected in series to each other as seen from FIG. 16 in comparison with FIG. 14. In other words, any dispersion in light emission characteristic of each organic EL device can be corrected by black level adjustment or dynamic range adjustment without providing any variation to the gamma characteristic. Consequently, the adjustment operation can be simplified.
Further, by changing the setting of the original reference voltage setting data DV and further by changing over the line unit or the frame unit, the configuration shown in FIG. 13 can be applied also to a liquid crystal display apparatus.
However, the configuration shown FIG. 13 has a problem in that the dynamic range and the black level cannot be adjusted with a high degree of accuracy, and this may possibly give rise to appearance of a color drift on the display.
In particular, in the example of FIG. 13, for example, if the original reference voltage setting data DV are formed as 6-bit data and the reference voltage production voltage VCOM is set to 5 V, the original reference voltages VRT and VRB can be produced with a resolution of approximately 80 mV (5 [V]/64). In this instance, for example, if a gamma characteristic by a great dynamic range is set as seen in FIG. 14, then a resolution substantially sufficient for practical use is obtained. However, if a gamma characteristic by a small dynamic range as seen in FIG. 16 is set, then the resolution becomes coarse, and consequently, it is difficult after all to adjust the dynamic range and the black level with a high degree of accuracy.
In particular, if the potential difference between the original reference voltages VRT and VRB is set to 5 V, then the resolution for the luminance of the emitted light is 1.6% (80 mV/5,000 [mV]). However, if the potential difference between the original reference voltages VRT and VRB is set to 2 V, then the resolution for the luminance of the emitted light is 4.0% (80 mV/2,000 [mV]), and the accuracy in adjustment drops as much. Thus, a color drift is caused.
In this instance, it is a possible idea to set the resistance values of the resistors from which the voltage dividing circuits 32A and 32H are formed to different values so as to partially enhance the resolutions of the original reference voltages VRT and VRB to be outputted from the selectors 33A and 33H. However, according to this countermeasure, it becomes to set the original reference voltages VRT, VB to VG, VRB to various values. Also it is a possible idea to provide a configuration similar to the configuration which uses the digital to analog conversion circuits 31B to 31G also in each of the digital to analog conversion circuits 31A and 31H so as to produce the original reference voltages VRT and VRB. However, this makes the configuration very complicated. Also it is a possible idea to increase the bit number of the original reference voltage setting data DV relating to the original reference voltages VRT and VRB and configure the voltage dividing circuits 32A and 32H and the selectors 31A and 31H with a resolution increase. According to the countermeasure just described, however, when the dynamic range decreases or in a like case, the integrated circuit must be newly fabricated.