A typical example of a semiconductor device having inter-electrode gaps of its memory cell transistors filled with insulating films is a NAND flash memory. Each memory cell transistor of the NAND flash memory is provided with control gate electrodes constituting the word line connecting the cells. Conventionally, a silicon oxide film and a silicon nitride film which is required in the backend steps are formed on the sidewalls of the word line. Further, interlayer insulating films are filled between the word lines. The above described configuration is described in JP 2000-311992 A, for example.
Further integration of design rules in integrated semiconductor circuits has discouraged employment of the above described configuration in view of the following respects. Narrower gaps between the word lines connecting the gate electrodes causes increase in the coupling capacitance between the adjacent memory cell transistors. Increased coupling capacitance becomes a problem especially when the insulating film filled between the word lines has high dielectric constant. Such being the case, it is difficult to employ a configuration that forms silicon nitride film having higher dielectric constant than the silicon oxide film on the sidewalls of the word line as described in the aforementioned document.
On the other hand, growing integration has reached a point where the level of resistance of the silicide formed on the upper portion of the gate electrode impose adverse effect on the device characteristics and conventional materials such as tungsten silicide (WSi) are no longer effective in such configuration. It has been known that alternative use of materials such as cobalt silicide (CoSi2) provides satisfactory characteristics as far as resistance is concerned.
Employing cobalt silicide as a gate electrode of a memory cell involves a step requiring low temperature processing to be performed in the backend step. Thus, a step is introduced to render partial silicidation of the upper portion of the gate electrode after etching the gate electrode. Hence, a cobalt film for silicide formation is initially formed (primarily by sputtering process) on the upper surface of the polycrystalline silicon film, the polycrystalline silicon film constituting the gate electrode being isolated to form the gate electrode. Thermal processing is subsequently performed to cause the aforementioned silicide alloying reaction. In order to ensure the silicide reaction of the polycrystalline silicon by the cobalt film to take place, a wet treatment such as DHF (dilute HF) is conventionally introduced for the purpose of cleaning the surface of the polycrystalline silicon film.
Also, when introducing a process using copper (Cu) as a metal interconnect, in the backend step of the silicide forming step, a silicon nitride film, for example, effective in preventing intrusion of Cu is disposed as a barrier film between the gate electrodes and metal interconnects in order to prevent intrusion of Cu into the active regions of the memory cell, and the like.
However, introduction of wet treatment involving the use of DHF, and the like, for cleaning the surface of the polycrystalline silicon film in turn causes the following deficiencies. Firstly, in case interlayer insulating films such as a silicon oxide film filling the inter-electrode gaps (recess) are formed, the wet treatment etches back the interlayer insulating film. On the other hand, when filling the inter-gate electrode gap having high aspect ratio with a silicon oxide film, seams are prone to occur in the silicon oxide film. Thus when the seams are exposed by etch back, a wet treatment performed under such state causes introduction of etching liquid into the seams, consequently progressing the etch and resulting in voids.
Occurrence of cavities or voids allows intrusion of the silicon nitride film formed as a barrier film in the backend process and the higher dielectric constant of silicon nitride film relative to silicon oxide film causes adverse effects such as increase in parasitic capacitance between the cells. Also, intrusion of silicon nitride film between the word lines cause deficiencies such as application of electric potential on the word line from the select gate which has relatively high voltage applied to it.