The invention relates to a method for the unidirectional and interference-safe transmission of digital data via radio waves, wherein the data which are composed of data packets each comprising a defined number of bytes and of at least one synchronization packet are transmitted from a transmitter to a receiver, a device for carrying out this method as well as a protocol for the unidirectional and interference-safe transmission of digital data via radio waves from a transmitter to a receiver, wherein the data are composed of data packets each comprising a defined number of bytes and of at least one synchronization packet.
The invention, in particular, refers to a protocol for the transmission of digital data, which is immune against bursty interferences, e.g. GSM signals in the 900 MHz frequency band, and which requires a minimum of hardware for the transmitter and the receiver in order to thereby guarantee interference-free transmission.
Such a protocol is used for the transmission of data packets of determined and limited lengths for signaling and controlling automatic procedures. A data packet, as a rule, contains usable information transmitted either encoded or nonencoded and optionally further information regarding data integrity. In addition, also channel coding information and synchronization information data are transmitted in order to ensure the optimum transmission via a radio channel.
Applications of such data transmission systems include remote keyless entry systems, identification systems for vehicles or persons, or machine commands operable by remote control.
In the transmission of data via radio channels, sufficient safety measures against interferences have to be taken, in particular where the frequency band used for transmission, or an adjacent frequency band, is used also by other services. This applies, for instance, to the transmission of data via the frequency band (868 MHz) released for ISM (Industrial Scientific and Medical) services, which transmission is disturbed by interferences with the signal packets of the 900 MHz GSM band.
In order to enhance the immunity against interferences both for data transmissions in which transmission errors of the individual bits occur independently of one another and for communication channels in which transmission errors occur by the splitting of clusters into bursts, the following systems are presently known:
A forward error correction system (FEC), which disregards the burst structure of the interferer. In order to ensure interference-free transmission, this system requires a great number of additional information, though. Besides, this method involves considerable decoding work.
An automatic request system (ARQ) presupposes a feedback channel, which is not available in most cases. Systems comprising a feedback channel call for a more complex hardware, requiring two transmitters/receivers and also time duplex or frequency multiplex system. When using frequency multiplex, the required band width will simultaneously increase.
The known ARQ and FEC systems offer insufficient error correction performances in the event of persistent interference bursts. Channel coding with FEC systems is feasible by one of the following methods:
Block codes offer an error detection capability just sufficient to detect random errors at individual bits. The encoder for a block code divides the information sequence into message blocks each having k information bits which are coded on n bits by the aid of block codes, block coders thus constituting systems without memory. Block codes require only simple circuits, yet are not suitable to prevent transmission errors caused by whole data packets of an interfering transmitter (burst errors).
Convolution codes differ from block codes in that the encoder includes a memory and outputs data at a given time not only as a function of the data inputs effected at that time, but also as a function of previous input blocks. A convolution coder, thus, is a system with a finite memory. Convolution codes, which were developed by Elias, Wozenkraft or Massey, are designed for the recognition of random errors. Convolution codes that are suitable for recovering burst errors, such as those developed by Berlekamp-Preparata or Iwadare-Massey, or interleaved convolution codes involve considerable decoding work. Convolution codes are primarily used for the continuous data transmission and not for the transmission of data packets. Convolution codes also call for long code sequences in order to be immune against burst errors.
Cyclic codes are suitable for both recognizing and recovering burst errors. Fire discovered a large class of cyclic codes correcting burst errors. Fire codes may be decoded by means of simple circuits. Yet, even Fire codes are designed for the continuous transmission of data, but not for the transmission of data packets.
It hence follows that the known codes either are unsuitable for recovering burst errors as is the case, for instance, with block codes or some types of convolution codes, or involve considerable decoding procedures as, e.g., for convolution codes. Cyclic codes and convolution codes, in turn, are suitable only for the continuous data transmission, but not for the transmission of individual data packets as would be of interest for applications such as, e.g., telecommanded locks.
The present invention aims to provide an interference-safe data transmission method which avoids the afore-mentioned drawbacks, which will do with a low-expense hardware both for the transmitter and for the receiver and which, moreover, keeps the power consumption of the receiver low. To solve this object, the initially described method essentially consists in that each byte is transmitted in a manner comprised of flag bits as start bits, information-representing information bits and identification bits encoding the number of the respective byte and carrying the parity information, and that the flag bits and the information bits are inverted in every second byte. The flag bits of each individual byte and the changing identification bits of the byte number prevent the formation of long sequences of 0 or 1. Because of that, the direct current (DC) components of the transmitted signal are kept as low as possible in order to thereby reduce the susceptibility to failures of the transmission. Inverting of the flag bits and of the information bits in every second byte appears like a simple encoding process, thus likewise reducing the direct current (DC) components of the signal. High DC-components in the baseband range during demodulation, i.e., in the merger lead to an offset and hence to information losses. During frequency modulation, carrier frequency shifts may occur, in particular. In order to further enhance the safety of data transmission against interferences, it is advantageously proceeded in a manner that the identification bits are arranged to be distributed within the information bits. The flag bits and the identification bits of all bytes received are known in the receiver on account of their positions within the received data flow such that, due to the distribution of the identification bits within the information bits, error signals will be recognized merely by checking the flag bits and the identification bits. The content of a byte, moreover, is provided with a parity information in one of the identification bits such that even a single error will be recognized. An even number of errors within a byte will be recognized by the additional parity information of the remaining identification bits.
Advantageously, each byte is composed of 3 bits as the start flag, 8 information bits and 3 identification bits, and each data packet is composed of 16 bytes. In this case, the DC-components of the transmitted signal are further reduced in that an unambiguous identification of 16 bytes will be enabled by the aid of the 3 identification bits, if the information bits and the flag bits of every second transmitted byte are inverted. The identification bits representing the byte number are not inverted such that with two consecutive bytes of identical parity the 3-bit identification number will, thus, be the same, yet with one of the two bytes being inverted.
In that case, it is advantageously proceeded in a manner that every second data packet is generated by inverting the preceding data packet such that, for instance, in data packets having an even packet number byte No. 2n+1 will be found inverted and in packets having an odd number byte No. 2n will be found inverted, wherein, in the instant case, inverting a data packet refers to the inversion of all of the bytes of a data packet and inverting a byte refers to the inversion of the flag bits and information bits of the byte. Different coding of one and the same information in data packets having even and odd packet numbers also leads to a reduction of the DC-component of the transmitted signal. For the flag bits, a 0-1-0 bit sequence is advantageously selected, thus enabling the same to serve as a synchronization information.
The method according to the invention, furthermore, is carried out in a manner that switch signals are generated in the receiver, which signals trigger a shift from the quiet mode of the receiver into an operating mode, whereupon the receiver is reset from the operating mode into the quiet mode after a defined time interval. The power consumption of the usually battery-powered receivers may thus be considerably lowered, whereby, for the safe identification of a signal eventually emitted by a transmitter during the short-term operating mode, the receiver after a time interval is reset into the quiet mode, which corresponds to the transmission time of 4 to 8 bits, in particular 6 bits. The receiver is thus able, during the time window in which it is in the operating mode, to recognize a signal of the associated transmitter by way of the, for instance, 6 bits received and optionally change into the permanent receive mode.
In order to prevent the receiver from remaining in a permanent quiet mode, or returning into the quiet mode, on account of the signals of an interfering transmitter, it is proceeded in a manner that the switch signal generator is based on an interval circuit whose intervals follow a defined interval pattern which is periodically repeated, and that integer multiples of the time slots of an interfering transmitter are advantageously selected as said intervals. By integer multiples in this context the result of a multiplication by 1, 2, 3, . . . , n is to be understood. The definition of the shift intervals between quiet mode and operating mode is based on the time frame of the interfering transmitter. The times of shifting into the operating mode must be chosen such that each time slot of the interfering transmitter during the total wake-up procedure will coincide with a time window in which the receiver is in the operating mode only once at most, irrespective of the relative timing of the interfering transmitter and the receiver and irrespective of the tolerance of the receiver quartz. In the event that the interfering transmitter is a GSM signal, an integer multiple of (4, 10, 14) time slots of the interfering transmitter or an integer multiple of (6, 6, 14) time slots of the interfering transmitter is selected as said interval pattern, said intervals being the number of GSM time slots located between the individual times at which the receiver is shifted into the operating mode.
In order to reach sufficient immunity against interference, the transmitter prior to the data packets transmits a synchronization packet comprised of a 0-1 bit sequence over a period of time which is larger than, or equal to, the period of time between the first and last switch signals of an interval pattern of the receiver. In doing so, the synchronization packet serves as a signal which causes the receiver to switch into the permanent receive mode. By transmitting the synchronization packet over a period of time which is larger than, or equal to, the period of time between the first and last switch signals of an interval pattern, it is safeguarded that the receiver within the synchronization packet receive period changes into the operating mode so often as to prevent the synchronization signal from coinciding with the signal of the interfering transmitter at least once during the operating mode time frame. In the event that the interfering transmitter is a GSM signal, the transmitter prior to the data packets transmits a synchronization packet composed of at least 274 bits, in particular 282 bits, and comprised of a 0-1 bit sequence. The intervals between the switching procedures, which are indicated by the number of GSM time slots, may be approximated also by the transmission time of a bit of the receiver, for the (6, 6, 14) pattern this means, for instance, (63, 63, 148), i.e., a 63 bit interval corresponds to approximately 6 GSM time slots and a 148 bit interval corresponds to approximately 14 GSM time slots. Hence, the total interval pattern is 274 bits long. Thus, the synchronization packet having a length of 282 bits is longer such that at least three shift procedures of the receiver are provided within the synchronization packet.
It may, however, also be proceeded in a manner that the transmitter between the individual data packets each transmits a synchronization packet comprised of a 0-1 bit sequence over a period of time which is unequal to an integer multiple of the time frame of an interfering transmitter, wherein the transmitter, for GSM signals constituting the interfering transmitter, between the individual data packets each transmits a 252 bit long synchronization packet comprised of a 0-1 bit sequence.
In the main, the method according to the invention, thus, enables the obtainment of an interference-safe data transmission. The data packets are repeatedly transmitted with the transmission of the synchronization information being provided either prior to the transmission of all of the data packets or prior to the transmission of each individual data packet. In order to transmit, for instance, the complete information in an environment including two interfering packets, the transmission of but three data packets one after the other will be sufficient. For the receiver, there is provided a wake-up procedure, which ensures that the receiver even in the presence of interfering packets will be waked up only if a data packet is being transmitted.
The device according to the invention for carrying out the method according to the invention essentially is characterized in that a code generator is arranged within the transmitter, which code generator encodes in bytes the data to be transmitted, wherein each byte is comprised of flag bits as start bits, information-representing information bits and identification bits encoding the number of the respective byte and carrying the parity information, and the flag bits and the information bits are found inverted in every second byte. Hence result the same advantages as pointed out above, particularly advantageous further developments being apparent from the subclaims.
Another object of the invention is a protocol for the unidirectional and interference-safe transmission of digital data via radio waves from a transmitter to a receiver, wherein the data are composed of data packets each comprising a defined number of bytes and of at least one synchronization packet. Such a protocol is to stand out for its particularly safe and error-free data transmission, wherein, in particular, it is to be immune against interference signals that are transmitted in the form of data packets. Furthermore, the DC-components of the signal transmitted by the aid of this protocol are to be kept low. This will be achieved in that each byte is comprised of flag bits as start bits, information-representing information bits and identification bits encoding the number of the respective byte and carrying the respective parity information, and that the flag bits and the information bits are found inverted in every second byte. Advantageously, the identification bits are arranged to be distributed within the information bits, wherein, furthermore, the flag bits are composed of a 0-1-0 bit sequence. The flag bits of each individual byte and the changing bits of the byte number together with the inversion of individual bytes will cause long sequences of 0 or 1 to be avoided and the DC-components of the signal to be reduced. The latter may be reduced even further if, in addition, every second data packet is generated by inverting the preceding data packet. Due to the fact that the identification bits are arranged to be distributed within the information bits, it is safeguarded that during the action of an interfering transmitter also at least one of the identification bits or of the flag bits will be changed, so that such a change will be recognized in the evaluation circuit of the receiver and the byte concerned will be identified as defective. Identification bit changes and flag bit changes may be readily recognized in the receiver, because their values and positions within the data flow are known.
In order to protect against GSM interfering signals, the protocol according to the invention is composed of 3 bits as the start flag, 8 information bits and 3 identification bits. A synchronization packet comprised of a 0-1 bit sequence, which is part of the protocol, may be arranged in front of all data packets, wherein additional synchronization packets may optionally each be arranged between the individual data packets. When using said protocol in GSM-near frequency bands, the synchronization packets comprise at least 274 bits, in particular 282 bits, and 252 bits, respectively.