1. Field of the Invention
This invention relates to a semiconductor device including semiconductor integrated chips mounted on a package, such as a ceramic package or a plastic package, more particularly to a semiconductor device in which electrodes of the semiconductor integrated chips such as a power processing circuit (a power MOS FET), a signal processing circuit etc. are joined to leadframes of the package through a plurality of bonding wires of different materials, for example Au (Gold) wires and Aluminum (Al) wires.
2. Description of the Prior Art
Recently LSI (Large Scale Integration) or VLSI (Very-Large Scale Integration) devices mounted on one chip, as semiconductor devices, have been fabricated. Each device comprises a semiconductor integrated circuit with a power element as a power processing circuit capable of handling large amounts of electrical power and a signal processing circuit for processing signals (digital/analog) dissipating a relatively small current. These devices are used for applying to an automobile switch (called by "IPD").
In such semiconductor devices, the electrical power portion of the chip (as the power processing circuit) for handling approximately several ampere current or more consists of the power MOSFETs or power bipolar transistors, or other semiconductor devices.
Accordingly, in the prior art, a multi-point wire bonding method is used for wiring multi-point bonding wires to the electrical power portion, to supply electrical power to the outside of the chip, by which a leadframe of the chip is connected to a bonding pad as an electrode of the electrical power portion.
As an example of the multi-point bonding wires formed by the multi-point bonding method in the prior art, for example, there is a following case.
FIG. 1 is a schematic diagram showing a bonding pad as a multi-point bonding portion and bonding pads in a signal processing portion (as the signal processing circuit) in the semiconductor device.
In the same diagram, the power processing portion 2b and the signal processing portion 2a are formed on a chip 2 mounted on a die pad 1 in a package (not shown).
The bonding pads 3a in the signal processing portion 2a, in which small current flows, are joined to inner lead portions 4 (as leadframes of the package) through bonding wires 5 of Au (Gold) or Cu (Copper) wires of approximately 25 to 50 .mu.m in diameter which are commonly used.
While, in the power processing portion 2b or a power portion in the chip 2, the bonding pad 3b is joined to the inner lead portion 8 using the three bonding wires 6 whose diameters are each as large as the bonding wires 5 used in the signal processing portion 2a.
Thus, in the prior art, plural bonding wires must be required per pad to carry the larger current in the power processing portion 2b. When only one bonding wire is used per bonding pad in the power processing portion 2b, the bonding wire cannot carry the amount of large current, for example several amperes.
On the other hand, there are several disadvantages in the multi-point wire bonding method.
For example, the number of the bonding wires needed to bond the inner lead portion 8 are limited by the size of a capillary which leads the bonding wires 6 to a target portion (in such a case, it is the bonding pad 3b) for bonding, the area of inner lead, and others.
When a bonding wire of 50 .mu.m in diameter is used for bonding in the bonding pad of 1.times.3 mm.sup.2 in area, the maximum number of the bonding wires is three or four. Accordingly, the current intensity taken out from the power portion 3b is limited by the number of the bonding wires provided at the bonding pad 3b. Thus, the ability of the power portion 2b is limited and reduced by the number of the bonding wires.
Moreover, in the multi-point bonding method, the bonding wires are integrated in a small area, such as the bonding pad 3b and the leadframe 8, for bonding so that these are short-circuited to each other, then the large short current flows, so as to weld these bonding wires.
Furthermore, the current intensity taken from the power processing portion 2b, or the balance of the power consumption in the power processing portion 2b, are changed by the difference of the portion joined with the bonding wires 6 in the power processing portion 2b or of the interval between the bonding wires 6 so that the power processing portion 2b cannot adequately exhibit its ability.
In the prior art, the multi-point bonding method is commonly used for the bonding of the semiconductor device, including the integrated circuit capable of handling large electrical power and the integrated circuit for processing signals having small current.
Consequently, the power processing circuit cannot exhibit its ability, so that the reliability of the semiconductor device is reduced.