1. Field of the Invention
The invention relates to a semiconductor memory having a multiplicity of memory cells.
2. Description of the Related Art
Nonvolatile semiconductor memory elements are known in a multiplicity of different embodiments. By way of example, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memories, and also SONOS memories are used depending on the application. They differ in particular in terms of erasure option, programmability and programming time, retention time, storage density, and also their fabrication costs. A low fabrication price associated with a minimum of further options has the highest priority for a multiplicity of applications. It would be desirable, in particular, to have available a particularly inexpensive memory element which is electrically programmable at least once at the lowest possible voltages of less than 10 V, having a retention time in the region of about 10 years, and is compatible with present-day complementary metal-oxide semiconductor (CMOS) technology with the least possible changes.
A known nonvolatile semiconductor memory which is compatible with present-day CMOS technology is described, for example, in the European patent application having the application number EP 02 004 568.8. In this application, each memory cell of the semiconductor memory has a planar transistor (planar MOSFET), and a trapping layer is provided in a cutout of the (control) gate section. Hot electrons that can be generated in the transistor channel as a result of suitable potential conditions at the transistor terminals can overcome the thin gate oxide layer and be trapped by the trapping layer. The presence of the electrons trapped in the trapping layer brings about a shift in the characteristic curve of the transistor, which is manifested in particular by a different threshold voltage. The difference in the threshold voltage can be utilized in a known manner for writing a “bit,” since it can be determined by means of a read step.
What is disadvantageous, however, about this known memory concept is the limited scalability of the memory transistors, which makes it difficult to use this concept to fabricate high-density semiconductor memories. Consequently, the main area of application for these conventional memory transistors is in logic circuits or “system on chip” circuits (SOC circuits) with a low storage density.
A further memory transistor, which accords best of all with the requirements mentioned in the introduction, is a transistor fabricated according to the SONOS concept such as is described by Eitan et al. in “NROM: A novel localized trapping, 2-bit nonvolatile Memory Cell”, IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pages 543–545. However, this memory concept also has disadvantages with regard to its scalability, so that obtaining a high-density or highly compact arrangement of memory transistors with very small dimensions is difficult. The smallest cell areas that can be achieved in the case of such NROMs are typically 2F2 in the ideal case, where F represents the smallest feature size of the semiconductor memory. In practice, only 3F2 can be achieved on account of technology-dictated safety margins.
Therefore, there is a need for a semiconductor memory having a multiplicity of memory cells that permits a high-density cell arrangement in conjunction with simple fabrication.