Programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), are user-programmable integrated circuits that can be programmed to implement user-defined logic circuits. In a typical FPGA architecture, an array of configurable logic blocks (CLBs) and a programmable interconnect structure are surrounded by a ring of programmable input/output blocks (IOBs). Other FPGA architectures implement columns of IOBs, memory blocks and hard cores throughout the logic array. The programmable interconnect structure comprises interconnects and configuration memory cells. Each of the CLBs and the IOBs also includes configuration memory cells. The content of the configuration memory cells determines how the CLBs, the IOBs and the programmable interconnect structure are configured. Additional resources, such as multipliers, block random access memory (BRAM) and microprocessors are also included on an FPGA for use in user-defined circuits.
In order to realize a user-defined circuit, a configuration bitstream is loaded into the configuration memory cells such that the CLBs and IOBs are configured to implement particular circuit components used by the user-defined circuit. The configuration bitstream also programs the configuration memory cells of the programmable interconnect structure creating the desired connections between the various configured CLBs and IOBs.
The configuration bitstream is generally created through use of multiple electronic design tools. The processing of a design from the initial inception through creation of a configuration bitstream is often referred to as the “design flow.” A design flow generally begins with an architecture description that is defined by a hardware description language (HDL), such as Verilog, very-high-speed integrated circuit hardware description language (VHDL), or advanced Boolean equation language (ABEL). In addition to functional descriptions, the design description may include certain timing requirements. These timing requirements are often checked using a static timing analyzer (STA). Synthesis tools convert the HDL design into a gate-level representation that can be mapped to a specific-device, such as a field-programmable gate array (FPGA). Logic delays can be estimated for the representative gates. However, interconnection delays may be difficult to determine because the routing between logic has not yet been determined. A placement tool places the gate-level representation into prefabricated locations on the PLD. A routing tool allocates routing resources between these locations. Such allocation is represented by a fully placed and routed netlist.
Static timing analysis (STA) is often performed on the netlist to identify timing constraints. STA is the process of analyzing the temporal relationships of a circuit. One method of implementing STA involves the use of directed graphs to represent various nodes and their connections. Expected signal propagation timings are represented by the directed graphs and used to compare against timing requirements or to identify worst case paths. A problem with synthesis optimizations is that changes may be required in the topology of the input netlist and the circuit. Such changes may invalidate any previous graph representations and require regeneration of the timing topology and timing state of the graph. Further problems with synthesis optimizations relate to the efficiency of the optimization. Exhaustive optimization techniques that analyze large circuits all at once may not scale well with different design/circuit sizes and may require complicated algorithms and multiple passes by place and route modules.
The present invention may address one or more of the above issues.