A capacitor C coupled between the input and output terminals of an amplifier with a voltage gain of −Av experiences a net voltage across its terminals of Vin*(1+Av). This multiplicative effect means that the effective capacitance seen looking into the input terminal is C*(1+Av), which is a well understood example of the “Miller effect.” Field Effect Transistors or FETS inherently include a certain amount of parasitic drain-to-gate capacitance, which exhibits the Miller effect when FETs are used, for example, as inverting voltage amplifiers.
The Miller effect is a well-understood phenomenon and is exploited in the design of audio amplifiers and other electronic circuits, such as for limiting amplifier bandwidth and enhancing stability. Load-switching circuits represent an example scenario where the Miller effect is used to control voltage slew rates. In a representative configuration, an FET or other transistor is configured as a high-side or low-side switch that switches current through a load. Miller effect compensation is sometimes used in such circuits to limit the voltage slew rates associated with switching the transistor on and off.
However, it is recognized herein that such circuit arrangements leave unaddressed certain practical issues. For example, Miller compensation is not traditionally used to control the current slew rates of a load-switching transistor circuit, e.g., for reducing Electro-Magnetic Interference or EMI, and particularly not in a manner that is substantially independent of the associated load voltages. Moreover, it s recognized herein that traditional approaches for implementing the switching circuitry used for power transistor switching do not consider the problems arising from asymmetrical positioning of the switching control voltages with respect to the turn-on threshold of the switching transistor.