As feature sizes of semiconductor technology continues to shrink, the need arises to design high voltage IO interfaces by using the low voltage devices. The use of low voltage devices at high voltage results in over-voltage stress across the device terminals. The over-voltage stress across the device terminals results in reliability issues (degradation) like Hot Carrier Injection (HCI), Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) degradation in the devices over time. To reduce the reliability degradation on such devices, design techniques are being used to reduce the over-voltage stress across the device terminals. The cascode technique is one of the most common techniques used to design the 2×VDD (VDDE) voltage level IO buffer by using VDD voltage level devices, in which the VDD level reference voltage (REFH and REFL) derived from VDDE supply is used as biasing voltage for the cascoded devices. In such architectures the Vds stress (measured as the voltage difference between the drain and source terminals of the transistor) across the cascoded devices become very high during the transition, which leads to a very high HCI degradation in these cascoded devices. Therefore, to ensure the proper operation of devices over the time, the Vds stress across the cascoded devices must be minimized.
There is a pulse based approach proposed in the prior art (U.S. Pat. No. 8,044,684) to reduce the Vds stress across the cascoded devices during the transition. However, in that approach ensuring the pulse width and synchronizing it with the output transition time becomes very complex, especially across the different PVT corners. Therefore the pulse based technique reduces the Vds stress up to some extent, but not completely.
FIG. 1 shows a block diagram of a reference based output buffer 100 for high voltage applications showing the output pre-driver circuit 102, the output driver circuit 104, and the reference voltage generator 106. Also shown are the PD0 and ND0 signals, the REFH and REFL voltages, and the 10 signal.
FIG. 2 shows a conventional architecture of a cascoded output driver circuit 200, including cascoded transistors MP2, MP1, MN1, and MN2 coupled between the VDDE power supply and the GNDE ground connection. The two switching signals and reference voltages, as well as the output signal previously referred to with FIG. 1 are also shown.
FIG. 3 shows a gate pulse based architecture of a cascoded output driver circuit 300, including transistors MP2, MP1, MN1, and MN2 coupled between the VDDE power supply and the GNDE ground connection. In addition to the previously reference PD0 and ND0 switching signals, the REFL and REFH voltages are shown as pulsed, and provided by the gate pulse generator 302, which in turn receives a plurality of control signals.
Therefore, a need remains for a relatively simple buffer circuit that addresses the Vds stress issue described above.