The present invention relates generally to semiconductor devices and more particularly to methods for implanting and activating dopants in transistor drain extensions in the manufacture of semiconductor products.
MOS transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for fabricating MOS devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products. At the same time, many new applications have created a need to operate transistors and other semiconductor devices at lower power and voltage levels. Thus, whereas previous MOSFET devices were designed to operate at voltages of 5 or more volts, newer applications may require such devices to operate from DC supplies of around 3 volts or less. In addition, switching speed requirements of MOS transistors continue to increase in order to facilitate faster and improved product performance. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which occupy less physical space, consume less power, and operate at higher switching speeds and at lower voltages.
MOS transistors include a conductive gate overlying a channel region of the substrate with a thin gate dielectric, typically oxide, therebetween. Source and drain regions of the substrate (sometimes referred to as junction regions) are doped with impurities on opposite sides of the channel, wherein the source/drain regions of NMOS devices are doped with n-type impurities (e.g., As, Sb, P, etc.) and PMOS devices are doped using p-type impurities (e.g., B, Ga, In, etc.). The length of the gate structure overlying the channel is typically referred to as the physical channel length. The source and drain dopants are typically implanted into the silicon substrate using ion implantation systems, wherein the dosage and energy of the implanted ions may be varied depending upon the desired dopant concentration, depth, and profile. The ion dosage generally controls the concentration of implanted ions for a given semiconductor material, and the energy level of the beam ions determines the distance of penetration or depth of the implanted ions (e.g., the junction depth).
Following implantation, the dopant atoms in the source/drain regions occupy interstitial positions in the substrate lattice, and the dopant atoms must be transferred to substitutional sites to become electrically active. This process is sometimes referred to as xe2x80x9cactivationxe2x80x9d, and is accomplished by high temperature annealing in an inert ambient such as argon. The activation anneal process also causes diffusion of implanted dopant species downward and laterally in the substrate, wherein the effective channel length becomes less than the physical channel length. As device sizes continue to shrink, the physical and effective channel lengths continue to be scaled downward, wherein short channel effects become significant.
In addition to short channel effects, hot carrier effects are also experienced in short channel devices. For example, during saturation operation of a MOS transistor, electric fields are established near the lateral junction of the drain and channel regions. This field causes channel electrons to gain kinetic energy and become xe2x80x9chotxe2x80x9d. Some of these hot electrons traveling to the drain are injected into the thin gate dielectric proximate the drain junction. The injected hot carriers, in turn, often lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability.
To combat channel hot carrier effects, drain extension regions are commonly formed in the substrate, which are variously referred to as double diffused drains (DDD), lightly doped drains (LDD), and moderately doped drains (MDD). These drain extension regions absorb some of the potential into the drain and away from the drain/channel interface, thereby reducing channel hot carriers and the adverse performance degradation associated therewith. Referring to FIG. 1, a conventional transistor fabrication process 2 is illustrated beginning at 4, wherein isolation structures are formed in a substrate at 6, and a gate oxide (e.g., gate dielectric) is formed at 8. At 10, a layer of polysilicon is deposited over the gate oxide, and is then patterned at 12 to form a polysilicon gate structure.
An LDD implant is performed at 14, wherein drain extension regions are implanted using As. Typically, the LDD implant at 14 is a fairly low concentration dopant implantation process, which uses the edge of the patterned gate structure as an implantation mask. Where As is used, a cap oxide layer is then formed over the substrate and gate structure at 16, which prevents As from diffusing outward from the silicon substrate during subsequent annealing. Spacers are then formed at 18 along the sidewalls of the gate structure, and a second implantation (e.g., sometimes called a xe2x80x9csource/drain implantxe2x80x9d) is performed at 20 using a higher dopant concentration and implantation energy to form the source/drain junction regions.
An activation anneal is then performed at about 1050 degrees C. at 22 to activate the implanted As in the drain extensions and the source/drain regions, and also to cause diffusion or migration of As downward and laterally in the silicon. Thus, drain extension regions and source/drain regions are provided, which partially overlap one another in the substrate. Typically, the drain extension regions extend downward to a somewhat shallow depth and laterally to or under the gate structure, whereas the deeper source/drain regions are laterally spaced from the gate (e.g., by about the sidewall spacer width). The gate and source/drain regions are then silicided at 24 and back-end interconnect processing is performed at 26 before the method 2 ends at 28.
As a result of the two implantations at 14 and 20, a dopant gradient is established across the junction from the source/drain region of the junction to the drain extension region adjacent the channel, sometimes referred to as a graded junction. The drain extension region operates to assume a substantial portion of the entire voltage drop associated with saturation operation at the drain junction, while the more heavily doped source/drain region forms a low resistivity region suitable for enhanced contact conductivity. Further, the source/drain dose is implanted at a higher energy to produce deeper source/drain junctions and thereby to provide better protection against junction spiking.
Recently, lightly doped drain extensions have given way to moderately doped and highly doped drain extensions, wherein the drain extension depths are becoming smaller (e.g., shallower). The recent trend is toward shallower junctions with lower sheet resistance, wherein reducing sheet resistance facilitates higher drive currents (e.g., improved threshold voltage transistor performance), and faster switching times. Shallower junctions reduce short channel effects, facilitating continuing efforts at scaling MOS transistors to smaller and smaller dimensions, both lateral and vertical scaling. The amount of dopant activation in the drain extensions plays an important role in determining the sheet resistance thereof, wherein increasing the dopant activation (e.g., lowering the sheet resistance) serves to lower parasitic resistance within the source to drain path. Thus, there is a need for fabrication techniques for MOS type transistors, by which improved drain extension dopant activation can be facilitated in the manufacture of semiconductor devices.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to methods for MOS transistor fabrication, by which improved drain extension dopant activation may be achieved in both NMOS and PMOS type devices.
In one aspect of the invention, a first dopant species of a first type is implanted into a drain extension region of the substrate adjacent the channel via a first implantation process. As used hereinafter, the term drain extension includes extension regions associated with transistor drains as well as those associated with transistor sources. The implanted first dopant species is activated using a first anneal process. A second dopant species of the same type (e.g., n-type or p-type) is implanted into the drain extension region after the first anneal process using a second implantation process. The second dopant is then activated using a second anneal process. In one NMOS implementation illustrated and described below, the first and second dopants are different species of the same type, such as As (arsenic) and Sb (antimony) or P (phosphorus). PMOS implementations are also possible, for example, wherein the first dopant is B (boron) or BF2 (boron difluoride) and the second dopant is In (indium).
In the NMOS example, the first anneal process can be carried out at about 1050 degrees C. to activate the As dopants, and the subsequent second activation anneal process is done at about 950 degrees C. to activate the implanted Sb dopants. The implantation of two different dopant species of the same type, along with separate activation anneal processes has been found to facilitate fabrication of ultra-shallow super active drain extension junctions, by which sheet resistances of about 270 ohms/square have been achieved at junction depths of about 200-250 xc3x85. This aspect of the invention has thus been found to provide significant improvement in reducing sheet resistance compared with prior methods, such as illustrated in FIG. 1 above. The first and second anneal processes, moreover, may advantageously provide active first and second dopant species throughout substantially all of the drain extension region adjacent the channel region.
The formation of the source/drain regions may be integrated into this process, for example, wherein gate sidewall spacers are formed before the first anneal process, and a source/drain implant process is performed (e.g., As) using the sidewall spacers as an implantation mask. In this case, the first anneal process may be employed to concurrently activate the dopants in the source/drain regions as well as the first dopant species in the drain extension regions, and the sidewall spacers are removed before the second drain extension implant. In another implementation, the sidewall spacers are formed, the source/drain implant is performed, and the sidewall spacers are removed prior to implanting the first dopant species in the drain extensions. In this implementation, the first anneal process may again be employed to concurrently activate the dopants in the source/drain regions and the drain extension regions, after which the second drain extension implant and the second activation anneal are performed. Other alternate implementations are possible, for example, wherein a separate activation anneal is performed for the source/drain region dopants.
In another aspect of the invention, a method is provided for fabricating a MOS transistor in a wafer, comprising implanting a first dopant species into a drain extension region, and implanting a second dopant species of the same type into the drain extension region, wherein the first and second dopant species are different. The method further comprises separately activating the implanted first and second dopant species in the drain extension region, such as by performing first and second activation anneal operations, one of which is done prior to implanting the second dopant species. Yet another aspect of the invention provides active first and second dopant species throughout substantially all of the drain extension region adjacent the channel region. In still another aspect, the active first and second dopant species are of similar concentrations in the drain extension region.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.