Integrated circuits are electrical circuits that arrange transistors, resistors, capacitors, and other components on a single semiconductor die or substrate, upon which the various components are interconnected to perform a variety of functions. Typical examples of integrated circuits include, for example, microprocessors, programmable-logic devices (PLDs), electrically-erasable-programmable-read-only memory devices (EEPROMs), random-access-memory (RAM) devices, operational amplifiers, voltage regulators, etc.
Often, circuit designs are simulated by computer to verify functionality and timing to ensure that performance goals will be satisfied. Design and circuit analysis procedures are often performed using electronic-computer-aided design (E-CAD) tools. The design and subsequent simulation of a printed circuit, a very large scale integration (VLSI) circuit, or other electrical devices via E-CAD tools allows a product design to be confirmed, and often eliminates the need for building a prototype. Thus, E-CAD tools may enable a VLSI circuit manufacturer to bypass costly and time consuming prototype construction and performance verification stages in the product development process.
A VLSI circuit design can be represented at different levels of abstraction using a hardware description language. Some hardware description languages support circuit description at a register-transfer level, as well as at a logic level. At any abstraction level, a circuit design may be specified using behavioral or structural descriptions, or a combination of both. A behavioral description is often specified using Boolean functions. A structural description may include a list describing the various connections in a network of primitive or higher-level cells. Such a list is often called a “netlist.” The netlist may be used by logic synthesizers, circuit simulators, and other circuit design optimization tools to model the circuit. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip-flops. A register is an example of a higher-level (i.e., a non-primitive) cell.
A number of known systems use information provided in netlists to evaluate circuit timing and other related parameters. Although the operational specifics vary from system to system, such systems generally operate by identifying certain critical timing paths, modeling the conductors and the various cells defining each critical timing path using a resistor-capacitor (RC) network, and then evaluating the circuit to determine whether timing violations occur for signals required to traverse each of the critical paths. Static-timing tools, which are a specific type of optimization tool, are used to confirm that received input signals will arrive in time for the receiving block to process the signals, and confirm that block output signals will reach their designated destination circuits before the next clock cycle. Static-timing tools are designed with a focus on cell to cell (e.g., register to register) travel time estimates.
Unfortunately, this cell to cell approach is not well suited to convey useful and accurate timing information in the early design stages of a VLSI circuit design. First, VLSI circuits are commonly designed by circuit design teams. Each circuit designer, or a team of circuit designers, is assigned to create the circuits that will be used in one or more functional areas or blocks across the die that will contain the entire circuit. In the final product, each of the separately designed functional blocks must function correctly over time while receiving input signals and sending output signals across functional block interfaces. This functional block by functional block design approach can lead to circuit timing flaws that may not be identified until the functional blocks are integrated.
In addition, these block level interface-timing problems worsen as clock signal frequency increases. As the clock signal frequency increases, the corresponding shorter clock cycles increase the relative impact of signal transfer delays between an interface of a functional block and the various circuit components (e.g., registers) contained within respective blocks. Thus, static-timing tools designed with the intention of confirming a circuit design are not well suited to generate timing information that can be communicated to the designers of each of the functional blocks before they finalize the details of their assigned block circuit designs. Moreover, static-timing tools do not provide a mechanism to convey block level to block level timing information for a hierarchically arranged integrated circuit.
In addition to the above mentioned shortcomings of conventional static-timing tools, increases in integrated circuit density and complexity have led to an increase in memory requirements and test run times. Early test cases designed to simulate the operation and signal-timing verification of the latest generation of integrated circuits can require many days or weeks to perform a static-timing analysis over the entire integrated circuit.
Techniques and methods adopted in an attempt to reduce the memory requirements and run times to perform static-timing tests for integrated circuit designs rely on the tester's knowledge of both integrated circuit design and the static-timing process. Moreover, these techniques and methods require a great deal of manual intervention, resulting in techniques and methods that are error prone and time consuming.
In light of competitive pressures to design functional VLSI circuits with confidence that functional blocks will operate as desired over time, while reducing the design life cycle and development costs, there is a need for a system and method that addresses these and/or other shortcomings of the prior art, while providing a functional VLSI circuit design.