1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor wafer having a multiple layered structure, and a semiconductor device manufactured using the same. In particular, it relates to a semiconductor device having the multiple layered structure that is a silicon on insulator (SOI) structure.
2. Description of Related Art
At present, lower power consumption and longer operation hours of portable information terminal devices in the semiconductor industry are demanded on the market. Above all, it is one of the most important tasks to reduce power consumption of semiconductor devices that compose portable information terminal devices. In recent years, the silicon on insulator (SOI) technique has been developed as a technique to lower the power consumption of semiconductor devices. According to this technique, a silicon oxide layer, that is a dielectric film, is embedded in a conductive silicon substrate wafer, thereby reducing leak current from a semiconductor device to the substrate and reducing parasitic capacitance of MOS transistors, to achieve a lower power consumption in a semiconductor device.
Methods for providing SOI wafers may be generally divided in two methods. One of them is an oxygen implantation method, which is called a SIMOX (Separation by Implanted Oxygen) method, and the other one is a lamination method in which two wafers are laminated by intermolecular force. As a result of recent research, both of the methods have been improved to a level where their quality does not affect the device characteristics. However, there are still problems yet to be resolved. In particular, in view of mass-production, the oxygen implantation method needs oxygen ions to be implanted in large quantities and for a long time, which leads to a problem of long processing hours for each wafer. On the other hand, the lamination method is superior because embedded dielectric films are formed by thermal oxidation, such that the processing time can be shortened compared to the oxygen implantation method. However, the following complex processes are required after lamination. One of them is a process that requires a separation step by hydrogen ion implantation and an etching-polishing step. Another is a process that requires steps of providing a porous layer with a reduced mechanical strength in the laminated wafer, and conducting separation by applying water pressure.
A process of conducting separation by application of water pressure is described below with reference to FIG. 4. A porous silicon layer 10, a single crystal silicon layer 3 and a silicon oxide film (embedded dielectric film) 2 are provided on the side of a silicon substrate (support substrate) 11, which is laminated with a silicon substrate 1. As pure water is shot with high pressure against the porous silicon layer 10 from the side surfaces of the multiple layered wafer structure, the porous silicon layer 10 with a low mechanical strength is destroyed, such that a silicon on insulator structure 8 is separated from the silicon substrate (support substrate) 11.
This process requires a method for forming the porous silicon layer 10 that is mechanically weak on the support substrate 11 and the single crystal silicon layer 3 with good control, and a technique that converges water pressure on the thin porous silicon layer 10, which requires many complex mechanical devices. Also, at the time of separation with water pressure, since a uniform stress needs to be applied to the entire wafer, water pressure needs to be applied while the wafer is slowly rotated, which leads to a longer processing time for each wafer. The high level control, complex machinery, longer processing time increase the cost of each SOI wafer.