1. Field of the Invention
The invention relates to semiconductor integrated circuits and more particularly to a spiral inductor device.
2. Description of the Related Art
Many digital and analog elements and circuits have been successfully applied to semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit includes a silicon substrate. One or more dielectric layers are disposed on the substrate, and one or more metal layers are disposed in the dielectric layers or thereon. The metal layers may be employed to form on-chip elements, such as on-chip inductors, by current semiconductor technologies.
Conventionally, an on-chip inductor is formed over a semiconductor substrate and employed in integrated circuits designed for the radio frequency (RF) band. FIGS. 1A and 1B illustrate a plan view of a conventional on-chip inductor device with a planar spiral configuration and a cross-section along 1B-1B′ line shown in FIG. 1A, respectively. The on-chip inductor device is formed on an insulating layer 102 on a substrate 100, comprising a spiral conductive trace 103 and an interconnect structure. The spiral conductive trace 103 is disposed on the insulating layer 102. The interconnect structure includes conductive plugs 105 and 109 and a conductive layer 107 embedded in the insulating layer 102 and a signal output/input conductive trace 111 on the insulating layer 102. An internal circuit of the chip or an external circuit may provides a current passing through the coil, which includes the spiral conductive trace 103, the conductive plugs 105 and 109, the conductive layer 107, and the signal output/input conductive trace 111. A principle advantage of the planar spiral inductor device is the increased level of circuit integration due to the reduced number off-chip circuit elements and the complex interconnections required thereby. Moreover, the planar spiral inductor can reduce parasitic effect induced by the bond pads or bond wires between on-chip and off-chip circuits.
For a spiral inductor device, the quality factor (Q value) or inductor performance is reduced due to the conductor loss produced by the spiral conductive trace, the parasitic capacitor between the spiral conductive trace and the semiconductor substrate, and the substrate loss produced by the coupling between the spiral conductive trace and the semiconductor substrate. To reduce the conductor loss, increase of the thickness and the width of the spiral conductive trace have been proposed. Additionally, to reduce substrate loss, the use of a grounding metal shielding layer, interposed between the spiral conductive trace and the semiconductor substrate, has been proposed. Although the metal shielding layer can reduce the coupling between the spiral conductive trace and the semiconductor substrate, an additional parasitic capacitor is formed between the metal shielding layer and the semiconductor substrate so as to increase the parasitic capacitance between the spiral conductive trace and the semiconductor substrate.
Since the performance of integrated circuit devices is based on the Q value of the inductor devices, there is a need to develop an inductor device with increased Q value.