1. Field of the Invention
The present invention relates to a semiconductor memory devices
2. Description of the Related Art
In accompaniment with the advancement of a semiconductor technique, semiconductor memory devices have been installed in various electronic equipments. In particular, the demand for a nonvolatile semiconductor memory device has been increased year by year. As the nonvolatile semiconductor memory device that is currently generally spread, EEPROM, a Flash Memory registered trademark) and the like are exemplified. FIG. 1 is a sectional view showing the configuration of a typical nonvolatile semiconductor memory device. With reference to FIG. 1, a memory cell 121 is provided with a substrate 122, a floating gate 126 and a control gate 125. Also, as shown in FIG. 1, a source diffusion region 123 and a drain diffusion region 124 are formed in the substrate 122. In an operation of the nonvolatile semiconductor memory device, a gate voltage Vg to be applied to the control gate 125, a source voltage Vs to be applied to the source diffusion region 123, and a drain voltage Vd to be applied to the drain diffusion region 124 are changed for each of the plurality of memory cells 121 to control the charge amount in the floating gate 126. A charge (hot electron) amount stored in the floating gate 126 of the memory cell 121 is changed to vary a threshold or a memory cell transistor. In short, the memory cell transistor in which hot electrons have been injected into the floating gate 126 has a high operation threshold, and the memory cell transistor in which the hot electrons are not injected has a low operation threshold. In the nonvolatile semiconductor memory device, each of the thresholds of the plurality of memory cell transistors is controlled to store a data.
FIG. 2 is a circuit diagram showing the configuration of a memory cell array in a NOR type flash memory 100 as the conventional nonvolatile semiconductor memory device. Referring to FIG. 2, the NOR type flash memory 100 is provided with memory cells 121 arranged in a matrix, a power supply wiring line 101 for supplying power to each of the memory cells 121, a plurality of word lines WO to Wn 102 formed in a row direction, and a plurality of digit lines D0 to Dn 103 formed in a column direction, As shown in FIG. 2, the power supply line 101 supplies a common power supply voltage to the respective memory cells 121. In read, write and erasure of the data in the NOR type flash memory 100, a word voltage is selectively supplied to one of the word lines W0 to Wn and also a digit voltage is selectively supplied to one of the digit lines D0 to Dm.
In the above circuit configuration, the power supply line 101 is arranged between the two of the memory cells 121 in the conventional NOR type flash memory 100 to supply the common power supply voltage to the respective memory cells 121. FIG. 3 is a diagram showing a layout pattern of the memory array in the conventional NOR type flash memory 100, and the layout pattern corresponds to the circuit configuration shown in FIG. 2. As shown in FIG. 3, a power supply line pattern 201 and a group of digit line patterns 203 are formed to extend in a column direction. A group of word line patterns 202 is formed in a layer different from the group of digit line patterns 203 to extend in a row direction. The power supply line pattern 201 is connected through contacts 216 to a diffusion region 215 as the above-mentioned source diffusion region 123. The digit line patterns 203 are connected through contacts 214 to the diffusion region 215 as the above-mentioned drain diffusion region 124. The word line patterns 202 function as the control gates 125 to supply the word voltage to the control gates 125 of the memory cells 121.
FIG. 4 is a circuit diagram when the layout pattern shown in FIG. 3 is represented by circuit symbols. Here, the circuit shown in FIG. 4 is equivalent to the circuit shown in FIG. 2. With reference to FIG. 4, the plurality of memory cells 121 are arranged to oppose to each other with respect to a corresponding one of the plurality of source lines 217 extending in the row direction. Also, each of the plurality of source lines 217 is connected through the contact 216 to the power supply line pattern 201.
FIG. 5 is a circuit diagram showing a relationship between the groups of digit line patterns 203 and the power supply line patterns 201 in the above layout. As shown in FIG. 5, one of the power supply line patterns 201 in the NOR type flash memory 100 is arranged for each of the groups of digit line patterns 203 extending in the column direction. The power supply voltage is supplied through the source lines 217 extending in the row direction to each of the plurality of memory cells 121. The power supply line patterns 201 and the source lines 217 are arranged in a lattice manner, and the contacts 216 are positioned at intersections between the power supply line patterns 201 and the source lines 217.
FIG. 6 is an expanded diagram showing a predetermined region in FIG. 5. With reference to FIG. 6, the conventional NOR type flash memory 100 contains the contact 216 for connecting the source line 217 and the power supply line pattern 201, and the contact 214 for connecting the diffusion region and the digit line pattern 203. The contacts 214 contained in the group of digit line patterns 203 are arranged on lines extending in the row direction. The contacts 216 are arranged on lines which do not overlap the above lines, Also, the power supply line pattern 201 is located in an upper layer than a wiring layer for the word line patterns 202. Thus, in order to prevent intersection of the word line patterns 202 and the contacts 216 and to suppress the increase in the circuit area in the column direction, the word line pattern 202 is obliquely bent in the vicinity of the contacts 216. Consequently, in the conventional NOR type flash memory 100, the interval between the contact and the control gate is secured.
FIGS. 7A and 7B are sectional views showing the section structure of the NOR type flash memory 100 in the Layout pattern of FIG. 6. FIG. 7A shows the section structure of the flash memory 100 along the line A-A′ in FIG. 6, and FIG. 7B shows the section structure of the flash memory 100 along B-B′ in FIG. 6. Referring to FIG. 7A, the memory cell 121 has the source line (diffusion region) 217, the digit line (diffusion region) 219, a floating gate 218 and the control gate as the word line pattern 202, As shown in FIG. 7A, the digit voltage is applied from the digit line pattern 203 to the digit line (diffusion region) 219 through the contact 214. Also, the power supply voltage is applied from the power supply line pattern 201 to the source line (diffusion region) 217 through the contact 216.
In the NOR type flash memory, in order to supply the power supply voltage to each memory cell 121, the contacts 216 are arranged on the source lines 217. This contact 216 connects the power supply line pattern 201 in the upper layer than the word line pattern 202 and the diffusion region for the source line 217 in the substrate. Thus, in order to prevent any intersection between the word line pastern 202 and the contact 216, an interval of a certain length or more is required to be secure in the column direction. Also, the control gates are arranged in a predetermined interval, in an area where the contacts 216 are not formed.
As mentioned above, in the conventional NOR type flash memory 100, reduction of the chip area in the column direction is achieved by bending the word line pattern 202 obliquely. In this case, in the conventional NOR type flash memory 100, the width of the power supply line pattern 201 in the row direction is made wider than the width of the digit line pattern 203.
A technique for preventing the word line pattern 202 from being bent so that the increase in the chip area can be suppressed is known in Japanese Laid Open Patent Application (JP-A-Heisei 6-151782). FIG. 8 is a diagram showing a layout pattern of a NOR type flash memory 200 with the above technique employed. Referring to FIG. 8, the NOR type flash memory 200 is provided with the group of digit line patterns 203 extending in the column direction, and the power supply line pattern 201 extending in parallel to the digit line patterns 203. The NOR type flash memory 200 contains the plurality of contacts 214. Through the plurality of contacts 214, the digit line patterns 203 and the drain diffusion regions 124 are connected. The contacts 214 are arranged on a line extending in the row direction. Also, the NOR type flash memory 100 contains the contacts 216. Through the contact 216, the power supply line pattern 201 and the source diffusion regions 123 are connected. The contacts 216 are arranged on the above line on which the contacts 214 are arranged.
FIGS. 9A and 9B are sectional views showing the section structures of the NOR type flash memory 200 shown in FIG. 8. FIG. 9A shows the section of the flash memory 200 along the line C-C′ in FIG. 8, and FIG. 9B shows the section of the flash memory 200 along the line D-D′ shown in FIG. 8.
In order to form the contact 216 and the contact 214 on the same line, an N+ diffusion region 300 is formed below the word line patterns 202 before the word line patterns 202 are formed. Then, through the contact 216, the power supply line pattern 201 and the N+ diffusion region 300 are connected. Consequently, the contact 216 can be arranged on the same line as the contacts 214. As shown in FIG. 9B, the application of the power supply voltage to the source line 217 is carried out through the N+ diffusion region 300.
In the present memory cell array as shown in FIG. 6, the word line patterns 202 are obliquely bent in the neighborhood of the contact 216 to reduce the chip area in the column direction. At this time, as mentioned above, the interval between the word line pattern 202 and the contact 216 needs to be set to a certain length or more. In order to secure the interval, the width of the power supply line pattern 201 is set to be thicker than the width of the digit line pattern 203 in the structure of the current memory cell array.
If the power supply line pattern 201 is set to the same width as the digit line pattern 203, it is necessary to bend the word line pattern 202 on the digit line patterns 203 adjacent to the contact 216. Also, it is difficult to prevent contact of the word line pattern 202 with the contact 214. Also, if the word line pattern 202 is not bent, the chip area in the column direction of the memory cell array becomes extremely large.
If a reticle having the line patterns whose widths are different is used, there is a case that an optical diffraction is caused so that variation in the width of a diffusion region is generated between the digit line pattern close to the power supply line and the digit line away from it. The variation in the width of a diffusion region causes the variation even in the memory cell characteristics, such as a write time, an erasure time, a threshold in reading, and a breakdown voltage, between the memory cell 121 on the digit line close to the power supply line pattern 201 and the memory cell 121 on the digit line away from the power supply line pattern 201. Finally, there is a case that the performance of the entire memory cell array is reduced.
For this reason, when the present memory cell array is configured, an optical correction for adjusting the width of each digit line on a mask in advance is carried out in order to uniformly form the respective digit lines. However, even if this optical correction is carried out, there is a case that the optical diffraction causes the variation of the cell characteristics. Also, since the power supply line pattern is wide, the chip area of the memory cell array in the row direction is also increased.
Also, when an accurate pattern is carved on a wafer surface, DOF (Depth of Focus) at a time of exposure is preferred to be a certain depth or more. At present, an exposing method having a high resolution is used in association with the fine semiconductor process. In the exposure of the high resolution that is typically used in the current semiconductor manufacture, the DOF becomes deep if a pattern density is high. However, in case of a low density, there is a case that the DOF becomes shallow. With reference to FIG. 6, when the pattern density of the digit voltage supply contact 214 and the pattern density of the power supply voltage supply contact 216 are compared, the density of the pattern where the power supply voltage supply contact 216 is contained is indicated to be lower. Thus, in order to form the contacts 216 in the low density so as to be effective, the contact 216 needs to have the margin of a certain value or more and to cope with the DOF of the shallow depth.
In the technique shown in FIG. 8, as mentioned above, impurity is implanted below the word line pattern 202 in advance to from the N+ diffusion region 300. The contact 216 which is formed on the same line as the contact 214 can connect the power supply line pattern 201 and the N+ diffusion region 300. In other words, in the technique shown in FIG. 8, the power supply voltage is applied through the N+ diffusion region 300 to the source line 217. However, the impurity is implanted below the word line pattern 202 by using a mask before the formation of the word line pattern 202 to form the N+ diffusion region 300. When the N+ diffusion region 300 is formed, the impurity needs to be implanted below the word line pattern 202. However, the impurity must not be implanted into the adjacent digit line diffusion regions. For this reason, the mask to form the source diffusion regions needs to have a margin of a certain value or more. Thus, in the technique shown in FIG. 8, it is difficult to reduce the chip area between the source line diffusion region and the digit line diffusion region.