A selectively doped heterostructure transistor, SDHT, (also known as a MODFET for modulation doped FET, a TEGFET for two-dimensional electron gas FET, or a HEMT for high electron mobility transistor, and will be referred to generically, for purposes here, as a heterojunction field-effect transistor, or HFET) has superior performance compared to conventional (non-heterojunction) metalsemiconductor FETs (MESFET) in bandwidth and noise figure, etc. For example, see U.S. Pat. No. 4,163,237 by Dingle et al. and assigned to the same assignee as this invention. One drawback to using HFETs is the difficulty in the formation thereof in integrated form with consistent device characteristics across a wafer, even across a single chip. For example, the threshold voltage of HFETs can vary so much in a single chip that logic circuits built using HFETs do not operate reliably, reducing the yield of operable circuits from a wafer.
A simple process for the manufacture of HFETs in compound semiconductor integrated circuits has been a goal of many manufacturers to increase the yield and produce high performance, low cost ICs. One such process is described in U.S. Pat. No. 4,194,935 and assigned to the assignee of this invention. However, no provision is made for manufacturing both depletion and enhancement types of HFETs.
Another HFET manufacturing process is described in U.S. Pat. No. 4,615,102. Here, both enhancement and depletion HFETs are provided for but the threshold voltages of the HFETs are very difficult to make uniform, particularly the threshold voltage of the enhancement HFETs. Further, the resulting structure is very uneven, making metalization difficult and unreliable where the metal thins out over sharp changes in topography.