This invention relates to a connection structure between an integrated circuit chip and a wiring substrate and, more particularly, to a chip connection structure suitable for use in high-density, high-performance and low-cost packaging.
Conventional technologies for connecting an integrated circuit chip to a wiring substrate are disclosed in, for example, "Multichip Module Technologies and Alternatives: The Basics", New York, Van Nostrand Reinhold, pp. 56-66, 302-303, 1993.
Wire bonding (WB), Tape Automated Bonding (TAB), Flip Chip Solder Bump (FCSB), and High Density Interconnections (HDI) are widely known as representative chip connection technologies.
WB is a technology used for connecting an integrated circuit to a wiring substrate using a metal wire. This technology is the oldest and has been most widely used. According to above-mentioned references, for instance, a bonding pad 711 laid along the periphery of a chip 710 is connected to a bonding pad 713 of a substrate 714 by a wire 712, as shown in FIG. 7A.
TAB is a technology for connecting a chip to a substrate using a TAB tape. As shown in FIG. 7B, an inner lead 723 of a TAB tape 724 is connected to a bump 722 formed on an I/O pad 721 along the periphery of a chip 720. An outer lead 725 of the tape 724 is connected to an I/O pad 727 of a substrate 726. TAB makes it possible to connect a chip on smaller pitches and to provide a larger number of pins, compared with WB. The tape automated bonding is the second most popular technology, after WB.
FCSB is a technology for connecting a chip to a substrate using a spherical solder bump. As shown in FIG. 7C, a chip 730 is mounted on a substrate 734 with its circuit side facing down. An I/O pad 731 of the chip 730 and an I/O pad of the substrate 734 are connected together by a solder bump 732. FCSB can implement area array layout as well as layout along the periphery of the chip 730. Compared with TAB, FCSB is used for high-speed chip connection with a larger number of pins.
HDI is a technology for laminating a thin film wiring on the surface of a chip and the substrate. As shown in FIG. 7D, a chip 740 is mounted inside a cavity 749 formed in a substrate 748. Insulating films 742 and 744 are laid on top of the other on the surface of the chip 740 and the substrate 748, and via-holes 746, 747 and wires 743, 745 are formed in turn. An I/O pad 741 of the chip 740 and wires 743, 745 are connected together by the via-holes 746, 747. HDI is used for high-speed chip connection on smaller pitches.
There is a strong demand for improved cost-performance and downsizing in many processors, from a high-speed computer to a portable terminal equipment. Particularly in the case of memory, a lot of packing area is occupied by substrates and cards which form hardware. The realization of a smaller and less expensive memory module having a larger capacity is a very important problem facing designers. Further, in the field of an IC card and personal equipment, a reduction in thickness as well as in size is demanded.
Associated with these demands, an improved packaging density, improved electrical and mechanical performance, and reduced costs for facilities and packaging are more required. There is a tendency for microprocessor chips and memory chips such as, dynamic random access memory, and static random access memory to be increased in speed, size and the number of pins. It is required to address the previously mentioned problems based on this tendency.
As mentioned in detail in the above listed literature, the conventional chip connection technologies have both merits and demerits with respect to the above described problems. They may solve one problem but are not suitable for solving the other problem. In this way, the conventional solutions to the problems are in a trade-off relationship with each other.
Of the prior art technologies, WB and TAB are disadvantageous with respect to packaging density, that is, they require a larger packaging area compared with the packaging area needed by FCSB and HDI. As shown in FIG. 7, a bonding area for a wire 712 is additionally needed in the surrounding of a chip 710 in addition to a footprint of the chip itself. TAB requires a tape area 724 between an inner lead 723 and an outer lead 725, and a bonding area for an outer lead 725, as shown in FIG. 7B. TAB usually requires a larger packaging area than the packaging area of WB.
To increase packaging density in a thicknesswise direction, attempts have been made to reduce the thickness of a chip itself by chemical etching or mechanical polishing. However, WB requires a predetermined thickness for bending a wire (the wire 712 shown in FIG. 7A), and FCSB also requires a predetermined thickness for a solder bump (a bump 732 shown in FIG. 7C). Therefore, these two technologies are not suitable for reducing the thickness of the package.
Compared with FCSB and HDI wherein a chip and a wiring substrate are two-dimensionally connected together along the surface of the chip, WB and TAB have a limit to the number of connections because the chip and the wiring substrate are connected together along the periphery of the chip. In consideration of the large packaging area, WB and TAB are disadvantageous in view of a connection density.
Compared with FCSB and HDI, WB and TAB are not suitable for high-speed signal transmission with regard to electrical performance. In the case of WB and TAB, the length of a connection between pads of a chip and pads of a substrate becomes longer, as can be seen from FIGS. 7A and 7B, whereby resistance and inductance become larger. If short TAB or two-layer TAB is used in lieu of conventional single-layer TAB, better performance will be obtained. However, it may require a higher cost.
FCSB requires careful design compared with the other technologies with respect to mechanical performance, particularly, reliability against thermal stress and external stress. In the case of WB and TAB, it is possible for the wire 712 and the tape 724, shown in FIGS. 7A and 7B, to absorb stress. In the case of FCSB, stress concentrates on solder bumps 732, shown in FIG. 7C, and particularly on the bumps arranged along the outer periphery of the chip. In the worst case, the bumps may fracture. To reinforce the bumps, a space between bumps is filled with resin, which incurs extra process cost.
WB is most inexpensive in view of cost. On the other hand, TAB, FCSB, and HDI are expensive with respect to costs for facilities and connection process. A facility for TAB which performs connection on small pitches is very expensive. Infrastructure, such as chips or facilities, for FCSB is not yet established, and the automation of FCSB is not as well implemented as with WB and TAB. TAB and FCSB require a process for forming bumps on a chip or a substrate, and hence a chip requires special design. TAB further incurs the cost for producing a tape. HDI needs a laborious process for laying films 742, 744 and wires 743, 745, on top of the other, on the surfaces of the chip and the substrate, as shown in FIG. 7D. Reworking of HDI is very difficult and complicated, and therefore HDI is the most expensive among the conventional technologies.
The conventional representative chip connection technologies have been described above. The conventional technologies have their own merits, and variations on the conventional technologies are also conceivable. However, none of them provides a totally satisfactory solution to our challenges.