The present invention relates generally to signal coupling circuits, and in particular to a wide bandwidth signal coupling circuit having a variable DC voltage-level shift from input to output. Electronic signal-processing circuits are typically grouped in stages which are coupled together in such a manner that each stage may perform its intended operation without influencing or being influenced by the remaining stages, and without degrading signal fidelity. A very commonly encountered problem in connecting these stages together is that at the appropriate points of connection the signals or logic levels may have quiescent or average values which are other than zero volts.
A typical method of coupling circuit stages together is by coupling capacitors or transformers; however, these methods are not practical if DC information is to be preserved. In situations in which DC information is needed, Zener diodes or even batteries are sometimes used to provide a fixed DC level shift. However, these devices introduce an uncertain resistance value in series with the input signal path, resulting in difficulties in impedance matching. Moreover, the inherent capacitance of these devices serves to limit the frequency bandwidth of signals being transmitted therethrough.
Another method of signal coupling is the use of a resistive divider; however, the problem associated with such dividers is that the signal is attenuated and perhaps limited in signal bandwidth. In a case in which the resistive divider is part of a passive attenuator probe, other problems become apparent. Consider, for example, the loading effects on a logic family such as emitter-coupled logic (ECL). ECL logic is most commonly operated from a -5.2-volt supply with V.sub.cc connected to ground. In this configuration, the high signal level is approximately -0.8 volts and the low signal level is approximately -1.7 volts. The output of a typical ECL gate is the emitter of an NPN emitter follower transistor, the collector of which is connected to ground. The output is pulled down to a negative supply (usually about -2 volts) with an external pull-down resistor (usually 50 to 100 ohms). Since speed is a major consideration in ECL designs, the interconnections between logic gates are often transmission lines, and the pull-down resistor doubles as a line termination. If a conventional 500-ohm, 10.times. passive probe were used in conjunction with an oscilloscope to examine an ECL output, the probe's 500-ohm resistance to ground would form a voltage divider with the output termination resistor of the particular logic gate being examined. This divider can cause severe distortion of the output signal level, shift the DC operating point of the output transistor of the logic gate, and greatly reduce the gate's noise margin.