1. Field of the Invention
The present invention relates to a method for manufacturing a vertical MOS transistor.
2. Description of the Related Art
With the miniaturization of semiconductor devices in recent years, the current driving ability of a MOS transistor making up a semiconductor device tends to decrease. In order to improve this current driving ability, a vertical MOS transistor of a three-dimensional structure in which the source region, the channel region, and the drain region are vertically located is proposed. This vertical MOS transistor has the advantage that a significant improvement in current driving ability can be achieved by completely depleting the channel region.
A related vertical MOS transistor comprises a Si pillar that forms source/drain regions and a channel region, as shown in FIG. 2 of U.S. Patent Application Publication No. 2004/262681, and this channel region is surrounded by a gate insulating film and a gate electrode.
Also, this vertical MOS transistor is used in various areas, making use of its advantage. As an example of its use, an example in which a vertical MOS transistor is used as the memory cell transistor of a DRAM is proposed in FIG. 8 of U.S. Pat. No. 6,818,937. In this structure, a capacitor is provided on an impurity diffusion layer on a channel region making up a three-dimensional transistor, and a bit line is located under an impurity diffusion layer under the channel region. Also, the channel region is surrounded by a gate electrode (a word line) via a gate insulating film.
A vertical MOS transistor as described in U.S. Patent Application Publication No. 2004/262681 has the advantage that the current driving ability can be improved, but has the problem that the junction leak increases due to GIDL (Gate Induced Drain Leakage).
Also, when a DRAM cell transistor is formed using a vertical MOS transistor, and for example, with the source/drain regions being of N-type and the channel region being of P-type, a capacitor is formed under the lower N-type impurity diffusion layer, the junction leak increases in the depletion layer of the junction portion formed by the N-type impurity diffusion layer and p-type Si due to GIDL. Also, a DRAM cell transistor in U.S. Pat. No. 6,818,937 has the problem that the junction leak increases in the depletion layer of the junction portion formed by the impurity diffusion layer and the channel region due to GIDL.
In other words, the present inventor has discovered that when vertical MOS transistors are used, problems occur in any case, for example, the charge stored in the capacitor leaks due to junction leak current due to GIDL.