1. Field of the Invention
The invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter with a decreased number of comparators and a pipeline analog-to-digital converter with a decreased number of comparators.
2. Description of the Related Art
In portable digital multimedia consumer electronic systems, analog-to-digital converters (referred to as ADCs) with high speed and low power consumption are required to process analog signals. Pipeline ADCs are ADCs with pipeline structures which can achieve high speed and high precision. The pipeline ADCs have sampling rates reaching dozens of trillions of sampled points per second; even reaching hundreds of trillions of sampled points per second. That is, the sampling rates are dozens of MS/s; even hundreds of MS/s. This characteristic is advantageous for pipeline ADCs, so pipeline ADCs are commonly used in consumer electronic systems.
FIG. 1A is a schematic view showing a conventional pipeline ADC. As shown in FIG. 1A, a pipeline ADC has a multi-stage pipeline circuit structure. The second pipeline circuit stage is given as an example for illustration (refer to the portion surrounded by a dotted line in FIG. 1A). The second pipeline circuit stage comprises a sample-and-hold (referred to as S/H) circuit, a sub ADC circuit, a sub digital-to-analog converter (referred to as sub DAC) circuit, a subtracter circuit, and a residue amplifier circuit. The sub ADC circuit is used to quantify an analog-signal input quantity Vin, perform an analog-to-digital conversion to the quantification result, and output a digital quantity (that is a binary digital signal) corresponding to the analog-signal input quantity Vin. The sub DAC circuit processes the digital quantity output from the sub ADC circuit and outputs an analog-signal quantity. The subtracter circuit performs a subtraction operation to the analog-signal input quantity Vin and the analog-signal quantity output from the sub DAC. Then, the coarse an amplifying operation performed by the residue amplifier circuit, a residue signal Vout of the analog-signal input quantity Vin is obtained. The residue signal Vout serves as the analog-signal input quantity of the next pipeline circuit stage and is processed by the next pipeline circuit stage. In each pipeline circuit stage, the S/H circuit, the sub DAC circuit, the subtracter circuit, and the residue amplifier circuit are generally called a multiplying digital-to-analog converter (referred to as an MDAC).
FIG. 1B is a schematic view showing a 3.5-bit MDAC and a sub ADC circuit in a conventional pipeline ADC. FIG. 1C shows input/output characteristics of the circuit in FIG. 1B. As shown in FIGS. 1B and 1C, for the pipeline ADC circuit with the 3.5-bit precision, the sub ADC circuit 10 comprises fourteen capacitors 101 which are coupled in parallel. Comparison voltages (sampling voltages) at input terminals of the respective comparators 10 are Vr1˜Vr14, respectively. That is, there fourteen levels for the sampling voltages. The input/output characteristics of the sub ADC circuit 10 is shown in FIG. 1C, wherein Vr1 is equal to − 13/16Vr, and Vr14 is equal to 13/16Vr. In the conventional pipeline ADC, the number of comparators in the sub ADC circuit is equal to fourteen. The total number of comparators is large. Thus, the comparators occupy a large area of the entire circuit, and the power consumption of the pipeline ADC is thus high.
As the above described, the number of comparators in the sub ADC circuit of the conventional pipeline ADC is large, such that the comparators occupy a large area of the entire circuit, and the power consumption of the pipeline ADC is high. Moreover, with the enhancement of the precision level of the pipeline ADC, the number of comparators in the pipeline ADC is increased. Thus, the total size of the pipeline ADC becomes larger, and the power consumption thereof becomes higher.