Gate Driver on Array (GOA) technique is a kind of process technique for integrating Gate Driver ICs directly on an array substrate to replace external driver ICs. Application of such technique may not only reduce a manufacturing process procedure and thus a product cost and increase an integration, but also may accomplish a design with two symmetric sides of a panel and omit a bonding area and a fan-out wiring space for the gate ICs, such that a narrow frame design may be achieved, thus increasing productivity and yield rate.
FIG. 1 is a schematic diagram of GOA for bi-side parity alternate driving circuit of a display apparatus which includes two sets of cascaded shift registers on the left and on the right respectively, FIG. 2 shows the controlling timing sequence signals for operation of the shift register, FIG. 3 shows a circuit design of the shift register, wherein a pulling-down control signal may be connected to a direct current signal source or an alternating current signal source. The two sets of cascaded shift registers on the left and on the right respectively have a same operational principle, taking the circuit on the left (that is, the circuit for odd rows) in FIG. 1 as an example, an output of a previous odd row is connected to an input terminal (INPUT) of a current odd row shift register, and an output of a next odd row is connected to a reset terminal (RESET) of the current odd row shift register. The basic operational principle is as follows: when a signal at the INPUT terminal is at a high level, a first transistor M1 is turned on to charge a node PU; when a clock control signal (it is a first clock control signal CLK1 for a first row, a fifth row, a ninth row and so on, and it is a third clock control signal CLK3 for a third row, a seventh row, an eleventh row and so on) is at a high level, a third transistor M3 is turned on and the OUTPUT terminal outputs a pulse of a high level, meanwhile the bootstrapping function of a capacitor C1 may further pull up the voltage at the node PU; then the RESET terminal is at a high level, a second transistor M2 and a fourth transistor M4 are turned on to discharge the node PU and the OUTPUT terminal; then the node PD is controlled to be charged by a pulling-down control signal, such that the node PU and the OUTPUT terminal are discharged, thus ensuring that noise is pulled down in a non-operational time of the current row.
When a direct current signal is selected as the pulling down control signal, the node PU can be charged constantly, thus ensuring that noises at the node PU and the OUTPUT terminal may be pulled down immediately once they occur. Nevertheless, there is a problem that a Thin Film Transistor (TFT) in a pulling down unit for controlling the node PD is always in an operational state in which the duty cycle is nearly 100%, such that a lifespan of the TFT may be reduced largely and a long-term reliability and stability of the GOA circuit will be affected severely. When an alternating current signal (usually a clock control signal) is selected as the pulling down control signal, the lifespan of the TFT in the pulling down unit may be effectively increased; however, since the node PD is controlled by the alternating current signal, there is a low level state at the node PD, and at this time, the noises at the node PU and the OUTPUT terminal cannot be pulled down in time once they occur due to the low level of the node PD, such that abnormality is prone to appear in display, especially in a high temperature the higher noise is output.