1. Field of the Invention
The present invention relates to the field of mass storage of data. More particularly, the present invention relates to a non-volatile solid-state mass storage device.
2. Discussion of the Related Art
In electronics, the term mass storage refers to the storage of large amounts of data in a persisting way, even in absence of a power supply. The storage media used for mass storage applications may be divided in three broad classes: magnetic mass storage devices, such as hard disks, floppy disks, drum memories and magnetic tapes; optical mass storage devices, such as compact disks, Digital Versatile Disks (DVDs) and magneto-optical discs; and solid-state mass storage devices, such as Electrically Programmable Memories (EPROM), NOR/NAND flash memories and ovonic memories.
In order to make a comparison of the various mass storage devices, it may be useful to examine their most important features, such as the storing capacity, the data transfer speed and the access time.
More particularly, the greater the storing capacity, the better the mass storage device. However, the cost of a mass storage device significantly depends on said feature, together with the technology used for implementing the device. Magnetic mass storage devices are nowadays those featuring the highest storage capacity, followed by optical mass storage devices and then, last in the rank, by solid-state mass storage devices.
However, magnetic and optical mass storage devices have the great disadvantage of exhibiting a long access time. In fact, referring for example to a hard disk, during a program operation in which data have to be stored in addressed memory locations, data are actually written into said locations after a relatively long access time, e.g., of the order of 10 milliseconds, during which the magnetic read/write head of the hard disk moves for reaching the position on the track corresponding to the addressed memory locations. On the other hand, solid-state mass storage devices have very low, practically null, access times with respect to the other classes.
At the present time the class of mass storage devices featuring the highest data transfer speed (both in program and in read) is that of the magnetic mass storage devices. Modern hard disks, once their magnetic read/write head has been correctly positioned (as discussed above, the time required to bring the read/write head to the addressed memory locations is the access time), are capable to store data with a rate of 20 Mbits per second. On the contrary, the data transfer speeds of the solid-state mass storage devices are lower. For example, modern four-level NAND flash memories typically have program speeds of 2 Mbits per second, while two-level (also referred to as binary) NAND flash memories typically have program speeds of 10 Mbits per second.
As known to those skilled in the art, the data transfer speed of a NAND flash memory, and in particular its program speed, depends on several factors, like: the number of levels to which each memory cell can be programmed, the width of the memory cells' threshold voltage distributions corresponding to the various levels, the duration and the number of program voltage pulses used during the program operation for programming the memory cells.
Since the program operation for a NAND flash memory consists in repeatedly performing the actions of applying a program voltage pulse to the addressed memory cells and then verifying the program state reached by such memory cells after the program pulse voltage application, the highest the number of program voltage pulses, the longer the time required for programming. Consequently, in order to have a program speed that is sufficiently high, it should be necessary to reduce the number of program voltage pulses necessary to bring the memory cells to the target program states.
However, the minimum allowed number of program voltage pulses significantly depends on the number of the program levels, i.e., on the number of the threshold distributions and on their width.
To be able to finely adjust the memory cells' threshold voltage, the increment of the program voltage pulses has to be sufficiently low (and, consequently, the number of pulses necessary for bringing the memory cells to the target program states has to be sufficiently high). This constraint is more severe the higher the number of program levels, i.e. the number of threshold voltage distributions within a certain threshold voltage range of values (wider threshold voltage distributions make it difficult to discriminate the program level; for example, an ideal threshold voltage distribution of a four-level NAND flash memory should have a width of about 150 mV).
For the above reasons, in order to correctly program a multilevel NAND flash memory, more program voltage pulses are needed than in the case of a binary NAND flash memory: consequently, the program speed of a binary NAND flash memory is higher than that of a multilevel NAND flash memory.
Back Pattern Dependency (BPD) and Floating Gate Coupling (FGC) are known effects which cause the widening of the threshold voltage distributions.
In order to describe how the BPD affects the width of the threshold voltage distributions, attention has to be paid to the fact that the memory cells in a NAND flash memory are arranged according to strings of serially-connected memory cells between a drain select transistor, connected to the bit line, and a source select transistor, connected to a reference voltage distribution line; said strings are connected in parallel to each other. When all the memory cells belonging to a same string have to be programmed, usually the first memory cell subjected to programming is the cell connected to the source select transistor of the string, followed by the subsequent memory cells of the string proceeding towards the memory cell connected to the drain select transistor. Therefore, each memory cell of the string to be programmed is connected to the corresponding bit line by means of still non-programmed (i.e., erased) memory cells. With such a program method, the condition (by the resistance point of view) of each memory cell of the string during the program operations (i.e., when their program state is verified) is different than in the case in which all the memory cells of the string have already been programmed. In fact, while the source resistance (i.e., the resistance seen at the source electrode) of each cell to be programmed is the same both during the verify and after that all the memory cells of the string have been programmed, the drain resistance (i.e., the resistance seen at the drain electrode) usually changes. This is due to the fact that while the source resistance depends on the channel resistances of the memory cells that have already been programmed, the drain resistance depends on the channel resistances of the memory cells that probably will change their program states, being not programmed yet. In other words, when the memory cells are subjected to a read operation in order to retrieve their program states later on, said read operation is performed in conditions that may be different from the ones during the verify operations. This (program) pattern dependency increases the width of the threshold voltage distributions corresponding to the non-erased states by a non negligible amount (for example, equal to 50 mV).
Regarding the FGC effect, it is known that the floating gate of a generic memory cell is not totally shielded (from an electrical point of view) from the floating gates of the adjacent memory cells, being instead capacitively coupled thereto. Considering a generic memory cell in the memory cell array, it is surrounded by 8 other memory cells, two along the bit line direction, two along the word line direction and four along the two diagonal directions. As is known to those skilled in the art, the FGC effect depends significantly on the amount of variation in the threshold voltages that the adjacent memory cells experience during the program operations. For example, let us consider a multilevel memory, with memory cells Mc that are adapted to store 2 bits, and whose threshold voltages may be programmed to four different levels, denoted for simplicity as “A”, “B”, “C”, “D” (with A being associated with the erased state and D with the programmed state corresponding to the highest threshold voltage). If a memory cell is adjacent to memory cells that are subjected to program operations for bringing them to the last programmed state D, this memory cell heavily experiences the FCG effect. In fact, since the threshold voltages depend on the amount of electrical charge stored in the floating gates, a memory cell passing from the state A (i.e., corresponding to a condition in which the floating gate has a small amount of electrical charge stored therein) to the state D (i.e., corresponding to a condition in which the floating gate has a high amount of electrical charge stored therein) requires the transfer of a great amount of electrical charge, which in turn affects the threshold voltages of the adjacent floating gates, being capacitively coupled therewith. The higher the variation in the threshold voltages of the memory cells to be programmed, the higher the amount of electrical charge involved in the transfer and the higher the variation in the threshold voltages of the adjacent memory cells. As a consequence, said capacitive coupling between the floating gates of adjacent memory cells increases significantly the width of the threshold voltage distributions corresponding to the non-erased states. In particular, the disturbances on the considered memory cell induced by the programming of the eight adjacent cells may cause the width of the threshold voltage distribution to be increased by 400-500 mV.
In order to prevent that the undesired widening of the threshold voltage distribution impairs the memory operation (which would occur in case two threshold voltage distributions corresponding to two program states overlap), measures need to be taken to ensure that the threshold voltage distributions are narrow, carefully planning the width, the number and the time duration of the program voltage pulses to be applied to the memory cells. Unfortunately, the extent of the undesired effects described above is such as to cause the data transfer speed (during the program operations) of the NAND flash memories to be lower than the transfer speed of magnetic mass storage devices.
As a consequence, magnetic mass storage devices greatly predominate on the market over the other mass storage device classes in all the applications where great amounts of data have to be sequentially stored. In fact, in case a magnetic mass storage device (e.g., a hard disk) has a sufficiently large free space, the data to be sequentially stored can be written in adjacent memory locations; in this way, the positioning of the magnetic read/write head of the hard disk has to be performed only once, for the first memory location, and the high data transfer speed is fully exploited. However, when the amount of data to be stored is not so great, and when the frequency of the access to the storage device is relatively high, it is more advantageous to use solid-state mass storage devices.
Reassuming, apart in case the access to the stored data is very frequent, the most convenient storage media for mass storage applications at the present time are still the magnetic mass storage devices.
However, solid-state mass storage devices are more robust compared to the magnetic (and optical) counterparts, since-solid state devices do not include mechanical and movable parts (like the read/write heads, the spindle and the platters). The presence of such mechanical and movable parts, in addition to cause the devices to be more fragile, prevents the miniaturization thereof, since the sizes of the mechanical parts can not be scaled down in the same way as that of electronic components. Moreover, in order to be capable of moving the mechanical parts, magnetic (and optical) mass storage devices have to include motors, which need power supplies higher than those normally used for supplying electronic devices.
For all these reasons it would be strongly desirable to use solid-state mass storage devices for all mass storage applications. However, to this purpose, their data transfer speed should be increased significantly.