The term “transistor” is derived from “transfer-resistor”, which means “varying resistor” or “adjustable resistor”. In electronics, the transistor plays an unparalleled role. The bipolar junction transistor (BJT) varies the built-in resistor to regulate current. In digital logic electronics, the unipolar transistor maximizes the built-in resistor to turn off current or minimizes the built-in resistor to conduct current, such as JFET (Junction-Field-Effect-Transistor), MESFET (Metal-Semiconductor-Field-Effect-Transistor), and MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor). The ability, that control the adjustment of built-in resistor in transistor, is based on the forward bias or reverse bias that both arranged and selected initially of the built-in potential created by the PN junction within structures. In BJT consisting of an emitter, a base and a collector, the bias of the base controls the resistance value of the resistor. In FET consisting of a source(S), a gate(G) and a drain(D), the bias of the gate controls the conduction state of carriers (electrons or holes). In MOS developed afterward, a body(B) is added to FET to prevent from floating potential, and a four-electrode transistor is thus formed. The base or gate functions exactly like a faucet switching on/off water and regulating the flow rate of water.
In fabricating each electrode of the three-electrode or four-electrode transistor, a diffusion, deposition, ion-implanting or epitaxial process forms patterns of cuboids having width, length and depth. The junctions of the electrodes are parallel arranged top-down or from left to right. Thus, the configuration of transistor elements in IC appears like a mosaic pattern, as shown in FIG. 1A and FIG. 1B. FIG. 1A is a top view schematically showing a CMOS inverter, and FIG. 1B is a sectional view of the CMOS inverter shown in FIG. 1A.
In 1947, Shockley, Bardeen and Brattain of the Bell Laboratory invented the transistor, which is a point contact germanium junction transistor and was disclosed in a U.S. Pat. No. 2,569,347 “Circuit Element Utilizing Semiconductive Material” issued on Sep. 25, 1951. However, in early 1960s, the idea of integrating a plurality of transistors into a substrate to miniaturize the digital computer was regarded as an extremely ridiculous thought by the Bell Laboratory—the birthplace of transistors. From then on, microelectronics has advanced by leaps and bounds. From nowadays view, the “humor” of the Bell Laboratory seems to be the motive force of the researchers challenging the miss impossible.
The conventional BJT has advantages of fast response and high current density and extensively applies to analog circuits. In applications to the inverters of digital logic circuits, TTL (Transistor-Transistor Logic) circuits and ECL (Emitter-Coupled Logic) circuits, the conventional BJT is hard to parallel FET, which uses voltage of electric field to control the conduction state, in the integration. Limited by the electrode areas, the conventional BJT is harder to promote the integration. As BJT uses the base current to control the collector-emitter current, the base layer has to physically exist to function as the carrier exchange body no matter how thin it is. The gate of FET is moved to the upper space and uses voltage to control the conduction state of the source-drain current. Thus, FET outperforms BJT in IC integration. Among FETs, MOSFET (MOS for short) has further higher integration, further lower power consumption, further greater input impedance and further smaller input current and thus becomes the most popular element in digital logic circuits. The electron mobility of the N-channel MOS (NMOS for short) is much greater than the hole mobility of the P-channel MOS (PMOS for short). Under the conditions of identical dopant concentrations and identical width-length ratios of the gates, NMOS operates much faster than PMOS. After the appearance of the ion implant technology for a high N-type dopant concentration and a high-precision doping-profile control, NMOS has replaced PMOS.
Refer to FIG. 1A and FIG. 1B. A conventional PMOS 103 and a conventional NMOS 101 are cascaded to form a conventional CMOSFET (Complementary MOSFET, CMOS for short). Two gates of NMOS 101 and PMOS 103 are connected to form a signal input terminal 102 of the digital logic circuit. The cascaded drain and source is used as a signal output terminal 104. NMOS 101 and PMOS 103 are respectively connected to a high voltage level 105 VDD and a low voltage level 106 VSS—dual-state logic signals. When the common gate inputs a high voltage or a low voltage, one channel of NMOS 101 and PMOS 103 turns on, and the other channel turns off. In other words, whether the input signal is of a high voltage or a low voltage determines the output terminal of the CMOS. Theoretically, CMOS has none static power consumption. Only in the transient moment that PMOS and NMOS exchange the conduction states and turn on simultaneously, CMOS has dynamic power consumption. Since 1980s, CMOS has be used as the low-power consumption and fast-operation transistor structure for digital logic circuits and contributed much to the electronic industry. The conventional CMOS is formed via cascading NMOS and PMOS. No matter whether CMOS has a single well structure or a double well structure, CMOS intrinsically has a parasitic PNPN thyristor structure, which may generate a latch-up effect and make CMOS temporarily or eternally lose the voltage control function or even cause abrupt current increase and circuit burnout.
Refer to FIG. 2A and FIG. 2B for a latch-up state of an N-well CMOS inverter. FIG. 2A is a sectional view of an N-well CMOS. FIG. 2B is a diagram of an equivalent circuit of the CMOS shown in FIG. 2A. Q⊥ denotes a vertical parasitic PNP bipolar transistor, which is formed of a P+ source, an N-type well and a P-type substrate of PMOS. Q∥ is a horizontal parasitic NPN bipolar transistor, which is formed of an N+ source, a P-type substrate and an N-type well of NMOS. The collector of the horizontal NPN is connected to the base of the vertical PNP via the N-type well. The collector of the vertical PNP is connected to the base of the horizontal NPN via the P-type substrate. Then, the P-type substrate functions as the base (of NPN), the collector (of PNP), and the connection medium between the NPN base and the PNP collector; the N-type well functions as the base (of PNP), the collector (of NPN), and the connection medium between the PNP base and the NPN collector. Thus, the P-type substrate and the N-type well (functions like a substrate) become the repeated both collectors and bases (using the same carrier source), which are the origin of the latch-up phenomenon. The thorough solution to exterminate the latch-up phenomenon is to separate the N-type well from the P-type substrate. RW is the cascade resistor between the N-type well and the P+ source of PMOS and thus called the N-type well resistor. Rsub is the cascade resistor between the P-type substrate and the N+ drain of NMOS and is thus called the substrate resistor. At some instant, a voltage surge caused by turning on a power source, an ionization event or another transient state results in so high a current that flows through the NPN collector and causes the current flowing through the N-type well resistor to bias the base and emitter of the PNP bipolar transistor Q⊥, wherein the N-type well functions both the NPN collector and the PNP base and thus may have a conflict. If the bias is great enough to force the PNP collector to generate current, the current flowing through the substrate resistor Rsub will further bias the base and emitter of the NPN bipolar transistor Q∥. Then, Q∥ will amplify more current to the N-type well resistor RW and increase the bias of Q⊥. The repeated circulation generates a positive feedback, and the latch-up phenomenon will not stop unless the power source is removed.
The conventional approaches to avoid the latch-up phenomenon include: (1) increasing the distance between NMOS and PMOS, (2) increasing the dopant concentration of the base, (3) using an epitaxial layer in the substrate to increase the triggering bias voltage from the horizontal resistance, (4) shortening the distance between the contact of the source and the contact of the body (Butted Contact), (5) Trench Isolation, (6) using a guard ring to absorb the injected charges and prevent from the dual carrier operation, (7) using a SOI (Silicon On Insulation) technology, and (8) using a 3D stacked CMOS structure. The abovementioned approaches (1)-(6) can be interpreted as increasing RW and Rsub in FIG. 1B to prolong or avoid the advanced triggering of Q⊥ and further inhibit the triggering of Q∥. Though approaches (1)-(6) can improve the latch-up problem, they cannot thoroughly exterminate the latch-up phenomenon, especially when high integration is required. Further, they all reduce the circuit density (integration) and decrease the switching speed of the circuit. In approach (7), MOS is completely constructed on the insulation layer, and the thyristor structure is almost vanished and hard to generate coupling current. Approach (7) can indeed prevent from the latch-up phenomenon. However, PMOS and NMOS are arranged on a plane side-by-side, and the integration is thus hard to increase. In approach (8), a MOS is formed over another MOS, and an oxide layer interposes therebetween. Although approach (8) can successfully overcome the latch-up phenomenon, it still has to overcome the problems of aligning masks and forming silicon semiconductor crystals on an oxide layer in the fabrication of 3D CMOS.
In using the low power consumption CMOS, the increased integration results in a high element density and delays the switching speed, which is another problem needing attention in addition to the latch-up problem.