1. Field of the Invention
This invention relates to sign extension circuits and more particularly to a circuit employing an adder which can perform sign extension.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers, and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input output unit (I/O unit), the control unit, and the arithmetic logic unit (ALU).
The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of the signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed.
The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor. Essential components of an ALU may include circuitry for sign extending a m bit operand to an n bit operand. Sign extension is necessary for several reasons when processing operands. Most notably, sign extension is needed to prevent an overflow condition arising upon addition of two m bit signed operands. Sign extension is also needed in order to properly add operands of unequal length.
Upon sign extension, two operands along with a carry or borrow input, can be provided to an adder/subtractor circuit within the ALU without fear of an overflow condition arising. Addition or subtraction are two of the most commonly invoked operations during the execution of a computer program. The speed with which the adder/subtractor circuit can compute the sum or difference of two input operands is extremely important in determining the speed of the overall system. Indeed ALU speed is a critical feature in the design of microprocessors. A further critical design is the area occupied by the ALU within the microprocessor. ALU designers seek to reduce the size of the ALU while increasing the operating frequency thereof.
FIG. 1 shows select components of a prior art ALU including a pair of sign extension circuits 14a,b coupled to an adder/subtractor circuit 18. Each of the sign extension circuits 14a,b include a fanout circuit 20a,b coupled to a multiplexer 22a,b. The first sign extension circuit 14a is configured to receive a first input operand (a.sub.n:1) which can be a n bit operand or a m bit operand zero extended to n bits. The second sign extension circuit 16 is configured to receive a second input operand (b.sub.n:1) which can be a n bit operand or a m bit operand zero extended to n bits. The most significant (m+1)th bit in each of the zero extended input operands represents the sign bit of the m bit operands.
Each multiplexer 22a,b has a pair of multiple bit inputs, one of which is configured to receive the output of corresponding fanout circuit 20a,b, the other of which is configured to receive the corresponding input operand. Each multiplexer 22a,b also has an input coupled to a control node 24 which is configured to receive a first or second control signal. When the first control signal is provided to control node 24, multiplexer 22a,b operates to pass the output of fanout circuit 20a,b to adder/subtractor circuit 18, wherein the output of the fanout circuit represents the corresponding m bit operand sign extended to n bits. When control node 24 receives the second control signal, multiplexer 22a,b operates to pass the corresponding n bit operand to the adder/subtractor circuit 18.
Adder/subtractor circuit 18 includes a carry/borrow input node 26 and a carry/borrow output node 28. When adder/subtractor circuit 18 operates as an adder, adder/subtractor circuit adds the outputs provided by multiplexers 22a,b along with a carry input bit provided to carry/borrow input node 26, and generates a n bit result operand along with a carry output bit at carry/borrow output node 28. When adder/subtractor circuit 18 operates as a subtractor, adder/subtractor circuit subtracts the borrow input bit provided to carry/borrow input node 26 and the output provided by multplexer 22b from the output provided by multiplexer 22a, and generates a n bit result operand along with a borrow output bit at carry/borrow output node 28.
FIG. 2 shows a typical fanout circuit 20a used in the ALU of FIG. 1 to generate the m bit operand sign extended to n bits. Fanout circuit 20b is identical in structure. For purposes of illustration, FIG. 2 shows fanout circuit 20a configured to receive a four bit operand of a four bit operand zero extended to eight bits. The fanout circuit includes four inputs and eight outputs. In general, the four inputs are coupled to receive the four bit operand of the four bit operand zero extended to eight bits. The eight outputs generate the four bit operand sign extended to eight bits which, in turn, is provided to multiplexer 22a.
Fanout circuit 20a further includes a first set of buffers 30 (1)-30 (4) coupled to the four inputs, and a series of second buffers 32 coupled in series with buffer 30 (4). As can be seen, the four least significant bits outputted by the fanout circuit equate to the four bit operand provided to the fanout circuit. Further, each of the four most significant bits outputted by the fanout circuit equate to the sign bit of the four bit operand provided to the inputs. The series coupled buffers 32 are needed to drive the extra capacity on the four most significant outputs of the fanout circuit. However, one problem with fanout circuit 20 relates to signal propagation delay. More particularly, the five most significant bits of the output are generated after generation of the three least significant bits due to the added delay caused by series coupled buffers 32. Ultimately, this delay slows the operation of the ALU circuit shown in FIG. 1. Moreover, adding the series coupled buffers 32 adds to the silicon area size of fanout circuit 20.
It would be desirable to produce a faster ALU which can extend and/or add operands using less silicon surface area and without the propagation delay of the prior art.