The design of timing in digital circuits is an extremely difficult challenge. Conventional clocked digital design solves this problem by decomposing the circuit into cycle-free combinational logic (CL) stages and interstage clocked latches; the clock cycle is simply tuned to accommodate the worst-case propagation delay in the CL stages. The behavior of the combinational logic can then be specified and synthesized without considering timing. Speed Independent (SI) asynchronous circuits are analogous to clocked CL design because SI circuits are independent of time--the behavior will be correct for any arbitrary gate delay.
High-performance circuits, both clocked and asynchronous, benefit from more aggressive timing methodologies. Clocked circuits can treat time locally to allow adaptive and variable time in different parts of the circuit. Timed asynchronous and sequential circuits can have significantly enhanced performance, at the cost of lower robustness to delay variation.
Metric timing requires the specification of either propagation times or of ranges of propagation times. Unfortunately metric timing analysis can explode in complexity even when simple localized timing is used. The synthesis and verification of even moderate-sized timed circuits can therefore become intractable. Further, accurate metric ranges require layout parameters, which may not be present when a circuit is to be synthesized.
What is needed is a system and method of defining a circuit which frees the circuit from a dependence on propagation delays or on estimates of propagation delays while maintaining synthesis and verification of hazard-free designs.