Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memories. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. A typical floating gate memory cell is fabricated in an integrated circuit substrate and includes a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by a dielectric material, typically an oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is also typically made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is “floating” in dielectric so that it is insulated from both the channel and the control gate. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively. Other types of non-volatile memory include, but are not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), and Magnetoresistive Random Access Memory (MRAM).
Yet another type of non-volatile memory is a Flash memory. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate embedded in a MOS transistor. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed selectively by tunneling charges to the floating gate. The negative charge is typically removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their drains are connected to column bit lines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to word lines. However each memory cell is not directly connected to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each floating gate memory cell of the series connected string, restricted only by the memory cells of each string that are selected to be read. Thereby placing the current encoded stored data values of the row of selected memory cells on the column bit lines.
Two common programming techniques for NAND architecture Flash memories are the “boosted bitline” and the “boosted source line.” In these techniques a high voltage is applied to the gate of a selected floating gate transistor of a string, while the remaining transistors are turned on in a pass through mode, from either the connected bitline or from a source line connected to the opposite end of the chain of floating gate transistors.
A problem with programming NAND architecture Flash memories is that programming typically involves applying a high voltage to elements of the memory array; usually the bitline or the source line and/or their associated elements, depending on whether “boosted bitline” or “boosted source line” programming is used. This can require the usage of larger feature circuit elements or differing circuit designs in these portions of the memory array to be able to withstand the higher programming voltages. The use of larger featured circuit elements and/or more complex designs can cause design issues and/or force the manufacturer to utilize a larger integrated circuit chip die, increasing manufacturing costs and reducing the final integrated circuit chip die yield for a given process and process substrate wafer size, further increasing costs. Additionally, small variations in the circuit elements of the bitlines, source lines, and/or their associated circuit elements can lead to variations in the programming voltages applied to the individual floating gate memory cells. This can lead to problems with over/under programming and/or write fatigue of the selected memory cells and an increased likelihood of disturb problems in the unselected memory cells of the array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative circuits and methods of programming NAND architecture Flash memory arrays.