1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor read only memory (ROM) and a method of manufacture therefor. The present invention further provides a method of directly transforming CMOS-compatible single-poly one-time programming (OTP) memory into coded non-volatile memory without the need of re-designing the peripheral circuitry, thereby reducing product cost and chip development time.
2. Description of the Prior Art
Read-only memory (ROM) semiconductor integrated circuits are widely used as memory storage devices for digital electronic equipments, in particular, microprocessor-based computer systems, to almost permanently store predetermined programs. ROMs are made on special orders with the programming code being specified by the customers. In a conventional semiconductor ROM device, the channel region of a memory cell is selectively implanted with ions to adjust the threshold voltage thereof depending on whether the programmed memory cell is turned on or turned off to represent a logic xe2x80x9c1xe2x80x9d or a logic xe2x80x9c0xe2x80x9d in binary, respectively. In the case of mask ROM, the coding of the data bits onto the memory cell transistors is generally performed by implanting ions into the channel regions of the appropriate memory cell transistors, thereby adjusting their threshold voltages. This step of coding the data into the ROM array structure through ion implantation is performed using a code mask which permits the implantation of ions into only certain regions of the semiconductor.
A ROM array consists of a large number of memory cells. Each memory cell consists of a MOS transistor having a gate, a source and a drain. The gates are parts of polysilicon strips which are the X address lines or word lines for the array. Typically, the sources are part of an N+ diffused region which is connected to ground, source lines, or Vss, while the drains are part of N+ diffused regions which are Y output lines or bit lines. To reach a maximum memory packing density, most of the prior art ROM devices use the above-described one memory cell one MOS transistor structure. Nevertheless, in some applications, it needs that a ROM cell consists of two MOS transistors.
Typically, during the development phase of a system IC, there are several steps taken prior to that the firmware or program code is fixed. First, to facilitate the debugging procedure, an external flash memory is used to store the program code. After the hardware design is completed, single chip IC design will be implemented using embedded flash processes so that the program code can be stored in the embedded flash to facilitate the debugging. Thereafter, as all the hardware and software bugs are fixed, the embedded flash will be replaced with an embedded ROM, which is known as Flash-to-ROM conversion. However, it usually takes a lot of time to implement the Flash-to-ROM conversion since the different technologies between the flash memory and ROM. For example, the peripheral circuitry must be re-designed and the back-end process such as testing has to be revised. Consequently, the prior art Flash-to-ROM conversion is expensive and time-consuming.
It is therefore a primary objective of this invention to provide a dual-transistor ROM structure and a method of converting dual-transistor field programmable logic devices into embedded non-volatile memory coded with fixed program code.
It is a further objective of this invention to provide a fast FPLD-to-ROM conversion method. After the final software code is fixed and the addresses where the memory units to be coded are determined, the FPLD are transformed into a ROM by either changing the layout of a photo mask that is used to define polysilicon gates to cancel the pre-selected floating gates according to the fixed software code, or by ion implanting the pre-selected floating gate channel regions underneath those floating gates where the memory units are to be coded, but without the need of re-designing peripheral circuitry or changing logic processes.
According to the claimed invention, a CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data xe2x80x9c1xe2x80x9d or digital data xe2x80x9c0xe2x80x9d. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line. The second P+ source doping region and the second P+ drain doping region define a floating gate channel region under the floating gate. According to one preferred embodiment of the present invention, P+ type dopants such as boron are implanted into the floating gate channel region in advance (before the formation of the floating gate thereon) using an additional photomask, thereby turning the second single-poly PMOS transistor into a depletion mode transistor. According to another preferred embodiment of the present invention, the layout of a photo mask (or poly mask) that is used to define polysilicon gates including word lines and floating gates is changed to cancel the pre-selected floating gates according to a fixed software code. P+ type dopants such as boron are implanted into the floating gate channel region where the pre-selected floating gates are cancelled in the step of ion implanting source/drain regions of transistors.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.