1. Field
Example embodiments are directed to tape wiring substrates and packages including the same.
2. Description of the Related Art
Flat panel displays may include, for example, a liquid crystal display (“LCD”) for portable phones, a thin-film transistor liquid crystal display (“TFT LCD”) for computers and plasma display panels (“PDP”) for domestic use. A flat panel display may include a component part known in the art as a tape package. In some applications, the tape package may have fine pitch wiring patterns.
Tape packages may include a tape wiring substrate. The two principal types of tape packages may be a tape carrier package (“TCP”) and a chip on film (“COF”) package. The tape wiring substrate of a TCP may have a chip mounting window in which a semiconductor chip may be mounted via an inner lead bonding method (for example). The tape wiring substrate of a COF package may not include a chip mounting window.
The semiconductor chip may be flip chip bonded to the tape wiring substrate. As compared to the TCPs, the COF packages may allow a thinner tape wiring substrate and/or finer pitch wiring patterns.
In the COF packages, I/O terminal patterns may act as external connection terminals, instead of solder bumps. The I/O terminal patterns may be directly attached to a printed circuit board or a display panel.
FIG. 1 is a plan view of a conventional COF package 1100. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.
Referring to FIGS. 1 and 2, the COF package 1100 may include a tape wiring substrate 1120. A semiconductor chip 1110 may be flip chip bonded to the tape wiring substrate 1120. A molding compound 1140 may seal the flip chip bonded portion through an underfill process.
The semiconductor chip 1110 may have an active surface that may support electrode pads 1112. The electrode pads 1112 may be provided along the edge portions of the active surface. Electrode bumps 1116 may be provided on the electrode pads 1112. The electrode bumps 1116 may include input bumps 1117 and output bumps 1118, for example. The input bumps 1117 may include ground bumps 1117a and power bumps 1117b, for example.
The tape wiring substrate 1120 may include a base film 1121, and an upper metal layer 1124 provided on the upper surface 1122 of the base film 1121. The base film 1121 may have a chip mounting area confronting the semiconductor chip 1110. The chip mounting area may be located in the center portion of the base film 1121. The base film 1121 may include sprocket holes 1129. The sprocket holes 1129 may be arranged along the base film 1121 at predetermined or desired intervals. An end of the upper metal layer 1124 may be connected to the electrode bumps 1116. Another end of the upper metal layer 1124 may extend outwards from the chip mounting area. The upper metal layer 1124 may include input terminal patterns 1125 and output terminal patterns 1126. The input terminal patterns 1125 may include input terminal patterns for ground 1125a (“ground terminal patterns”) and input terminal patterns for power 25b (“power terminal patterns”). The input terminal patterns 1125 may extend to one side of the base film 1121 relative to the semiconductor chip 1110, and the output terminal patterns 1126 may extend to another side of the base film 1121 relative to the semiconductor chip 1110. The input and the output terminal patterns 1125 and 1126 may extend parallel to the arrangement of the sprocket holes 1129.
When the semiconductor chip 1110 is flip chip bonded to the tape wiring substrate 1120, the ground bumps 1117a may be bonded to the ground terminal patterns 1125a and the power bumps 1117b may be bonded to the power terminal patterns 1125b. 
Although conventional COF packages are generally thought to be acceptable, they are not without shortcomings. For example, to facilitate achievement of semiconductor products having lighter weight, smaller size, higher speed, multifunction and/or increased performance, the upper metal layer 1124 may have fine pitch wiring patterns, the semiconductor chip 1110 may be more miniaturized, and the number of electrode bumps 1116 may be increased. Accordingly, the ground terminal patterns 1125a and the power terminal patterns 1125b may be reduced in pitch. The ground and the power terminal patterns 1125a and 1125b provided on the upper surface 1122 of the base film 1121 may have insufficient areas for stable ground and/or power supply, for example.
The conventional COF package 1100 may insufficiently reduce electromagnetic waves and/or noise that may occur during operation of the semiconductor chip 1110, which may result in poor electromagnetic interference and/or noise characteristics. Further, the conventional COF package 1100 may unstably supply power to the semiconductor chip 1110.
FIG. 3 is a plan view of another conventional COF package 1200. FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3. FIG. 5A is a bottom view of the conventional COF package 1200. FIG. 5B is a bottom view of another conventional COF package 1300.
Referring to FIGS. 3 through 5B, the COF package 1200 may include a tape wiring substrate 1120 and semiconductor chip 1110. The tape wiring substrate 1120 may have a dual metal layer 1124 and 1131. The semiconductor chip 1110 may be flip chip bonded to the tape wiring substrate 1120. A molding compound 1140 may seal the flip chip bonded portion. The molding compound may be provided via an underfill process, for example.
The semiconductor chip 1110 may have an active surface with electrode pads 1112. The electrode pads 1112 may be provided along the periphery of the active surface. Electrode bumps 1116 may be provided on the electrode pads 1112. The electrode bumps 1116 may include input bumps 1117 and output bumps 1118, for example. The input bumps 1117 may include ground bumps 1117a and power bumps (not shown), for example. The input bumps 1117 may be larger in size and/or pitch than the output bumps 1118. This may reduce fault likelihood which may occur (for example) due to static electricity between the input bumps 1117. The semiconductor chip 1110 may include dummy bumps 1119. The dummy bumps 1119 may be provided at the corner regions of the active surface, for example. The dummy bumps 1119 may improve assembly stability and/or heat radiation, for example.
The tape wiring substrate 1120 may include a base film 1121. The base film 1121 may be fabricated from polyimide, for example. The base film 1121 may be fabricated from numerous other materials that are well known in this art. The dual metal layer 124 and 1131 may be fabricated from Cu foiled on the base film 1121, for example. The dual metal layers 1124 and 1131 may be fabricated from numerous materials (other than Cu) and using numerous techniques (other than foiling) that are well known in this art. The base film 1121 may have an upper surface 1122 including a chip mounting area, and a lower surface 1123 opposite to the upper surface 1122. The chip mounting area may be that portion of the upper surface 1122 that may confront the semiconductor chip 1110. That is, the semiconductor chip 1110 may be superposed above the chip mounting area of the upper surface 1122. Vias 1127 may penetrate the base film 1121. The dual metal layer 124 and 1131 may include an upper metal layer 1124 provided on the upper surface 122 of the base film 1121, and a lower metal layer 1131 provided on the lower surface 123 of the base film 1121.
The upper metal layer 1124 may be provided on the chip mounting area and may be connected to the electrode bumps 1116. The upper metal layer 1124 may extend outwards from the chip mounting area. The upper metal layer 1124 may include input terminal patterns 1125 and output terminal patterns 1126, for example. By way of example only, the input terminal patterns 1125 may extend to one side of the base film 1121 relative to the semiconductor chip 1110, and the output terminal patterns 1126 may extend to another side of the base film 1121 relative to the semiconductor chip 1110. The input terminal patterns 1125 may include ground terminal patterns 1125a connected to the ground bumps 1117a. 
The lower metal layer 1131 may be provided on a region of the lower surface 1123 corresponding to the chip mounting area. For example, the chip mounting area may be superposed above the lower metal layer 1131. The lower metal layer 1131 may include a ground layer 1132. The ground layer 1132 may be connected to the ground terminal patterns 1125a through the vias 1127. By way of example only, the ground layer 1132 may cover at least the chip mounting area. The ground layer 1132 may be fabricated from a plate or a mesh, for example. The ground layer 1132 may provide a sufficient ground area to reduce the dissipation of electromagnetic waves and/or noise that the semiconductor chip 1110 may emit, thereby improving the electrical stability.
The vias 1127 connecting the ground terminal patterns 1125a to the ground layer 1132 may reduce the need for separate wirings for connecting the ground terminal patterns 125a to the ground layer 1132, and/or reduce the ground route length.
The upper metal layer 1124 may be arranged on an outer peripheral region of the chip mounting area. The upper metal layer 1124 may not cover a central portion of the chip mounting area. The arrangement of the upper metal layer 1124 only on the peripheral region of the chip mounting area (and not on the central portion of the chip mounting area) may facilitate the flow of the molding compound 1140 during an underfill process and/or decrease the likelihood of void generation.
The ground layer 1132 may serve as a heat sink for radiating the heat which the semiconductor chip 1110 may emit, for example. The dummy bumps 1119 may be connected to the ground layer 1132 to improve heat radiation characteristics, for example. The dummy bumps 1119 may be connected to dummy terminal patterns 1128 through dummy vias 1134.
The ground layer 1132 may be of an integral, one-piece construction or the ground layer may be of a multi-piece construction. For example, referring to FIG. 5B, a COF package 1300 may include a tape wiring substrate 220 having a first ground layer 1232a and a second ground layer 1232b. First ground bumps 1217a′ may be connected to the first ground layer 1232a through first vias 1227a. Second ground bumps 1217a″ may be connected to the second ground layer 232b through second vias 1227a″. 
The multi-piece ground layer 1232 may be implemented when different voltages may be applied to a semiconductor chip 1210. For example, when the semiconductor chip 1210 has an analog circuit having an applied voltage of 5V and a digital circuit having an applied voltage of 1.5V, the ground layer may be separated into a ground layer for the analog circuit and a ground layer for the digital circuit.
The base film may have the ground layer only or the base film may have a ground layer and a power layer.