This invention relates in general to flat plasma display panels and in particular to a method and apparatus for resonant injection of discharge energy into a flat plasma display panel.
Flat plasma display panels, or gas discharge panels, are well known in the art and generally have a structure that includes a pair of substrates that are in a spaced relationship to define a gap therebetween. Ionized gas is sealed in the gap. Additionally, parallel column and row electrodes are deposited upon the surfaces of the substrates and coated with a dielectric material such as a glass material. The substrates are arranged with the electrodes in an orthogonal relation to one another to define points of intersection. The points of intersection in turn define discharge cells at which selective discharges may be established to provide a desired storage or display function.
It is also known to operate such panels with alternating voltages and particularly to provide a write voltage which exceeds the firing voltage at a given discharge point, as defined by a selected column and row electrode, to produce a discharge at a selected cell. The discharge at the selected cell can be continuously “sustained” by applying an alternating voltage. However, the alternating voltage by itself is insufficient to initiate a discharge. The technique relies upon wall charges generated upon the dielectric layers of the substrates which, in conjunction with the sustain voltage, operate to maintain discharges.
Details of the structure and operation of flat plasma display panels are set forth in U.S. Pat. No. 3,559,190 that issued on Jan. 26, 1971.
Referring now to FIG. 1, there is shown generally at 10, a schematic diagram for a known driver circuit 12 for providing a sustaining voltage to a flat Plasma Display Panel (PDP) 14. The PDP 14 is represented in FIG. 1 by a plurality of capacitors 15 and a panel inductor 16 enclosed within a dashed rectangle. The sustainer driver 12 for a TS PDP is required to make a 600-V transition with a 200-ns rise time. This has traditionally been done using a series-resonant network, split into two series-resonant sections, as shown in FIG. 3, with each series-resonant section driving one end of the sustainer capacitance of the PDP 14. As shown in FIG. 1, each series-resonant section is composed of an driver inductor 17 plus a series combination of a MOSFET (IRF740) 18 and a pn diode (MUR1540) 20. The left portion of the driver section 12 is connected through a driver capacitor 22 to ground while the right portion of the driver section 12 is connected between a power supply 24 and ground. A first driver diode 26 is connected between the input to the PDP 14 and the power supply 24 while a second driver diode 28 is connected between the input to the PDP 14 and ground.
The operation of the driver circuit 10 is illustrated in FIGS. 2 and 2A. The MOSFET's are sequentially switched between conducting and non-conducting states by a logic circuit (not shown). As the driver section 12 operates, charge flows through the driver inductance 17 and back and forth between the PDP 14 and driver capacitance 22. The combined inductors and capacitors of the driver section 12 and the PDP 14 form a resonant circuit. As shown in FIG. 2, a resonant transition is then expected to be a half-wave pulse of current, driving the sustainer capacitance of the PDP panel 14 through most of its voltage transition, which is then completed by the loose turn-on of clamping MOSFET's (IRFP360), which are also expected to carry the sustainer discharge current. The resonant loop on any given resonant transition therefore includes two IRF740's, 18, two MUR1540's, 20, two resonant inductors 16 and 17, and the sustainer capacitance 15, all in series. The bottom curve in FIGS. 2 and 2A represents the sustaining voltage applied to the PDP 14 while the middle curve represents the current flowing through the driver inductor 17 and the upper curve represents the current supplied by the clamp in the driver circuit. As shown in FIG. 2, the clamp occurs after the ramp up. This requires a fast voltage ramp up time in order to complete the sequence in the allocated time. Because of the fast voltage ramp up, ringing can occur, as also is apparent in FIG. 2. At time treturn, the driver operates in a similar manner to return the sustainer voltage to the original voltage level.
It has been found that the driver section 12 shown in FIG. 1 recovers about 90% of the energy normally lost in driving the panel capacitance 15. Accordingly, a PDP using the circuit shown in FIG. 1 can operate with only about 10% of the power required by earlier prior art PDP's. Further details of the sustainer driver circuit are included in U.S. Pat. No. 5,081,400 that issued on Jan. 14, 1992. A complete sustainer driver circuit is shown in FIG. 3, where both driver sections 12 and 26 are illustrated. Components shown in FIG. 3 that are similar to components shown in FIG. 1 have the same numerical identifiers. The driver section 12 on the left in FIG. 2 is operative to raise the sustaining voltage while the driver section 26 on the right in FIG. 3 is operative to return the sustaining voltage to the original level.
Further details of the structure and operation of the above described sustaining voltage supplies are set forth in U.S. Pat. No. 4,866,349 that issued on Sep. 12, 1989.
The prior art sustainer voltage driver circuits are complex and require a number of switching FET's. Accordingly, it would be desirable to provide a simpler driver circuit that would include less expensive components.