1. Field of the Invention
The present invention relates to a voltage regulator circuit for generating a supply voltage adopted in a semiconductor memory device, and more particularly to an improved voltage regulator circuit for a semiconductor memory device capable of separately controlling the operation of a voltage regulator circuit in accordance with an operational condition of a semiconductor memory device to generate an internal power source having stable voltage, while decreasing a stand-by current.
2. Description of the Prior Art
FIG. 1 illustrates a conventional voltage regulator circuit for a semiconductor memory device. The conventional voltage regulator circuit includes a first internal source voltage generator 1 for receiving a reference voltage Vref and for converting an external source voltage VCC to an internal source voltage VDD; and a second internal source voltage generator 2 for receiving the reference voltage Vref and a row address strobe signal RAS and for converting an external source voltage VCC to an internal source voltage VDD.
The external source voltage VCC denotes a source voltage being applied from an exterior of a semiconductor memory device, and the internal source voltage VDD denotes a source voltage being supplied to the semiconductor memory device by the voltage regulator circuit.
With reference to FIG. 2 detailing FIG. 1, the first internal source voltage generator 1 includes a first differential amplifier D1 for comparing the reference voltage Vref and the internal source voltage VDD, and a first PMOS transistor P1, the gate of which receives an output signal Es from the first differential amplifier D1, the source of which is connected to the external source voltage VCC, and the drain of which is connected to the internal source voltage VDD. The first differential amplifier D1 is connected to current source Istb.
The second internal source voltage generator 2 includes a second differential amplifier D2 for comparing the reference voltage Vref and the internal source voltage VDD, and a second PMOS transistor P2, the gate of which receives an output signal Ea of the second differential amplifier D2, the source of which is connected to the external source voltage VCC, and the drain of which is connected to the internal source voltage VDD. The second differential amplifier D2 is connected to current source fact which is controlled by the row address strobe signal RAS.
The operation of the above-described conventional voltage regulator device will now be separately described with reference to a stand-by state and an active state which are related to the logic level of the row address strobe RAS.
When the row address strobe RAS has a low level (i.e., stand-by state), the source current lact of the second internal source voltage generator 2 is turned off, causing the second differential amplifier D2 to become inactivated so that the second internal source voltage generator 2 is not driven. To the contrary, the first internal source voltage generator 1 is constantly driven by a source current Istb (not shown). That is, in a stand-by state, only the first internal source voltage generator 1 is operated.
In the stand-by state, when the internal source voltage VDD being applied through a non-inverting terminal of the first differential amplifier D1 in the first internal source voltage generator 1 is higher than the reference voltage Vref being applied through an inverting terminal of the first differential amplifier D1, the output voltage Es of the first differential amplifier D1 becomes heightened, and a gate-source voltage Vgs of the first PMOS transistor P1 becomes lowered. Therefore, the driving capacity of the first PMOS transistor P1 becomes deteriorated, thereby lowering the internal source voltage VDD. Also, when the internal source voltage VDD is lower than the reference voltage Vref, the output voltage Es of the first differential amplifier D1 becomes lower, causing the gate-source voltage Vgs of the first PMOS transistor P1 to increase consequently, the driving capability of the first PMOS transistor P1 and the external source voltage VDD are increased.
With repetition of such operation, the internal source voltage VDD becomes identical to the reference voltage Vref.
Accordingly, an active state denotes a state in which the second internal source generator 2 and the first internal source voltage generator 1 are concurrently operated. When the row address strobe RAS has a high level, the source current Iact of the second internal source voltage generator 2 is turned on and the second differential amplifier D2 is operated, causing the second internal source generator 2 to be operated.
In the active state, the operation of the first internal source voltage generator 1 becomes identical to that of the stand-by state, and the operation of the second internal source voltage generator 2 will now be described.
When internal source voltage VDD being applied to a non-inverting terminal of the second differential amplifier 2 in the second internal source voltage generator 2 is higher than the reference voltage Vref being applied to an inverting terminal of the second differential amplifier D2, the output voltage Ea of the second differential amplifier D2 becomes lower, causing the gate-source voltage Vgs of the second PMOS transistor P2 to become lower. Therefore, the driving capacity of the second PMOS transistor P2 becomes deteriorated, thereby lowering the internal source voltage VDD.
To the contrary, when the internal source voltage VDD is lower than the reference voltage Vref, the output voltage Ea of the second differential amplifier D2 decreases causing the gate-source voltage Vgs of the second PMOS transistor P2 to decrease. Consequently, the driving capacity of the second PMOS transistor P2 and the internal source voltage VDD increases.
With the repetition of the above-described operation, the second internal source voltage generator 2 causes the internal source voltage VDD to become identical to the reference voltage Vref during the active state.
The source current Istb of the first differential amplifier D1 is determined by considering characteristics of the first differential amplifier D1, such as driving capacity, response speed, and stand-by current. When a magnitude of the source current Istb is substantially small, the stand-by current is attenuated, and the driving capacity and response spaced of the first differential amplifier D1 become deteriorated. To the contrary, when the source current Istb is sufficiently large, the stand-by current becomes increased and the driving capacity and the response speed of the first differential amplifier D1.
However, in the above-described conventional voltage regulator circuit for a semiconductor memory device, a column address strobe signal CAS (not show) maintains a high level when the row address strobe signal RAS has a low level corresponding to a stand-by state. Because the column address strobe signal CAS is applied to the semiconductor memory device, temporal current consumption occurs in the semiconductor memory device, effectively deteriorating the internal source voltage VDD. Once the first differential amplifier D1 is operated, if data is accessed before the internal source voltage VDD becomes identical to the reference voltage Vref, an erroneous system operation may occur.
Conventionally, in order to solve such disadvantages, the internal source voltage VDD had to be adjusted to a level that is identical to the reference voltage Vref, by using a method of increasing the magnitude of the source current Istb and improving the response speed of the first differential amplifier D1. However, there is witnessed a disadvantage in that when the source current Istb is increased, the stand-by current of the memory device becomes increased.