The present invention generally relates to a method for to manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can reduce the thickness of an oxide layer formed on a polysilicon layer for bit line contacts.
In a DRAM (dynamic random access memory) in which a is unit cell is constituted by one MOS (metal oxide semiconductor) transistor and one capacitor, it is important to have a high degree of integration in order to increase the capacitance of the capacitor that occupies a large area, and decrease the area that is occupied by the capacitor.
Therefore, in order to form a capacitor having high capacitance within a small area, attempts such as increasing the height of the capacitor or reducing the thickness of a dielectric layer have been made.
However, in the case of increasing the height of the capacitor so as to secure desired capacitance of the capacitor, problems are caused due to an increase in the depth of step portions, resulting from the increase in the height of the capacitor. Further, in the case of reducing the thickness of a dielectric layer, leakage current increases.
In order to cope with these problems, recently, a method has been proposed, in which bit line parasitic capacitance is decreased to the level of one half by using a buried type gate structure, so that the capacitance of a capacitor that is required to maintain the same performance of a sense amplifier is significantly decreased.
FIGS. 1A through 1F are cross-sectional views explaining a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1A, after forming an isolation layer 11 in a cell region CELL and a peripheral region PERI of a substrate 10 in such a way as to delimit active regions 10A, a hard mask layer 12 is formed in the cell region CELL and the peripheral region PERI. Trenches 13 are defined by etching the hard mask layer 12, the isolation layer 11 and the substrate 10 at gate forming zones in the is cell region CELL.
Then, after forming buried type gates BG in the lower portions of the trenches 13, sources S and drains D are formed in the active regions 10A on both sides of the trenches 13. A capping layer 14 is formed in the cell region CELL and the peripheral region PERI to fill the trenches 13. An interlayer dielectric 15 is formed on the capping layer 14.
Next, bit line contact holes 16 are defined by sequentially etching the interlayer dielectric 15, the capping layer 14 and the hard mask layer 12 in the cell region CELL, in such a way as to expose the drains D. A heavily doped polysilicon layer 17 is formed on the entire surface, including the bit line contact holes 16. The polysilicon layer 17 is formed for bit line contacts to electrically connect subsequently formed bit lines and the drains D. The polysilicon layer 17 is formed as a heavily doped polysilicon layer so as to reduce the resistance of bit line contacts.
Referring to FIG. 1B, by removing the polysilicon layer 17, the interlayer dielectric 15, the capping layer 14 and the hard mask layer 12 in the peripheral region PERI, the substrate 10 is exposed in the peripheral region PERI.
Referring to FIG. 1C, by conducting an oxidation process, a gate oxide layer 18A and an oxide layer 18B are respectively formed on the surface of the substrate 10 in the peripheral region PERI and on the surface of the polysilicon layer 17 in the cell region CELL. In the oxidation process, the surface of the polysilicon layer 17 in the cell region CELL is oxidated, by which the oxide layer 18B is formed on the polysilicon layer 17 in the cell region CELL.
A thickness D1 of the oxide layer 18B, which is formed on the polysilicon layer 17 in the cell region CELL, is proportional to the doping concentration of the polysilicon layer 17. Therefore, for example, the thickness D1 of the oxide layer 18B is at least three times greater than a thickness D2 of the gate oxide layer 18A, which is grown on the substrate 10 in the peripheral region PERI.
Referring to FIG. 1D, a mask pattern 19 is formed to cover one portion of the peripheral region PERI excluding the cell region CELL.
Referring to FIG. 1E, the gate oxide layer 18A, which is exposed by the formation of the mask pattern 19, is removed by using the mask pattern 19 as a barrier.
When removing the gate oxide layer 18A, a partial thickness of the oxide layer 18B in the cell region CELL which is not masked by the mask pattern 19 is also etched.
Since the oxide layer 18B in the cell region CELL is at least three times thicker than the gate oxide layer 18A in the peripheral region PERI as described above, when etching is completed, the oxide layer 18B in the cell region CELL is removed only by the partial thickness. Therefore, the oxide layer 18B remains as a predetermined thickness on the polysilicon layer 17 in the cell region CELL.
Referring to FIG. 1F, after removing the mask pattern 19 by conducting an oxidation process, a thin gate oxide layer 30A and a thin oxide layer 30B, each having a small thickness, are respectively formed in the peripheral region PERI and the cell region CELL.
As a result of the oxidation process, a thick gate oxide layer having a structure in which the gate oxide layer 18A and the thin gate oxide layer 30A are stacked is formed in the one portion of the peripheral region PERI. A thin gate oxide layer that is constituted only by the thin gate oxide layer 30A is formed in the other portion of the peripheral region PERI. Hence, a gate oxide layer of a dual structure is formed in the peripheral region PERI.
Thereafter, while not shown in a drawing, a gate conductive layer (not shown) is formed in the cell region CELL and the peripheral region PERI, and by conducting a CMP (chemical mechanical polishing) process to expose the interlayer dielectric 15, bit line contacts are formed in the bit line contact holes 16. The gate conductive layer is used as gate electrodes of transistors that are formed in the peripheral region PERI.
However, the above-described conventional method for manufacturing a semiconductor device has the following problems.
The thick oxide layer 18B that is formed on the polysilicon layer 17 in the cell region CELL remains even after the etching process is subsequently completed. Due to the presence of the remaining oxide layer 18B, when subsequently conducting the CMP process to form the bit line contacts, the bit line contacts are likely to be inappropriately separated and adjoining bit line contacts are likely to be short-circuited.
Thus, in order to prevent the bit line contacts from being short-circuited, it is necessary to reduce the thickness of the oxide layer 18B in the cell region CELL before conducting the CMP process for the separation of the bit line contacts. To this end, when conducting the etching process as shown in FIG. 1E, overetching of the oxide layer 18B in the cell region CELL is needed.
In this regard, if the overetching of the oxide layer 18B in the cell region CELL is conducted, the isolation layer 11 in the peripheral region PERI is attacked. As a consequence, problems are caused in that the height of the isolation layer 11 is decreased and the top corner portions of the isolation layer 11 are lost.
As a result, a phenomenon occurs in which the threshold voltage of a semiconductor device formed in the peripheral region PERI is distorted.