Scaling the dimensions of memory arrays and cells affect operational characteristics of memory technologies. In some memory technologies, a reduction in size of word lines or bit lines can increase the resistivity of those lines as the cross-sectional area of conductive paths is reduced also. The increased resistance of word lines or bit lines may produce a reduction of voltage (e.g., voltage drops) along those lines, for example, as a function of the amount of memory cells conducting current from the word lines or bit lines.
At least some conventional memory architectures, such as those including dynamic random access memory (“DRAM”) cells and Flash memory cells, typically include gates as part of metal oxide semiconductor (“MOS”) transistors or structures. The gates operate to open and close conductive paths between the word lines or bit lines and portions of the memory cells used as storage. When one of the conventional memory cells is unselected, its gate is in an “off” mode of operation and conducts negligible to no current. The gate structures used in conventional memory architectures buffer the conventional memory cells from the affects of increased resistance of word lines or bit lines. The above-described memory architectures, while functional for their specific technologies, are not well suited to address the scaling of memory array and cell dimensions for other memory technologies.
It would be desirable to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional techniques for facilitating memory operations in scaled memory arrays and cells.
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