1. Field of the Invention
The invention relates to an electronic circuit (hereinafter, referred to as xe2x80x9cload driving circuitxe2x80x9d) for controlling the power feed to the load which circuit has a function of detecting an abnormal state such as the disconnection and the short circuit of the load.
2. Description of the Related Art
FIG. 1 is a schematic diagram for conceptually describing the structure of a conventional load driving circuit in a high side driver configuration which circuit is used in the electronic control unit (ECU) mounted in a vehicle and has a load disconnection and/or short circuit detection function. The circuit of FIG. 1 comprises a battery 1 having its negative electrode connected to ground; a load driving circuit IC (integrated circuit) 100 having its positive power terminal or pin 101 connected to the positive electrode of the battery 1 and its negative power or ground pin 103 connected to ground; a load 2 connected between an output terminal 102 of IC 100 and the ground; and a pull-up resistor 3 connected between positive power pin 101 and output pin 102 of IC 100 for pulling up the IC output pin 102.
In the load driving circuit IC 100, between its positive power 101 and output 102 pins, there are connected the drain and source of an N-channel power MOSFET 111 and the cathode and anode of a protection diode 112, respectively. Between the gate and the source of FET 111 there is connected a diode 117 to prevent the reverse biasing of the FET 111 gate. The IC 100 further comprises a charge pump 109 having its input voltage supplied from the positive electrode of battery 1 through a dedicated pin 104 of IC 100 to provide a charge voltage Vc; a switch circuit 110 connected between the output of charge pump 109 and the gate of FET 111 to effect connection and disconnection between them; a buffer 108 having its input connected to a power feed control signal input pin 105 to receive a binary power feed control signal Sa from a not-shown external controller and its output connected to a control terminal of switch circuit 110 so as to control the switching operation thereof; an inverter 114 having its input connected to the buffer 108 output to provide an inverted version {overscore (Sa)} of signal Sa; a discharging NPN transistor 14 having its gate connected to the inverter 114 output and its emitter connected to the ground pin 103; a resistor 116 connected between the collector of discharging transistor 14 and the node including the gate of power FET 111; and a comparator 113 having its non-inverting input connected to the power output pin 102, its inverting input supplied with a reference voltage Vr and its output Sc connected to a comparator output pin 106 which is connected to the above-mentioned not-shown controller.
In thus structured load driving circuit, if the power feed control signal Sa is at the high level that indicates that the battery voltage Vb should be supplied to the load 2, then the switch 110 is on (i.e., conductive) and the transistor 115 is off(i.e., nonconductive), holding the power FET 111 on, which means that the load 2 is electrically connected to the battery 1 through the FET 111. If the power feed control signal Sa is at the low level that indicates that the battery voltage Vb should not be supplied to the load 2, then the switch 110 is off and the transistor 115 is on, holding the power FET 111 off, which means that the load 2 is not connected to the battery 1. For this purpose, the charge pump circuit 109 is so arranged as to use the battery voltage Vb supplied through an IC pin 104 and generate a raised voltage Vc higher than the battery voltage Vb by more than the threshold voltage Vt of the power FET 111: i.e., Vc greater than Vb+Vt.
Since the load driver IC 100 is provided with the comparator 113 and has the external pull-up resistor 3, the IC 100 can detect abnormalities such as a disconnection and a short circuit of the load 2. Though a short circuit can be always detected by monitoring the level of the comparator 113 output or the IC pin 106, the abnormality detection is preferably performed while the power FET 111 is off. If the FET 111 is off for example, then the current from the battery 1 flows mainly through either of the following two current paths in response to the connection condition of the load 2. That is, the current flows through:
in case of disconnection of the load 2,
the first path comprising the battery 1 positive electrode, the pull-up resistor 3, the power output pin 102, the diode 117, the resistor 116, the discharging transistor 115, the ground pin 103 and the battery 1 negative electrode; and
in cases other than disconnection of the load 2,
the second path comprising the battery 1 positive electrode, the pull-up resistor 3, the load 2 and the battery 1 negative electrode.
If the load 2 is normally connected, then the FET 111 being off causes the current to flow through the second path. In this case, The level of the power output pin 102, i.e., Vo, is given by Vbxc2x7R2/(R2+R3). Here, R2 and R3 are the resistor values of the load 2 and the pull-up resistor 3, respectively. (Hereinafter, we make it a rule to express the resistance value of an element denoted by a reference numeral xe2x80x9cNxe2x80x9d with a form of xe2x80x9cRNxe2x80x9d.) Since the resistance R3 of the resistor 3 is usually set to a sufficiently large value as compared with the resistance value R2 of the load 2, the output pin 102 level is close to 0V. If a disconnection exists in the load 2 when the load is viewed from its both ends, then the FET 111 being off causes the current to flow through the first path, resulting in the level Vo of the IC pin 102 being equal to the voltage drop due to diode 117, resistor 116 and transistor 115. The voltage drop is roughly given by Vbxc2x7R116/(R3+R116).
Thus, as long as the condition that R2 less than R3 less than R116 is met, it is possible to correctly detect the disconnection and the normal connection of the load 2 from the output Sc of the comparator 113 by setting the reference voltage Vr of the comparator 113 to a medium value between Vbxc2x7R2/(R2+R3) and Vbxc2x7R116/(R3+R116).
For this purpose, it is a possible solution that the resistance value R3 is set to a relatively large value and the resistance value R116 is set to a still larger value. However, this solution causes the impedance of the discharge path through which the electric charges are drawn out of the gate capacitance of the power FET 111 to be large, which disadvantageously results in increases in the turn-off time of the power FET 111 (i.e., a speed-down of the load driving operation) and the switching loss of the power FET 111.
Considering the foregoing, we makes it an object of the invention to provide a load driving circuit capable of detecting abnormality such as disconnection of the load with a high accuracy and driving the load at a high speed with low power consumption.
It is another object of the invention to provide a load driver IC which enables the detection of abnormality such as disconnection of the load with a high accuracy while driving the load at a high speed with low power consumption.
According to an aspect of the invention, a circuit for controlling a feed of a power supply voltage of a power supply to a load which circuit has a function of detecting a load driving state such as disconnection and short circuit is provided. The circuit comprises: a MOSFET connected in series with the power supply and the load for effecting an on/off operation; a circuit (such as a charge pump circuit) responsive to a feed control signal given from external for supplying a driving voltage to the gate to turn the MOSFET on; a resistor connected between the power supply and the load for causing a voltage drop during an off period of the MOSFET; a detection circuit or a comparator for providing a signal indicative of the load driving state on the basis of a comparison between a predetermined reference voltage and a voltage of a node between the load and the MOSFET; protection element (such as a diode) connected between a source and a gate of the MOSFET for providing a protection against a reverse bias applied between the source and gate by by-passing; transistor circuit connected between the source and gate of the MOSFET for discharging a gate capacitance of the MOSFET; and driving circuit responsive to a non-feed indication by the feed control signal for flowing a driving current in a control electrode of the transistor circuit such that a magnitude of the driving current is enough to operate the transistor circuit and the voltage drop caused by the driving current is smaller than a difference between the power supply voltage and the predetermined reference voltage.
The transistor circuit may include a plurality (N) of transistors in such a configuration that a channel current of one of the transistors flows in a control electrode of a next transistor.
The driving circuit may comprise a resistor element for providing such a resistance as let the driving current flow, and a circuit, serially connected to the resistor element and responsive to the feed control signal, for effecting an on/off operation.
Alternatively, the driving means may comprise a current source circuit for providing the driving current; and a circuit, responsive to the non-feed indication, for enabling the current source circuit to operate.
The invention can be implemented either in a high side driver configuration or in a low side driver configuration. In the high side driver configuration, the MOSFET is connected between the power supply and the load and the MOSFET is of an N-channel type. In this case, the transistor circuit includes a PNP transistor.
In the low side driver configuration, the MOSFET is inserted in a low side of the load and the MOSFET is of a P-channel type. In this case, the transistor circuit includes an NPN transistor.
According to another aspect of the invention, an integrated circuit for use in the above-mentioned load driving circuit is provided.