Communications networks involve moving information from one entity to another. Communications networks, from the very basic to the highly advanced, require varied information to be grouped at a source entity, transmitted, and then ungrouped at a destination entity. An inherent problem in communications networks involves the process of multiplexing and demultiplexing information to be transmitted. This problem is greatly intensified in high speed networks where rapid processing and transmission requirements magnify the issues surrounding multiplexing and demultiplexing data. In an attempt to address this problem, a plurality of high-speed communications network protocols have adopted complex control signals to control the flow of information. One such net work protocol is asynchronous transfer mode (ATM).
Historically, ATM networks have been some of die few communications networks that support simultaneous transmission of voice, video, and data. The ATM network protocol is a connection-oriented protocol that utilizes short fixed-length packets called “cells”. The use of cells allows ATM networks to provide high-throughput, low delay, and service-independent transport. The user of an ATM network is not assigned a static bandwidth as in time division multiplexed systems; the user can obtain dynamically allocated bandwidth and bandwidth on demand. ATM devices typically support network links that carry traffic of a plurality of different protocols at a plurality of different speeds. One ATM node might simultaneously support the data traffic of a plurality of xDSL modems, DS1, DS3, OC-3, OC-12, E1, E3, STM-1, and/or STM-4 connections. The protocol of ATM was designed to facilitate the implementation of varied services in hardware, thus resulting in the ability to quickly process data with little incurred delay. In order to rapidly process the data relating to the multiple subscriber links, the ATM node must have an efficient means by which to interface with these subscriber links. This interface can be described as the interface between the ATM Layer and the Physical Layer.
The ATM protocol has a hierarchical layered structure which is similar to the open systems interconnection (OSI) reference model. The physical layer of the ATM hierarchy corresponds directly to the Physical Layer of the OSI model. The physical layer embodies the manner in which communicating entities interpret the electrical representations of the ones and zeros transmitted and received in a session. Header error control (HEC) functions are also performed by the physical layer. The physical layer interfaces with the ATM Layer. The ATM Layer performs a majority of the functions described in the data link (Layer 2) and Network (Layer 3) of the OSI model. The ATM layer is responsible for receiving data from the physical device, interpreting the source and destination of that data, and muxing the data for transport. In addition, the ATM layers must also demux data and transmit that data to the appropriate physical layers. It is in the ATM layer that virtual path identifiers (VPI) and virtual channel identifiers (VCI) are translated and cell headers are generated or extracted. In the typical case, the ATM Layer can be viewed as the master device controlling a large amount of slave devices, physical layer devices. The resulting network of ATM layer devices and physical layer devices make up the lower level part of a system that is known as the ATM switching system.
The ATM switching system performs the function of receiving ATM cell streams on its interfaces. The ATM switching system independently transmits each cell to a predefined output interface based on input port, ATM cell header, and associated connection. An individual cell that enters an ATM switching system is processed independently based on a service level agreement and the status of the system. The whole of service level agreements in a system dictate policies that are to be carried out in times of congestion. In order to carry out service level agreements and the associated quality of service (QoS) levels, the ATM switching system must be able implement scheduling and buffering techniques to minimize loss and prioritize traffic in the most efficient manner possible. This implementation involves a plurality of considerations, and these considerations are of concern to most standard ATM switching systems.
The standard ATM switching fabric involves an ATM Layer Device which typically processes data at a rate far faster than any of its associated physical (PHY) layer devices. For example, a typical ATM layer traffic processing device operating at rates of 622 Mbps may be employed for ATM traffic processing for DS3 (45 mbps), DS1 (1.544 Mbps), or DSL (144 Kbps to 8 Mbps) ports in a switching system. In this case the high speed ATM layer device can be shared across a multitude of low speed physical layer interfaces. The requirement for sharing the ATM layer across multiple physical layer interfaces is a very typical architecture for an ATM node. ATM switching systems providing large numbers of low/medium speed traffic interfaces can achieve greater port densities at lower cost by sharing the ATM layer over a greater number of port interfaces. For example, in a DSLAM or broadband access concentrator application, the ATM node has a small number of high bandwidth uplinks and a large group of lower bandwidth subscriber links. In this manner, the ATM node multiplexes a plurality of subscriber links onto a high bandwidth link to a larger network. Thereby, the ATM layer device must have the ability to interface with multiple PHY layer devices. The universal test and operations physical interface for ATM (UTOPIA) protocol defines a standard interface between the ATM layer and PHY layer of an ATM switching system. The UTOPIA interface specification defines the control signals to be interchanged between the ATM layer and PHY layer, the timing relationships of control signals and data flow, and the management and control of such an interface. As mentioned earlier, the ATM layer devices multiplex data onto high bandwidth links. In accordance with this characteristic, UTOPIA level 1 was designed to support an 8-bit cell transfer mode to support a single interface at rates up to 155 Mbps (OC-3). The UTOPIA level 2 specification was designed to include a 16-bit cell transfer supporting multiple physical interfaces having a combined line rate up to 622 Mbps (OC-12). In order to interface high speed ATM layer traffic processors and not incur buffer over-run at the PHY layer devices, the UTOPIA specification designates certain flow control signals to be communicated between the two layers. This allows the ATM layer to be rate matched to the PHY layer in order to service the PHY layer at its corresponding transmission rate.
FIG. 1 depicts the flow control signals in accordance with the prior art, UTOPIA Level 1 and 2. The UTOPIA standard specifies an addressing process enabled by a 5 bit addressing signal. A PHY Layer Device 180A is identified in a reception by a 5 bit TxAddr[B:0] 115 signal. A PHY Layer Device 180A is identified in a transmission by a 5 bit RxAddr[B:0] 145 signal. The flow control signals and the data transmissions described by UTOPIA are synchronized by a transmit clock, TxClk 135, and a receive clock, RxClk 165. In the 8-bit mode, the clocking rate is usually 25 Mhz and double that rate, 50 Mhz, for 16-bit mode. An additional synchronization signal indicates the beginning of cell transfer. Start-Of-Cell, TxSOC 125 or RxSOC 155, designates when the data signal, Transmit Data (TxData[A:0]) 110 or Receive Data (RxData[A:0]) 140, contains the first valid byte of a cell. UTOPIA requires a PHY Layer Device to implement rate matching buffers, i.e. FIFO's. Although the PHY Layer Device FIFOs are necessary, they are usually of minimal size (2-4 cells). With such small buffers, the two layers must be able to indicate their respective statuses in order to process communication data successfully. The ATM Layer 101 indicates status by asserting the Transmit Enable, TxEnb 130, signal when TxData 110 contains valid cell data. In addition, the ATM Layer 101 asserts the Received Enable, RxEnb 160, to indicate that RxData 140 and RxSOC 155 will be sampled at the end of the next cycle. The PHY Layer Device communicates status by asserting Cell Available signals. Transmit Cell Available, TxClav 120, is asserted to indicate the PHY Layer Device can accept the transfer of a cell. Receive Cell Available, RxClav 150, is asserted to indicate the PHY Layer has a cell ready for transfer to the ATM Layer.
It is apparent that the aforementioned flow control signals are extensive and can be quite cumbersome on the system as a whole. This complicated flow control is a result of the inherent nature of the ATM protocol. The ATM protocol is a connection oriented, protocol independent, cell based solution. Thus, ATM requires that each cell be independently processed. As technology expands, the cumbersome flow control signals become a more significant problem. As previously mentioned, ATM nodes in broadband network access applications most typically multiplex data from a plurality of low bandwidth subscriber links onto one high bandwidth network link. A typical ATM node is, for example but not limited to, a digital subscriber line access module (DSLAM). A DSLAM might aggregate multiple ADSL G.992.2 (G.Lite) subscribers onto a single OC-12 interface to an upstream network. In this case, the DSLAM would have the bandwidth capacity to multiplex up to 414 G.Lite 1.5 Mbps subscribers on to one 622 Mbps OC-12 interface. Thus, the ATM layer devices of the DSLAM would have to communicate to a large number of the ADSL PHY layer devices. This example illustrates the limitations of the cumbersome flow control requirements of UTOPIA. UTOPIA specifies a 5-bit address field for the PHY Layer Devices. A 5-bit address field results in 32 possible addresses in which one address is reserved for idle transactions. Therefore, an ATM layer device operating in accordance with the UTOPIA specification can only support 31 PHY layer device interfaces. As exemplified by the above DSLAM discussion, this characteristic would be severely limiting for a high bandwidth ATM node attempting to support 411 PHY layer devices. This would require the ATM node to have at least 14 ATM layer devices.
The limitations of the flow control specification within UTOPIA have many significant impacts. The boundary of 31 PHY Layer Devices to a single ATM Layer Device greatly affects the cost of an ATM switching system. The ATM Layer Devices is are fairly costly due to their bandwidth performance, traffic processing and traffic management complexity, and ability to support large amounts of high-speed cell buffers. In view of the ever-increasing processing rates of electronics hardware, it would be extremely costly to have the amount of ATM Layer Devices dictated not by the processing capacity but by the specifications of an interface standard.
Another problem resulting from the UTOPIA limitation is the increase in complexity of the ATM switching system. In the system described above with 14 ATM layer devices, a complex hierarchy of control signals would most likely be required in order manage the processes on the 14 devices. This management would be greatly simplified by reducing the amount of ATM layer devices that are necessary.