The present invention relates to semiconductor devices, and more particularly, to vertical semiconductor devices.
In the fabrication process of a conventional vertical transistor, shallow trench isolation (STI) regions are usually formed to isolate the vertical transistor from the surrounding devices. However, the formation of the STI regions is usually not perfectly aligned with the deep trench of the vertical transistor. As a result, the drain/source regions of the vertical transistor usually has sharp corners resulting in low threshold voltage (Vt) for the vertical transistor. Low Vt is undesirable because the vertical transistor may erroneously switch states in response to a small glitch on the input signal.
Therefore, there is a need for a structure of a novel vertical transistor which has Vt relatively higher than that of prior art. Also, there is a need for a method for fabricating the novel vertical transistor.