The present invention relates to techniques for alleviating distortion in switching amplifiers. More specifically, the present invention provides methods and apparatus for compensating for xe2x80x9cbreak-before-makexe2x80x9d distortion in digital switching amplifiers.
Digital power amplifiers are increasing in popularity due to their high power efficiency and signal fidelity. An example of an digital audio amplifier 100 which employs oversampling and noise-shaping techniques is shown in FIG. 1. The input audio signal is oversampled and converted into 1-bit digital data. These data are used by power stage driver 102 to control power switches M1 and M2 which, in this example, comprise two nmos power transistors. To reduce the quantization noise introduced by sampling, amplifier 100 employs a noise-shaping loop filter 104 in a feedback loop which pushes the quantization noise out of the audio signal band. A low pass filter comprising inductor L and capacitor CAP filters out high frequency noise and recovers the amplified audio signal which drives speaker 106.
Referring now to FIGS. 1 and 2a, break-before-make (BBM) generator 108 receives the 1-bit switching signal Y from comparator 110 and generates two signals A and B which are 180 degrees out of phase with each other. A and B are level-shifted by power stage driver 102 to become Axe2x80x2 and Bxe2x80x2 which are used to alternately turn on power transistors M1 and M2. As is well known, if there is no dead time between pulses in A and B, i.e., time when both A and B are low, there is a possibility that both of transistors M1 and M2 may be turned on at the same time creating the potential for an undesirable and possibly catastrophic shoot-through current from the positive power supply VCC to the negative power supply VSS at each transition of Y (as shown in the waveform designated Ist). Such a condition may arise, for example, due to the delays for signals A and B through power stage driver 102, as well as the rise and fall times of transistors M1 and M2. At a minimum, such shoot-through current increases switching losses thereby reducing the amplifier""s power efficiency. In the worst case, power transistors M1 and M2 may be damaged or destroyed.
To eliminate shoot-through current and avoid its deleterious effects, and as shown in FIG. 2b, a period of dead time (also referred to herein as break-before-make (BBM) time) is introduced as between signals A and B such that there is a period of time between signal transitions during which both signals are low. This ensures that transistors M1 and M2 are never turned on at the same time even when there are delay mismatches between the rise and fall times of the transistors. Input data BBM less than 2:0 greater than  allows adjustment of BBM time to meet the design requirements of the particular amplifier as shown in Table I. Unfortunately, while the BBM generator eliminates shoot-through current, it produces a degenerative effect on amplifier performance by introducing harmonic distortion. The nature of this distortion is described below with reference to FIGS. 3a, 3b, and 4a-4c. 
Referring also to amplifier 100 of FIG. 1, when transistors M1 and M2 are off during the BBM period, the voltage at node C is determined by parasitic capacitance CP. Because inductor L resists instantaneous changes in current, when the output current of the amplifier is charging CAP, the voltage at node C is pushed to VCC (clipped by Schottky diode D1) during the BBM period. On the other hand, when the output current is discharging CAP, the voltage at node C is pulled down to VSS (clipped by Schottky diode D2).
FIG. 3a shows the current through inductor L when the input to amplifier 100 is grounded. Under this condition, the signal at node Y is a square wave and the resulting current through L is represented by a sawtooth waveform which changes polarity at each transition of the signal at node Y. By contrast, FIG. 3b shows the switching pattern of the signal at node Y and the current through inductor L when the input to the amplifier is a sine wave. In the first half of the sine wave cycle, the switching pattern at node Y is modulated to have a relatively wide pulse width resulting in transistor M1 being turned on more often than transistor M2. During this time, the inductor current is largely positive, i.e., charging CAP and directed into speaker 106. During the second half of the sine wave cycle, the switching pattern at node Y is modulated to have a relatively narrow pulse width such that transistor M2 is now on more often than transistor M1. This results in a largely negative inductor current, i.e., discharging CAP and flowing out of speaker 106. Near the zero crossing of the sine wave, the switching pattern at node Y is similar to that shown in FIG. 3a which causes the inductor current to switch polarity at each Y node signal transition.
With the description of FIGS. 3a and 3b as background, the nature of the BBM distortion will now be described with reference to FIGS. 4a-4c. FIG. 4a illustrates the case where the switching pattern at node Y is a square wave. This results in waveforms A and B with a predetermined BBM period as shown. The current through inductor L is also shown. Between t1 and t2, i.e., the BBM period, both transistors M1 and M2 are off and the voltage at node C is pulled down to VSS because the inductor current is discharging CP. Between t2 and t3 M2 is turned on, keeping the voltage at node C at VSS while the inductor current change polarity. From t3 to t4, i.e., the next BBM period, M2 is turned off again and the voltage at node C is pushed to VCC because the inductor current is now flowing in the other direction. Beyond t5, this switching pattern is repeated and it can be seen by comparing the signals at nodes Y and C that the BBM time has no effect on the output switching pattern when the input is a square wave.
FIG. 4b illustrates the case where the switching pattern at node Y has relatively wide pulse widths as described above with reference to the first half of the cycle of the sine wave of FIG. 3b. As described above, this corresponds to an inductor current which is charging CAP and directed into speaker 106. At time t1, M2 is turned off and the voltage at node C is kept at VSS by the inductor current during the BBM period until M1 is turned on at t2, at which point the voltage at node C is pulled up to VCC. When M1 is turned off again at t3, the voltage at node C is again pulled down to VSS by the inductor current. After the next BBM period (t3-t4), M2 is turned on and the voltage at node C is kept at VSS. By comparing the signals at node Y and C it can be seen that the output pulse width (at node C) is reduced from the input pulse width (at node Y) by a BBM period.
FIG. 4c illustrates the case where the switching pattern at node Y has relatively narrow pulse widths as described above with reference to the second half of the cycle of the sine wave of FIG. 3b. As described above, this corresponds to an inductor current which is charging parasitic capacitor CP. At time t1, M1 is turned off and the voltage at node C is kept at VCC during the BBM period until M2 is turned on at t2, at which point the voltage at node C is pulled down to VSS. When M2 is turned off again at t3, the voltage at node C is again pulled up to VCC by the inductor current. After the next BBM period (t3-t4), M1 is turned on and the voltage at node C is kept at VCC. By comparing the signals at node Y and C it can be seen that the output pulse width (at node C) is increased relative to the input pulse width (at node Y) by a BBM period.
Thus, for example, for a sine wave input, the output switching pattern at node C introduces relatively little or no distortion at the zero crossings of the input signal. However, the pulse width at node C may be reduced or increased by an entire BBM period during other parts of the sine wave cycle. Because these changes in the output waveform are dependent on the input signal, undesirable distortion results. It is therefore desirable to provide techniques by which this distortion may be reduced or eliminated.
According to the present invention, a technique is provided by which the distortion due to xe2x80x9cbreak-before-makexe2x80x9d (BBM) periods in digital switching amplifiers may be reduced or eliminated by converting the BBM periods into loop delay. A distortion detection circuit detects the BBM distortion and a distortion compensation circuit pre-shapes the input pulse to compensate for the distortion caused by the subsequent BBM circuitry. That is, the distortion compensation circuit xe2x80x9cpre-distortsxe2x80x9d the input pulse pattern such that the output pulse is delayed from the input pulse by the BBM period but has little or no BBM distortion.
Thus, the invention provides a switching amplifier having an input stage for generating a switching signal. Break-before-make distortion compensation circuitry alters the switching signal. Break-before-make generator circuitry generates two drive signals from the altered switching signal. A power stage includes two switches which are alternately driven by the two drive signals. Break-before-make distortion detection circuitry detects a distortion pattern at the power stage output node and controls the break-before-make distortion compensation circuitry to alter the switching signal in response to the distortion pattern detected to thereby eliminate at least some break-before-make distortion.
The present invention also provides a method for reducing break-before-make distortion in a switching amplifier which includes break-before-make generator circuitry for generating two drive signals from an altered switching signal, and a power stage including two switches which are alternately driven by the two drive signals. A distortion pattern is detected at the output node of the power stage. A switching signal is altered before the break-before-make generator circuitry in response to the distortion pattern detected thereby eliminating at least a portion of the break-before-make distortion.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.