1. Field of the Invention
The present invention relates to field programmable gate array (FPGA) integrated circuits having an array of logic modules and interconnect architecture configured by static random access memory (SRAM) cells disposed within the array of logic modules. More particularly, the present invention relates to cyclic redundancy checking (CRC) of the contents of the configuration SRAM for the logic modules and interconnect architecture in an FPGA.
2. The Prior Art
One manner known in the art for configuring the logic modules, interconnect and other circuits, such as input/output (I/O) circuits, in an FPGA is with data stored in SRAM cells distributed throughout the FPGA. The SRAM cells employed to configure the FPGA to implement the user-design are typically referred to as configuration SRAM. For reasons of reliability, it is important that the data in the configuration SRAM remains unchanged. Hence, one of the primary disadvantages in using configuration SRAM is that the data in the configuration SRAM is susceptible to an unintended change of at least one bit, known as single event upset (SEU).
In certain high reliability applications the undetected occurrence of a SEU is not considered acceptable. The reluctance among design engineers to use SRAM configured FPGA's in high reliability applications such as space, aeronautics, and military equipment due to the vulnerability to SEU's in harsh environments is well known. Though lowering the probability of an SEU in a harsh environment may be accomplished, eliminating the possibility of an SEU altogether seems unlikely. However, by checking the contents of the configuration SRAM for the FPGA, the detection and correction of an SEU may be accomplished.
In addition to providing SRAM for the configuration of an FPGA, the need for fast, flexible, inexpensive user-assignable SRAM for a variety of purposes such as register files, FIFOs, scratch pads, look-up tables, etc. has become more apparent. Because as integrated circuit technology advances, the shrinking of geometries improves performance and increases densities so that the design of systems of ever increasing complexity and performance at ever decreasing cost is made feasible.
This is especially true in logic products such as Application Specific Integrated Circuits (ASICs), Complex Programmable Logic Devices (CPLDs), and Field Programmable Gate Arrays (FPGAs). There are significant cost and performance savings to be obtained by integrating fast, flexible, inexpensive user-assignable SRAM directly into these types of logic products. However, providing this memory by having other than explicitly dedicated SRAM blocks included in the FPGA has not proved satisfactory. In one case, the implementation of memory without dedicated SRAM blocks has been done using array logic modules and flip-flops.
When user-assignable SRAM is implemented with the logic modules in the FPGA, it requires a substantial amount of the routing and logic resources of the FPGA, and the critical paths are quite long for even a small memory block. This substantially degrades both the performance and flexibility of the FPGA, and offers no density improvement over ordinary FPGA functionality. Further, when the logic blocks are configured as user-assignable SRAM, checking the contents of the configuration SRAM is not readily accomplished, because changing the contents of user-assignable SRAM alters the data in the configuration SRAM.
For example, Xilinx offers the capability on their 4000 series of parts to use the configurable logic blocks as 16×1 user-assignable SRAM blocks, and also offers the ability to check contents of the configuration SRAM. However, when the logic blocks are configured as user-assignable SRAM, checking the data in the configuration SRAM can only be accomplished by providing an additional PROM to mask off those logic modules implemented as SRAM, because changing the SRAM contents alters the data in the configuration memory. The use of a separate PROM is undesirable, because PROMs are expensive, require additional printed circuit board space, and consume I/O pins on the FPGA itself.
It is therefore an object of the present invention to detect and/or correct SEUs to the data in a configuration SRAM of an FPGA.
It is yet another object of the present invention to detect and/or correct SEUs to the data in a configuration SRAM of an FPGA without the need for an additional external component.
It is yet another object of the present invention to detect and/or correct SEUs to data in a user-assignable SRAM of an FPGA.
It is yet another object of the present invention to detect and/or correct SEUs to fixed data in a user-assignable SRAM of an FPGA without the need for an external component.
It is yet another object of the present invention to employ cyclical redundancy checking (CRC) to detect an SEU to the data in a configuration SRAM of an FPGA.
It is yet another object of the present invention to employ cyclical redundancy checking (CRC) to detect an SEU to fixed data in a user-assignable SRAM of an FPGA.