The present invention relates to a semiconductor design technology, and more particularly to a semiconductor memory device capable of rapidly transferring data, which are applied to local I/O lines, to a global I/O line.
A plurality of memory banks are provided within a semiconductor memory device such as a DDR SDRAM (Double Data Rate Synchronous DRAM) and each memory bank is comprised of a set of a plurality of memory cells each of which has a cell transistor and a cell capacitor. Herein, an area in which the memory bank is positioned is called “core area” and an area to input and output the data to and from the memory bank is called “peripheral area.” The data transferred from the peripheral area at a write operation are inputted into the core area through a write driver which is positioned in the vicinity of the core area and the data are outputted from the core area to the peripheral area through an I/O sense amplifier.
Generally, a global I/O line is a data line to be coupled between a data I/O pin and an I/O sense amplifier and a local I/O line is a data line to be coupled between the core area and an I/O sense amplifier.
FIG. 1 is a circuit diagram illustrating a conventional I/O sense amplifier. The conventional I/O sense amplifier includes a sense amplifying unit 110 for sensing and amplifying data applied to positive/negative local I/O lines LIO and LIOb in response to the I/O strobe signal IOSTP, a precharging unit 130 for precharging first and second output terminals OUT and OUTb of the sense amplifying unit 110 in response to the I/O strobe signal IOSTP, and a pull-up/pull-down driving unit 150 for pull-up and pull-down driving the global I/O line GIO in response to a voltage level of the first and second output terminals OUT and OUTb of the sense amplifying unit 110.
The sense amplifying unit 110 includes a differential input unit 112 for receiving differential data applied to the positive/negative local I/O lines LIO and LIOb, a differential amplifier 114 for amplifying the differential data inputted from the differential input unit 112, and an activation unit 116 for enabling the differential input unit 112 in response to the I/O strobe signal IOSTP.
The I/O sense amplifying unit is a circuit which senses and amplifies a minute voltage level difference between the data applied to the positive/negative local I/O lines LIO and LIOb. Therefore, in order to properly sense the minute voltage level difference of the differential data, there is provided a minimum voltage level difference Δt between the positive/negative local I/O lines LIO and LIOb. With the minimum voltage level difference Δt, the differential input unit 112 is activated, the data loaded on the positive/negative local I/O lines LIO and LIOb are amplified, and then the amplified data are transferred to the global I/O line GIO.
FIG. 2 is a timing diagram illustrating an operation of each signal of FIG. 1. In FIG. 2, there are shown voltage levels of the positive/negative I/O lines LIO and LIOb, the I/O strobe signal IOSTP, the first and second output terminals OUT and OUTb, and the global I/O line GIO.
An operation of the conventional sense amplifier will be illustrated below referring to FIGS. 1 and 2. For the sake of convenience in illustration, it is assumed that logic high data is transferred through the positive local I/O line LIO and logic low data is transferred through the negative I/O line LIOb.
First, before a read command RD is inputted to the semiconductor memory device, the I/O strobe signal IOSTP is maintained in a low level. Accordingly, an NMOS transistor NM1 in the activation unit 116 is turned off, the current flowing toward a ground voltage level is blocked, and then the sense amplifier is in a standby state. Two PMOS transistors PM1 and PM2 in the precharging unit 130 are turned on such that the first and second output terminals OUT and OUTb are precharged to a voltage level corresponding to an external voltage VDD.
When the read command RD is inputted, the voltage level of the negative local I/O line LIOb is more and more decreased. The I/O strobe signal IOSTP is activated to a high level after the time of tA which is required to guarantee the voltage level difference of ΔV between the positive and negative local I/O lines LIO and LIOb.
At this time, the two PMOS transistors PM1 and PM2 in the precharging unit 130 are turned off so that the first and second output terminals OUT and OUTb are not precharged any more to the voltage level of the external voltage VDD. The NMOS transistor NM1 in the activation unit 116 is turned on so that the sense amplifying unit 110 senses the differential data having the voltage level difference of ΔV and the sensed data are outputted through the first and second output terminals OUT and OUTb.
An operation of the sense amplifying unit 110 will be described below. First, when the I/O strobe signal IOSTP is transited from a low level to a high level, an NMOS transistor NM2 of which the gate is connected to the negative local I/O line LIOb is gradually turned off so that an amount of the current flowing in the NMOS transistor NM2 is smaller than that in an NMOS transistor NM3 to be connected to the positive local I/O line LIO. An NMOS transistor NM5 connected to the first output terminal OUT of the differential amplifier 114 is strongly turned off more than an NMOS transistor NM4 connected to the second output terminal OUTb so that the voltage level of the second output terminal OUTb strongly turns on a PMOS transistor PM3 of which the source and drain are connected to the first output terminal OUT. Accordingly, the voltage level of the first output terminal OUT is increased and the voltage level of the second output terminal OUTb is decreased by an NMOS transistor NM4 which is turned on by the voltage level of the first output terminal OUT.
As a result, a high level of the first output terminal OUT turns off an NMOS transistor NM6 in the pull-up/pull-down driving unit 150 and a low level of the second output terminal OUTb turns on a PMOS transistor PM4 in the pull-up/pull-down driving unit 150, thereby pull-up driving the global I/O line GIO in the pull-up/pull-down driving unit 150.
On the contrary, when logic low data are transferred through the positive local I/O line LIO and logic high data are transferred through the negative local I/O line LIOb, the first output terminal OUT is in a low level and the second output terminal OUTb is in a high level, thereby pull-down driving the global I/O line GIO in the pull-up/pull-down driving unit 150.
Meanwhile, ‘tD’ in FIG. 2 is a time which is taken from the transition time, in which the I/O strobe signal IOSTP is transited from the low level to the high level, to the pull-up driving of the global I/O line GIO.
In other words, ‘tA’ is a time which is required to secure the voltage difference of ΔV for safely performing the sensing operation when the voltage difference between the positive local I/O line LIO and the negative local I/O line LIOb is amplified, and ‘tD’ is a time which is taken from the activation of the I/O strobe signal IOSTP to the pull-up and pull-down driving of the global I/O line GIO via the sense amplification. Accordingly, ‘tA+tD’ is a time taken by the data transmission time while the differential data, which are applied to the positive/negative local I/O lines LIO and LIOb, are transferred to the global I/O line GIO.
On the other hand, the read operation of the semiconductor memory device becomes slow if the time of ‘tA+tD’ gets longer. As a result, there is a problem in that the working speed of the chip becomes slow. Different kinds of plans are presented in order to satisfy this working speed of the semiconductor memory device these days. Further, the reduction in the time of ‘tA+tD’ may be improved to realize the high-speed operation of semiconductor memory device.