1. Field of the Invention
The present invention relates to a data processing control system, a controller, a data processing control method, a program, and a medium.
2. Description of the Related Art
(A) With recent advances in multimedia technology, continuous media data such as digitized moving image data, voice data, etc. have increasingly come to be stored on hard disks and other data storage devices (random access devices) Because of huge data sizes of continuous media data, it is becoming common to configure a plurality of random access devices into an array and make the array appear to the system as a single large capacity virtual device.
With this trend in mind, the configuration and operation of a prior art data storage array system will be described with reference to FIGS. 11(a), 11(b), and 13. FIG. 11(a) is a flow chart of a semaphore acquisition operation according to the prior art, and FIG. 11(b) is a flow chart of a semaphore release operation. FIG. 13 is a diagram showing the configuration of the prior art data storage array system.
As shown in FIG. 13, the prior art data storage array system comprises a controller 1001xe2x80x2 and data storage devices 1021xe2x80x2, 1022xe2x80x2, . . . , 102nxe2x80x2. 
When a data access request is received from an external host device 1003xe2x80x2 (see FIG. 13), the controller 1001xe2x80x2 generates a child thread to control access to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2. The data storage array system can thus accept a plurality of data access requests simultaneously (command queuing). With command queuing, the data storage array system can perform data access and command issuing operations in overlapping fashion on the data storage devices, and data access performance can thus be enhanced.
In the child thread, the data access request issued by the external host device 1003xe2x80x2 is divided into a plurality of requests to issue to the data storage devices 10211, 102nxe2x80x2. When all the data access requests to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2 are completed, the child thread sends a completion notification to the external host device 1003xe2x80x2.
In the child thread generated by the controller 1001xe2x80x2, access control is performed using a synchronization mechanism called a semaphore in order to prevent excessive load from being applied to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2. To facilitate understanding, the semaphore will be briefly explain below.
A semaphore is a synchronization mechanism used to control access rights to system resources. In operation, access to the system is controlled by performing a semaphore acquisition operation just before accessing a system resource and by performing a semaphore release operation upon completing the access to the system resource.
Here, let A denote the maximum allowed number of simultaneous accesses to a system resource and B the maximum number of accesses currently being made to the system resource. Then, as shown in the process of FIG. 11(a), the semaphore acquisition operation is started (S1), and if A greater than B, the semaphore is successfully acquired, granting the request for access to the system resource, after which B is incremented and the semaphore acquisition operation is terminated (S2, S4, and S5). On the other hand, if Axe2x89xa6B, the semaphore acquisition operation waits until B becomes smaller than A (S3). In the process shown in FIG. 11(b), the semaphore release operation is started (S6), and then, B is decremented and the semaphore release operation is terminated (S7 and S8).
In this way, in the prior art data storage array system, the controller 1001xe2x80x2 controls access rights to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2 (system resources) by using semaphores in order to prevent excessive load from being applied to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2. 
(B) With recent advances in multimedia technology, continuous media data such as digitized moving image data, voice data, etc. have increasingly come to be stored on hard disks and other data storage devices (random access devices). Because of huge data sizes of continuous media data, it is becoming common to configure a plurality of random access devices into an array and make the array appear to the system as a single large capacity virtual device. To implement this, RAID (Redundant Array of Inexpensive Disks) technology, which improves reliability by managing data storage by providing redundancy to continuous media data stored in an array of random access devices, has been attracting attention.
The configuration and operation of a prior art data storage array system of RAID 3 will be described below. FIG. 25 is a diagram showing the configuration of a data storage array system of RAID 3 according to the prior art. FIGS. 26(a) and 26(b) are flow charts illustrating the operation of a controller 1 in the prior art data storage array system of RAID 3. FIG. 28 is a flow chart of semaphore acquisition and release operations according to the prior art.
As shown in FIG. 25, the prior art data storage array system of RAID 3 comprises the controller 1, data storage devices 21 to 2n and a redundancy calculator 3. The controller 1 receives a data access request issued by an external host device 4, converts it into internal access requests, issues them to the data storage devices 21 to 2n, and sends a completion notification to the external host device 4 when the internal data access requests to the data storage devices 21 to 2n are completed or when a timeout has occurred. The data storage devices 21 to 2n are devices for storing data. When the data access request issued by the external host device 4 is a write request, the redundancy calculator 3 generates redundant data using the write data from the external host device 4 before issuing the internal data access requests to the data storage devices 21 to 2n; on the other hand, when it is a read request, the redundancy calculator 3 restores write data using redundant data if the write data is lost because of the occurrence of a timeout. The external host device 4 is a device that issues data access requests.
Next, the operations performed by the controller 1 in response to an external data access request will be described in detail with reference to FIGS. 26(a) and 26(b). The following description is given based on the premise that the controller 1 is operating in a multi-threaded programming (multi-processing programming) environment.
The controller 1 waits for a data access request from the external host device 4 (S1). When a data access request is received from the external host device 4, the controller 1 generates a child thread to process the data access request (S2). The data storage array system can thus accept a plurality of data access requests simultaneously (command queuing). In the generated child thread, the data access request is converted into n internal data access requests (S3). In the case of RAID 3, the conversion to the internal data access requests (S3) is performed so that the access data designated by the data access request is divided across (nxe2x88x921) disks and the redundant data generated based on the access data is stored on the remaining one disk. FIG. 27 shows how the conversion to the internal data access requests is accomplished. After S3, the controller 1 examines whether the data access request received from the external host device 4 is a read request or a write request (S4).
If the data access request received from the external host device 4 is a write request, the controller 1, using the redundancy calculator 3, generates redundant data by duplicating the write data (S5). Next, the controller 1 acquires access rights to the data storage devices 21 to 2n by performing the semaphore acquisition operation (S6). The controller 1, which has acquired the access rights to the data storage devices 21 to 2n in S6, issues the internal data access requests to the data storage devices 21 to 2n (S7); then, after starting timer counting from the time the internal access requests to (nxe2x88x921) data storage devices are completed, when all the internal access requests are completed or a timeout error occurs (S8) the controller 1 performs the semaphore release operation (S9) to release the access rights acquired to the data storage devices 21 to 2n. Finally, the controller 1 issues a data access completion notification to the external host device 4 (S10) and terminates the child thread (S11).
On the other hand, if, in S4, the data access request received from the external host device 4 is a read request, the controller 1 acquires access rights to the data storage devices 21 to 2n by performing the semaphore acquisition operation (S12). The controller 1, which has acquired the access rights to the data storage devices 21 to 2n in S12, issues the internal data access requests to the data storage devices 21 to 2n (S13); then, after starting timer counting from the time the internal access requests to (nxe2x88x921) data storage devices have been completed, when all the internal access requests are completed or a timeout error occurs (S14) the controller 1 performs the semaphore release operation (S15) to release the access rights acquired to the data storage devices 21 to 2n. Next, the controller 1 determines whether a timeout error or a read error has occurred in S14 (S16). If a timeout error or a read error has occurred, the controller 1 restores the data lost due to the error by using the redundancy calculator 3 (S17). Finally, the controller 1 issues a data access completion notification to the external host device 4 (S10) and terminates the child thread (S11).
In the above-described operational flow, the controller 1 performs access control by using a synchronization mechanism called a semaphore, as in the case of Section (A) first described, in order to prevent excessive load from being applied to the data storage devices 21 to 2n, thereby preventing the resources from becoming unavailable for internal processing due to excessive external load.
Here, let A denote the maximum allowed number of simultaneous accesses to a system resource and B the maximum number of accesses currently being made to the system resource. Then, as shown in FIG. 28, the semaphore acquisition operation is started (S1), and if A greater than B, the semaphore is successfully acquired, granting the request for access the system resource, after which B is incremented and the semaphore acquisition operation is terminated (S2, S4, and S5). On the other hand, if Axe2x89xa6B, the semaphore acquisition operation waits until B becomes smaller than A (S3) Further, as shown in FIG. 28, the semaphore release operation is started (S6), and then, B is decremented and the semaphore release operation is terminated (S7 and S8).
In this way, in the prior art data storage array system of RAID 3, the controller 1 controls access rights to the data storage devices 21 to 2n as system resources by using semaphores in order to prevent excessive load from being applied to the data storage devices 21 to 2n. 
However, as can be seen from the explanation given in Section (A), when issuing data access requests simultaneously to a plurality of data storage devices (random access devices) such as hard disk drives and controlling them for synchronized operation, if data access requests to the plurality of data storage devices are placed in a command queue and remain in the queue, variations in data access time among the data storage devices will accumulate with time.
The inventor has concluded that the variations in data access time among the data storage devices occur mainly due to the following three factors.
(Factor 1) Even when the data storage devices are in factory-adjusted conditions (in normally operating conditions) variations occur in data access time because of the seek time, latency, alternate sector processing, retry processing, etc. that differ from device to device.
(Factor 2) The performance of the bus connecting between the controller 1001xe2x80x2 and the data storage devices and the bus priorities assigned to the respective storage devices contribute to causing variations in data access time among the data storage devices.
(Factor 3) As the performance of the mechanism and storage medium degrades due to the aging of each data storage device, the seek time, latency, alternate sector processing, retry processing, etc. increase, causing variations in data access time among the data storage devices.
While the phenomena described in (Factor 1) and (Factor 2) occur even in a normally operating data storage array system, the phenomenon described in (Factor 3) is a kind of phenomenon that may cause trouble in the future.
The following description is given dealing with the phenomenon described in (Factor 3).
As the operating hours of a data storage device increase, the storage medium degrades and the number of data access retries and the number of bad sectors tend to increase, increasing the data access time.
When handling continuous media data such as moving image or voice data, the access time of each data storage device must not exceed the time limit required of the continuous media data.
If the time limit is exceeded, a frame or frames will be dropped in the case of a moving image; therefore, the controller 1001xe2x80x2 must constantly monitor the data access time of each data storage device, and must immediately notify the external host device 1003xe2x80x2 when any one of the data storage devices is detected exhibiting a data access delay of more than a predetermined time (a timeout situation) with respect to the other normally operating data storage devices.
The timeout interval is an important factor that determines the data access response performance and failure prediction accuracy of the data storage array system, and if a shorter timeout interval can be set, the accuracy of the failure prediction performed based on the detection of the data access response can be enhanced.
However, since the variations in data access time accumulate because of the Factor 1 and Factor 2 even in the case of normally operating data storage devices, the timeout interval cannot be shortened.
The longer the timeout interval, the lower is the accuracy in detecting a data storage array system that is about to fail and thus exhibiting a delay in data access time, which is not desirable when storing continuous media data such as moving image data; after all, it is of utmost importance to solve the problem of data access delays resulting from the accumulation of the variations in data access time caused by the Factor 1 and Factor 2.
Referring to FIGS. 12(a) and 12(b), the data access delay Tdelay occurring as a result of the accumulation of the variations in data access time will be described in further detail below. FIGS. 12(a) and 12(b) are operational chart diagrams illustrating data write operations in the data storage array system. FIG. 12(b) is the continuation of FIG. 12(a), and the right-hand edge of part 12(a) indicates the state at the same instant of time as the left-hand edge of part 12(b).
Here, the external host device 1003xe2x80x2 issues a data access request in such a manner that a constant load will be maintained in the data storage array system; that is, the external host device 1003xe2x80x2 issues a data access request to the controller 1001xe2x80x2 only when the condition A greater than B is satisfied, where A is the maximum allowed number of simultaneous accesses to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2, and B is the number of data accesses currently being made to the data storage devices 1021xe2x80x2, . . . , 102nxe2x80x2. 
To simplify the explanation, A and n are both set to 3, and it is assumed that the data storage device 1022xe2x80x2 has a longer data access time than the other data storage devices 1021xe2x80x2 and 1023xe2x80x2. This delay in data access time is assumed to be within an allowable range as a data storage device.
As can be seen from FIG. 12, the external host device 1003xe2x80x2 (FIG. 13) issues a data access request the instant that the condition A greater than B is satisfied. Accordingly, at any instant in time, data access requests are being issued to the data storage devices 1021xe2x80x2, 1022xe2x80x2, 1023xe2x80x2, and the inventor has noticed that the delay in the data access time of the data storage device 1022xe2x80x2 accumulates with time.
More specifically, this data access time delay reaches a steady state partway through the process as shown in FIG. 12 and, in the steady state condition, the data access time delay Tdelay of the data storage device 1022xe2x80x2 is expressed as
Tdelay=Tdxc3x97Axe2x88x92Tnxe2x88x92Trxe2x88x92Tx
where Td is the data access time of the data storage device 1022xe2x80x2, Tn is the data access time of each of the data storage devices 1021xe2x80x2 and 1023xe2x80x2, Tr is the time at which the data access request is issued from the controller 1001xe2x80x2, and Tx is the data transfer time between the external host device 1003xe2x80x2 and the controller 1001xe2x80x2.
Accordingly, even when provisions are made not to apply excessive load to the data storage array system by using a semaphore, the data access time of the data storage array system increases because of the data access time delay Tdelay. As a result, the timeout interval in the data storage array system must be set equal to Tdelay at the shortest.
If the timeout interval is set shorter than Tdelay, a situation occurs where the data storage array system reports a timeout error to the external host device 1003xe2x80x2 when the data storage device 1022xe2x80x2 is operating normally. Conversely, if the timeout interval is set longer than Tdelay, then if any one of the other data storage devices 1021xe2x80x2 and 1023xe2x80x2 falls into a condition about to fail, causing a delay in the data access time, the faulty condition cannot be detected until after a timeout occurs; this, as a matter of course, results in degradation of the failure prediction performance and causes inconvenience in handling continuous media data.
On the other hand, as can be seen from the explanation given in Section (B), when it is desired to synchronize the operation among data storage devices (random access devices) such as hard disk drives as in the prior art data storage array system of RAID 3, if a situation continues where data access requests are incessantly issued to the data storage devices, variations in data access time among the data storage devices will accumulate with time. This is because variations are caused in the data access time due to such factors as the latency, alternate sector processing, and retry processing that differ from device to device. Even if the data access performance is the same among the data storage devices, since the performance of the bus connecting between the controller 1 and each data storage device differs, the variations in data access time among the data storage devices accumulate with time.
Consider, for example, the case where the data storage devices are connected to the controller 1 via a SCSI bus. In this case, the priority for the use of the SCSI bus is determined by the ID assigned to each data storage device such that the access time increases with decreasing priority, and this phenomenon causes variations in the access time among the data storage devices. Further, in the case of a conventional bus (such as a PCI bus) where each connected device has the same bus priority, variations in the data access time occur due to differences between the data transfer timing within each data storage device and the data transfer timing on the bus connected to it. Thus, variations in the data access time become a factor that hampers the synchronized operations of the plurality of data storage devices.
The feature that RAID offers when handling continuous media data such as moving image or voice data is that to ensure real time processing of continuous media data, the data to be output can be restored using redundancy if the last one data storage device does not respond within a predefined time interval (the timeout interval) after the data access requests to the (nxe2x88x921) data storage devices have been completed. The setting of the timeout value is very important in order to ensure the real time processing. It goes without saying that the shorter the real time interval can be set, the better result can be obtained. This is because in the case of a moving image, for example, the possibility of frame dropping increases as the timeout value increases.
The data access time delay Tdelay that increases the data access time as described above will be explained in more detail with reference to FIG. 29. FIG. 29 is an operational chart diagram illustrating data write operations in the prior art data storage array system of RAID 3; the lower part of the diagram is the continuation of the upper part, and the right-hand edge of the upper part of FIG. 29 indicates the state at the same instant of time as the lower part.
Here, the external host device 4 issues a data access request in such a manner that a constant load will be maintained in the data storage array system. That is, the external host device 4 issues a data access request to the controller 1 only when the condition A greater than B is satisfied, where A is the maximum allowed number of simultaneous accesses to the data storage devices 21 to 2n, and B is the number of data accesses currently being made to the data storage devices 21 to 2n. 
To simplify the explanation, A and n are both set to 3, and it is assumed that the data storage device 22 has a longer data access time than the other data storage devices 21 and 23. As can be seen from FIG. 29, the external host device 4 issues a data access request the instant that the condition A greater than B is satisfied. Accordingly, at any instant in time, data access requests are being issued to the data storage devices 21 to 23, and it is seen that the delay in the data access time of the data storage device 22 accumulates with time.
More specifically, this data access time delay reaches a steady state partway through the process as shown in FIG. 29 and, in the steady state condition, the data access time delay Tdelay of the data storage device 22 is expressed as
Tdelay=Tdxc3x97Axe2x88x92Tnxe2x88x92Trxe2x88x92Tx
where Tn is the data access time of each of the data storage devices 21 and 23, Td is the data access time of the data storage device 22, Tr is the time at which the data access request is issued from the controller 1, and Tx is the data transfer time between the external host device 4 and the controller 1.
Accordingly, even when provisions are made not to apply excessive load to the data storage array system by using a semaphore, the data access time of the data storage array system increases because of the data access time delay Tdelay, and synchronized operations of the plurality of data storage devices become difficult to implement. Furthermore, since the timeout value needs to be set equal to Tdelay at the shortest, the prior art data storage array system of RAID 3 is not suitable for handling continuous media data such as moving image data.
In view of the above-described problems of the prior art, it is an object of the present invention to provide a data processing control system capable of appropriately handling continuous media data, etc., and a controller, a data processing control method, a program, and a medium for use with such a data processing control system.
One aspect of the present invention is a data processing control system comprising a controller for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, wherein
said controller (1) sends every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number, and (3) when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, starts sending said queued instructions in sequence to said plurality of data processing devices, and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number.
Another aspect of the present invention is a data processing control system comprising a controller for receiving an instruction directing a data processing operation, and for causing said received to be executed across a plurality of data processing devices, wherein
said controller (1) detects a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed, (2) sends every received instruction to said plurality of data processing devices until said detected difference exceeds a prescribed limit, (3) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once said difference has exceeded said prescribed limit, (4) starts sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and (5) detects said difference again and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until said detected difference exceeds said prescribed limit.
Still another aspect of the present invention is a data processing control system comprising a controller for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, wherein
said controller (1) detects a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed, (2) sends every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number, (3) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number, and (4) when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, starts sending said queued instructions in sequence to said plurality of data processing devices, and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number, and wherein
said predetermined number is varied according to said detected difference.
Yet still another aspect of the present invention is data processing control system, wherein said data processing operation is a data read or data write operation.
Still yet another aspect of the present invention is data processing control system, wherein said data processing operation is a data write operation for writing data containing redundant data which is used to restore data based on successfully readout data when data cannot be read correctly on any one of said plurality of data processing devices.
A further aspect of the present invention is a data processing control system, wherein said data processing operation is a data read operation for reading data containing redundant data which is used to restore data based on successfully readout data when data cannot be read correctly on any one of said plurality of data processing devices.
A still further aspect of the present invention is a data processing control system, wherein said data processing operation is a data write operation for writing data redundantly so that data can be restored in case data cannot be read correctly on any one of said plurality of data processing devices, and wherein
said plurality of data processing devices are arranged in two or more pairs for writing data redundantly.
A yet further aspect of the present invention is a data processing control system, wherein when said difference is detected again, and the number of said queued or newly received instructions issued until said detected difference exceeds said prescribed limit becomes smaller than a predetermined threshold value, said controller determines that a data access delay error has occurred on one of said plurality of data processing devices.
A still yet further aspect of the present invention is a data processing control system, wherein when said predetermined number which is varied according to said detected difference becomes smaller than a predetermined threshold value, said controller determines that a data access delay error has occurred on one of said plurality of data processing devices.
An additional aspect of the present invention is a controller for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, wherein
said controller (1) sends every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number, and (3) when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, starts sending said queued instructions in sequence to said plurality of data processing devices, and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number.
A still additional aspect of the present invention is a controller for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, wherein
said controller (1) detects a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed, (2) sends every received instruction to said plurality of data processing devices until said detected difference exceeds a prescribed limit, (3) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once said difference has exceeded said prescribed limit, (4) starts sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and (5) detects said difference again and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until said detected difference exceeds said prescribed limit.
A yet additional aspect of the present invention is controller for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, wherein
said controller (1) detects a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed, (2) sends every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number, (3) does not send any received instructions to said plurality of data processing devices but holds said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number, and (4) when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, starts sending said queued instructions in sequence to said plurality of data processing devices, and continues to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number, and wherein
said predetermined number is varied according to said detected difference.
A still yet additional aspect of the present invention is a data processing control method for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, comprising the step of:
sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number;
not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number; and
starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number.
A supplementary aspect of the present invention is a data processing control method for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, comprising the steps of:
detecting a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed;
sending every received instruction to said plurality of data processing devices until said detected difference exceeds a prescribed limit;
not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once said difference has exceeded said prescribed limit;
starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof; and
detecting said difference again and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until said detected difference exceeds said prescribed limit.
A still supplementary aspect of the present invention is a data processing control method for receiving an instruction directing a data processing operation, and for causing said received instruction to be executed across a plurality of data processing devices, comprising the steps of:
detecting a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed;
sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number;
not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number;
starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number; and
varying said predetermined number according to said detected difference.
A yet supplementary aspect of the present invention is a program for causing a computer in the data processing control method to carry out all or part of the steps of: sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number; and starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number.
A still yet supplementary aspect of the present invention is a program for causing a computer in the data processing control method to carry out all or part of the steps of: detecting a difference in execution end timing of said instruction between designated two of said plural of data processing devices across which said instruction is executed; sending every received instruction to said plurality of data processing devices until said detected difference exceeds a prescribed limit; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once said difference has exceeded said prescribed limit; starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof; and detecting said difference again and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until said detected difference exceeds said prescribed limit.
Another aspect of the present invention is a program for causing a computer in the data processing control method to carry out all or part of the steps of: detecting a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed; sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number; starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number; and varying said predetermined number according to said detected difference.
Still another aspect of the present invention is a computer readable medium having a program recorded thereon for causing a computer in the data processing control method to carry out all or part of the steps of: sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number; and starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number.
Yet still another aspect of the present invention is computer readable medium having a program recorded thereon for causing a computer in the data processing control method to carry out all or part of the steps of: detecting a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed; sending every received instruction to said plurality of data processing devices until said detected difference exceeds a described limit; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once said difference has exceeded said prescribed limit; starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be execute by said plurality of data processing devices has become zero by completing the execution thereof; and detecting said difference again and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until said detected difference exceed said prescribed limit.
Still yet another aspect of the present invention is computer readable medium having a program recorded thereon for causing a computer in the data processing control method to carry out all or part of the steps of: detecting a difference in execution end timing of said instruction between designated two of said plurality of data processing devices across which said instruction is executed; sending every received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches a predetermined number; not sending any received instructions to said plurality of data processing devices but holding said received instructions in a queue once the number of instructions being executed or waiting to be executed by said plurality of data processing devices has reached said predetermined number; starting sending said queued instructions in sequence to said plurality of data processing devices when the number of instructions being executed or waiting to be executed by said plurality of data processing devices has become zero by completing the execution thereof, and continuing to send said queued instructions or every newly received instruction to said plurality of data processing devices until the number of instructions being executed or waiting to be executed by said plurality of data processing devices reaches said predetermined number; and varying said predetermined number according to said detected difference.