1. Field
The present invention generally relates to semiconductor integrated circuits and debug mode determination methods, and more particularly to a semiconductor integrated circuit which is configured to determine a debug mode of a microcontroller using power-ON reset and to a debug mode determination method.
2. Description of the Related Art
In an apparatus including an information processing unit such as a Central Processing Unit (CPU), typified by a microcontroller such as a Micro Control Unit (MCU), a debug system is generally used when developing a program which is to be operated by the CPU. The debug system supports the debugging by displaying various operation information of the program that is being developed, and providing specific operating functions with respect to the program that is being developed.
FIG. 1 is a block diagram showing an example of a structure of a debug system for a single-chip MCU. In FIG. 1, a MCU 1, which is a semiconductor integrated circuit, is connected to a host computer 3 via an external debug unit 2.
The MCU 1 includes a CPU 11, a debug circuit 12, a storage device 13, peripheral function parts (or blocks) 14 and 15, a power-ON reset circuit 16, a reset control circuit 17, and debug terminals (or mode terminals) 18 which are connected as shown in FIG. 1. The CPU 11, the storage device 13, and the peripheral function parts 14 and 15 are connected via a bus 19. The debug system is formed by at least the debug circuit 12 within the MCU 1 which is a debug target, the external debug unit 2, and the host computer 3.
The debug circuit 12 monitors and controls various operations and states of the CPU 11. The debug circuit 12 is connected to the external debug unit 2 which carries out various debug processes outside the MCU 1, via the debug terminals 18 and a dedicated (or exclusive) signal interface 41. The external debug unit 2 is connected, via a dedicated (or exclusive) signal interface 42, to the host computer 3 which executes a debugger software 31.
The debug terminals 18 for connecting the debug circuit 12 and the external debug unit 2 are subject to restrictions, and the debug terminals 18 cannot be used at times other than the time of the debugging or, the debugging of the debug terminals 18 cannot be made even if the debug terminals 18 are used at times other than the time of the debugging. For this reason, there is a demand to minimize the number of debug terminals 18. Particularly in a debug system which enables the debugging of a mass-produced MCU by providing a debug circuit in the mass-produced MCU, it is desirable that only a single debug terminal is provided.
When the number of debug terminals 18 is one, it is necessary to multiplex into one signal the necessary functions, such as a communication function between the external debug unit 2 and the debug circuit 12 and a debug mode control function of the debug circuit 12, which were realized by a plurality of debug terminals 18. A description will hereunder be given for a case where the communication function between the external debug unit 2 and the debug circuit 12 and the debug mode control function of the debug circuit 12, which are the minimum necessary functions necessary to realize the debug function, are multiplexed.
The communication function between the external debug unit 2 and the debug circuit 12 can be realized by making the debug terminal 18 function as a bidirectional terminal for half-duplex serial communication.
The debug mode control function of the debug circuit 12 determines a mode (debug valid mode) which permits the debugging of the MCU 1 and a mode (debug invalid mode) which prohibits the debugging of the MCU 1. The power-ON reset circuit 16 within the MCU 1 outputs a reset signal (hereinafter referred to as a power-ON reset signal) Por when the power-ON reset circuit 16 detects that the power is turned ON and/or a power supply voltage has decreased below a tolerable value (hereinafter referred to as a time when the power supply voltage decreased is detected). Hence, an input signal level at the debug terminal 18 is latched during a time when the power-ON reset signal Por is generated, and a mode selected by the latched signal level is judged. After the mode is determined, a user program is executed after the resetting of the MCU 1 is cancelled in the case of the debug invalid mode, and a debug program (or monitor program) dedicated to (or exclusively for) the debugging is executed after the resetting of the MCU 1 is cancelled in the case of the debug valid mode.
The use of the debug terminal 18 for the debug mode control is limited to the timings when the power is turned ON and the power supply voltage decrease is detected. At these timings, the MCU 1 is initialized, and for this reason, no communication is made between the external debug unit 2 and the debug circuit 12. Hence, the communication function between the external debug unit 2 and the debug circuit 12 and the debug mode control function of the debug circuit 12 do not interfere with each other.
FIG. 2 is a flow chart for explaining a process of the debug mode control. In FIG. 2, the power of the MCU 1 is turned ON in a step S1, and a step S2 decides whether or not a power-ON reset by the power-ON reset signal Por is generated. If the decision result in the step S2 is NO, a step S3 judges that the debug mode is indefinite, and the process ends.
If the decision result in the step S2 is YES, a step S4 decides whether or not the external debug unit 2 is connected to the MCU 1. If the decision result in the step S4 is NO, a step S5 sets an input signal to the debug terminal 18 to a high level when cancelling the power-ON reset, and a step S6 determines the mode to the debug invalid mode. The resetting of the MCU 1 is cancelled in a step S7, the CPU 11 executes the user program in a step S8, and the process ends.
If the decision result in the step S4 is YES, a step S9 sets the input signal to the debug terminal 18 to a low level when cancelling the power-ON reset, and a step S10 determines the mode to the debug valid mode. The resetting of the MCU 1 is cancelled in a step S11, and the CPU 11 executes the monitor program for realizing the debug function in a step S12. In addition, a step S13 makes a communication with the external debug unit 2 via the debug terminal 18, and the process ends.
FIG. 3 is a circuit diagram showing an example of a conventional debug circuit. In addition, FIGS. 4 through 6 respectively are time charts showing timings of the debug mode control for a case where a debug circuit 12A shown in FIG. 3 is used as the debug circuit 12 shown in FIG. 1. FIG. 4 is a time chart for explaining a case where the debug invalid mode is specified, FIG. 5 is a time chart for explaining a case where the debug valid mode is specified, and FIG. 6 is a time chart for explaining a case where the power-ON reset is not generated in a normal manner. In FIGS. 4 through 6, VCC denotes the power supply voltage of the MCU 1, Por denotes the power-ON reset signal output from the power-ON reset circuit 16, Pdt denotes a debug signal which is input to the debug terminal 18 and specifies the debug mode of the MCU 1, and Pdm denotes a debug mode signal which is output from the debug circuit 12 and shifts the mode of the MCU 1 to the debug mode. In FIGS. 4 through 6, the ordinate indicates the signal level in arbitrary units, and the abscissa indicates the time in arbitrary units.
The debug circuit 12A shown in FIG. 3 includes a communication function block 211, and a debug mode control circuit 212 which has a data latch circuit 213. The data latch circuit 213 is formed by a delay latch (D-latch). The communication function block 211 realizes the above described communication function between the external debug unit 2 and the debug circuit 12A, and a communication function block having a known structure may be used for this communication function block 211. The debug terminal 18 is connected to the power supply voltage VCC via pull-up resistor 19. The debug signal Pdt which is input to the debug terminal 18 during an active time of the power-ON reset signal Por is latched by the data latch circuit 213, and the latched value is output as the debug mode signal Pdm. In this example, the debug mode signal Pdm assumes a low level as shown in FIG. 4 and indicates the debug invalid mode when the input signal level at the debug terminal 18 is high at the time of the power-ON reset, and the debug mode signal Pdm assumes a high level as shown in FIG. 5 and indicates the debug valid mode when the input signal level at the debug terminal 18 is low at the time of the power-ON reset. Accordingly, when the external debug unit 2 is not connected to the MCU 1, the input signal level at the debug terminal 18 becomes high at the time of the power-ON reset, and the debug mode signal Pdm always assumes a low level to indicate the debug invalid mode. When the external debug unit 2 is connected to the MCU 1, the external debug unit 2 monitors the power supply of the MCU 1, and inputs a low-level signal to the debug terminal 18 of the MCU 1 for a predetermined time from a time when the power is turned ON (that is, from a time when the power-ON reset is generated). Consequently, in the debug circuit 12A, the debug mode signal Pdm assumes a high level to indicate the debug valid mode.
Therefore, the power-ON reset signal Por, which is output from the power-ON reset circuit 16 when the power is turned ON and the power supply voltage decrease is detected, is used when determining the debug mode. However, as shown in FIG. 6, this power-ON reset signal Por may not be generated in a case where the power supply voltage VCC rises very slowly or gradually. In such a case, the latch gate of the data latch circuit 213 shown in FIG. 3 which receives the power-ON reset signal Por will not become active, and the debug mode signal Pdm output from the data latch circuit 213 will become indefinite. As a result, there is a possibility that the MCU 1 will be started in the debug mode that is not intended.
The reset control circuit 17 outputs a reset signal Rst which resets the MCU 1 based on the power-ON reset signal Por.
Among other things, a Japanese Laid-Open Patent Application No. 59-146352 proposes a single-chip microcontroller having a normal mode and a debug mode.
Conventionally, if the external debug unit is not connected to the MCU which is provided in an apparatus, for example, the debug invalid mode is anticipated for the debug mode when no power-ON reset is generated, but there is a possibility that the debug valid mode will occur. On the other hand, when the external debug unit is connected to the MCU, the debug valid mode is anticipated for the debug mode, but there is a possibility that the debug invalid mode will occur.
When the MCU is provided in an apparatus, such as a product, and is operated, the MCU must operate in the debug invalid mode. However, according to the conventional debug mode control, there is a possibility that the debug valid mode will occur if the power-ON reset is not generated when the power is turned ON. If the MCU provided in the apparatus assumes the debug valid mode which is not intended, the MCU operates in the mode which is not intended by the apparatus and may cause considerable effects on the operation of the apparatus. As a countermeasure, it is conceivable to resume the mode from the debug valid mode which is not intended, but this would require detection of a mode abnormal state of the MCU and turning ON the power of the MCU again. However, the structure of the apparatus would become complex and the cost of the apparatus would increase if a mechanism for realizing such a countermeasure were to be implemented in the apparatus. For this reason, it is essential to avoid the mode becoming the debug valid mode in the case where the debug invalid mode is specified.
Therefore, when no power-ON reset is generated, it was conventionally difficult to appropriately determine the debug mode.