High resolution and narrow bezel have become development trends of a flat panel display technology, and a gate driving circuit integrated into a display panel is a most important solution for realizing display of high resolution and narrow bezel.
The gate driving circuit is formed by cascading multi-stage shift registers sequentially. FIG. 1 is a circuit diagram of a shift register in prior art, and the shift register includes: a trigger transistor T100, a reset transistor T200, a first pull-up transistor T300, a second pull-up transistor T400, a bootstrap capacitor C100 and a pull-down module. The first pull-up transistor T300 is used for pulling up a signal output by an output terminal of the shift register, and the second pull-up transistor T400 is used for pulling up a signal output by a transmission signal output terminal of the shift register. The transmission signal output terminal of the shift register is a cascading terminal for cascading the shift register of a present stage with a shift register of a previous stage and a shift register of a next stage. A first node PU1 is a connecting point between the bootstrap capacitor C100 and a gate electrode of the second pull-up transistor T400. A STV is a start signal input by a start signal terminal connected with a gate electrode of the trigger transistor T100; a RESET is a reset signal input by a reset signal terminal connected with a gate electrode of the reset transistor T200; a CLK is a clock signal input by a clock signal terminal connected with a drain electrode of the second pull-up transistor T400; an OUTPUT is a signal output by an output terminal of the shift register; a VZ is a transmission signal output by the transmission signal output terminal of the shift register; a VGH denotes a voltage of high level; and a VGL denotes a voltage of low level.
As shown in FIG. 2, at a pull-up stage of the shift register, with the STV being at high level (the RESET is at low level) and the trigger transistor T100 being turned on, the bootstrap capacitor C100 is charged by the VGH, and a voltage of the first node PU1 is pulled up to high level; and with the second pull-up transistor T400 being turned on and the CLK being at high level, a signal output by the transmission signal output terminal of the shift register is pulled up, so that a transmission signal of high level is output by the transmission signal output terminal of the shift register. At a pull-down stage of the shift register, with the RESET being at high level (the STV is at low level), high level of the first node PU1 is pulled down to low level by the pull-down module, while the transmission signal output by the transmission signal output terminal of the shift register is pulled down from high level to low level.
In the pull-down stage of the shift register, the voltage of the first node PU1 jumps, that is jumping from high level to low level. A coupling effect of the bootstrap capacitor C100 may directly cause the transmission signal VZ output by the transmission signal output terminal of the shift register to generate a sharp spine, seriously affecting stability of shift transmission of the shift register. Noises of the shift register circuit may be increased by reducing the stability of the shift transmission of the shift register, so that stability of signal output by the output terminal of the shift register is affected.