The present invention relates to a semiconductor memory device; and, more particularly, to a device for improving a speed margin at an operating voltage of the memory device.
In general, a memory device carries out a burn-in test by applying a power supply voltage higher than an operating power supply voltage in order to perform a stress test. At this time, the operations such as read, write and so on are done by applying a power supply voltage higher than an operating power supply voltage, and will be described below.
FIG. 1 is a circuit diagram for explaining read/write operations in a conventional memory device.
As shown in the drawing, a write enable signal bwen is generated by combining a pulse signal byprep and a discrimination signal wt_rdb by a NAND gate NA11 and an inverter I11. And, a read enable signal isotb is produced by combining the pulse signal byprep and an inverted signal of the discrimination signal wt_rdb done by an inverter I12 by a NAND gate NA12 and an inverter I13. That is, the write enable signal bwen is generated in the section where both the pulse signal byprep and the discrimination signal wt_rdb are a logic high level and the read enable signal isotb is created in the section where the signal byprep is a logic high level and the discrimination signal wt_rdb is a logic low level.
Here, the pulse signal byprep is the one that is generated when an external command for read/write operations is inputted, and is used to issue Yi (column selection signal) in the operation of the memory device, to create the read enable signal isotb in the read operation, and to create the write enable signal bwen in the write operation.
In addition, the discrimination signal wt_rdb is to discriminate between the read operation and the write operation. As mentioned above, the write enable signal bwen is generated when the discrimination signal wt_rdb is a logic high level and the read enable signal isotb is created when it is a logic low level.
The write enable signal bwen generated by combining the pulse signal byprep and the discrimination signal wt_rdb is delayed by a delay circuit 110 and applied to a write driver 130 which performs a write operation of the memory device in response to the write enable signal bwen. That is, data on a global input/output line GIO are carried on a local input/output line LIO.
Further, the read enable signal isotb created by combining the pulse signal byprep and the discrimination signal wt_rdb is delayed by a delay circuit 120 and applied to an input/output sense amplifier (IOSA) 140 which performs a read operation of the memory device in response to the read enable signal isotb. That is, the data on the local input/output line LIO is brought on the global input/output line GIO.
The write enable signal bwen and the read enable signal isotb generated by the pulse signal byprep and the discrimination signal wt_rdb are provided through the delay circuits 110 and 120, and are delayed without using a capacitor or resistor because these signals are all pulse signals. Therefore, the delay circuits 110 and 120 through which those signals are passed employ an inverter chain with inverters coupled in series.
The global input/output line GIO generally has a large metal line loading which enables a delay.
The delay circuits 110 and 120 with the inverter chain, through which the pulse signals are passed, have delay values that change depending on a variation of a power supply voltage. However, the global input/output line GIO with metal line loading has a delay value which does not almost vary even if the power supply voltage is varied.
When the write/read operations of the memory device are tested with a voltage much higher than the operating voltage as in the burn-in test, the delay values of the delay circuits 110 and 120 are highly decreased and the delay value of the global input/output line GIO does not almost vary. Thus, in case the delay values of the pulse signals are set in conformity with the operating voltage, the delay values of the signals are not correct in the burn-in test mode, thereby causing a failure in the write/read operations.
In order to solve the above problems, the conventional memory device sets delay values in conformity with the voltage in the burn-in test, which is higher than the operating voltage. In other words, more delay values than necessary are set because of the operation at the high voltage as in the burn-in test, thereby leading to a loss of speed margin in the general operation.