1. Field of the Invention
The present invention relates to a technology for testing a semiconductor memory which requires periodic refresh operations to retain data written in its memory cells. In particular, the present invention relates to a technology for testing a semiconductor memory which performs refresh operations automatically inside itself without requiring refresh commands from the exterior.
2. Description of the Related Art
Recently, mobile devices such as a cellular phone have been sophisticated in service facilities, with ever-increasing amounts of data to be handled. Then, work memories to be mounted on the mobile devices require larger capacities accordingly.
Conventionally, the work memories of the mobile devices have used SRAMs which are easy to configure a system with. SRAMs are, however, greater than DRAMs in the number of devices for constituting each single bit of cell, and thus are disadvantageous for larger capacities. On this account, semiconductor memories which have DRAM memory cells and perform refresh operations on the memory cells automatically inside to operate as SRAMs have been developed (pseudo SRAMs).
In the semiconductor memories of this type, the refresh operation time for performing a single refresh operation is included in the read cycle time or write cycle time. Specifically, the first half of a cycle time is allocated for the refresh operation time. The actual read operation or write operation is performed in the second half of the cycle time. Thus, the systems (users) on which the semiconductor memories are mounted need not be aware of the refresh operations in the semiconductor memories. That is, the users can use these semiconductor memories as SRAMs.
Moreover, in the semiconductor memories of this type, the refresh operation time is rendered shorter than the read operation time for the sake of reduced cycle times, as disclosed in Japanese Examined Patent Application Publication No. Hei 7-58589. Specifically, the time for selecting word lines in refresh operation is shorter than the time for selecting the word lines in read operation.
As mentioned above, pseudo SRAMs perform refresh operations automatically without being recognized from the exterior. Meanwhile, data retained in the memory cells might be corrupted if refresh operations are performed improperly. It is therefore necessary to evaluate that refresh operations are performed properly. In particular, detailed evaluations are required of the circuit operation when a conflict occurs between a request for a read operation or write operation which is supplied from the exterior and a request for a refresh operation which occurs inside the chip.