When conducting hierarchical design and physical development of ICs, circuit designers often face the problem of having voluminous smaller designs at various levels of the IC topological design hierarchy. When a layout designer needs to trace signal paths, which traverse numerous design hierarchies within the same design window for various levels of the IC topological design hierarchy, the designer/user usually has to select a menu item and verify that they wish to descend, i.e., scroll through, one level in the hierarchy. Furthermore, while attempting to debug the IC and/or edit circuit schematics that traverse numerous design hierarchies within the same design window, all the viewable hierarchical design levels distract and may confuse the circuit designer conducting the editing process involving only a few targeted hierarchical levels. Such electronic design automation tools fail to offer an easy interface to allow the user to traverse, debug and edit schematics involving multiple levels of design hierarchies.
Therefore, the need exists for a hierarchical design navigation method and a navigation apparatus for use in debugging layout induced electrical characteristics and layout-to-schematic verification (LVS) violations, as well as editing and other schematic modifications that are typical for those of ordinary skill in the art.
An additional need exists for a convenient design hierarchy method and device, which can save time and effort in viewing, editing and modifying design elements.
Furthermore, the need exists for a scroll mechanism to traverse through schematic hierarchical levels of design, giving circuit designers/users control over traversing a definable viewable scope at different levels of design hierarchy up and down quickly and smoothly, which in turn will aid the debugging and editing processes.