1. Field of the Invention
The method and apparatus of the present invention generally relates to an architecture for distributing a control store memory used to control a programmable device and, more particularly, to a control store memory architecture of a microprogrammed electronic data processing system in which multiple subunits have their own local control store memories.
2. Description of the Prior Art
It is common practice today to implement data processing systems in which the software instruction is executed by use of microprocessors which are firmware controlled. In this type of system, the firmware is stored as a series of microinstructions in a memory referred to as a control store. The control store may be a random access memory (RAM) which can be written into, as well as read from, or it may be a read only memory (ROM) of one type or another. A control store memory of the read only type is often referred to as read only storage as ROS. The use of firmware is increasing with more of the logic of systems being microprogammable.
Today, it is common to find in electronic data processing systems a central peripheral that is microprogram controlled as well as various peripheral controllers, each of which may be microprogram controlled. In such systems, the control store of the central processing unit (CPU) is controlled and addressed by logic located within the central processor and the control stores associated with each of the peripheral controllers are controlled and addressed by logic contained within each of the peripheral controllers. A more recent development is to have multiple subunits within a unit controlled by one or more control store memories. One such system is shown in FIG. 1 in which the CPU is composed of microprocessor 1, commercial instruction processor 3, microprocessor ROS 9, and commercial instruction processor ROS 11. The central processor communicates to main bus 27 via lines 46. Main bus 27 is comprised of address, data and cotnrol lines which are used by the various units to transfer information among them. Main memory 29 communicates to main bus 27 by lines 48 and is used to store software program instructions and data to be used by the central processing unit. Peripherals 31 and 33 communicate via lines 50 and 52, respectively, to main bus 27 and are used to input, output and store date within the electronic data processing system.
In the CPU of this system, the commercial instruction processor (CIP) 3 works in parallel with microprocessor 1. Microprocessor 1 is responsible for performing binary arithmetic and logic operations within the central processor. It is also the master subunit responsible for controlling which microinstruction will be read from the control store comprised of microprocessor ROS 9 and CIP ROS 11. The next address generation logic 67 in microprocessor 1 generates an address which is output on lines 12 to ROS address register 19. This address is latched into ROS address register 19 at the appropriate time during the execution of a microinstruction with the output of ROS address register 19 being a 12-bit address, signal ROSADDR, on lines 2 which is used to address microprocessor ROS 9 and commercial instruction processor ROS 11. This 12 bits of address are indicated by the number 12 next to the diagonal slash on line 2. The 12-bit ROS address can address any one of the 4K (1K=1024) 48-bit word microinstructions in microprocessor ROS 9 and any of the 2K 8-bit microinstructions in CIP ROS 11. If the address is between 0 and 2047, a 48-bit microinstruction word is read from microprocessor ROS 9 with all 48 s going to ROS data register 53 of microprocessor 1 with 35 bits being signal MPROSDT on lines 4 and 13 bits being signal CMROSDT on lines 8. The 13 bits signal CMROSDT on lines 8 also go to ROS data register 55 of commercial instruction processor 3. If the 12-bit ROS address specifies an address between 2048 and 4095, a 56-bit microinstruction is read from the control store memory with 48 bits coming from microprocessor ROS 9 and 8 bits coming from CIP ROS 11. In this case, the 35 bits of signal MPROSDT on lines 4 go to ROS data register 53, the 13 bits of signal CMROSDT on lines 8 go to ROS data register 53 and ROS data register 55 and the 8 bits of signal CIPROSDT on lines 6 go to ROS data register 55.
After the microinstruction is read out and becomes available to microprocessor 1 from ROS data register 53, some of the bits within the microinstruction word are used to determine the address of the next microinstruction to be read from the control store. These bits are transferred to next address generation logic 67 on lines 10. In addition, there are 4 bits from indicator register 61 of commercial instruction processor 3 which are transferred to next address generation logic 67 on line 60. These 4 bits on line 60 from indicator register 61 enter the computation of the next control store address if the microinstruction being processed by microprocessor 1 contains a microoperation specifying that a major branch is to be done based upon the conditions of the four bits from indicator 61. Through this mechanism, the microinstruction programmer has the ability to take into account various conditions rising within commercial instruction processor 3 by programming branch on indicators microoperations within the microinstructions stored in microprocessor ROS 9. The ability to control the flow of microinstructions by controlling the generation of the next microinstruction address can be seen in the firmware flow chart of FIG. 2.
In FIG. 2, block A contains a microinstruction MP1 which performs an operation within microprocessor 1. Block A contains no microoperations to be performed by commercial instruction processor 3. In block B, microoperation MP2 is programmed to be performed by microprocessor 1 and CIP2 is programmed to be performed by commercial instruction processor 3. In block C, microprocessor 1 executes microoperation MP3 and commercial instruction processor 3 executes microoperation CIP3. Within microoperation MP3, a branch on indicators is programmed. If the branch is taken because the tested indicators are set, the microinstruction corresponding to block H is read from the control store and the microoperation MP6 is executed by microprocessor 1 and CIP6 is executed by commercial instruction processor 3. Block I is then performed executing microinstruction MP7 in microprocessor 1 and CIP7 in commercial instruction processor 3. Microoperation MP7 contains within it a branch to block F so that the next microinstruction is read from location F of the control store which contains microoperations MP8 and CIP8. If the microinstruction in block C did not take the branch because the indicator conditions were not set, block D would be read and microoperation MP4 would be executed by microprocessor 1 and CIP4 would be executed by commercial instruction processor 3. Block E would then be read and microoperation MP5 would be executed by microprocessor 1 and microoperation CIP5 by commercial instruction processor 3. At this point, the microprogram returns to the main path and block F would be executed with microoperations MP8 being performed by microprocessor 1 and CIP8 being performed by commercial instruction processor 3. Block G would then be entered with microprocessor 1 performing microoperation MP9 and the commercial instruction processor 3 perfroming a no operation. A more detailed discussion of the operation of the central processor illustrated in FIG. 1 and the method of executing a microprogram illustrated in FIG. 2 can be found in U.S. patent application Ser. No. 537,991 now U.S. Pat. No. 4,608,659 entitled, "A Commercial Instruction Processor for Performing Decimal Arithmetic Operations" having inventors John J. Bradley, Theodore R. Staplin, Jr., Ming T. Miu, Thomas C. O'Brien, George M. O'Har, Melinda A. Widen and Brain L. Stoffers.
Although the above system works quite well in that it allows subunits within a unit to be controlled by a common control store, it has the disadvantage that the number of subunits within the system must be predetermined because the next address generation logic is designed to handle a predetermined number of external conditions and the microoperations which control the unit containing the next address generation logic must also be predetermined in order to be able to branch on these various external conditions. It has the further disadvantage that a programmer writing the firmware for the unit must be aware when a condition can arise in any one of the subunits and must program test branches within the firmware in order to test for the existence of the condition within the microprogram. In addition, the test branches within a microprogram may also lengthen the microprogram and cause it to be executed more slowly than would otherwise be the case if the microprogram did not have to test for external conditions in other subunits.
If the master subunit controlling the generation of the control store address is a signal integrated circuit, or if the next address generation logic of the master subunit controlling the addressing of the control store is a single integrated circuit, it may be impossible to accommodate the addition of other subunits within the system which may cause external conditions which need to be tested by the master subunit in order to access that portion of the microprogram written to respond to the external condition.
Therefore, what is needed is an architecture which permits microprogrammed subunits to be easily added to a unit without having to change logic within the master subunit controlling the generation of the control store address.