Oversampling analog-to-digital converters (ADC) generally consists of two parts, an analog modulator and a digital filter. The first part, the analog modulator, receives an analog signal and produces a serial data stream having a bit rate which is much greater than the Nyquist sampling frequency. The quantization noise of the analog modulator is shaped to minimize the noise in the passband of interest, at the expense of higher noise outside of this passband. This is as opposed to distributing the noise evenly between DC and the modulator sampling frequency. The digital filter portion of the ADC is operable to filter and decimate the modulator output to a lower frequency, higher resolution digital representation of the analog input. Since the modulator quantization noise is shaped, the digital filter must filter this out-of-band quantization noise and reduce the output word frequency to twice the effective Nyquist frequency. Decimation is a well-known technique that is utilized in most oversampling ADCs.
In some applications utilizing decimation, the output sampling rate must be set at one of a plurality of sampling rates. In order to provide for these different sampling rates, an ADC needs to have the ability to select one of a plurality of decimation rates to provide the selected output sampling rate. This must either be done by providing a plurality of ADCs with fixed and separate decimation rates or to perform some control of the digital filter to effect a variable decimation rate architecture.
Conventional digital filters in ADCs utilize some form of digital signal processor utilizing multiple stages of digital filtering. These stages of digital filtering typically utilize a finite impulse response (FIR) filter topology which requires at minimum a multiplier and an accumulator and stored filter coefficients that define the transfer function of the filter. The data is processed with the multiplier and accumulator utilizing the stored filter coefficients. Each set of filter coefficients is designed to provide a specific decimation rate and filter transfer function. In order to provide a variable decimation rate, it is necessary to process data through multiple filter stages with the number of filter stages varied. With conventional digital filter processors with unlimited processing power, select filter topologies and the order thereof can be realized. However, an ADC that is incorporated into an integrated circuit has limited silicon real estate available and, therefore, incorporating the full power of a digital signal processor is not feasible. Typically, oversampling ADCs have utilized a fixed decimation architecture to realize a desired filter transfer function.