The present invention relates to the formation of metallized, high aspect ratio vias, in which the diameter of at least one of two ends of a via is preferably flared, the ends being connected by side walls therebetween. More particularly, the present invention relates to high aspect ratio plated conductive vias which are fabricated in the semiconductor substrate of a multichip module (MCM) or packaging structure. Other applications include, but are not limited to, micro-electro-mechanical systems (MEMs); micro-opto-electro-mechanical systems (MOEMs); RF MEMs; BioMEMs; lab-on-chip (LOC) and other sensors; and membranes.
Much work has been done in the integrated circuit (IC) art to address reliability problems in metallized vias attributed to poor metal coverage of via side walls, lower step coverage at angularities such as at via and wiring level intersections, metal flaking at stress points, and incomplete fill of metal within the via. Stresses caused by such irregularities contribute to electromigration problems, increased resistivity of the via, ultimately the electrical failure of the device and difficulty in obtaining reproducibly acceptable vias within a chip and from batch to batch.
Work directed at solving via fill and coverage problems has generally related to interlevel vias, i.e. conductive vias formed through a dielectric layer and providing an electrical connection between conductive levels of an IC structure, or to vias providing an electrical connection between conductive levels and devices which are either mounted or buried in the semiconductor substrate. Generally, the via metallization has comprised dry deposited aluminum, including aluminum which includes a fractional percent of copper, silicon or tin, or tungsten or a titanium-tungsten alloy. It would be desirable to use pure or nearly pure copper instead, since the choice of copper would provide lower resistivity. Resistivity limits signal speed.
It has long been recognized that sloping the via walls might resolve the problem of via failure due to inadequate fill and coverage within the via, as the conductor metal would be deposited over a smoother surface more available to the anisotropic, i.e. essentially vertical, dry deposition of metal within the vias. However, as the diameter of interlevel vias in ICs approach one micron (μm) or less and aspect ratios approach 1 or more, sloping alone does not provide consistently satisfactory coverage. In addition, since sloping involves widening at the via opening, it uses up valuable real estate and increases the pitch (i.e. distance between the center of one via and the nearest edge of the neighboring via).
Numerous structures and processes have been proposed in the art for fabricating interlevel slope-walled conductive vias in integrated circuit structures. Some of the approaches to solving the via coverage problem by sloping have included altering the dielectric material through which the vias are etched (e.g. U.S. Pat. Nos. 5,308,415; 4,830,706), altering the temperature of the etch reaction (e.g. U.S. Pat. Nos. 3,986,912; 6,171,964), altering the state, selecting layer materials of particular composition and relative thickness (e.g. U.S. Pat. Nos. 4,624,740; 4,487,652), altering composition or composition ratio of the etchant (e.g. U.S. Pat. Nos. 5,354,386; 4,814,041), perhaps in stages throughout the etch (e.g. U.S. Pat. Nos. 4,814,041; 5,746,884; 5,841,196; 4,902,377; 5,354,386), etching through an insulator (e.g. U.S. Pat. Nos. 5,162,261; 5,308,929), or by manipulating the position of the mask through which the via is exposed, or by first depositing in the via to fill up to 40% of the diameter a refractory metal that provides better subsequent coverage for the dry deposited aluminum, copper, etc. (U.S. Pat. No. 6,171,964 B1).
Techniques in the art are described generally as producing sloping at an angle chosen between 45° and 70° to the lateral. Some slopes are continuous from top to bottom of the via; some are located only at the via opening. Vias are filled with a wide variety of materials which are inserted in many ways into vias of many dimensions. Vias may be mechanically drilled, dry and/or wet etched, or laser drilled (e.g. U.S. Pat. Nos. 6,433,301; 6,400,172 B1). For example the '172 patent describes using laser drilling to shape slopes at either or both ends of through-vias in a substrate such as silicon for test purposes. Slope openings are 10 μm wide or more. The vias are filled with a variety of metals and alloys or conductive polymer, and dry deposited or electrolessly plated. The '301 patent describes laser-shaped blind and through-vias having diameters of 5 to 300 μM formed through at least two types of layers, e.g. copper and organic dielectric, in a package or MCM.
In U.S. Pat. No. 6,506,332 B2 it is stated that the industry struggles to fill 6:1 aspect ratio (depth:diameter) vias, and describes filling, with paste under pressure, vias of aspect ratios between 1:1 and 17:1, in which vias can be as narrow as between 2 and 25 thousandths of an inch. Since this range of via diameter converts to 3 to 38 μm, the depth would be 3 to 646 μm for that range of aspect ratio. The filling is a fail-safe performed after brief plating to compensate for the plating discontinuities taken for granted to be present at high aspect ratios. In the present invention, a method is provided to obtain deep via, voidless metallization coverage and fill.
Sloped interlevel vias have become viewed as less desirable as IC features have become smaller and denser, and slope width uses up valuable real estate. U.S. Pat. No. 5,292,558 describes a way of avoiding or reducing sloped walls in vias of one μm or less by wetting the unfilled interior of a via with an adherent, optionally photosensitive, hydrophilic polymer-polyoxometalate solution to improve coverage in the subsequent deposition of metal, including copper and, even in steep walled vias. It is stated therein that producing noble interconnection film using organic ligand-bound metal atoms and ions by selective heating is known, but that the method described therein has the advantage of not requiring as high a temperature and of being able to foster the deposition of a prime coat, preferably of Mo or W, which have the added advantage of acting as a diffusion barrier between silicon and the metal fill. In the present invention fluted vias are acceptable because real estate is not as critical a consideration.
A number of organo-halide plasma etchants are known. For example, U.S. Pat. No. 5,501,893 describes steps of anisotropic etching of silicon through a mask using a plasma mix of sulfur hexafluoride (SF2) and argon, which removes polymer, alternating with a polymerization etch stop step using a plasma mix of trifluoromethane (CHF3) and argon, the silicon in this exothermic process being cooled in helium or by adhesion to silicon electrodes. The alternation of etch and polymerization steps is stated to produce vertical vias. Although the temperature is not specified in the '893 patent, the Bosch process described therein is used at substrate temperature at or about room temperature.
While the present invention involves filled via fabrication, it is directed to deep, or ultradeep, vias preferably in or through silicon-containing material, such as comprises semiconducting substrates, rather than to interlevel vias formed through dielectric layers to connect conductive lines within the multilevel superstructure. The present invention involves etching and polymerizing under cooling, the goal of which is to create deep vias that have voidless plating coverage and fill. The vias of the present invention allow for electrical and/or thermal contact to the power chip through the package. An alternative would be to thin the wafer and create shallow vias that can be metallized for interconnection. However, thinned wafers are difficult to handle (break easily). In using deep vias, i.e. about or above 100 μm thick, the package, being thicker, is more mechanically stable for ease of handling.
Following the fabrication of deep vias, the issue becomes how to metallize the deep via. It was originally expected that electroplating would be rather straightforward, based on experience in metallizing much smaller vias having about 1 μm diameter and about 6 μm depth. However, enormous difficulty was unexpectedly encountered at first in filling the deep vias, and void-free continuous plating of the deep vias was not achieved by means used to plate the shallower vias.
In the present invention, deep high aspect ratio filled vias are fabricated in a material including, but not limited to, silicon; silicon monoxide; silicon dioxide; silicon nitride; polysilicon; quartz; glass; silicates; silicon germanium; and gallium arsenide. Presumably, the fabrication process would be applicable to any material susceptible to the etchant. The option of fabricating vias having only straight walls is selected should ease of achieving conservation of surface real estate be desired more under the circumstances than assurance of total plating coverage and fill. The option of fabricating vias having fluted walls, i.e. walls sloped at at least one via opening, is selected when ease of achieving total plating coverage and fill is desired more under the circumstances than is conservation of surface real estate. The flared-opening fluted vias are generally easier to fill completely.
Fluted walls are provided in a controlled fashion using a fluoride-containing etchant, and are reproducible within less than about 5% variation, usually within about 1–2%, from wafer to wafer and from center to edge. Whereas angles of slope described in the art were preferred to be between about 45 and about 70 degrees, voidless filled vias and complete wall coverage is obtained in the present invention in a via having a slope angled as low as about 3° to the vertical axis (i.e. about 87° to lateral) in vias having an aspect ratio of greater than about 2 and as high as about 35.
Despite the work reported in the field of via fabrication, the need remains for the unique combination of elements and processes set forth in the present invention.