This invention relates to the use of compact trench resistor structures in conjunction with MOS and bipolar transistors and logic inverters to achieve static random access memories and logic elements which are more compact than hitherto possible.
In recent years, the drive towards higher density integrated circuits resulted in the development of trench structures to improve device density. Trenches are regions in the silicon which are etched vertically downwards several microns deep into the silicon wafer, using anisotropic reactive ion etching (RIE). The two major applications widely reported for this technique are for use as charge storage capacitors in dynamic random access memory (DRAM) cells, and for device isolation in advanced CMOS, bipolar, and BICMOS technologies.
The prior art trench DRAM cell 100 (FIG. 1) includes an access transistor consisting of gate 101 which is part of a word line, drain 102 which is part of a bit line, storage node 103, and trench capacitor 106 which is electrically connected to storage node 103. Trench capacitor 106 consists of a deep trench etched into the silicon surface with essentially vertical walls 104, diffused silicon region 103a serving as the first electrode of trench capacitor 106, dielectric insulation layer 105, and polycrystalline silicon field plate 108 serving as the second electrode of the trench capacitor. The storage capacitance of trench capacitor 106 can be increased by making the trench deeper. Oxide isolation regions 107, 109 are used to isolate cell 100 from adjacent cells and trenches in a memory array.
There are several other variations of the use of the trench structure for high density DRAM cells. A good review article of the various DRAM cells previously proposed is provided by Chatterje et al., "Trench and Compact Structures for DRAMs", Technical Digest of IEEE International Electron Devices Meeting, December 1986, p. 128.
The second use proposed for trench structures is for electrical isolation between adjacent transistors in high density CMOS or bipolar circuits. Trenches one to two microns wide and several microns deep are etched into the silicon along the periphery of active regions, thereby separating adjacent transistors. These trenches are filled with dielectric isolation material (usually chemical vapor deposition of SiO.sub.2, capped by undoped polycrystalline silicon to fill the cavity of the trench). An example of a prior art device using such isolation is provided in an article by Ueno et al., "A sub-40 picosecond ECL circuit at a switching current of 1.2 mA", Technical Digest of IEEE International Electron Devices Meeting, December 1987, p. 371.
Prior art static random access memory (SRAM) cells employ a pair of cross-coupled inverters (flip flops) which are stable in one or the other of two binary states. Each of the two inverters consists of a switching transistor and a pullup load device. This load device may be a transistor or a resistor. The highest density SRAM devices available commercially employ a cell consisting of four N channel MOS (NMOS) transistors and two resistors. FIG. 2a is a schematic diagram of such a prior art SRAM cell. Transistors T.sub.1 and T.sub.2 are the switching transistors of the cross-coupled inverters. Transistors T.sub.3 and T.sub.4 are access transistors through which the binary state on nodes O.sub.1 and O.sub.2 is sensed during read by a sense amplifier (not shown) connected to bit lines D, D and through which new data from D and D is written into the memory cell. Resistors R.sub.1 and R.sub.2 are very high resistivity loads. The high resistance is necessary in order to minimize the quiescent power dissipation through the one of the two cross-coupled inverters whose transistor (T.sub.1 or T.sub.2) is switched on at any one time. Typically, the current through either one of the load resistors is in the nanoamp range or lower.
A compact SRAM cell is achieved by implementing the high resistivity loads in a layer of undoped or lightly doped polycrystalline silicon. An example of such prior art cell is described by Komatsu et al., "A 35 nanosecond 128K.times.8 CMOS SRAM", IEEE Journal of Solid-State Circuits, Oct. 1987, SC-22:721. These polycrystalline silicon loads are typically 500 nanometers or less in thickness, one to two microns wide, and three to eight microns long. Two such resistors are required per cell, consuming a significant amount of device surface area even when implemented in a second or third layer of polycrystalline silicon which can be placed at least partially physically above the two switching transistors T.sub.1, T.sub.2. The implementation of polycrystalline silicon load resistors also requires three additional masking steps, the first to define buried contacts from load resistors to diffusions, the second to define the geometry of the resistors in the layer of polycrystalline silicon, and the third to protect the resistor areas during doping of the other areas of the polycrystalline silicon to achieve electrical contact to the Vcc supply, in order to maintain the high resistivity of resistors R.sub.1 and R.sub.2. A great deal of effort has been spent in the industry to scale down the size of the polycrystalline silicon resistors. The main problem with scaling is due to sideways diffusion of arsenic or phosphorous dopants along polycrystalline silicon grain boundaries resulting in unacceptably high leakage currents. To eliminate such problems, some prior art devices eliminate altogether the load elements, relying instead on temporary storage of charge on the parasitic capacitances of nodes O.sub.1, O.sub.2 (FIG. 2b). Such an approach is described by Hanamura et al., "A 256K CMOS SRAM with internal refresh", Digest of Technical Papers from 1987 ISSCC, FAM 19.1, p. 250. Hanamura claims that elimination of the high resistivity polycrystalline silicon loads results in a SRAM cell which is approximately 30% smaller, and is altogether more scalable at higher densities. Unfortunately, Hanamura's cell requires periodic refresh of every bit in the memory array to reinforce the charge on storage nodes O.sub.1, O.sub.2. This forces a memory cycle time which is double the memory access time, in contrast to SRAMs using polycrystalline silicon loads where cycle time and access time are the same, and where no extra circuitry is required for the refresh cycle.
Prior art semiconductor structures have also had difficulty in providing a good, low resistivity interconnection path between the surface of the semiconductor and buried diffusion regions. Such a buried diffusion may be the buried collector of a vertical NPN transistor, the N+ or P+ buried diffusions underlying PMOS and NMOS transistors, respectively, in CMOS or BICMOS structures, or N++ or P++ substrates carrying one of the supply voltages in an epitaxial structure. FIG. 3a shows a cross section of a prior art vertical NPN bipolar transistor 300 (taken from the Ueno paper referenced above). In this transistor, isolation trench 320 surrounding NPN transistor 300 is etched through an N- epitaxial layer 307 and through a second N+ epitaxial layer 306 grown on P- substrate 305. Walls 301 of isolation trench 320 are insulated with thin oxide film 302 and trench 320 is filled with polycrystalline silicon 303 to achieve a flat surface topology. Shallow N+ emitter region 314 is formed by out diffusion from N+ doped polycrystalline silicon layer 311, P+ base region 308 is contacted with polycrystalline silicon 310, and N- on N+ buried collector 306 is contacted from the top surface through N+ downward diffusion 309, using N+ doped polycrystalline silicon 312 as the diffusion dopant source. This N+ diffusion 309 requires a prolonged high temperature diffusion cycle which is detrimental to other shallow junctions in this structure, and introduces a collector series resistance.
FIG. 4 shows the cross section of another prior art BICMOS structure, as shown by Ogiue et al., "13ns, 500 mW, 64K bit ECL RAM using HI-BICMO Technology, " IEEE Journal of Solid State Circuits, Oct. 1986, SC-21:681. In this structure, bipolar transistor 400 is a vertical NPN transistor similar to prior art transistor 300 (FIG. 3). PMOS transistor 440 has its N well 423 and source diffusion 424 held at Vcc potential, supplied by a top surface Vcc metal bus line (not shown). NMOS transistor 450 has its P well 428 and source diffusion 429 held at ground potential, supplied by another top surface ground metal bus line. These metal lines as well as additional metal lines serving as the P+ to N well straps and N+ to P well straps consume significant surface area in prior art structures.