Overload current limiting circuits, especially short circuit current limiting circuits are used in digital output drivers which use large transistors to drive output loads to specified voltage levels at adequate speed. As a result of the drive and timing requirements digital output drivers can deliver excessive current, if, because of a fault there is established a low impedance path to a supply reference voltage level on a system coupled to the output of a large transistor.
One example of such a high current condition is where an output driver is being driven by a logic high and therefore its output is coupled to a logic high rail by an output transistor. If the output is then shorted to logic low by a fault condition the pull up transistor may supply excessive current. This excessive current could damage its output transistor and therefore this current should be limited. It should be noted that short circuit conditions can also occur to logic high rails when being driven low and indeed shorts resulting in excessive currents can occur to different voltage levels than supply rails.
Various attempts have been made to reduce overload currents in order to prevent damage to the circuits and components. In one approach, a digital comparison is made of the output voltage on a digital buffer versus its input voltage and then the driver is put into a low current state either by “three stating” the output or flipping over the output driver to drive it to the correct logic level. A disadvantage of this approach is that after removing of the short circuit condition an explicit reset function has to be carried out to return the output voltage/logic state to its normal value.
In another approach two sense amplifiers are designed to have certain trip points to detect a high current state when faulted to a low or high output voltage. This approach requires a parallel weaker secondary driver device to enable the circuit to correct the logic state after removal of the high current state. A disadvantage is the fact that at least one of the secondary drivers is on at all times in normal operation. Another design monitors the output voltage of a digital output driver versus its input logic state and “three states” the output if a fault condition is detected. A refresh loop periodically refreshes the fault detection circuitry thereby returning the output to the correct state after the fault condition has been removed. But the refresh loop is relatively complex and consumes extra power and requires substantial area.
In still another approach, the output current is mirrored in a parallel sense path. If the sense current is greater than a reference value, the drive of the output transistor is restricted. The current feedback paths in these circuits are relatively complex, consume considerable power, and require careful design for stability. In addition, an analog reference current must be generated which is in itself a substantial task.
In still another approach, the gate drive of an output transistor is clamped when it is delivering high current in a fault state by using two series connected transistors. These transistors both conduct to clamp the voltage at the output node of the digital buffer. However, it is difficult to totally shut off this large driving transistor without consuming high current in the sensing path and if the gate drive is limited too much, the output node will remain clamped even when the short circuit is removed.