1. Field
One or more embodiments described herein relate to a method for placing a parallel multiplier.
2. Description of the Related Art
A System-on-Chip (SOC) may include numerous internal datapaths and logic circuits. Such an SOC may be fabricated using an automated placement and routing method. However, determining a placement algorithm which seeks to minimize wire lengths while at the same time achieve optimal power, performance, and space may be difficult to implement. This is because placement algorithms do not take into consideration architectural characteristics of the datapaths. In an attempt to cope with this kind of algorithmic problem, structural placement and routing may be performed manually. However, this approach has proven to be costly and time inefficient.