Automatic Test Equipment (ATE) is commonly used within the field of electrical chip manufacturing for the purposes of testing electronic components. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
Presently, there are two types of systems for testing system-on-chip semiconductor devices: Tester-Per-Site (TPS) and Tester-Per-Pin (TPP). The TPS system groups together a number of test functions that may be performed on each device under test (DUT) within what may be referred to as a “test site.” In a real time testing environment, a TPS system includes testing several DUTs on several test sites with one resource station available to provide testing resources for each site. FIG. 1A provides a depiction of a conventional Tester-Per-Site system (TPS). As illustrated by FIG. 1A, resources 1, 2, 3 and 4 comprise a pool of per-site resources dedicated to testing DUT 101 when connected to their corresponding pins located in DUT 101 (pins 6, 7, 8 and 9 respectively).
This particular architecture provides for test flow flexibility in the sense that each device is tested independently, which decreases potential bottlenecking caused by failing devices. However, implementation of this architecture may also come at the expense of wasting testing resources since each resource cannot be shared among multiple sites during the test phase. Furthermore, the TPS system's dedicated testing approach, in which all testing resources are focused on a single DUT, may result in wasted resources for devices that do not require those resources, thus resulting in resource inefficiencies. An example of the TPS system is disclosed in U.S. Pat. No. 6,779,140 “Algorithmically Programmable Memory Tester with Test Site Operating in a Slave Mode.”
The competing TPP system provides a range of analog and digital drive and receive capabilities which may operate independently of each other. Through the use of “pins”, the TPP system assigns each pin of the tester device to provide a specific resource capable of supporting a test. FIG. 2B provides a depiction of a conventional Tester-Per-Pin system (TPP). The TPP system supports the use of multiple tester “channels” to test multiple DUTs on multiple test sites when testing in parallel. As depicted in FIG. 1B, channels 80 through 94 provide various tester resources to DUT 101 once the channels are connected to their respective pins (180 through 184) located on DUT 101. It is understood that channels 85 through 89 and 90 through 94 may be configured in a similar manner as channels 80 through 84 with regards to their respective DUTs (201 and 301 respectively).
However, when testing in parallel under the TPP system, multi-site inefficiency problems exist. Although tester workstation 15 is able run multiple tests on multiple DUTs, these tests must be kept in lock step. For example, in the event that DUT 101 reports a failure, channels 80 through 84 must wait while DUTs 201 and 301 finish testing before channels 80 through 84 can be re-initialized and reassigned to test another device. Additionally, DUT 101 may require a longer testing period than DUT 201, thus tying up available channels that may be better utilized on another DUT. Therefore, although multiple devices may be tested in parallel under this approach, test flow is dependent upon the completion of the longest test to finish on a DUT. An example of the TPP system is disclosed in U.S. Pat. No. 5,461,310 “Automatic Test Equipment System Using Pin Slice Architecture.”