As semiconductor devices are becoming more highly integrated, design specifications for the devices, such as design rule, critical dimensions (CD) and contact area, are becoming gradually reduced. For this reason, electronic circuits on substrates are becoming more and more complicated, and circuit-packing densities for the substrates are gradually increasing. High circuit packing density requires high operation precision in each unit process for manufacturing the semiconductor devices, and thus detection technology for detecting defects in the electronic circuits is becoming more and more sophisticated.
A test element group (TEG) inspection technology has been suggested for improving the accuracy and efficiency of a detection process. A test structure including various TEGs is formed on a test chip, and processing defects in the electronic circuits are detected by an in-line detection process that is performed with respect to the test structure simultaneously with the manufacturing process for the semiconductor device. The above TEG inspection technology is performed through an electrical process, and thus shows accurate information on whether or not defects exist in the electronic circuits. However, there is a problem in that the TEG inspection technology cannot provide any further information on detected defects such as the kinds, locations and causes of the defects.
In order to solve the above problems of the TEG inspection technology, a voltage contrast inspection technology has been used instead of the TEG inspection technology. According to the voltage contrast inspection technology, charged particles such as electron beams and ion beams are irradiated onto the test chip, to thereby form a data image of the TEG illustrating the voltage contrast of the TEG on the test chip. The data image is compared with a reference image illustrating the voltage contrast of a reference TEG having no defects, to thereby detect processing defects in the electronic circuits of the devices. That is, the voltage contrast inspection technology detects the defects using the charged particles instead of the electrical process. The voltage contrast inspection technology provides accurate information on the kinds, locations and causes of the defects, as well as the defects themselves.
For example, United States Patent Publication No. 2003/0001598 (Assignee: KLA-Tencor Corp., U.S.A.) discusses the voltage contrast inspection technology based on a density of secondary electrons. The secondary electrons emitted from a test structure including grounded conductive lines and floating conductive lines are detected and the processing defects of TEGs are inspected using voltage contrast between the grounded conductive lines and the floating conductive lines based on the density of the detected secondary electrons. The voltage contrast inspection technology of the above United States patent publication can detect physical defects, such as a shape deformation of a circuit pattern, as well as electrical defects, such as electrical openings or shorts.
Referring now to FIG. 1, a view illustrating a test structure for a conventional voltage contrast inspection technology will be discussed. As illustrated in FIG. 1, a test structure 10 for the conventional voltage contrast inspection technology includes a plurality of grounded conductive lines 12 and floating conductive lines 14. For example, each of the grounded conductive lines 12 includes a metal wiring grounded to a substrate through a contact plug, and each of the floating conductive lines 14 includes a conductive line electrically insulated from the metal wiring by a dielectric layer.
Electron beams are irradiated onto the test structure 10 including the grounded conductive lines 12 and the floating conductive lines 14 so as to detect processing defects in the test structure 10 using the voltage contrast inspection technology.
Processing defects in the test structure 10 are detected by an assessment scan of the electron beam that is irradiated onto the test structure 10 in a vertical direction to the conductive lines 12 and 14, and locations of the detected processing defects are identified by an identification scan of the electron beam that is irradiated onto the test structure 10 in a direction parallel with the grounded conductive lines 12, to thereby determine the kinds and locations of the processing defects.
When the electron beams are irradiated onto the test structure 10, a plurality of secondary electrons is generated from the conductive lines 12 and 14 of the test structure. The secondary electrons, which are generated from the grounded conductive lines 12, flow into a ground sink and form an electron flow from the conductive lines 12 to the ground sink. Thus, the electron flow through the grounded conductive lines 12 is detected to have a relatively large voltage. In contrast, the secondary electrons, which are generated from the floating conductive lines 14, cannot flow into the ground sink and flow only in the floating conductive lines 14, because the floating conductive lines 14 are electrically isolated from other portions of the test structure 10. Thus, the electron flow through the floating conductive lines 14 is detected to have a relatively small voltage. The detected voltages are visually shown as a bright portion 22 and a dark portion 24 in a voltage contrast image 20 in accordance with each of the conductive lines 12 and 14. The bright portion 22 of the voltage contrast image 20 corresponds to the voltage of the electron flow through the normal grounded conductive lines 12 having no processing defects therein, and the dark portion 24 of the voltage contrast image 20 corresponds to the voltage of the electron flow through the normal floating conductive lines 14 having no processing defects therein.
The grounded conductive lines 12 and the floating conductive lines 14 are alternately positioned in the test structure 10 and are spaced apart from each other by a predetermined distance, and thus the bright portions 22 and the dark portions 24 are also alternately arranged and spaced apart by the same distance as the conductive lines 12 and 14 if the conductive lines 12 and 14 have no processing defects. That is, when the conductive lines 12 and 14 have no processing defects therein, a pair of the bright and dark portions 22 and 24 is periodically repeated in the voltage contrast image 20 in accordance with each of the conductive lines 12 and 14. Therefore, the assessment scan to the test structure 10 may find a break point at which the alternating arrangement and periodicity of the bright and dark portions 22 and 24 of the voltage contrast image 20 is broken, and may determine which of the conductive lines 12 and 14 has processing defects.
For example, when an electrical short is generated between the grounded conductive lines 12 and the floating conductive lines 14 adjacent to each other, the floating conductive lines 14 are electrically grounded to the ground sink through the grounded conductive lines 12. For that reason, the floating conductive lines 14 including electrical short defects are represented as bright portions, as shown in a first portion A of the voltage contrast image 20, even though the floating conductive lines 14 including no defects should be represented as dark portions. Furthermore, when each of the grounded conductive lines 12 includes an opening, a portion of each of the grounded conductive lines 12 is electrically isolated from the other portion thereof, and each of the grounded conductive lines 12 works similarly to the floating conductive lines 14. As a result, the grounded conductive lines 12 including opening defects are represented as dark portions, as shown in a second portion B of the voltage contrast image 20, even though the grounded conductive lines 12 including no defects should be represented as bright portions.
Thereafter, the identification scan is performed along the conductive lines including defects, to thereby determine the locations and causes of the detected defects. The identification scan is usually performed in an analysis system including a focused ion beam (FIB) unit and a scanning electron beam (SEB).
The above assessment scan and identification scan are performed in a real-time process simultaneously with every unit process of a semiconductor manufacturing process, so that the inspection process is performed simultaneously with the manufacturing process of the semiconductor device.
However, the above voltage contrast inspection technology provides accurate information on the processing defects generated in each of the unit processes of the manufacturing process for the semiconductor device, but typically does not provide any information on a process margin of each of the unit processes.
In general, the processing defects, which may reduce a production yield of a semiconductor device, are classified into random defects caused by particles or voids, and system defects caused by insufficient transcription of a layout for a circuit pattern. Random defects represent all kinds of the processing defects that are randomly and unintentionally generated in the unit processes of the manufacturing process for the semiconductor device, and includes electrical or physical defects caused by random particles or random voids that are unintentionally generated in the manufacturing process.
System defects represent all kinds of defects caused by discrepancies between a circuit layout and a circuit pattern that is transcribed from the circuit layout in a unit process, so that the system defects are mainly influenced by an allowable error range or a process margin of the unit process. When a circuit pattern is formed to have smaller critical dimensions (CD) using a usual apparatus for the unit process having conventional specifications and operational characteristics, the layout for the circuit pattern may be difficult to accurately transcribe onto a substrate, to thereby increase the possibility of system defects due to the poor accuracy of the transcription. As the degrees of integration of recent semiconductor devices are being improved, each unit process for manufacturing the semiconductor device is required to be performed more accurately. Accordingly, there may be a higher possibility of system defects being generated due to discrepancies between the circuit pattern on a substrate and the circuit layout.
The conventional defect inspection technology discussed above has been good for detecting random defects that have already been generated in a unit process; however, the conventional defect inspection technology generally cannot provide any information on system defects that may be generated after the unit process has been completed. Furthermore, a recent manufacturing process has a higher chance of generating system defects due to high process accuracy that is required for patterns having reduced CDs and line widths.
Random defects have already been generated in a unit process, and thus the inspection technology for random defects is focused on detection of the defects. In contrast, system defects are caused by incomplete transcription of the layout onto the substrate, and thus the inspection technology for system defects is focused on obtaining a sufficient allowable error range or process margin. The system defects as well as the random defects can have a higher effect on the production yield of semiconductor devices as the degree of integration increases and the line width of the semiconductor devices decreases.