Phase Locked Loops (PLL) circuits are electronic circuits that provide for a variable frequency oscillator (VCO) and a phase/frequency detector (PFD) which generate an output signal having a phase that is associated with the phase of an input signal to the PLL. Typically, the PLL attempts to generally provide for phase matching as between the phases of the input signal and the output signal by adjusting the frequency of the VCO based on control signals of the PFD through a feedback loop. A PLL can provide for demodulation by tracking the frequency of the input signal or a PLL may generate a frequency that is a multiple of the frequency of the input signal for frequency synthesis.
PLL circuits have applicability in a variety of electronic equipment including radio, computer, telecommunication equipment and other electronic applications, such as microprocessors. PLL circuits are widely used for synchronization purposes. PLL circuits in digital wireless communication system applications are used to provide the local oscillator for up-conversion during transmission and down-conversion during reception often in microprocessor applications. PLL circuits can also provide for distributing clock pulses.
FIG. 1 depicts a block diagram of a PLL frequency multiplier circuit 100. The input reference signal (frequency reference input) 110 is applied to an input of a PFD 120. A second input of the PFD 120 receives the signal output 115 of a counter 120. In a balanced operation, the frequencies of the input reference signal 110 and the counter output 115 will approximate one another. The PFD 120 provides an output 125 of a voltage proportional to the phase difference between the two signal inputs (110, 115) of the PFD 120, to a loop filter 130. The loop filter 130 typically determines dynamic characteristics of the PLL and provides a control signal 135 to the VCO 140. Ideally, the VCO 140 provides an output 145 at a frequency that is N times the input supplied to the frequency reference input as the frequency output of the PLL at 150. N is defined as an integer herein and throughout. The VCO output 145 is also provided to the counter 120 via 146 as input at 147.
FIG. 2 depicts a block diagram of another PLL circuit 200. In circuit 200, an input reference signal 210 is provided as input to a PFD 220. A second PFD input is provided from the counter output 291 of the counter 290. As in FIG. 1, the PFD 220 compares the two input signals (210, 291) and produces an output up pulse 225 and an output down pulse 226 which are proportional to the phase differences of the two input signals (210, 291). The output pulses (225, 226) are provided as input to the charge pump 230 and act to control switches of the charge pump to adjust current into or out of a capacitor of the charge pump, effectively causing the voltage across the capacitor to increase or decrease, where the charge delivered is therefore dependent on the phase difference. Typically a charge pump in a PLL design is constructed in integrated-circuit (IC) technology, consisting of pull-up, pull-down transistors and on-chip capacitors. The output of the charge pump 235 is preferably passed to a low-pass filter 240 which is then used to tune or drive the VCO 250 creating an output signal frequency 260 that is also used as feedback (e.g., a negative feedback loop) to the counter 290.
In operation, if the output phase drifts, the output signal from the PFD will increase, driving the VCO phase in the opposite direction resulting in a reduction to the phase drift. Similarly, if the phase becomes ahead of the reference, the PFD alters the control signal to the VCO to slow the oscillator of the VCO down. Therefore, the output phase is referred to as being “locked” to the phase of the input reference signal.
What is desired to improve the performance of PLL circuits is to reduce the amount of time required to lock without sacrificing performance in noise or frequency breadth limitations. Various approaches to achieve this objective have been proposed including increasing the charge pump current by a factor of N, while reducing the loop filter zero-resistor by sqrt(N). However, such approaches of bandwidth extension typically require a boost to the charge pump gain thereby requiring additional and significant circuit area. Therefore, a solution to provide a reduced locking time that provides for satisfactory performance without the need for significant footprint area for the PLL circuit by boosting PFD and CP gains is desired. Furthermore, the solution should be applicable to both integer-N and fractional-N PLL, in order to find wide applications in modern communication systems.
The term charge pump herein may refer to charge pumps which are known in the art, to those under and being developed to advance the state of the art, and more particularly to specifically also include as interchangeable with the referential term here, that which is set forth in U.S. Provisional Application No. 61/417,291, filed on Nov. 26, 2010, which is incorporated by reference in its entirety herein by reference.
As used herein the terms device, apparatus, system, etc. are intended to be inclusive, interchangeable, and/or synonymous with one another and other similar arrangements and equipment for purposes of the present invention though one will recognize that functionally each may have unique characteristics, functions and/or operations which may be specific to its individual capabilities and/or deployment.