1. Field of the Invention
This invention relates to bipolar transistor ROM devices and particularly to a fabrication process therefor.
2. Description of Related Art
U.S. Pat. No. 5,029,127 of Uchida et al, for "Bipolar SRAM Having Word Lines as Vertically Stacked Pairs of Conductive Lines Parallely Formed with Holding Current Lines" shows a bipolar SRAM.
FIG. 1 is a schematic circuit diagram of a prior art FET ROM with bit lines BL1, BL2 . . . BLN. Word lines WL1, WL2 . . . WLN are shown also. The gates of FET devices T1, T2, T3, and T4 (shown as examples) connect to word lines WL1 and WL2. The sources of FET devices T1, T2, T3, and T4 connect to bit lines BL1 and BL2. The drains of FET devices T1, T2, T3, and T4 connect to reference potential (ground.)
As the geometry of MOS ROMs shrink, the current of an MOS ROM is reduced until at smaller and smaller sizes the current becomes low, causing the speed of the ROM device to be slow because of the reduction of the current level.
Bipolar current devices are relatively insensitive to geometry as compared with MOSFET devices. The current of bipolar devices is from about 1 to about 2 orders of magnitude greater than the current of MOSFET devices of comparable size, so a bipolar ROM of equal size is a far higher speed device. For this technology, a bipolar ROM is a self-aligned structure, so the density is also high.