Fault-tolerant clock systems using redundant clock sources are currently available for providing timing signals in the failure of one or more of the individual clock sources therein. Some systems require relatively complex self-testing circuitry while other systems which rely on a majority decision among redundant sources are arranged in ways which could cause erroneous output pulses to be formed. Still other systems utilize the approach of detecting, isolating and correcting faults as they occur, a design which requires the determination of all failure modes prior to design, thereby producing a complex and relatively expensive system.
Other systems require a relatively large number of clock elements to provide tolerance for faults. One such system which has been devised for minimizing the number of redundant clock sources required for tolerating a selected number of clock failures, thereby reducing the cost and complexity of such a system, has been disclosed in U.S. Pat. No. 4,239,982, issued on Dec. 16, 1980 to T. Basil Smith et al. In such system, for example, a selected number, e.g., r, of clock source failures can generally be tolerated while using only (2r+2) redundant clock sources.
In the Smith et al. system the clock generator of each redundant clock source utilizes a variable frequency generated clock signal, the frequency of which is controlled by a voltage controlled oscillator (VCO). The phase of a derived system clock signal is compared with the VCO generated clock signal and the compared output is supplied to a low pass filter which produces a DC voltage for controlling the operation of the voltage controlled oscillator so as to change the frequency of the output thereof until it is in phase with the derived system clock signal. The latter signal is normally determined by a majority (M) of the total number of clock signals from the redundant clock sources.
While such a system works better than previously designed fault-tolerant clock systems, the reliability of VCO clock generated sources is relatively low, while the cost thereof is relatively high.
It is desirable, therefore, to design a fault-tolerant clock system which avoids the use of VCO circuitry and utilizes effective logic circuitry which is both less expensive and more reliable for long term use.