As a technology for achieving high performance, multifunction and compactness of an electronic device such as a mobile device, there is known a so-called chip on chip (COC) technology in which a plurality of semiconductor chips such as a memory chip and a logic chip are stacked in three dimensions. Among semiconductor devices manufactured by utilizing the COC technology, a semiconductor device in which two semiconductor chips are flip-chip bonded is advantageous for achieving compactness, speeding up of data transfer between chips, and so on, and is often used in various electronic devices.
Conventionally, a semiconductor device with a COC structure using such flip-chip bonding is manufactured by bonding terminals of respective surfaces (circuit formation surfaces) of two semiconductor chips via solder bumps and thereafter filling an underfill material therebetween. The solder bumps are formed on terminals of at least one of the semiconductor chips and the solder bumps are molten by reflow processing and bonded. Lead-free solder, for example, SnCu, or SnAg, which does not include Pb, is generally used for the solder bumps in view of environment conservation. The reflow processing is performed, for example, at a peak temperature of 240-260° C., which is 20-30° C. higher than the melting temperatures of above lead-free solders.
However, in such a semiconductor device manufactured by an existing method, warpage of the two semiconductor chips occurs due to influence of an insulation film or the like formed on the surface of the semiconductor chip as a protection film, each bonded part of the bumps being compressed or tensioned. This may result in a connection failure (short circuit or open circuit). In particular, an organic film, for example, polyimide film, having cure temperature of about 350° C. to 380° C., has been often used as an insulation film because of its excellence in a trap function for dust such as Si. In this case, warpage becomes minimum at the cure temperature, increasing as a temperature goes down, sometimes reaching 30 μm at the temperature at which the solder bumps solidifies (for example, solidification point of SnAg solder is about 221° C.), so that the connection failure at bonded parts of the bumps as described above tends to occur easily. Thus, a technology suppressing occurrence of warpage of a semiconductor chip is required.
Relating to such a kind of technology, there is disclosed, for example, in JP-A 2009-158706 (KOKAI), a method for suppressing deformation of a semiconductor package due to a difference in thermal expansion between a sealing material and a package substrate. However, since this method is to suppress deformation of the semiconductor package in mounting to a motherboard, a method for solving the above-described problem in a semiconductor device with a COC structure has not been found yet.