A related patent application Ser. No. 10/001,628 by Abu-Hena M. Kamal, Ramsin M. Ziazadeh and Laurence D. Lewicki has been filed concurrently with this patent application entitled xe2x80x9cLow Power Analog Equalizer with Current Mode Digital to Analog Converterxe2x80x9d. The related patent application and the present patent application are commonly assigned to the assignee of the present patent application.
The present invention relates generally to the field of analog equalizers. More particularly, the present invention provides an improved analog equalizer that is capable of adaptively compensating for analog signal distortions that are caused by transmitting an analog signal through a cable to a receiver.
A gigabit data transmission rate is equal to the transmission of one billion (109) bits per second. The use of transceivers that are capable of gigabit data transmission rates is well known in digital communications technology. A gigabit Ethernet system enables data communication by transmitting and receiving data bits as analog signals over a Category 5 (CAT-5) unshielded twisted pair (UTP) cable. During the data communication process a receiver recovers the digital data from the transmitted analog signal. Data carrying signals are distorted severely as they are transmitted over a long cable length at a high frequency in the form of a multi level symbol alphabet, such as MLT-3 or PAM-17.
In such a case a gigabit receiver operates under several detrimental effects such as cable attenuation, echo from its own transmitter, etc. If channel distortion is not equalized or corrected, then the recovered clock signal from the received signal will be so erroneous that the recovered data will have an unacceptable bit error rate (BER), typically greater than 10xe2x88x9210. It is thus often necessary to improve the signal quality before attempting clock or data recovery. A cable equalizer circuit is implemented to compensate for the cable transmission loss and reshape the signal to its original (transmitted) waveform to improve inter-symbol interference (ISI) of the recovered data.
The transmission loss in decibels (dB) within the cable is linearly proportional to the cable length. The cable transmission loss in decibels (dB) is also proportional to the square root of the data transmission rate. The data transmission rate or transmission frequency and cable length are interdependent. An adaptive equalizer synthesizes a frequency response that is inversely proportional to that of the cable.
Various types of adaptive equalizers have been developed. Prior art adaptive equalizers improve signal quality either alone or in combination with digital finite impulse response (FIR) filters.
For example, U.S. Pat. No. 5,841,810 issued to Wong et al. on Nov. 24, 1998 describes a multistage adaptive equalizer. The input data signal in the Wong patent is successively filtered and magnitude weighted by successive adaptive filter circuits in accordance with corresponding adaptive control signals. In accordance with its respective adaptation control signal, each adaptive filter stage equalizes the data signal for a length of the cable through which the data signal was received. The adaptation control signal generator generates the individual adaptation control signals based upon an input equalization control signal. The input equalization control signal can be in, the form of an analog voltage or in the form of a multiple bit digital signal. Each adaptive filter stage is configured with a constant gain signal path connected in parallel with a high frequency boosted, variable gain signal path. The input data signal is amplified in accordance with a first signal gain G1 that is constant over frequency F to provide one of the input signals to a signal summer. The input signal is also amplified in accordance with a second signal gain G2 that increases with frequency in a manner that is complementary to the complex cable loss characteristic of the cable. The resulting high frequency boosted signal is then amplified in accordance with a third signal gain G3. While constant over frequency F, the third signal gain G3 is a function of the corresponding adaptation control signal. The resulting high frequency boosted, variable gain signal is then summed with the constant gain signal to provide the partially equalized signal.
Another type of analog adaptive equalizer is described in U.S. Pat. No. 5,455,843 issued to Cherubini et al. on Oct. 3, 1995. Another type of analog adaptive equalizer is described in an article entitled xe2x80x9cA 3.3V Analog Adaptive Line-Equalizer For Fast Ethernet Data Communicationxe2x80x9d by J. N. Babanezhad in IEEE 1998 Custom Integrated Circuits Conference, pp. 343-346 (1998). Another type of device for equalizing channel distorted signals is described in U.S. Pat. No. 6,047,024 issued to How on Apr. 4, 2000.
It would be desirable to have an analog equalizer that is capable of operating at lower operating voltages than prior art analog equalizers.
It would also be desirable to have an analog equalizer that is capable of consuming less power than prior art analog equalizers.
It would also be desirable to have an analog equalizer that has a reduced die size compared to prior art analog equalizers.
The present invention is directed to an analog equalizer that is capable of adaptively compensating for analog signal distortions that are created during a gigabit data rate transmission of an analog signal through a cable to a receiver.
An advantageous embodiment of the present invention comprises an apparatus and method that adaptively compensates for gigabit channel impairment caused by the variation in channel length. A typical gigabit channel is a Category 5 (CAT-5) cable. The equalization created by the present invention provides a maximum boost of approximately twenty decibels (20 dB) which is sufficient to compensate for the attenuation experienced by a signal in a cable approximately one hundred twenty five meters (125 m) in length. The analog equalizer of the present invention synthesizes a frequency response that is inversely proportional to the frequency response of the cable. The analog equalizer of the present invention enables a one and eight tenths volt (1.8 volt) operation while significantly reducing power consumption and die size compared to prior art analog equalizers.
An advantageous embodiment of the present invention comprises a low impedance summing node in a regulated cascode configuration, an operational amplifier with a feedback network, and an impedance network comprised of passive resistors and capacitors to create an impedance profile that is inversely proportional to frequency. The impedance network is AC coupled to the low impedance summing node.
It is an object of the present invention to provide an apparatus and method for providing an analog equalizer that operates at a lower operating voltage than prior art analog equalizers.
It is another object of the present invention to provide an apparatus and method for providing an analog equalizer that consumes less power than prior art analog equalizers.
It is also an object of the present invention to provide an apparatus and method for providing an analog equalizer that has a smaller die size than prior art analog equalizers.
It is another object of the present invention to provide an apparatus and method for providing an analog equalizer that has greater linearity than prior art analog equalizers.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.