Modern mainframe data processing systems include central processing units (CPU), central memory directly addressable by the CPU, input-output (I/O) storage devices to enter data into and record data from the system, and I/O processing systems which control and buffer the movement of data between the I/O devices and the central memory. I/O processing systems relieve the CPU of directly controlling the I/O devices and permit data processing to proceed concurrently with I/O operations.
In an I/O operation it is necessary to transfer data and control information between various components of the system, generally along a path between the CPU and the I/O storage devices. For instance, to store data from the central memory in a storage device, the data must be transferred from the memory to the I/O processing system and from there to the selected storage device. As each of these components typically operate at different clock rates, or at least are not synchronized, interlocked interfaces are necessary to permit interface operations to proceed independently of the internal speed of the individual components.
Although interlocking schemes have taken various forms in the prior art, they generally provide for interlocking on a byte by byte or word by word (unit) basis, such that each unit of information or data transmitted is acknowledged by the receiving component before another is sent by the transmitting component. Good examples of such prior art "fully" DC interlocked interfacing schemes are disclosed U.S. Pat. No. 3,336,582--Interlocked Communication System--Beausoleil et al and U.S. Pat. No. 3,582,906--High-Speed DC Interlocked Communication System Interface--Beausoleil et al.
While fully interlocked interfacing schemes are typically simple and reliable, they are inherently limited as to the data transfer rates which may be achieved therewith. In very high speed applications involving terminals or peripheral devices capable of transmitting or receiving data at clock rates in the range of 10 Mhz (100 ns clock period) propogation delays on interfacing cables (approximately 1.6 ns/foot) become a dominant speed limiting factor for fully interlocked interfaces when cables longer than even just a few feet are used. Considering that in many applications it is necessary as a practical matter to provide cabling lengths in the range of 80 feet, the "round trip" time required to interlock a unit of data can exceed 250 ns. Thus for a typical 16-bit data path width the maximum unit transfer rate of fully interlocked schemes is in the neighborhood of 64 Mbps, too slow even to take full advantage of relatively fast state-of-the-art disk drive units, not to mention much faster solid-state storage device. (For a graphic example of the inherent delays in fully interlocked interfacing systems of this nature see, for instance, FIG. 15 of the proposed standard interface specification entitled "Intelligent Standard Interface (ISI)," SPEC 77653440, CD 6, REV B, 4/30/82, published by Magnetic Peripherals Inc., (a Control Data Company)).
Accordingly, alternate interfacing techniques have been developed to minimize the delays inherent in fully interlocked systems. One such technique, generally known as "data streaming" provides that two or more parcels of data be transmitted per interlock acknowledgment by the receiving component. Thus, where L equals the propogation delay time for a interface cable, and N equals the number of data parcels transmitted per interlock acknowledgment, a transmission time 2L (N-1) is saved over fully interlocked systems for the transmission of N data parcels. As may be readily appreciated, substantially higher data transmission rates may be obtained in this manner, thus providing the potential for reducing I/O related CPU idle time and permitting a reduction in the quantity of I/O processing hardware (such as data channels) required to sustain a given overall system I/O rate.
Data streaming does, however, entail more complicated and expensive interface hardware and software. For instance, it generally requires the buffering of data on each side of the interface to assure a continuous stream is available to be sent from the transmitting side without underrun and to assure the receiving side may absorb the transmitted stream without overrun. Thus, information or data buffers must be provided along with addressing control to an extent over and above that normally necessary in a fully interlocked system, increasing complexity, cost, and space and power requirements. However, if the stream length is minimized to reduce associated buffering requirements, speed is sacrificed. Relatedly, if the stream length is maximized to increase speed, buffering requirements can approach prohibitive levels and data handling flexibility is sacrificed; short streams cannot be handled efficiently and multiplexing capability is diminished or at least made more difficult to provide.
While the data transfer rate is perhaps the most important feature of any interfacing scheme designed to move large amounts of data over relatively great distances, there are other things which must be considered. Pinouts and terminals are usually a limited resource in any system and thus must be conserved. Similarly, it is preferable to hold cabling requirements down. Therefore, the number of signal lines utilized in an interface should be held to minimum. There are, however, contraindicating factors. Transfer rate may be easily improved by providing more data and/or control lines; interface protocol and control is simplified if a number of specialized function lines are provided, which, where complicated devices such as disk drives need be controlled, would indicate a relatively large number of function lines; and, maintenance of data integrity during a transfer favors multibit check bytes per parcel of information transferred.
Thus, as may be readily seen there are many conflicting factors to be considered in designing an interface system. In fact, the considerations are so various that the maximization of resources warrants detailed statistical analysis. The present invention, through optimizing data transfer rate, data handling flexibility, and data integrity maintenance while minimizing buffering, terminal, cabling, and control requirements and complexity, provides a relatively simple yet fast, flexible and reliable electrical interface system. As shown in the drawing and explained in the ensuing description, the present invention strikes an optimum balance between a very high speed hardware intensive interface characterized by extensive complex buffering, multi-bit parity codes and overly simplified controls utilizing many specialized control lines and a protocol intensive interface characterized by extensive sharing of hardware resources between different sides of the interface (e.g. a bi-directional data bus), complicated protocol and minimal terminal and cabling requirements.