The present invention relates to semiconductor devices and methods thereof and more particularly, to DRAM devices having a capacitor and methods thereof.
In semiconductor devices such as DRAMs (Dynamic Random Access Memory), each cell is composed of one transistor and one capacitor. In DRAMs, cells require periodic reading and refreshing. Owing to the advantages of low price-per-unit-bit, high integration, and ability to simultaneously perform read and write operations, DRAMs have enjoyed widespread use in commercial applications. In the meantime, a phenomenon referred to as “soft error” can be caused in DRAM devices by a loss of charge that was stored in a capacitor due to external factors, thereby causing malfunction of DRAMs. In order to prevent the occurrence of soft error, a method of enhancing the capacitance of a capacitor has been suggested. The capacitance of the capacitor can be enhanced by increasing the surface area of a lower electrode. Although many studies have been investigated in the area of increasing the lower electrode surface area, challenges are presented in formulating practical manufacturing processes due to the ever increasing high level of integration of semiconductor devices.
FIG. 1 is a cross-sectional view of a conventional DRAM device including a capacitor.
Referring to FIG. 1, a first interlayer insulating layer 3 is formed on a semiconductor substrate 1 having a cell array region and a peripheral circuit region. The first interlayer insulating layer 3 is patterned to form contact holes exposing the semiconductor substrates 1 on the cell array region and the peripheral circuit region respectively, and the contact holes are filled with a conductive material to form a lower electrode contact plug 5A and a peripheral circuit contact plug 5B. An etch stop layer 7 and a second interlayer insulating layer 9 are sequentially formed on the resulting structure.
The second interlayer insulating layer 9 and the etch stop layer 7 are sequentially etched in the cell array region to form the lower electrode contact plug 5A and a storage node hole 11 exposing the first interlayer insulating layer 3 around the lower electrode contact plug. After a lower electrode layer 13 is conformally stacked on the resulting structure, a planarization process is carried out to form a lower electrode 13 covering a bottom and an inner sidewall of the storage node hole 11. A dielectric layer 15 and an upper electrode layer 17 are sequentially stacked and patterned on the semiconductor substrate 1. The third interlayer insulating layer 19, the second interlayer insulating layer 9 and the etch stop layer 7 are sequentially patterned in the peripheral circuit region to form a metal contact hole.(not shown) exposing the peripheral circuit contact plug 5B, and the metal contact hole is filled with a conductive material to form a metal contact plug 21.
In the conventional architecture shown in FIG. 1, methods are available for increasing the height of the lower electrode as a method for increasing the surface area of the lower electrode to increase capacitance. In one such method, the thickness of the second interlayer insulating layer where the lower electrode is positioned is increased. However, if the thickness of the second interlayer insulating layer is increased, the process burden is also increased because large amount of etching is required when the metal contact hole is formed. In addition, because of the large amount of etching required, the peripheral circuit contact plug 5b may not be exposed, and, as a consequence, the metal contact plug 21 and the peripheral circuit contact plug 5b may not be electrically connected. Thus, the reliability of the semiconductor device can be degraded.