The present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory (DRAM) incorporated with a self-refresh circuit.
It is indispensable for a DRAM to refresh each memory cell in order to retain data stored therein. The refresh operation must be performed on each memory cell at least once within a period during which each memory cell can hold data stored therein without destroying it. This period is called hereinafter "data hold-enable period".
In one way of refreshing, external control signals such as a row address strobe (RAS) signal and a column address strobe (CAS) signal are employed. The so-called RAS-only-Refresh and CAS-before-RAS Refresh are well known in the art. While a refresh cycle, i.e. a time interval of each refresh operation, is designated by a DRAM maker, in order to satisfy a demand for a system design from users, the DRAM maker supplies different types of DRAMs with respect to a required refresh period. For example, one type DRAM specifies that a refresh operation is required to be performed 1024 times within a 16 msec period. Such a DRAM is called 1K-type DRAM. Another type DRAM is called 2K-type DRAM and specifies that a refresh operation has to be performed 2048 times with a 32 msec period. Still another type DRAM is called 4K-type DRAM and specifies that a refresh operation has to be performed 4096 times within a 64 msec period.
Assuming here that those 1K-type, 2K-type and 4K-type DRAMs have the same memory capacity as one another and hence have the same number of word lines as one another, the word lines are energized in response to every refresh operation one by one in the 4K-type DRAM, two by two in the 2K-type DRAM and four by four in the 1K-type DRAM. Therefore, the DRAM maker produces, in place of producing chips for those DRAMs independently of one another, a common chip for them but equipped with a bonding option function. In the common chip with the bonding option, two bonding pads are provided, each of which is connected to a power potential or a ground potential by a bonding wire. The potential levels of the bonding pads are supplied to a row address buffer and/or a row address decoder. Thus, when the combination of the potential levels designates the 1K-type, four word lines are energized simultaneously by some refresh address. In the case of designating the 2K-type or 4K-type, two word lines or one word line is energized by that refresh address.
In another way for refreshing, a DRAM itself performs a refresh operation by a self-refresh circuit incorporated therein, as disclosed in Digest of Technical Papers of "1990 IEEE International Solid State Circuits Conference", pp. 230, 231 and 303. The self-refresh circuit includes a refresh timer and a refresh address generator. The timer generates a refresh timing signal in a predetermined cycle such that all the memory cells are refreshed at least once within the data hold-enable period. This predetermined cycle is called a self-refresh cycle. Each time the refresh timing signal is generated, a word line selected by a row address from the refresh address generator is energized to refresh the memory cells connected to the selected word line. The refresh address is thereafter incremented or decremented by one.
Consider now that the self-refresh circuit would be incorporated into the above-mentioned chip with the bonding option. In this case, if the 1K-type is designated, since four word lines are energized simultaneously each time a self-refresh operation is performed, it is performable to expand the self-refresh cycle. Otherwise, each of word lines is energized many times within the data hold-enable period, resulting in increase in power consumption. In the case of designating the 4K-type, on the other hand, since only one word line is energized by every refresh operation, it is preferable to make the self-refresh cycle short. Otherwise, the energization of all the word lines is not completed within the data hold-enable period, and some word lines may remain without being energized. Thus, the self-refresh cycle should be varied in accordance with the designation by the bonding option.
For this purpose, a plurality of refresh timers would be provided to generate a plurality of refresh timing signals having refresh cycles different from one another. A selector would be also required to select one of the refresh timing signals in accordance with the designation by the bonding option. As result, a DRAM thus produced has complicated hardware.