1. Field of the Invention
The present invention relates to a field of electronic, such as semiconductor, devices, and, more specifically, to improving write operation for phase change random access memory.
2. Discussion of Related Art
Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) are widely used to store information in an electronic system, such as a computer. However, both DRAM and SRAM are volatile memory which will lose stored information whenever electrical power is interrupted.
Consequently, it is desirable to store critical information in non-volatile memory, especially for a portable electronic system, such as a mobile internet device (MID).
Flash memory is a type of non-volatile memory. However, flash memory may not be scaleable to very small dimensions since information is stored as charge in a floating gate, and reducing the number of electrons per bit will degrade the reliability of stored information.
In addition, flash memory typically uses NAND or NOR architecture. A NAND device erases a page at a time while a NOR device erases a block at a time.
In contrast, phase-change RAM (PRAM) is a type of non-volatile memory that is scaleable to extremely small dimensions since each bit of information is stored as resistance in a material, which is a physical property that can be measured very precisely.
The PRAM also erases a bit at a time since every memory cell may be addressed separately by selecting a combination of bit line and word line.
However, a write operation is slower than a read operation for PRAM. Furthermore, the write operation is asymmetric. In particular, a SET phase (0) is slower to write than a RESET phase (1) when binary logic is used.
Accordingly, it is desirable to improve the write operation for PRAM.