1. Field of the Invention
The present invention relates to a MOS transistor (MOS=metal oxide semiconductor) having a source region, a gate region, a drain region, and a drift region in an SOI wafer (SOI=semiconductor on insulator), whereby the SOI wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region, and whereby the active semiconductor layer, at least in one part of the drift region, is thicker than in the source region.
The invention relates further to a method for producing a MOS transistor structure having a source region, a gate region, a drain region, and a drift region in an SOI wafer, whereby the SOI wafer has a carrier layer, which bears an insulating intermediate layer, and whereby the insulating intermediate layer bears an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region, and whereby the active semiconductor layer, at least in one part of the drift region, is thicker than in the source region.
2. Description of the Background Art
A MOS transistor and method are known from U.S. Pat. No. 5,338,965. In this publication, a DMOS transistor is provided, whose source and channel regions lie on a field oxide. A resurf drift region is electrically insulated by a pn-junction from the substrate material. High leakage currents result because the drift region is not dielectrically insulated.
A DMOS transistor (DMOS=double diffused MOS) is a MOS transistor, whose channel is produced not solely by photolithographic processes, but by diffusion processes. According to current understanding, a DMOS transistor compared with a conventional CMOS transistor (complementary metal oxide semiconductor) is characterized in that a drift region is provided between an edge of a control gate and a drain region of the transistor, i.e., a region in which the movement of the charge carriers is effected only through an electrical field prevailing between the opposite ends of the region. In a lateral DMOS transistor (LDMOS transistor), the drift region extends in the lateral direction, between the edge of the control gate and the drain region removed therefrom in the lateral direction.
A sideways, lateral growth in a trench, whose bottom is covered by oxide, is known from U.S. Pat. No. 5,481,126. This prior-art method is not advantageous because a connection to the bulk wafer remains in the finished structure.
A structure is known from EP 1 049 156 A1 in which a trench structure (trench) is surrounded by oxide. The trench is filled by an ELO process (ELO=epitaxial lateral overgrowth) with use of a seed, which was produced in the bottom of the trench by opening the oxide layer. A seed is understood to be a surface structure of a single crystal to which atoms attach during the ELO process and thereby assume the crystal orientation of the single crystal. The seed opening is then closed by a trench. This is a costly and space-consuming structure. Only SOI islands insulated from one another can be fabricated.
According to U.S. Pat. No. 6,204,098 B1, insulated islands are produced by epitaxial growth. The active silicon layer of the SOI wafer serves as the seed. Here as well, only insulated islands of the same height can be produced.
In U.S. Pat. No. 5,686,755, a DMOS transistor is presented, whose source and channel regions are within a buried oxide. The resurf driftzone (Resurf=reduced surface field) is electrically insulated from the substrate material by means of a pn junction. Because the drift zone is not dielectrically insulated, high leakage currents develop.
BCDMOS technology (BCDMOS=bipolar-CMOS-DMOS) is generally understood to be integrated circuits and their manufacturing processes, in which high-voltage DMOS features are combined with low-voltage CMOS and bipolar properties on a chip. A voltage of five volts is a typical example of low voltage, whereas high voltage in this context is understood to be values of up to more than one hundred volts. DMOS transistors are used as high-voltage components, whereby the high voltage can be applied between the drain region and the source region of the transistor.
In contrast to the bipolar technology, in MOS technologies there is a systematic approach to structure miniaturization by scaling of the length scale for component dimensions. Important electrical properties of MOS transistors do not depend on individual lengths, but rather on the ratios of transistor width and channel length. Based on this dependence, in principle all lengths and widths within a circuit can be reduced by a mutual scaling factor k, without a change in electrical properties.
The scale miniaturization of components in BCDMOS circuits with vertical SOI insulation, however, is limited by the aforementioned contradictory requirements. To minimize leakage currents at high temperatures, the active silicon thickness in the CMOS portion should be very thin, so that source and drain lie upon the buried oxide. In the DMOS drift region, the active silicon layer in contrast should be thicker to increase the dielectric strength.