In traditional GOA (Gate On Array) circuit designs, during the output turning-off holding phase (i.e., the phase after outputting a gate driving signal at a high level), the gate electrode of the output transistor is at a potential of −8V, while the output terminal for the gate driving signal is also at a potential of −8V, so that the gate-source voltage of the output transistor is 0V during the output turning-off holding phase, which may lead to abnormal display due to the relatively higher leakage current in a high-temperature environment. As illustrated in FIG. 1, a voltage control circuit uses an NAND gate 10 to control the gate-source voltage of the output transistor MO to be less than 0V during the output turning-off holding phase, i.e., to control the reverse control voltage Vgl2 to be input into the gate electrode of the transistor MO when the potential of the pull-up node PU is controlled to be at a low level. However, because the NAND gate 10 includes a P-type transistor as the first control transistor MC1, the voltage control circuit has poor process compatibility. The circuit as illustrated in FIG. 1 further includes a storage capacitor Cs, a second control transistor MC2 included by the NAND gate 10, an output terminal for gate driving signal OUTPUT, and a first clock signal CLK.