The use of correlated double sampling (CDS) is advantageous in Infrared Readout Integrated Circuits (IR ROIC), and other image sensor types. In short, CDS is the subtraction of inherent pixel noise from the measured signal. This can be achieved by separately reading out the reset level (signal present in a pixel when substantially no charge has been integrated) and the measurement signal (the signal generated by integration of photon-driven charge). However, separate readout of the two signals creates complicated readout schemes and issues with power consumption, noise, and limited bandwidth.
Accordingly, in-pixel CDS circuits and methods have been developed to implement CDS at the pixel level, such that only a single read of the corrected pixel signal is necessary. For example, in-pixel CDS circuits are disclosed in pending United States Patent Application Publication Number 20140016027, entitled “CTIA In-Pixel Correlated Double Sampling with Snapshot Operation for IR Readout Integrated Circuits,” filed May 31, 2013, the contents of which are hereby incorporated by reference in their entirety.
FIG. 1 depicts a prior art circuit configured for in-pixel CDS. The circuit is connected to a photodetector 101, e.g. an infrared photodetector. Current flows from the IR detector element as photons are received. The current output is accumulated as charge on the capacitor 104 of a charge transimpedance amplifier 103. A feedback loop across capacitor 104 is present, which stores photointegrated signal on the capacitor during the read phase. The output of the buffer amplifier is thus a voltage representative of the amount of current that has been integrated. The amplifier is connected in series with pixel output circuitry across a CDS capacitor 106, such that the output side of the circuit is AC-coupled to the input side of the circuit. The amplifier output voltage is read across the capacitor by a source follower 110 that connects to pixel output components, for example a snapshot switch 111, storage capacitor 112, and an additional source follower amplifier 113.
During the reset phase, the reset switch 105 in the amplifier feedback loop is closed, shorting the capacitor and causing the amplifier reset level signal to be output by the amplifier. Meanwhile, switch 109 is closed, applying a bias voltage to the output side of the CDS capacitor. The reset signal becomes stored on the CDS capacitor. Switch 105 is released at the end of the reset phase, causing a transient disturbance of the amplifier, which settles within a matter of nanoseconds. Switch 109 is released after a settling interval, e.g. 10-100 ns after the reset switch is opened. The time period between release of the reset switch and the release of the voltage clamping switch will be referred to herein as the “clearance interval.”
Thereafter, the integration period begins again, during which time the voltage signal representing the integration of charge by the IR detection unit is output by the CTIA. Integration causes a voltage swing in the output of the CTIA, such voltage swing being read across the CDS Capacitor in opposition to the stored reset signal. The resulting final signal across the CDS capacitor at the end of the integration period is thus the differential between the integration signal and the previously stored reset signal. Accordingly, the resulting output signal (read by a source follower voltage buffer, for example) is a corrected integration signal from which reset signal has effectively been subtracted.
The CDS scheme outlined above advantageously eliminates noise. However, due to the timing of the operations, the potential for a lost signal or “fold-over” error artifact exists. During the clearance interval, current from the IR detector causes charge to accumulate on the CTIA capacitor and a voltage signal is output by the CTIA to the CDS capacitor. Because the clamping switch is still closed during the clearance interval, this integration does not get coupled through to the output side of the CDS capacitor. The CDS capacitor is effectively off-line during the clearance interval, and the signal representing photon-generated current from the photodetector is lost, this signal referred to as “lost signal” herein. Once the clamping switch is released at the end of the clearance interval, integrated charge results in a voltage signal that is accumulated across the CDS capacitor and is not lost. However, in the case of a bright input stimulus, the lost signal is non-negligible, creating an under-measurement error. In the event of an extremely bright stimulus, the CTIA can saturate before the clamping switch is released, such that no signal is recorded during the subsequent integration period, when a signal corresponding to a bright stimulus should have been recorded. Thus, the signal can be said to have “folded-over.”
A foldover event is depicted in FIG. 2., which is an idealized plot of signal strength vs. input signal level in a photodetector. As input signal increases, the reference voltage (line 204) signal increases. Pixel signal (line 202) increases as well, until the pixel becomes saturated. In an in-pixel CDS scheme, where output signal (line 202) is the difference between pixel signal and reference signal, the output signal begins to decline after pixel saturation, this decline in signal being a foldover (203).
Accordingly, there is a need in the art to improve in-pixel CDS techniques by adding the ability to record lost signal, and to detect and correct for foldover events.