1. Field of the Invention
Embodiments of the present invention generally relate to methods and apparatus for modeling and characterization of features formed on semiconductor substrates.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors, resistors, and the like) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. Circuit density has a pronounced importance as the speed and number of functions a circuit can execute increases along with the density of the circuit structure. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
Due to the reduction in dimensions, copper has become a choice metal for filling the sub-micron, high aspect ratio interconnect features needed for the next generation of ultra large scale integration. This is because copper and its alloys have lower resistivities and significantly higher electromigration resistance as compared to previously used materials. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed.
Test chips have long been used to predict performance of features formed on the chip and to detect process variation during manufacture. For example, test chips have been used to predict and monitor CMP performance of silicon oxide and tungsten structures for interconnect applications. As both silicon oxide and tungsten are relatively hard and have long planarization distances, test chips having test structures on the order of 4 mm2 or larger were developed and used for these materials.
However, the dramatic changes seen in the processes and materials used to manufacture today's smaller, faster circuits has not seemed to change the test chip design mentality. Traditional millimeter scale test structures are still being used in copper design prediction and process monitoring even though the copper and low-k materials currently used in damascene and dual damascene processes are significantly softer than tungsten and oxide.
It has been observed that small features may not perform as predicted by the larger, conventional test chips and that, therefore, the phenomena and understanding gained from these large test structures cannot be scaled down to predict the performance of small feature chips. In addition, it has been observed that how copper is initially polished plays a critical role in final device performance.
Thus, there is a need for an improved method and apparatus for modeling and characterization of small-feature integrated circuits.