1. Field of the Invention
The present invention relates to a communication between processors for a switch, and in particular to a communication apparatus between processors for a switch and a method of the same which are implemented based on a hub method.
2. Description of the Background Art
FIG. 1 is a view schematically illustrating the blocks for a communication between processors in order to explain a communication method between the processors in a conventional switch. As shown therein, the conventional switch formed of a plurality of processors 1xcx9cn includes one master processor Proc1(1), and a plurality of slave processors Proc2xcx9cProcN(2xcx9cn), which are connected in a multi-drop type.
The master processor 1 and the slave processors 1xcx9cn perform a communication between processors based on a method which is directed to occupy a certain serial BUS and transmit a data based on a Round Robin method. Here, the master processor 1 includes a synchronous signal generator 10 for generating a frame synchronous signal FRS and a counter synchronous clock signal ASTCLK, and a BUS controller 20-1 for controlling a BUS. The slave processors 2xcx9cn include bus controllers 20-2xcx9c20-n for controlling the BUS.
FIG. 2 is a block diagram illustrating a detailed construction of the synchronous signal generator 10 of the master processor 1. As shown therein, the synchronous signal generator 10 includes a counter circuit 11 for providing 32 times bus occupancies and generating a frame synchronous signal FRS which is a reference signal for initializing a local counter of each processor, a clock signal generator 13 for generating a 1.25 MHz clock signal, and a buffer circuit 12 for generating a counter synchronous clock signal ASTCLK for synchronizing the local counter of each processor in accordance with a clock signal generated by the clock generator 13.
In addition, FIG. 3 is a block diagram illustrating the BUS controllers 20-1xcx9c20-n provided at each processor 1xcx9cn. As shown therein, the BUS controllers 20-1xcx9c20-n each include a counter circuit 21 for an inherent arbitration address AA[6:0] in accordance with a frame synchronous signal FRS applied from the synchronous signal generator 10, a counter synchronous clock signal ASTCLK, and a bus occupancy signal AST applied from other processors, a control circuit 22 for exchanging a data transmission requiest signal RTS and a data transmission verification signal CTS with a communication chip (not shown) and generating a bus occupancy signal AST for informing to other processors when the same occupied the BUS, and a buffer circuit 23 for transmitting and receiving a data and clock signal TxData, TxCLK/RxData, RxCLK outputted from the communication chip (not shown) to/from other processors by synchronizing to a certain clock signal BRCLK via the BUS.
FIG. 4 is waveforms of the signals FRS, ASTCLK, AST, BRCLK and DATA.
The communication between processors at a conventional switch will be explained with reference to the accompanying drawings.
First, the synchronous signal generator 10 of the master processor 1 supplies a frame synchronous signal FRS and a counter synchronous clock signal ASTCLK which are used for an arbitration at each processor, to the BUS controllers 20-1xcx9c20-n of the processors 2xcx9cn via the BUS.
The processors 1xcx9cn connected via the BUS initializes the counter circuit 21 based on an arbitration address value AA[6:0] given when mounting a system when the frame synchronous signal FRS is activated.
In the case that the bus occupancy signal AST is in an inactivation state, namely, no processors occupy the bus, the processors 1xcx9cn operate a corresponding counter circuit 21 in accordance with a counter synchronous signal ASTCLK applied from the BUS controller 20-1 of the master processor 1 and counts up its arbitration address value AA[6:0]. In the case that the bus occupancy signal AST is in an activation state, namely, other processors occupy the bus, the counting operation is stopped.
For example, the operation that the third processor 3 transmits data will be explained.
The counter circuit 21 of the BUS controller 20-3 of the processor 3 counts up the arbitration address value AA[6:0] which is given when the bus occupancy signal AST is in an inactivation state on the BUS. When the count value reaches a certain value(which is set to have a bus occupancy right), when there is a data transfer request(RTS: Request To Send) from a communication chip(not shown), the control circuit 22 of the processor 3 activates the bus occupancy signal AST for thereby informing other processors of that the control circuit 22 occupies the bus.
In this case, other processors stop the counting operation. The buffer circuit 23 of the processor 3 transmits a transmission data TxData and a transmission clock signal TxCLK from the communication chip(not shown) to a certain destination via the BUS.
When the data transmission is completed, the processor 3 inactivates the bus occupancy signal AST, and then the counter circuits 21 of each processor begin to count.
When the count value reaches a certain value, the processor has a bus use right, and the processor having the bus use right activates the bus occupancy signal AST in the case that there are data to be transmitted and transmits itself data to a certain destination.
The above-described operation is performed by a certain number. For example, 32 times bus occupancy rights are given, and the synchronous signal generator 10 of the master processor 1 generates a frame synchronous signal FRS and initializes the local counter 21. The above-described operation is repeatedly performed.
In the above-described communication method between the processors of the conventional switch, since all processors are connected via one communication line, if an error occurs in one of a plurality of processors, a critical problem occurs in the entire communication system. In particular, when mounting and unmounting the processors, the communication of the previously installed processors may be affected, so that the contents of the communication is damaged.
In addition, since the signals for implementing a synchronization between processors are distributed, a malfunction may occur. Since the arbitration address is manually set in a back plane when installing the system, the arbitration address may be erroneously recognized due to a certain small error or a contact error.
Accordingly, it is an object to provide a communication apparatus between processors of a switch and a method of the same which are capable of implementing an accurate communication among a plurality of processors by providing a hub circuit at a switch for overcoming the problems which are encountered in the conventional art.
To achieve the above object, there is provided a communication method between processors for a switch which includes a step in which a processor, which has a data to be transmitted, among a plurality of processors transmits a first control signal to the buffer, a step in which the error detection unit detects whether an error occurs at a processor which generates the first control signal and informs the controller of a result of the detection, a step in which the controller transmits the first control signal based on a certain arbitration method, selects one processor among a plurality of the processors which do not have an error, and transmits a second control signal to a corresponding processor, a step in which a corresponding processor which receives the second control signal from the controller transmits a transmission data and clock signal, a step in which the error detection unit detects whether an error occurs at the processor which transmits the data and informs the controller of a result of the detection, a step in which, when an error occurs, the controller stops a data transmission of a corresponding processor, a step in which, when an error is not occurred, a corresponding processor which finished to transmit the data, releases the first control signal, and a step in which the data transmission is completed by releasing the second control signal applied to the processor, wherein a communication system includes a plurality of processors, a buffer for receiving and transmitting a control signal or a data from/to the processors, a controller for controlling the data transmissions of the processors, and an error detection unit for detecting whether an error occurs at the processor.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.