The present invention is generally related to improving the architecture of cache and memory devices in order to reduce the average time to access data from the main memory (RRAM) as well as overcome various challenges associated with data storage and movement between CPU registers and RRAM memory devices. One such challenge includes addressing cache management issues, such as reconciling the transfer and access of bits when CPU cache accesses bits of a size that are different from RRAM memory page size.
Another disclosed invention relates to techniques to overcome limitations associated with status polling on an RRAM device (e.g., standalone memory). Polling is the process of periodically reading the status of an operational activity until a device indicates the operation is complete. For instance, a non-volatile flash memory requires status polling to determine whether a read or write command has completed, regardless of whether an error occurs or does not occur. As next generation non volatile memory technologies become faster and faster as compared to flash memories, current polling mechanisms are becoming antiquated and tend to consume a substantial amount of bus bandwidth which results in a lowering of system performance. As such, new methods for determining whether errors occur upon completion of a device operation are needed.