1. Field of the Invention
The invention relates to a universal test platform and related test method for latch-up, and more particularly, to a universal test platform and related test method for latch-up implemented by a test platform for developing a chip.
2. Description of the Prior Art
Please refer to FIG. 1 showing a cross-sectional view of a conventional CMOS and its associated parasitic circuit. In an integrated circuit (IC) two problems may occur: either a short circuit between a drain voltage node (VDD) and a source voltage node (VSS) may be formed due to a parasitic circuit effect, or the circuit cannot normally operate due to sudden voltage change when the power is off. Such kind of influence by a parasitic circuit is called a latch-up phenomenon. When a large amount of electrons is injected into an N-type substrate and received by a P-type well, the voltage drop between parasitic resistors Rs and Rw caused by a large current formed by the electrons is sufficient to conduct a low voltage in equivalent transistors T1, T2, resulting in a short circuit between VDD and VSS so that latch-up phenomenon occurs and the system fails. In order to prevent system failure due to latch-up, the resistance of the parasitic resistors Rs, Rw need to be lowered or the gain constant of the equivalent transistors be reduced. The gain constant of the equivalent transistors can be reduced by improving the IC manufacturing process. In addition, connecting the base of an N-type field transistor to the source voltage node can reduce the resistance of the parasitic resistors Rs, Rw, so that latch-up phenomenon is less possible to occur.
Please refer to FIG. 2 showing a conventional method for testing latch-up phenomenon in an IC 10. During the test, a test voltage 12 and an ammeter 14 is first installed between a power end (Vs) and a ground end (GND), and a trigger current 16 is then applied between a pin under test (PUT) and GND so that the ammeter 14 measures a current between Vs and GND. If latch-up phenomenon does not occur, the trigger current 16 is increased to continue the test. Such kind of latch-up test is standardized by JEDEC EIA/JESD78, in which each pin is required to sustain a trigger current 16 of 200 mA. The trigger current 16 increases 25 mA each time starting from 25 mA, and during the test the current measured between Vs and GND cannot exceed 100 mA. Generally, each different IC has its own test platform for developing and testing its functions. The test platform provides a parameter measurement unit (PMU), which is a set of power supplies providing current source and voltage source, as well as a set of units for measuring current and voltage. It is easy to execute latch-up test by PMU. Therefore, IC makers develop test programs on a test platform for different types of ICs according to JEDEC EIA/JESD78, to ensure that each IC passes the latch-up test.
As described above, latch-up phenomenon due to the parasitic circuit of the IC itself causes malfunction of the circuit system; thus each IC is required to pass the latch-up test by complying with the JEDEC EIA/JESD78 standard to ensure that the system operates normally. Since different ICs have their own test platforms, the IC makers can develop test programs on the test platforms for different types of ICs according to JEDEC EIA/JESD78 standard. However, it is troublesome to develop test programs for every different IC, since there are various types of ICs.