The present invention relates to a nonvolatile semiconductor memory device and a method for driving the same. More particularly, the present invention relates to a nonvolatile semiconductor memory device functioning as a flash EEPROM employing a two-layer gate electrode structure including floating gate and control gate electrodes and to a method for driving the same.
In recent years, a flash EEPROM is increasingly required to perform a rewrite operation using a single power supply at a low voltage and a high-speed read operation at a low voltage. A xe2x80x9clow voltagexe2x80x9d herein refers to about 1.5 V to about 3.3 V.
Various types of flash EEPROMs are now available. For example, a flash EEPROM developed by a certain corporation injects channel hot electrons (CHE) from a drain into a floating gate electrode while writing, and ejects the electrons out of the electrode into a source by using FN tunneling current while erasing. Hereinafter, a flash EEPROM of this type will be called a xe2x80x9cCHE-type flash EEPROMxe2x80x9d. The CHE-type flash EEPROM is advantageous in that the circuit configuration and fabrication process thereof can be implemented by extending EPROM technologies. However, since current of about 500 xcexcA should be consumed per cell for writing, a rewrite operation using a single power supply at 5 V can be performed relatively easily. But a rewrite operation using a single power supply at 2.5 V or less is hard to realize.
Another flash EEPROM, ejecting electrons out of a floating gate electrode into a drain while writing and injecting electrons into the floating gate electrode while erasing by using, in both operations, FN tunneling current over the entire surface of a channel, has prevailed in the art recently. Examples of flash EEPROMs of this type include a DINOR-type flash EEPROM disclosed in U.S. Pat. No. 5,283,758 and an AND-type flash EEPROM disclosed in U.S. Pat. No. 5,592,415. Flash EEPROMs of those types use the FN tunneling current for both writing and erasing. Accordingly, the level of current required for writing and erasing may be low and therefore a rewrite operation can be performed using a single power supply at a low voltage (e.g., 2.5 V). Hereinafter, a flash EEPROM of such a type will be called a xe2x80x9cdrain-side FN-FN type flash EEPROMxe2x80x9d.
A memory cell structure for a drain-side FN-FN type flash EEPROM and a method for driving the same will be described, and the problems thereof will be clarified. And then another conventional nonvolatile semiconductor memory device and a method for driving the same will be described as an exemplary means for solving the problems. It is noted that the drain-side FN-FN type flash EEPROM exemplified below is supposed to be a DINOR-type flash EEPROM.
First, a memory cell structure for a drain-side FN-FN type flash EEPROM and a method for driving the same will be described.
FIG. 24 is a cross-sectional view illustrating an exemplary memory cell structure for a drain-side FN-FN type flash EEPROM. As shown in FIG. 24, the memory cell includes: a P-type semiconductor substrate 101; a deep N-type well 102; a P-type well 103; a gate insulating film 104; a floating gate electrode 105; an interelectrode insulating film 106; a control gate electrode 107; a drain diffusion layer 108; and a source diffusion layer 109.
The flash EEPROM shown in FIG. 24 has fundamentally the same memory cell structure as that of the CHE-type flash EEPROM, but is somewhat different from the latter in the shapes of the diffusion layers. Specifically, in a memory cell of the CHE-type flash EEPROM, a source diffusion layer is deeper than a drain diffusion layer. Conversely, in a memory cell of the drain-side FN-FN type flash EEPROM, the drain diffusion layer 108 is deeper than the source diffusion layer 109. This structural difference comes from the locations of the tunneling current utilized by the flash EEPROMs of these two types. That is to say, the CHE-type flash EEPROM uses the tunneling current flowing between the source diffusion layer and the floating gate electrode, whereas the drain-side FN-FN type flash EEPROM uses the tunneling current flowing between the drain diffusion layer 108 and the floating gate electrode 105.
Next, the array structure of the drain-side FN-FN type flash EEPROM and an erasing method thereof will be described. FIG. 25(a) is an electric circuit diagram illustrating voltages applied for simultaneously erasing data from all the memory cells in the drain-side FN-FN type flash EEPROM as a conventional nonvolatile semiconductor memory device. And FIG. 25(b) is a cross-sectional view illustrating how electrons move during the erase operation.
First, the array structure of the drain-side FN-FN type flash EEPROM will be described with reference to FIG. 25(a). As shown in FIG. 25(a), each memory word line M.W-0, 1, 2 interconnects the control gate electrodes 107 of memory cells arranged on the same row in the direction X. Each source line S-0, 1, 2 interconnects the source diffusion layers 109 of memory cells arranged on the same row in the direction X. And each bit line B-0, 1, 2 interconnects the drain diffusion layers 108 of memory cells arranged on the same column in the direction Y.
In this manner, the source lines are disposed in parallel to the word lines for memory cells (i.e., the memory word lines) and the bit lines are disposed vertically to the memory word lines.
Next, an erasing method will be described. FIG. 25(a) illustrates the voltages applied for simultaneously erasing data from all of the nine memory cells illustrated. As shown in FIG. 25(a), a voltage of +7 V is applied to the memory word lines M.W-0, 1, 2 and a voltage of xe2x88x927 V is applied to the P-type well PW. As a result, the potential difference between the control gate electrode 107 and the surface of the channel is 14 V at every memory transistor. Consequently, as shown in FIG. 25(b), tunneling current flows from the entire surface region of the channel into the floating gate electrode 105, whereby electrons are injected into the floating gate electrode 105. In this case, the threshold voltage of the memory transistor is about 4 V.
Next, a writing method will be described. FIG. 26(a) is an electric circuit diagram illustrating voltages applied for writing data into only one memory cell located at the center of the array and selected from the nine memory cells included in the drain-side FN-FN type flash EEPROM. And FIG. 26(b) is a cross-sectional view illustrating how electrons move during the write operation. As shown in FIG. 26(a), a voltage of xe2x88x929 V is applied to the memory word line M.W-1 connected to the memory cell to which data is selectively written (i.e., a selected memory cell). And voltages of +5 V and 0 V are respectively applied to the bit line B-1 connected to the selected memory cell and to the P-type well (PW) 3. As a result, the potential difference between the control gate electrode 107 and the drain diffusion layer 108 is 14 V at the selected memory cell. Consequently, as shown in FIG. 26(b), tunneling current flows from the floating gate electrode 105 into the drain diffusion layer 108 and electrons are ejected out of the floating gate electrode 105. In this case, the threshold voltage of the memory transistor is about 1.2 V.
Also, in order to prevent the data from being erroneously written into non-selected memory cells, a voltage of 0 V is applied to the other memory word lines M.W-0, 2 and to the other bit lines B-0, 2. As a result, the potential difference between the control gate electrode 107 and the drain diffusion layer 108 can be no greater than 9 V at the non-selected memory cells and it is possible to prevent the data from being erroneously written into the non-selected memory cells.
Next, a reading method will be described. FIG. 27(a) is an electric circuit diagram illustrating voltages applied for reading data from only one memory cell located at the center and selected from the nine memory cells included in the drain-side FN-FN type flash EEPROM as a nonvolatile semiconductor memory device. And FIG. 27(b) is a cross-sectional view illustrating how electrons move during the read operation. As shown in FIG. 27(a), a voltage of 3 V is applied to the memory word line M.W-1 connected to a memory cell from which data is selectively read out (i.e., a selected memory cell). And voltages of 1 V and 0 V are respectively applied to the bit line B-1 connected to the selected memory cell and the P-type well PW. As a result, if the selected memory transistor is in a write state (VT=1.2 V), then the current flows as shown in FIG. 27(b). On the other hand, if the selected memory transistor is in an erase state (VT=4 V), then the current does not flow. Based on the current flow, the existence of data stored can be sensed.
The drain-side FN-FN type flash EEPROM has the following three problems.
The first problem concerns the unsatisfactory reliability thereof. In accordance with the method used by the drain-side FN-FN type flash EEPROM utilizing the tunneling current between the drain diffusion layer 108 and the floating gate electrode 105, a potential difference of about 5 V is required between the drain diffusion layer 108 and the P-type well 103. In addition, since a voltage of xe2x88x929 V is applied to the control gate electrode 107, band-to-band tunneling current is generated between the drain diffusion layer 108 and the P-type well 103. As a result, holes are generated owing to the band-to-band tunneling current in the vicinity of a boundary region between the P-type well 103 and the drain diffusion layer 108, and are trapped in the gate insulating film 104. Consequently, the reliability is deteriorated.
The second problem pertains to the power consumed during writing. In the drain-side FN-FN type flash EEPROM utilizing the tunneling current flowing between the drain diffusion layer 108 and the floating gate electrode 105, the band-to-band tunneling current is generated as described above. Accordingly, write current of about 100 nA is required per cell.
And the third problem relates to the lower limit of the power supply voltage during reading. A memory cell of the drain-side FN-FN type flash EEPROM is constituted by only one memory transistor. Accordingly, if the variation in threshold voltages is to be controlled after the write operation has been performed, then a write depth (i.e., the threshold voltage) should be controlled on a bit-by-bit basis, which requires a too much complicated controller. Moreover, since the controllable variation of the threshold voltage is as small as about 0.8 V, the threshold voltages after the write operation has been performed are distributed in the range from about 0.8 V to about 1.6 V. Thus, in order not to cause erroneous reading, the power supply voltage cannot be less than about 2.5 V, even through the voltage is preferably further lower.
In order to solve these problems, a nonvolatile semiconductor memory device, in which a memory cell includes a sidewall-shaped select transistor, was proposed in U.S. Pat. No. 5,402,371, for example. Hereinafter, the nonvolatile semiconductor memory device and a method for driving the same will be described.
FIG. 28 is a cross-sectional view illustrating a memory cell structure for the nonvolatile semiconductor memory device. As shown in FIG. 28, a select transistor is formed as a sidewall on the side face of the floating gate electrode 105 and the control gate electrode 107, and includes a select gate electrode 113. A lateral interelectrode insulating film 112 is interposed between the select gate electrode 113 and the floating gate and control gate electrodes 105, 107. Also, a gate insulating film 111 is interposed between the select gate electrode 113 and the substrate.
In order to solve the three problems of the drain-side FN-FN type flash EEPROM, the memory cell shown in FIG. 28 uses the sidewall-shaped select gate electrode 113 made of polysilicon, thereby realizing a rewrite operation using the tunneling current flowing between the floating gate electrode 105 and the entire surface of the channel for both writing and erasing. In accordance with such a rewrite method, no potential difference is required between the drain diffusion layer 108 and the P-type well 103, and therefore no band-to-band tunneling current is generated. Accordingly, no holes resulting from the band-to-band tunneling current are generated. As a result, the reliability problem can be solved and the current consumed during rewriting can be reduced. Also, even when the threshold voltage of a memory transistor is negative, the threshold voltage of the memory cell may be determined by the threshold voltage of the select transistor additionally provided.
Such a rewrite method using the tunneling current flowing between the floating gate electrode 105 and the entire surface of the channel for both writing and erasing was also implemented by a NAND-type flash EEPROM. Also, it was already proved that this method is more advantageous in terms of reliability (i.e., the number of times satisfactory rewriting is ensured). In addition, this method enables a rewrite operation using a single power supply at a lower voltage. However, since the NAND-type flash EEPROM has an array structure of a NAND type, this flash EEPROM requires an adversely long random access time. On the other hand, the nonvolatile semiconductor memory device shown in FIG. 28 has an array structure of a NOR type, and therefore can effectively perform random access in a shorter time. However, the cell size of the NOR-type flash EEPROM is larger than that of the NAND-type flash EEPROM.
In sum, the nonvolatile semiconductor memory device shown in FIG. 28 has a NOR-type array structure enabling random access at a higher speed and realizes a rewrite operation using the tunneling current between the floating gate electrode 105 and the entire surface of the channel for both writing and erasing. Hereinafter, the array structure of the conventional nonvolatile semiconductor memory device shown in FIG. 28 and a method for driving the same will be described.
FIG. 29(a) is an electric circuit diagram illustrating voltages applied for simultaneously erasing data from all the memory cells, each including the sidewall-shaped select transistor of the conventional nonvolatile semiconductor memory device as shown in FIG. 28. And FIG. 29(b) is a cross-sectional view illustrating how electrons move during the erase operation.
First, the array structure of the nonvolatile semiconductor memory device will be described. As shown in FIG. 29(a), each memory word line M.W-0, 1, 2 interconnects the control gate electrodes 107 of memory cells arranged on the same row in the direction X. Each select word line S.W-0, 1, 2 interconnects the select gate electrodes 113 of memory cells arranged on the same row in the direction X. Each source line S-0, 1, 2 interconnects the source diffusion layers 109 of memory cells arranged on the same row in the direction X. And each bit line B-0, 1, 2 interconnects the drain diffusion layers 108 of memory cells arranged on the same column in the direction Y. In this manner, the source lines are disposed in parallel to the word lines for memory cells (i.e., the memory word lines and the select word lines) and the bit lines are disposed vertically to the word lines.
Next, an erasing method will be described. FIG. 29(a) illustrates the voltages applied for simultaneously erasing data from all of the nine memory cells illustrated. As shown in FIG. 29(a), a voltage of xe2x88x927 V is applied to the memory word lines M.W-0, 1 and 2 and a voltage of +7 V is applied to the P-type well PW. As a result, the potential difference between the control gate electrode 107 and the surface of the channel is 14 V at every memory transistor. Accordingly, as shown in FIG. 29(b), tunneling current flows from the floating gate electrode 105 into the entire surface region of the channel, whereby electrons are ejected out of the floating gate electrode 105. In this case, the threshold voltage of the memory transistor is about xe2x88x921 V. Since each memory cell is a serial connection of a select transistor (VT=0.6 V) and a memory transistor (VT=xe2x88x921 V), the threshold voltage of each memory cell is 0.6 V.
Next, a writing method will be described. FIG. 30(a) is an electric circuit diagram illustrating voltages applied for writing data into only one memory cell located at the center and selected from the nine memory cells, each including the sidewall-shaped select transistor of the nonvolatile semiconductor memory device as shown in FIG. 28. And FIG. 30(b) is a cross-sectional view illustrating how electrons move during the write operation. As shown in FIG. 30(a), a voltage of +9 V is applied to the memory word line M.W-1 connected to a memory cell to which data is selectively written (i.e., a selected memory cell). And a voltage of xe2x88x925 V is applied to the select word line S.W-1 and the bit line B-1 that are connected to the selected memory cell and to the P-type well PW. As a result, the potential difference between the control gate electrode 107 and the surface region of the channel is 14 V at the selected memory transistor. Accordingly, as shown in FIG. 30(b), tunneling current flows from the entire surface region of the channel into the floating gate electrode 105, whereby electrons are injected into the floating gate electrode 105. In this case, the threshold voltage of the memory transistor is about 4 V. Since each memory cell is a serial connection of a select transistor (VT=0.6 V) and a memory transistor (VT=4 V), the threshold voltage of each memory cell is 4 V.
Also, in order to prevent the data from being erroneously written into non-selected memory cells, a voltage of xe2x88x925 V is applied to the other memory word lines M.W-0, 2 and select word lines S.W-0, 2, and a voltage of 0 V is applied to the other bit lines B-0, 2. As a result, the potential difference between the control gate electrode 107 and the surface region of the channel can be no greater than 9 V at the non-selected memory cells and it is possible to prevent the data from being erroneously written into the non-selected memory cells. In this case, a voltage of xe2x88x925 V is applied to all the select word lines S.W-0, 1, 2, because all the select transistors should be turned OFF. For example, if a voltage of 0 V is applied to the select word line S.W-1 connected to the selected memory cell, the select transistor of the memory cell is turned ON. Then, the voltage of xe2x88x925 V, applied to the selected bit line B-1, is unintentionally transmitted through the source line S-1 to the non-selected memory cells connected in common with the selected memory cell in the direction Y. As a result, erroneous writing is caused.
Next, a reading method will be described. FIG. 31(a) is an electric circuit diagram illustrating voltages applied for reading data from only one memory cell located at the center and selected from the nine memory cells, each including the sidewall-shaped select transistor of the nonvolatile semiconductor memory device as shown in FIG. 28. And FIG. 31(b) is a cross-sectional view illustrating how electrons move during the read operation. As shown in FIG. 31(a), a voltage of 3 V is applied to the memory word line M.W-1 connected to the memory cell from which data is selectively read out (i.e., a selected memory cell). And voltages of 3 V, 1 V and 0 V are respectively applied to the select word line S.W-1 and the bit line B-1 that are connected to the selected memory cell and to the P-type well PW. As a result, if the selected memory transistor is in an erase state (VT=0.6 V), then electrons move from the source diffusion layer 109 toward the drain diffusion layer 108 and the current flows as shown in FIG. 31(b). On the other hand, if the selected memory transistor is in a write state (VT=4 V), then the current does not flow. Based on the current flow, the existence of data stored can be sensed.
The nonvolatile semiconductor memory device shown in FIG. 28 and the method for driving the same have the following three advantages over the drain-side FN-FN type flash EEPROM shown in FIG. 24.
The first advantage lies in the improvement of reliability. In accordance with the method used by the drain-side FN-FN type flash EEPROM shown in FIG. 24 utilizing the tunneling current between the drain diffusion layer 108 and the floating gate electrode 105 for writing, a potential difference of about 5 V is required between the drain diffusion layer 108 and the P-type well 103. In addition, since a voltage of xe2x88x929 V is applied to the control gate electrode 107, band-to-band tunneling current is generated. As a result, holes are generated owing to the band-to-band tunneling current and trapped in the gate insulating film 104. Consequently, the reliability is deteriorated. By contrast, the flash EEPROM shown in FIG. 28 including the sidewall-shaped select gate electrode uses the tunneling current flowing between the floating gate electrode 105 and the entire surface region of the channel of the memory transistor for both writing and erasing. Accordingly, no potential difference is generated between the drain diffusion layer 108 and the P-type well 103 and no band-to-band tunneling current is generated. Thus, since almost no holes are generated, the deterioration of reliability can be suppressed.
The second advantage pertains to the reduction of power consumed during writing and erasing. In the drain-side FN-FN type flash EEPROM shown in FIG. 24 utilizing the tunneling current flowing between the drain diffusion layer 108 and the floating gate electrode 105 of the memory transistor, the band-to-band tunneling current is generated as described above. Accordingly, write current of about 100 nA is required per memory cell. On the other hand, in the flash EEPROM shown in FIG. 28, no band-to-band tunneling current is generated during either writing or erasing. Thus, write current of only 1 nA or less is required per memory cell. That is to say, the flash EEPROM shown in FIG. 28 can operate while consuming one-hundredth or less power compared with the drain-side FN-FN type flash EEPROM. As a result, the area occupied by an internal voltage step-up circuit can be reduced. Alternatively, since the number of bits, to which data can be written simultaneously, increases, a write time can be decreased or a rewrite operation can be performed at an even lower voltage.
And the third advantage relates to the lower limit of the power supply voltage during reading. A memory cell of the drain-side FN-FN type flash EEPROM is constituted by only one memory transistor. Accordingly, if the variation in threshold voltages is to be controlled after the write operation has been performed, then a write depth (i.e., the threshold voltage) should be controlled on a bit-by-bit basis, which requires a too much complicated controller. Moreover, since the controllable variation of the threshold voltages is as small as about 0.8 V, the threshold voltages after the write operation has been performed are distributed within a range from about 0.8 V to about 1.6 V. Thus, in order not to cause erroneous reading, the power supply voltage cannot be less than about 2.5 V, even through the voltage is preferably further lower. By contrast, in the flash EEPROM shown in FIG. 28, a memory cell has a serial connection of two transistors, i.e., select transistor and memory transistor. Accordingly, even when the threshold voltage of the memory transistor is negative, the threshold voltage of the memory cell is no lower than the threshold voltage of the select transistor. Thus, the threshold voltage of the memory cell can be set somewhere between about 0.6 V and about 0.8 V. By narrowing the voltage range in this manner, reading can be performed at as low as about 1.5 V, for example.
However, in the flash EEPROM shown in FIG. 28, the area occupied by a memory cell increases. In the drain-side FN-FN type flash EEPROM, a memory cell is constituted by a single memory transistor. On the other hand, since the memory cell structure of the flash EEPROM shown in FIG. 28 requires a select transistor to operate, the area occupied by a memory cell increases for that part. Nevertheless, by using the sidewall-shaped select transistor, the increase of the area occupied by a single memory cell is less large than the case of additionally providing a select transistor for the drain-side FN-FN type flash EEPROM.
Therefore, the nonvolatile semiconductor memory device shown in FIG. 28 and a method for driving the same can be regarded as having the above described three advantages over the drain-side FN-FN type flash EEPROM. However, in actually implementing the device and the method, the following two problems are likely to be caused.
The first problem concerns the reliability of the lateral interelectrode insulating film 112 formed between the select gate electrode and the control gate electrode.
During the write operation shown in FIG. 30(a) and 30(b), when voltages of 9 V and xe2x88x925 V are respectively applied to the memory word line M.W-1 and the select word line S.W-1 connected to the selected memory cell, a potential difference of 14 V (i.e., 5+9 V) is generated in the lateral interelectrode insulating film 112 between the control gate electrode 107 and the select gate electrode 113. However, in order to carry out the fabrication process thereof efficiently, the lateral interelectrode insulating film 112 and the gate insulating film 111 of the select transistor should be formed during the same process step. On the other hand, the lateral thickness (i.e., the gate length) of the select gate electrode 113 shaped like a sidewall cannot be too large and at most about 0.2 xcexcm in view of the process efficiency. Accordingly, the thickness of the gate insulating film 111 of the select transistor should be about 4 nm. or more to make the select transistor exert its originally intended function. Thus, the thickness of the lateral interelectrode insulating film 112 is at most about 10 nm even when the effect of accelerated oxidation of polysilicon is taken into consideration. That is to say, since a potential difference of 14 V is generated in the lateral interelectrode insulating film 112 having a thickness as small as 10 nm during writing, insulation breakdown possibly happens to deteriorate the reliability.
The second problem relates to the source-to-drain breakdown voltage of the select transistor including the select gate electrode 113.
During writing, the drain diffusion layer 108 of the select transistor in each of the non-selected memory cells connected in common with the selected memory cell to the same word line has a potential of about 0 V. And the source diffusion layer 109 thereof has a potential of about xe2x88x925 V. Though the source line is open, the potential of the source diffusion layer 109 is substantially equal to that of the P-type well. As a result, a potential difference of about 5 V is generated between the drain diffusion layer 108 and the source diffusion layer 109. However, considering that the gate length of the select gate electrode 113 is at most about 0.2 xcexcm, the source-to-drain breakdown voltage of the select transistor is at most about 2.5 V, which is far lower than 5 V. Accordingly, during writing, since the select transistors of the non-selected memory cells are not turned OFF, erroneous writing possibly happens.
The conventional nonvolatile semiconductor memory device shown in FIG. 28 and the method for driving the same have these problems, and therefore it is doubtful whether the device and the method can be implemented satisfactorily.
The object of the present invention is to provide a nonvolatile semiconductor memory device functioning as a flash EEPROM, in which a memory cell includes a memory transistor and a select transistor, and a method for driving the same. Specifically, the device of the present invention is configured to prevent the lateral interelectrode insulating film between the select transistor and the memory transistor from being deteriorated and to suppress erroneous writing resulting from an insufficient source-to-drain breakdown voltage of the select transistor.
The present invention takes the measures of: using an independent transistor, not a sidewall-shaped transistor, as the select transistor; disposing electrically independent source lines in parallel to or vertically to respective bit lines (i.e., vertically to or in parallel to respective word lines); and providing a plurality of electrically independent well regions for the respective bit lines.
A first nonvolatile semiconductor memory device according to the present invention has an array of memory cells arranged in columns and rows over a well region of a semiconductor substrate. Each of the memory cells includes a memory transistor including: a first gate insulating film, which is formed on the semiconductor substrate and has such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode, which is formed on the first gate insulating film and where charges are storable; an interelectrode insulating film formed on the floating gate electrode; and a control gate electrode formed on the interelectrode insulating film. Each memory cell further includes: a select transistor including a second gate insulating film formed on the semiconductor substrate and a select gate electrode formed on the second gate insulating film, the select transistor being disposed on the semiconductor substrate to be spaced apart from the memory transistor; an intermediate diffusion layer formed in a region of the semiconductor substrate and located between the memory transistor and the select transistor; and source/drain diffusion layers formed in the semiconductor substrate to interpose a region underlying the memory transistor, a region underlying the select transistor and the intermediate diffusion layer therebetween.
Since the first device of the present invention has such a structure as preventing band-to-band tunneling current from being generated, the reliability can be improved and the power consumption during writing and erasing can be reduced. In addition, since this device includes a select transistor, the threshold voltage of a memory cell can be defined by the stable threshold voltage of the select transistor. Accordingly, the power supply voltage may be low during reading. Moreover, the memory transistor and the select transistor are provided to be spaced apart from each other. Thus, unlike a conventional nonvolatile semiconductor memory device where a memory cell includes a sidewall-shaped select gate electrode, the deterioration in reliability of a lateral interelectrode insulating film is not an issue in this device of the present invention. Furthermore, the gate length of the select gate electrode of the select transistor can be set at a sufficiently large value. Accordingly, the breakdown voltage of the select transistor is no longer insufficient. Consequently, a nonvolatile semiconductor memory device, exhibiting excellent characteristics and having an easily implementable structure, is realized.
In one embodiment of the present invention, the select transistor may be disposed between the source diffusion layer and the intermediate diffusion layer, while the memory transistor may be disposed between the drain diffusion layer and the intermediate diffusion layer. And the first device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same row and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In an alternate embodiment, the select transistor is preferably disposed between the source diffusion layer and the intermediate diffusion layer, while the memory transistor is preferably disposed between the drain diffusion layer and the intermediate diffusion layer. And the first device preferably further includes: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In such an embodiment, the source lines extend in parallel to the bit lines (i.e., along the columns) and are provided electrically independently from each other for the respective bit lines. Accordingly, in this structure, no leakage current is generated between bit lines through a source line. As a result, not only the above effects are attained, but also erroneous writing can be prevented without fail while electrons are injected into the floating gate electrode of the memory transistor. Moreover, the circuit size of a decoder controlling a select word line can be reduced and a high-speed operation is realized.
In another embodiment of the present invention, the select transistor may be disposed between the drain diffusion layer and the intermediate diffusion layer, while the memory transistor may be disposed between the source diffusion layer and the intermediate diffusion layer. And the first device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In such an embodiment, since the source lines extend in parallel to the bit lines (i.e., along the columns) and are provided electrically independently for the respective bit lines, the effects described above can be attained. In addition, since the configuration of a bit line driver including a read circuit can be simplified, this structure is advantageous to a high-speed read operation.
In still another embodiment, the well region is divided into a plurality of electrically isolated regions corresponding to the respective columns.
In such an embodiment, the potential in each well region can be controlled on a bit line basis. Thus, the potential difference between a source or drain diffusion layer and an associated well region can be 0 V and no breakdown voltage needs to be secured for this part. As a result, the reliability can be further improved.
In still another embodiment, the select transistor may be disposed between the source diffusion layer and the intermediate diffusion layer, while the memory transistor may be disposed between the drain diffusion layer and the intermediate diffusion layer. And the first device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In an alternate embodiment, the select transistor is preferably disposed between the drain diffusion layer and the intermediate diffusion layer, while the memory transistor is preferably disposed between the source diffusion layer and the intermediate diffusion layer. And the first device preferably further includes: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In such an embodiment, the source lines are provided in parallel to the bit lines and electrically independently from each other for the respective bit lines. Accordingly, in this structure, no leakage current is generated between bit lines through a source line. As a result, erroneous writing can be prevented without fail while electrons are injected into the floating gate electrode of the memory transistor.
In still another embodiment, the first device may further include a circuit for controlling a potential in each said select word line, the circuit being a high-power transistor optimized to operate at about a power supply voltage such that the potential in the select word line is variable in the range from a ground potential to the power supply voltage.
In such an embodiment, the circuit size of a decoder can be reduced and a high-speed read operation is realized.
In still another embodiment, the first device may further include a circuit for controlling a potential in each said bit line, the circuit being a high-power transistor optimized to operate at about a power supply voltage such that the potential in the bit line is variable in the range from a ground potential to the power supply voltage.
In still another embodiment, the second gate insulating film of the select transistor and the first gate insulating film of the memory transistor are formed at the same thickness during the same process step such that a potential difference between the select gate electrode of the select transistor and the well region causes an electric field of 5 MV/cm or less to be applied to the second gate insulating film.
In such an embodiment, the thickness of the second gate insulating film may be adjusted at such a value as limiting the voltage applied thereto to 5 V or less, while the thickness of the first gate insulating film may be adjusted at such a value as allowing electrons to be tunneled.
A second nonvolatile semiconductor memory device according to the present invention has an array of memory cells arranged in columns and rows over a well region of a semiconductor substrate. Each memory cell includes a memory transistor including: a first gate insulating film, which is formed on the semiconductor substrate and has such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode, which is formed on the first gate insulating film and where charges are storable; an interelectrode insulating film formed on the floating gate electrode; and a control gate electrode formed on the interelectrode insulating film. Each memory cell further includes source/drain diffusion layers formed in the semiconductor substrate to interpose a region underlying the memory transistor therebetween. The well region is divided into a plurality of electrically isolated regions corresponding to the respective columns.
Since the second device has a structure making the potential in a well region controllable on a bit line basis, the potential difference between a source or drain diffusion layer and an associated well region can be 0 V and no breakdown voltage needs to be secured for this part. As a result, satisfactory reliability can be ensured without providing a select transistor, and therefore the device size can be further miniaturized while attaining the above effects.
In one embodiment of the present invention, the second device preferably further includes: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line.
In another embodiment of the present invention, the first or second device may further include: a plurality of laterally isolating regions, formed along the columns and between the respective well regions and made of a semiconductor or an insulator of an opposite conductivity type to that of the well regions, for laterally isolating the respective well regions from each other; and a plurality of vertically isolating regions, each said vertically isolating region being interposed between an associated one of the well regions and the semiconductor substrate and made of a semiconductor or an insulator of the opposite conductivity type to that of the well regions.
In such an embodiment, the well regions can be electrically isolated from each other for the respective columns with more certainty.
A first method for driving a nonvolatile semiconductor memory device according to the present invention is a method for driving the first nonvolatile semiconductor memory device. In accordance with this method, tunneling current, allowing electrons to pass through the first gate insulating film of the memory transistor, is used while the electrons are ejected out of the floating gate electrode and while the electrons are injected into the floating gate electrode.
In accordance with this method, a nonvolatile semiconductor memory device, having such a structure as preventing the deterioration in reliability of the lateral interelectrode insulating film and the shortage of a breakdown voltage unlike a conventional nonvolatile semiconductor memory device, is driven so as to prevent band-to-band tunneling current from being generated. Accordingly, write and erase operations can be performed with low power consumption while suppressing the deterioration in characteristics of the nonvolatile semiconductor memory device.
In one embodiment of the present invention, an erase operation is performed by applying a ground potential or a first negative voltage to the control gate electrode of the memory transistor and a second voltage, higher than the first voltage, to the well region and thereby ejecting electrons out of the floating gate electrode of the memory transistor.
In such an embodiment, tunneling current flows through the entire surface of the first gate insulating film and electrons move from the floating gate electrode toward the well region. As a result, the band-to-band tunneling current is not generated, and therefore an erase operation can be performed with low power consumption and without deteriorating the reliability.
In another embodiment of the present invention, a threshold voltage of the memory transistor is negative after the erase operation has been performed.
In such an embodiment, if the threshold voltage of the select transistor is set at a relatively low positive voltage, the threshold voltage of a memory cell can be easily defined by the threshold voltage of the select transistor, even through the threshold voltage of the memory transistor is variable. Accordingly, a read operation can be performed at a low voltage.
In still another embodiment, the select transistor may be disposed between the source diffusion layer and the intermediate diffusion layer, while the memory transistor may be disposed between the drain diffusion layer and the intermediate diffusion layer. And the device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same row or the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line. Then, a write operation may be performed by applying: a first positive voltage to the control gate electrode of one of the memory transistors, to which transistor data is written; a second voltage, lower than the first voltage, to the control gate electrodes of the other memory transistors, to which the data is not written; a third voltage, lower than the first voltage, to the well region; a fourth voltage, equal to or higher than the third voltage, to the bit line connected to the memory transistor, to which the data is written; and a fifth voltage, higher than the fourth voltage, to the bit lines connected to the memory transistors, to which the data is not written, and thereby selectively injecting electrons into the floating gate electrode of the memory transistor, to which the data is written.
In such an embodiment, by controlling the voltages of the drain diffusion layer and the well region in the vicinity of the memory transistor during writing, the voltage applied to the first gate insulating film of the memory transistors in the non-selected memory cells can be smaller than the voltage applied to the first gate insulating film of the memory transistor in the selected memory cell. As a result, erroneous writing can be prevented with more certainty.
In still another embodiment, the select transistor may be disposed between the drain diffusion layer and the intermediate diffusion layer, while the memory transistor may be disposed between the source diffusion layer and the intermediate diffusion layer. And the device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line. Then, a write operation may be performed by applying: a first positive voltage to the control gate electrode of one of the memory transistors, to which transistor data is written; a second voltage, lower than the first voltage, to the control gate electrodes of the other memory transistors, to which the data is not written; a third voltage, lower than the first voltage, to the well region; a fourth voltage, equal to or higher than the third voltage, to the source line connected to the memory transistor, to which the data is written; and a fifth voltage, higher than the fourth voltage, to the source lines connected to the memory transistors, to which the data is not written, and thereby selectively injecting electrons into the floating gate electrode of the memory transistor, to which the data is written.
In such an embodiment, by controlling the voltages of the source diffusion layer and the well region in the vicinity of the memory transistor during writing, the voltage applied to the first gate insulating film of the memory transistors in the non-selected memory cells can be smaller than the voltage applied to the first gate insulating film of the memory transistor in the selected memory cell. As a result, erroneous writing can be prevented with more certainty. In addition, since erroneous writing can be prevented without the application of a negative voltage to the bit line of the selected memory cell, simplified control is realized during writing.
In still another embodiment, the well region may be divided into a plurality of electrically isolated regions corresponding to the respective columns. And the device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line. Then, a write operation may be performed by applying: a first positive voltage to the control gate electrode of one of the memory transistors, to which transistor data is written; a second voltage, lower than the first voltage, to the control gate electrodes of the other memory transistors, to which the data is not written; a third voltage, lower than the first voltage, to the well region where the memory transistor, to which the data is written, is located; and a fourth voltage, higher than the third voltage, to the well regions where the memory transistors, to which the data is not written, are located, and thereby selectively injecting electrons into the floating gate electrode of the memory transistor, to which the data is written.
In such an embodiment, by independently controlling the respective potentials in the well regions that are electrically isolated from each other for the respective columns, the potential difference between a source or drain diffusion layer of a memory cell and an associated well region can be substantially eliminated. Accordingly, since no breakdown voltage should be secured, the structure can be simplified.
In still another embodiment, each said source line may interconnect the respective source diffusion layers of the memory cells arranged on the same row and associated with the source line, and the third voltage, applied to the well region, is applied to the select gate electrodes of the select transistors associated with the write operation such that the select transistors are turned OFF.
In such an embodiment, even when the breakdown voltage of a select transistor is low, erroneous writing can be prevented with much more certainty.
In still another embodiment, a threshold voltage of the memory transistor is equal to or higher than a ground potential after the write operation has been performed.
In such an embodiment, a control voltage can be set relatively high during reading. Accordingly, erroneous reading resulting from the unintended activation of the memory transistors in the non-selected memory cells can be prevented.
In still another embodiment, the device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line. Then, the device may be driven such that a potential in each said select word line is variable between a ground potential and a power supply voltage during erase, write and read operations.
In such an embodiment, a decoder for controlling a select word line may be a very small transistor having a breakdown voltage as low as a power supply voltage. As a result, the circuit area of the decoder used for controlling a select word line can be reduced and a high-speed operation is realized.
In still another embodiment, the device may further include: a plurality of memory word lines, each said memory word line interconnecting the control gate electrodes of the respective memory transistors in the memory cells arranged on the same row and associated with the memory word line; a plurality of select word lines, each said select word line interconnecting the select gate electrodes of the respective select transistors in the memory cells arranged on the same row and associated with the select word line; a plurality of source lines, each said source line interconnecting the source diffusion layers of the memory cells arranged on the same column and associated with the source line; and a plurality of bit lines, each said bit line interconnecting the drain diffusion layers of the memory cells arranged on the same column and associated with the bit line. Then, the device may be driven such that a potential in each said bit line is variable between a ground potential and a power supply voltage during erase, write and read operations.
In such an embodiment, a decoder for controlling a bit line may be a very small transistor having a breakdown voltage as low as a power supply voltage. As a result, the circuit area of the decoder used for controlling a bit line can be reduced and a high-speed operation is realized.
In still another embodiment, the device may be driven such that a potential difference between the select gate electrode of each said select transistor and the well region causes an electric field of 5 MV/cm or less to be applied to the second gate insulating film during erase, write and read operations.
In such an embodiment, since the voltage applied to the second gate insulating film can be reduced, a method for driving a nonvolatile semiconductor memory device is realized without deteriorating the reliability thereof owing to the deterioration of the second gate insulating film.
A second method for driving a nonvolatile semiconductor memory device according to the present invention is a method for driving the second nonvolatile semiconductor memory device. In accordance with this method, tunneling current, allowing electrons to pass through the first gate insulating film of the memory transistor, is used while the electrons are ejected out of the floating gate electrode and while the electrons are injected into the floating gate electrode.
In accordance with this method, a nonvolatile semiconductor memory device, having such a structure as preventing the deterioration in reliability of the lateral interelectrode insulating film and the shortage of a breakdown voltage without using a select transistor unlike a conventional nonvolatile semiconductor memory device, is driven so as to prevent band-to-band tunneling current from being generated. Accordingly, write and erase operations can be performed with low power consumption while suppressing the deterioration in characteristics of the nonvolatile semiconductor memory device.
In one embodiment of the present invention, an erase operation may be performed by applying a first positive voltage to the control gate electrode of the memory transistor and a second voltage, lower than the first voltage, to the well region and thereby injecting the electrons into the floating gate electrode of the memory transistor.
In such an embodiment, unlike the case an erase operation is performed by ejecting electrons out of the floating gate electrode, excessive erasure does not happen. Accordingly, erroneous reading can be prevented with the variation in threshold voltages of a memory transistor suppressed.
In another embodiment, a threshold voltage of the memory transistor is preferably equal to or higher than a ground potential after the erase operation has been performed.
In such an embodiment, erroneous reading, resulting from the unintended activation of memory cells in erase state, can be prevented during a read operation.
In still another embodiment, each said memory cell may further include: a select transistor including a second gate insulating film formed on the semiconductor substrate and a select gate electrode formed on the second gate insulating film, the select transistor being disposed on the semiconductor substrate to be spaced apart from the memory transistor; and an intermediate diffusion layer formed in a region of the semiconductor substrate and located between the memory transistor and the select transistor.
If each said memory cell includes only the memory transistor, then a threshold voltage of the memory transistor is preferably equal to or higher than a power supply voltage after the erase operation has been performed.
In such a case, while the memory transistor of a selected memory cell, from which data is read out, is in erase state, the memory cell is not activated. Accordingly, erroneous reading can be prevented with more certainty.
In still another embodiment, a write operation may be performed by applying: a ground potential or a first negative voltage to the control gate electrode of one of the memory transistors, to which transistor data is written; a second voltage, higher than the first voltage, to the control gate electrodes of the other memory transistors, to which the data is not written; a third voltage, higher than the first voltage, to the well region where the memory transistor, to which the data is written, is located; and a fourth voltage, lower than the third voltage, to the well regions where the memory transistors, to which the data is not written, are located and thereby selectively ejecting electrons out of the floating to gate electrode of the memory transistor, to which the data is written.
In such an embodiment, the threshold voltage can be in a controllable write state on a bit-by-bit basis. Unlike the case an erase operation is performed by ejecting electrons out of the floating gate electrode, the variation in threshold voltages resulting from excessive erasure can be prevented. Accordingly, the variation in threshold voltages of a memory transistor, to which data is written, can be suppressed and erroneous reading can be prevented with more certainty.
In still another embodiment, a threshold voltage of the memory transistor is negative after the write operation has been performed.
In such an embodiment, the threshold voltage of a memory cell in write state is clearly different from the threshold voltage of a memory cell in erase state. Accordingly, erroneous reading can be prevented.
If each said memory cell includes only the memory transistor, a threshold voltage of the memory transistor is preferably in the range from a ground potential to a power supply voltage after the write operation has been performed.
In still another embodiment, a constant potential, close to a ground potential, is preferably established in the control gate electrodes and the well regions of the memory transistors in selected ones of the memory cells, from which data is read out, and a potential in the select gate electrodes of the select transistors in selected ones of the memory cells is preferably set in the range from a threshold voltage of the select transistors to the power supply voltage.
In such an embodiment, a read operation is performed by setting a potential in a memory word line, which is activated with a delay because of the complicated configuration of a decoder, at a constant value in both the selected memory cell and the non-selected memory cells and controlling a potential in a select word line with a decoder having a simpler configuration. Accordingly, reading can be performed at a high speed.
In still another embodiment, a potential in the control gate electrodes of the memory transistors in selected ones of the memory cells, from which data is read out, is set at the power supply voltage.
In such an embodiment, the power supply voltage may be lower.