Typically, a semiconductor device is biased at Direct Current (DC) and/or modulated at relatively low frequencies, for example, below ten megahertz (MHz). Concurrently, the device can generate, amplify, and/or manipulate signals at much higher frequencies (for example, above one gigahertz (GHz)). A requirement for optimizing the device design at DC and low frequencies, on one hand, and at high frequencies are clashing and difficult or impossible to satisfy simultaneously. For example, FIG. 1 shows an illustrative heterostructure field effect transistor (HFET) 2A according to the prior art, which can be operated as a switch. When implemented in circuits such as power converters, the device dynamic on-resistance of the HFET 2A should be minimized. As a result, it is desirable to minimize a total channel length between the source electrode S and drain electrode D (e.g., the sum of the distances LGS, LG, and LGD). However, in order for the HFET 2A to withstand high voltage levels without breakdown, the distance, LGD, between the gate electrode G and the drain electrode D must be sufficiently large, since most of the external voltage drop will occur between these two electrodes. Therefore, the requirements for large breakdown voltage and low on resistance are clashing.
FIG. 2 shows an alternative HFET 2B, which illustrates one approach to address the breakdown problem, according to the prior art. HFET 2B includes a dielectric 3A, 3B deposited in the gate-source and gate-drain spacing and a field-modulating plate (FP). While the field-modulating plate FP is shown connected to the gate electrode G, other approaches connect one or several field-modulating plates FP to the source electrode S, drain electrode D, and/or the gate electrode G. Regardless, the field-modulating plate FP decreases a peak field near the electrode edge by splitting it into two or more peaks, thereby increasing the breakdown voltage of the HFET 2B. However, the field-modulating plate FP increases the inter-electrode and electrode-semiconductor capacitances, and thus decreases a maximum operating frequency for the HFET 2B.
FIGS. 3A and 3B show an illustrative HFET 2C in the on state and the off state, respectively, when being operated as a radio frequency (RF) switch according to the prior art. In the on state illustrated in FIG. 3A, a conducting channel 4 exists between the source electrode S and the drain electrode D. To turn the HFET 2C off, a corresponding bias is applied at the gate electrode G, which removes the channel under the gate electrode G thereby disconnecting the drain electrode D from the source electrode S. However, this disconnection is only true at low frequencies. At high frequencies as illustrated in FIG. 3B, a capacitive coupling is present between the source and drain sides of the channel which reduces a maximum operating frequency for the HFET 2C. If the channel 4 had been fully depleted in the entire source—drain spacing, the device capacitance would be lower and the maximum operating frequency would be higher.