The present invention relates generally to integrated circuit memory devices and, more particularly, to a bitline twisting structure for memory arrays incorporating reference wordlines.
Semiconductor integrated circuits typically are formed by MOS (metal oxide semiconductor) or by bipolar transistors that are integrated at a top planar major surface of a silicon chip. Electrical interconnections between various transistors, as well as between certain transistors and access pins typically located along the periphery of the chip, have typically taken the form of two (or more) “levels” of interconnections, i.e., electrically conducting lines in the form of metallization stripes running along two (or more) essentially planar surfaces that are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Interconnection vias (windows) in the insulating layers are provided whenever they are needed in accordance with the desired circuit interconnections.
In a variety of such integrated circuits, such as random access memories (RAM) and logic circuits, the electrical circuit requires interconnections by means of a number of electrically conducting lines which conveniently are geometrically arranged in the form of an array of mutually parallel metallization stripes. For example, in a DRAM (dynamic RAM), within an array of parallel bitlines the unavoidable parasitic capacitance across each pair of neighboring bitlines gives rise to electrical cross-coupling or “cross-talk” therebetween.
More specifically, during read operations, only a small differential voltage (e.g., on the order of about 100 mV) between the true bitline and the complementary bitline is used by the sense amplifier since a larger differential voltage would increase the read time. Thus, in order to reduce the effects of a large mutual capacitance between adjacent bitlines, the complementary bitlines within a given bitline pairs are twisted at various locations along the length thereof. Generally, even numbered bitline pairs are twisted at different locations with respect to adjacent odd numbered bitline pairs. For example, along the entire length of a plurality of bitline pairs, the even numbered bitline pairs might be twisted just once at the middle of the total length, while the odd numbered pairs are twisted once at ¼ of the total length, and again at ¾ of the total length. Because differential sense amplifiers use the both lines of a bitline pair to sense differential voltages, bitline twisting allows for a disturbing signal on neighboring bitline to impact both the true and complementary bitline of a bitline pair in the same way, without impact to the differential voltage.
One specific type of DRAM sensing scheme is what is known as a half-VDD sensing scheme, in which both the true and complementary bitlines are precharged to a value approximately halfway between a logic “1” voltage (VDD) and a logic “0” voltage (ground). When a cell is coupled to the precharged bitline, the voltage thereof will then slightly increase or decrease, depending on the value of the bit stored in the cell, thus creating a differential with respect to the complementary bitline still at VDD/2. However, for reasons known to those in the art, a ground sensing scheme may present a desirable alternative, wherein the bitline pair is precharged or restored to ground prior to a read operation. Because of the precharging to ground, reference wordlines needed to place a reference voltage (e.g., VDD/2) on either the bitline or the complementary bitline in order to be able to read a “0” bit.
Unfortunately, the use of bitline twisting complicates such reference wordline schemes, in that reference cells for each “region” are required. In existing layouts, the reference cell regions tend to be centrally located so as to reduce the physical proximity between a reference cell and the regions supported by the cell. On the other hand, a central location of a reference region has a negative impact on available device real estate, due to the additional devices associated with a reference region.
Accordingly, it would be desirable to configure a bitline twisting scheme such that the reference cell regions could be moved to the outer ends of the bitlines, while still being in relatively close proximity to the cell regions supported thereby.