In recent years, solid-state drives (SSDs) have been developed as data storage devices, each using NAND flash memories (hereinafter referred to as “flash memories” in some cases) that are rewritable nonvolatile memories.
The SSD is configured to perform an error check and correction (ECC) process before the data read from any flash memory is transferred to a host system provided. Hereinafter, the error check and correction (ECC) process will be referred to as “ECC process” in some cases.
The SSD transfers data in which no errors have been detected in the ECC process or data which has been corrected in the ECC process to the host system. The SSD performs the ECC process not only on the data to be accessed in a read process (also known as “user data”), but also on data such as logical block addresses (LBAs) contained in a data format of specific units (e.g., sectors).
In the SSD, an error correction process is performed on any errors detected in the ECC process. The error correction process has a prescribed error correction capability. If too many errors for this capability are detected, they cannot be corrected. Assume that at most eight error bits, if detected in the user data and LBAs, can be corrected. Then, the data cannot be corrected if 9 error bits are detected in the data.
If it is determined that the data cannot be corrected, the data is read again from the flash memory, and the ECC process is again performed on the data. The ECC process performed again will decrease the read efficiency of the SSD.