1. Field of the Invention
The invention relates in general to an electrostatic discharge (ESD) protective device for an integrated circuit (IC) and its fabrication, and more particularly to an ESD protective device with a low threshold voltage and a process for its fabrication.
2. Description of the Related Art
In general, ICs are easily damaged by ESD. Tolerance of ESD varies from device to device. However, a metal-oxide semiconductor field effect transistor (MOSFET) is one of the most easily damaged devices. Techniques for fabricating an IC semiconductor are now in the range of deep sub-microns, for example, less than 0.35 .mu.. Therefore, a common thickness of a deep sub-micron gate oxide is about 75.about.85 .ANG..
A cross sectional view of a conventional metal gate field threshold device is shown in FIG. 1. A P-type dopant 12 is typically implanted in a substrate 10 under a field oxide layer (FOX) 11 to increase field isolation of the metal gate field threshold device. Subsequently, the field threshold voltage is more than about 12 V.
The threshold voltage of the field oxide layer will be much larger than that of a gate oxide layer if the thickness of the gate oxide layer is much smaller than the thickness of the field oxide layer. As the trend of high integration continues, the sizes of devices must be reduced. However, as channel length is reduced, the width of the source/drain's depletion layer can be almost the same as the channel length. Therefore, the phenomenon called "punch through" tends to occur, which causes the mixing up of the two depletion layers, and the gate can barely control current.
The threshold voltage of the metal gate field threshold device is much larger than the breakdown voltage of a gate oxide layer with a thickness of about 75.about.85 .ANG., which is about 8 V. Therefore, it is now of great interest to find a low voltage ESD protective device, which is suitable for operation at less than about 3.3 V but without damaging the gate oxide layer.