1. Field of the Invention
The present invention relates to high-speed serial transfer device test method, program, and device which examine mis-synchronization failure of a high-speed serial transfer device; and particularly, relates to high-speed serial transfer device test method, program, and device which generate a test pattern in which same values are continued in serial transfer data which has undergone code conversion from the test pattern and successively transfer the data.
2. Description of the Related Arts
Conventionally, in a high-speed data transmission system such as Ethernet (R), gigabit-order high-speed data transfer is realized by use of high-speed serial transfer devices. In systems and devices using high-speed serial transfer devices, mis-synchronization and garbled-bit failure associated with it (hereinafter, referred to as “mis-synchronization”) is known to have a high percentage among device failure caused by the high-speed serial transfer devices. A PLL circuit is incorporated in the high-speed serial transfer device, and a synchronized state is maintained when the PLL circuit detects synchronization loss between received data and clock at the timing of bit change in the received data, and feeds back the synchronization loss. As described above, the timing for detecting and feeding back synchronization loss in the PLL circuit is at the timing of bit change in the received data; therefore, as long as the same values which are 0 or 1 bits are continued, the feed-back function of the PLL circuit for synchronization loss does not work. Consequently, in the high-speed serial transfer devices having low tolerance, margin, or the like with respect to frequency deviation, when the same values are continued, the data and the clock lose synchronization to an extent that signals cannot be normally reproduced, thereby causing mis-synchronization to occur. Among the high-speed serial transfer devices which have passed tests as single parts and been shipped out, some of them having low tolerance or a margin with respect to frequency deviation when mounted on a device sometimes cause mis-synchronization, etc. since noise, etc. from the entire device also affects. Therefore, tests with respect to mis-synchronization have to be effectively performed in a state in which the high-speed serial transfer device is mounted on a device or in an operating state. Conventionally, the test for examining mis-synchronization, etc. can be performed by use of a PRBS pattern (Pseudo-random Binary Sequence: pseudo-random sequential pattern) which corresponds to benchmark testing for high-speed serial transfer.    [Patent Document 1] Japanese Patent Application Laid-Open (kokai) No. 2002-084247    [Patent Document 2] Japanese Patent Application Laid-Open (kokai) No. 2002-051033    [Patent Document 3] Japanese Patent Publication (kokoku) No. H07-028211    [Patent Document 4] Title: What is a pseudorandom number sequence URL:    http://infohost.nmt.edu/tcc/help/lang/fortran/pseudo.html
However, such conventional tests for examining mis-synchronization has a problem that they require a long period of time in many cases. One reason thereof is that the test is not performed by use of a pattern which is targeting on detection of mis-synchronization of the high-speed serial transfer device. Also the test using the PRBS pattern corresponding to a benchmark test for high-speed serial transfer devices cannot be considered as an effective test for mis-synchronization and the like since the pattern is not particularly specialized for detection of mis-synchronization and the like. of the high-speed serial transfer device. Therefore, when devices involving mis-synchronization of high-speed serial transfer devices pass mass-production tests and cause failure in the field even though the high-speed serial transfer devices have passed tests as single parts and been shipped out, actions such as collection, investigation, repair, and maintenance take labor hours and time, thereby providing a factor of increased cost. In the high-speed serial transfer device, for example, serial transfer is performed after the transfer data is subjected to a code conversion; and for this code conversion, two different code conversion tables of RD− conversions and RD+ conversions are provided in accordance with running disparity RD (Running Disparity) for facilitating amplification of faint signals, and whether the conversion of the subsequent data will be an RD+ conversion or an RD− conversion is controlled depending on whether the number of 0 bits and 1 bits of the preceding converted data is the same or different. Therefore, as one function test of the high-speed serial transfer device, all of the converted data stored in the code conversion tables is desired to be sequentially caused to flow through transfer channels so as to test the function of the receiving side in the field. This test can be performed, for example if it is 8-bit/10-bit conversion, by causing 256 variations of 8-bit data to be successively flowed and converted. However, the code conversions of the high-speed serial transfer device include two different conversions, that is, RD+ conversions and RD− conversions, and which conversion is to be performed depends on the RD value of the converted data immediately preceding the test pattern. This depends on the state of the device at the moment, and cannot be externally specified. Therefore, even when 256 variations of 8-bit data are caused to flow successively, all the conversions of the code conversion tables in which RD+ conversions and RD− conversions are performed cannot be performed to transfer the converted data. Thereat, there has been no other way but to repeat causing the 256 variations of 8-bit data to flow continuously so as to achieve function examination which is statistically close to that using the all the converted data; which involves problems that the examination takes time, and the converted data which is not transferred remains although the amount thereof is small. An object of the present invention is to provide high-speed serial transfer device test method, program, and device which enable examination of mis-synchronization to be performed in a short period of time by generating a test pattern specialized for examination of mis-synchronization failure in a high-speed serial transfer device and successively transferring the pattern in a target device.