1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to 3D chip stack skew reduction with resonant clock and inductive coupling.
2. Description of the Related Art
Three-dimensional (3D) stacked chips include two or more electronic integrated circuit chips stacked one on top of the other. Three-dimensional integration offers the advantages of heterogeneous design and higher input/output (I/O) density for designers. However, clock distribution across the chip can be challenging considering wafer-to-wafer variation and even stacking chips with different technologies.