A Johnson counter produces a quotient signal having a quotient frequency Fquotient responsive to a reference clock signal having a dividend frequency Fdividend, such that Fquotient=Fdividend/(N*2), where N represents a delay measured in cycles of the reference clock signal and (N*2) is a corresponding divide factor.
Johnson counters should have flexible divide factors to produce variable output frequencies. In a known Johnson counter configuration, multiple tap points from a linear shift register having sequential buffers (hereinafter referred as signal or delay buffers) are multiplexed to choose one as feedback in order to select one of multiple possible delays and corresponding divide factors.
FIG. 1 is a diagram illustrating a known Johnson counter 100 having selectable delays in the range of one through eight (i.e., N=1, 2, 3, 4, 5, 6, 7, 8) and corresponding divide factors in the range of two through sixteen (i.e., N*2=2, 4, 6, 8, 10, 12, 14,16). Johnson counter 100 includes signal buffers 105A, 105B, 105C, 105D, 105E, 105F, 105G, 105H (collectively 105) that are serially coupled to successively delay a quotient signal 175. Each of the signal buffers 105 is further coupled to receive a clock signal 121 via a reference clock distribution network 120 to synchronize the delaying of quotient signal 175. A multiplexer 110 is coupled to multiplex an output from each one of signal buffers 105 to an inverter 115. Inverter 115 inverts quotient signal 175 received from multiplexer 110 and feeds back an inversion 180 of quotient signal 175 to signal buffer 105A.
Multiplexer 110 selects quotient signal 175 output from one of signal buffers 105 to select a delay N between one and eight, inclusive. For example, when multiplexer 110 selects the output from signal buffer 105E, quotient signal 175 is successively delayed through signal buffers 105A, 105B, 105C, 105D, and 105E to arrive at inverter 115. Johnson counter 100 is accordingly set to a delay N of five cycles of reference clock signal 121 (N=5), and a divide factor of ten (N*2=10).
Starting at the input of signal buffer 105A, the first N number of signal buffers 105 successively delays quotient signal 175. After N cycles of reference clock signal 121, quotient signal 175 emerges at the output of multiplexer 110. Inverter 115 inverts quotient signal 175 and sends inversion 180 back to the input of signal buffer 105A. Inversion 180 is successively delayed by the first N number of signal buffers 105 for additional N cycles of clock signal 121. Thus quotient signal 175 is inverted once every N cycles of reference clock signal 121 and each cycle of quotient signal 175 is equal to (N*2) cycles of reference clock signal 121. Therefore, dividend frequency Fdividend of reference clock signal 121 is divided down to quotient frequency Fquotient of quotient signal 175 by a divide factor of (N*2).
The critical path of Johnson counter 100 is limited by multiplexer 110. The complexity of multiplexer circuits increases with additional selection inputs, resulting in a corresponding performance degradation. Johnson counter 100 requires each signal buffer 105 corresponding to a desired selectable divide factor to be tapped and fed into a corresponding input of multiplexer 110. Thus the size of multiplexer 110 (i.e., the number of inputs on multiplexer 110) corresponds to the desired number of selectable divide factors. Consequently, the number of selectable divide factors is limited by the logic complexity of multiplexer 110. Large numbers result in unacceptable performance degradation, particularly when implemented in high-speed divider applications.