1. Field of Invention
This invention relates to a small area basic cell used in semiconductor integrated circuit.
2. Description of Related Art
There are several kinds of semiconductor integrated circuits. More particularly, Application Specific Integrated Circuits (ASIC), whose design is based on functions required by a user, includes gate array and cell-based schemes. In gate array semiconductor integrated circuits, a master slice is manufactured in advance which is common up to a transistor forming process. Then, it is customized at a metal wiring process depending on functions required by a user to provide a user-desired semiconductor integrated circuit in a reduced time and cost. The master slice includes a cell array, in which basic cells are regularly arranged in an array, on a surface of a semiconductor substrate. Here, the basic cell includes a plurality of transistors as basic units.
In this customizing scheme, photomasks designed and produced depending on functions needed by a user are used for the metal wiring processes. The gate array scheme also includes another customizing scheme where connections between the basic units are changed by using an energy beam such as a laser beam.
In the cell-based scheme, customization is implemented from transistor forming processes in order to provide a high density and high performance semiconductor integrated circuit. In this case, standard cells such as basic gates and a flip-flop, macro cells such as a memory and a multiplier, and/or mega cells such as a CPU and a DSP core, are designed and prepared in a cell library in advance, and then are combined in order to design an integrated circuit, which implements functions needed by a user.
Other kinds of ASICs include a Programmable Logic Device (PLD) such as a Field Programmable Gate Array (FPGA), and a Complex Programmable Logic Device (CPLD). In PLDs, a product manufactured according to a certain specification is purchased by a user and programmed according to functions needed by the user. In FPGAs, an array of programmable basic cells (also called Programmable Logic Elements, Configurable Logic Blocks, or the like) and programmable wiring are formed on a semiconductor substrate and programmed by a user.
FIG. 15 shows a plan view of a layout of an exemplary basic cell used in a conventional gate array integrated circuit. As shown, three basic cells 72 (cells 72a, 72b and 72a are shown) having the same configuration are arranged in line in the lateral direction of the figure. Each of basic cells 72 includes four P-type transistors 12 (including two large transistors 12a and two small transistors 12b), and two N-type transistors 14. The p-type transistors comprise a P-type active region 16, which is formed within an N-well (not shown) on a surface of the semiconductor substrate, and two common gate electrodes, 20a and 20b, which are placed over the P-type active region 16. The N-type transistors 14 comprise an N-type active region 18, which is formed within a P-well (not shown) and two common gate electrodes, 20a and 20b, which are placed over the N-type active region 18. On both sides of the gate electrodes of the P-type and N-type active regions are formed N-type and P-type diffusion regions, respectively. Those diffusion regions form sources and drains of the transistors.
On the surface of the active region, which is overlapped with the gate electrode, is formed a channel of the transistor. The width and length of the gate electrode in the area overlapping the active region determine a channel length and a channel width of the transistor. Usually, the width of the gate electrode in this area, which determines the channel length of the transistor, is formed to be a minimum width, which may be manufactured by a process technology used to manufacture the semiconductor integrated circuit. A current driving capacity of the transistor is determined by a ratio of the channel width and the channel length. Because the channel length is determined by the process technology to be used, it is necessary to increase a dimension of the active region in the direction where the gate electrode extends (the dimension in the vertical direction in the case of the basic cell in FIG. 15) and to increase the channel width. It increases the driving capacity of the transistor and provides a semiconductor integrated circuit which can operate with a higher frequency.
In the plane view layout of FIG. 15, a power supply line 24 is placed on the upper side of the P-type transistors 12a, 12b, and a ground line 26 is placed on the lower side of the N-type transistor 14 in the lateral direction, respectively. The power supply line 24 and the ground-line 26 are formed in the first metal wiring layer (M1). The power supply line 24 is used for supplying a power supply potential to the transistors. The ground line 26 is used for supplying a ground potential to the transistors. Though not shown, a power supply potential and a ground potential are also supplied to the N- and P-wells.
The power supply line 24 and the ground line 26 (referred to together as xe2x80x9cpower bus wiringxe2x80x9d hereinafter) have not formed yet in the master slice where processes up to the transistor forming process have been completed. However, the power bus lines are also parts of the basic cell in that they are formed in the same pattern regardless of the function needed by a user.
Further, in the basic cells 72a, 72b, two N-type transistors 22 are placed on the lower side of the ground line 26.
Cross symbols (+) shown in FIG. 15 indicate boundaries between basic cells. As shown, the basic cells 72a and 72b form a layout where they are mirror-inverted with respect to a vertical boundary line. They have the same configuration in that they include the same number of transistors having the same dimensions (channel widths and channel lengths) and conductive types. In a practical case, basic cells, which are mirror-inverted in the vertical direction as well, are placed to form a cell array.
Black dots (xe2x80xa2) shown are grid points 34 provided with a fixed pitch in the lateral and vertical directions. The grid points 34 are virtual points, which are used as a reference for positioning various components. Such points do not exist in an actual semiconductor integrated circuit. For example, contacts may be placed on the grid points 34, which are for connecting source and drain diffusion regions and gate electrodes 20a, 20b of the P-type and N-type transistors with wires in M1 layer placed on the interlayer insulating film over the transistors.
The pitch between the grid points is determined by the process technology to be used for semiconductor integrated circuit manufacturing. For example, the distance between centers of two contacts placed on diffusion regions on both sides of the gate electrode must be equal to, or larger than, a value determined by the sum of twice the distance between the gate electrode and the contact, which is needed for preventing a short between the gate electrode and the contact, and a width of the gate electrode and a dimension of a contact. For example, in a manufacturing process with a design rule (generally indicated by a minimum width of a gate electrode) of 0.25 xcexcm, when the gate electrode width and the contact dimension are assumed to be minimum, the minimum distance is 1.04 xcexcM where the gate electrode width, the contact dimension (the length of one side of a square) and the space between the gate electrode and the contact are 0.24 xcexcm, 0.32 xcexcm, and 0.24 xcexcm, respectively.
The pitch of the grid points 34 in FIG. 15 is set to the minimum value of 1.04 xcexcm in order to allow for positioning of the contacts at arbitrary grid points.
Grid points 34 are positioned in the same pitch over a whole area within the cell array region where basic cells 72a, 72b are placed in the vertical and horizontal directions. However, the pitch in the vertical direction between the grid points on the pad at the lower end of the common gate electrodes 20a and 20b and those on the diffusion regions 18 of the N-channel transistor 22 at the bottom are exceptional and set to 1.56 xcexcm.
In the illustrated structure, a plurality of grid points 34 are placed on the source and the drain of two P-type transistors 12a and two N-type transistors 14, respectively. Further, four or five pads 28 are provided for each of the gate electrodes 20a and 20b, which are common to P-type and N-type transistors 12a, 12b and 14. Further, three pads are provided for each of two gate electrodes of the transistors 22. A grid point 34 is placed on each of these pads. It is possible to place contact(s) on either one, or on several, of the plurality of grid point(s) of each of these source and drain regions and the gate electrodes, as needed.
FIG. 16 shows a plane view layout diagram of one example of a circuit block, which includes the basic cells shown in FIG. 15.
An Exclusive-OR (EXOR) gate 74 shown in FIG. 17 is formed by using three basic cells 72a, 72b and 72a shown in FIG. 15 by placing contacts at proper places, connecting them through wires in M1 layer, forming vias in the first via layer (VIAL) at proper places on top surfaces of the M1 wires, and connecting them with wires in the second metal wiring layer (M2) 60 thereabove. In FIG. 16, squares indicate contacts, and ones for connecting vertically and horizontally between them indicates wires of M1 layer. Shaded squares are vias in VIA1 layer (areas where the contacts and VIA1 vias are overlapped are also shaded), and ones for connecting vertically between them are wires of M2 layer.
FIG. 17 shows a circuit diagram corresponding to the above-described layout diagram. Input and output terminals A, B and Y in FIG. 17 are formed in positions with the same reference symbols on the layout of FIG. 16, respectively.
As shown in FIG. 17, the Exclusive-OR gate 74 includes inverters 76a, 76b and 76c, a transfer gate 82a consisting of P-type and N-type transistors 78a and 80a, and a transfer gate 82b consisting of P-type and N-type transistors 78b and 80b. In the layout figure shown in FIG. 16, two inverters 76a and 76b are formed with the right-side basic cell 72, two transfer gates 82a and 82b are formed with the center basic cell, and the inverter 76c is formed with the left-side basic cell, respectively.
A signal A is input to one end of the inverter 76a and the transfer gate 82a, and an output of the inverter 76a is input to one end of the transfer gate 82b. Further, an input signal B is input to the inverter 76b and the gates of the P-type and N-type transistors 78a and 80b, and an output of the inverter 76b is input to the gates of the N-type and P-type transistors 80a and 78b. The other end of the transfer gates 82a and 82b are shorted and input to the inverter 76c, and a signal Y is output from the inverter 76c. 
As shown in FIG. 16, positions of contacts on diffusion regions of the transistors 12 and 14 are selected depending on arrangements for connecting each of source/drain diffusion regions of transistors 12 and 14 in order to form a desired circuit block. For example, contact 30 is placed only on the lower one of the two grid points 34 provided on each of the diffusion regions on the right-hand side of the common gate electrode 20a and that between two common gate electrodes 20a and 20b of the P-type transistor 12a in the basic cell 72b at the center of FIG. 16. A M1 wire not connected to any of these diffusion regions is extended over the upper ones of the grid points on which no contact is placed.
Also, the positioning of contacts 30 on pads 28 for the gate electrodes 20a and 20b are selected depending on an arrangement for connecting each transistor. For example, only a pad 28 at the lower side of the ground line 26 is selected to place a contact 30 for the left common gate electrode 20b of the transistors 12 and 14 of the center basic cell 72b. Contacts 30 are not placed on three pads 28 on the common gate electrode 20b between the P-type and N-type transistors 12 and 14. Wires in M1 layer 32, which are not connected to the gate electrode 20b, are placed over these pads 28 to achieve required connections between transistors.
In the circuit diagram of the example above, the EXOR gate 74 also includes vias in VIA1 layer 58 and wires in M2 layer 60. The contact 30, VIA158, and M1 wire 32 and M2 wire 60 are all placed on the grid points 34 with a predetermined pitch. As described below, M2 wires 60 are used also as wires for connecting between circuit blocks. Therefore, the number of M2 wires 60 within the circuit block, such as shown in FIGS. 16 and 17, is preferably minimized to increase the flexibility of wiring between blocks.
In an integrated circuit with the conventional basic cells 72, only some of the pads 28 on the common gate electrodes 20a and 20b are used to place the contact 30, and the other pads 28 are not used. Nevertheless, in a conventional semiconductor integrated circuit, a plurality of pads 28 are provided for each of the common gate electrodes 20a and 20b in order to make necessary connections to form a circuit using a limited number (e.g., two layers) of metal wires. That is, in the conventional semiconductor integrated circuit, the common gate electrode with a plurality of contact pads is also utilized to connect between transistors. For example, in the circuit block shown in FIG. 16, the pad 28 at the lower side of the ground line 26 is selected to place the contact 30 of the left gate electrode 20b of the transistors 12 and 14 in the center basic cells 72. Then, connections from the contact to the gate of the P-type transistors 12, as well as the connection to the gate of the N-type transistor 14, are made through the common gate electrode 20a. 
Thus, in the conventional basic cell, a plurality of positions where contacts can be placed, are provided for each of the source, the drain and the gate electrodes in order to preserve flexibility of connection. Also, providing a plurality of pads on the common gate electrodes allows the common gate electrode to connect between transistors, which reduces the number of metal wires needed. If only one contact placement position is provided for the respective source, drain and the gate electrodes, or if a plurality of contact placement positions are provided, but the number of the positions are not sufficient, connections between transistors cannot be achieved. As a result, the number of transistors that cannot be used is increased, and the efficiency of transistor utilization is lowed, resulting in an increase in the chip area size of the semiconductor integrated circuit.
On gate electrode pads 28, which are not used to place contact 30, M1 wires 32 may be placed. However, the surface area of the semiconductor substrate on which the pad 28 is provided cannot be utilized as a channel region of a transistor, which produces circuit current. Therefore, extra areas, which correspond to pad regions, are needed in the conventional basic cell 72, which increases the size of the semiconductor integrated circuit. Thus, the number of LSI chips which can be manufactured on one silicon wafer is reduced, and the cost of the LSI chip is increased.
The description above is an example of an EXOR gate circuit block 74. A number of circuit blocks including circuit blocks other than the EXOR gate 74 are formed on a LSI chip using M1 and M2 wires 32 and 60. Further, those circuit blocks are connected between them by using wires up to M2 or the third metal wiring layer (M3), or by also using wires in higher metal layers, and a whole LSI chip with desired functions is formed.
FIG. 18 is a layout diagram showing an example of conventional wiring connections between circuit blocks. FIG. 18 shows a schematic drawing of connections between circuit blocks in an LSI chip manufactured with two layers of metal wires. Wires in M1 layer are used mainly as wires in the lateral direction, while M2 wires 60 are used mainly as wires in the vertical direction, in FIG. 18.
The rectangles in FIG. 18 represent circuit blocks of various kinds. Each circuit block is formed by connecting transistors in one basic cell, or in a plurality of basic cells, arranged in the lateral direction with M1 and M2 wires. The transistors and wires within the basic cells are not shown in the figure. In FIG. 18, two groups of circuit blocks, each of which are arranged in the lateral direction, are provided. There is a region without a circuit block between them. In reality, basic cells are arranged in the lateral and vertical directions to form a cell array including the regions where circuit blocks are not placed, and it is possible to form circuit blocks at an arbitrary position within the cell array. However, in the example shown in FIG. 18, every other row of basic cells is not used to form circuit blocks to provide regions where wires for connecting between circuit blocks are placed (channel region).
In the semiconductor integrated circuit using the basic cells 72 of the conventional example shown in FIGS. 16 and 18, contacts and vias for connecting within blocks or between blocks are placed on the grid points 34. Further, wires in M1 and M2 layers 32, 60 are placed on virtual lines which connects between grid points 34 vertically and laterally (called xe2x80x9cgrid linexe2x80x9d hereinafter). Specifying places where the contacts, the vias and the wires are placed as such allows quick and easy design works for forming circuit blocks and for connecting the circuit blocks on a CAD (Computer Automated Design).
In the semiconductor integrated circuit using the conventional basic cells 72 shown in FIGS. 16 and 18, the pitch between grid points 34 is determined by a dimension of a position where the widest pitch is needed, or, more specifically, by a distance between contacts placed on diffusion regions on both sides of the gate electrode. In some manufacturing processes, it may be determined by a position other than that described above, such as a distance between contacts placed on diffusion regions on both sides of an isolation region. In either case, the grid point pitch is determined by a portion where the widest pitch is needed in the manufacturing process to be used. As a result, simply by placing contacts, vias or wires on the grids, sufficient pitches are ensured between individual contacts, vias or wires each other. Thus, acceptability of the positioning of various features does not have to be considered for each case, which allows designing in a short period of time.
However, as a result, the pitch is increased more than necessary in positions other than the above-described position, which determines grid point pitch. For example, in the semiconductor integrated circuit shown in FIGS. 16 and 18, the pitch between M1 wires and M2 wires is larger than the minimum pitch acceptable by the manufacturing process.
Thus, the pitch between metal wires in the semiconductor integrated circuit using the conventional basic cells 72 is larger than the minimum metal wire pitch which can be manufactured. As a result, areas of circuit blocks and, further, the area of a whole LSI chip, are increased, which reduces the number of LSI chips that can be manufactured on a silicon wafer.
It is an object of this invention to provide a basic cell and a semiconductor integrated circuit, which can overcome problems of the above-described conventional technology, and reduce manufacturing cost by reducing the area and increasing the density of a LSI chip.
According to one aspect of the invention, an exemplary basic cell of a gate array semiconductor integrated circuit comprises: a plurality of transistors arranged on a semiconductor substrate, the transistors including a plurality of terminals; and a plurality of terminal wires connected to the terminals of the transistors at terminal connection points and arranged in at least one first wiring layer over the semiconductor substrate, the terminal wires having thereon a plurality of terminal wire connection points for connecting with circuit wires to be formed in at least one second wiring layer above the first wiring layer. At least one of the terminal wires is connected to one or more of the terminals at only one of the terminal connection points and has thereon at least two of the terminal wire connection points.
Preferably, at-most one of the terminal connection points is provided for each of the terminals of the transistors. Preferably, the at least two of the terminal wire connection points of the at least one of the terminal wires are arranged two-dimensionally. Preferably, the circuit connection points are arranged on grid points with a fixed pitch, and at least some of the terminal connection points are displaced from the grid points. Preferably, the first wiring layer is a low resistance metal wiring layer.
According to another aspect of the invention, an exemplary semiconductor integrated comprises: a cell array including a plurality of basic cells, each of the basic cells including a plurality of transistors arranged on a semiconductor substrate and a plurality of terminal wires formed in at least one first wiring layer over the semiconductor substrate, the transistors having a plurality of terminals and the terminal wires being connected to the terminals at terminal connection points; and a plurality of circuit wires formed in at least one second wiring layer above the first wiring layer, and connected to respective terminal wires. The terminal wires have thereon a plurality of terminal wire connection points for connecting with the circuit wires, and at least one of the terminal wires is connected to at least one of the terminals of the transistors at only one of the terminal connection points and has thereon at least two of the terminal wire connection points.
Preferably, the circuit wires are arranged along grid points with a fixed pitch, and at least some of the terminal connection points are displaced from the grid points.
According to another aspect of the invention, an exemplary method of increasing flexibility of connection to transistor terminals, comprises: arranging terminal wires connected at terminal connection points to terminals of transistors formed on a semiconductor substrate, the terminal wires are formed in at least one first wiring layer over the semiconductor substrate, at least one of the terminal wires is connected to one or more of the terminals at only one of the terminal connection points; and providing a plurality of terminal wire connection points on the terminal wires for connecting with circuit wires to be formed in at least one second wiring layer above the first wiring layer such that the at least one of the terminal wires has at least two of the terminal wire connection points.
Preferably, the plurality of terminal wires connection points are provided such that at least one of the terminal wire connection points are provided for each of the terminals of the transistors.
According to another aspect of the invention, an exemplary semiconductor integrated circuit comprises: a cell array area including an array of basic cells arranged on a semiconductor substrate, each of the basic cells including a plurality of transistors having a plurality of terminals and a plurality of terminal wires formed in at least one first wiring layer over the semiconductor substrate, the terminals of the transistors having thereon terminal connection points; and a plurality of circuit wires formed in at least one second wiring layer above the first wiring layer, each of the circuit wires having at least one circuit connection point arranged on grid points. At least one of the terminal connection points is displaced from the grid points, and the displaced terminal connection point is connected to one of the circuit connection points through the corresponding terminal wire.
Preferably, each of the terminal wires is connected to only one of the terminal connection points. Preferably, the terminal connection points are connected to the respective circuit connection points always through the respective terminal wires.
Preferably, the terminal wires have thereon terminal wire connection points arranged on the grid points, and the connection between the displaced terminal connection point and the corresponding circuit connection point is formed by connecting corresponding one of the terminal wire connection points to the circuit connection point located above the corresponding terminal wire connection point. Preferably, at least one of the terminal wires connected to the at least one displaced terminal connection point has thereon a terminal wire connection point displaced from the grid points; and the connection between the displaced terminal connection point and the corresponding circuit connection point is formed by connecting the displaced terminal wire connection point to the corresponding circuit connection point through a terminal wire connection element extending in the second wiring layer between a position above the displaced terminal wire connection point to the corresponding circuit connection point.
Preferably, the transistors in each of the basic cells include gate electrodes generally extending in a first direction and arranged in a second direction perpendicular to the first direction, and the displaced terminal connection point is displaced from the grid points at least in the second direction.
According to another aspect of the invention, an exemplary method of connecting to transistor terminals, comprises: arranging basic cells on a semiconductor substrate, each of the basic cells including a plurality of transistors having a plurality of terminals and a plurality of terminal wires formed in at least one first wiring layer over the semiconductor substrate, the terminals of the transistors having thereon terminal connection points; placing a plurality of circuit wires in at least one second wiring layer above the first wiring layer, each of the circuit wires having at least one circuit connection point arranged on grid points; and connecting the terminal connection points to the circuit connection points through the respective terminal wires, wherein at least one of the terminal connection points is displaced from the grid points.
Preferably, the connecting the terminal connection points is performed such that connections between the terminal connection points and the circuit connection points are always formed through the respective terminal wires.
According to another aspect of the invention, an exemplary semiconductor integrated circuit comprises: a cell array including a plurality of basic cells arranged on a semiconductor substrate along a first direction with a pitch Pc, each of the basic cells including a plurality of transistors; and a plurality of circuit wires over the cell array, the circuit wires being placed on grid lines perpendicular to the first direction, the grid lines being arranged with a pitch Pw in the first direction, wherein Pc is not an integral multiple of Pw, and Pcxc3x97n is equal to Pwxc3x97m, and where each of m and n is an integer greater than one.
Preferably, each of the basic cells includes k gate electrodes generally extending perpendicular to the first direction and arranged in the first direction, where k in an integer greater than one, and m is greater than (k+1)xc3x97n.
According to another aspect of the invention, an exemplary semiconductor integrated circuit comprises: a cell array including a plurality of basic cells arranged on a semiconductor substrate along a first direction, each of the basic cells including a plurality of transistors; a plurality of circuit wires over the cell array, the circuit wires being placed on grid lines perpendicular to the first direction, wherein the grid lines have a fixed pitch in the first direction, and include cell grid lines above the basic cells and boundary grid lines above boundaries between the basic cells.
Preferably, each of the basic cells includes k gate electrodes generally extending to a second direction perpendicular to the first direction and arranged in the first direction, where k is an integer greater than one, and the cell grid lines include at least k+1 cell grid lines arranged over each of the basic cells.
Preferably, the plurality of basic cells includes two adjacent basic cells arranged on both sides of one of the boundary grid lines; and the circuit wires are formed in at least one first wiring layer, and each of the adjacent basic cells includes a buried wire formed in at least one second wiring layer below the first wiring layer, the buried wire is not connected to the transistors within the respective basic cells, wherein the buried wires of the adjacent basic cells are coupled to extend across the adjacent basic cells.
According to another aspect of the invention, an exemplary semiconductor integrated circuit comprises: a cell array including a plurality of basic cells arranged on a semiconductor substrate along a first direction, each of the basic cells including a plurality of transistors; a plurality of circuit wires formed in at least one first wiring layer, the circuit wires including a boundary circuit wire placed over a boundary between two adjacent ones of the basic cells and a cell circuit wire over each of the adjacent basic cells; and each of the adjacent basic cells further including a buried wire formed in at least one second wiring layer below the first wiring layer, the buried wires are not connected to the transistors within the respective basic cells. The buried wires in the adjacent basic cells are coupled to extend across the adjacent basic cells, and the cell circuit wires over the adjacent basic cells are connected through the buried wires without connecting to the boundary circuit wire.
Preferably, the circuit wires are placed on grid lines perpendicular to the first direction, and the grid lines are arranged with a fixed pitch in the first direction.
In this invention, the term xe2x80x9ctransistor terminalxe2x80x9d means a gate, a source or a drain terminal of a transistor. The term xe2x80x9cterminal connection pointxe2x80x9d means a position on the terminal where a contact can be placed.
A terminal wire is formed in at least one wiring layer above the transistor, like the first metal wiring layer (M1), for example, and functions for pulling out the transistor terminal. The terminal wire connection point is a position where a via in the first via layer (VIA1), for example, can be placed.
A circuit wire is formed in one or more wiring layers above the terminal wire, like the second metal wiring layer (M2), the third metal wiring layer (M3) and above, for example, and forms a circuit by connecting between transistors.
The terminal wire is formed in a fixed pattern as an element for forming a basic cell. The circuit wire is customized depending on the functions that are needed.
The circuit connection point is a position on the circuit wire that can be connected to a via connecting the terminal wire and the circuit wire, like the via in VIA1 layer, for example. A terminal wire connection element is a wire element formed in the same layer as the layer used for the circuit wire. When a circuit connection point on the circuit wire is not exactly above the terminal wire connection point, which should be connected, the terminal wire connection element is extended from a position over a via placed at the terminal wire connection point to the circuit connection point in order to connect the circuit connection point to the via.
A basic cell according to the present invention is typically a basic cell for a gate array semiconductor integrated circuit. In this case, a plurality of basic cells having an identical configuration are arranged in an array and a cell array is formed. Then, circuit wires in two or more layers of metal wires are placed over a cell array region where the cell array is placed, and various kinds of circuit blocks are formed. Then, the circuit blocks are connected in order to form a semiconductor integrated circuit having the functions that are needed by a user. It is possible to form a semiconductor integrated circuit only with circuit blocks formed with basic cells according to this invention. It is also possible to form a semiconductor integrated circuit by combining circuit blocks formed with basic cells and various kinds of macrocells and/or megacells. In a cell-based semiconductor integrated circuit, it is possible to form at least a part of circuit blocks, which is not prepared in a cell library, by using basic cells.
It is also possible to place a cell array of basic cells according to this invention in a cell-based semiconductor integrated circuit chip. Circuit blocks, which are formed by performing wiring over the cell array region, can be used for a design modification after a transistor forming process, a design change after manufacturing a sample device, or the like.
On the other hand, in an integrated circuit customized by using a laser beam or other energy beam, the basic cell according to this invention may be manufactured by performing manufacturing steps including metal wiring steps. Also, it is possible to use the basic cell of this invention as a programmable basic cell, such as a FPGA.