The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also been accompanied by increased complexity in design and manufacturing of devices incorporating these ICs. Parallel advances in manufacturing have allowed increasingly complex designs to be fabricated with precision and reliability.
Advances have been made to device fabrication as well as to the fabrication of the network of conductors that couple them. In that regard, an integrated circuit may include an interconnect structure to electrically couple the circuit devices (e.g., Fin-like Field Effect Transistors (FinFETs), planar FETs, Bipolar-Junction Transistors (BJTs), Light-Emitting Diodes (LEDs), memory devices, other active and/or passive devices, etc.). The interconnect structure may include any number of dielectric layers stacked vertically with conductive lines running horizontally within the layers. Vias may extend vertically to connect conductive lines in one layer with conductive lines in an adjacent layer. Similarly, contacts may extend vertically between the conductive lines and substrate-level features. Together, the lines, vias, and contacts carry signals, power, and ground between the devices and allow them to operate as a circuit.