Redundant columns in a memory array improve the manufacturing yield of a memory integrated circuit. Defects in the memory array are repaired by, for example, swapping out a typical column in the memory array which has a defect, and swapping in a redundant column as a replacement for the defective column, by appropriate processing of column addresses.
Defects in a memory array may not be isolated to within a same column of the memory array. One approach to the problem of defects that occur in different columns of the memory array is to include more redundant columns. In this fashion, even defects that occur in different columns of the memory array can be addressed, by swapping out each of the defective columns and swapping in a redundant column. Unfortunately, this is an expensive solution because adding additional redundant columns consumes area.
Another approach to the problem of defects that occur in different columns of the memory array, is to divide the columns of the memory array into multiple segments, or row blocks. Defects which occur in different columns of the memory array may be replaced by the same redundant column, so long as the defects also occur in different row blocks of the columns. One example implementation is described in U.S. application Ser. No. 12/893,235.
Although the division of columns into multiple row blocks increases the area efficiency of redundant columns that repair defects, the multiple row blocks complicate the process of verifying a memory operation such as program or erase. If a row block of a column in the memory array has been replaced with a row block of a redundant column, then it does not make sense to verify the replaced row block. Accordingly, memory for each column of the status memory indicates whether or not to include particular memory columns in the verify process. Such status memory increases with the granularity of the division of columns into multiple row blocks.
It would be desirable to take advantage of the increased area efficiency of redundant columns which results from a defect repair system that divides memory columns and redundant columns into multiple segments or multiple row blocks, while mitigating the area penalty from the need to store larger volumes of repair status information for the verify process.