1. Technical Field
The present invention relates to a CMOS image sensor (CIS), and more particularly, to an analog-to-digital converter (ADC) for converting analog signals output from pixels of a CIS into digital data by using a double sampling technique.
2. Discussion of the Related Art
A CIS has found increasing use in battery-dependent portable applications such as digital cameras, video cell phones and hand-held scanners because it operates at a low voltage and consumes less power than a charge-coupled device (CCD).
However, when images are produced using the CIS, a sun black effect may occur. The sun black effect is a phenomenon similar to a sunspot in which a portion of an image to be displayed brightly is displayed darkly due to an overflow of a charge inside a pixel when a high illumination person or object such as the sun is photographed.
In particular, the sun block effect occurs when the intensity of radiation under high illumination exceeds a dynamic range of a pixel. In other words, the sun black effect occurs when a difference between a reset level and a signal level of an active pixel sensor (APS) in the CIS is decreased because the reset level is below a normal level.
FIG. 1 shows a conventional column ADC circuit for use with a CIS circuit.
As shown in FIG. 1, the column ADC circuit converts an analog voltage corresponding to a photo charge output from an APS in the CIS circuit into digital data by double sampling.
The double sampling is composed of a reset sampling for sampling a reset voltage of the APS and a signal sampling for sampling a signal voltage of the APS. A voltage difference generated by the double sampling is then converted into digital data.
The column ADC circuit of FIG. 1 includes a first switch SW1 controlled by a first control signal S1 located between an output port of the APS and a first node 17, a second switch SW2 controlled by a second control signal S2 located between an output port of a ramp generator of the CIS and a second capacitor C1, a first capacitor C0 connected between the first node 17 and a first input port 19 of a comparator 11, and the second capacitor C1, connected between the first node 17 and the second switch SW2.
The column ADC circuit also includes the comparator 11 having the first input port 19 for receiving a voltage output from the APS and a second input port for receiving a reference voltage Vref and comparing a light signal voltage input from the first input port 19 with the reference voltage Vref, and outputting the result of the comparison, an inverter 13 for inversely amplifying signals output from the comparator 11, and a digital converter 15 for converting an analog signal output from the inverter 13 into digital data.
The column ADC circuit further includes a third switch SW3 connected between the first input port 19 and an output port of the comparator 11 and controlled by a third control signal S3, a fourth switch SW4 connected in parallel to the inverter 13 and controlled by a fourth control signal S4.
The digital converter 15 includes a plurality of latches connected in series for counting a clock to correspond to a signal level detected during a normal operation and converting the signal level into digital data on a basis of the counted value.
FIG. 2 shows waveforms for driving the column ADC circuit shown in FIG. 1 and a voltage level at internal nodes of the column ADC circuit in FIG. 1.
Referring now to FIGS. 1 and 2, when the column ADC circuit operates, the control signals S1, S2, S3 and S4 become logic-high in a reset sampling period and their corresponding switches SW1, SW2, SW3 and SW4 are turned-on.
Then, the comparator 11 and inverter 13 have a feedback structure. A reset voltage output from the APS is stored in the first capacitor C0 and a ramp voltage output from the ramp generator is stored in the second capacitor C1. Therefore, a voltage Vp of the first node 17 becomes the level of the reset voltage output from the APS.
A signal voltage corresponding to a photo charge output from the APS is then transmitted to the first node 17 in a signal sampling period. As shown in FIG. 2, a voltage difference 21 is generated between the reset voltage output from the first node 17 and the signal voltage because the signal voltage is lowered to correspond to the photo charge. Similarly, a voltage difference 23 between a reset voltage output from the second node 19 and the signal voltage corresponds to the voltage difference 21 at the first node 17.
As shown in FIG. 2, the voltage Vp of the first node 17 and the voltage Vin of the second node 19 operate as shown by the solid lines when under normal illumination, thus illustrating a voltage difference that is proportional to an incident intensity of radiation. As further shown in FIG. 2, the voltages Vp and Vin operate as shown by the dotted lines when under high illumination, thus illustrating a voltage difference that is smaller than an actual incident intensity of radiation.
In other words, when the voltages Vp and Vin are the dotted lines as shown in FIG. 2, the reset voltage output due to an overflow of the APS during the reset sampling is lower than a normal reset voltage. Therefore, a sun black effect occurs because voltage differences 22 and 24 between the signal voltage during the signal sampling and the reset voltage are below the normal level.
FIG. 3 shows another conventional column ADC circuit for use with a CIS circuit.
The column ADC circuit of FIG. 3 includes the same or similar components as the column ADC circuit in FIG. 1, except for a diode 31. Accordingly, a description of the duplicative components is omitted.
As shown in FIG. 3, a reset voltage may be maintained by adding the diode 31 to an output port of an APS even if an overflow is generated in the APS, thus preventing a sun black effect.
However, in the column ADC circuit of FIG. 3, a double sampling should not be performed since a fixed pattern noise (FPN) may be generated when an input voltage Vclamp of the diode 31 is low. In addition, a sun black effect may be generated when the input voltage Vclamp is high. Further, an image sensing error may result due to variations in the input voltage Vclamp.
As such a need exists for a column ADC circuit for use with a CIS that is capable of double sampling while preventing a reset voltage from dropping upon generating an overflow in an APS of the CIS.