In micro-electro-mechanical system (MEMS) technology, a MEMS device is integrated with a logic circuit including, for example, a complementary metal-oxide-semiconductor (CMOS) device in a single chip by using conventional semiconductor manufacturing processes such as electroplating and etching.
The dimension of the features of the logic circuit is becoming smaller to allow greater aerial densities across the substrate. The features may include connector bumps, interconnects, semiconducting or oxide features, gates, electrodes, resistors, vias and many others. The features are covered by a passivation layer to protect thereof or to electrically isolate the features. However, the formation of the passivation layer may cause a particular problem.
For example, a conventional passivation layer 10 can be used to cover features 12, as shown in FIG. 1, to protect the features 12 that may be used as interconnects or connector bumps to connect the active and passive devices on a substrate 14. However, it becomes increasingly difficult to deposit a continuous, conformal, and substantially defect-free passivation layer 10 around the features 12. Referring to FIG. 1, the passivation layer 10 forms a plurality of seams 16, which split open the passivation layer 10 at a plurality of bottom side-wall corners 18 of the features 12. These seams 16 induce cracking during the subsequent wet etching process.
U.S. Pat. No. 8,563,095 disclose an approach to solving the problems related to the seams of the passivation layer. In U.S. Pat. No. 8,563,095, prior to depositing a dielectric layer, a plurality of steps including plasma cleaning, conformal liner deposition and adhesion layer deposition are performed.
Accordingly, it is needed to provide an improved passivation layer on a feature in order to solve the above-mentioned problems relating to cracking induced by the seams at the bottom side-wall corner thereof during wet etching process, so as to achieve a seam-free passivation layer.