This invention relates to a processor for parallel image processing which performs local neighboring (Kernel) image processings such as a spacial convolution operation.
The image processing for processing image data is classified into a preprocessing operation, a feature extraction processing operation, judgement processing, etc., and the parallel image processing processor according to this invention is directed mainly to the preprocessing operation.
This preprocessing is desired to be performed by an image processor which is versatile and allows a high speed processing. However, since the image data to be processed is two-dimentionally extended, it is difficult to parallely process all the image data. Therefore, the parallel processing is often performed for the operations among local neighboring image data such as a spacial convolution operation which is intended for noise reduction and edge enhancement. In order to process such local neighboring image data, there has been proposed an LSI circuit of a local parallel type image processor which is disclosed in Japanese Patent Unexamined Publication No. 59-146,366 (corresponding to U.S. application Ser. No. 578,508) and U.S. Pat. No. 4,550,437. This circuit was large-scale integrated using as a main module a parallel operation circuit which operates parts of the local neighboring data in parallel; plural main modules are arranged or one main module is subjected to a time division processing to extend the size of the local image region, thereby performing the parallel processing of local neighboring operations at a high speed and versatilely.
Namely, this processer performs an m.times.n (m, n: integer) local parallel image processing in such a way that (1) m main modules, each having an arithmetic unit (processor elements, PE's) are arranged and perform the process in one machine cycle or (2) a single main module having n PE's is used in a time division manner and performs the processing in m machine cycles.
In the above prior art, plural main modules are used to perform an image processing, line buffer circuits, are employed, as externally equipped circuits, for supplying in parallel the image data to the respective main modules. Therefore, once the wiring is made, the local image region which permits a parallel processing is disadvantageously fixed. Moreover, additional line buffer circuits must be employed for expanding the local neighboring region. For example, where a 3.times.3 local parallel operation is performed with an operating frequency of 6 MHz for an image of 256.times.256 pixels with each pixel data indicated by 8 bits, a 4 K bit high speed memory or shift register operating with a frequency of 6 MHz is required so that the required amount of hardware becomes large.
On the other hand, where the time division processing is carried out for the image processing, the above line buffer circuit is not required. However, the image data must be supplied to the main module by means of a stick scanning method. In order to convert the ordinary raster-scanned image data into the stick-scanned image data, a larger amount of hardware is required than the above line buffer circuit.