A. Technical Field
The present invention relates generally to signal synchronization, and more particularly, to the design of low-power delay cells.
B. Background of the Invention
The importance and application of electronic technology to day-to-day life is well known. The increasing accuracy of signal processing circuits has allowed ever-increasing amounts of data to be transmitted and received across a communication path in a reliable manner.
Circuits that process these high-speed signals are generally required to be in synchronization with various other signals or clock signals. The signals fed to these high-speed circuits may be “source-synchronized” by timing their relationship with an external clock signal(s). Using this clock, these high-speed circuits provide synchronized sampling of high-speed data signals for further signal processing applications.
Delay cells are an example of devices that may be used to adjust a clock-data phase relationship to an optimal setting to achieve the highest timing margin. The delay cell is typically designed with an array of delay elements arranged such that any number of elements can be chosen to apply a particular delay. However, due to the nature of the cell architectures, glitches can occur when the input or delay settings are changed.
FIG. 1 illustrates an exemplary signal processing scenario in which source synchronization is used to sample a data signal. As shown, a source-synchronized application 101 may be a high-speed circuit accepting a data signal 112 and a clock signal 114. The data signal 112 may be a high-speed signal. An interface 122 at the input of the source-synchronized application 101 is generally used to affect the synchronization between the data signal 112 and the clock signal 114. The interface may provide the source-synchronized signal for further processing in a signal-processing module 124. Output data 126 from the signal-processing module 124 may be made available on output.
In providing the synchronization of the data signal 112 and the clock signal 114, the interface 122 may use delay cells. In one example of a delay cell, a delay cell may be used to introduce variable delay to one of input signals in order to synchronize them with respect to the other. This variation in the delay may be required to be introduced during working of the circuit and the change in the delay may be required to be introduced quickly within the cells or “on the fly.”
If the logical level of the delay is quickly changed, the response of voltage or current characteristics of the delay cells may lag. A “glitch” in the form of spikes or irregularity in the original signal may be introduced and thus initiate a corresponding undesired response in the circuit. For example, in a clock signal having an off-time duration of 5 ns, a glitch may be introduced at 3 ns leading to initiation of a corresponding faulty response.
“Signal fighting” within the cell may also introduce glitches. The phenomena of “signal fighting” may occur when a component receives signal from two or more branches. The signal at individual branches may effectively try to overrun one another leading to a temporary unstable state. For example, when one delay cell branch is providing a low level signal while another branch is providing a high level signal, then for a certain period the high level signal will overrun the low level signal leading to a glitch in the resultant signal.
Power consumption may also be an important factor in the design and performance of a delay cell. Because delay cells are typically integrated within a chip, power considerations need to be addressed in order to optimize the power requirements of the chip. In addition, improper power management within the delay cell may introduce noise on a signal and may significantly affect the signal-to-noise ratio.