1. Field of the Invention
The present invention relates to a bipolar transistor which can achieve high-speed operation and a method of manufacturing the same.
2. Description of the Prior Art
FIGS. 4 and 5 illustrate well-known examples of conventional bipolar transistors for achieving high-speed operation.
The bipolar transistor as shown in FIG. 4 comprises a p.sup.- -type semiconductor substrate 2 which is formed on its element region, being isolated by an oxide film 1, with an n.sup.+ -type collector buried layer 3, an n.sup.- -type epitaxial growth layer 4, a p-type base diffusion layer 5 and an n.sup.++ -type emitter diffusion layer 6. A nitride film 7 is formed on the oxide film 1 and a polycrystal silicon layer 8 for extracting a base electrode is formed on the nitride film 7 with a prescribed pattern, while an oxide film 9 for passivation is formed on the polycrystal silicon layer 8 and the nitride film 7. A collector electrode interconnection layer 10 is connected with the collector buried layer 3 through a contact hole defined in the oxide films 1 and 9 and the nitride film 7. A base electrode interconnection layer 11 is connected with the polycrystal silicon layer 8 through a contact hole defined in the oxide film 9. Further, an emitter electrode interconnection layer 12 is connected with the emitter diffusion layer 6 through a polycrystal silicon layer 13 for emitter layer diffusion and emitter electrode extraction.
The bipolar transistor as shown in FIG. 5 comprises a p.sup.- -type semiconductor substrate 15 formed on its element region, being isolated by an oxide film 14, with an n.sup.+ -type collector buried layer 16, an n.sup.- -type epitaxial growth layer 17, a p-type base diffusion layer 18, an n.sup.++ -type emitter diffusion layer 19 and a polycrystal silicon layer 20 for extracting a base electrode. A base electrode interconnection layer 21 is connected with the polycrystal silicon layer 20 through a contact hole defined in an oxide film 22. An emitter electrode interconnection layer 23 is connected with the emitter diffusion layer 19 through a polycrystal silicon layer 24 for emitter layer diffusion and emitter electrode extraction. Further, a collector electrode interconnection layer 25 is connected with the collector buried layer 16 through a contact hole defined in the oxide film 22.
Both of these bipolar transistors are adapted to reduce parasitic capacity and resistance by refinement for achieving high-speed operation, while improving cut-off frequency (F.sub.r) by horizontal size reduction of the base diffusion layers 5 and 18.
In the case of the bipolar transistor as shown in FIG. 4, mask alignment for forming the base diffusion layer 5 may be performed only once so that the emitter diffusion layer 6 is thereafter formed in a self-alignment manner, whereby the width of the emitter diffusion layer 6 can be refined to about 0.5 .mu.m in order to attain high-speed operation. In the case of the bipolar transistor as shown in FIG. 5, on the other hand, an outlet for extracting the base electrode may be provided on the side surface of the base diffusion layer 18 to substantially equalize the horizontal area of the emitter diffusion layer 19 with that of the base diffusion layer 18, thereby to achieve high-speed performance substantially identical to that of the bipolar transistor as shown in FIG. 4.
In such conventional bipolar transistors, however, base areas are determined by limitation in lithography and cannot be refined beyond the limitation. The base diffusion layer 5 is formed by ion implantation through the nitride film 7 serving as a mask in the case of FIG. 4 while the base diffusion layer 18 is formed by ion implantation through the oxide film 22 serving as a mask in the case of FIG. 5, whereby refinement of the areas of the base diffusion layers 5 and 18 is limited by lithography. Thus, floating capacity caused in p-n junction parts between bases and collectors cannot be reduced over a prescribed level, whereby high-speed operation is prevented. Further, the wide collector buried layers 3 and 16 for extracting electrodes from collectors are required in order to vertically drive the bipolar transistors, whereas floating p-n junction capacity is caused between the collector buried layers 3 and 16 and the silicon substrates 2 and 15 to prevent high-speed operation.