The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices providing higher-speed operation and higher integration.
In a conventional semiconductor device, a source region of each transistor formed by an impurity diffusion layer extends to a boundary between standard cells to be coupled to a power supply interconnect shared by standard cell rows, thereby securing an interconnect resource in a standard cell and reducing the area of the standard cell.
FIGS. 8A-8E illustrate an example configuration of a conventional semiconductor device. FIGS. 8A-8C are layout top views. FIG. 8D is a cross-sectional view taken along the line Y81-Y81′ of FIG. 8A. FIG. 8E is a cross-sectional view taken along the line Y82-Y82′ of FIG. 8B. A circuit diagram of FIG. 9 is implemented by the configuration shown in FIGS. 8A-8E. In FIG. 9, two NMOS transistors 901 are coupled in parallel between a power supply interconnect VSS and a terminal A. Two NMOS transistors 902 are coupled in series between the power supply interconnect VSS and a terminal B. In FIGS. 8A-8C, two transistors above the power supply interconnect VSS in the drawing correspond to the NMOS transistors 901, and two transistors below the power supply interconnect VSS in the drawing correspond to the NMOS transistors 902.
In FIG. 8A, potential is supplied from the power supply interconnect VSS, which is provided around the boundary between adjacent transistors, to the source region of each transistor via a potential supply interconnect and a contact hole. Thus, impurity diffusion regions and contact holes are provided immediately below the power supply interconnect VSS to reinforce the power supply interconnect VSS.
In FIG. 8B, the source region of each transistor is extracted to immediately below the power supply interconnect VSS, which is provided around the boundary between adjacent transistors and a contact hole is provided, thereby supplying potential to the source regions of the transistors. An impurity diffusion region and contact holes are provided immediately below the power supply interconnect VSS to reinforce the power supply interconnect VSS.
FIG. 8C illustrates a variation of the configuration of FIG. 8B. An impurity diffusion region and contact holes are provided immediately below the power supply interconnect VSS only in the portion where the source region of each transistor extends to the power supply interconnect VSS.
Contrary to the configuration of FIG. 8A, there is no need to use an interconnect region from the power supply interconnect VSS to the source region of each transistor in FIGS. 8B and 8C. This measure is advantageous in reducing the chip area, since the interconnect resource critical in reducing the height of a standard cell can be effectively used. While the potential supply interconnect extending from the source region of each transistor is a metal interconnect in FIG. 8A, the potential supply interconnect is an impurity diffusion region in FIGS. 8B and 8C. Since a metal interconnect resource is not used, the area can be reduced.
As miniaturization in a semiconductor manufacturing process progresses, a technique of accurately processing a gate electrode by repeating exposure and etching a plurality of times in patterning the gate electrode has been used. Advantages in repeating exposure and etching (a complex process) in patterning a gate electrode will be described below with reference to FIGS. 10A and 10B.
FIGS. 10A and 10B illustrate a difference between a design shape and a finished shape of the pattern of a gate electrode where the pattern is formed by a conventional single process. FIG. 10A is a layout illustrating the design shape of impurity diffusion regions and gate electrodes forming the source/drains of transistors. The terminals of the gate electrodes of upper and lower transistors in the drawing, which protrude from the impurity diffusion regions, face each other.
FIG. 10B illustrates the actual finished shape of the gate electrodes of the layout of the design shape in FIG. 10A. In the drawing, OL is the protruding amount of each gate electrode to prevent shorting of a source region and a drain region even if the masks of the gate electrodes and the impurity diffusion regions are misaligned. EX is the receding amount of the thin line pattern in patterning the gate electrodes. S is the separating interval to prevent shorting in the layer. L is the length required for obtaining a desired transistor width in FIGS. 10A and 10B.
On the other hand, FIGS. 10C and 10D illustrate a difference between a design shape and a finished shape of the pattern of a gate electrode where the pattern is formed by a complex process. FIG. 10C is a layout illustrating the design shape of impurity diffusion regions and gate electrodes forming the source/drains of transistors. The terminals of the gate electrodes of upper and lower transistors in the drawing, which protrude from the impurity diffusion regions, are coupled to each other. A recognition layer 1002 for removing the gate electrodes in a subsequent step is provided in the region coupled to the gate electrodes of the upper and lower transistors in the drawing.
FIG. 10D illustrates the actual finished shape of the gate electrodes of the layout of the design shape in FIG. 10C. In the actual finished shape, the gate electrodes of the upper and lower transistors in the drawing are separated. In the drawing, OL is the protruding amount of the each gate electrode to prevent shorting of a source region and a drain region even if the masks of the gate electrodes and the impurity diffusion regions are misaligned. S′ is the distance separated in removing the gate electrodes. EX is the receding amount of the thin line pattern in patterning the gate electrodes. EX is required in the single process and a margin not required in FIG. 10D. Therefore, EX corresponds to reduction in the size in the vertical direction of the drawing.
As shown in FIGS. 10A-10D, where the gate electrodes are patterned by the single process, the length L is required in the vertical direction of the drawing. On the other hand, where the gate electrodes are patterned by the complex process, only the length of (L−2×EX) is required for forming transistors providing the same performance. As such, the chip area can be reduced.
Japanese Patent Publication No. 2008-4790 (page 11, FIG. 3) is cited for reference.