1. Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to the manufacture and use of semiconductor devices used for electrostatic discharge (ESD) protection in integrated and other circuits.
2. Description of the Related Art
To protect against electrostatic discharge (ESD) events in integrated circuit devices, ESD clamp circuits are typically provided as voltage limiting devices across the inputs and/or other terminals of such integrated circuit devices. Conventional approaches for designing ESD clamp circuits include using bipolar transistors and/or silicon controlled rectifier circuits (a.k.a., thyristor circuits) between the protected terminals which turn “on” at a triggering threshold voltage Vt and conduct current when voltage across the protected terminals rises beyond a predetermined triggering threshold voltage or limit. In operation, as the voltage applied to the terminals is increased, very little current flows through the ESD clamp circuit until the triggering threshold voltage Vt is reached, at which point the ESD clamp circuit begins conducting current up to a holding point (defined by a higher holding current IH and lower holding voltage VH) after which, depending upon the internal on-state resistance RON of ESD claim circuit, the current and voltage may further increase to breakdown point beyond which destructive failure may occur leading to further current increase accompanied by voltage decrease.
With advanced smart power technologies, ESD designers confront increasingly narrow design windows which define the voltage range between a low limit (set by the protection latch-up to be smaller than the holding voltage VH) and a high limit (set by the breakdown point for the circuit being protected). As the design windows shrink, there are design tradeoffs between the on-state resistance RON, the tuning of the triggering threshold voltage Vt and holding voltage VH for the ESD clamp, and the size of the ESD clamp. These design tradeoffs can be exacerbated with ESD clamp circuits that are designed to protect against both positive and negative voltage fluctuations. For example, it is desirable to keep the on-state resistance RON low so that the on-state voltage stretch-out does not lead to the degradation of the protected circuit, while the triggering threshold voltage Vt and holding voltage VH must be tuned to activate the ESD clamp under relatively high voltage conditions that effectively increase the on-resistance, which is undesirable. In many cases, the only way to get a low enough on-state resistance RON is to increase the size of the ESD protection circuit, thereby increasing chip cost.
Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.