Photolithography is a fabrication process by which patterns for various devices, such as integrated circuits (ICs), are generated on substrate wafers. This process generally starts with the design of an IC chip, including the various circuit elements, their electrical interconnects, and their physical layout across the chip. The IC design typically describes each layer required to fabricate the IC in a FAB using a photolithographic process. There are generally many layers to an IC chip.
After an integrated circuit is designed, a photomask is created. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. Masks are critical to the lithography process. There are different types of masks, including binary chrome-on-glass, attenuated phase-shifting masks (attPSM) and alternating phase-shifting masks (altPSM). Before being used in a photolithography system to replicate the mask image in reduced size onto a wafer when building the IC, the mask is inspected for defects. Defects found in the mask will often be repaired so that they will not be replicated on or introduce harmful distortions to the chips created from that mask.
A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer. The photomask is a critical piece of the photolithography process, because it holds the essential integrated circuit design pattern information for circuits replicated from that mask. Masks may be created by various processes. In one method, an electron beam or a laser-based system is used in a photolithographic process to write the pattern on the mask in accordance with mask data developed to produce via lithography the intended chip pattern on the wafer.
The resolution limit of conventional optical lithography technology is increasingly being challenged by the sub wavelength, or low-k1, dimensions of the critical IC feature geometries. Not only are the critical dimension feature geometries decreasing in size in accordance with, or even faster than, Moore's Law predictions, the already large number of these feature geometries is growing at a dramatic rate as well. Furthermore, due to the necessity to mitigate optical proximity effect distortions through resolution enhancement techniques at the mask level, the overall polygonal figure count is skyrocketing. These critical feature geometries are patterned far more precisely as well due to the severity and sensitivity of the non-linear imaging. (These effects are often referred to in this context as resulting from the mask error enhancement factor, or MEEF). Extreme precision is required for sub wavelength, or low-k1, applications due to highly non-linear imaging behaviors which often magnify mask errors by large factors and non-intuitive manners.
With the overall year-to-year increase in IC logic function, industry trends towards larger and more complex system-on-chip and mixed signal designs, and increasingly aggressive use of artificial layout enhancement for manufacturability (LEM) features such as Resolution Enhancement Technology (RET) and dummy fill patterns, IC physical design layout data volume and resulting mask data file volume sizes are exploding. The overall design and manufacturing process integration complexity is also expanding, as it attempts to span a widening and deepening gap between the different technical disciplines and ‘cultures’ of manufacturing and design. This has led to increases in the length of time to create masks, in the number of errors impacting mask elements, and in the costs associated with the mask process.
Some of these difficulties may be described by example with respect to a traditional photolithography process, including mask creation and inspection methods, as shown in FIG. 1. At block 102 an integrated chip (IC) design is created, often by using various EDA systems such as those produced by Cadence Design Systems, Inc., of San Jose, Calif. An IC design flow typically starts with a desired circuit operation, then proceeds to a design layout for a set of circuit elements expected to produce that desired operation.
The IC design 102 may include circuit design and analysis, layout synthesis and routing, and verification and tapeout. The design 102 often produces a set of circuit elements in a layout to effect a desired circuit electrical operation on a layer-by-layer basis. This is often referred to as the design flow. For background on IC design and mask manufacturing processes, see Resolution Enhancement Techniques in Optical Lithography, Chapter 1, by Alfred K. Wong, SPIE Press, 2001, which is incorporated by reference in its entirety.
Up until tapeout, a vast amount of information is available, including, for example, the relation of the physical layout to the design schematic or netlist; individual circuit element models and properties; circuit criticalities; and manufacturing assumptions which were used in the IC design. Furthermore, the information is typically in a design hierarchy of fundamental library base cells, or ‘hard IP,’ of predesigned and characterized blocks, or ‘cores.’ Circuit elements at this level may include, for example, transistors, power buses, resistors, capacitors, and interconnects. Logos and manufacturing elements, such as area fill cells, may also be included.
Tapeout is typically the last step in the IC design flow and is the ‘handoff’ mechanism to manufacturing. Typically, tapeout produces a geometries-only design hierarchical data file in GDS-II stream format. However, a wealth of design knowledge is stripped out into this geometry-only format, and therefore is unavailable to any data file derived from it or any design or manufacturing integration process occurring thereafter.
Due to fundamental inherent limitations in current and near-future optical lithography processes, the layout of the IC is no longer directly equivalent to the pattern printed on the eventual IC wafer. As a result, various Resolution Enhancement Techniques (RETs) are used to compensate for various distortions, or to enable higher resolution, through advanced optical techniques. For background on RETs, see Resolution Enhancement Techniques in Optical Lithography, Chapter 1, by Alfred K. Wong, SPIE Press, 2001; and TCAD Development for Lithography Resolution Enhancement, L. W. Liebmann et al., IBM Journal of Research and Development, Vol. 45, No. 5, September 2001, both of which are incorporated herein by reference in their entirety. RETs are typically added at the bottom of the design flow, prior to tapeout, and out of view of the designer. However, increasingly more and more RET impact is being dealt with upstream in the design flow, with layout consideration and even RET insertion being applied earlier.
After the integrated circuit design is created, 102, a process to prepare mask data and create a job deck, 104, follows. This starts the mask flow, which runs through mask inspection and repair. Knowledge of the mask writing process, and to some extent the photolithography process, may be employed in ‘fracturing’ the GDS-II design database into a data file during mask data preparation. At ‘fracturing,’ the mask data is prepared for the mask writing equipment by breaking complex polygonal shapes into a simple base set of shapes and by applying mask writer electron- or laser-spot proximity effect shape, exposure compensation, and sizing operations to the data. Numerous output files may be generated.
Typically, the mask data is prepared into a MEBES data file format, although other formats may also be used. The MEBES file holds polygon and geometry information to be used in writing, but, like the GDS-II stream file, it holds none of the higher-level IC design or circuit feature functionality or criticality information available in the IC design flow. The MEBES file may include information detailing polygonal shapes, dimensions, positions on the mask, manufacturing features added to improve lithographic fidelity at the chip surface, and other parameters.
However, there is no ‘knowledge’ of what a feature is beyond its geometry and location. Conventionally, very little “design” is done at block 104, as the IC design process sets the layout and often most of the RET. This typically leaves only fracturing, job deck creation, and secondary chip surface feature additions (such as registration marks) to be handled during the preparation 104, after the IC design process 102 and before the mask writing process 106.
A mask writing process 106 then follows. Mask writing often involves writing the polygonal shapes and layout of a mask design pattern (from the MEBES file, for example) in a photo- or electron-sensitive coating (often called a “resist”) on a mask substrate (often glass) and then etching in chrome, glass or other materials associated with the specific mask technology being employed (for example attPSM, altPSM). Mask writing may be based on various technologies, including electron beam-based or laser-based systems. The fidelity of a mask element written on a mask substrate may be defined by the energy applied, shaped-beam aperture employed, and possibly by the adjacency of other features due to laser, electron or thermo-chemical proximity effects on the mask. Positive effects of increased time and beam energy on element writing may be offset by negative impacts resulting from thermal and chemical changes in the surrounding photoresist caused by the applied energy. There is a tradeoff between optimizing writing speed and the deleterious effects of thermal, chemical and proximity effects related to the writing speed.
A mask writing system may be provided with and controlled by a database containing the mask's polygonal shape and layout information, such as the mask information in the MEBES data file. The design data connectivity and ‘design intent’ information usually have been destroyed by this point. Design data connectivity includes data relating to the electrical net list or schematic, functional intent and criticality of the various IC elements. Thus, the writing tool only receives simple polygonal shapes and location data. There is no knowledge of the design intention of a given polygon, nor a mechanism for establishing the requisite relationship in order to perform design-aware information processing.
In such systems, from this point on, imaging operations of mask writing and inspection operate under the most general uniform imaging assumptions of isotropic imaging. Therefore, the features are processed under the same conditions as their neighbors, and they are spatially invariant and device- and circuit-unaware. Thus, the polygonal shapes across the mask are treated equally in terms of their importance to the effectiveness of the resulting circuit. As the IC industry moves to deep sub-wavelength, or 'low k1, layout features, lens aberrations may increasingly violate these space-invariance assumptions, requiring additional higher-level consideration in the design flow as well as the mask flow.
In continuing reference to the example of a traditional photolithography process as shown in FIG. 1, after mask writing, a mask inspection process 108 is performed. A mask that has been written or printed with polygonal mask elements is inspected for defects. Such inspection often includes comparing a written mask against a perfect version of the mask as defined by its mask design database. Defects may include any departures from the mask design, such as missing, misaligned or misshapen shapes, pinholes, bridging features, or holes.
Defects in a mask are generally assumed to result in defects in an integrated circuit replicated from that mask. The mask inspection process 108 references only the polygonal shape and layout information from a mask data file 104 generated by the fracturing tool, which is often in a file format such as, for example, Klaris (an abbreviation for KLA-Tencor Reticle Inspection System, produced by KLA-Tencor, Inc. of San Jose, Calif.). Little information from the IC design process relating to the function or relative importance or criticality of individual mask elements can then be applied in comparing a mask to its mask design template. This is an isotropic approach to mask inspection. As a result, each mask element is inspected equally in terms of the time and resolution of the inspection system, regardless of its relative importance to the operation of the resulting circuit.
Typically, deviations from the ideal are considered defects. Some mask defects, however, have no significant negative impact on a circuit produced from the mask, and thus can be ignored as essentially “non-defects.” The “non-defects” may include defects next to mask elements that do not require exact fidelity to effect their function, such as a logo or an area fill cell. Additionally, some defects may have a positive impact, and thus may be ignored or maintained on the mask. The “positive defects” may include a defect located at a distance (such as the Rayleigh distance, for example) from a mask element. This type of defect operates to enhance the depth of focus of the lithography for the mask element, which occurs with RET scattering bars, for example. The ‘non-defects’ and ‘positive’ defects may be waived or determined not to be defects for purposes of defect analysis or correction.
An analysis 110 is performed to discern whether any defects were found during the mask inspection process. Defects may be found near or on the polygonal mask shapes, such as in their relative positioning or in unintended shapes on the mask, such as pinholes, bridging, isolated artifacts or “hard” or “soft” defects. Defects may also include opaque or transparent errors on a mask. Transparent defects may not be visible under certain inspection conditions, or in the alternative may be visible in the inspection condition but not in the use condition. Such transparent defects may impact the phase of light passing through them resulting in unwanted optical interference effects, while opaque defects block or alter such light in some way. If no defects are found, then generally chip creation 118 is performed.
Each found defect is examined, 112, to determine if it can be repaired. If the defect is unrepairable, an analysis is performed to determine whether it may be accepted without repair. This decision may require advanced modeling and simulation of the defect under the specific lithography process being employed. An “unrepairable defect” might be a defect that cannot be easily fixed by a repair process, such as focused ion-milling or a deposition repair technique, for example.
An unrepairable defect requires the mask to be discarded and a new mask writing process, 116, to be performed. For example, a mask repair performed by ion beam milling or other processing may be more time-consuming and expensive than writing a new mask. Additionally, mask correction often creates further defects in a mask, as it may add unwanted material during the ion milling process or alternatively may erode the mask elements in some unwanted manner. Merely handling the mask may alter or damage it through any number of means, including electrostatic discharge (ESD).
At repair block 114, a mask repair process fixes the defect. Mask defect repair often involves focused ion beam (FIB) repair. After the mask correction is performed, the mask inspection process 108 is performed again to find any new defects which may have been introduced during the repair process. Such a cycle is often costly and time-consuming. Once a written mask is found to have either no defects or an acceptable number and type of defects during analysis 110, the integrated chip is created, 118.
During the photolithography process 118, the mask is used to transfer the mask pattern to a wafer. The mask allows light to pass through transparent sections defined by the polygonal mask elements previously written or etched thereon. An image of the mask so produced is then passed through an imaging lens system, often at a reduced image size, and replicated on a wafer surface through the lithography process to create the integrated circuit. Thus, the mask plays a critical role in transmitting the circuit design to the wafer surface.
Therefore, there is a need to allow image understanding in the context of circuit performance and manufacturing requirements, by providing important design awareness.