Improvement in MOS device technology is directly proportional to the rate at which MOS transistors can be scaled to increasingly smaller dimensions. Smaller CMOS architecture dimensions allows for more transistors to be included into integrated circuits, which in turn, leads to improved microprocessor performance. Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10 μm in the 1970's to a present day size of 0.1 μm.
Practical scaling limits, however, are being reached for known technology. Consequently additional techniques, such as channel engineering, have been proposed for improving electrical properties of the transistor channel. One such technique is known as retrograde well engineering. Retrograde well engineering includes creating a particular doping profile (“well”) in the channel region of a transistor that affects the distribution of the electric field inside the transistor channel. Retrograde wells have been used to increase transistor drive without causing an increase in the off-state leakage current of the transistor. FIG. 1 illustrates a NMOS transistor 100 with a retrograde well 102 according to the prior art. The retrograde well 102 is typically formed by inserting a slow diffusing p-type dopant species such as indium (In) into a surface of a substrate 103 in an area corresponding to the channel region of the transistor 100. The device is then formed including typical structures such as source/drain regions 104, gate dielectric 106, gate electrode 108, and spacers 110.
Indium has the advantage of maintaining a concentration profile that is retrograde to the surface of the substrate even after substantial annealing. This retrograde profile results in improved electrical characteristics, such as a lower threshold voltage for the transistor compared to fast-diffusing p-type dopants, such as boron, that typically form non-retrograde wells after significant annealing. FIG. 2 illustrates a retrograde indium profile 202 for a conventional NMOS retrograde well. The indium profile 202 illustrates that the indium dopant concentration increases in the downward direction to a peak 204 of 1E18/cm3 at around 200 angstroms (Å) below the substrate surface, then decreases as the profile extends deeper into the substrate surface. The retrograde contour is essential to provide for an optimally minimal threshold voltage and an optimally minimal off-state leakage current.
In the current art, indium solubility in a silicon substrate is limited to, at best, about 3e18/cm3, which is approximately the concentration required to support off-state leakage currents for about a 90 nm gate. However, to support higher dopant levels for next generation gate lengths, 60 nm or below, higher dopant levels are required, or in other words, indium needs to have a higher concentration than 3e18/cm3, which is conventionally impossible to create. Simply using more indium does not work. During activation, the substrate can only hold a certain amount of indium before becoming saturated with excess indium molecules, causing the excess indium to diffuse, thus forming a concentration profile similar to the indium profile 206 illustrated in FIG. 2. The concentration profile 206 is not retrograde, thus resulting in an undesirably high threshold voltage for the transistor and, at best, the indium concentration is still only about 3E18/cm3 at the desired depth below the substrate surface.