Recent innovations in the design of nonvolatile memory cell arrays, such as bit line isolation by trenching, disclosed in U.S. Pat. No. 4,698,900, "Method of Making a Non-Volatile Memory Having Dielectric Filled Trenches" assigned to a common assignee, reduce current leakage and punch through to the point where individual cell sizes on the order of 13 square microns are achievable. The decreases in cell size which are necessary for fabricating higher density memory devices, e.g., greater than 1 megabit, also require significant reductions in programming voltages. Prior efforts to achieve these higher cell densities have required scale reductions in the cross sectional areas of bit lines. These reductions are known to result in increased bit line resistance, which, in turn, require more ohmic contacts to limit voltage losses. A greater number of contacts will increase the size of the array, in part cancelling out the effectiveness of the smaller cell size.
A need also exists for a floating gate memory cell which may be more rapidly and reliably programmed with a relatively low operating voltage. For example, even though the programming time of some prior art nonvolatile memory arrays is reasonably fast, such designs are known to achieve much less than 100% programmation per pass. If 90% of the cells were to program successfully on each pass, then a megabit memory would be expected to require six programming cycles to complete programming. It is desirable to reduce multiple program/read/reprogram cycles (known as "bit-banging") in order to fully program megabit and higher density memory devices at faster rates. An associated need exists for a fabrication method and process for forming such an improved memory device based upon well-known silicon technology.