1. Technical Field
The invention relates to analog-to-digital (A/D) converters, and in particular to a novel sigma-delta A/D type converter having a programmable input reference voltage circuit that enables conversion to be tailored to input voltage amplitudes.
2. Description of Related Art
Analog-to-digital (A/D) conversion is the process of converting a continuous range of analog signals into digital codes, or quantization levels. Increasing the maximum number of digital codes provides greater resolution and more granularity of scale which leads to more accurate digital sampling.
However, AID converters (also know as quantizers) have a maximum sampling rate that limits the speed at which they can perform continuous conversions, and hence the number of digital codes produced. The sampling rate is the number of times per second that the analog signal can be sampled and reliably converted into digital code. The minimum sampling rate must be at least two times the highest frequency of the analog signal sampled to satisfy the Nyquist sampling criterion (two times the highest frequency sampled is termed the "Nyquist rate"). Sampling above the Nyquist rate (oversampling) creates a more accurate digital representation of the analog signal.
There are many types of oversampling A/D conversion methods. So-called "sigma-delta conversion," one such method, is characterized by oversampling the analog input signal far above the Nyquist rate (e.g., between 16 and 256 times the Nyquist rate) and converting the oversampled signal to a digital signal.
Referring to FIG. 1, a conventional, first order, sigma-delta A/D converter arrangement 100 employs an oversampled modulator 112 sampling at a rate well above the Nyquist rate. The modulator 112 comprises an integrator 103 that performs a time domain integration of a sampled difference between an input analog waveform applied at input terminal 101 and a feedback signal produced by D/A converter 105, produced at summer 102. The output of integrator 103 is applied to A/D converter 104, the output of which is applied to a digital filter 106 and also fed back, through D/A converter 105, to summer 102.
A/D converter 104 and D/A converter 105 employed in modulator 112 may each be of single bit resolution (e.g., a simple comparator and a pair of switches coupling the comparator output to each of two reference voltages, respectively) or may be multi-bit circuits. The following discussion will assume the latter.
The analog input signal applied to input terminal 101, is oversampled at a high rate (e.g., greater than 16:1), and differentially summed with the feedback signal at summer 102 to produce an error signal to be applied to integrator 103. Integrator 103 in turn produces an integrated output signal of 1-bit resolution, converted to a multi-bit digital signal by A/D converter 104.
This multi-bit digital signal is applied to a digital filer 106 which removes quantization noise to provide an output signal of increased signal-to-noise ratio (SNR), a parameter that is a measure of performance as described in more detail later. The filtered signal is supplied by filter 106 to a decimator 107 that converts the filtered signal to a multi-bit word output at the Nyquist sampling rate (two times the maximum frequency of input bandwidth). Thus, an appropriately sized output multi-bit word is provided by decimator 107, but reduced from a high sampling rate of relatively low bit resolution to a lower sampling rate having relatively high bit resolution. Hence, digital filter 106 and decimator 107 convert oversampled A/D output signals from analog modulator 112 to a multi-bit Nyquist rate digital word.
A/D converter 104 also supplies its digital output signal to the input of a D/A converter 105 which performs a reconversion to an analog signal generally complementary to the operation of A/D converter 104. The reconverted analog signal is differentially summed with the input signal to derive the error signal that is integrated with the previous data sample and error values, and converted to an updated digital value.
The error signal applied to integrator 103 reflects not only changes in the input signal and aliasing errors due to the limit of resolution of A/D converter 104 (which will be reflected in the D/A converted signal), but also errors due to deviations from complementarity of the output signals produced by A/D converter 104 and D/A converter 105. Integrator 103 accumulates all such errors without regard to source. Therefore, to avoid discrepancies in the accumulated error value, the resolution and accuracy of the D/A conversion must be at least as great as that of the final decimated A/D conversion. D/A converter 105 must be capable of processing at least as many bits as the overall A/D converter 100 after filtering and decimation, at an accuracy not less than the incremental value corresponding to the least significant bit (LSB) of the overall A/D converter 100 after filtering and decimation.
The performance of sigma-delta converter is usually expressed in terms of signal-to-noise ratio (SNR), computed by dividing rms (root mean square) input signal power by quantization noise power. For example, for a conventional second order sigma-delta analog section (one having two summers and two integrators): EQU SNR=M.sup.5 *(30K.sup.2)/(.DELTA..sup.2.PI..sup.4) EQ (1)
where:
M is the oversampling ratio defined as the ratio of the sampling rate to the Nyquist rate; PA1 K is the peak amplitude of the input signal being converted; and PA1 .DELTA. is the range of the quantizer over which conversion is accomplished, and is dependent on a reference voltage (Vref) used in conjunction with the conversion process.
Performance of a conventional second-order sigma-delta converter is depicted graphically in FIG. 2 with reference to plots 102, 104, and 106 (dashed lines). The plots 102, 104, and 106 illustrate the relationship between SNR and relative input signal power for oversampling ratios (M) equal to 64, 128, and 256, respectively. With reference voltage held constant, the differences between plots 102, 104, and 106 are based on differences in oversampling ratios (M). An increase in oversampling ratio (M) yields increased performance as depicted by peaks 108a, 108b, and 108c with SNR levels that increase successively. For example, the peak SNR amplitude 108a for plot 102 (M=64) is approximately at 80 dB, whereas that for plot 106 (M=256) is approximately dB. It should be noted that peak SNR amplitudes for all three plots 102, 104, 106 occur at approximately -6 dB on the relative input power axis. This is because the sigma-delta converter generating plots 102, 104, 106 use the same constant reference voltage (Vref).
For plots 102, 104, and 106, the range (.DELTA.) is fixed and constant, with a constant reference voltage (Vref). Although range (.DELTA.) is shown only for plot 102, the ranges (.DELTA.) for plots 104 and 106 increase with an increase in oversampling rates (M) because the range (.DELTA.) is extended to the point where the plot crosses (not shown for 104, 106) the relative input power axis. The range (.DELTA.) of plot 102 spans between approximately -85 dB and slightly above zero on the relative input power axis. However, as quantizer saturation, clipping and distortion tend to occur above the -6 dB level, the operating range (.DELTA.) of plot 102 is shown as extending only up to -6 dB, because performance of the sigma-delta converter significantly drops off above that point.
Typically, range (.DELTA.) is also dependent on input power supply voltage level (Vdd). To optimize performance, it is desirable to match input amplitude (K) with the peak SNR level of the quantizer. This peak occurs at -6 dB for plot 102 at 108a. Replacing range (.DELTA.) in EQ (1) to determine peak performance yields the following equation (for K.ltoreq.Vdd/2): EQU SNR=M.sup.5 *(30K.sup.2)/((Vdd).sup.2.PI..sup.4) EQ (2)
By analyzing EQ (2), it is determined that the peak SNR performance of the quantizer is achieved when input amplitude (K) matches 1/2 of the range (.DELTA.) of the quantizer, i.e., when input amplitude (K)=Vdd/2.
However, a problem arises when input amplitude (K) fluctuates based on varying signals or varying applications for which the sigma-delta converter is used. In applications such as modem technology, input voltage amplitudes, and thus relative input power levels, fluctuate for various reasons. As the length of a telephone line that carries input signals requiring conversion is increased, the input voltage applied to the modem from that line tends to be reduced. Thus, the performance of the sigma-delta converter will vary depending on distance to the source. Furthermore, sigma-delta converters can be used in a variety of other applications, such as cellular telephones, hand-held camcorders, portable computers, and set-top cable TV boxes. Any of these applications can face fluctuating input signals depending on the time of use or the environment in which conversion is implemented.
One apparent disadvantage of conventional sigma-delta converters is that they are unable both to accommodate input signals having significant variance and maintain a high level of performance. Another disadvantage is an inability to shift range of performance to avoid saturation, clipping and distortion.