The invention relates to a monolithically integrated circuit arrangement wherein a group of one-transistor storage elements is provided arranged on a semiconductor layer. Each storage element is formed of a selection MIS field effect transistor and a storage capacitor. One electrode of the storage capacitor is fed with information potential to be stored, and is electrically connected to the drain zone of the field effect transistor. Source terminals of the field effect transistors of some of the group of storage elements are connected to a common bit line and gate terminals of field effect transistors of other of the storage elements are connected to a common world line.
A circuit arrangement of this type is disclosed in the German AS No. 25 53 591 and the magazine "Electronic Letters", Vol. 12, No. 6, Mar. 18, 1976, pages 140-141. A strip-shaped zone is provided which is oppositely doped to the semiconductor layer and which is connected to a reference potential R. The zone connects to reference electrodes arranged on a surface of the semiconductor substrate and consist, in particular, of inversion layers of the MIS storage capacitors of a plurality of storage elements. Here a MIS storage capacitor is understood as a capacitor which possesses a metallic gate electrode which is separated from a silicon layer by an insulating layer. This metallic gate electrode can be replaced by an electrically conductive gate electrode consisting of highly doped semiconductor material such as, for example, polysilicon. The items of data stored in the individual storage elements are governed by the voltages connected to the gate electrodes of the relevant MIS storage capacitors relative to the reference potential fed through the strip-shaped zone. Furthermore, between the storage capacitor zone and the field effect transistor of each individual storage element, there is arranged a zone in which the insulating layer which covers the surface of the semiconductor layer is fundamentally thicker than beneath the gate electrode of the storage capacitor. This prevents the inversion layer of the storage capacitor which forms on the surface of the semiconductor layer from extending to the drain zone of the assigned field effect transistor.