1. Field of the Invention
The present invention generally relates to the forming, in an integrated circuit chip in and/or on which are formed other active and/or passive components as well as corresponding connection lines of devices disturbing in terms of inductive and/or capacitive parasitic couplings. More specifically, the present invention relates to the forming of conductive lines intended to receive high-frequency and/or high currents, such as an inductive winding (inductance) intended to be used as an antenna for mobile phone, or a metal line intended to be used as an electrode for a capacitor of metal/insulator/metal type (MIM).
2. Discussion of the Related Art
Conventionally, an insulating area between such a conductive line and the underlying conductive levels, such as a semiconductor substrate, is provided to avoid or at least reduce possible capacitive and/or inductive couplings due to the flowing in the line of a high-frequency and/or high current.
FIGS. 1A to 1C illustrate, in a simplified partial cross-section view, conventional steps of forming of said lines on an integrated circuit chip. For clarity and as a non-limiting example, the forming of a single line, forming an inductive winding or inductance, will be considered.
FIG. 1A illustrates the state of an integrated circuit after initial steps preceding the forming of an inductance. At this stage of the process, a solid semiconductor substrate 10, typically made of silicon, in and on which are formed various elements, is covered with successive conductive layers, each layer including conductive portions separated by insulating portions. Only the last two layers, Mn−1 and Mn, formed before the inductance forming are detailed in FIG. 1. The various other layers between substrate 10 and layer Mn−1 are generally designated with reference 11. Layer Mn−1 includes metal portions 12, 13, separated by insulating portions 14. Similarly, upper layer Mn includes metal portions 15 separated by insulating portions 16.
At the next step, illustrated in FIG. 1B, an insulating layer 17 is deposited so that its upper surface is substantially planar. Insulating layer 17 is particularly thick as compared to insulators 14, 16 of underlying layers Mn−1, Mn. Thus, while insulators 14, 16 typically have a thickness on the order of from 0.5 to 1.5 μm, insulating layer 17 exhibits a thickness ranging between 5 and 20 μm.
At the next steps, an insulating layer 18 is deposited so that its upper surface is planar. Insulating layer 18 is opened according to the inductance pattern and a metal layer 19, generally made of copper, is deposited. Layer 19 is then etched to only be maintained in place in the pattern previously opened in layer 18. It is ascertained that only insulating portions are present in each of layers Mn, Mn−1 and of underlying layers 11 above inductance 19. Thick layer 17 has the object of insulating the lower levels (underlying substrate 10) from any inductive or capacitive parasitic coupling with inductance 19.
A disadvantage of the previously-described method results from the need to provide a thick insulating layer above the usual layers intended for the integrated circuit interconnections, the metal intended for the inductance forming being arranged above this thick insulating layer.