The present invention generally relates to semiconductor devices and more particularly to a direct-tunneling semiconductor memory device that stores information by injecting carriers into a floating gate by direct-tunneling of carriers and the fabrication process thereof.
A flash memory is a non-volatile semiconductor memory device having a simple structure in that a single MISFET constitutes a single memory cell and is used in various applications.
More specifically, a flash memory is a semiconductor memory device having a floating gate electrode provided on a channel region via a tunneling insulation film and has a control gate electrode formed in capacitive coupling with the floating gate electrode. Thus, a flash memory holds information in the floating gate electrode in the form of electric charges by injecting hot electrons induced in the channel region into the floating gate electrode through the tunneling insulation film.
Thus, in order to hold the electric charges thus injected into the floating gate electrode and to achieve the desired non-volatile memory operation, a flash memory uses a relatively thick tunneling insulation film typically having the thickness of 8-10 nm.
Thereby, injection of hot electrons is achieved by applying a writing voltage of 5-6V or higher to the control gate electrode. At the time of erasing the information, on the other hand, a high erasing voltage of 10-20V is applied to the control gate electrode and deformation of band structure is induced in the tunneling insulation film. Thereby, the electric charges injected into the floating gate electrode are withdrawn from the floating gate electrode in the form of Fowler-Nordheim (F-N) tunneling current.
With such a conventional flash memory that uses hot electrons injected into the floating gate electrode, on the other hand, there exists a problem in that most of the excited hot electrons are absorbed by the drain region of the device in the form of drain current, and only a small portion of the hot electrons are injected into the floating gate electrode. Thus, conventional flash memory has suffered from the problem of poor carrier injection efficiency and large power consumption. Further, with such a conventional flash memory, there exists another problem in that it takes a long time, at the time of erasing the written information, for pulling out the injected electrons through the thick tunneling insulation film in the form of the FN tunneling current. Thus, a conventional flash memory suffers from the problem of slow operational speed, particularly very slow erasing operation.
On the other hand, in the case retention (non-volatility) of written information is not important, it becomes possible to reduce the thickness of the tunneling insulation film, and thus, it becomes possible to realize a so-called direct-tunneling memory (DTM), in which injection and withdrawal of carriers is achieved through a thin tunneling insulation film by direct-tunneling phenomenon. Reference should be made to Patent Reference 1 or Non-Parent Reference 1.
Because such a direct-tunneling semiconductor memory device operates with high speed at low voltage, use thereof for replacing SRAMs or DRAMs is contemplated.
While non-volatility of written information is not important with a direct-tunneling semiconductor memory device, it is still preferable to hold the information, and thus the electric charges injected into the floating gate electrode. Because of this, a direct-tunneling semiconductor memory device requires a refreshing operation similar to one used in a DRAM.
In order to decrease the frequency of refreshing operation as much as possible and to realize so-called pseudo-nonvolatile operation, it is practiced in a direct-tunneling semiconductor memory device to form the source and drain diffusion regions offset in the silicon substrate from the region right underneath the floating gate electrode, such that leakage of the electric charges from the floating gate electrode to the source region or drain region is suppressed as much as possible.
FIG. 1 shows the construction of such a conventional direct-tunneling semiconductor memory device 100.
Referring to FIG. 1, the direct-tunneling semiconductor memory device 100 is formed on a device region defined on a silicon substrate 101 by a device isolation region 102 of LOCOS oxide film, or the like, and includes a very thin tunneling insulation film 103 having the thickness of 2-3 nm formed on the silicon substrate 101, a floating gate electrode 105 formed on the tunneling insulation film 103, and an upper control gate electrode 107 formed on the floating gate electrode 105 via an insulation film 106 in capacitive coupling with the floating gate electrode 105.
Further, the sidewall surfaces of the stacked gate electrode structure, which is formed of the floating gate electrode 105, the insulation film 106 and the upper control gate electrode 107, are covered with an insulation film 106S similar to the insulation film 106, and there are provided lateral control gate electrodes 108 at the respective outer sides of the insulation films 106S in capacitive coupling with the floating gate electrode 105 via the insulation films 106S. Further, the outer sidewall surfaces of the lateral control gate electrodes 108 are covered with sidewall insulation films 109, respectively.
Further, with this direct-tunneling semiconductor memory device 100 of conventional art, diffusion regions 110 are formed in the silicon substrate 101 at the both lateral sides of the stacked gate electrode structure as the source and drain regions, with offset from the floating gate electrode 105. Thereby, the diffusion regions 110 do not penetrate into the part of the substrate 101 right underneath the floating gate electrode 105.
Thus, with the foregoing direct-tunneling semiconductor memory device, escaping of the electric charges from the floating gate electrode 105 through the thin tunneling insulation film 103 is suppressed, and the direct-tunneling semiconductor memory device 100 of FIG. 1 shows pseudo non-volatility.
Table 1 below shows typical examples of operation of the direct-tunneling semiconductor memory device 100.
TABLE 1OperationalControlvoltage (V)gateDrainSourceSubstrateWrite5000voltage (V)Erase−5000voltage (V)Read1100Voltage (V)
Referring to Table 1, it will be noted that writing of information can be achieved by merely applying a voltage of about +5V to the control gate electrodes (CG) 107 and 108 while grounding the source region S and drain region D. Further, it will be noted that erasing can be achieved by merely applying a voltage of about −5V to the control gate electrodes 107 and 108.
At the time of reading, a read voltage of about +1V is applied to the control gate electrodes 107 and 108 while grounding the source region S and applying a drive voltage of +1V to the drain region D. In Table 1, “substrate” represents the substrate biasing.
Thus, with a direct-tunneling semiconductor memory device, there is no need of using a high voltage as is used in the conventional stacked type flash memory at the time of writing or erasing operation, and with this, it becomes possible to eliminate the high voltage circuit.
Because a direct-tunneling semiconductor memory device is not a normal non-volatile memory device, the information held therein is erased naturally with time as a result of dissipation of the electric charges. On the other hand, the device does have pseudo non-volatility, it becomes necessary in such a device to carry out erasing operation shown in Table 1 for achieving high-speed rewriting.
(Patent Reference 1) Japanese Laid-Open Patent Application 2002-16155 official gazette
(Patent Reference 2) Japanese Laid-Open Patent Application 2000-150680 official gazette
(Patent Reference 3) U.S. Pat. No. 6,165,292
(Non-patent Reference 1) Usuki, T., et al., Advantage of a quasi-nonvolatile memory with ultra thin oxide, SSDM2001, p. 532 2001