1. Field of the Invention
This invention relates in general to decoupling capacitors for integrated circuits, and more particularly to a method and apparatus for providing improved loop inductance of decoupling capacitors.
2. Description of Related Art
Recent developments in integrated circuit technologies have led to higher levels of performance and faster operation speeds and, also, have led to the development of more complex integrated circuits (ICs). These and other achievements and increased levels of complexity has made it more and more difficult to maintain the power source level applied to an integrated circuit (IC) within a prescribed range. For example, technological achievements in integrated circuit technologies have driven the operating frequencies (e.g., clocking speeds) to much higher levels and, correspondingly, are driving voltages as well as noise margins lower and lower.
Surface mount capacitors are typically mounted close to logic chips on nearly all Printed Circuit Board (PCB) designs. These capacitors serve as temporary, low inductance current supplies to the nearby logic devices which are drawing current between the PCB power and ground planes. In this way the capacitors decouple the two main functions of the power and ground planes: supplying DC current and controlling high frequency noise. The ability of the capacitors to provide temporary AC shorts between planes also enables return currents to flow uninterrupted near signal lines when the signal lines switch layers in a printed circuit board.
Common practice for dealing with power surges and noise problems is to add decoupling capacitors, electrically in parallel, until a sufficiently low inductance path between voltage supply planes is created. This is often accompanied by capacitors that use a range of values. This results in the need for more capacitors of differing values to accomplish a sufficiently low inductance, which adds to product cost and is arguably ineffective.
Decoupling problems are most acute for high performance printed circuit board designs, such as those with high speed logic, impedance controlled interconnect lines, and multiple voltage levels. Problems arise from noise in the voltage supply planes adversely affecting logic chips and from return current discontinuities causing excessive coupling between signal lines.
The series input inductance of an individual, mounted capacitor is due in large part to the relative arrangement of the capacitor's surface mount pads and its via breakouts, which provide connections from the top of the board to the internal voltage planes. However, the placement of the power and ground vias relative to the pads has never been minimized. This results in input inductance that violate today's electrical requirements.
It can be seen then that there is a need for a novel pad and via arrangement which reduces the mounted capacitor's input inductance without violating common manufacturing requirements for certain minimum separations.
It can also be seen that there is a need for a method and apparatus that reduces the input inductance for mounted capacitors as well as minimizing the number of capacitors required.