1. Field of the Invention
The present invention relates to a method for fabricating a gate of a semiconductor device, and more particularly, to a method for forming an isolation layer for a trench.
2. Description of Related Art
As the integration extent of a semiconductor device increases, many researches have been made to develop a technology for reducing an isolation region. Shallow Trench Isolation (STI) was introduced as an isolation technology for the next generation devices having high integration through flatness of an isolation region and precise design rule.
FIG. 1A is a plane view illustrating a typical gate of a metal oxide semiconductor (MOS) transistor according to the related art, and FIG. 1B is a cross-sectional view illustrating the gate of FIG. 1 taken along the line I-I′. FIGS. 2A to 2H are cross-sectional views illustrating the gate of FIG. 1A taken along the line I-I′ for describing a STI process.
As shown in FIG. 2A, a pad oxide layer 102 and a pad nitride layer 104 are formed on a substrate 100.
As shown in FIG. 2B, an etch mask 106 for forming a trench is formed on the pad nitride layer 104.
As shown in FIG. 2C, trenches 108 are formed in the substrate 100 by performing an etch process using the etch mask 106. In the etch process, the pad nitride layer 104, the pad oxide layer 102, and the substrate 100 are partially etched. As a result, a pad nitride pattern 104A, a pad oxide layer pattern 102A, and a substrate 100A internally having the trenches 108 are formed.
As shown in FIG. 20, the etch mask 106 (see FIG. 2C) is removed.
Then, a sidewall passivation layer 110 is formed on an inner side of the trenches 108.
As shown in FIG. 2E, an insulation layer 112 is deposited until filling up the trenches 108.
As shown in FIG. 2F, a first isolation layer pattern 112A is formed in the trenches 109 by removing the pad nitride layer pattern 104A (see FIG. 2E) after polishing the insulation layer 112 (see FIG. 2E).
As shown in FIG. 2G, the pad oxide layer pattern 102A (see FIG. 2F) is removed by etching the pad oxide layer pattern 102A. In this process, portions of the first isolation layer pattern 112A and the sidewall passivation pattern 110 are also etched to thereby form a second isolation layer pattern 112B and a sidewall passivation pattern 110A
Then, a gate insulation layer 114 and a gate conductive layer 116 are formed on an active region 101 of the substrate 100A as shown in FIG. 1B and FIG. 2H. Here, the gate insulation layer 114 is formed by oxidizing the active region 101 through an oxidation process performed in an oxygen (O2) atmosphere.
However, the STI process of the semiconductor device according to the related art has following problems.
In FIG. 2D, the sidewall passivation layer 110 is formed by oxidizing the inner sidewall of the trench through an oxidizing process. Since impurities in the substrate 100A are absorbed at the sidewall passivation layer 110, the impurity concentration of an upper corner portion 120 (see FIG. 2H) of the trench 108 varies. The impurity concentration in the substrate 100A effects the growth of the gate insulation layer 114.
Therefore, the growth of the gate insulation layer becomes thinner than a target thickness at the upper corner portion of the trench 108 as shown in FIG. 3 when the gate insulation layer 114 is grown in FIG. 2H. Accordingly, the gate insulation layer cannot be uniformly grown, a breakdown voltage is reduced and gate oxide integrity (GOI) is deteriorated as shown in FIG. 4.
Furthermore, a parasitic transistor having a threshold voltage lower than an original channel is formed due to the impurity concentration variation of the upper corner portion 120 of the trench 108. Therefore, a leakage current increases when an OFF operation of a transistor is performed. Such a leakage current deteriorates the performance of a transistor that functions as a switching element and degrades threshold voltage mismatching. As shown FIG. 5, a product thereof may perform poor operation because it shows an I-V curve characteristic that cannot be expressed as a SPICE model.