According to a scaling rule, microfabrication of the field-effect transistor (MISFET:Metal Insulator Semiconductor Field Effect Transistor) is done as high integration of a semiconductor device progresses. However, resistance of a gate or a source/drain increases and the problem that high-speed operation is not obtained even if microfabrication of the field-effect transistor is done happens. Then, the salicide technology which reduces resistance of a gate and a source/drain by forming the metal silicide layer of low resistance, for example a nickel silicide layer or a cobalt silicide layer on the front surface of the electric conduction film which forms a gate, and the semiconductor region which forms a source/drain, by self align is examined.
In Japanese patent laid-open No. 2005-109504 (Patent Reference 1), the technology regarding the manufacturing method of a semiconductor element including the stage which forms a metal layer on a gate electrode and a source/drain region, the stage of performing the surface treatment of the metal layer using Ar plasma, and the stage which does annealing treatment of the silicon substrate in which the metal layer was formed at a predetermined temperature, and forms a silicide thin film is described.
In Japanese patent laid-open No. 2006-294861 (Patent Reference 2), the technology regarding the method of forming a metal inclusion film on Si inclusion part front surface of providing the physical-surface-treatment step which processes the front surface of Si inclusion portion physically by the plasma using high frequency, the chemical cleaning step which processes chemically the front surface of Si inclusion portion where processing by plasma was performed with reactive gas, and the film formation step which forms a metal inclusion film on Si inclusion portion to which chemical cleaning was performed is described.
In Japanese patent laid-open No. 2003-119564 (Patent Reference 3), the technology which forms continuously a film including a high melting point metal on the Si substrate from which the natural-oxidation film was removed within the same chamber that had etching and film formation optimized after removal of the natural-oxidation film which is on the surface of a Si substrate within the chamber of a plasma CVD device without exposing the Si substrate from which this natural-oxidation film was removed to the atmosphere is described.
[Patent Reference 1] Japanese patent laid-open No. 2005-109504
[Patent Reference 2] Japanese patent laid-open No. 2006-294861
[Patent Reference 3] Japanese patent laid-open No. 2003-119564