1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device and a method for fabricating the same suitable for increasing its tolerance and packing density.
2. Discussion of the Related Art
Since high integration densities have been required, many methods are being suggested in which the packing density of a semiconductor device is heightened. Among them, one is often used in which a width of a gate electrode is reduced. This method has problems that it is hard to prevent punch-through and that short channel effect is easily generated so that the reliability becomes deteriorated. Accordingly, a method for increasing the tolerance as well as packing density of a semiconductor device is desired.
A conventional semiconductor device and a method for fabricating the same will be described below with reference to the accompanying drawings.
FIG. 1A is a plan view of a semiconductor device and FIG. 1B is a cross-sectional view taken along line I--I of FIG. 1A.
As shown in FIGS. 1A and 1B, a shallow trench isolation (STI) region 2 is formed beneath the surface of a semiconductor substrate 1 at a field region. A gate oxide film 3 and a gate electrode 4 are formed, stacked in a direction on the semiconductor substrate 1 at an active region. A sidewall spacer 6 having a predetermined thickness is formed on the sides of the gate electrode 4. Lightly doped impurity regions 5 are formed beneath the surface of the semiconductor substrate 1 under the sidewall spacer 6. Source and drain regions 7a and 7b are formed beneath the surface of the semiconductor substrate 1 at both sides of the gate electrode 4 and its sidewall spacers 6. Silicide layers 8a are formed on the gate electrode 4 and on the source and drain regions 7a and 7b.
A conventional method for fabricating a semiconductor device will be described with reference to the accompanying drawings.
As shown in FIG. 2A, field and active regions are defined in a semiconductor substrate 1, and then shallow trenches are formed at the semiconductor substrate 1 of the field region. Next, an oxide film is deposited on the shallow trenches and a polishing process is then subjected to the oxide film for the purpose of planarization, thus forming shallow trench isolation regions 2.
A thin oxide film is formed by performing a thermal oxidation process over the entire surface. A polysilicon layer is coated on the oxide film. Subsequently, the polysilicon layer and the oxide film are anisotropically etched by using a gate-forming mask, thus forming a gate oxide film 3 and a gate electrode 4. At this time, the width of the gate electrode 4 should be narrower than that of a general gate electrode in order to increase the packing density of the semiconductor device.
As shown in FIG. 2B, with the gate electrode 4 serving as a mask, ions are lightly implanted into the active region, thus forming LDD regions 5. Thereafter, A chemical vapor deposition (CVD) process is performed to the entire surface to deposit either an oxide film or a nitride film and an anisotropical etching process is subjected to form sidewall spacer 6 surrounding the side of the gate electrode 4.
As shown in FIG. 2C, with the sidewall spacer 6 and the gate electrtode 4 serving as masks, source and drain regions 7a and 7b are formed in the active region at both side of the gate electrode 4. Thereafter, a metal layer 8 made of, for example, Ti, Co, Mo, or Ni is deposited so that it reacts with silicon layer to form silicide.
As shown in FIG. 2D, an annealing process is performed to form silicide layers 8a on the source and drain regions 7a and 7b and the gate electrode 4. Thereafter, the metal layer 8 that doesn't turn silicide is removed.
A conventional semiconductor device and a conventional method for fabricating the same have problems. Since the width of a gate electrode is reduced too much for the high integration of a semiconductor device, it is difficult to accomplish good reliability.