The present invention relates to an interrupt controller, and more particularly, relates to an interrupt routing mechanism for routing interrupts from a peripheral bus to an interrupt controller for booting an operating system (OS).
Computer systems are designed to support one or more input/output (I/O) devices, including, for example, keyboards, input mouses, disk controllers, serial and parallel ports to printers, scanners, and display devices. These P,O devices require intermittent servicing by a host processor in order to ensure proper operation. Services may include data transmission, data capture and/or any other data manipulative operations essential to the functionality of the I/O devices. Each I/O device may have a different servicing schedule that is defined by the type of I/O device and its current condition. The host processor is required to service these I/O devices in accordance with their individual needs while running one or more background programs. Two methods of advising the host processor of a service need from an I/O device have been used: polled device and device interrupt method. In the former method, each I/O device is periodically checked to see if a flag has been set indicating a service request, while, in the latter method, the device service request is routed to an interrupt controller that can interrupt the host processor, forcing a branch of its current program to a special interrupt service routine. The interrupt method provides much improved processing efficiency in comparison with polling since interrupt routines are executed only when required.
A well known example of an interrupt controller is the 8259 Programmable Interrupt Controller (PIC) manufactured by Intel Corporation. Each 8259 PIC may include up to eight interrupt request lines (IR0-IR7) to service interrupt request inputs from various I/O devices and an interrupt (INTR) output line to the host processor. Multiple 8259 PIC configurations may be available to provide an expanded number of usable I/O interrupt request lines. Generally, one or more of the 8259 PIC""s interrupt request inputs may be asserted at any given time. The 8259 PIC uses a priority scheme to determine which of the pending interrupt requests is the most important, and then passes that interrupt request along to the host processor by asserting the processor interrupt request via the INTR output line. However, the 8259 PIC was designed for single processor implementations and has no mechanism to direct interrupt requests to different processors in multi-processor systems such as servers and/or workstations.
A more advanced interrupt controller is known, for example, as the 82489DX Advanced Programmable Interrupt Controller (APIC) also manufactured by Intel Corporation. The APIC system supports 8259 compatible operations, but provides a more flexible and easy to implement solution for handling interrupt requests from I/O devices in a multi-processor system when compared to the 8259 mechanism. Such an APIC system typically includes an I/O APIC module which receives interrupt requests from I/O devices and routes those interrupt requests to local APIC modules embedded in different processors of a multi-processor system over a dedicated APIC bus, as described in detail in a publication entitled xe2x80x9c82489DX Advanced Programmable Interrupt Controllerxe2x80x9d published by Intel Corporation. The APIC interrupt architecture is well described in the xe2x80x9cMultiProcessor Specification (MPS)xe2x80x9d Version 1.1., September 1994, Order Number 242016-003 from Intel Corporation.
Since the APIC system is a relatively new system component, only most recent operating systems (OS) such as Microsoft Windows NT and Windows 2000 Operating Systems may handle necessary levels of interrupts for processors using APIC systems. Many popular operating systems such as Microsoft Windows 95/98, Sun Solaris and Netware Novell may not support APIC systems. Therefore, 8259 PIC may be incorporated into a system board along with the APIC system to ensure proper operation of an operating system (OS) regardless whether such an operating system (OS) may or may not support an APIC system. However, external logic devices are required to route particular interrupts from a non-legacy peripheral bus to the 8259 PIC. General purpose I/O pins are then needed to enable/disable this functionality once an operating system (OS) which understands the APIC system is loaded. In addition, special software must also be written to operate those general purpose I/O pins to steer those particular interrupts to the 8259 PIC. Accordingly, there is a need for an efficient means for routing interrupts from a peripheral bus such as a non-legacy PCI bus to an interrupt controller such as Intel 8259 PIC for booting an operating system (OS).
Accordingly, various embodiments of the present invention are directed to an interrupt routing mechanism of a host chipset for routing interrupts from a peripheral bus to an interrupt controller external to the host chipset. Such an interrupt routing mechanism comprises input terminals coupled to interrupt request lines of input/output (I/O) devices from the peripheral bus, to receive incoming interrupts from the peripheral bus; and logic circuitry operated to logically combine the interrupts and to pass an output boot interrupt to the interrupt controller, when an operating system does not support an advanced peripheral interrupt controller integrated in the host chipset.