The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the electronic design methodologies. In modern electronic circuits, the total number of transistors have increased; geometries have become smaller; and clock frequencies have increased over time. IR-drop in a power net supplying power to a chip has been found to have more critical impact on the timing behavior of the chip. Inaccurate capturing of the IR-drop in a power net may thus cause an electronic design to deviate from the timing requirements in physical optimizations and corrections, not to mention the lack of characterizing the IR-drop in the power net. For example, a Vdd power net may exhibit 100 mV IR-drop that may cause the timing behavior through a single MOS device to deviate by tens of picoseconds, especially when considering that a common power net in an integrated circuit (IC) may include many hundreds of thousands of Vdd and Vss nodes. The aggregated deviation in timing through a collection of such devices may simply cause an electronic design to fail the timing requirements. This problem is exacerbated due to the ever increase in the sizes of and complexities in power nets.
Some conventional approaches model the power net with individual circuit components. Although these approaches may achieve satisfactory accuracy, these conventional approaches are impractical to cope with the sizes and complexities of modern electronic designs. That is, these conventional approaches not only require much more computational resources but also often cannot produce useful results in a timely manner to satisfy the time-to-market requirement. Some other approaches adopt various circuit reduction techniques to reduce the size of a power net for electrical analyses. These other approaches are more efficient from the computer runtime perspective but at the price of accuracy and thus present marginal benefits over the former conventional approaches. Some of these approaches try to balance between accuracy and performance and employ conservative circuit reduction techniques with relatively low reduction ratios in sizes. These approaches offer inferior performance than approaches with aggressive circuit reduction techniques and inferior accuracy than approaches modeling details of the power net.
Moreover, some circuit reduction techniques often combine multiple nodes into a single node that assumes a single voltage value whereas the voltage values at these multiple nodes may in fact differ from each other by tens of millivolts in the actual design. These reduction techniques combining multiple nodes into a single node may thus cause further deviation in the electrical analysis results and thus further impact the timing behavior. Some other approaches adopt a multi-level electrical analysis methodology where the first level electrical analysis is performed upon the assumption of an ideal power supply, and the subsequent stage of electrical analysis uses the results from the first stage to characterize the electrical characteristics of an electronic circuit. These approaches may achieve somewhat satisfactory results only when the assumption is valid or when the underlying electronic circuit is relatively benign not to be affected by such an unrealistic assumption.
Therefore, it is important for an EDA tool to adequately and accurately perform electrical analyses to correctly and efficiently capture potential IR drop in an electronic design.