The present invention relates to integrated circuit devices and, more particularly, integrated circuit devices including capacitors and methods for manufacturing such integrated circuit devices.
As the integration density of integrated circuit devices has increased, it has become more difficult to obtain a desired capacitance in a conventional Metal-Insulator-Semiconductor (MIS) capacitor, for example, due to a low k-dielectric layer formed between a dielectric layer and a silicon layer. An alternative to an MIS capacitor is a metal-insulator-metal (MIM) capacitor.
FIG. 1 is a cross-sectional diagram illustrating an integrated circuit (semiconductor) device including a conventional MIM capacitor coupled to a transistor. As shown in FIG. 1 a first transistor includes a gate 13a, a source 15, and a drain 17a formed in an integrated circuit substrate 11. A second transistor includes a gate 13b and a drain 17b formed in the integrated circuit substrate 11. The second transistor also includes the source 15.
The drain 17a of the first transistor is connected to a lower electrode 21 of a MIM capacitor via a conductive pattern 19. A dielectric layer 23 and an upper electrode 25 of the MIM capacitor are formed on the lower electrode 21. The lower electrode 21 and the upper electrode 25 are conductive metal layers. An interconnection layer 27 is formed on and connected to the upper electrode 25 of the MIM capacitor.
The drain 17b of the second transistor is connected to an upper interconnection layer 33 via the conductive pattern 19 and interconnection layers 29 and 31. While not shown in FIG. 1, the interconnection layer 27 may also be connected to the upper interconnection layer 33. Also shown in FIG. 1 are insulating layers 35, 45, 55, and 65.
One limitation on the performance of the MIM capacitor illustrated in FIG. 1 is the insufficient distance between the interconnection layer 27 and the lower electrode 21. As this distance is reduced, an undesirable level of parasitic capacitance may develop, which parasitic capacitance may adversely affect the characteristics of the MIM capacitor. Problems become more severe when the thickness of the insulating layers is reduced, because parasitic capacitance of the device is generally inversely proportional to the thickness of the insulating layer.
FIG. 2 is a graph illustrating a simulation of the influence of parasitic capacitance for different thicknesses of an insulating layer, such as the insulating layer 55. As illustrated in FIG. 2, as the thickness of the insulating layer decreases, the parasitic capacitance increases in a non-linear manner.
Thus, for a conventional integrated circuit device including a MIM capacitor as illustrated in FIG. 1, an increase in parasitic capacitance between the interconnection layer 27 and the lower electrode 21 may degrade and/or reduce the stability of the characteristics of the MIM capacitor. In addition, the variability of the parasitic capacitance based on process variables such as the thickness of an insulating layer may increase the difficulty of forming MIM capacitors with stable characteristics.