Field of the Invention
The present invention relates to a semiconductor device.
Description of the Related Art
With the recent increase in the integration of semiconductor integrated circuits, semiconductor chips having as large a number of transistors as 1,000,000,000 (1 Giga (G)), have been developed for state-of-the-art micro-processing units (MPUs). As disclosed by Hirokazu YOSHIZAWA in “Shi mosu opi anpu kairo jitsumu sekkei no kiso (Fundamentals on CMOS OP amp circuit design for practical use)”, CQ Publishing Co., Ltd., page 23, conventional transistors formed in a planar manner, called planar transistors, require complete isolation of an n-well region which forms a p-channel metal-oxide semiconductor (PMOS) and a p-type silicon substrate (or p-well region) which forms an n-channel metal-oxide semiconductor (NMOS) from each other. In addition, the n-well region and the p-type silicon substrate require body terminals for applying potentials thereto, which will contribute to a further increase in the area of the transistors.
To address the issues described above, a surrounding gate transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and in which the gate surrounds an island-shaped semiconductor layer has been proposed, and a method for manufacturing an SGT and a complementary metal-oxide semiconductor (CMOS) inverter, a NAND circuit, or a static random access memory (SRAM) cell which employs SGTs are disclosed (see, for example, U.S. Pat. No. 8,039,893 B2 and its counterpart Japanese Patent No. 5130596; U.S. Pat. No. 8,901,640 B2 and its counterpart Japanese Patent No. 5031809; Japanese Patent No. 4756221, and published application No. US 2010/0219483 A1 and its counterpart International Publication No. WO2009/096465).
FIG. 19, FIG. 20A, and FIG. 20B illustrate a circuit diagram and layout diagrams of an inverter that employs SGTs.
FIG. 19 is a circuit diagram of the inverter. The symbol Qp denotes a p-channel MOS transistor (hereinafter referred to as a “PMOS transistor”), the symbol Qn denotes an n-channel MOS transistor (hereinafter referred to as an “NMOS transistor”), the symbol IN denotes an input signal, the symbol OUT denotes an output signal, the symbol Vcc denotes a power supply, and the symbol Vss denotes a reference power supply.
FIG. 20A illustrates a plan view of a layout of the inverter illustrated in FIG. 19, which is formed of SGTs, by way of example. FIG. 20B illustrates a cross-sectional view taken along a cut-line A-A′ in the plan view of FIG. 20A.
In FIG. 20A and FIG. 20B, an insulating film such as a buried oxide (BOX) film layer 1 disposed on a substrate has formed thereon planar silicon layers 2p and 2n. The planar silicon layers 2p and 2n are formed as a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like. A silicide layer 3 disposed on surfaces of the planar silicon layers (2p and 2n) connects the planar silicon layers 2p and 2n to one another. Reference numeral 4n denotes an n-type silicon pillar, and reference numeral 4p denotes a p-type silicon pillar. Reference numeral 5 denotes a gate insulating film that surrounds each of the silicon pillars 4n and 4p. Reference numeral 6 denotes a gate electrode, and reference numeral 6a denotes a gate line. A p+ diffusion layer 7p and an n+ diffusion layer 7n are formed on top portions of the silicon pillars 4n and 4p, respectively, through impurity implantation or the like. Reference numeral 8 denotes a silicon nitride film for protection of the gate insulating film 5 and the like. Reference numerals 9p and 9n denote silicide layers connected to the p+ diffusion layer 7p and the n+ diffusion layer 7n, respectively. Reference numerals 10p and 10n denote contacts that connect the silicide layers 9p and 9n to metal lines 13a and 13b, respectively. Reference numeral 11 denotes a contact that connects the gate line 6a to a metal line 13c. In the following, the planar silicon layers 2p and 2n are also referred to as the lower diffusion layers 2p and 2n, and the diffusion layers 7p and 7n are also referred to as the upper diffusion layers 7p and 7n. 
The silicon pillar 4n, the lower diffusion layer 2p, the upper diffusion layer 7p, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp. The silicon pillar 4p, the lower diffusion layer 2n, the upper diffusion layer 7n, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn. Each of the upper diffusion layers 7p and 7n serves as a source, and each of the lower diffusion layers 2p and 2n serves as a drain. The metal line 13a is supplied with the power supply Vcc, and the metal line 13b is supplied with the reference power supply Vss. The input signal IN is connected to the metal line 13c. The output signal OUT is output from the silicide layer 3 that connects the lower diffusion layer 2p serving as the drain of the PMOS transistor Qp to the lower diffusion layer 2n serving as the drain of the NMOS transistor Qn.
The inverter that employs SGTs illustrated in FIG. 19, FIG. 20A, and FIG. 20B has a feature of enabling a very compact layout (arrangement) since the PMOS transistor and the NMOS transistor are structurally isolated completely from each other, eliminating the need for isolation of wells unlike planar transistors, and, in addition, since the silicon pillars are used as floating bodies, eliminating the need for any body terminals for supplying potentials to the wells unlike planar transistors.
As described above, the most outstanding feature of SGTs is that it is possible to utilize, in terms of structural principles, a lower-layer line implemented in a silicide layer located close to a substrate below a silicon pillar and an upper line implemented by connection via a contact above the silicon pillar.