1. Field of the Invention
The present invention generally relates to the design of semiconductor chips and integrated circuits, and more particularly to a method of computing slew rates and gate delays for timing closure.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, combinatorial cells, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 may be used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, and cells and the cell-pins creating interconnections with the nets. The netlist is transformed over the design process. The cells are assigned selections from a library of possible choices and have specific characteristics such as delay, power or area. A cell's location, or placement, is assigned in the resultant chip. The nets in the netlist are routed (wired) from cell-pin to cell-pin in a unique physical path. The netlist is checked during the refinement process to see if it meets requirements such as timing or power. Eventually, the netlist is elaborated into a layout which typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements for fabrication such as matching the function the of original netlist. The result is a set of design files known as an intermediate form that describes the layout. The design files are then run through a dataprep process that is used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to etch or deposit features in a silicon wafer in a sequence of photolithographic steps using a complex lens system that shrinks the mask image. The process of converting the specifications of an electrical circuit into such a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different hardware-design languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between static-timing analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete, and the computational requirements are increasing as designs with more gates need to be placed.
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales with 90 nm technology and beyond, the impact of wire delay is becoming more dominant in the overall timing closure of the circuits comprising ICs such as ASIC chips and systems such as servers. Static-timing analysis is a process where the delay of a circuit is calculated assuming the worst input criteria, it provides a bound to circuit performance and is significantly computationally faster than circuit simulators such as SPICE. Timing is divided into individual circuits usually bounded by memoried elements like a latch that capture or launches a logic signal on a clock edge. Timing paths then comprise a specific path from a launching point to a capture point through a set of nets, cells and the pins connecting them. While most cells have more than one input, and often more than one output, timing analysis for a path can be simplified for the purposes of example as a path comprising single input and output cells. The timing of other paths through a cell from other launching and capture points must be calculated in a similar manner. Static-timing analysis provides a method to prune this analysis for efficiency.
As part of the timing analysis, it is necessary to compute delays caused by gates in the circuit. Gate delay is further dependent on the slew of the incoming signal. Slew (or slew rate) refers to the rise time or fall time of a switching digital signal. Different definitions can be used to quantify slew, the most common being the 10/90 slew which is the time it takes for a waveform to cross from the 10% signal level to the 90% signal level. Other definitions such as 20/80 slew or 30/70 slew are often used when the waveform has a slowly rising or falling tail. The slew is altered by the capacitance and resistance of the interconnecting nets as well as the gain of the transistors within a cell.
One common way of measuring slew is referred to as path-slew mode, wherein all slew rates are propagated through all wires and logic to compute the slew rate at any given gate. This approach is illustrated in the example of FIG. 1. The input signal has a slew of 40 ns, and a wire length leading to the first gate A increases the slew to 60 ns. Based on this input slew, gate A incurs a delay of 26 ns. Gate A refreshes the signal so the slew drops to 32 ns, and after another wire length it rises to 45 ns for input to gate B. Based on this input slew, gate B incurs a delay of 20 ns, and the output signal from gate B has a slew of 27 ns. While this approach is the most accurate, propagating the slew rate of a signal through the circuit is one of the most costly computations for incremental timing closure. Moreover, changes in slew rate typically do not propagate beyond a small number of logic levels. In order to mitigate the runtime expense of accurate slew rate computation, an abstraction called pin-slew mode can be used. In pin-slew mode the slew rate at a given gate is computed by asserting a default slew rate at the input pin of the gate of the previous logic stage. The default slew rate can be provided by the designer but is typically a mean of a random sample of slew values taken from the circuit design. That default slew rate is then propagated through the input gate and its output net to find the slew rate at the gate under consideration.
While pin-slew mode is much faster than path-slew mode, pin-slew mode can lead to significant inaccuracies, particularly near the switch in the analysis from pin-slew mode to path-slew mode. It would, therefore, be desirable to devise an improved method of computing slew rates that is faster than path-slew mode but more accurate than pin-slew mode. It would be further advantageous if the method could be implemented with low overhead and be readily incorporated in existing physical design flows.