1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a phase-change memory device for compensating for a leakage current in a read operation.
2. Description of the Related Art
When a Phase-Change Random Access Memory (PRAM) is heated and then cooled, the PRAM is maintained in one of two states, and is made of phase-change material such as chalcogenide alloy that can be again changeable by a heating and cooling operation. The two states are a crystalline state and an amorphous state. The PRAM has been disclosed and described in U.S. Pat. No. 6,487,113 and U.S. Pat. No. 6,480,438.
In a PRAM, the resistance is low in the crystalline state and is high in the amorphous state. The logic value of the PRAM is determined as 0 or 1 by the resistance value. The crystalline state corresponds to set or logic 0, and the amorphous state corresponds to reset or logic 1.
To change the phase-change material of the PRAM to its amorphous state, the PRAM is heated by resistance heat above the melting point of the phase-change material, and then is rapidly cooled. To change the phase-change material to the crystalline state, the phase-change material is heated for a predetermined time at a temperature under the melting point.
The kernel of the phase-change memory is the phase-change material, such as chalcogenide. The phase-change material, generally called a GST alloy, contains germanium (Ge), antimony (Sb) and tellurium (Te). The GST alloy has the properties of being rapidly changed by a heating and cooling operation between the amorphous state (reset or 1) and the crystalline state (set or 0), and thus it can be usefully applied to a memory device.
Phase-change materials have a high resistance in the amorphous state and a low resistance in the crystalline state.
A memory cell made of chalcogenide as a phase-change material includes a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode and an access transistor. The operation of reading a programmed cell is performed by measuring the resistance of the chalcogenide material. Programming, or the write operation, denotes that a memory cell has reset and set states and has corresponding logic values of 1 and 0 respectively.
Writing data in a memory cell is accomplished by heating chalcogenide above its melting point and then by rapidly cooling it to enter its amorphous state, or by heating it at a temperature under its melting point, maintaining the temperature for a predetermined time and then cooling it to enter its crystalline state.
FIGS. 1A and 1B illustrate a conventional memory cell in set and reset states.
A memory cell 100 includes a top electrode 12 having conductivity, formed on a phase-change material 14. A bottom electrode contact (BEC) 16 having conductivity connects the top electrode 12 and the phase-change material 14 with a bottom electrode 18 having conductivity.
Referring to FIG. 1A, the memory cell 100 is in the set state or the logic 0 state. In this state the phase-change material 14 has a crystalline state. Referring to FIG. 1B, the memory cell 100 is in the reset state or the logic 1 state. In this state the phase-change material 14 has an amorphous state.
FIGS. 1A and 1B respectively include an access transistor N20 for controlling the current flowing through the memory cell. When current flows through the memory cell 100, the bottom electrode contact 16 operates as a heater for heating the phase-change material 14 to change its state.
FIG. 2 illustrates an electric circuit configuration of a memory cell shown in FIGS. 1A and 1B.
In FIG. 2, a word line WL controls the activation of the memory cell 100. A current ICELL flowing through the memory cell 100 and a bit line BL are used in programming or reading the memory cell 100.
FIG. 3 illustrates conventional time-temperature curves for programming the phase-change material. FIG. 3 also shows the correlation between the time and the temperature of a programming pulse for programming the phase-change material to a set or reset state according to a conventional programming method.
In FIG. 3, a reset curve 35 illustrates the time-temperature correlation of a reset pulse, and a set curve 36 illustrates the time-temperature correlation of a set pulse.
With reference to the reset curve 35 of FIG. 3, to program the phase-change material to the reset state, the phase-change material is heated above its melting point Tm. Next, heat is applied to the phase-change material for a short time. Then the phase-change material is cooled rapidly. In the set curve 36 of FIG. 3, to program the phase-change material to the set state, the phase-change material is heated to a temperature under its melting point Tm. The temperature corresponds to a set window provided between the melting point Tm and a crystalline temperature Tx. The temperature is maintained for a predetermined time and then the phase-change material is cooled.
FIG. 4 illustrates a conventional current-voltage curve of the phase-change material.
Referring to FIG. 4, there is a reset state {circle around (1)} and a set state {circle around (3)} for a read operation, and a program state {circle around (2)} to program the phase-change material to a set state. For the read operation of a memory cell, a voltage applied to the phase-change material should be smaller than a threshold voltage Vth of the phase-change material. A voltage Vread for the read operation is applied to the phase-change material in a range of, e.g., 0.4Vth-0.6Vth. For a read operation, a read current Iread is applied to the bit line of the memory cell.
When a leakage current escapes to non-selected memory cells connected to the same bit line, the read current Iread necessary for a read operation cannot be sufficiently supplied to the selected memory cell, which may cause read error. Such an error operation may become larger by increased integration and lower power consumption of semiconductor memory devices.
Thus, if leakage current in a read operation can be compensated, integration of semiconductor memory devices can be increased and error operations caused by leakage current can be prevented.