The present invention relates in general to integrated circuit device structures and their fabrication. More particularly, the present invention relates to transistor structures with reduced parasitic capacitance and improved junction sharpness.
In an integrated circuit, transistors such as metal oxide semiconductor field effect transistors (MOSFETs) have a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode.
Non-planar MOSFET architectures, such as nanosheet (or nanowire) transistors, can provide increased device density and increased performance over planar transistors. Nanosheet transistors, in contrast to conventional planar FETs, include a gate stack that wraps around the full perimeter of multiple nanosheet channel regions for improved control of channel current flow. Nanosheet transistors enable fuller depletion in the nanosheet channel regions and reduce short-channel effects.