1. Field of the Invention
This invention relates to electronic systems. Specifically, the present invention relates to electronic circuits.
2. Description of the Related Art
Modern electronic systems are implemented with integrated circuits. The integrated circuits include digital logic that is implemented with analog devices, such as Field Effect Transistors (FET(s)). A conventional integrated circuit may have millions of analog devices included in one circuit.
Integrated circuits are often combined into electronic systems, such as chips or microprocessors. Chips are combined in electrical boards, which form the building blocks of many large-scale electronic systems. For example, a common computer system may include a motherboard that includes a number of microprocessors or chips, such as a central processing unit (i.e., CPU).
In order to integrate a large-scale electronic system, design requirements are established for each component so that the components work together. For example, specific types of FETs may be specified or specific voltage requirements may be established. For example, in many large-scale electronic systems, the microprocessor technology (i.e., integrated circuit) is implemented with 2.5-volt FETs. The 2.5-volt FETs offer a high degree of performance. However, technology on the board may be implemented with higher-voltage devices. For example, 3.3-volt technology is now common on boards.
In order for a large-scale electronic system to operate, signals are transferred between the integrated circuit (i.e., chip) and the board. For performance reasons, it is often desirable to implement the integrated circuit with low voltage components. As a result, the board would be implemented with high-voltage components and the chip would be implemented with low-voltage components. An interface is implemented between the chip and the board to transfer signals between the two. The interface is referred to as a pad. In the foregoing configuration, a pad would be necessary because applying high voltages (i.e., 3.3 volts) across low-voltage devices (i.e., 2.5-volt FETs) would result in the destruction of the low-voltage devices.
An example of an interface circuit, which performs level shifting, is presented in FIG. 1. In FIG. 1, a level shifter is presented as 100. The level shifter is used to shift the voltage levels between the devices found in the chip and the devices found in the board. In FIG. 1, an input voltage (e.g., Vin) is shown as 102. Input voltage Vin 102 is the voltage coming from the core side (i.e., the chip) of the architecture. The input voltage Vin 102 is applied to nFET 104. The input voltage Vin 102 is inverted using inverter 106. The inverted input voltage is applied to nFET 108. Both nFETs 104 and 108 are connected to ground 110. Two pFETs 116 and 118 are also shown. The node between nFET 104 and pFET 116 is shown as 112. The node between nFET 108 and pFET 118 is shown as 113. An output voltage (e.g., Vout) is shown as 114. A supply voltage is shown as 120.
During operation, the input voltage Vin 102 is applied to nFET 104 and the complement the input voltage Vin 102 is applied to nFET 108. As a result, when a high signal (i.e., logical 1) is placed on nFET 104, a low signal (i.e., logical 0) is placed on nFET 108. When a high signal is placed on nFET 104, nFET 104 conducts and pulls the node 112 on the drain of nFET 104 to ground 110. As a result, the pFET 118 sees ground 110 on its input and attempts to pull the node 113, located between nFET 108 and pFET 118, high. The node 113 and the output voltage Vout 114 carry the same signal or state. In addition, when there is a high signal on the gate of nFET 104, there is a low signal on the gate of nFET 108. The low signal on the gate of nFET 108 turns off nFET 108. Therefore, a low-impedance path is established between output voltage Vout 114 and the supply voltage 120. As a result, a high signal is on output voltage Vout 114 and a low signal is on the node 112, which is located between nFET 104 and pFET 116. In addition, as output voltage Vout 114 is pulled high, the gate on pFET 116 sees a high voltage that turns the pFET 116 off.
On the left-hand side of the level shifter 100, there is a FET that is on all of the time (i.e., nFET 104) and a FET that is off all of the time (i.e., pFET 116). On the right-hand side of the level shifter 100, there is also a FET that is on all of the time and a FET that is off all of the time. As a result, in the level shifter 100, a DC current does not appear between the supply voltage 120 and ground 110. One of the transistors in the pair on either side is always off and that forces output voltage Vout 114 to go to one of the rails (e.g., supply voltage 120 or ground 110).
Ultimately, in the conventional level shifter 100, there is a differential output or a complementary output that shifts the input voltage Vin 102, which is applied to the gates of nFETs 104 and 108; to a high-voltage signal that is presented at the node 113 and at the output voltage Vout 114.
It should be noted that in the design of the level shifter 100, the FETs are 2.5-volt FETs. As discussed previously, when input voltage Vin 102 is high, nFET 108 sees a low-voltage signal as an input. nFET 108 sees ground 110 as its input so output voltage Vout 114 (and node 113) is pulled high. When output voltage Vout 114 is pulled high, pFET 118 provides a low-impedance path to the supply voltage 120 (i.e., the high rail), which is 3.3 volts. As a result, output voltage Vout 114 is also at 3.3 volts. If output voltage Vout 114 is at 3.3 volts, then nFET 108 sees 3.3 volts from its source to its drain. Applying 3.3 volts from the source to the drain of nFET 108, which is a 2.5-volt FET, will cause breakdown in nFET 108.
In addition, since output voltage Vout 114 is 3.3 volts, pFET 116 sees 3.3 volts on its gate. If output voltage Vout 114 is high, node 112 is low; meaning that node 112 is at ground 110. Since output voltage Vout 114 is applied to pFET 116, you get a potential of 3.3 volts across pFET 116 from its gate (i.e., 3.3 volts) to its drain (i.e., ground). Since pFET 116 is a 2.5-volt FET, pFET 116 will experience breakdown.
Thus, there is a need in the art for a method and apparatus for transferring signals from a low-voltage environment to a high-voltage environment. There is a need in the art for a method of interfacing with a high-supply voltage when using low-voltage FETs. There is a need for a circuit design that uses low-voltage FETs, which are configured so that the low-voltage FETs do not breakdown when they are exposed to a high-voltage supply.
A method and apparatus are presented that configure low-voltage devices so that they do not experience breakdown when exposed to a high-supply voltage. In one embodiment of the present invention, low-voltage FETs are configured to produce an output. The low-voltage FETs receive a high-supply voltage. The low-voltage FETs are configured so that they will not experience breakdown when exposed to the high-supply voltage.
In one embodiment of the present invention, the method and apparatus are implemented as an interface between a high-voltage environment and a low-voltage environment. The high-voltage environment may be an electronic system, such as a motherboard, and the low-voltage supply may be an integrated circuit located on a chip, which is a component of the motherboard.
In the method and apparatus of the present invention, the low-voltage devices may be 2.5-volt FETs that are used to interface with a high-voltage supply of 3.3 volts. The 2.5-volt FETs are configured so that the FETs do not experience breakdown when they are exposed to the 3.3-volt supply. Further, the FETs are used to shift the voltage level of signals that are exiting the chip (i.e., microprocessor) and entering the high-voltage environment. Therefore, in one embodiment of the present invention, the FETs are configured in a circuit that shifts signals from 2.5 volts up to 3.3 volts for interfacing with the high-voltage environment.
In one embodiment of the present invention, a system comprises a low-voltage driver generating low-voltage signals; a high_bias circuit generating high_bias signals; a first clipping stage coupled to the low-voltage driver and coupled to the high_bias circuit, the first clipping stage generating clipped low-voltage signals in response to the low-voltage signals generated by the low-voltage driver and in response to the high_bias signals generated by the high_bias circuit; a low_bias circuit generating low_bias signals; a high-voltage driver generating high-voltage signals; a second clipping stage coupled to the high-voltage driver and coupled to the low_bias circuit, the second clipping stage generating clipped high-voltage signals in response to the high-voltage signals generated by the high-voltage driver and in response to the low_bias signals generated by the low_bias circuit; an accelerator generating acceleration signals; and an output coupled to the first clipping stage, coupled to the second clipping stage, and coupled to the accelerator, the output generating output signals in response to the clipped high-voltage signals second clipping stage, in response to the clipped low-voltage signals generated by the first clipping stage, and in response to the acceleration signals.
In another embodiment of the present invention, a level system comprises a low-voltage driver generating low-voltage signals; a first clipping stage coupled to the low-voltage driver and generating clipped low-voltage signals in response to the low-voltage signals generated by the low-voltage driver; a high-voltage driver generating high-voltage signals; a second clipping stage coupled to the high-voltage driver and generating clipped high-voltage signals in response to the high-voltage signals generated by the high-voltage driver; an accelerator generating acceleration signals; and an output coupled to the first clipping stage, coupled to the second clipping stage and coupled to the accelerator, the output generating output signals in response to the clipped high-voltage signals generated by the second clipping stage, in response to the clipped low-voltage signals generated by the first clipping stage and in response to the acceleration signals generated by the accelerator.
A system comprises a low-voltage driver generating low-voltage signals; a high-voltage driver generating high-voltage signals; a bias circuit generating bias signals; an accelerator generating acceleration signals; and a clipping stage coupled to the low-voltage driver, coupled to the high-voltage driver, coupled to the bias circuit and coupled to the accelerator, the clipping stage generating output signals in response to the high-voltage signals generated by the high-voltage driver, in response to the low-voltage signals generated by the low-voltage driver, in response to the bias signals generated by the bias circuit and in response to the acceleration signals generated by the acceleration accelerator.