1. Field of the Invention
This invention relates to Hardware Design Language (HDL) tools for the design of circuit components and for determining the performance and logical correctness of the designed circuit components. Hardware Design Languages and HDL tools transform high-level designs (e.g., functional specifications or functional-level logic such as Boolean expressions, truth tables, or standard macro logic) into its hardware implementation, and model the target system to predict its performance analyze its behavior.
2. Background Art
The state-of-the-art in hardware design is to utilize a Hardware Description Language (HDL), such as VHDL (Very-High-Speed Integrated Circuits HDL) or Verilog (Verify Logic) HDL. The HDL design file consists of a hierarchical structure of modules using a set of predefined library constructs and routines. In order to compile the design, preprocessing of the HDL source file is required. Preprocessing includes creating a bottom-up list of related file names. This list is needed by the compiler so that the required parts (modules and libraries) can be located and fetched. This shows a need for a method to create this list, also known as the “makefile”, automatically and with minimal user intervention.
Manual creation of this “makefile” list requires that a designer visually inspect each source file and create the needed hierarchy. This works for small designs; however, it becomes a tedious task very quickly especially when multiple designers are involved and over an extended period of time.
Automatic creation of the “makefile” is a parsing operation that is done starting at the top-level (highest in hierarchy) HDL source code wherein the needed lower-level modules are identified by detecting language-specific keywords that instantiate those entities, i.e.represent those entities as an abstract concept by a concrete instance. Although this will generate a top-down list of required module and routine names, the actual file names stored on disk are usually different, especially when a file contains multiple modules. Therefore another search is done inside all HDL source files of a defined path to look for the module definitions, and again, using language-specific keywords. The “Makefile” is thus created in a top-down fashion as each hierarchy level is done. The process has to go through the lower level files recursively repeating that process until all needed definitions are located.
Automatic creation of the “Makefile” requires extra programming, knowledge of the file name containing the top-level module, and is time consuming with large designs due to the special HDL source code parsing required. Additionally, automatic creation of the “Makefile” requires a special script for each hardware design language.
Semi Automatic creation of the “Makefile” is similar to Automatic creation of the “Makefile” but instead of searching through files for module definitions, the file base names are required to be the same as the module name.
Semi Automatic creation of the “Makefile” has some drawbacks, including imposing module and file names, that is, it requires the designer to match module and file names although language naming rules are usually different than those of the operating system. Additionally, each source file is restricted to either one module definition, or to be self-contained in the module hierarchy. Additionally, semi automatic creation of the “Makefile” does not work on non-conforming designs (such as legacy or external source code) unless the files are modified.
A further feature of hardware description language (HDL), such as VHDL or Verilog is the need for and capability of pre-compilation debugging of the source code file. To help in debugging, design automation vendors provide HDL source browsers that perform a variety of debugging functionalities, such as:    1—Simulation value annotation: Signal values obtained from a simulation database are annotated back to the HDL source.    2—Syntax highlight: Different token types (keywords, comments, identifiers, etc) are highlighted in different colors.    3—Semantic navigation: Semantic navigation involves tracing through the code from a signal usage jump to its declaration or its type declaration, list all sources and sinks of a signal, from a VHDL entity jump to its architecture, hierarchy navigation, etc.
One of the most important capabilities of semantic navigation in an HDL language is the hierarchy navigation. From a top level module, a lower level module is instantiated along with the connections to its ports (inputs, outputs, inputs). Current Vendor source browsers require the HDL to be compiled before getting displayed, resulting in performance and usability problems. These problems include first, all of the HDL code needs to be compiled although the user is only interested in viewing few modules, and second, in a large project it is not always possible to have access to all the VHDL files.
Thus, a need exists for s pre-compilation solution for alleviating the above two limitations by compiling the instantiated modules on-demand.
Another issue is with overloading operators and functions. Both VHDL and Verilog support overloading operators. The built in operators can be extended to accept operands of any types. For example the user can overload the “+” operator to add a record to an array and return an integer. Although this is a powerful feature, it makes browsing the HDL very complicated especially for nested expressions. Both languages also support overloading user defined functions, in which the same function name is used with different operand types. Current Vendor source browsers help the user in browsing the HDL by displaying the list of all operators and functions that are visible at the point of the operator or function usage. It leaves to the user the task of matching the operator usage to the list of operators, which exponentially increases in complexity with the number of operators and the nested level of the expressions. This illustrates a further need for a technique that allows browsing HDL operators and functions in a very simple and helpful way.