An embodiment of the present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a silicon-on-insulator (SOI) wafer for use in microelectromechanical systems (MEMS).
Semiconductor wafer fabrication generally refers to the process of making integrated circuits on silicon wafers. A typical semiconductor wafer is generally circular in plan view and has a diameter on the order of 25-300 millimeters (mm). Individual electronic circuits or devices are formed across at least one surface of the wafer and then the wafer is typically cut (sawed or diced) into a plurality of individual “dies” for packaging into individual integrated circuits (ICs).
SOI semiconductors, dielectric isolation (DI) semiconductors, and bonded wafer semiconductor devices are generally known in the art. For example, basic known processes to bond semiconductor wafers include forming a layer of silicon dioxide (which may be a buried oxide layer) on one silicon wafer, sometimes referred to as the “handle wafer,” placing a second silicon wafer (device layer) on the silicon dioxide, and annealing (i.e., generally heating to and holding at a suitable temperature and then cooling at a suitable rate) the stacked wafers to form a bonded wafer semiconductor device having a buried oxide layer. Other methods of forming SOI semiconductor wafers are also known.
The development of MEMS technology has provided the ability to combine microelectronic circuits and mechanical parts, such as cantilevers, membranes, holes, and the like, onto a single chip. MEMS chips may be developed to provide, for example, inertia sensors (e.g., for use in an accelerometer), radio frequency (RF) switches, and pressure sensors, and may also be used in optics applications, such as for digital light processing (DLP) televisions.
The MEMS chips are often manufactured using SOI wafers, wherein at least a portion of the buried oxide layer is etched out as a sacrificial layer. In the example of an inertia sensor, a proof mass is formed in the device layer and is suspended from the device layer by one or more membranes. Following the removal of the buried oxide layer, the proof mass is free to move in the resulting cavity.
Unfortunately, difficulties may arise to the extent that the proof mass or the membranes may contact the top surface of the handle wafer. Typically, the bottom surface of the device layer and the top layer of the handle wafer are highly polished. As a result, the two surfaces are prone to sticking to one another by way of the electrostatic or van der Waals forces. This phenomenon is known as “stiction.”
It is desirable to manufacture a SOI wafer, and more specifically a MEMS device, such that the SOI substrate stiction may be eliminated or greatly reduced between the handle wafer and device layer surfaces.