1. Technical Field
The embodiments herein generally relate to semiconductor processing and characterization, and more specifically, to a high throughput combinatorial characterization tool for combinatorial semiconductor substrates.
2. Description of the Related Art
The ability to process uniformly across a monolithic substrate and/or across a series of monolithic substrates is advantageous for manufacturing efficiency and cost effectiveness, as well as repeatability and control. However, uniform processing across an entire substrate can be disadvantageous when optimizing, qualifying or investigating new materials, new processes, and/or new process sequence integration schemes, since the entire substrate is nominally made the same using the same materials, processes and process sequence integration schemes. Each processed substrate generally represents, in essence, only one possible variation per substrate. Thus, the full wafer uniform processing under conventional processing techniques results in fewer data points per substrate, longer times to accumulate a wide variety of data, and higher costs associated with obtaining such data.
For example, the lifetime and reliability characteristics are very important specifications for any new or existing product. Lifetime and reliability tests are usually tested with accelerated conditions such as high temperature, voltage, longer time, etc. Voltage Breakdown (VBD) and Time Dependent Dielectric Breakdown (TDDB) are the two main reliability tests for back end of line (BEOL) applications. However, as a current industrial standard, VBD and TDDB are performed at the package level or wafer level with at least four metal pattern layers. To evaluate a process at a first metal (M1) layer, one wafer with M1 exposed is processed by a single process condition and then passivated with a cap layer such as SiN. Then, several subsequent layers are deposited and patterned. Afterwards, the VBD and TDDB tests are performed. Moreover, using conventional technology, a wafer can generally only be used to evaluate a single process condition. This unit process and test workflow used in current industry is complicated, time consuming, and not cost efficient.
Moreover, wafer level TDDB, especially at the M1 layer is generally not well understood and not typically used commercially in the industry. Currently, each process is performed one wafer at M1 or higher layer. Then, the wafer is passivated and at least four more layers are deposited, or the wafer even is packaged, and then reliability testing is performed. To know the result of each condition, one wafer with many follow-up steps is required, which under current technology is very complicated as well as cost inefficient. In particular, semiconductor companies conduct research and development (R&D) on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in high R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner.