The present invention relates to error recovery in high availability processors, and more specifically, exemplary embodiments of the present invention relate to error recovery systems and methods of instruction processing for high availability processors with both recoverable and non-recoverable modes of operation.
High availability computer systems necessitate both detection of hardware faults and methods to recover from the detected faults and prevent any incorrect results. In a conventional microprocessor supporting fault recovery, most fault recovery operations are hardware-specific and integrated within the microprocessor itself. Therefore, software executed on the microprocessor may run uninterrupted while lacking disruption or signaling resulting from transient hardware faults within the microprocessor hardware.
These conventional recovery mechanisms implemented in microprocessors usually discard instructions that are processed, or potentially processed, through faulty circuits, while keeping results from any chronologically older instructions that are processed prior to detecting a fault. In order to differentiate as to whether or not results of instructions are potentially faulty, results need to be buffered and/or held until associated results are checked against any potential faulty conditions before these instructions (and their results) are committed as non-faulty. If a faulty condition is detected, these potentially faulty results will need to be rolled-back, and any affected instruction will be discarded and later reissued.
In order to achieve the capabilities described above, extra pipeline resources are necessary to buffer instruction results until no faults are detected. In addition, because instructions need to be retired from a good architectural state, appropriate states (architectural and sometimes non-architectural) need to be maintained (e.g., through check-points). Such buffering, maintenance, and check-pointing increases overall circuitry required or reduces the net available resources available for instruction processing in conventional microprocessors supporting fault-recovery.