1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, particularly devices having a nitrided silicon substrate manufactured by nitrogen ion implantation and having high dielectric constant insulators.
2. Description of Related Art
As semiconductor devices are made smaller to accommodate desired increases in device density, it is desirable to decrease the dimensions of the insulating elements in the devices. Particularly, the minimum dimensions of metal on silicon field effect transistors (xe2x80x9cMOSFETSxe2x80x9d) in semiconductors can be limited by the requirements for effective insulation, or xe2x80x9cgate insulationxe2x80x9d between the silicon substrate and gates. For example, in non-volatile memory devices, the gate insulator prevents charge leakage from occurring between the gate and the substrate. Typically, an insulator such as SiO2 is used to provide the gate, and is called xe2x80x9cgate oxide.xe2x80x9d However, the minimum thickness of the insulating layers can be determined in part by the dielectric constant of the insulating material. Therefore, as semiconductor device density increases and device dimensions become smaller, it becomes increasingly useful to provide insulating materials that have high insulating capability. Recently, materials having high insulating capability and high capacitance have become available, and have been used to provide alternatives to SiO2 as gate insulators.
A. Semiconductor Device Manufacture
The manufacture of semiconductor devices is typically carried out by creating areas of isolation or insulation on a semiconductor substrate, such as silicon, and then forming active devices between the areas of electrical isolation. The semiconductor substrate can typically be a p-doped substrate, although one can alternatively use an n-doped substrate. Insolation areas can be manufactured, by way of example, using Shallow Trench Isolation (xe2x80x9cSTIxe2x80x9d), whereby areas of electrical isolation are formed by inscribing trenches in the silicon substrate and then filling the trenches with an insulating material, including, by way of example only, a silicon oxide. The prior art methods of manufacturing devices using STI are depicted in FIGS. 1-3. FIG. 1 depicts a semiconductor wafer 100 comprised of a silicon substrate 104 and having a layer of pad oxide (xe2x80x9cPoxxe2x80x9d) 108 formed thereon. The pad oxide can be formed by way of example, by dry oxidation of silicon in the presence of oxygen (O2) at a temperature of about 950xc2x0 C. for about 30 minutes. FIG. 2 depicts the semiconductor wafer shown in FIG. 1, but after the layer of pad oxide 108 is formed, a photoresist mask (not shown) is applied to the substrate and a layer of nitride 112 is deposited over the wafer, leaving those areas uncovered where shallow trenches are to be formed. FIG. 3 depicts the same semiconductor wafer as in FIG. 1 and 2, but after a shallow trench 116 has been formed in the substrate between the areas having the nitride layers 112. The nitride layer 112 can act as an etch-stop layer to prevent the removal of substrate 104 during the formation of shallow trenches, thus providing for localized areas of electrical isolation. Subsequently, the shallow trenches are filled with a dielectric material such as silicon dioxide, and thereafter the nitride layer 112 is removed, thereby exposing the layer of pad oxide 108.
The next step in semiconductor device manufacture is typically the deposition of a layer of insulating material or gate insulator on the pad oxide. Gate insulating layers are typically made of SiO2 and after formation of a gate insulator, the manufacture of semiconductor devices involves the deposition of a conductive material on top of the insulating material, thereby forming a xe2x80x9cgatexe2x80x9d structure which forms part of the active device elements. Because the dielectric constant of SiO2 is about 3.9, and other materials can have dielectric constants higher than that of SiO2, it can be desirable to incorporate other, high-dielectric constant materials into gate insulators.
B. High-Dielectric Constant Insulators
One indicator of a material""s ability to act as an electrical insulator is the dielectric constant (xe2x80x9cKxe2x80x9d). The dielectric constant is a measure of the ability of an insulator to prevent the discharge of electric current between conductive elements through the insulator. Better insulators have higher dielectric constants. The dielectric constant is quantified by comparing the insulating ability of an insulating material to the insulating ability of air, which has a dielectric constant defined to be 1.0. The commonly used dielectric material, silicon dioxide (SiO2) has a dielectric constant of about 3.9. High dielectric constant materials are herein defined to have dielectric constants of greater than 3.9. In contrast, insulators having dielectric constants of less than 3.9 are herein considered to be low dielectric constant insulators.
Examples of high dielectric constant materials include tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), silicon nitride (Si3N4), zirconium dioxide (ZrO2), titanium dioxide (TiO2), barium-strontium-titanium oxide (xe2x80x9cBSTxe2x80x9d), and lead-zirconium-titanium oxide (xe2x80x9cPZTxe2x80x9d), although other materials can also be used. Tantalum pentoxide has a dielectric constant of about 30, and therefore, is a useful material because it can be made into an insulating layer having high capacitance. Other materials, having dielectric constants up to about 200 are known in the art, and can be desirably used as gate insulators.
High-dielectric constant materials are desired for use as insulators because of the possibility that the increased dielectric constant and capacitance can permit the use of thinner layers of insulating materials, permitting device dimensions to be smaller than previously possible using more conventional insulators. Therefore, to take advantage of high-dielectric constant materials, instead of depositing SiO2 as the gate oxide, more recent manufacturing methods have incorporated high dielectric constant materials. Unfortunately, conventional manufacturing methods involving high dielectric constant insulators can suffer from the problem of interfacial oxide formation between the silicon substrate and the high dielectric material.
C. Sacrificial Oxide and Interfacial Oxide Layers
Silicon wafers, as depicted in FIG. 1, typically can have a thin layer of oxide 108 on the surface. This layer of oxide can be termed xe2x80x9csacrificial oxidexe2x80x9d or xe2x80x9cpad oxide.xe2x80x9d As depicted in FIG. 4, with the deposition of the high dielectric constant material 132, a layer of silicon oxide 110 (xe2x80x9cinterfacial oxidexe2x80x9d) can form under the high dielectric constant material. The interfacial oxide can have the structural formula SiXOy, where x and y are not necessarily integers. Although the interfacial oxide can be thin, it can provide an oxide equivalent thickness of about 10 xc3x85. Oxide equivalent thickness (xe2x80x9cOxeqxe2x80x9d) of an insulating layer X, is defined as the thickness of a layer of SiO2 sufficient to provide the same accumulation capacitance as the insulating layer X. Oxeq can be calculated from the thickness of the insulating layer, T, and dielectric constant of the insulator, K, according to the formula:       Ox    eq    =                    T        ⨯        3.9            K        .  
However, like conventional gate oxide, interfacial oxide has a dielectric constant of about 3.9. Thus, the conductive layer of the gate structure is separated from the silicon substrate by the layer of high dielectric constant material and the interfacial oxide which underlies the high dielectric constant layer.
Nevertheless, as device dimensions are reduced, and as the thickness of the high dielectric constant layer is reduced, the capacitance of the insulator should remain at a high, desirable level. Unfortunately, the formation of a layer of interfacial oxide during deposition of the high-dielectric constant material can result in the formation of a mixed insulating layer. This mixed layer can have a capacitance less than that of the high dielectric constant material alone. This is because the capacitance of the total insulating layer can be determined by the capacitances of both the high dielectric constant material and of the oxide. The total capacitance (xe2x80x9cCtotalxe2x80x9d) of such a mixed layer of high dielectric constant (xe2x80x9cHi-Kxe2x80x9d) material and an oxide such as SiO2 can be related to each other as follows:             1              C        total              =                  1                  C          oxide                    +              1                  C                      Hi            -            K                                ,
wherein Coxide is the capacitance of the oxide layer and CHi-K is the capacitance of the high-dielectric constant material. For mixed insulators as depicted in FIG. 4, comprising both high dielectric constant material 132 and interfacial oxide 110, the presence of SiO2 effectively decreases the gate oxide equivalent thickness of the combined insulating layer. The interfacial oxide can offset the gate oxide equivalent thickness of the high dielectric constant material, and thereby decreasing the capacitance of the mixed insulating layer compared to the same thickness of high dielectric constant material alone. Using conventional manufacturing methods the promise of thin, high dielectric constant layers has been difficult to realize. Therefore, to provide thin insulating layers comprising high dielectric constant materials, it is desirable to be able to deposit the high dielectric constant materials while limiting the growth of interfacial layers of silicon oxides.
D. Dopant Diffusion
Device reliability can be degraded if dopants such as boron penetrate into the gate oxide regions. For example, such penetration can occur if a p-type dopant is introduced into a conductive polysilicon layer over a gate oxide layer. Gate oxide is relatively permeable to boron atoms, and thus, with the thermal cycling that occurs during subsequent semiconductor manufacturing steps, there can be opportunity for dopant atoms to diffuse from the doped polysilicon regions and into the gate oxide regions. Diffusion of boron atoms can degrade the insulating properties of the gate oxide and prevent adequate charge from being stored in the gate, and can result in leakage currents from the gate to the substrate. Moreover, as device dimensions are reduced to meet the demands of smaller, faster semiconductor devices, the problems associated with dopant diffusion can become greater. Therefore, it can be desirable to limit the diffusion of boron and/or other dopant atoms from polysilicon gates into the underlying gate oxide regions.
Another object of this invention is the manufacture of semiconductor devices comprising insulators having increased capacitance.
Another object of this invention is the manufacture of semiconductor devices having decreased gate insulator thickness.
This invention addresses the above problems caused by interfacial oxide by providing a nitrided silicon substrate under the pad or sacrificial oxide layer. This nitrided silicon substrate can be provided by the implantation of nitrogen ions through the pad oxide or sacrificial oxide layer and into the silicon layer. By providing such a nitrided silicon substrate, subsequent exposure of the semiconductor wafer to oxidating conditions suitable for deposition of high dielectric constant insulators can result in reduced growth of interfacial oxide compared to growth of insulating layers without the nitrided silicon substrate. The sacrificial oxide layer can be subsequently etch off, revealing the underlying nitrided silicon substrate, thereby permitting the deposition of high dielectric constant material directly on the nitrided silicon substrate with little intervening interfacial oxide.
Thus, one aspect of this invention is the implantation of nitrogen ions through a sacrificial oxide layer to form an implanted nitride, and subsequent removal of the sacrificial oxide layer.
An additional aspect of this invention is the deposition of a layer of high dielectric constant material on an exposed nitrided silicon substrate, thereby resulting in an insulating layer having less interfacial oxide underneath.
A further aspect of this invention is the manufacture of semiconductor devices having high dielectric constant insulating layers with reduced interfacial oxide.
Another aspect of the invention is the manufacture of semiconductor devices having different types of insulating layers in different regions of the semiconductor wafer.