Synchronous communication between endpoint devices such as data or voice transport using an International Telecommunications Union (ITU) Synchronous Digital Hierarchy (SDH) or Plesiochronous Digital Hierarchy (PDH) transmission system over an asynchronous packet network such as an Ethernet Transport and Access Network (EATN) or Metropolitan Ethernet Network (MEN) often requires that the devices have some mechanism for achieving frequency synchronization. One technique that allows transport of SDH or PDH links over a packet network is the Circuit Emulation Service (CES), in which bits from one or more consecutive TDM frames are encapsulated in an Ethernet packet. See, for example, MEF8, Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet Networks, Metro Ethernet Forum, October 2004, and IETF RFC 4553, A. Vainshtein and Y. J. Stein, “Structure-agnostic time division multiplexing (TDM) over packet (SATOP),” June 2006.
Similar synchronization requirements exist for wireless backhaul networks implemented over an EATN or MEN. In such wireless backhaul networks, radio frequencies must be synchronized to certain, often rigorous, precision levels and the synchronization requirement exists regardless of whether the endpoint devices are native packet-based devices or circuit-based devices.
Certain known frequency synchronization techniques utilize clock recovery based on differential timestamps. See, for example, R. C. Lau and P. E. Fleischer, “Synchronous techniques for timing recovery in BISDN,” IEEE Transactions on Communications, vol. 43, no. 234, pp. 1810-1818, February-March-April 1995. Such differential clock recovery techniques may make use of a common reference clock if available. The common reference clock is typically a SONET/SDH clock (e.g., in ATM networks) or a clock sourced from Building Integrated Timing Supply (BITS) or Global Positioning System (GPS) timing systems. Although originally designed for ATM networks, differential clock recovery techniques apply to any packet network, such as Ethernet, as long as the common reference is available. The recent development of synchronous Ethernet will allow native Ethernet deployments to have access to a common reference clock.
The main advantage of differential clock recovery is its insensitivity to packet delay variation (PDV) within the packet network. However, not all installations have access to BITS or GPS timing systems, and deploying synchronous Ethernet generally requires a substantial upgrade of the packet network.
Adaptive clock recovery techniques are also known. Such techniques, often implemented together with the CES service, use packet arrivals as clock indications and thus do not require the above-noted common reference clock. However, adaptive clock recovery techniques are very sensitive to PDV. PDV can be reduced if CES packets are given strict priority at queuing points in the network using Quality of Service (QoS) assignments, but as the number of emulated circuits grows, CES flows start competing against each other, defeating the purpose of QoS. Also, the processing operations needed to handle multiple CES flows can consume excessive amounts of computational and memory resources on the endpoint devices. Adaptive clocking techniques are therefore not readily scalable, and fail to provide adequate performance in many situations.