Such an analog to digital converter is known in the art, and is e.g. described in "Session 1:Data converters -WAM 1.2:a CMOS 40 MHz 8b 105 mW Two-Step ADC" of the Proceedings of ISCC 89, Feb. 15, 1989, pp. 14-18. Therein a two stage analog to digital converter for converting an analog input voltage into a digital output voltage is described. The two stages are interlaced in such a way that they form a single network of 256 resistors of equal value. The subdivided voltages of the first or coarse stage are taken from the resistor network every sixteenth resistor. This gives 15 voltages which are derived from a reference voltage and compared with the analog voltage by coarse comparators. The result thereof indicates the level of the analog voltage and determines which switches of the switching means are to be closed as well as which sixteen cascaded resistors are used as resistors of the second or fine stage to supply the subdivided voltages of this fine stage.
A disadvantage of this known converter is that the switches connecting the resistors to the comparators of the fine stage are operated at a voltage depending on the level of the analog input voltage since the choice of which cascaded resistors constitute the fine stage is dependent upon the analog input voltage. As a consequence and because the switches have a series resistance depending on the voltage they are operated at, the resistance introduced in the fine stage by the switches depends on the analog voltage, and thereby introduces linearity errors.