1. Field of the Invention
The present invention relates generally to electronic circuits, and in particular, to charge pump circuits, which operate at relatively low power supply voltages and produce output signals with relatively low static phase offset.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A charge pump is a circuit that delivers a certain amount of current for a certain amount of time. More specifically, a charge pump is a circuit that receives a pair of input pulses and connects either a constant current source or a constant current sink to an output line depending on which input pulse is active. The output connection generally lasts for the duration of the input pulse.
One use for a charge pump is in a phase-lock loop circuit. Phase-locked loops (PLLs) are routinely used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. In some cases, PLLs may be used in the input/output (I/O) interfaces of digital integrated circuits to hide clock distribution delays and to improve overall system timing. In general, a PLL may be used to generate one or more clocking signals that are in phase alignment with a reference clock signal. More specifically, a PLL is a closed-loop device that uses a Phase Frequency Detector (PFD), a charge pump (CP), a low pass filter, and a voltage-controlled oscillator (VCO) to obtain accurate phase alignment between the generated clocking signal and the reference clock signal. The PFD detects the difference between the reference clock signal and a clock signal (referred to below as a feedback clock) generated by the VCO and fed back to the PFD. Output signals from the PFD activate the charge pump for an amount of time substantially equal to the difference between corresponding edges of the reference and feedback clock signals. The PLL may then use the output current generated by the charge pump as an error signal, which is used to correct the phase offset between the reference signal and the VCO generated clocking signal. In this manner, the PLL may be ideally configured for generating one or more clocking signals, which demonstrate a relatively low (and preferably zero) static phase offset from the reference signal at the lock point.
Conventional charge pump circuits are typically driven with inputs received directly from the phase frequency detector (PFD). As such, the inputs generally exhibit rail-to-rail voltage swings (e.g., from about 0 V to about 1.2 V in some processes). As used herein, a signal with a “rail-to-rail voltage swing” has a magnitude equal to the difference between the power supply voltage (e.g., VDD) and a ground potential (e.g., VSS). As such, the signal magnitude may fluctuate with variations in the power supply voltage. An exemplary conventional charge pump solution is shown in FIGS. 1A and 1B. This conventional charge pump solution generally includes two identically-formed differential current-steering circuits 100, 150, one for supplying a positive control voltage (VCOUP), and one for supplying a negative control voltage (VCODN) to the VCO. The current-steering circuits of FIGS. 1A and 1B each include an n-channel metal oxide semiconductor (NMOS) transistor current source (IN), a p-channel metal oxide semiconductor (PMOS) transistor current source (IP), two NMOS switching transistors (N1, N2) and two PMOS switching transistors (P1, P2). The switching transistors (N1, N2, P1, P2) are driven directly from the PFD; they deliver current to the VCOUP and VCODN nodes depending on the state of the full-swing input signals (pd_low, pd_high, pu_high, pu_low) received from the PFD circuit.
Disadvantages of the conventional charge pump solution of FIGS. 1A and 1B become evident when the charge pump operates at relatively low power supply voltages (e.g., less than about 1.2V). At low power supply voltages, the full rail input voltage swing from the PFD forces the switching transistors into the triode operating region when the switching transistors are in the “on” state. This changes the magnitude of the gate-to-drain capacitance (Cgd, sometimes referred to as the Miller Capacitance) and causes large Miller Capacitance mismatch currents to be produced at the VCOUP and VCODN nodes. As described in more detail below, the mismatched currents may cause the PLL to lock with a significant static phase offset between the reference and feedback clock signals.
A capacitance curve for one of the PMOS switching transistors in the conventional charge pump circuit is shown in FIG. 2. As seen in FIG. 2, the Miller capacitance (Cgd) varies between approximately 0.62 femto-Farards (fF, or 10−15 Farads) and 1.69 fF from the “off” state to the “on” state of the PMOS switching transistors. Similar results may be obtained from one of the NMOS switching transistors in the charge pump circuit. The large Cgd mismatch between “on” and “off” states results in large (and therefore, undesirable) output current mismatches at the switching point of the PMOS (and NMOS) switching transistors. This forces the phase-lock loop (PLL) to generate a charge in the opposite direction to cancel out the mismatched charges during lock. The result is that the PLL locks with a relatively large static phase offset between the reference and feedback clock signals. A plot of charge vs. phase, simulated at a typical process corner and maximum VCO control voltage for the conventional technology, is shown in FIG. 3. This plot indicates a static phase offset of about 90 picoseconds (ps) for the conventional charge pump shown in FIGS. 1A and 1B.
In an ideal situation, a charge pump circuit would operate with zero Miller capacitances; however, this is not possible with conventional devices. Therefore, a need exists for a means to minimize these capacitances, and more importantly, to accurately match these capacitances between all switching transistors. In other words, it would be desirable to have a charge pump circuit that does not suffer from Miller Capacitance mismatches between “on” and “off” states of its switching transistors. It would be further desirable to have a charge pump circuit with switching transistors that demonstrate a substantially low and constant Miller Capacitance when operated at relatively low power supply voltages (e.g., less than about 1.2 V).