This invention relates to methods of forming thinner silicon structures with precisely defined thicknesses in a thin silicon substrate, and more particularly to subtractive methods of precisely thinning selected portions of a silicon structure to form recesses with various precise depths in the surface of the thin silicon substrate into which recesses various devices including MOSFETS, resistors, capacitors and diodes can be formed.
This invention provides a method for forming a structure with a precision recessed gate structure for an Ultra Thin (UT) Silicon-On-Insulator (SOI) device comprising a thin layer of doped silicon formed on the surface of a Buried OXide (BOX) layer. The method can also be used for precision thinning of selected regions of the top silicon layer on a SOI (SOI) wafer. This can be used to provide an optimal silicon thickness for each type of electronic device which is to be formed on the same wafer. For example, MOSFETS require thinner silicon than resistors or capacitors or diodes in order to achieve the best electrical characteristics.
Scaling of SOI devices can be limited by the ability to thin the silicon. The silicon thickness must be thinned to achieve device performance targets, but simultaneously the silicide used to contact the source/drain region must be prevented from consuming the entire thickness of the silicon and as a result contacting the BOX layer. This is a significant problem because source/drain contact resistance increases very rapid as the silicide layer approaches the BOX layer.
FIGS. 1A and 1B illustrates a possible approach to forming a raised source/drain structure that employs the option of forming raised source regions and drain regions (above the SOI structure) juxtaposed with the gate electrode stack of the MOSFET device by deposition of additional silicon adjacent to the gate electrode stack after formation thereof.
In FIG. 1A, a MOSFET device 10 is shown in an intermediate stage of manufacture. The substrate 12 comprises a BOX layer upon which a thin doped silicon layer 14 has been formed to serve as the doped region in which the source/drain and channel of an FET device are to be formed. Above the center of the silicon layer 14, a gate electrode stack comprising a gate oxide layer GOX, a polysilicon gate G and a silicide layer SCD have been patterned followed by formation of sidewall spacers on the sidewalls of the gate electrode stack ST.
FIG. 1B shows the device 10 after the exposed surfaces of the thin silicon layer aside from the spacers SP has been coated with a thin epitaxial silicon layer 16 to form what will later be employed as raised source/drain regions by additional processing steps as will be well understood by those skilled in the art.
The method of FIGS. 1A and 1B has significant issues with the selective epitaxy necessary to form the raised source drain. In the selective epitaxy process, silicon is deposited selectively only on exposed silicon surfaces and not on dielectric surfaces such as silicon dioxide isolation regions and silicon nitride spacers. This process is difficult to control because it relies on the balance between silicon deposition and etching in a chemical vapor deposition reactor. Even when acceptable deposition rates on silicon are achieved while simultaneously getting no significant deposition on the dielectric surfaces, the shapes of corners and edges of the silicon surfaces can be changed because of variations in the silicon growth/etch rates with crystallographic orientation. This leads to faceting of these edges resulting in unacceptable device structures. The process is also very sensitive to surface contamination and prior processing conditions during such commonly used process steps as ion implantation, reactive ion etching and wet chemical cleans and etches. The deposition rates are also affected by dopant species and concentration in the silicon surface layers. This can lead to different deposition thicknesses on nFETs and pFETs which is generally undesirable.
Another option is recessing the gate. Such an approach is described by Morimoto et al. U.S. Pat. No. 6,492,696 entitled “Semiconductor Device And Process Of Manufacturing The Same”. Morimoto et al. describes use of a LOCOS process to form a recess of a controlled thickness. A LOCOS film is formed on the surface of exposed areas on the surface of a silicon layer of an SOI substrate. Then the LOCOS film is etched away, leaving a thinner channel region (a recessed channel region) where the LOCOS film has been etched away. Next, a metal film is formed on the entire surface of the substrate to form a silicide film. Since this method utilizes the SOI substrate by adjusting the thickness of the surface silicon layer, the depth of a source/drain region can be controlled, so a source/drain region of relatively large depth can be formed by a common step for forming the source/drain region. This LOCOS recessing process is problematic due to the control necessary in defining the silicon thickness below the gate electrode stack.