A digital phase locked loop (DPLL) in general comprises a phase comparator, a loop filter, a controlled oscillator, and a feedback path. The feedback signal is compared with a reference signal to generate an error signal. The loop filter filters the error signal to generate the control signal for the digital controlled oscillator. In this way the output of the phase locked loop is locked to the reference signal. The convergence time is the time it takes for the output to lock on to the reference signal and is proportional to the filter bandwidth. A low filter bandwidth is desirable to reduce jitter but this implies a long convergence time.
In one type of DPLL, known as a type II PLL, the loop filter is of second order. The loop filter has two parts, known as the proportional or P-part, and integral I-part, which generate corresponding components of the DCO frequency control signal. The I-part accumulates the phase errors into a frequency offset, which is added to the instantaneous phase from the P-part in each cycle. The convergence time is normally dominated by the P-part. However, when the frequency is in lock with the reference signal and the I-part has a small frequency offset, the residual phase convergence time is governed by the small error from the I-part. Under these circumstances the phase error can change extremely slowly, especially when the loop bandwidth is low.
A typical type II DPLL, shown in FIG. 1, comprises a phase comparator 10, a loop filter 11, and a digital controlled oscillator (DCO) 12. The DCO 12 comprises an adder 13 and unit delay memory 14 together forming an integrator with input digital frequency df. Φe is the phase error between the reference clock Φref and the local DCO 12 output or some derivative thereof, for example, a fraction thereof, potentially with some preset offset, with Φe being the output of phase comparator 10. It will be understood that the whole circuit operates under the control of a system clock (not shown).
In this loop filter 11, the P-part 8 consists of multiplier 15, which multiplies the output Φe of the phase comparator 10 by the scaling factor P, and the I-part 9, which consists of multiplier 16 having the scaling factor I as an input, and an integrator, the integrator consisting of adder 17 and memory 18 with unit delay forming part of a delayed feedback loop. The P-part 8 produces a phase compensation component dfp and the I-part produces an integral component dfI, representing a frequency offset relative to the frequency of the reference clock Φref. The components dfp and dfI are further summed in adder 20 to produce a control signal df which is arranged to set the frequency of the DCO 12 so that it becomes locked to the reference clock Φref.
The memory 18 stores the value of the frequency component dfI for one cycle so that the current input dfI to the adder 20 is dfI (previous cycle)+I*dfP (current). Consequently the DCO control signal df at the output of the adders is given by df=dfP (current)+dfI (previous cycle)+I*dfP (current).
The loop bandwidth is generally set by user and is determined by the scaling factor P, which is typically set to be: P=2πf/fsys, where f is the loop bandwidth and fsys is the system clock for the DPLL loop. The P-part will give an instantaneous PLL update value dfp. The scaling factor I, which is input to the multiplier 16, maintains the filter integral part at a very low rate in relation to the P part and in general: I=P/D, where D>>1 is a damping factor.
The DPLL convergence time is proportional to the loop bandwidth and hence is dominated by the P value, which is the input to multiplier 15 as shown in FIG. 1. However, at low bandwidths, when the frequency is in lock, but potentially with a small frequency offset, any small residual phase error Φe will slowly converge to zero responsive to the value of the scaling factor I. In many cases, the convergence could take days, for example, at 1 mHz bandwidth. This is unacceptable for PLL applications and in particular data transmission. In order to speed up the convergence time, it would be theoretically possible to either increase the values of factors P or I. However, the value for scaling factor P is determined by bandwidth and the value for scaling factor I determines the DPLL frequency response. Changing either of them will impact the PLL frequency response and/or the desired bandwidth behavior of the DPLL.