This invention relates to logic circuitry and in particular to current mode logic (CML) circuits employing metal oxide semiconductor (MOS) devices.
In many applications, such as TV systems, high speed counters are a key element. Current-mode logic (CML) circuits employing bipolar transistors for forming high speed counters are known. One stage of such a bipolar transistor current-mode logic (CML) circuit which can be used to perform various counting functions is shown in the Prior Art circuit of FIG. 1.
The circuit of FIG. 1 includes a first differentially connected input stage comprised of transistors Q1, Q2, and Q5 having complementary inputs INA and INB and complementary outputs O1 and O2. The outputs O1 and O2 are respectively coupled via level shift transistors Q7 and Q8 to produce the actual outputs applied to the bases of Q4 and Q3 which function as the inputs of a second differentially connected cross-coupled stage comprised of Q3, Q4, and Q6. The collectors of Q3 and Q4 are respectively connected to outputs O1 and O2 whereby Q3 and Q4 are cross-coupled and function as a latch when Q6 is turned-on.
The outputs O1 and O2 are coupled via resistors R1 and R2, respectively, to the positive supply VDD. The emitters of transistors Q5 and Q6 are connected to the collector of a current source transistor Q9 and the emitters of Q7 and Q8 are respectively connected to the collectors of current source transistors Q10 and Q11. A bias voltage Vbias is applied to the bases of Q9, Q10, and Q11, whereby these transistors function as relatively constant current sources.
Complementary clock signals CLA and CLB are applied to the bases of transistors Q6 and Q5, respectively, to control the turn-on and turn-off of these transistors. When CLB is "high" and CLA is "low", Q6 is OFF while Q5 is ON and couples current source Q9 to the emitters of Q1 and Q2. When CLA is "high" and CLB is "low", Q5 is OFF while Q6 is ON and couples current source Q9 to the emitters of Q3 and Q4.
In the operation of the circuit, when CLB is "high" the differential input stage is enabled and is responsive to the input data, INA and INB, to produce corresponding signals at the outputs O1 and O2. That is, when INA is "high" and INB is "low" the output O1 is "low" and the output O2 is "high" and when INA is "low" and INB is "high", the output O1 is "high" and O2 is "low". When CLA is "high" and CLB is "low" the differential input stage is disabled while the cross-coupled stage is enabled and stores the information generated at the outputs O1 and O2 when the preceding CLB signal was "high". Thus when CLB is "high", input data is acquired by the differential input stage and during the succeeding phase when CLA is "high", the data is stored (i.e., latched) in the cross-coupled differential stage for subsequent transfer and/or application to other stages.
The circuit of FIG. 1 may be used to perform many desirable functions. However, the circuit suffers from some significant drawbacks.
For example, the circuit of FIG. 1 requires the use of at least one transistor Q9 to form a current source and additional peripheral circuitry (not shown) to generate a bias voltage for Q9 to ensure the proper operation of Q9. In addition, the use of transistor Q9 introduces a third level in series with the level of the differentially connected transistors (Q1, Q2) and the level of switch Q5. The presence of the third level (i.e. Q9) complicates the biasing of the stage and the range of the signal swing at the stage output.
Also, the amplitude of the clock signals CLA and CLB applied to the bases of Q5 and Q6 must be within a prescribed range. Otherwise, Q5 and Q6 will be driven into saturation obviating the high speed advantage of the circuit. Hence in the cicuit of FIG. 1, the amplitude of the clock signals must be carefully limited imposing severe constraints on the clock generating circuit.
Furthermore, the outputs O1 and O2 must be coupled via level shift transistors (Q7,Q8) to step down the signal swing to provide an appropriate interface with the next differential stage present at the bases of transistors Q3,Q4. This requires that the circuit includes level shift transistors Q7, Q8 and their associated current source transistors Q10, Q11. Still further, the circuit of FIG. 1 includes resistors R1, R2 which have to be high quality, well matched components. This places a burden on the process since R1 and R2 are non-standard components.
The disadvantages discussed above are overcome in circuits embodying the invention by employing insulated-gate field-effect transistors (IGFETs). Circuits embodying the invention enable a very high frequency operation not achievable using standard complementary MOS Logic circuits.