1. Field of the Invention
The present invention relates to high-voltage MOS transistors and, more particularly, to a high-voltage MOS transistor which is formed on a silicon on insulator (SOI) wafer.
2. Description of the Related Art
A MOS transistor is a device that controls a channel current, which flows from the drain to the source of the transistor, in response to a voltage applied to the gate of the transistor. As a result of this ability to control the channel current, MOS transistors are commonly used as voltage-controlled switches where the transistor provides a very-low resistance current path when turned on, and a very-high resistance current path when turned off.
FIGS. 1A-1B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional n-channel MOS transistor 100. As shown in FIGS. 1A-1B, transistor 100 includes spaced-apart n+ source and drain regions 114 and 116 which are formed in a p-type substrate 112, and a channel region 118 which is defined between source and drain regions 114 and 116. In addition, transistor 100 also includes a dielectric layer 120 which is formed over channel region 118, and a gate 122 which is formed over dielectric layer 120.
In operation, transistor 100 turns on when the drain-to-source voltage V.sub.DS is positive, the drain-to-substrate junction is reverse-biased, and the gate-to-source voltage V.sub.GS is equal to or greater than the threshold voltage V.sub.T. Often, the positive drain-to-source voltage V.sub.DS and the reverse-biased drain-to-substrate junction are set by tying substrate 112 and source region 114 to ground, and applying a positive voltage to drain region 116.
With source region 114 tied to ground, a gate-to-source voltage V.sub.GS which is greater than the threshold voltage V.sub.T may be obtained by simply applying a voltage to gate 122 which is equal to or greater than the threshold voltage V.sub.T. When these conditions are met and transistor 100 turns on, a channel current I.sub.C flows from drain region 116 to source region 114. On the other hand, to turn transistor 100 off, and stop the channel current I.sub.C from flowing, the voltage on gate 122 may be simply lowered so that the gate voltage is less than the threshold voltage V.sub.T.
MOS transistors may be used in both low-voltage and high-voltage environments. High-voltage MOS transistors, however, must be able to withstand significantly larger drain voltages without inducing avalanche breakdown.
Avalanche breakdown occurs when the voltage on the drain region is so large that the electric field across the reverse-biased drain-to-substrate junction accelerates thermally-generated electron-hole pairs at or near the junction. The accelerated electron-hole pairs have ionizing collisions with the lattice which form additional electron-hole pairs that quickly multiply to form a large avalanche current.
This large avalanche current, in turn, has numerous detrimental effects on the operation of a high-voltage transistor.
One technique for reducing the strength of the junction electric field of a high-voltage transistor is to surround the drain region with a lightly-doped region of the same conductivity type. FIG. 2 shows a cross-sectional diagram of a high-voltage n-channel MOS transistor 200 that illustrates this technique.
As shown in FIG. 2, high-voltage transistor 200, like transistor 100, has spaced-apart source and drain regions 214 and 216 which are formed in a p-type substrate 212, and a channel region 218 which is defined between source and drain regions 214 and 216. In addition, transistor 200 also has a dielectric layer 220 which is formed over channel region 218, and a gate 222 which is formed over dielectric layer 220.
As further shown in FIG. 2, transistor 200 principally differs from transistor 100 in that drain region 216 includes a n+ region 216A and a n- region 216B which surrounds n+ region 216A. The purpose of n- region 216B, which is formed as an n- well, is to absorb some of the potential of n+ region 216A, and thereby reduce the strength of the junction electric field.
High-voltage MOS transistors are typically used in output circuits that often require both high-voltage n and p-channel transistors. FIG. 3 shows a cross-sectional diagram of a portion of an output circuit 300 that illustrates the use of both high-voltage n-channel and p-channel MOS transistors.
As shown in FIG. 3, circuit 300 includes high-voltage n-channel transistor 200, and a high-voltage p-channel transistor 310. P-channel transistor 310 includes spaced-apart p+ source and drain regions 314 and 316 which are formed in a deep n-well 312 which, in turn, is formed in p-type substrate 212. Further, drain region 316 of p-channel transistor 310 includes a p+ region 316A and a p- region 316B which is formed from a p-well.
In addition, transistor 310 also includes a channel region 318 which is defined between source and drain regions 314 and 316, a dielectric layer 320 which is formed over channel region 318, and a gate 322 which is formed over dielectric layer 320.
One problem with output circuit 300, however, is that transistor 310 can not be formed with a standard CMOS process because conventional CMOS logic transistors do not require a deep well structure, such as deep n-well 312. In addition, conventional bulk CMOS wafers are typically unable to accommodate a deep well structure.
As a result, high-voltage n-channel and p-channel transistors can not be incorporated onto a chip having CMOS logic circuitry without using non-standard bulk wafers, and altering the fabrication process. Both of these steps, however, add additional cost and complexity to the process and the finished result.
Thus, there is a need for n-channel and p-channel high-voltage MOS transistors which can be incorporated into a standard CMOS process.