The present invention generally relates to a static random access memory, and particularly to a partial random access memory in which a partial write is available with high flexibility.
Currently, a random access memory (hereafter simply referred to as a RAM) is widely used from the following reasons. First, a data write and read can arbitrarily be carried out. Secondly, the degree of freedom to use RAMs is high. Thirdly, there is no need for a refresh operation, while a need exists for a refresh operation in a dynamic random access memory. Recently, there is a great demand for custom integrated circuits called application specific integrated circuits (ASICs), which are fabricated so as to conform to specific applications. Therefore, a further increased degree of freedom to use RAMs is required.
A conventional RAM has a plurality of memory cells arranged in matrix form so as to construct a memory cell array. Each of the memory cells stores data amounting to one bit. In operation, word lines arranged in the Y direction of the memory cell array are selected by a decoded address signal obtained by an address decoder provided in the RAM, which decodes an address signal supplied from an external circuit such as a central processing unit. In this state, bit lines arranged in the X direction of the memory cell array are selected by a data signal consisting of a predetermined number of bits, which is supplied from the external circuit. Thereby, data can be written into or read out from the RAM. The read/write operation in conventional RAMs is carried out for a predetermined number of bits such as 8, 16, 32 and 64 bits.
Currently, in an application, there is a need for partially writing a predetermined number of data bits (high-order bits, low-order bits, or intermediate bits) in addition to the function of writing of all the bits of input data at one time. For example, such a need exists for a floating-point computation, in which the exponent and mantissa parts of two binary numbers to be computed are separately processed. In another application, it is required to rewrite only 36 high-order or low-order bits of data consisting of 72 bits. A write such as the above-mentioned writing operations is referred to as a partial write.
It is noted that conventionally, in order to achieve the partial write, a plurality of write control systems must be provided in a RAM. For example, in the above-mentioned case, a write control system must be provided for each of the 32 high-order bits and 32 low-order bits. It is additionally noted that generally, the partial write function of conventional RAMs is not flexible. For example, 32 intermediate bits of the 64-bit input data cannot be processed in the conventional partial write, when the partial write function is designed to process the 32 high-order bits and 32 low-order bits.
Currently, in RAMs as custom ICs, there is a variety of needs for the bit width of input data, bit width and position of data to be processed in the partial write, all depending on users, demand. Further, a boundary is not always fixed at which bits to be partially written and bits to be maintained as they are, are separated. In the above-mentioned cases, it is very difficult to effectively achieve the partial write simply by using a plurality of write control systems. In other words, the degree of freedom to use RAMs is low.