(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating multilevel interconnections having self-aligned and borderless polysilicon and metal landing plug contacts for integrated circuits. The method is particularly useful for making polysilicon N doped landing plugs for low current leakage to Nxe2x88x92 contacts on the substrate, while concurrently making metal contacts to N+ and P+ contacts on the substrate for low contact resistance.
(2) Description of the Prior Art
Ultra Large Scale Integrated (ULSI) circuits fabricated on semiconductor substrates require multilevels of metal interconnections to electrically interconnect the discrete semiconductor devices on the semiconductor chips. In the conventional method, the different levels of metal interconnections are separated by layers of insulating material. These interposed insulating layers have etched contact holes and via holes which are used to electrically connect the metal layers to the underlying semiconductor substrate and to other underlying patterned conducting layers, such as doped polysilicon, polycide (polysilicon/silicide) layers, and the like.
However, in future generations of integrated circuits, as the minimum feature sizes of semiconductor devices decrease (for example, minimum feature sizes of 0.25 um or less) the lines/spacings shrink. This results in aspect ratios (height/width) of the contact holes or via holes increasing dramatically. Therefore, the contact openings to different underlying Nxe2x88x92, N+, and P+ contacts on the substrate and to tungsten silicide and/or tungsten lines are difficult to make because of the contact opening high aspect ratio. This makes it difficult to etch reliable contact holes to the substrate without damaging the substrate.
To better appreciate this problem, FIG. 1 shows a schematic cross-sectional view of a partially completed integrated circuit on a semiconductor substrate having the conventional contact openings by the prior art. The cross section shows a substrate 10 having field effect transistors (FETs) with gate electrodes 16 with a cap oxide 18 and sidewall spacers 20, and a gate oxide 14. Lightly doped source/drain areas 17(Nxe2x88x92) are formed adjacent to the gate electrodes on some of the FETs in device areas of a first type, for low current leakage contacts, while N+ and P+ contacts 19(N+ or P+) are formed in device areas of a second type for low contact resistance (Rc), such as for CMOS circuits. A planar first insulating layer or an inter-polysilicon oxide (IPO) layer 20 is used to insulate the FETs and on which the next level of electrically conducting lines 24, such as tungsten silicide or tungsten, are formed having a cap oxide layer 26 and sidewall spacers 28. A second insulating layer 40 is deposited to insulate the electrically conducting lines 24, and is planarized. Electrical connections are then made by etching high-aspect-ratio contact openings C to the substrate 10, to the FET gate electrodes 16, and to the next level of inter-connections 24. When these contacts are etched to the shallow Nxe2x88x92 contacts on the substrate, it is difficult to avoid overetching (notching) of the substrate and destroying the Nxe2x88x92, N+, and P+ contact-to-substrate junctions, as depicted by the points N in FIG. 1. Also, for these closely spaced gate electrodes 16, it is difficult to etch the contact C to the substrate without etching into the polysilicon gate electrode, resulting in electrical shorts as depicted by the point S in FIG. 1. Also, in etching contacts C to the substrate, it is difficult to avoid overetching the contacts Cxe2x80x2 to the next level of inter-connecting lines 24, as depicted by the point O in FIG. 1.
Several methods of making high-aspect-ratio borderless contacts are reported in the literature. One method for making borderless contacts is described in U.S. Pat. No. 4,966,870 to Barber et al., in which a silicon nitride etch-stop layer is used on the substrate when the borderless contact is etched in an overlying silicon oxide layer. Other methods for making high-aspect-ratio borderless contacts in insulators are described by Liang et al., U.S. Pat. No. 5,665,623, in which borderless contacts are made to source/drain areas that are less than the minimum feature size of the current photolithographic resolution utilizing the lateral oxidation resulting from the field oxide when the local oxidation of silicon (LOCOS) is used. Huang et al., U.S. Pat. Nos. 5,674,781 and 5,654,589, describe a method and structure in which a titanium/titanium nitride (Ti/TiN) layer is used to make a Ti/TiN stacked interconnect structure to form local inter-connects and contact landing pads on the same level.
Therefore there is still a need in the industry to provide a simpler method for making improved landing plugs for multilevel interconnect structures, which reduces the aspect ratios of contact openings and prevents substrate damage.
It is a principal object of the present invention to make polysilicon and metal contact landing plugs with self-aligned borderless contacts for multilevel interconnections on integrated circuits.
It is another object of the present invention to concurrently make metal/polysilicon interconnecting lines during formation of the polysilicon/metal contact landing plugs, thereby simplifying the manufacturing process steps.
Still another object of this invention is to form N+ polysilicon contacts to Nxe2x88x92 doped substrate contacts, and concurrently to form metal contacts to N+ and P+ doped regions to provide improved (low) contact resistance (Rc).
It is another object of this invention to utilize the polysilicon and metal contact landing plugs to etch contact openings with reduced aspect ratio.
Yet another objective of this invention is to use the process for making these polysilicon/metal plug landing contacts to make improved dynamic random access memory (DRAM) circuits.
This invention describes a method for making polysilicon and metal landing plugs as borderless and self-aligned contacts for multilevel interconnections. The method provides a means for forming N+ doped polysilicon plugs to Nxe2x88x92 doped substrate contacts for low leakage currents, as is typically desired for capacitor node contacts on DRAM device, while providing metal contacts to N+ and P+ doped contacts on the substrate for low contact resistance (Rc), such as in the peripheral areas of the DRAM chips for CMOS circuits.
The method begins by providing a semiconductor substrate having first and second device areas wherein the first device areas require N+ polysilicon contacts to Nxe2x88x92 substrate contacts, while the second device areas require metal contacts to the heavily doped N+ and P+ contacts on the substrate. Typically the substrate is a single-crystal silicon having a  less than 100 greater than  crystallographic orientation and includes N and P wells for making P-channel and N-channel FETs having these P+ and N+ contacts, respectively. A relatively thick Field OXide (FOX) is formed that surrounds and electrically isolates the device areas in and on the substrate. One conventional method of forming the field oxide areas is by shallow trench isolation (STI), as commonly practiced in the industry. The FETs are formed next by growing a thin gate oxide by thermal oxidation on the device areas. An N+ doped polysilicon layer and a refractory metal silicide layer are deposited to form a polycide layer. A cap oxide composed of silicon oxide/silicon nitride is deposited on the polycide layer, and the multilayer is then patterned to form the gate electrodes having this cap oxide. Lightly doped source/drain (LDD) areas are implanted adjacent to the gate electrodes to improve the device characteristics (minimize short-channel effects). Borderless polysilicon and metal landing plug contacts are now formed self-aligned to the gate electrodes. A conformal first silicon nitride (Si3N4) layer is deposited and partially etched back to form sidewall spacers on the gate electrodes and to protect the device areas. The N+ and P+ contact regions in the second device areas are formed by using photoresist ion implant block-out masks and implanting arsenic (As) or phosphorus (P) ions for the N+ contacts, and implanting boron (B) ions for the P+ contacts. A first insulating layer, preferably composed of silicon oxide (SiO2), is deposited by low-pressure chemical vapor deposition (LPCVD), and is planarized, for example by chemical/mechanical polishing (CMP). A first photoresist mask and anisotropic plasma etching are used to selectively etch first contact openings in the first device areas. The first contact openings are etched in the first insulating layer to the first Si3N4 layer in the first device areas for the polysilicon landing plugs, and are self-aligned to the FET gate electrodes. The first Si3N4 layer is then removed in the first contact openings to expose the Nxe2x88x92 contacts on the substrate. After removing the first photoresist mask, an N+ doped polysilicon layer is deposited on the substrate contacting the Nxe2x88x92 source/drain contact areas. A second photoresist mask and anisotropic etching are used to selectively etch second openings in the polysilicon layer and the first insulating layer to the gate electrodes, and to partially etch in the first insulating layer over the N+ and the P+ contact regions in the second device areas on the substrate. The remaining portion of the SiO2 first insulating layer in the second openings over the N+ and P+ contacts is then selectively etched to the first Si3N4. The first Si3N4 layer is then selectively etched in the second openings to expose the N+ and P+ contacts on the substrate. A titanium/titanium nitride first barrier layer is deposited on the N+ polysilicon layer and in the second contact openings making electrical contact to the N+ and P+ contacts in the second device areas. A first tungsten metal layer is deposited on the first barrier layer and is sufficiently thick to fill the first and second openings. The tungsten is also deposited to a thickness sufficient to provide an essentially planar surface. A second Si3N4 layer is deposited. The second Si3N4 layer, the first tungsten metal layer, the first barrier layer, and the polysilicon layer are patterned to form local interconnecting lines. Concurrently during patterning, N+ doped polysilicon landing plugs are formed in the first device areas and tungsten metal landing plugs are formed to the N+ and P+ contact regions in the second device areas. A third Si3N4 layer is deposited and etched back to form sidewall spacers on the local interconnecting lines. A CVD SiO2 second insulating layer is deposited and planarized by CMP. Multilevel contact holes (via holes) are etched in the second insulating layer to the polysilicon landing plugs, to the tungsten metal landing plugs, and to the interconnecting lines. The self-aligned landing plugs prevent overetching the contacts in the substrate and etching into the gate electrodes as commonly occurs in the prior art. Also, the self-aligned landing plugs reduce the aspect ratio for the via holes, thereby making it easier to etch submicron-wide via holes. The process up to the first metal is now completed by depositing a titanium/titanium nitride second barrier layer and a second tungsten metal layer. The tungsten metal layer and the second barrier layer are blanket etched back to form metal plugs in the via holes to the polysilicon landing plugs and to the tungsten landing plugs. A conducting metal multilayer, preferably composed of a titanium-titanium nitride/aluminum copper/titanium nitride (Tixe2x80x94TiN/AlCu/TiN), is deposited and patterned to complete the integrated circuits up to a first level of metal interconnections.