The present invention relates generally to verification of data processing devices. More specifically, the present invention relates to an innovative verification methodology for a deeply embedded computational element.
Various methods and devices have been developed to test logic circuitry which is embedded in an electronic device. Such logic circuitry may include logic elements such as gates and inverters and multiplexers, storage elements such as latches and flip-flops, and more complex elements such as adders and multipliers. All of these devices have inputs for receiving input signals, outputs for providing output signals. The output signal is a function of the input signals and in some cases the previous state of the device.
Testing logic circuitry generally involves verifying the correct operation of the circuitry under a variety of conditions. These conditions include combinations of input signals as well as time-dependent conditions. Under a particular combination of input signals, a certain output signal should result. All possible input and output combinations should be verified for correctness. For circuits for which the output signal is a function of the previous state of the device, all possible input combinations and previous state combinations should be verified.
Some logic circuitry can be prohibitively difficult to test. One example is a deeply embedded computational element within a pipeline circuit. FIG. 1 illustrates a pipeline circuit 100. The pipeline circuit 100 is a functional block implementing a chain of operations. The pipeline circuit 100 includes a plurality of data processing elements 102, 104, 106, 108 connected in series so that the output of one element is the input of the next element. The pipeline circuit 100 has a pipeline input 112 and a pipeline output 114. The data processing elements 102, 104, 106, 108 may be executed in parallel to speed processing. In that case, buffers or other storage may be included between the elements 102, 104, 106, 108 to store intermittent data for the next element. The data processing elements 102, 104, 106, 108 of the pipeline may contain computational elements, such as computational elements 116, 118 of data processing element 104. The location of the computational element 116, 118 within a data processing element 104 that itself is within a pipeline 100 means that the computational element is deeply embedded.
While the exemplary deeply embedded computational element 116, 118 is within a data processing stage of a pipeline circuit 100, the devices and techniques disclosed herein are not limited to this configuration. The devices and techniques also apply to verification of other deeply embedded computation elements, such as a floating point math unit in a central processing unit (CPU).
In a pipeline structure, the outputs of the respective data processing element 102, the inputs and outputs of the respective data processing elements 104, 106, and the inputs of the respective data processing element 108 are generally not available for testing. Neither are the inputs and outputs of the computational element 116, 118 that is located within a data processing element 104 generally available for testing. Conventionally, only inputs to the pipeline and outputs from the pipeline are available. The intermediate signals are not present. Therefore, the operation of each respective data processing element or deeply embedded computational element cannot be readily verified.
One prior solution to the problem of verifying a pipeline structure is to manipulate the input signals to the pipeline block so as to create the desired inputs to the computational block. However, this is difficult and time consuming since the inputs do not directly control the elements. Instead, inputs to the pipeline block pass through many transformations first. Further, if an error condition is detected, it may be difficult to isolate and correct the problem since the erroneous output of the block under test will have passed through data transformations in the pipeline stages that follow it.
A second solution to the problem of verifying a pipeline structure is to multiplex the inputs to the computational elements of the pipeline with an external input. Likewise, an internal output signal of the pipeline can be made available for testing through a multiplexer or other circuit. However, while it may be effective for testing the circuit, this test method adds substantial additional circuitry, which itself can be a source of error and also slows down operation of the pipeline. Since processing speed and throughput are often key features of a pipeline, added circuitry may not be a suitable solution.