1. Field of the Invention
The present invention relates to a voltage level detecting circuit suitable for use in a semiconductor integrated circuit.
2. Description of the Prior Art
It is necessary to prevent an erroneous operation of a semiconductor integrated circuit, particularly an erroneous writing in a memory due to power supply voltage variations.
FIG. 5 shows a prior art voltage level detecting circuit which provides a binary signal by detecting the level of a power supply voltage. This circuit comprises a voltage divider 4 composed of a resistor r and three n-channel MOS transistors 41, 42 and 43 (hereinafter referred to simply as n-MOS transistors 41, 42 and 43) connected in series between the power supply voltage Vcc and ground Vss via the resistor r, and a CMOS inverter 5. The total ON-resistance value of the n-MOS transistors 41, 42 and 43 is significantly smaller than the resistance value of the resistor r.
The voltage level detecting circuit operates as follows. When the power supply voltage Vcc is less than the sum 3VT of the threshold voltages of the n-MOS transistors 41, 42 and 43, the n-MOS transistors 41, 42 and 43 are in OFF-state. Accordingly, the voltage divider 4 will provide a Vcc level or a 2VT level at the node via the resistor r. When the power supply voltage Vcc is greater than 3VT, the voltage divider 4 will provide a 2VT level at the node D. This is caused by the fact that two n-MOS transistors 42 and 43 are in an MOS diode connection.
If the CMOS inverter 5 has a threshold voltage of 1/2 Vcc, it produces a low level signal when the output node D is greater than 1/2 Vcc and a high level signal when the output node D is less than 1/2 Vcc. Accordingly, the detection level of the prior art voltage level detecting circuit is equal to four times the threshold voltage of the n-MO transistors.
In conclusion, the detection level of the prior art voltage level detecting circuit is determined by multiplication of the threshold voltage of the n-MOS transistors, the number of n-MOS transistors connected in series in the voltage divider 4 and the number of n-MOS transistors in the CMOS inverter 5.
The temperature characteristics of the prior art voltage level detecting circuit is described below.
FIG. 6 is a computer simulated graph showing the voltage variations of the nodes D and E with respect to the detected power supply voltage a temperatures of -40.degree. C. and 125.degree. C. The prior art voltage level detecting circuit is extremely sensitive to temperature. The reason is that the voltage detection level is determined by the temperature sensitive threshold voltage of the n-MOS transistors. Provided that the temperature coefficient of the threshold is -1.5 mV/K, the power supply voltage level to be detected varies approximately 1.0 volt under the temperature variations of from -40.degree. C. to 125.degree. C. (165.degree. C. in temperature difference), as shown by the following equation:
(1.5.times.10.sup.-3).times.4.times.(40+125).apprxeq.1.0 volt.
As is evident from the abovenoted explanation, the prior art voltage level detecting circuit can not maintain an exact voltage detection level because it has large temperature dependent characteristics.