One of non-volatile memories in which a storage cell is comprised of a transistor having a floating gate and a control gate is described, for example, in "Complete Transient Simulation of Flash E.sup.2 PROM Devices" by S. Keeny et al., Ie ED-39, No. 12 Dec., 1992". The basic structure of this storage cell is illustrated in FIG. 1.
In FIG. 1(a) and FIG. 1(b), the storage cell is comprised of a MOS field-effect transistor (typically, a so-called SAMOS transistor) having source 2 and drain 3 formed on a substrate 1 made of an impurity semiconductor, such as p-type silicon; a floating gate 4 disposed along and above a channel between the source and drain, and also surrounded by an oxide; a control gate 5 formed above the gate 4 and separated by the oxide therefrom. FIG. 1 (a) depicts how a write or programming is performed to the cell, when the gate voltage V.sub.G and drain voltage V.sub.D are raised to high levels, hot electrons are generated, which are stored onto the floating gate 4. FIG. 1(b) depicts how information stored on the cell is erased, where raising the source voltage V.sub.s to a high level causes the electrons stored on the floating gate 4 are pulled into the source 2, so that holes are stored on the floating gate 4. In other words, by controlling the carriers in the floating gate 4, an information storage state is produced in one cell. For example, the programming state is assigned to "0", and the erasure state to "1".
FIG. 2 shows drain current I.sub.D vs. gate voltage V.sub.G characteristics in programming and erasure states of the memory cell.
However, one cell assumes only two states; thus, because it stores only binary information (i.e., one bit of binary data), it has a disadvantage for recent trends toward expanding memory capacity.
It is an object of the present invention to provide a non-volatile memory which is amenable to increasing memory capacity, and a method of programming it.