1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of field effect transistors having extremely shallow PN junctions.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on an appropriate substrate. Typically, a MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed at an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain region, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of a specified control voltage to the gate electrode, the conductivity of the channel region substantially determines the characteristics of the MOS transistors. For this reason, the channel length represents a dominant design criterion and a size reduction thereof provides increased operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith, which have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.
One problem in this respect is the requirement of extremely shallow PN junctions. That is, the depth of the source and drain regions with respect to an interface formed by the gate insulating layer and the channel region has to be decreased as the channel length is reduced so as to maintain the required controllability of the conductive channel. The depth of the source and drain regions substantially determines the sheet resistance thereof, which may not be arbitrarily reduced by correspondingly increasing the dopant concentration in the source and drain regions, since an extremely high dopant concentration may give rise to increased leakage currents. Furthermore, the dopants implanted into these regions at very high concentrations may not be completely activated by conventional rapid thermal anneal cycles without negatively affecting the overall dopant profile within the source and drain regions. That is, for a desired channel length, defined by the PN junctions, an increased dopant concentration requires higher temperatures and/or a prolonged duration of the corresponding anneal cycles, thereby, however, influencing the dopant profile forming the PN junctions by the inevitable thermal diffusion of the dopants, which finally may lead to a non-acceptable variation of the finally achieved channel length.
In an attempt to further reduce the sheet resistance of the drain and source regions, the conductivity thereof is frequently increased by forming a metal silicide of superior conductivity compared to a highly doped silicon. However, since the penetration depth of the metal silicide is restricted by the depth of the PN junctions, the improvement in gaining conductivity in these regions is therefore coupled to the depth of the corresponding PN junctions. Moreover, in many CMOS technologies, a corresponding metal silicide is simultaneously formed on the gate electrode, wherein a shallow junction depth therefore also creates a very shallow metal silicide in the gate electrode, thereby providing only limited improvement in gaining superior gate electrode conductivity.
In one approach, extremely shallow source and drain regions may be formed by raising the source and drain regions above the gate insulation layer/channel region interface and maintaining the drain-source dopant concentration at an acceptable level while providing the possibility of forming highly conductive metal silicide regions without being restricted by the actual depth of the PN junctions due to the increased size of the raised drain and source regions.
With reference to FIGS. 1a–1d, a typical conventional process flow for forming raised drain and source regions will now be described in more detail. FIG. 1a schematically shows a cross-sectional view of a field effect transistor 100 at an early manufacturing stage. The transistor 100 comprises the substrate 101, for instance a bulk silicon substrate or a silicon-on-insulator (SOI) substrate including a buried insulating layer. Above the substrate 101, a substantially crystalline layer 102 is formed with a thickness that is appropriate for forming PN junctions and a channel region therein. For instance, the transistor 100 may represent an SOI transistor with a thickness of the silicon layer 102 in the range of approximately 20–100 nm. A gate electrode 103, comprised of polysilicon, is formed above the silicon layer 102 and is separated therefrom by a gate insulation layer 104. The gate insulation layer 104 may be formed in sophisticated devices by a nitrogen-containing silicon dioxide layer with a thickness of approximately 0.6–4.0 nm. The residue 105 of an anti-reflective coating covers a top surface 103a of the gate electrode 103, while the sidewalls 103b thereof, as well as the remaining surface of the silicon layer 102, are covered by an oxide liner 106.
The transistor 100 as shown in FIG. 1a may be formed in accordance with the following process flow. The substrate 101 may be obtained by a manufacturer of respective substrates in the form of a silicon bulk substrate or in the form of an SOI substrate, wherein the SOI substrate may comprise a crystalline silicon layer that may be formed in accordance with well-established wafer bonding techniques. The silicon layer 102 having the appropriate thickness may then be formed by corresponding process techniques, such as chemical mechanical polishing to thin a given silicon layer of an SOI substrate to a desired thickness and/or by epitaxial growth of silicon on the exposed surface of the SOI substrate or the bulk substrate. The epitaxial growth technique of a semiconductor material is a deposition technique in which the deposited material layer forms a crystalline structure in conformity with the crystalline structure of the underlying material as long as the deposited material is able to form a lattice that is sufficiently similar in structure and lattice spacing to the lattice of the underlying material. After the formation of the silicon layer 102, an insulating layer is formed having a thickness and a composition that are appropriate for forming the gate insulation layer 104. To this end, sophisticated oxidation and/or deposition techniques may be used as are well established in the art. Thereafter, a polysilicon layer of appropriate thickness is deposited by low pressure chemical vapor deposition. Next, an anti-reflective coating, for instance comprised of silicon oxynitride, and a resist layer are deposited and are patterned by sophisticated photolithography so as to form an etch mask for a subsequent anisotropic etch process for patterning the gate electrode 103 from the deposited polysilicon layer. Thereafter, the gate insulation layer 104 may be patterned and subsequently the oxide liner 106 may be formed by an appropriately designed oxidation process.
FIG. 1b schematically shows the transistor 100 having formed thereon sidewall spacer elements 107 comprised of a material, such as silicon nitride, that exhibits a moderately high etch selectivity with respect to the underlying oxide liner 106 so that the spacers 107 may be readily removed after a selective epitaxial growth process. The sidewall spacers 107 may be formed by well-established techniques including the deposition, for instance by plasma enhanced chemical vapor deposition, of a silicon nitride layer of a specified thickness and a subsequent anisotropic etch process, which reliably stops on and in the liner oxide 106, thereby leaving the spacers 107. A width 107a of the spacer 107 is readily controllable by appropriately adjusting the thickness of the silicon nitride layer. Hence, a lateral extension of epitaxial growth regions adjacent to the gate electrode 103 is substantially determined by the spacer width 107a. 
FIG. 1c schematically shows the device 100 with selectively grown silicon regions 108 above the silicon layer 102, wherein a lateral distance of the regions 108 from the gate electrode 103 substantially corresponds to the spacer width 107a (FIG. 1b) plus the minimal thickness of the liner oxide 106. The transistor 100 as shown in FIG. 1c may be obtained by the following processes. Starting from the device as shown in FIG. 1b, the liner oxide 106 is selectively etched so as to expose the silicon layer 102 at portions that are not covered by the spacers 107, the gate electrode 103, and any isolation structures (not shown). Before and/or after the removal of the liner oxide 106, well-established cleaning procedures may be carried out to remove oxide residues and other contaminants that may have accumulated in a surface region of the silicon layer 102. Thereafter, silicon is selectively grown on exposed portions of the silicon layer 102, thereby forming the silicon regions 108 with a specified thickness in conformity with design requirements. Thereafter, the spacer 107 is removed by a selective etch process, for instance by using hot phosphoric acid, which exhibits an excellent etch selectivity to silicon dioxide and silicon. During this etch process, the residue 105 on top of the gate electrode 103 may also be removed. Thereafter, a conventional process sequence may be performed, as is the case for transistor devices without having the additional selectively grown silicon regions 108. That is, an appropriate number of sidewall spacers may be formed, followed by appropriately designed implantation sequences, so as to establish a required dopant profile in the silicon layer 102.
FIG. 1d schematically shows the transistor 100 after the above mentioned transistor formation process using, for instance, three different sidewall spacers. In FIG. 1d, a first sidewall spacer 109, for instance comprised of silicon dioxide, is located adjacent to the oxide liner 106 and has an appropriate thickness for profiling the dopant concentration in the vicinity of the gate electrode 103 during a subsequent implantation sequence. A second spacer 110 is located next to the first spacer 109 and separated therefrom by an additional liner 106a, followed by an oxide liner 111 and a third spacer 112. The width of these spacers 109 and 112 is appropriately selected to obtain the desired dopant extension regions 113 and the drain and source regions 114, thereby defining a channel region 115 between the extensions 113 with a specified channel length 116.
During the formation of the spacer 109 when comprised of silicon dioxide, the liner 106 is typically etched off the surface portion of the semiconductor layer 102. Therefore, usually the additional liner 106a is deposited prior to the formation of the spacer 110 to provide an etch stop layer. If the first spacer 109 is comprised of silicon nitride, the liner 106 is preserved during the anisotropic etch for forming the spacer 109, however, possibly with an inhomogeneous thickness owing to the etch-induced damage. Therefore, the liner 106 may be removed and the additional liner 106a may also be deposited in this case. The formation of the spacers 109, 110 and 112 may be accomplished by well-established spacer technologies, such as described with reference to the spacer 107, wherein the corresponding spacer width may be controlled by the corresponding deposition thicknesses of the respective spacer layers, for instance comprised of silicon nitride, wherein the first spacer 109 and the oxide liner 111 provide the required etch selectivity in anisotropically patterning the spacers.
As a result, the above-described process flow enables the formation of required shallow PN junctions in the form of the extensions 113, while nevertheless providing a low contact resistance to the drain and source regions 114 by providing the additional selectively grown silicon regions 108, which may be used to receive a highly conductive metal silicide, wherein the silicidation process does not adversely affect the extensions 113, nor is the silicidation process restricted by the depth of the extensions 113 and the drain and source regions 114.
Although the process flow described above provides significant improvements in forming raised drain and source regions, the problem of the restricted channel conductivity still remains since, as previously explained, the channel conductivity depends on the channel length 116 as well as on the dopant concentration within the extensions 113 and the channel region 115. The channel length 116 is substantially determined by the dimensions of the gate electrode 103 and thus a further reduction of the channel length 116 requires an enhanced resolution of the photolithography in the conventional process flow. On the other hand, a further increase of the dopant concentration may lead to increased leakage currents during the transistor operation and may also necessitate sophisticated anneal cycles, thereby possibly adversely affecting the dopant profile in the extensions 113 and the drain and source regions 114. Consequently, further improvements of the conventional process flow are required so as to obtain superior device characteristics for a given channel length 116.
In an effort to improve the channel conductivity, it has been suggested to create tensile or compressive stress in the channel region 115, thereby enhancing the mobility of electrons and holes, respectively. It has been stated that the application of tensile or compressive stress may increase the mobility of charge carriers up to about 20% for a given dopant profile and channel length. The generation of stress in the channel region 115 may, however, entail substantial changes of the above-described well-approved process sequence when a strain layer is formed in the channel region 115 as is suggested in some known process strategies.
In view of the above situation, there is a need for an improved technique that enables the formation of raised source and drain regions substantially in accordance with a conventional process flow while still providing the potential for improving the transistor characteristics by, for instance, increasing the channel conductivity.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.