1. Field of the Invention
The present invention relates to a wiring device for a semiconductor device, a composite wiring device for a semiconductor device, and a resin-sealed semiconductor device. The invention more particularly relates to a wiring device for a semiconductor device, a composite wiring device for a semiconductor device, and a resin-sealed semiconductor device, each of which is capable of mounting thereon a semiconductor chip smaller than conventional semiconductor chips and is manufactured at lower cost than those for manufacturing conventional ones.
2. Description of the Related Art
In recent years, semiconductor devices have been increasingly integrated and functionalized due to their higher integration densities, progress in miniaturization techniques, and the advent of highly functionalized and light and nimble electronic devices. For semiconductor devices formed at higher integration densities and having such enhanced functions, it is requested that the total number of their external terminals (pins) be increased or their terminals (pins) be made multiple.
A semiconductor package has been proposed for such semiconductor devices. The semiconductor package includes a structure in which a semiconductor chip such as an IC chip or LSI chip is mounted on a lead frame and sealed by insulating resin. As the integration density of semiconductor devices is increased and the size of the semiconductor device is reduced, the structure of the semiconductor package is also changed. As the semiconductor package, a small outline J-leaded package (SOJ) and a quad flat package (QFP) were developed. External leads for the SOJ and the QFP protrude from a side wall of a resin package to the outside of the package. After the development of the SOJ and the QFP, a quad flat non-leaded package (QFN) and a small outline non-leaded package (SON) were developed. External leads for the QFN and the SON do not protrude to the outside of the package and protrude from a back surface of a resin package. The QFN and the SON have small thicknesses and small areas in which parts are mounted.
In order to avoid problems with a mounting efficiency and mountability of the QFP, resin-sealed semiconductor devices each including a surface-mount package in which solder balls are provided as external terminals of the package have been produced in large quantities. This package of the resin-sealed semiconductor device is called a ball grid array (BGA). In addition, a semiconductor device including a surface-mount package has been developed in which external terminals are composed of flat electrodes formed in a matrix instead of solder balls of the BGA. This package is called a land grid array (LGA).    Patent Document 1: Japanese Patent No. 2688099    Patent Document 2: JP-A-10-41434