Referring to FIGS. 1-4, a package 10 according to the prior art includes a conductive can 12, and a power semiconductor die 14. Can 12 is typically formed with an electrically conductive material such as copper or a copper-based alloy, and may be coated with silver, gold or the like. Die 14 may be a vertical conduction type power semiconductor MOSFET having its drain electrode 16 electrically and mechanically attached to an interior surface of can 12 by a conductive adhesive 18 such as solder or a conductive epoxy (e.g. silver epoxy). Source electrode 20, and gate electrode 22 of die 14 (which are disposed on a surface opposite to the drain electrode) each includes a solderable body which facilitates its direct connection to a respective conductive pad 24, 26 of a circuit board 28 by a conductive adhesive (e.g. solder or conductive epoxy) as illustrated by FIG. 4. Note that die 14 further includes passivation body 30 which partially covers source electrode 20 and gate electrode 22, but includes openings to allow access at least to the solderable portions thereof for electrical connection. Further note that in package 10 conductive can 12 includes web portion 13 (to which die 14 is electrically and mechanically connected), wall 15 surrounding web portion 13, and two oppositely disposed rails 32 extending from wall 15 each configured for connection to a respective conductive pad 34 on circuit board 28. Also, note that die 14 is spaced from wall 13 of can 12; i.e. wall 13 surrounds die 14. Thus, a moat 36 is present between die 14 and wall 13.
In a package according to the prior art, source electrode 20, and gate electrode 22 are soldered down by the user. Specifically, the user applies solder to, for example, the pads of a circuit board, and the electrodes of the die are attached to the pads by the solder so placed.
A package as described above is disclosed in U.S. Pat. No. 6,624,522.
In a package, according to the prior art, reducing the thickness of the die results in the reduction of Rdson and improved thermal performance as the active area of the die becomes closer to the can.
However, reduction of the thickness presents challenges in wafer handling, back end packaging and particularly die attach processes. For example, as the die thickness is reduced, the die attach fillet 37 height either requires reduction, or, if kept the same, the die attach gets closer to the front side of the die. Reducing the height of the die attach fillet decreases the strength of the die attach joint which may adversely affect reliability. FIG. 5, in which like numerals identify like features, illustrates a package that uses a die with etched apertures to create an assembly with performance close to that of a thin die package but with the ease of the assembly of a thicker die.
A semiconductor package according to the present invention includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive disposed between each raised portion and a respective interior surface of a depression.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.