The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to metal-insulator-semiconductor (MIS) capacitors for use in association FinFET structures and the fabrication of such capacitors.
Fin-type field-effect transistors (FinFETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. Impurities can be introduced below the fins to provide a punch through stop (PTS). Punch through isolation of fins in bulk FinFET devices is provided to avoid leakage and is typically formed with the well implant. A relatively deep implant is required for relatively tall fins. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed following fin patterning. Gate-last procedures can involve forming a dummy gate, fabricating other elements of the transistor such as the source/drain regions, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.
Disposable gate level layers may be lithographically patterned to form disposable gate structures. Specifically, a photoresist is applied over the topmost surface of the disposable gate level layers and is lithographically patterned by lithographic exposure and development. The pattern in the photoresist is transferred into the disposable gate level layers by an etch process, which can be an anisotropic etch such as a reactive ion etch (RIE). The remaining portions of the disposable gate level layers after the pattern transfer form disposable gate structures.
Source/drain extension regions are formed after the disposable gate structures have been completed. A planarization dielectric layer is deposited over the semiconductor substrate, the disposable gate structures, and gate spacers on the disposable gate structures. The planarization dielectric layer may include a dielectric material that can be planarized, for example, by chemical mechanical planarization (CMP).
The disposable gate structures are removed by at least one etch. The at least one etch can be a recess etch, which can be an isotropic etch or anisotropic etch. The removal of the disposable gate structures can be performed employing an etch chemistry that is selective to the gate spacers and to the dielectric materials of the planarization dielectric layer. Cavities are formed from the spaces remaining after the disposable gate structures are removed. The semiconductor surfaces above the channel regions of the substrate can be physically exposed at the bottoms of the gate cavities, though native oxide layers may be present. The gate cavities are laterally enclosed by the gate spacers that were formed on the sidewalls of the disposable structures.
Replacement gate structures are ordinarily formed in the gate cavities. Replacement gate structures are formed by replacement of the disposable structures and overlie channel regions of field effect transistors. A gate dielectric and a gate electrode are formed within each of the gate cavities. A gate dielectric layer can be deposited on the bottom surface and sidewall surfaces of each gate cavity and over the planarization dielectric layer. An electrically conductive material layer can be deposited on a work function material layer to form the remainder of the replacement gate. Portions of the gate conductor layer, the work function material layer(s), and the gate dielectric layer(s) are removed from the planarization dielectric layer by a planarization process. Replacement gate structures are thus formed, which include gate conductor layers, work function material layers, and gate dielectric layers.
Integrated circuits typically include both active semiconductor devices such as field-effect transistors (FETs) and passive devices such as capacitors and resistors. As CMOS technology has advanced, both active and passive devices have been scaled to increasingly smaller dimensions. Metal-insulator-metal (MIM) capacitors have been formed on finned structures to form integrated circuits including both FinFETs and capacitors. Such 3D capacitors can be employed for memory applications, oscillators, or as elements of other integrated circuits.