The present invention relates generally to a path monitoring bit extraction device. More specifically, the invention relates to a path monitoring bit extraction device in a transmission communication system in which an information transmission frame is divided into a plurality of blocks, and time slots of these blocks are assigned to data of a plurality of paths respectively including path monitoring bits for transmission in time division multiplexing manner.
Such type of extraction device for a path monitoring bit has been known as a path alarming terminal device. The path alarming terminal will be discussed hereinafter with reference to FIGS. 11A and 11B. In NNI(Network Node Interface) hierarchy according to the CCITT doctrine, three information blocks of the VC3 path (Virtual Container 3 Path) as a multiplexing unit are multiplexed in a frame of a multiplexing signal, which is thus expressed as VC3.times.3, as shown in FIG. 11A.
In each VC3 path of the multiplexing unit, a path monitoring bit for monitoring the path is contained in addition to data to be transmitted, which path monitoring bit is various alarming information detected in the period of the path.
The frame format of FIG. 11A can be illustrated in a form of timing chart as shown in FIG. 11B. Information transmission frame is divided into a plurality of blocks 1.about.3. Each of the blocks 1.about.3 is further divided into a plurality of time slots. Data in a first path is divided into 1-C, 1-A, 1-B. The data 1-C is superimposed to the first time slot of the block 1. Similarly, the data 1-A is superimposed to the first time slot of the second block 2 and the data 1-B is superimposed to the first time slot of the third block 3. In a similar manner, respective data of the second and third paths, are superimposed and data in the three paths are multiplexed in a time division manner.
It should be noted that SOH means a section overhead and a pointer represents the position of the path monitoring bit in each path.
The path alarming terminal device is adapted to detect and extract the path monitoring bit of each path from the frame. FIG. 12 is a schematic block diagram of the path alarming terminal device. In the shown construction, all data of the information transmission frame 201 is passed through a frame aligner 21 to match the phases of frames of respective path. Then, the path monitoring bit of each path is extracted.
FIG. 13 is a timing chart of the operation of the path alarming terminal device. An input data 201 is input to the frame aligner 21 and sequentially written in a memory in the frame aligner 21 in synchronism with write frame pulse 202. Output data 203 is read out from the frame aligner 21 in a condition where each path is matched to the frame phase by a reading frame pulse 204. The output data 203 is input to a path alarming terminal circuit 22. In the path alarming terminal circuit 22, only the path monitoring bit is extracted and output as a path alarming output signal 205. It should be noted that, in FIG. 13, the data 1-A of the first path, the data 2-A of the second path and the data 3-A of the third path are the path monitoring bits for respective paths.
In such prior art, despite of the fact that the ratio of capacity occupied by the path monitoring bit is small relative to overall data, the frame aligner is required to have a memory of a capacity capable of maintaining all data in order to match the phase of respective paths. This is clearly wasteful and defective.