A current means of being able to resolve the problem of predicting performance during the design of complex systems consists in constructing models of these systems upstream of development, and in doing so at increasingly high levels of abstraction. Starting with a purely behavioural model described by functional blocks and/or algorithms in C, C++, SystemC, the model is gradually enriched by temporal properties and by the description of the constituents of the hardware platform, so that research can be conducted into architectures and an analysis of their performance carried out.
The usual technique consists in using the C++/SystemC computer languages as a means for describing the system models at the so-called transactional abstraction level. Each model is developed rather in a manual way by direct writing of the C++ source code. The model for the architectural study is created by developing successive refinements or enrichments, which produces a complex model that requires considerable creation and verification time, before it can be used to extract results.
The current simulation technique for modelling the effect of a real-time executive (or operating system), which manages the sharing of the CPU resource and the scheduling of the tasks requiring the resource, is applied generally by direct use of the object (or machine) code of this real-time executive (or operating system). This simulation technique is known as native because the real-time executive (or operating system) code is executed directly on the simulation calculator. In this case, it is necessary to have available a model of the processor of the instruction set level, also known as an ISS (“Instruction Set Simulator”) model. Another known native simulation solution consists in using a real-time executive (or operating system) simulator on a workstation of the PC or UNIX (trademark) type.
Moreover, the creation of an architectural model that combines the behaviour of the application with the behaviour of the complex system (including the real-time executives and/or operating systems) is a laborious task and one that is very costly in time terms. Therefore, any modification of the application or complex system requires development and verification time. The combined use of software processors (each running a real-time executive or operating system) and hardware processors (for example programmable and reconfigurable processors of the FPGA type) complicates model creation work still further. This difficulty seriously hampers investment by companies in such developments, which means that architectures are not explored and that, consequently, the performance of architectural choices is only discovered very late in the development cycle with a very significant risk of seeing constraints unmet.
A first major drawback of the known techniques is the considerable time and the significant skill required to develop such models given the manual development.
A second essential drawback of the known techniques stems from the fact that the model developed is monolithic in its construction, in other words the model contains all the aspects in a fully nested way: the functional model, the temporal properties, the processor components, the interconnections between these processors, the simulation model of a real-time executive or operating system for the hardware processors (CPU, MCU and DSP).
A third drawback is that simulation with an operating system (or real-time executive) requires the object code of this operating system (or real-time executive) and of the ISS model of the processor used as execution support to be available. A simulation technique of this kind is, on the one hand expensive since these constituents have to be paid for, on the other hand very slow (factor of 1000 relative to the technique of the disclosure), since the simulation is of the machine cycle (“cycle-accurate” or “cycle-approximate”) level. Of course it is quite precise.
A fourth drawback of the known techniques is that the so-called native simulation technique (direct execution, on the simulation calculator, of the operating system or real-time executive code, or of an approximate model thereof (and therefore without an ISS model of the processor in the latter case)) exists only for a single level of tasks managed by a scheduler. The Applicant of the present application has this known technique at his disposal and it has been added to the SystemC 2.0 language. University teams such as TIMA, INPG of Grenoble and CECS, University of Irvine, CA, have a fairly similar technique at their disposal.
To the knowledge of the inventors of the present disclosure, there is not therefore today in existence any known technique of simulation by execution of models in native for a hierarchy of schedulers for processors (of the software, hardware, mechanical, human type etc). In other words, there is no known technique of simulation by execution of models for several executives or operating systems used hierarchically (a task managed by an executive or an operating system is itself an executive or an operating system) for tasks which it supports.
In fact, there is a need for this since more and more applications, particularly real-time ones, will be operating hierarchical scheduling. Modelling and simulating complex systems executing these applications will therefore probably become unavoidable. By way of example we may cite mobile phones that run a number of specialised nested operating systems, or the capacity of any software application run on an operating system (OS) based on UNIX (trade Mark) or Linux (trade Mark) and using the notions of tasks (processes) and light processes (threads) of these operating systems.
The drawbacks above lead to the situation whereby designers do not explore possible architectures for their systems, and do not do so for reasons of cost and due to lack of time, relying therefore more on their experience and even their intuition to decide on choices of architectures.