(1) Technical Field
This invention relates generally to an apparatus and method for making integrated circuits and more particularly, the invention relates to linear platens and polishing belts for chemical mechanical polishing (CMP) of substrates and its capacity to improve the substrate""s within wafer nonuniformity (WIWNU).
(2) Description of the Prior Art
The following documents relate to methods dealing with chemical mechanical polishing of integrated circuits formed on semiconductor wafers.
U.S. Pat. No. 6,231,427 B1 issued May 15, 2001 to H Talieh et al. shows a linear CMP Tool.
U.S. Pat. No. 6,248,006 B1 issued Jun. 19, 2001 to M. Madhusudan et al. discloses a split multi padded rotary platen for a CMP tool.
The fabrication of integrated circuits on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic photomasks onto the wafer. The photomasking processing steps opens selected areas to be exposed on the wafer for subsequent processes such as inclusion of impurities, oxidation, or etching.
During the forming of integrated circuit structures, it has become increasingly important to provide structures having multiple metallization layers due to the continuing miniaturization of the circuit elements in the structure. Each of the metal layers is typically separated from another metal layer by an insulation layer, such as an oxide layer. To enhance the quality of an overlying metallization layer, one without discontinuities of other blemishes, it is imperative to provide an underlying surface for the metallization layer that is ideally planar. The process of planarizing is now a standard process application of integrated circuit manufacturers.
Plasma or reactive ion etching of the oxide layers having a resist-planarizing medium, is conventional planarization techniques that are used to provide a smooth surface and a local planarization with a range of 1 um.
To meet the demand for larger scale integration, and more metal and oxide layers in devices and the exacting depth of focus needed for submicron lithography, a new planarization method, known as chemical mechanical polishing (CMP), was developed and is presently used by most major semiconductor manufacturers. CMP planarization of a wafer involves supporting and holding the wafer against a rotating polishing pad wet with polishing slurry and at the same time applying pressure. Unlike the conventional planarization techniques, CMP provides a substantially improved overall planarization, that is, an improvement of 2 to 3 orders of magnitude over conventional methods.
CMP enables technology for submicron design rules because it has excellent planarization capacity to meet the stringent lithography requirements. Therefore, it has emerged as an essential process for multilevel interconnection of ULSI chip fabrication. However, poor understanding of polishing phenomena makes it difficult to achieve local and global uniformity. The fundamental consideration of pad properties and motions to achieve global planarization of IC wafers is extremely crucial. The factors effecting WIWNU are material removal rate, planarity and polished surface quality. Among these factors, the polishing pad plays an important role in the CMP process. The role of the polishing pad is the transportation of slurry to the polishing reaction point and how the pad responds to and supports the downward force applied by the wafer-polishing head. Moreover, the pad transfers a shear force of the slurry to the wafer surface and needs to eliminate the polished residue from the polishing point to aid the new polishing reaction. As a result of these effects, properties and behavior of a polishing pad directly affects polishing results.
The polishing pad behaves as being elastic and viscoelastic under applied pressure and this phenomenon affects the WIWNU or planarity. The combination of different belts having different properties such as, percentage of rebound, percentage of compressibility and degree of hardness, would give an overall increase in polishing uniformity. This is based on a soft pad providing better global planarization with poor local planarity, while a hard pad shows better local planarity with poor global planarization.
Therefore, a need exists for a polishing apparatus and method for permitting CMP operations to be done on a semiconductor substrate under controlled process conditions for planarizing particular zones on the substrate while oscillating on several polishing belts simultaneously. Each of the polishing belts having different degrees of hardness, compressibility, percentage of rebound and speeds. The foregoing combination to improve the WIWNU.
A principal object of the invention is to provide a method and apparatus for improving WIWNU, or planarity, using an improved chemical mechanical polishing apparatus for planarizing semiconductor substrates.
Another object of the invention is to provide an apparatus for polishing semiconductor substrates using at least two linear platens for supporting at least two polishing belts having different properties, and to polish with or without an abrasive slurry, so that the best attribute from each belt is used for improving overall global and local planarity of the polished substrate.
Still another object of the invention is to provide at least two adjustable drives for driving each polishing belt at different linear velocities.
Yet another object of the invention is to oscillate the substrate over the selected polishing belts to fix the end point for the desired profile.
Yet, still another object of the invention is to provide pressure control under each belt to increase the polishing rate.
Since a polishing pad behaves as being elastic and viscoelastic under applied pressure which affects the overall planarity of the substrate. Viscoelastic behavior of polymeric pad is considered an important factor affecting polishing results. The combination of different belt pads having different properties such as, percentage of rebound, percentage of compressibility and degree of hardness, would give an overall increase in polishing uniformity. This, as explained before, is partly based on the soft pad providing better global planarization with poor local planarity, while the hard pad does just the opposite. A need exists, therefore, for a polishing apparatus and method for permitting CMP operations to be done on a semiconductor substrate under known and controlled polishing conditions.
A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to motors to independently drive and control at least two of the polishing belts.
Therefore, an apparatus and method is provided for improving the WIWNU conditions by planarizing particular areas on the substrate while oscillating on several polishing belts simultaneously with each belt having different degrees of hardness, compressibility, percentage of rebound and speeds.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follow