This invention relates to a method for manufacturing a semiconductor device, and particularly an IC device, having semiconductor elements formed on an insulating substrate.
An SOS (Silicon On Sapphire) structure is known as a preferred example of the above-mentioned IC structure. The SOS type is suitable for a high density integrated circuits, for it is easy to electrically classify semiconductor elements and the isolation of the semiconductor elements can be effected merely by selectively etching a silicon layer. In the SOS type integrated circuits, a stray capacitance between ground and connections made of aluminium and or poly-silicon and a capacitance on a pn junction are decreased by two orders of magnitude as compared with an ordinary integrated circuit (hereinafter referred to as an integrated circuit constructed of bulk silicon) in which semiconductor elements are formed in a silicon substrate. Thus, the SOS type is also fitted for a high-speed integrated circuit. The SOS type integrated circuit is generally formed as follows.
A number of electrically isolated semiconductor islands are formed on a sapphire substrate. Semiconductor elements are formed in the islands by means such as an impurity diffusion method, etc. A wafer made of the substrate and islands is diced to provide a number of chips. This method, however, presents difficulty in forming a contact opening for taking out a metal connection from the semiconductor element. Contact openings are formed by selectively removing a resist layer by photoetching and selectively etching a CVD (Chemical Vapor Deposition) oxide film or PSG (phosphosilicate glass) film on the silicon layer using ammonium fluoride, while using the remaining resist layer as a mask. In this case, a judgment as to whether or not the silicon layer is exposed by etching, i.e., whether or not the formation of the contact hole is completed is made as follows. That is, the silicon layer repels an ammonium fluoride solution without being wetted, while on the other hand the CVD film or the PSG layer present around the contact opening is intimately wetted with the ammonium fluoride solution. In many cases, the sapphire substrate exposed between the semiconductor elements is relatively intimately wetted with the solution. For this reason, the etching process is judged as complete when solution repellence is observed. Since, however, a number of very small contact openings (In the present design standard, for example, 6.mu.m.times.6.mu.m) are present in the semiconductor wafer it is very difficult to judge the time at which the contact openings have been completed. This exerts a great influence over an LSI (Large Scale Integration) yield. In the LSI circuits, several thousands to several tens of thousands of contact openings are occupied in a single chip. The presence of a single defective contact opening results in a defective chip. With the advent of a high-density LSI circuit there is a tendency for the size of contact openings to be reduced to 4.mu.m .times. 4.mu.m and further to 2.mu.m .times. 2.mu.m, Therefore, such a judging technique is more and more important in the fabrication of intergrated circuits. The other difficulty involved in the manufacture of SOS type integrated circuits resides in that much time is required in positioning a mask. In the method for fabricating integrated circuits comprised of a bulk silicon, a field oxide film is formed which has the feature of being easily distinguishable. The field oxide film is removed along dicing lines on a wafer and, in this case, the position of the dicing line is clearly indicated. The cutting line can be utilized as a mark in locating a mask and thus the mask alignment is easy to achieve. In the method for the manufacture of conventional SOS type integrated circuits, no field oxide film is formed and that surface portion of a sapphire substrate as will be marked with cutting lines is exposed or merely coated with a CVD oxide film. In consequence, it is difficult to provide clear dicing lines. Since the dicing line can not be utilized as a mark in the alignment of a mask, much time will be required in the mask alignment.