The unit of transmission used in the ATM is a cell. An ATM cell contains 53 bytes or 424 bits of information. These cells are transferred at one of the standard transmission rates, e.g., these cells may be transferred at OC-1 (51.84 megabits/second) or OC-3 (155.52 megabits/second) or OC-12 (622.08 megabits/second) or OC-24 (1.244 gigabits/second) or OC-48 (2.488 gigabits/second) and so on. A very high storage capacity and high transfer (input and output) speed storage devices are very much desirable in the ATM network components. The DRAM, Dynamic Random Access Memory, provide lower cost per bit storage capability and provide more memory in the same unit of area compared to most other semiconductor memory devices. For this reason, DRAMs are excellent choice where large quantities of data need to be stored.
There are number of disadvantages of using a DRAM in a conventional way to store ATM cells. One can use the commercially available DRAMs to store the ATM cells but the these DRAMs offer a small number of data input/output pins, e.g., 1, 4, 8, 16 or 18 bits. Therefore, if one desires to construct a cell storage device capable of transferring an entire ATM cell at a time, one has to use many such DRAM chips. For example, using an 8 data bit wide DRAM one has to use at least 53 DRAM chips in parallel.
The speeds at which DRAMs operate, i.e., read/write the external data, are relatively slow. For example, some of the commercially available DRAM chips have memory cycle times of 90, 100, 120, 130 nanoseconds, etc. If one decides to use one such DRAM to store (write) or read an ATM cell, 8 bits at a time, then it would take at least 53 write cycles to store or read the entire cell.
Presently, DRAM memory devices are not commercially available that can read or write an entire ATM cell, in a row of memory array from the external world, in one memory cycle.
The present invention provides a capability of reading or writing an entire ATM cell into a DRAM in one memory cycle and therefore provides a solution for high capacity cell storage and high speed ATM cell input and output with the ATM network external to the integrated circuit device.