In a typical integrated circuit fabrication process, there is at least one fabrication step which patterns a dielectric layer to form windows in the dielectric which expose selected portions of an underlying layer. The windows in the dielectric are generally formed with vertical sidewalls made by a dry etching process and are typically filled with an electrically conducting material, e.g., aluminum or tungsten, to form an electrical contact to at least a portion of the underlying layer. While filling such windows with a metal is conceptually simple, problems arise in practice, and these problems become more severe as the dimensions of the windows continue to decrease. For example, aluminum deposition in small diameter windows may result in electrical discontinuities because typical aluminum deposition processes do not produce conformal layers. Aluminum is typically deposited by sputtering. The aluminum often forms re-entrant angles which make complete filling of high aspect ratio windows difficult.
Many of the problems associated with filling windows with metal or other conductive material may be alleviated by tapering the upper portion of the window so that it is wider at the top than at the bottom. Although producing a window with such a taper seems to be a simple solution to the problem described, it is not easily implemented in practice because the etching techniques widely used to pattern dielectric layers rely on etching which produces substantially vertical sidewalls, i.e., anisotropic etching. Thus, changing the etching technique to produce tapered sidewalls may not be simple. Additionally, whatever etching technique is used, the taper should not produce an excessive increase in window diameter at the underlying layer surface.
Another problem which confronts integrated circuit designers is planarization or dielectric smoothing. As integrated circuits become more complex, additional levels of metallization are often required. The layers of metallization are often separated by dielectric materials. It is desirable that each dielectric layer be comparatively smooth so that subsequently deposited metal can be adequately patterned to form runners.
One approach to dealing with the problem of forming vias and planarization is described in U.S. Pat. No. 4,879,257 issued on Nov. 7, 1989 to Patrick. The Patrick patent teaches the deposition of first and second dielectric layers and the etching of tapered windows through a selectively deposited resist. The windows are filled with metal and coated with resist. A resist etchback, i.e., a planarizing etch that removes resist and the second dielectric at approximately the same rate, is performed to yield a nominally planar dielectric surface having plugged vias.