Thanks to the progress in the field of production processes of integrated electronic circuits, electronic components have become smaller, thus allowing the production of substrates including a large number of integrated circuits. It is also possible to produce compact electronic circuits including a large number of components and consequently the density of the connection terminals suitable for coupling the integrated electronic circuits has also drastically increased. The latest generation of devices thus have a large number of terminals or pads to place in contact, which have a small area and are often very close to one another.
After having been formed in the substrate of a wafer, the integrated circuits are tested so as to be able to optionally remove defective components or repair them if possible. The functionality of each integrated circuit in the substrate is checked by means of suitable probes that make contact with the connection terminals or pads of the integrated circuit itself that is under test and that in the jargon is called DUT (Device Under Test). During the testing process an ATE (Automatic Test Equipment) or tester is electrically coupled to the wafer on which the electronic components are formed. The interface between the ATE and the wafer is a probe card, including a PCB (printed circuit board) and a plurality of probes that electrically couple the ATE with the pads of the devices under test. In general, the wafer is arranged on a support called a chuck belonging to an apparatus called a prober.
The pads commonly used in the building of integrated circuits can have very complex and articulated mechanical structures. A structure for a pad suitable for reducing the risk of delamination and microfractures after high mechanical stresses of the assembly process is described in US 2002/0179991 A1, which is incorporated by reference.
Moreover, in the literature there are various known mechanical structures for pads, which have the purpose of increasing the reliability of the assembly and packaging process and of making the surface of the pad rough so as to increase the adhesion of the wire bond on the pad itself. The increasing need for electronic applications capable of withstanding increasingly high temperatures has required the introduction of new materials for the pads and for the connections between the pads and the package in order to ensure a good electrical coupling. Such materials strengthen the pad itself and give it different mechanical characteristics with respect to those obtained using conventional materials like aluminum. A material used to manufacture latest-generation pad structures is, for example, nickel, which has a greater hardness than aluminum.
In general, the structure of the pad is designed so as to reduce its parasitic capacitance. In this way it is intended to avoid alterations of the signal received or emitted by the pad like, for example, loss, attenuation, or distortion of the signal.
In the testing operations commonly carried out on integrated circuits or DUTs (Devices Under Test) electromagnetic interfaces are also used that allow the exchange of information between ATE and DUT through wireless communication based on electromagnetic waves. Consequently, both in the ATE and in the DUT there are suitable transmitting and receiving circuits (TxRx) coupled, for example, to capacitive antennae that are very often capacitors. A system such as described above is illustrated in FIG. 23.
For chips with high energy consumption, it may be necessary to also provide the power supply in a conventional manner through probes coupled to the pads of the DUT. Concerning this, the upper surface of the pad 1111 (FIG. 24) is also used as an armature of a capacitor of the wireless communication interface that will be of the capacitive type between the pad itself and a system outside the chip. This situation is schematically illustrated in FIG. 24.
To check the integrated circuits, power lines can also be used, wherein a radio-frequency signal can, for example, be superimposed on the power supply as discussed in US 2009/0224784, which is incorporated by reference.
The use of condensers/capacitors is of great importance in many systems like, for example, testing apparatuses and in particular testing interfaces like probe cards where the capacitors are often used on the power lines.
In the system described in US 2006/0038576, which is incorporated by reference, two MEMS probes are capacitively coupled with a capacitor arranged near to the tips of the probes. However, such a capacitor is present on the probe card and not in the integrated circuit tested. Therefore, if the application for which the chip will be used requires the presence of a capacitor, this will have to be added externally in a subsequent step for the final application. This solution is somewhat disadvantageous because it requires the addition of a capacitor outside of the integrated circuit during the production step of the final system, which must be carried out after the chip has been tested, and this results in an end product of greater size given that the capacitor is coupled and located outside of the integrated circuit.
US 2003/0234415, which is incorporated by reference, describes various ways to make a capacitor in an integrated circuit, for example, how to use MIM (Metal Insulator Metal) capacitors or condensers that use the fringing capacitance. An example of a capacitor that uses the fringing capacitance is illustrated in FIG. 25 a where the capacitor is made with coplanar conductive interdigitated structures. Alternatively, the capacitor can also be made vertically as illustrated in FIG. 25 b, where such a capacitor is made up of an upper metal layer 2510, a lower metal layer 2520 and vertical structures 2530 that extend alternatively from the upper metal layer 2510 and lower metal layer 2520 and respectively point towards the lower metal layer 2520 and upper metal layer 2510. In order to increase the capacitance of the capacitor just described, it may be possible to use a stack of metal layers and of vertical connections (vias) that create vertical columns.
Another capacitor for use in integrated circuits including more than two terminals is described in US 2007/0102788, which is incorporated by reference, and is obtained by creating spirals formed on different metallization layers.
Although the solutions in which the capacitor is integrated in the chip allow a saving in cost and production time, the integrated circuits designed in this way may be large in size since the capacitors occupy a substantial area of the chip.
U.S. Pat. No. 6,476,459, which is incorporated by reference, describes a device in which the capacitor is integrated in the substrate of a chip under other structures like, for example, a pad. An example of such a system is schematically illustrated in FIG. 26 in which the capacitor includes the metal layers 2604 and 2608 situated under the bond pad 2620 and surrounding a circuit (not shown).
Also in this case the capacitor is built as an independent structure and, although such a solution reduces the lateral dimensions of the integrated circuit, it may require a greater vertical area to integrate the capacitor. Indeed, since such a capacitor is below the conventional pad, it may be necessary to design a chip having a greater number of metallization layers in which to create the generic capacitor.
A problem of the structures described above is that the capacitive elements integrated in the chip occupy a large portion of its substrate, thus causing an increase in the size of the integrated circuit itself and in its cost.