1. Field of Use
The present invention relates to the cooperative operation of multiple processors in a single system and, more particularly, to a means for reducing the number of interrupt retry attempts between processors of a multiprocessor system.
2. Prior Art
A recurring problem in present computer systems arises from the need to combine the various processors of a multiprocessor system into a cooperative system, and in particular, the need to integrate communications between the processors of a multiprocessor system.
This problem frequently occurs in coordinating the operations of the interrupt mechanisms of the processors of the system. As is well known, "interrupts" are a primary means of communication between the elements of most computer systems, wherein one element of the system, such as a processor may send a request, referred to as an "interrupt", to another element of the system, such as another processor, requesting that the other processor perform some operation for the requesting element or for notifying the other processor of an event requiring attention. Interrupts are commonly assigned priority levels and, if the processor receiving the interrupt is executing an operation or servicing an interrupt of lower priority level than the interrupt, the receiving processor will suspend, or interrupt, the current operation and perform the action requested by the interrupt.
If, however, the receiving processor is servicing an interrupt of the same or a high priority than the new interrupt request, the new request will be denied, commonly referred to as "not acknowledged". This requires that the requesting processor repeat the request for the interrupt at a later time, and generally continue to repeat the interrupt request until the request is accepted. This repetition of interrupt requests until acceptance, however, can consume substantial mounts of processor and system bus resources which are urgently needed for actual operations.
This problem arises both in a multiprocessor system using a single type of processor and, even more acutely, systems using different types of processor units to allow the system to perform a wider range of operations than may be achieved through a system using a single type of processor or to increase the performance of the system by adding faster and more powerful processors or processors providing special capabilities. An example of one such system is disclosed in U.S. Pat. No. 5,283,870 to Thomas Joyce and James W. Keeley entitled, "Method and Apparatus for Avoiding Processor Deadly Embrace in a Multiprocessor System" which issued on Feb. 1, 1994.
It is also well known, and a further problem in interrupt communication between processors, that different types of processors frequently recognize and use different types, numbers and levels of interrupts, so that communications between, for example, a processor designed for a proprietary system such as a DPS 6000 and a processor such as the Intel 80486, can be more difficult.
Additionally, in the above discussed multiprocessor systems, it is important that each processor be able to communicate interrupt requests to other processors within the system in the most efficient manner. Generally, there are three basic reasons for a processor generating an interrupt. One reason is that the processor is calling itself to change priority level to service a more important task. Another reason is that another processor is generating a "solicited" interrupt notifying the processor attempted to be interrupted of the completion of a previously requested task. The last reason is a processor generates an "unsolicited" interrupt request to notify another processor of the occurrence an important event. Such an event could be the detection of a change in state of a mechanical device, environmental sensor or power fail device resulting in the generation of an unsolicited interrupt.
In these cases, it is most important that such interrupts be prioritized in order to ensure that they are processed in the most efficient manner. For example, unsolicited interrupt requests generally would be assigned the highest priorities so that they receive immediate attention. It can be seen that where a processor is generating an interrupt for calling itself, this operation may preclude the servicing of higher priority interrupts. Therefore, it is important to take into account the servicing of different types of interrupts within a multiprocessor system which are assigned different priorities.
It is therefore an object of the present invention to provide an efficient way of having the processors of a multiprocessor system respond to the different types of interrupt requests received from each other.