The present invention relates to comparators and more specifically to dual mode comparators.
It is known in the prior art to have dual mode comparators. Dual mode comparators are often used in automatic testing equipment (ATE) for testing one or more devices under tests (DUTs). Dual mode comparators can operates in any one of a plurality of modes including a differential mode, a common mode, and single-ended mode wherein the mode is selectable based upon an external selection signal provided to the dual mode comparator. The prior art designs provide separate circuitry for each of the modes. Additionally, for each comparison, there is a separate normal windowing comparator (NWC) as shown in FIG. 1.
FIG. 1 shows two inputs provided into the prior art dual mode comparator circuit, which are labeled DUT1 101 and DUT2 102. These inputs are each coupled to a device under test. These inputs may be attached to two separate inputs from a single device or the inputs may be coupled to two separate devices. The circuit includes a pair of output multiplexors (MUX) 103, 104. Each multiplexor receives a control signal that determines the selected comparator mode to output. Thus, by way of example, for the first multiplexor 103, each NWC 110, 111, 112, 113 is active and produces an output signal. Therefore, the multiplexor 103 receives in four input signal and selects two of the four input signals to output (either a single ended comparison of DUT1 with VOH1 and a single ended comparison of DUT1 with VOL1, or a differential comparison with VOH1 and a differential comparison with VOL1). As a result, each NWC 110, 111, 112, 113 circuit is always active. Each NWC 110, 111, 112, 113 circuit includes at least two stages, a comparison stage and an amplification stage. Therefore, the prior art configuration always requires power for the NWC.