The present invention is directed, in general, to semiconductor devices and, more specifically, to an interdigitated capacitor and a method of manufacturing thereof.
As is well known, various semiconductor devices and structures are fabricated on semiconductor wafers in order to form operative integrated circuits (ICs). These various semiconductor devices and structures allow fast, reliable and inexpensive ICs to be manufactured for today""s competitive computer and telecommunication markets. To keep such ICs inexpensive, the semiconductor manufacturing industry continually strives to economize each step of the IC fabrication process to the greatest extent, while maintaining the highest degree of quality and functionality as possible.
Integrated circuits in general have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continues to rise. In order to meet this demand, the integrated circuit industry continues to decrease the size of circuit structures in order to place more circuits in the same size integrated circuit area, thereby continually increasing the packing density for a given chip size. Over the last several years, structures have gone from 1.2 micron gate areas (1 Meg. Capacity) down to gate structure areas of 0.12 microns (1 Gbit capacity), and promise to become even smaller in the near future. Other devices that are steadily decreasing in size are semiconductor capacitors. However, since the capacitance of such capacitors depends somewhat on the surface area of their electrodes, decreasing the size of these capacitors is hampered by the need for a high surface area.
Thus, as the demand for higher quality yet smaller devices continues to grow, the use of different methods for manufacturing semiconductor capacitors has reached phenomenal proportions. Among the primary goals of these newer methods is the increase of the surface area of the electrodes of the capacitor, while maintaining the same, or even smaller, capacitor footprint. Those skilled in the art understand that as the surface area of the capacitor increases within a given footprint, so too does the overall capacitance provided by the device. Conversely, the overall size of a capacitor may be decreased, while maintaining the same or higher capacitance, if the surface area of the capacitor is proportionally increased.
At first glance, an obvious solution to manufacturing capacitors with increased electrode surface areas would be to simply increase the number of layers in capacitors while decreasing layer thickness. An example of such an approach may be a multi-layer ceramic capacitor (MLCC). However, to accommodate desired capacitances, numerous thin-film layers are required to arrive at the necessary surface area. Unfortunately, in addition to the increased risk of layer defects, as capacitor films become thinner they operate closer to the breakdown point of the layer. Thus, capacitors manufactured with such thin films, such as electrolytic capacitors, typically employ xe2x80x9chealing electrodesxe2x80x9d to repair some of the leakage problems that eventually develop. However, those skilled in the art understand that healing electrodes have relatively poor conductivity, making electrolytic capacitors a poor choice for high frequency (e.g.,  greater than 1 Mhz) applications.
Moreover, even if capacitor layer thickness were further reduced, without the adverse consequences discussed above, forming an increased number of layers, for example in an MLCC, results in increased manufacturing steps, which translates into increased manufacturing costs. With the already high cost of semiconductor manufacturing, as well as a market already filled with intense competition, semiconductor manufacturers must make every effort to stream-line the manufacturing process rather than increase the cost.
Accordingly, what is needed in the art is an improved semiconductor capacitor having an increased surface area, and a method of manufacturing thereof, that does not suffer from the deficiencies found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of forming an interdigitated semiconductor device. In one embodiment, the method comprises simultaneously forming first electrodes adjacent each other on a substrate, forming a dielectric layer between the first electrodes, and creating a second electrode between the first electrodes. In this embodiment, the second electrode contacts the dielectric layer between the first electrodes to thereby form adjacent interdigitated electrodes.
In another aspect of the present invention, the method includes producing a first conductive layer over the substrate prior to simultaneously form the first electrodes, and simultaneously form the first electrodes on the first conductive layer. In such an embodiment, the conductive layer interconnects the adjacent first electrodes. In a related embodiment, the dielectric layer is formed over and between the first electrodes, and the second electrode is formed by creating an electrode layer over and between the first electrodes to form interconnected second electrodes over and between the first electrodes.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.