This invention relates generally to a microprocessor and more particularly to a microprocessor utilizing a memory with an instruction space and a data space, where the spaces operate somewhat independently of each other so the microprocessor can perform fetches and execution of instructions and data simultaneously. This type of microprocessor architecture is commonly referred to as "Harvard Architecture". Generally, the type of microprocessor that utilizes Harvard Architecture is a digital signal processor (to be hereinafter called "DSP").
In such a DSP, both the instruction memory and the data memory utilize either read only memory (to be hereinafter called "ROM") or random access memory (to be hereinafter called "RAM"). The RAM or ROM may be located at the interior (on the DSP chip) or exterior of the DSP.
Generally, since the DSP requires high-speed processing capability, high-speed memory must be utilized. High-speed external RAM or ROM is relatively expensive. Although internal ROM is fast, it requires that the DSP must be customized, resulting in high manufacturing costs and a low production quantity. Therefore, it is proposed for high-speed processing and low manufacturing cost to incorporate internal RAM on the DSP chip. However, internal RAM on a DSP chip is limited in capacity. Therefore, there is a need that the RAM be effectively utilized.
One method for a DSP to utilize Harvard Architecture is shown in FIG. 1. An internal RAM 300 is divided into three memory blocks B0, B1, and B2. Blocks B1 and B2 are used only as data memory. Block B0 can be used as either data memory or as program (instruction) memory.
FIGS. 2 and 3 are memory maps (they show the allocation of memory) of the program memory 103, data memory 102, and I/O address memory 105 for this method. FIG. 2 shows the allocation of memory when block B0 is defined as data memory. FIG. 3 shows the allocation of memory when block B0 is defined as program memory.
Small programs requiring rapid execution can be stored inexpensively in block B0, yet be executed at high speed. However, to load a program onto block B0 as program memory requires several steps. Block B0 must first be defined as data memory by using a block definition instruction. The program must then be transferred from external memory to block B0 by using block transfer instructions. Finally, block B0 must be defined as program memory by using another block definition instruction.
A disadvantage of this example is its limited flexibility. Blocks B1 and B2 can only be used as data memory. Block B0 can be used as either data memory or program memory, but it can not be partitioned to store data and instructions. This limited flexibility results in the poor utilization of the limited capacity internal RAM.