1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory (SRAM) and a method of manufacturing the same.
2. Description of the Related Art
Although static random access memory (SRAM) has lower integration density than dynamic random access memory (DRAM), SRAM typically operates at high speed, so that SRAM is widely used for a small or mid-sized computer. A SRAM cell includes a flip-flop circuit composed of two access transistors, two drive transistors add two load devices. Memory information is stored as a difference in voltages between input and output terminals of the flip-flop, i.e., as a charge stored in a node of the cell. The charge is supplied by a power supply V.sub.cc through the load device, i.e., a PMOS transistor or a load resistor, so that the SRAM, unlike the DRAM, requires no refresh.
To sustain and enhance the high speed characteristics of the SRAM, the architecture of a chip, such as architectures for a circuit and an interconnect line for a memory cell must be optimized. In particular, line resistance and parasitic capacitance between the lines are determined by a method of arranging the lines.
The parasitic capacitance generated by a word line of a conventional SRAM will be described with reference to FIG. 1. FIG. 1 is a sectional view of two adjacent SRAM are taken along a word line in a CMOS type SRAM chip using a PMOS thin film transistor (TFT) as the load device.
An active region and an inactive region are defined by an isolation layer 12 formed on a semiconductor substrate 10, and a gate 14 of an access transistor and a gate 16 of a drive transistor are formed by interposing a gate insulating layer 13 on the semiconductor substrate 10 and isolation layer 12. A first interlevel dielectric layer 18 and a word line 20 are sequentially stacked on the gates 14 and 16. The word line 20 is connected to the gate 14 of the access transistor through a contact hole formed in the first interlevel dielectric layer 18. A second interlevel dielectric layer 22 and a gate insulating layer 24 of a PMOS TFT are sequentially stacked on the word line 20. A power supply (V.sub.cc) line 26 formed on the gate insulating layer 24, runs parallel with the word line 20. The power supply line 26 together with a source region of the PMOS TFT form a single body. A third interlevel dielectric layer 28 is stacked on the power supply line 26, and a plurality of bit lines 30 above to the word line 20 are formed on the third interlevel dielectric layer 28.
In a SRAM cell having a structure of FIG. 1, parasitic capacitances C1, C2 and C3 are respectively generated between the word line 20 and the power supply line 26, between the word line 20 and the substrate 10, and between the word line 20 and the gate electrode 16 of the drive transistor. Considering that each word line is connected to all horizontal adjacent cells in common, the total amounts of the parasitic capacitances C1, C2 and C3 produce a delay (RC) associated with the word line. Also, considering that every two word lines are arranged in each cell of all the adjacent vertical cells, the parasitic capacitances of the word line cause a reduction in the operational speed of the chip and a deterioration in chip performance.