1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device, wherein an oxide layer for regulating the ion-implantation is previously formed or separate spacers are selected and formed on different scales before the implantation of the impurities into a predetermined region of a P-lightly doped drain (LDD), to optionally regulate the implantation state of impurities implanted into the predetermined region of the LDD. Accordingly, if necessary, the PMOS and NMOS side predetermined channel lengths are selectively regulated, naturally maintaining the finished PMOS and NMOS side channel lengths equal irrespective of diffusion velocity of the respective impurities even if a substantial annealing process is performed and a P type impurity is diffused faster than an N type impurity.
2. Description of the Prior Art
Generally, a semiconductor device in the relevant art, for example, PMOS device/NMOS device is manufactured by the steps of implanting certain impurities into the predetermined well formation regions 3a and 3b and the predetermined channel formation regions 4a and 4b of a P type element region A1 and an N type element region A2 of a semiconductor substrate 1, which are electrically isolated by an element isolating layer 2, as shown in FIG. 1; forming a P-gate insulating layer 7, an N-gate insulating layer 9, a P-poly gate 8, and an N-poly gate 10 on the P type element region A1 and the N type element region A2, and then lightly doping the P/N type impurities such as, for example, BF or P(As), etc. into the predetermined P-LDD and N-LDD regions 5a and 6a of the respective poly-gates 8 and 10 using an ion-implantation process as shown in FIG. 2; forming spacers 13 and 14 on the sidewalls of the respective poly gates 8 and 10, and then by using the spacers 13 and 14 as a mask, heavily doping the P/N type impurities such as, for example, B or P, etc. into the predetermined P and N-source/drain regions 11a and 12a of the respective poly gates 8 and 10 as shown in FIG. 3; and using a high temperature annealing process for the semiconductor substrate 1 having the structures formed by the above procedures, inducing the diffusion of the impurities implanted in the predetermined well formation regions 3a and 3b, the predetermined P and N-channel regions 4a and 4b, the predetermined P and N-LDD regions 5a and 6a, and the predetermined P and N-source/drain regions 11a and 12a, thereby forming a well 3, a P-channel 4c, an N-channel 4d, a P-LDD 5, an N-LDD 6, a P-source/drain region 11, an N-source/drain region 12 and so on in the finished form as shown in FIG. 4.
For example, such PMOS device and NMOS device according to the prior art have been disclosed specifically in, for example, U.S. Pat. No. 4,745,086 entitled “Removal sidewall spacer for lightly doped drain formation using one mask level and differential oxidation”, U.S. Pat. No. 5,460,993 entitled “Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers”, U.S. Pat. No. 5,254,866 entitled “LDD CMOS with wider oxide sidewall on PMOS than NMOS”, U.S. Pat. No. 6,107,130 entitled “CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions” and so on.
In a system of the related art, in order to form the finished well 3, channels 4c and 4d, LDDs 5 and 6, source/drain 11 and 12 and so on, the annealing process should be performed on the semiconductor substrate 1. As shown in FIG. 5, the P type impurities (such as B) or N type impurities (such as P), etc. implanted into the predetermined P and N-LDD regions 5a and 6a, and the predetermined P and N-source/drain regions 11a and 12a are diffused at a constant velocity by the heat generated during the annealing process.
However, since the P type impurities such as B generally have a diffusion velocity that is greater than that of the N type impurities such as P or As, in the prior art system, the channel length CL1 of a finished PMOS device formed by the diffusion of P type impurities always is shorter than the channel length CL2 of a finished NMOS device formed by the diffusion of N type impurities.
Thus, unless a separate measure is taken in a state where the channel lengths CL1 and CL2 of the PMOS and NMOS devices are different, the PMOS device and NOMS device have no choice but to have different threshold voltages, so that the quality of a finished high integrated semiconductor device would be below a certain level.