1. Field of the Invention
The present invention relates to electrically rewritable semiconductor storage devices and methods of manufacturing the same, and in particular to a non-volatile semiconductor storage device among semiconductor storage devices, and a method of manufacturing the same.
2. Description of the Related Art
As demand for small and large capacity non-volatile semiconductor storage devices has grown, NAND-type flash memories have attracted increasing attention because of their potential improvements in integration density and capacity.
To improve integration density and capacity of such NAND-type flash memories, it is necessary to reduce their design rules. Reducing the design rules requires further refinement in wiring patterns. Since further refinement in wiring patterns requires very sophisticated processing technology, it is difficult to reduce the design rules.
Therefore, recently a large number of semiconductor storage devices have been proposed where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Japanese Patent Laid-Open No. 2003-078044, U.S. Pat. Nos. 5,599,724 and 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a SGT (columnar-type) structure (see, Japanese Patent Laid-Open No. 2003-078044, U.S. Pat. Nos. 5,599,724 and 5,707,885). This semiconductor storage device using transistors with a SGT (columnar-type) structure includes multiple layers of polysilicon corresponding to gate electrodes and pillar-like columnar semiconductors that are formed to penetrate the multiple layers of polysilicon. The columnar semiconductor serves as a channel (body) part of the transistor. The configuration including these gate electrodes and columnar semiconductor is referred to as memory string.
In addition, in the SGT (columnar-type) structure, to select one columnar semiconductor, selection gate lines that extend in a direction perpendicular to the longitudinal direction of columnar semiconductors are connected to the upper and lower portions of the columnar semiconductors. Each of the selection gate lines is formed in such a way that a corresponding columnar semiconductor fits in its width direction. In addition, each of the selection gate lines is arranged to be spaced apart from the adjacent selection gate lines by a certain distance while being insulated therefrom. Further, bit lines that extend in a direction perpendicular to the longitudinal direction of the selection gate lines and the columnar semiconductors are provided above the selection gate lines above the columnar semiconductors. Each intersection between a bit line and a selection gate line is formed to be located on the upper end of the corresponding columnar semiconductor.
In this case, for example, consider the minimum line width of lithography is “F”. If the columnar semiconductor has a diameter (width) of “F”, then selection gate line formed in such a way that the corresponding columnar semiconductor fits in its width direction has a width of “2 F” and may be formed with a space of “F” (in total, “3 F”). On the other hand, the bit line has a width of “F” and may be formed with a space of “F” (in total, “2 F”). That is, one channel part configured by a columnar semiconductor occupies “6 F2” (2 F×3 F). However, there is a need for a greater reduction in the occupation area.