With the sizes of semiconductor devices shrinking, it is a trend in the development of integrated circuits to integrate more electronic devices on a smaller chip. A 3D integrated circuit requires chip-to-chip, chip-to-wafer, or wafer-to-wafer bonding. However, misalignment due to the bonding of chips or wafers may cause shorts or interconnection opens, which significantly reduces the reliability of the integrated circuits and also increases the cost for manufacturing the integrated circuits to a large extent.
In view of this, it is desired to provide a novel 3D integrated circuit structure and a method for detecting whether there is misalignment between chip structures to increase the reliability of interconnection.