In many of today's integrated circuits (IC's), serializer/deserializer (SerDes) circuits are implemented to enable the ICs to exchange information with each other and with other components at very high data rates. As SerDes IO datarates increase to over 10 Gbps, the high speed datapaths for a transmitter can require multigigahertz clocks with multiple clock phases. As a consequence, the power dissipated in those circuits goes up as the frequency scales up, and for high-end multi-core and highly threaded microprocessors, increasing the I/O and memory bandwidth becomes critical in order to continually feed data into the processor pipelines. To support the ever increasing need for bandwidth, processor designs integrate more and more instances of SerDes transmitter and receiver lanes into the chip die area. As such, reducing the area of replicated circuits has a direct impact on reducing the overall area of SerDes IO and ultimately the total power dissipated in the chips.
SerDes circuits include a transmitter and a receiver, also called a serializer and deserializer. Typically, information is sent from a transmitter on one IC to a receiver on another IC through a series of analog pulses. Specifically, to send a digital bit of information, a transmitter determines whether the bit to be sent is a digital 1 or a digital 0. If the bit is a digital 1, the transmitter generates an analog signal (which may be made up of a single signal or a pair of differential signals) having a positive voltage. If the bit is a digital 0, the transmitter generates an analog signal having a negative voltage. After generating the analog signal, the transmitter sends the analog signal as a pulse having a specific duration to the receiver along a communications link. Upon receiving the analog signal, the receiver determines whether the analog signal has a positive voltage or a negative voltage. If the voltage is positive, the receiver determines that the analog signal represents a digital 1. If the voltage is negative, the receiver determines that the analog signal represents a digital 0. In this manner, the transmitter is able to provide digital information to the receiver using analog signals.
Ideally, the receiver should receive analog pulses that closely resemble the analog pulses that were sent by the transmitter. Unfortunately, due to a pulse response effect that is experienced at high data rates, this ideal cannot be achieved. In fact, the analog signal that is received by the receiver often differs from the pulse that was sent by the transmitter by such a degree that the receiver cannot determine whether the received analog signal represents a digital 1 or a digital 0.
To elaborate upon the concept of a pulse response, reference will be made to the sample pulse response shown in FIG. 1. FIG. 1 shows an example of what may be received by a receiver in response to a single positive-voltage pulse (representing a digital 1) sent by the transmitter. In the example shown in FIG. 1, a pulse, y(x−4)≧h0, is sent by the transmitter at sampling time x−4 and a pulse equal to h0 is received by the receiver four time intervals later beginning with sampling time x. Notice that even though the transmitter sent a pulse lasting only a single time interval, the receiver does not receive that pulse at just a single sample time. Instead, the receiver receives an analog signal that lasts for several time intervals. During sampling time x, the received signal has a magnitude of h0. At the next sampling time (x+1), the received signal still has a magnitude of h1. At the next several sampling times, the received signal still has magnitudes of h2, h3, h4, and so on. Thus, even though the transmitter sent a pulse lasting only one time interval, the receiver receives a signal that lasts for many time intervals.
Because of this pulse response effect, a pulse sent in one time interval affects pulses sent at future sampling times. To illustrate, suppose that the transmitter sends another positive-voltage pulse at sampling time x−3, and that this pulse is received by the receiver beginning at sampling time x+1. At sampling time x+1, the receiver would sense the h0 voltage of the pulse sent at sampling time x−3. The receiver would also sense the h1 voltage of the pulse previously sent at sampling time x−4. Suppose further that the transmitter sends another positive-voltage pulse at sampling time x−2, and that this pulse is received by the receiver beginning in sampling time x+2. At sampling time x+2, the receiver would sense the h0 voltage of the pulse sent at sampling time x−2. The receiver would also sense the h1 voltage of the pulse previously at sent sampling time x−3. In addition, the receiver would sense the h2 voltage of the pulse previously sent at sampling time x−4. Thus, the voltage sensed by the receiver at sampling time x+2 is an accumulation of the effects of the pulses sent at sampling times x−4, x−3, and x−2 (and even pulses sent at sampling times before x−4). As this example shows, when the receiver senses a voltage at a sampling time, the receiver does not sense the effect of just one pulse but the accumulation of the effects of multiple pulses.
FIG. 1 shows the pulse response for a single positive-voltage pulse. The pulse response for a single negative-voltage pulse (representing a digital 0) is shown in FIG. 2. Notice that the pulse response of FIG. 2 is similar to the pulse response of FIG. 1 except that the voltages are negative instead of positive. Thus, as shown by FIGS. 1 and 2, the effect that a pulse has on future pulses will depend on whether that pulse is a positive-voltage pulse (representing a digital 1) or a negative-voltage pulse (representing a digital 0). If a pulse is a positive-voltage pulse, then the pulse will add to the voltages of future pulses. Conversely, if the pulse is a negative-voltage pulse, then the pulse will subtract from the voltages of future pulses.
As can be seen from the above discussion, a pulse response can significantly affect the signals that are received by a receiver. Thus, ascertaining the pulse response effect that is experienced by a receiver can be highly desirable in many implementations because armed with knowledge of the pulse response, the pulse response's effects can be compensated for at the transmitter, at the receiver, or both, thus improving the receiver's ability to extract the digital data from the signal. Such compensation can include adjusting the pulse before the pulse is sent based on either preceding pulses or subsequent pulses.
For example, assume that the receiver is configured to detect analog pulses of +1 v (representing a digital 1) and −1 v (representing a digital 0) and assume the transmission delay is 4 time intervals. Because of the pulse response of the system, however, a+1 v pulse sent at sampling times x+10 will not be received at the receiver as a +1V pulse at sampling time x+14 because portions of the signals sent at sampling times x+9, x+8, x+7, etc. will still be sensed by the receiver and portions of the pulse sent at sampling time x+11 might be beginning to be sensed. Thus, in order for the receiver to receive a+1 v pulse at sampling time x+14, the transmitter needs to send a pulse of a different voltage at sampling time x+10. What that different voltage needs to be will depend on the data bits that were sent by the transmitter in previous sampling times (e.g. x+9, x+8, x+7, etc) and the data bits that will be sent in subsequent sampling time (e.g. x+11, etc.). The data bit to be sent (in this example at sampling time x+10) is referred to as the cursor bit. Data bits sent before the cursor bit (in this example, bits sent at sampling times x+9, x+8, and x+7) are referred to as post-cursor bits and bits to be sent after the cursor bit (in this case bits at sampling time x+11, etc.) are referred to as pre-cursor bits. How many pre-cursor and post-cursor bits and which pre-cursor and post cursor bits to use are a matter of design preference.
Depending on the detected pulse response and design preferences, an output driver, such as a current mode driver, of the transmitter might be configured to produce an output for each cursor bit that is a function of the cursor bit, a pre-cursor bit, and two post-cursor bits. Because the cursor bit, pre-cursor bits, and two post-cursor bits will all affect the received signal differently, each will be applied a different weighting, referred to as a tap weighting. For example, the output driver might apply a tap weighting of −0.1 to the pre-cursor bit, 0.6 to the cursor bit, −0.25 to the first post-cursor bit, and −0.05 to the second post-cursor bit, in which case the output would be: Y=−0.1pre1+0.6*cur−0.25*post1−0.05*post2.
For purposes of example, assume the following digital data is to be output by the transmitter and received by the receiver after a four time interval delay.
DIGITAL BIT TODIGITAL BITBE SENT BYRECEIVED ATTIMETRANSMITTERRECEIVERt11t21t30t41t511t601t710t801t901t1010
Because of the four time interval transmission delay, the digital bit sent at t=1 will be received at t=5, the digital bit sent at t=2 will be received at t=6, and so on. Therefore, in order for the system to transmit a digital 1 at t=5 so that a digital 1 will be received at t=9, the output driver will output a voltage that is a function of the digital bits sent at t=3, t=4, t=5, and t=6. In the case of the digital 1 at t=5, the voltage output by the current mode generator would be −0.1(−1 v)+0.6*(+1 v)−0.25*(+1 v)−0.05(−1 v) which equals +0.5 v.
Each subsequently transmitted bit will reuse three data bits used by the previously transmitted bit. The pre-cursor bit for the previously transmitted bit will be the cursor bit for the subsequently transmitted bit. The cursor bit for the previously transmitted bit will become the first post-cursor bit for the subsequently transmitted bit. The first post-cursor bit for the previously transmitted bit will become the second post-cursor bit for the subsequently transmitted bit, and a new bit will be the pre-cursor bit for the subsequently transmitted bit. Reducing the physical size and power consumption of the transmitter is desirable when implementing a SerDes transmitter in hardware. Thus, aspects of the present invention include a SerDes transmitter that limits how many reused, i.e. redundant, bits are transmitted across the high speed data path of the transmitter.