In today's test environment, application specific integrated circuits (ASICs) are extremely dense with various functions while having a limited number of I/O pins with respect to those functions. Often, there are significant, complex functions connected with only internal ASIC buses and signal paths, which are not exposed via an I/O pin. Further, due to the density and complexity of functions, it would not be practical to bring out all needed functions for observation and control, as this would result in potentially thousands of I/O pins.
The observation and control include testing functions within the ASIC. In today's (logical) ASIC test environment, ASICs and the system that contains the ASICs are verified to be functional using a variety of methods, including:
Scan chain testing (a string of values associated with specific input pins are serially loaded into the ASIC so as to present themselves at the input pins, then the ASIC executes a clock cycle, then the values of output pins are clocked out of the ASIC and the values verified to be as expected, then the process is repeated).
External ASIC testers, which connect to and manipulate the I/O pins.
Internal to the ASIC, “hard coded” routines.
Manufacturing test programs run on either processors within the system under test or on special test driver systems.
In addition, it is desirable to observe and control internal system errors in an ASIC. Internal system errors, such as parity errors, bus arbitration errors, errant code pointers, improper memory accesses (to restricted or nonexistent locations) and certain types of software errors have traditionally resulted in a lock-up condition in the system. When this occurs, several options exist:
A software or hardware reset of the system by an external entity, from which a catastrophic error recovery process can be executed (assuming the processor is still capable of running at this level).
A secondary “error service processor” observes the error condition and recovers the system. In some cases, it may be possible to reset only the portion of the system that experiences the error; thus, potentially saving current data or speeding up the error recovery process.
Historically, functional entities were embodied in multiple modules with an exposed bus and signal paths between the modules. This enables the use of logical analyzers, logic debuggers and like tools to be used to observe and control the system. With the advent of integration techniques, multiple modules and their interconnections are now placed inside a single chip, often an ASIC. Because of this integration, the use of these tools (external logical analyzers, logic debuggers and like tools) is not possible with today's ASICs, as there is no physical method available to place the tools on an internal-to-the-ASIC bus and no method to disconnect and tie up or down internal-to-the-ASIC signal paths to provide the observation and control of the functions.
Accordingly, what is needed is a system and method for allowing the observation and control of an ASIC that allows for placing tools internal to the ASIC without requiring additional I/O pins. The system should be easy to implement, cost effective and easily adaptable to standard cell IC design tool. The present invention addresses such a need.