1. Field of the Invention
The present invention relates to a method of determining whether or not the pulse duration or width of a pulse is in a predetermined range, and a pulse width determining device using the method.
2. Description of the Prior Art
In serial communications or the like, whether a pulse received complies with a protocol can be determined bymeasuring the pulse width of the pulse by means of an up counter while performing the receiving operation on the pulse. Referring next to FIG. 13, there is illustrated a block diagram showing the structure of a prior art pulse width determining device for determining whether or not the pulse duration of a pulse is in a predetermined range by means of an up counter. In the figure, reference numeral 131 denotes an edge detecting circuit for detecting the rising and falling edges of each asynchronous pulse applied thereto and for furnishing pulses EDG, EDG1, and EDG2 synchronous to a timer clock signal TCK used for synchronization in the whole of the device, 132 denotes a transfer control circuit for generating a transfer control signal TRS for enabling a switch 135 to transfer the count value of an up counter 136, which is a result of measurement of the pulse width, from the pluses EDG and EDG1 from the edge detecting circuit 131 after the pulse width measurement, and for furnishing the transfer control signal TRS to the switch 135, 133 denotes a counter clear control circuit for generating a clear signal CLR for resetting the count value of the up counter 136 to "00" from the pulses EDG1 and EDG2 from the edge detecting circuit 131 in preparation for the next measurement after the completion of the current pulse width measurement, and for furnishing the clear signal CLR to the up counter 136, and 134 denotes a register for storing the current count value of the up counter 136. The switch 135 can connect the up counter 136 with the register 134, or disconnect the up counter 136 from the register 134, according to the value of the transfer control signal TRS. The up counter 136 can furnish an overflow signal OVF indicating that it is impossible to determine the pulse width of each pulse applied the edge detecting circuit. Reference numeral 137 denotes an INTOVF output circuit which can furnish an interrupt signal INTOVF when the up counter 136 furnishes the overflow signal OVF to the INTOVF output circuit, 138 denotes an INTEDG output circuit for generating an interrupt signal INTEDG indicating the completion of the pulse width measurement from the pulses EDG and EDG2, and RST denotes a reset signal.
In operation, when the power to the pulse width determining device is turned on, the reset signal RST makes a LOW to HIGH transition and the device is then reset. The up counter 136 starts counting up the number of pulses of the timer clock TCK applied thereto. Other components within the device start to run in synchronization with the timer clock TCK.
Referring next to FIG. 14, there is illustrated a timing chart showing the waveforms of signals from components of the pulse width determining device. Hereafter, a description will be made as to the operation of the device with reference to the timing chart of FIG. 14. When the edge detecting circuit 131 receives a pulse, which is applied to the pulse width determining device, asynchronous to the timer clock TCK, it, from the pulse, generates a pulse EDG synchronous to the timer clock TCK, another pulse EDG1 delayed by one-half of the pulse repetition period of the timer clock with respect to the pulse EDG, and another pulse EDG2 delayed by the pulse repetition period of the timer clock with respect to the pulse EDG. The transfer control circuit 132 then receives the pluses EDG and EDG1 and generates and furnishes a transfer control signal TRS which is at a HIGH level to the switch 135 only when only any one of the pulses EDG and EDG1 is at a HIGH level. The switch 135 is turned on only when the transfer control signal makes a LOW to HIGH transition, and it is held in its on state while the transfer control signal TRS is at a HIGH level. When the switch 135 is turned on, the count value of the up counter 136 is transferred to and is then stored in the register 134. Simultaneously, when the INTEDG output circuit 138 receives the pulses EDG and EDG2 from the edge detecting circuit, it furnishes an interrupt signal INTEDG which is at a LOW level only when only any one of the pulses EDG and EDG2 is at a HIGH level.
On the other hand, when the counter clear control circuit 133 receives the pulses EDG1 and EDG2 from the edge detecting circuit, it furnishes a clear signal CLR which is at a HIGH level to the up counter 136 only when only any one of the pulses EDG1 and EDG2 is at a HIGH level. The clear signal CLR is delayed by one-half of the pulse repetition period of the timer clock TCK with respect to the transfer control signal TRS, as shown in FIG. 14. In response to the clear signal CLR, the up counter 136 resets itself and then starts counting up the number of pulses applied thereto from the count value "0" again.
In this manner, the up counter 136 counts up the number of pulses of the timer clock TCK applied thereto within a period of time during which the pulse EDG is held at a HIGH level, and stores the count value into the register 134 by way of the switch 135 when the pulse EDG makes a HIGH to LOW transition. As a result, either a system employing the pulse width determining device or the user can determine whether the received pulse signal has a pulse width which complies with a serial communications protocol by comparing the count value, stored in the register 134, representing the pulse width of the input pulse with the given pulse width defined by the serial communications protocol.
When the conventional pulse width determining device receives a pulse having a pulse width which is too unusually large for the device to measure it, the up counter 136 overflows and then furnishes an overflow signal OVF asserted LOW to the INTOVF output circuit 137. The INTOVF output circuit 137 generates and furnishes an interrupt signal INTOVF which makes a HIGH to LOW transition in synchronization with the falling edge of the overflow signal OVF, and, after that, makes a LOW to HIGH transition after the pulse repetition period of the timer clock signal TCK. A system employing the pulse width determining device or the user can realize that it is impossible to measure the pulse width of the received pulse from the interrupt signal INTOVF. This further makes it possible for the system or the user to implement action to, for example, stop the pulse width determining process for pulses which will be applied to the device.
Thus the prior art pulse width determining device which is so constructed as mentioned can determine whether a received signal complies with a protocol by determining the pulse width of the received signal. However, determining whether the received signal has a pulse width defined by the protocol rather than the pulse width of the received signal is of importance with serial communications. In other words, since INTOVF indicates that it is impossible to measure the pulse width of the received pulse and INTEDG indicates the completion of the pulse width measurement, it can be said that the prior art pulse width only performs a serial communications receiving operation on the received pulse so as to furnish such the indirect signals INTOVF and INTEDG.
While a protocol defining the processing time period for anomalous communication conditions has been being determined so as to handle communication anomalies in a short time, a problem with the prior art pulse width determining device mentioned above is that since the up counter can count up to it maximum count value which is much greater than a predetermined count value corresponding to a maximum pulse width defined by a communications protocol, when the prior art device receives a pulse having a pulse width greater than the maximum pulse width, it causes the up counter to continue to count up without furnishing the interrupt signal INTOVF that it is impossible to measure the pulse width until it determines the pulse width and finally it cannot determine the pulse width within the processing time period defined by the protocol, and therefore the prior art pulse determining device cannot keep up with speeding up communications.
Japanese Patent Application Laying Open (KOKAI) NO. 7-159463 discloses a pulse width determining circuit including a plurality of counters for speeding up the process of determining the duty cycle of a pulse, in which the arithmetic computations for the pulse width determining process are simplified. A problem with the prior art pulse determining circuit is that when it receives a pulse having an extraordinarily long pulse repetition period, it cannot perform the pulse width determining process at a high speed, like the aforementioned prior art pulse width determining device as shown in FIG. 13, because it obtains a reference computation data for the determination of the duty cycle by measuring one repetition period of a pulse the pulse width of which is to be determined.