1. Field of the Invention
The present invention relates to an integrated memory circuit and, more particularly, to a circuit and method for controlling a redundant memory cell during a burn-in stress test.
2. Description of the Related Art
Integrated memory circuits typically include a plurality of memory cells for storing data. A typical integrated memory circuit has capacity of 64 megabits (MBits). However, when one or more memory cells are defective, the integrated memory circuit cannot be used, which reduces manufacturing yield and thereby increases cost. In order to increase yield, integrated memory circuits usually include redundant memory cells. When a normal memory cell is defective, then it is replaced with a redundant memory cell, which allows the device to be used despite the defective memory cell and results in increased yield.
When an integrated memory circuit having redundant memory cells is subjected to a burn-in stress test, then a problem can arise wherein normal memory cells are mistakenly identified as defective and replaced with redundant memory cells. As a result, normal memory cells may be excluded from the burn-in stress test.
FIG. 1 is a circuit diagram of a conventional redundant memory cell control circuit for an integrated memory circuit. Referring to FIG. 1, the redundant memory cell control circuit includes a precharge enable unit 11, a decoder 13, a redundant controller 15 and a redundant enable signal generator 17. A redundant memory cell array 19 is connected to an output terminal of the redundant enable signal generator 17.
The precharge enable unit 11 is composed of a PMOS transistor coupled between a power supply terminal Vcc and a node N1. The gate of the PMOS transistor is driven by a precharge enable signal PPRE. When PPRE is active, the precharge enable unit 11 precharges node N1 to the voltage level of the power supply terminal Vcc. The voltage at the power supply terminal Vcc is typically 3.3 V during either a read or a write operation and is stressed to 5.5 V during a burn-in stress test.
The decoder 13 includes a series of fuses F1-F.sub.2n+2 coupled between node N1 and NMOS transistors M1-M.sub.2n+2. Each of the NMOS transistors M1-M.sub.2n+2 is coupled between one of the fuses F1-F.sub.2n+2 and a ground supply terminal GND and has its gate driven by one of a number of logic level of row address signals RAi/RAiB (i=0, 1, 2 . . . ).
The redundant controller 15 includes a NAND gate 31 and three invertors 33, 34 and 35 connected in series. Each of the inputs to NAND gate 31 receives one of the row address signals RAi-RAiB and generates a redundant control signal PREDE.
The redundant enable signal generator 17 includes a NAND gate 41 and an invertor 43. One input of NAND gate 41 receives the voltage at the node N1 and the other input of NAND gate 41 receives the redundant control signal PREDE which are logically combined in order to generate a redundant cell enable signal RED.
The redundant memory cell array 19 is enabled by the redundant cell enable signal RED. That is, when the redundant cell enable signal RED is logic high, the redundant memory cell array 19 is activated, and when logic low, the redundant memory cell array 19 is inactivated.
In the operation of the redundant memory cell control circuit of FIG. 1, when one of the normal memory cells (not shown) is defective, e.g. the memory cell connected to a row address RA0 is defective, then fuse F1 is cut. During the burn-in stress test, the precharge enable signal PPRE is activated to a logic low level and the precharge enable unit 11 precharges node N1 to the voltage level of power supply terminal Vcc, which is typically 5.5 V. When the node N1 is precharged and the row address signal RA0 is activated to a logic high level, the NMOS transistor M1 becomes active. However, because fuse F1 is cut, node N1 does not discharge and node N1 remains precharged to a high logic state. At this time, the redundant controller 15 generates the redundant control signal PREDE which is active at a logic high level. Accordingly, both inputs to NAND 41 of redundant enable signal generator 17 are at a logic high level and the redundant cell enable signal RED from the redundant enable signal generator 17 is activated to a logic high level and activates the redundant memory cell array 19. In this manner, the defective memory cell corresponding to the row address signal is replaced with the redundant memory cell array 19.
When the node N1 is precharged and the row address RA0 becomes inactive, then a row address RA0B becomes logic high level and node N1 is discharged. At this time, the redundant controller 15 will also generate the redundant control signal PREDE, but node N1 is discharged and the redundant cell enable signal RED will remain at a logic low level. When the redundant cell enable signal RED is inactivate, the redundant memory cell array 19 also remains inactivate.
However, the discharging speed of node N1 can be relatively slow, as illustrated in FIG. 2 (see FIG. 2A). This is because the precharged voltage at node N1 is at a higher level, 5.5 V, than the normal operating voltage, 3.3 V. Consequently, when the redundant control signal PREDE is activated at a logic high at a point P1 of FIG. 2 when the voltage at the node N1 has not sufficiently discharged, then the redundant cell enable signal RED will become a logic high and activate the redundant memory cell array 19. When the redundant memory cell array 19 is mistakenly activated due to the higher burn-in test voltage, a memory cell having no defect will be excluded from the burn-in stress test and may be defective. Thus, the reliability of the integrated memory circuit is reduced.