In the advanced semi-conductor integrated circuits (IC) technology to date, planarization of the structure topology is required at different steps of the fabrication process in order to achieve the desired high density of circuits to be integrated in the chip. This high density of circuits is obtained by miniaturizing the elementary devices such as transistors. Attaining the desired minimal device dimensions requires a high lateral resolution at the photolithographic levels which can only be obtained with a short depth of focus. This is the reason why it is absolutely necessary to planarize the structure before every photolithographic step.
Unfortunately, the planarization makes difficult the alignment of the photomask at a determined level on the previous levels because a plane surface causes a poor visibility of alignment marks and this alignment becomes even an impossible task when the chip has been coated with a layer of a poorly transparent (or in some instances a totally opaque) material. Because, opaque materials such as tungsten, tungsten silicide, polysilicon and TEOS SiO.sub.2 in some extent, are more and more used in planarized structures, this problem of accurate photomask alignment is considered to be very serious.
At present, the alignment problem is generally overcome by introducing an additional photolithographic step in the fabrication process after the planarization has been completed. The aim is to destroy the planarization in a specific region of the wafer, to create an alignment mark or a topology that has the desired visibility to perform the photomask alignment. Unfortunately, this is achieved at the cost of two extra steps: a photolithographic step and an etch step. This known solution to this problem of lack of visibility of alignment marks will be briefly described hereunder by reference to FIG. 1 and FIGS. 2A to 2L, in the particular case where very dense CMOS IGFETs isolated from one another by shallow isolation trenches are integrated in a semiconductor chip according to a conventional fabrication process.
FIG. 1 schematically illustrates a structure 10 shown as a part of a semiconductor wafer at the initial stage of this conventional fabrication process. Structure 10 consists of a silicon substrate 11 with a passivation layer 12 formed thereon. Typically, this passivation layer 12 consists of a 14.5 nm thick silicon dioxide (SiO.sub.2) bottom pad layer and a 150 nm thick silicon nitride (Si.sub.3 N.sub.4) pad top layer, jointly referred to hereinbelow as the Si.sub.3 N.sub.4 pad layer 12 for sake of simplicity. As known for those skilled in the art, substrate 11 is comprised of two types of regions, usually referred to as the "chip" and "kerf" regions respectively, that must be clearly distinguished. The chip region 13 contains the useful circuitry, while the kerf region 14 (which encompasses the chip) includes all the test devices, alignment marks and the like that are necessary to the fabrication of the circuit devices of the chip. The kerf region is destroyed when the wafer is diced in chips by a diamond saw.
Now, the shallow isolation trenches have to be delineated in the substrate 11. First, the structure of FIG. 1 is coated with a layer 15 of a photosensitive material such as a photoresist. After deposition, the photoresist layer 15 is exposed, then baked and developed as standard to leave a patterned layer, also referred to as the IT mask. In essence, the purpose of this masking layer, referenced 15 in FIG. 2A, is to define the locations, e.g. 16A, of the shallow isolation trenches to be formed at the main surface of the silicon substrate 11 in the chip region 13. However, as apparent in FIG. 2A, a specific pattern 16B is made above the kerf region 14. The role of pattern 16B is to define alignment trenches.
The process continues with the IT etch. The wafer is placed in a plasma etcher and an anisotropic RIE etch is performed to transfer the pattern of masking layer 15 in the silicon substrate 11 through the Si.sub.3 N.sub.4 pad layer 12. As apparent from FIG. 2B, a shallow isolation trench 17A (that is relatively wide) and a shallow alignment trench 17B (that has a narrow profile) are formed in substrate 11. Typically, the shallow trench depth is about 600 nm.
The alignment trench 17B that will be subsequently used to define an alignment mark has dimensions consistent with the specifications of photo-steppers that are used at the photolithographic level in consideration. For instance, with the photo-steppers NSR/MCSV manufactured by NIKON Corp. Tokyo, Japan, the alignment mark consists of three rows of 3 .mu.m wide square-shaped recesses separated one from another by 6 82 m, and in this case, the alignment trench width W is in the 1-3 .mu.m range. Next, the remaining portions of masking layer 15 are removed, for instance by ashing in an equipment such as model 200 AC II sold by FUSION SEMICONDUCTOR SYSTEMS, Phoenix, Ariz., USA. The structure 10 at this stage of the process is shown in FIG. 2B.
The next step consists in thermally growing a thin SiO.sub.2 layer (not shown) on the portions of the surfaces of the substrate that are not protected by the remaining portions of the Si.sub.3 N.sub.4 pad layer 12. Then, the shallow trenches 17A and 17B are filled with TEOS SiO.sub.2. To that end, a layer 18 of TEOS SiO.sub.2 having a thickness Th1 of about 700 nm is conformally deposited, generally by LPCVD or PECVD, onto the structure 10. It has therefore the adequate thickness to overfill (by about 100 nm) the shallow trenches as apparent from FIG. 2C. A wide depression 18A above isolation trench 17A and a small depression 18B above alignment trench 17B are created as it may be noticed in FIG. 2C. At this stage of the fabrication, the structure 10 must be planarized and the initial thickness of the TEOS SiO.sub.2 layer 18 must be reduced down to the surface of the Si.sub.3 N.sub.4 pad layer 12.
In reality, the planarization process is comprised of two main processing steps. The first main step comprises the successive deposition of two photoresist layers. A first 700 nm thick layer 19 is deposited onto the structure, then exposed, baked and developed as standard to leave a patterned layer referred to as the AB1 mask still referenced 19. Now turning to FIG. 2D, the AB1 mask 19 is comprised of parts 19A and 19B (blackened), which aims to fill the depressions 18A and 18B above the trenches 17A and 17B respectively.
The structure 10 is then heated to a temperature sufficient to cause the photoresist material of said parts 19A and 19B to flow and completely fill the depressions 18A and 18B for a coarse planarization. Next, a second 700 nm thick layer 20 of the same photo-resist is applied over the structure 10 to form the AB2 mask and baked. After this second step, we can consider that the wafer surface is substantially planar. At this stage of the process, the structure 10 is shown in FIG. 2E.
The planar surface of the FIG. 2E structure will be transferred to the TEOS SiO.sub.2 layer 18 to produce a thinner but still planar surface (except some TEOS SiO.sub.2 pits also referred to as "fences") all over silicon substrate 11. The wafer is placed in a plasma etcher such as an AME 5000 manufactured by Applied Materials Inc., Santa Clara, Calif., USA and is etched with a CHF.sub.3 /NF.sub.3 mixture. The top resist layer 20 and in some extent, the surface of the remaining portions of mask 19 as well, are etched until the surface of the TEOS SiO.sub.2 layer 18 (at mount locations) is reached. However, a slight overetching is performed at this stage of the process. The resulting structure is shown in FIG. 2F.
In the same plasma etcher, but with a different CHF.sub.3 /NF.sub.3 gas ratio, the remaining portions of ABl mask 19 and the TEOS SiO.sub.2 layer 18 are etched at substantially the same rate. Next, the TEOS SiO.sub.2 material is etched, still in the same plasma etcher, but with a CHF.sub.3 /CO.sub.2 mixture that etches the TEOS SiO.sub.2 material of layer 18 much faster than the photoresist of AB1 mask 19. At this stage of the fabrication, the structure 10 is shown in FIG. 2G.
The remaining portions of the AB1 mask 19 are then eliminated. After photoresist stripping, the resulting structure 10 is shown in FIG. 2H. As apparent from FIG. 2H, due to different etch rates and anisotropic conditions, peak-shaped TEOS SiO.sub.2 fences remain at the surface of the structure 10 that are referenced 18A above the shallow trench 17A in the chip region and 18B above the shallow trench 17B in the kerf region.
According to the second main step, a chemical-mechanical (chem-mech) polishing of the structure 10 now is performed. During this step, the TEOS SiO.sub.2 layer 18 remaining over the Si.sub.3 N.sub.4 pads 12 is eliminated. To that end, the structure 10 is first polished until the surface of the Si.sub.3 N.sub.4 pad layer 12 is reached and the polishing is continued for a slight overpolishing for complete removal of the TEOS SiO.sub.2 material except in the shallow trenches 17A and 17B as apparent from FIG. 2I. At this stage of the fabrication, the structure 10 surface is perfectly planar. This terminates the planarization process.
In the following step, the surface of the chip region is protected by a layer of photoresist. After exposition, bake and development, this layer of photoresist forms a block-out mask referenced 21 in FIG. 2J over the whole surface of the chip except above the shallow alignment trench 17B in the kerf region. Then, the TEOS SiO.sub.2 material filling trench 17B is removed by wet etching in a buffered HF bath to produce a recess referenced 22. It is not necessary to completely remove the TEOS SiO.sub.2 material in the trench 17B, a partial etch may be satisfactory as far as a step forming recess is created.
Next, the block-out mask 21 is stripped by ashing as standard. The remaining portions of the Si.sub.3 N.sub.4 pad layer 12 are then eliminated by wet etching in a hot H.sub.3 PO.sub.4 bath that has a high TEOS SiO.sub.2 /Si.sub.3 N.sub.4 selectivity. In turn, the underlying 14.5 nm thick SiO.sub.2 layer is removed by dipping structure 10 in a buffered HF solution. At this stage of the fabrication, the structure 10 is shown in FIG. 2K.
A thin (10 nm) layer of SiO.sub.2 is then thermally grown on the exposed regions of silicon substrate 11 to form the gate dielectric regions of the IGFETs. Finally, the gate electrodes of said IGFETs are formed above the gate dielectric regions. To that end, a 230 nm thick layer of polysilicon, a 230 nm thick layer of tungsten silicide (WSi.sub.x) and a 200 nm thick layer of TEOS SiO.sub.2 are successively blanket deposited onto the FIG. 2K structure. All these layers are represented by a single layer referenced 23 in FIG. 2L. The small depression referenced 23B that can be noticed above alignment trench 17B in FIG. 2L is of paramount importance, because it will be subsequently used as an alignment mark for the photolithographic step that will delineate the gate electrodes in layer 23 at the locations of the gate dielectric regions. The process continues in the other sectors of the manufacturing line until the complete fabrication of the devices composing the chips.
As clear from the above description, defining the gate electrodes over a planar surface coated with a stack of layers wherein at least one of the materials forming the composite layer 23 is opaque requires both a specific photolithographic step and an etching step to define an alignment mark in the kerf region (in this instance depression 23B). A photolithographic step implies the sub-steps of: depositing a layer of photoresist, baking, exposing the layer through a photomask to form a masking layer having the desired pattern to expose the alignment trench, etching the TEOS SiO.sub.2 material filling the alignment trench and finally stripping the masking layer of photoresist.