1. Field of the Invention
This invention relates to compilers and schedulers in multi-threaded environments, and particularly to systems, methods and computer products for cross-thread scheduling.
2. Description of Background
Current design-goals on multithread machines focus on achieving multiple instructions issuing but with limitation on the number of simultaneously issued operations per cycle. One example of the above-mentioned machine is a multiple instruction issue machine with limited same-thread multiple issues (e.g., a machine that can issue two instructions per cycle: one arithmetic-logic unit (ALU) one Memory unit (MEM) but only one instruction per thread). This design-goal would require multi-threading in order to achieve high throughput. In addition, it is appreciated that instruction level parallelism (ILP) traditionally exploited by compiler-based instruction schedulers cannot be achieved within a single thread. Thus, multiple threads are considered. What is needed is thread instruction scheduling to maximize the likelihood of high throughput of the machine (i.e. of all the threads running concurrently).