This disclosure relates to clock signal control.
Some examples of data processing circuitry make use of a so-called generic timer architecture which employs a system counter to provide a uniform measure of system time throughout the circuitry. Such a counter can count in proportion to a number of received clock pulses of a system clock signal and provide a “timestamp” dependent upon a current count value.
The count value can typically be distributed to multiple timers and/or “watchdogs”. Here a watchdog might be a circuit which detects, for example, a lack of activity by a processing element for a particular period of time, and in the event of such a detection issues a reset or interrupt signal to that processing element. In this way the watchdog circuit can detect (at least the symptoms of) a processing element becoming locked up or suffering a program crash, and initiate action to provide a recovery from that locked up situation.
For systems configured to selectively operate in low power modes, it is known to provide multiple clock signals at different respective clock frequencies. A simple example would be to have a slower reference clock and a selectable faster clock, for example generated from the slower clock by a device such as a phase locked loop (PLL). In a low power mode, the system runs on the slower clock and in a higher performance (but higher power consumption) mode the system runs on the faster clock.
But in both clocking modes a consistent count timestamp is required in order for subsystems or devices which depend on the timestamp (such as the timers and watchdogs discussed above) to operate correctly, such that the timestamp is not affected by changes in clock frequency. Implementing separate counters for each clock domain could require a potentially convoluted procedure to load timestamps from one clock domain to another to maintain a uniform view of system time.