Digital data streams permit high amounts of data to be transmitted over relatively long distances, often at high frequencies. For example, high speed serial data streams may transmit data in Gigabit range and higher. Some digital data streams, especially high-speed serial data streams are transmitted without an accompanying clock signal. A transceiver generates a clock from an approximate frequency reference and then phase-aligns to transitions in the data stream. Many digital data streams require relatively small preambles and large payloads in order to meet data rate transfer requires. Thus, these streams require fast locking on incoming data.
The circuits that lock onto incoming digital data streams are referred to as clock and data recovery unites (CDR). These modules are present within transceiver/receiver modules and perform phase alignment and phase picking to lock onto incoming data streams. Phase alignment attempts to set the sampling time to a center of a received signal (bit cell). In one example, a conventional system utilizes a phase locked loop (PLL) to perform phase alignment. Phase picking detects data transitions and picks data samples furthest away from detected data transitions.
Conventional solutions use classical phase detectors, including exclusive OR (XOR) detectors and are challenged by high frequency signals with short preambles. The conventional solutions suffer from limitations on usable synchronization preambles and voltage offset tolerances. The classical phase detectors only provide limited output signals. As a result, long dead times can occur when no clear phase relation between input pattern and sampling clock is present. This can prevent phase alignment logic from operating fast or correctly.
Classical high speed clock and data recover circuits try to keep the sampling point for a data sampler at an optimum point by watching samples at slopes and/or edges of an input signal. Clock phase changes are then derived out of a number of samples detecting a sufficient number of slopes.
Generally, if the slope is between leading edge sample point and data sample point, then the data sampling can be considered late. If the slope is between a data sample point and following edge sample point, the data sampling is too early. If there are slopes in both time sections, then no action is taken and there is phase alignment. If there is sampling error or noise, such as too many detected transitions in a cycle, no action is taken and needed adjustments can be delayed. The conventional systems will wait until additional samples are obtained. Further, the prevalent use of short preambles and/or synchronization periods, can further delay phase locking and prevent or reduce data transmission.