The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
The modern consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, (e.g. transistors), has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support increased circuit density.
One solution to such a problem is to stack the functional silicon devices into 3D (three dimensional) semiconductor packages formed from multiple functional silicon dies including one or more memories and one or more logic dies.
The more densely packed the functional elements become within any given semiconductor package, the better the performance will be for that semiconductor package as there can be more “stuff” within the same physical space capable of performing functional aspects of the functional semiconductor silicon dies and devices of the semiconductor package and the shorter the information must travel, thus resulting in faster processing.
Reducing the total space occupied by the same number of functional silicon dies helps to address this problem by stacking the functional silicon dies into a package to realize such physical space reductions.
But such a solution introduces additional complexity and brings additional problems which must now be addressed.
The present state of the art may therefore benefit from (i) the means for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems; (ii) the means for implementing fault identification of a Through Silicon Via (TSV) in Two-Level Memory (2LM) stacked die subsystems; (iii) the means for implementing testing of fault repairs to a Through Silicon Via (TSV) in Two-Level Memory (2LM) stacked die subsystems; and (iv) the means for implementing testing of a far memory subsystem within Two-Level Memory (2LM) stacked die subsystems, each of which are described herein.