1. Field of the Invention
This invention relates to the field of power-on reset circuits, and particularly to power-on reset circuits for use in systems operated with a low supply voltage.
2. Description of the Related Art
Power-on reset circuits are well-known. Such circuits assert a reset signal, typically by toggling a digital logic signal, when a power supply voltage ramps to its rated voltage from an off state. A conventional field-effect transistor (FET) power-on reset circuit is shown in FIG. 1a. A pair of transistors MP1 and MN1 are connected between supply voltages VDD and VSS at a node 10, and a pair of transistors MP2 and MN2 are connected between the supply voltages at a node 12. A latch 13 is also connected between VDD and VSS, formed from cross-coupled FETs MP3/MN3 and MP4/MN4; the latch is controlled by the voltages applied to the gates of MN3 and MN4, which are connected to nodes 10 and 12, respectively. The output (RESET) of the circuit is taken at latch node 14. When supply voltage VDD is less than the threshold voltage of MP2 (VtMP2), the status of node 14 is undetermined. When VDD becomes higher than VtMP2, MP2 is turned on, but MN2 is still off. Node 12 is pulled up to the supply (VDD), which turns on MN4 and pulls down output node 14. An active low reset signal is generated at node 14. When VDD further increases such that it is greater than VtMP1+VtMN1, node 10 is pulled up enough to turn on MN2 and MN3. Since MN2 is much stronger than MP2, node 12 is pulled down to VSS. The latch changes state so that the output at node 14 goes to VDD, i.e. the reset signal becomes inactive. The threshold voltage at which this occurs is referred to herein as Vdd,th. Operation of this circuit is illustrated in FIG. 1b, which plots the voltage at node 14 with respect to increasing VDD.
Unfortunately, the circuit shown in FIG. 1a encounters problems when the steady-state supply voltage is low (e.g.,  less than 2.4 volts), as is increasingly common. Because the threshold voltage of a MOS transistor can vary as much as xc2x10.2 volts with process and xc2x10.2 volts with temperature, the Vdd,th voltage, which is the sum of two MOS threshold voltages, can vary as much as xc2x10.8 volts. For example the Vdd,th can range from 0.8 volts to 2.4 volts using the above power on reset circuit, setting the minimum supply voltage to 2.4 volts.
One possible example of a power-on reset circuit which could be employed with a low supply voltage is shown in FIG. 2a. The circuit comprises a reference voltage generator 16 which produces a reference voltage Vref1 as VDD ramps up from zero volts to its rated voltage, and a voltage generator 18 which produces a voltage V2 that tracks the supply voltage. Here, V2=VDDxe2x88x92V1, where V1 is the voltage drop Vbe across a p-n junction. Reference generator 16 comprises a diode connected NMOS transistor MN5 biased by a current source i1, such that Vref1 is the gate-to-source voltage (Vgs) of an NMOS FET. A comparator 20 asserts a first reset signal RS1 when Vref1 is greater than V2, and deactivates RS1 when Vref1 is less than V2. By having V2 vary little with process and Vref1 compensate for changes in V2 over temperature, the threshold voltage Vdd,th at which RS1 is deactivated can be controlled to xc2x10.2 volts of a target value with standard process variation and a wide temperature range (e.g. xe2x88x9240xc2x0 C. to 125xc2x0 C.). When properly arranged, the power-on reset circuit shown in FIG. 2a can operate with supply voltages of less than 2 volts.
Unfortunately, the circuit shown in FIG. 2a works well when the time (xe2x80x9ctrxe2x80x9d) required for VDD to ramp up is such that there is a period during the ramp up when Vref1 greater than V2. However, when tr is too short, e.g., tr less than 1 ms, V2 may remain greater than Vref1 throughout the ramp-up time; when this happens, RS1 is not asserted. This is illustrated in FIGS. 2b and 2c. In FIG. 2b, VDD ramps up relatively slowly. At time t1, currents i1 and i0 start up, and V2 and Vref1 start to increase accordingly. At time t2, Vref1 becomes greater than V2, and RS1 is asserted. Then, at time t3, V2 becomes greater than Vref1 and RS1 is de-asserted. In this way, an active-low reset signal is generated, having a duration given by xcex94t=t3xe2x88x92t2.
There are two ways in which RS1 can fail. If xcex94t is too short, comparator 20 may not have a chance to work and RS1 will not be asserted. The second failure mechanism is illustrated in FIG. 2c. Here, VDD ramps up so quickly that Vref1 never becomes greater than V2 during the ramp up time. As such, RS1 is never asserted.
A power-on reset system is presented which overcomes the problems noted above. The present system is insensitive to the rate at which the power supply is ramped up. In addition, the power-on reset system preferably has a more precise Vdd,th than the prior art, such that it operates reliably at a low supply voltage.
The present system includes two power-on reset circuits. The first reset circuit normally asserts a first reset signal RS1 as VDD ramps up from zero volts to its rated voltage, as long as ramp up time tr is sufficiently long. The first reset circuit sets the threshold, Vdd,th, for the power-on-reset system.
The second power on reset circuit is designed to assert a second reset signal RS2 when the power-on ramp up time is short. The circuit comprises a first reference voltage generator which produces a reference voltage VR1 as VDD ramps up from zero volts to its rated voltage, and a second reference voltage generator which produces a reference voltage VR2 that is delayed with respect to VR1 and is higher than VR1 when VDD is at its rated voltage. A comparator asserts the second reset signal RS2 when VR1 is temporarily greater than VR2. A logic gate receives RS1 and RS2 at respective inputs, and asserts a reset signal RS3 when either RS1 or RS2 is asserted; RS3 is the output of the power-on reset system.
When so arranged, if the first reset circuit fails to assert RS1 due to a ramp-up time which is too short, the second reset circuit asserts its reset signal RS2. Output reset signal RS3 is thus asserted regardless of the duration of the ramp-up.
With the second reset circuit to overcome the short ramp-up time problem and the first reset circuit to provide a more precise Vdd,th, the reset system can operate reliably at supply voltages of less than 2 volts.