The present application relates to an interconnect structure and a method of forming the same. More particularly, the present application relates to copper wiring structures that are encapsulated on all surfaces (i.e., sidewalls, bottommost and topmost) by a copper titanium alloy and a method of forming such structures.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
As the interconnect feature sizes shrink, it is necessary to scale liner thickness in order to maximize copper volume and to enable low line and via resistance. Scaling sidewall liner thickness allows reduction of line resistance, and scaling liner thickness at the via bottom allows reduction of via resistance.
For void-free Cu fill at about 20 nm critical dimensions, a liner or seed enhancement layer such as ruthenium is typically needed to avoid the formation of sidewall voids which may degrade electromigration performance. Seed layer enhancement layers have a negative impact on the line and via resistance; they displace Cu volume in lines, and add to the contact resistance in the vias.
In view of the above, there is a need for providing a single low-resistivity material which can be formed at metal/interconnect dielectric interfaces and at metal/metal interfaces that avoids the formation of seed enhancement layers and thus provides reliable interconnect structures.