1. Field of the Invention
This invention relates to the prevention of reverse engineering of integrated circuits (ICs), and more particularly to security techniques in which the conductive or nonconductive nature of interconnections between circuit elements is made camouflaged.
2. Description of the Related Art
Several techniques have been used to reverse engineer Ics. Electron (e)-beam probing with a scanning electron microscope (SEM), either through SEM photographs or voltage contrast analysis, is a standard reverse engineering mechanism, although secondary ion mass spectrometry (SIMS), spreading resistance analysis and various other techniques have also been used. A general description of e-beam probing is provided in Lee, "Engineering a Device for Electron-beam Probing", IEEE Design & Test of Computers, 1989, pages 36-49.
Numerous ways to frustrate unwanted attempts to reverse engineer an IC have also been developed. For example, in U.S. Pat. No. 4,766,516 to Ozdemir et al. (assigned to Hughes Electronics, the assignee of the present invention), additional circuit elements that do not contribute toward the desired circuit function are added to an IC, and disguised with the visible appearance of being an ordinary part of the IC. The elements have physical modifications that are not readily visible but cause them to function in a different manner, inhibiting the proper functioning of the IC in case of an attempted copying or other unauthorized use. When the apparent function rather than the actual function of the disguised elements is copied, the resulting circuit will not operate properly.
In U.S. Pat. No. 4,583,011 to Pechar a pseudo-MOS (metal oxide semiconductor) device is given a depletion implant that is not readily visible to a copier, who would infer from the device's location in the circuit that it would be enhancement-mode. A somewhat related approach is taken in French patent publication no. 2 486 717 by Bassett et al., published Jan. 15, 1982; the circuit doping is controlled so that some devices which appear to be transistors actually function as either open or short circuits. And in U.S. Pat. No. 4,603,381 to Guttag the memory of a central processing unit is programmed by the doping of its channel regions, rather than by the presence or absence of gates, to protect permanently programmed software.
Instead of disguising circuit elements, some systems have a mechanism to protect the circuit from operating until a correct access code has been entered. Such systems are described in U.S. Pat. Nos. 4,139,864 to Schulman and 4,267,578 to Vetter.
Each of the above protection schemes requires additional processing and/or uses additional circuitry that is dedicated to security and does not contribute to the basic functioning of the circuit. This increases the cost of circuit production and complicates the circuitry.
U.S. Pat. No. 4,799,096 to Koeppe uses doped implants to connect the sources and drains of different transistors to improve circuit reliability and testability, but the circuit function can be determined from the transistor arrangement. U.S. Pat. No. 5,138,197 to Kuwana connects different transistors in an address decoder array with doped implants, but circuit functions can be determined from clearly visible elements such as gate electrodes and circuit interconnects. Japanese patent publication 58-190064 to Sawase provides a metalization over a diffused source to block light from the source/substrate junction and thus reduce leakage current. While this tends to camouflage the source, the nature of the circuit can still be determined from its visible elements.
In related application Ser. No. 08/532,326, filed Sep. 22, 1995 by the present inventors, heavily doped implant interconnections that are difficult for a reverse engineer to detect are used to provide interconnections among the transistors of various types of logic cells, with the pattern of interconnections determining each cell's logic function. The transistors of the different cells are arranged in a common pattern and a uniform pattern of interconnections among transistors is provided for each cell; different logic functions are implemented by interrupting some of the interconnections with the addition of opposite conductivity channel stop implants. The channel stops are quite small, making the interrupted and thereby non-conductive interconnections appear the same to a reverse engineer as the conductive interconnections. CMOS digital circuits such as NAND and NOR gates are camouflaged so that they appear identical under an optical microscope. However, when all of the device layers on top of the bare semiconductor substrate have been removed by a reverse engineer and an etchant applied to the underlying substrate, the pattern of channel stops may be brought out by selective etching of the substrate. If an etchant is used which etches N and P type material at different rates (typically N-doped material will etch faster than P-doped), a height differential or "step" will be formed at the boundaries between the channel stop and the adjacent oppositely doped interconnection line. If they are large enough, such steps can be detected by either optical microscopes or SEMs, thereby revealing which interconnections have blocking channel stops and which are true conductive interconnections.