1. Field of the Invention
The present invention generally relates to exchanging packets of data on a bus between two devices and, more particularly to dynamic reordering of data sequentially received on multiple single-byte input paths to ensure bytes of the data are properly aligned when presented on a multi-byte interface.
2. Description of the Related Art
A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory, such as a cache shared between the processors cores, and peripheral interfaces, such as external bus interfaces, on a single chip to form a complete (or nearly complete) system. The external bus interface is often used to pass data in packets over an external bus between these systems and an external device, such as an external memory controller or graphics processing unit (GPU).
Oftentimes, the processor cores of a SOC may process data using multiple physically independent external data paths. These external data paths may be of different dimensions (e.g., a smaller byte size/bus width) than the internal bus utilized by the processor cores, with data on the multiple paths merged (or interleaved) onto the internal bus. Data transferred on these multiple paths can become out of alignment by the time they get to internal bus receivers due to different paths on a card containing the SOC and different analog clock-to-data alignment selection within the receivers.
Unfortunately, as the data transfer rate between devices increases with advancements in technology, this misalignment problem may be worsened, resulting in data carried on one path leading or lagging data on another path by one or more bytes. This misalignment can lead to incorrectly assembled data fed into the processor cores after the misaligned data on different paths is merged, which may have unpredictable results and possibly catastrophic effects.
Accordingly, what is needed are methods and apparatus for automatically aligning bytes of data received over multiple data paths.