Presently available microprocessor chips are wire-bonded into chip carriers. The pins of a chip carrier are wire bonded to bonding pads on the chip. The microprocessor circuits are also connected electrically to those pads. The wires which connect the pads to the pins contibute an indctance typically of 2-4 nano Henries (nH). Some of those wires are connected to the ground BUS in the microprocessor chip. When the output drivers of the microprocessor are operated to switch current which has accumulated on the ground and power BUSES, the associated inductance of the ground and power lead connection leads to a voltage difference between the chip carrier ground and power terminals on the one hand and the chip's internal ground on the other. The voltage difference is identified as ground and power BUS noise. This voltage appears in series with the voltage of the output drivers thereby confusing the logic levels represented by the output voltages.
Efforts to eliminate this ground and power BUS noise have not been particularly successful. In one particular effort, a central processor unit (CPU) was isolated from the external memory BUS by a separate interface chip. Moreover, the BUS was heavily loaded by a capacitance of about 450 picofarads. The interface chip required extra time for operation and considerably reduced operating speed (throughput). In order to obtain high throughput levels, the CPU must drive significant amounts of memory and interface chips directly.
In the future, this problem will become even more complicated. Sharing of chip input-output (I/O) ports with associated multiplexing will have to be curtailed and increased numbers of BUSES will have to be driven simultaneously. Moreover, each external BUS will have about 100-150 picofarads (pF) capacitance load. Under such demands, the only way to reduce noise appears to be to provide a large number of ground connections.
But a problem exists with respect to the number of ground connections (N.sub.G) which can be permitted while still keeping the power BUS noise below the MOS threshold voltage (V.sub.TH) of 0.5 V. In this connection, the following equation (1) must be satisfied in order to keep the ground of power BUS noise less than V.sub.TH : ##EQU1## where N.sub.T =total number of drivers switching simultaneously.
N.sub.G =total number of ground connections. PA0 L.sub.S =inductance per bonding wire (4NH). PA0 V.sub.DD =power supply voltage (5 V). PA0 V.sub.TH =MOS threshold voltage (0.5 V). PA0 C=capacitance of a single data bus wire (150 pF). PA0 T=time required for an output driver to switch.
The equation provides the absolute minimum number of ground connections required for an ideal triangular discharge current waveform. As a practical matter, the number must be larger by at least a factor of two. Specifically, the formula does not provide for internally generated current spikes or for process variation. An additional factor of at least two, and realistically four, is required to compensate for such spikes and variations. If the right side of equation (1) is multiplied by a factor of four, equation (1) reduces to: ##EQU2## where T is in nanoseconds (NS). If we assume T is a 1/2 machine cycle at 25 MHz and 100 drivers switched simultaneously, then EQU N.sub.G .gtoreq.24. (3)
If this many ground connections are not provided, the chip generates a noise voltage higher than the MOS threshold. As system performance improves, the number of drivers which switch simultaneously also will have to increase as will BUS capacitance. The resulting requirement on the minimum number of ground connections is forbidding.