There have been widely used video cameras and electronic cameras in recent years. These cameras include solid-state image sensors such as CCDs (Charge Coupled Devices) or CMOS (Complementary Metal Oxide Semiconductor) image sensors. Such solid-state image sensors each include an imaging block in which a plurality of photoelectric conversion blocks each configured by a photodiode are disposed in a two-dimensional array, and there are formed unit regions (unit pixels) each including the photodiode as a main functional part.
In such a CCD, a light beam incident on each unit pixel is photoelectrically converted by a photodiode into a signal charge, which is transferred to a floating diffusion (FD) block provided at an output block through a vertical CCD transfer register as well as through a horizontal CCD transfer register. Thereafter, in the CCD, a MOS transistor detects a variation in electric potential of the FD block, and the detected variation in electric potential is amplified and outputted as an imaging signal.
To the contrary, a CMOS image sensor includes in each unit pixel an FD block as well as various types of MOS transistors used for transfer, amplification, and the like, and accordingly does not need to transfer an electric charge. The CMOS image sensor is thus operable at a lower voltage in comparison to a CCD-type solid-state image sensor, and is suited to reduce the electric power consumption. The CMOS image sensor is also suited to reduce the size of the image sensor since complicated signal processing functions can be easily integrated in one chip. There have been many conventionally used CMOS image sensors in each of which a MOS transistor having the amplification function is disposed in each pixel and three transistors are included in one pixel cell due to the miniaturization thereof.
For the purpose of further miniaturization, there is adopted a configuration in which a plurality of pixels share a reset transistor and an amplifier transistor, although the reset transistor and the amplifier transistor have been conventionally provided for each pixel.
FIG. 9 shows a CMOS image sensor having a configuration in which a reset transistor and an amplifier transistor are shared by four pixels. A pixel array 916 includes four photodiodes 902, 904, 906, and 908 as well as four electric charge transfer gates 903, 905, 907, and 909 respectively disposed as illustrated in a shared pixel 901, so as to share a reset transistor 910 and an amplifier transistor 911.
FIG. 10 is a diagram showing the configuration of a shared pixel array. In this array, a pixel cell 1001 corresponds to the photodiode 902. Similarly, pixel cells 1002, 1003, and 1004 correspond to the photodiodes 904, 906, and 908, respectively (see Patent Document 1, for example).
Upon receiving light beams, signal charges (electrons) accumulated in the photodiode 102 are transferred to a floating diffusion (FD) block through the electric charge transfer gate 903 in accordance with readout pulses that are applied from a readout signal line Tx01 to a gate electrode of the electric charge transfer gate 903.
The FD block is connected to a gate electrode of the amplifier transistor 911, and a variation in electric potential of the FD block caused by the signal charges (electrons) is impedance-converted by the amplifier transistor 911 and is then outputted to a vertical signal line.
Readout circuits 913 are connected to a horizontal shift register 914 so as to be selected for each pixel clock and obtain a image output from a signal output “readout”. Thereafter, the reset transistor 910 resets the electric potential of the FD block so as to be equal to the electric potential of a power supply line PV in accordance with a vertical reset pulse that is applied from a vertical reset line Rx0 to a gate electrode thereof.
A vertical shift register 915 reads out signals of the photodiodes from the signal output “readout” while sequentially activating the readout signal lines Tx and the vertical reset lines Rx.
Further, a readout circuit block performs CDS operations with use of noise memories and signal memories respectively provided for columns, thereby achieving removal of FPN noise and kTC noise generated in a pixel block.
This configuration realizes a MOS solid-state image pickup device of high sensibility and low noise, and it is becoming possible to achieve digital still cameras to have image quality properties better than those of a digital still camera including a CCD.
Furthermore, increase in the number of pixels reduces the area for one pixel in a digital still camera, so that micromachining techniques are essentially required. Patent Document 1 describes in detail a circuit design having a configuration in which a reset transistor and an amplifier MOS transistor are shared by four pixels to increase an opening space of each photodiode.