The present invention relates to a signal handling processor and, in particular, a processor for enabling the decoding and execution of instructions through a pipeline system.
FIG. 6 is a block diagram of a conventional microprocessor. Like reference numerals are employed to designate like parts or elements throughout the specification and any further explanation is omitted for similar parts or elements above.
The microprocessor shown in FIG. 6 comprises a program counter (PC) 1, an instruction memory 2, an instruction decoder 3, a data memory 4, a register file 5, a calculation circuit 6, [such as an arithmetic logic unit (ALU)], an accumulator 7, and a flag register 8.
The program counter 1 outputs an address signal P, which is applied to an address signal input terminal of the instruction memory 2. The instruction memory 2 allows the reading of an instruction Q stored in an address corresponding to the address signal P and writing of the instruction Q to an instruction register IR (not shown).
The instruction Q stored in the instruction register IR is applied to an instruction input terminal of the instruction decoder 3. The instruction decoder 3 decodes the content of the instruction and applies control signals g, h, i, j and k corresponding to the instruction Q to control terminals of the data memory 4, the register file 5, the calculation circuit 6, the program counter 1 and the instruction memory 2, respectively.
The data input and output terminals of the data memory 4, the register file 5 and the calculation circuit 6 are connected to a data bus. Data D is transferred between the data memory 4, the register file 5 and the calculation circuit 6 via the data bus. A system clock signal .phi. is applied to the clock input terminals of the program counter 1, the instruction memory 2, the data memory 4, the register file 5, the accumulator 7 and the flag register 8. The program counter 1, the instruction memory 2, the data memory 4, the register file 5, the accumulator 7 and the flag register 8 are operated in synchronism with a rise of a system clock signal .phi..
The calculation circuit 6 performs a calculation on data A' stored in the accumulator 7 and the data D supplied via the data bus. The result of the calculation is data A, which is stored in the accumulator 7. Any specific state, occurring upon the calculation, such as overflowing, sign of a result, zero as a result, and a carry output, is represented as a state signal of one bit called a "flag". The calculation circuit 6 collects such flags, and produces a flag signal F.
The flag register 8 stores the flag signal F. An output signal F' of the flag register 8 is applied as a calculated flag signal to a flag input terminal of the instruction decoder 3. The instruction decoder 3 utilizes the calculated flag signal F' as a branching condition of a conditional branch instruction. The conditional branch instruction is used when an instruction execution procedure is controlled.
The above-mentioned state signal is allocated to the calculated flag signal F' in the following way:
A third bit F3': an overflow flag V is "1" at an overflowing time and otherwise "0".
A second bit F2',: a signal flag S is "1" for a negative result and otherwise "0".
A first bit F1': a zero flag Z1 for a result of all 0s and otherwise "0".
A zero-th bit F0': a carry flag C is "1" at a carry from the most significant digit and otherwise "0".
For the instruction set of the processor, the following conditional branch instructions are prepared for controlling an instruction execution procedure in accordance with the respective flags.
JUMPV LABEL1; at F3'="1", branch to an address LABEL1
JUMPS LABEL1; at F2'="1", branch to an address LABEL1.
JUMPZ LABEL1; at F1'="1", branch to an address LABEL1.
JUMPC LABEL1; at F0'="1", branch to an address LABEL1.
In order to enhance the processing efficiency of the processor, a conventional technique is used for performing the instruction decode processing and instruction execute processing through a pipeline system. According to this technique, except for a first instruction reading step, a subsequent instruction reading and instruction executing step can be simultaneously effected. For this reason, a processor can achieve processing throughput about two times higher than a processor not using any pipeline system.
In such a processor using the pipeline system, the period in which an instruction described immediately before the conditional branch instruction is superimposed on the period in which the conditional branch instruction is decoded. It is, therefore, impossible, based on the instruction described immediately before the conditional branch instruction, to effect branching with the use of a content-varied flag.
The following is an example of a program with a combined calculation instruction and conditional branch instruction.
ADD A, R0; add the content of the register R0 to the accumulator's content A. PA1 NOP; not operated. PA1 JUMPV LABEL1; at an overflow flag F3'="1" branch to LABEL1.
For this exemplary program, at a first line the content of the register R0 at a zero-th of the register file 5 is applied to the input terminal of the calculation circuit (ALU) 6 via the data bus. The calculation circuit 6 adds the content in the register R0 and the content in the accumulator ACC 7 together and again stores the result of the addition into the accumulator 7.
At a second line, nothing is executed. This is a NOP (no operation) instruction, which is used for timing matching. Such an NOP instruction is included in an instruction set of most processors.
At a third line, detection is made to determine whether any overflowing occurs, and, if YES, a branch is made to LABEL1 address.
FIG. 7 shows a timing chart for executing the above-mentioned program with a calculation instruction and conditional branch instruction combined in a conventional processor using a pipeline system. This timing chart shows a time variation of an address signal P output from the program counter 1, an instruction Q held in the instruction requester IR, data D at the data bus, and a flag calculation signal F' held at the flag register 8. T represents a machine cycle.
As shown in FIG. 7, at a time T, an ADD instruction is read from an n address in the instruction memory 2 and written to the instruction register IR.
Then an ADD instruction is decoded and, at a time 2T, the content (R0) of the register R0 is read onto the data bus. Further, an NOP instruction is read from an n+1 address in the instruction memory 2 and written to the instruction register IR.
Subsequently, the content A' held in the accumulator 7 and data (R0) on the data bus are added together in the calculation circuit 6. At a time 3T, the result of the addition is written to the accumulator 7 and a flag F is written to the flag register 8. The flag register 8 outputs the flag signal F as a calculated flag signal F'. And at the time 3T a JUMPV instruction is read out from n+2 address in the instruction memory 2 and written to the instruction register IR.
Then the JUMPV instruction is decoded. At a time 4T, the instruction decoder 3 decides, with the use of an overflow flag F3' output from the flag register, whether or not any overflowing occurs. If YES, using the control signal j, the instruction decoder 3 causes an address signal, which is output from the program counter 1, to vary.
As evident from the above, the time 3T at which an overflow flag F3' is varied by the addition instruction is 2 machine cycles after the time T at which the ADD instruction is read out as the instruction Q. Therefore, if the conditional branch instruction is described immediately after the addition instruction, the output flag signal F' of the flag register 8 varies after the conditional branch instruction has been decoded by the instruction decoder 3. As a result, it becomes impossible to use, as a branching condition, the variation of a flag resulting from the addition instruction. In order to prevent this, the NOP instruction is inserted so that a result of the ADD instruction can be used as a condition of the JUMPV instruction.
In the conventional processor, in order to use the result of the addition instruction as the condition of the branch instruction, it is necessary to insert the NOP instruction as described above, thereby lowering the processing efficiency. In the case where, the conditional branch is executed in the repeating loop, its adverse effect appears prominent. As a result, the actual execution speed of the program becomes slower and an unexpected error actually occurs.