The present invention relates generally to memory devices, and more particularly to method and circuit for trigger column select line for write operations.
Memory devices are integral to a computer system, and to many electronic circuits. Constant improvements in the operating speed and computing power of a central processing unit (CPU) enables operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and data lines within memory devices. However, with regard to memory speed, the access time for a memory device is generally governed by certain limitations. More particularly, memory speed is, to a large extent, dictated by the charge and discharge rates of parasitic capacitance on memory data lines.
Conventionally, a memory access to write a data bit is performed by: (1) activating a row control line for the required memory location; (2) receiving a write command and the associated data bit; (3) activating a column select line; and (4) providing the data bit to the memory cell. Conventionally, these steps are performed in sequential order for each data bit being stored. Furthermore, memory operations are typically performed on one data bit per clock cycle. This is generally referred to as a single data rate (SDR) operation. Also, for a write operation, the write command and the associated data bit are typically received concurrently.
The process described above typically defines the access time of a memory device (i.e., to write a data bit to memory). The access time determines the maximum data transfer rate for a memory device. Traditionally, improvement in the access time of a memory write is limited, in part, to the time it takes to charge the sense line. Incremental improvements can be made to decrease the charge time by reducing the geometry of the device, thereby reducing the parasitic effects.
Large improvement in the data storage rate can be achieved by performing a (substantially) concurrent loading of two data bits to memory. This is generally referred to as a "prefetch" operation. The prefetch operation facilitates a double data rate (DDR) operation wherein two data bits are provided to memory in one clock cycle (i.e., on both the rising and falling edges of a clock signal). A DDR write is achieved by (serially) receiving two data bits, usually from one device input/output (I/O) pin, aligning the data bits, and performing a (concurrent) double write to memory.
In a DDR write operation, unlike a SDR write operation, the write command and the associated data bits are typically not received concurrently. For example, the input data bits may be received one or more clock cycles after the write command is received. Furthermore, the data and write command may not be referenced to a common (e.g., clock) signal. For example, the write command and the address signals for a DDR write may be referenced to the rising edge of the clock signal (i.e., similar to a SDR write operation) but the data may be referenced to a data strobe input signal (DQS). Therefore, techniques are needed to properly activate (or trigger or select) the column select line for write operations in a DDR or multi-data rate operation.