1. Field of the Invention
This invention relates to semiconductors, and more particularly, to a new structure for semiconductor read-only memory (ROM) and a method of fabricating the same.
2. Description of Related Art
As computers become more powerful in performance, memories with very fast access speed and large storage capacity are in great demand. In computer systems, two major types of memories are used: ROM (read-only memory) and RAM (random-access memory). The ROM is used for permanent storage of repeatedly used program code and data. During computer operation, data can only be read from the ROM, whereas data can be read from and written into the RAM. There are various types of ROMs such as mask ROM, PROM (programmable ROM), EPROM (erasable programmable ROM), and EEPROM (electrically erasable and programmable ROM), to name a few.
In addition, a new type of EEPROM with a very fast access speed, called flash memory, has been developed by Intel Corporation of America. Flash memory is substantially identical in structure with conventional EEPROMs except that the erasure operation of the flash memory is carried out in a block-by-block manner rather than a bit-by-bit manner. The flash memory is therefore reprogrammed more quickly than the conventional EEPROMs, making it highly cost-effective to use and manufacture.
For a particular type of ROM, the various units supplied to the customers are typically identical in semiconductor structure except for the different data stored therein. Therefore, the ROM devices are customarily fabricated up to the stage where they are ready for data programming. The semi-finished products are then stocked in inventories to await customer orders. When a customer order is received, the data specified by the customer are then programmed into the semi-finished ROM devices by performing the so-called mask programming process. This procedure is now a standard practice in the semiconductor industry for the manufacture of ROMs.
Conventional ROM devices are typically based on MOS transistors serving as memory cells. Whether a certain memory cell stores the data value 0 or 1 is dependent on whether or not the channel region of the associated MOS transistor is doped with impurities. If doped, the channel region will be increased in threshold voltage, thus setting the associated MOS transistor to a permanently OFF state, representing the storage of a first data value, for example 0, into the memory cell. On the other hand, if not doped, the channel region will have a low threshold voltage that allows the associated MOS transistor to be set to a permanently ON state, representing the storage of a second data value, for example 1, into the memory cell. The ROM device access operation is carried out through word lines and bit lines that are interconnected to the memory cells in the ROM device
To provide a more detailed description of the prior art, the structure of a conventional ROM device and the method of fabricating the same are illustratively depicted in the following with reference to FIGS. 1A-1E.
As shown in the top view of FIG. 1A, the conventional ROM device is constructed on a semiconductor substrate 100, such as a P-type silicon substrate. The substrate 100 is formed with a plurality of parallel-spaced N+ source/drain regions 106 extending in a first direction 110, which serve as a plurality of buried bit lines for the ROM device. Further, a gate oxide layer 102 (see FIG. 1B) is formed over the substrate 100, covering all of the buried bit line 106. Next, a plurality of parallel-spaced gate regions 112a is formed over the gate oxide layer 102, extending in a second direction 120. Preferably, the second direction 120 is perpendicular to the first direction 110. These gate regions 112a serve as word lines for the ROM device. The gate regions 112a intercross the buried bit lines 106 at a plurality of intersections. For each segment of the gate regions 112a between one neighboring pair of these intersections, a channel region is defined thereunder, as indicated by the region enclosed by a dashed box labeled with the reference numeral 107 in FIG. 1A. Each channel region 107 is associated with one memory cell of the ROM device. For each memory cell, whether it stores a data value 0 or 1 is dependent on whether or not the associated channel region 107 is doped with P-type impurities to vary the threshold voltage thereof. The ion-implantation process used for this purpose is customarily referred to as a code implantation process.
Detailed process steps taken to fabricate the foregoing ROM device are depicted in the following with reference to FIGS. 1B-1E.
FIG. 1B shows the case where the substrate 100 is P-type and the buried bit lines 106 (N+ source/drain regions) in the substrate 100 are formed by doping a high concentration of N-type impurities into predefined regions in the substrate 100. One channel region 107 is formed between each neighboring pair of the buried bit lines 106.
One drawback to this structure is that, when the ROM device is scaled down for high integration, the buried bit lines 106 are scaled down as well, and thus have increased electrical resistance that slows the speed of accessing the ROM device. There are two solutions to increase the conductivity of the buried bit lines 106: one is to increase the concentration of the impurity ions doped therein; and the other is to form the buried bit lines 106 at a greater depth in the substrate 100. These two solutions, however, would make neighboring buried bit lines highly susceptible to punchthrough. Therefore, the channel region 107 between each neighboring pair of the bit lines 106 should be wide enough to prevent punchthrough.
After the buried bit lines 106 are formed, the next step is to form the gate oxide layer 102 through either a thermal oxidation process or a CVD (chemical-vapor deposition) process. Subsequently, a plurality of parallel-spaced polysilicon layers 104 extending in the second direction 120 are formed over the gate oxide layer 102 to a thickness of 1,000-4,000 xc3x85 (angstrom).
FIG. 1C illustrates the subsequent step, in which a conductive layer 112 is deposited over the entire top surface of the wafer, covering all of the polysilicon layers 104 and the buried bit lines 106. This conductive layer 112 is preferably formed from tungsten silicide (WSix)
FIG. 1D illustrates the subsequent step, in which a photolithographic and etching process is performed on the wafer so as to etch away selected portions of the WSix conductive layer 112 until the surface of the gate oxide layer 102 is exposed, with the remaining portions being laid over the underlying polysilicon layers 104. These remaining portions of the WSix conductive layer 112 then serve as a plurality of parallel-spaced word lines 112a extending in the second direction 120, perpendicular to the first direction 110.
FIG. 1E illustrates the subsequent step, in which sidewall spacers 114 are formed on the sidewalls of the word lines 112a. These sidewall spacers 114 can be formed by, for example, first depositing an insulating layer (not shown) through a CVD process, and then performing an anisotropic etch-back process on the insulating layer (not shown) until the top surface of the gate oxide layer 102 is exposed. The remaining portions then serve as the sidewall spacers 114. After this, a dielectric layer (not shown) is formed over the wafer. This completes the fabrication of the main structure of the ROM device.
Still one drawback to the foregoing ROM device, however, is that when the ROM device is further scaled down for higher integration, the smaller word lines have increased resistance, thus slowing the access speed to the ROM device. Moreover, when the channel regions between the buried bit lines are too small, neighboring buried bit lines become more susceptible to punchthrough. The downsizing of the ROM device is thus limited to an unsatisfactory level.
It is therefore an objective of the present invention to provide a new structure for a ROM device and a method of fabricating the same, which can make the bit pitch between neighboring bit lines greater than that in the prior art. This allows the channel regions between the same to be longer than those in the prior art, allowing the ROM device to be made with higher integration in a cost-effective process with reduced cycle time.
In accordance with the foregoing and other objectives of the present invention, a new structure for a ROM device and a method of fabricating the same are provided.
The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI (shallow-trench isolation) structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines. Subsequently, the dielectric isolation layers in all of the STI structures in the cell region are removed, leaving a plurality of empty trenches behind. A conformal insulating layer and a conductive layer are then successively formed over the wafer, and the conductive layer is further selectively removed to form a word line in the cell region and a gate in the peripheral region. In the code implantation process, selected channel regions between the buried bit lines are doped with impurities for code implantation of data into the ROM device.