Referring to FIG. 1, a conventional system 10 with several components A–D is shown. The system 10 transfers data on a shared bus 20. A path 22a illustrates data moving from a transmitter (i.e., component A) to a receiver (i.e., component B). The components A–D can behave as either a transmitter or a receiver, but not both simultaneously. For example, a path 22b illustrates data moving from a transmitter (i.e., component B) to a receiver (i.e., component A). The paths 22c and 22d show similar configurations of the component C and the component D. There may be a period of time for a particular one of the components A–D to switch from being a receiver to transmitter, and vice versa. That period of time is measured in idle cycles of a system clock.
For example, a bus structure can multiplex addresses and a data over the bus 20. With such an implementation, the component A can read from the component B by first sending an address over the bus 20. The component B receives the address, decodes the address information, fetches the requested data, and sends the requested data back on the bus 20. The sequence of operations described creates the bus idle cycles where other components do not have access to the bus 20.
During the bus idle cycles, if the component C needs to read from the component D, the bus 20 is not available. In addition, the bus 20 normally only runs at one clock frequency. All of the components A–D need to interface to the bus 20 at the frequency of the bus 20. Conventional solutions resolve such multiple bus requests by waiting for the bus 20 to be available by adding idle cycles to separate the bus activity.
It would be desirable to implement a bus that implements simultaneous data traffic in opposing directions without imposing idle cycles.