The present invention relates to automated tools for integrated circuit design. In particular, the present invention relates to modeling tools for calculating, measuring or predicting electrical characteristics of interconnect wiring in an integrated circuit.
As integrated circuit (xe2x80x9cICxe2x80x9d) technology advances, integrated circuits are made at higher integration levels and to run at higher clock speeds. In fact, at sub-micron feature sizes, the signal delay associated with a signal path is dominated by metal interconnections, or xe2x80x9clinesxe2x80x9d, which are used to connect the active devices. For example, in gate-arrays and other routed designs with relatively long lines, the signal delays due to wiring (xe2x80x9cline delaysxe2x80x9d) dominate signal delays between active devices at dimensions just below 1.0 micron. For more densely packed standard-cell designs, line delays dominate at below 0.6 micron. Unlike the signal delay in the active device itself, which is typically well-characterized, and can be read from a device library, a line delay depends on the structures in the vicinity of the line, and thus cannot be accurately modeled or calculated until after all circuit elements associated with the signal path of interest are placed and routed. Often, the accurate modeling of parasitic effects (e.g., parasitic capacitances) associated with these lines is critical to a successful integrated circuit design.
However, accurate modeling of parasitic impedances of lines is a complex problem, requiring extensive knowledge in the diverse areas of device physics, process technology and electromagnetic field theory. Further, to be of practical value, an accurate model of parasitic impedances must be made both readily available to the integrated circuit designer in his/her normal course of work, and easily incorporated in the integrated circuit under design.
The tasks (xe2x80x9cdesign methodologyxe2x80x9d) of an integrated circuit designer can be summarized by the design flow chart 100 shown in FIG. 1. As shown in FIG. 1, at step 101, the designer uses a high level hardware description language (e.g. Verilog or VHDL) to specify the functional and logic designs of the integrated circuit. Then, at step 102, the logic circuit is synthesized to a logic gate level circuit description, using an automatic logic synthesis tool. Typically, at the next step (i.e., step 103), a preliminary timing analysis on the logic gate level circuit is performed. Upon completing various verification steps (not shown) to ascertain the correctness of the logic gate level circuit and satisfying all timing constraints at the gross level, the physical design step (i.e. step 104) is carried out.
During physical design step 104, which is illustrated in further detail by the flowchart of FIG. 2, the logic gate level circuit description of step 102 is provided to a layout design system to be xe2x80x9cplacedxe2x80x9d and xe2x80x9croutedxe2x80x9d (step 201). Placing is the process by which the logic elements of the logic gate level circuit description are realized in the circuit elements of a physical implementation. Routing is the process by which lines interconnecting the circuit elements of the physical implementation are created. At step 202, estimates of the parasitic impedances of lines in the physical implementation are made (xe2x80x9cextractedxe2x80x9d) to form an interconnect delay model. The estimated parasitic impedances are then used, in step 203, to calculate signal delays resulting from these parasitic impedances. At step 204, a detailed timing analysis is then performed to verify that timing requirements are met in the physical implementation. If timing requirements are not met, the integrated circuit designer must return to step 201, i.e., to the layout design step, to make corrective modifications to the layout design. In fact, in some instances, the circuit designer may have to return to step 102, where the logic circuit is redesigned such that a circuit implementation meeting timing requirements may be re-synthesized. Steps 202-204 are then repeated as necessary. In designing a high-speed logic circuit, steps 201-204 are typically reiterated many times.
When the design is deemed to have met its timing requirements, the final verification step (i.e. step 105) is performed. In the final verification step, the layout design is checked for compliance with design rules, and an even more extensive timing analysis is also performed.
In the prior art, as the physical circuit elements are interconnected, most place and route systems generate estimates of line parasitic impedances to be used in subsequent timing simulations. These estimates of parasitic impedances are typically based on a simplistic model which often takes into account only the dimensions of individual lines. The parasitic impedances due to the surrounding structures are compensated by a conservative xe2x80x9cguard bandxe2x80x9d. However, as integrated circuits go to successively higher levels of integration (i.e., smaller sizes and larger numbers of devices per chip) and use more layers of conductors, the simplistic model breaks down. In fact, the simplistic model is insufficient to allow accurate analysis of sub-micron designs, especially when estimating parasitic impedances in xe2x80x9ccriticalxe2x80x9d nets of the integrated circuit.
For an accurate analysis of parasitic impedances, Poisson""s equation and Maxwell""s equations can be solved for the space of interest using a 3-dimensional field solver. However, because both the computation and the input parameters are highly complex, 3-dimensional field solvers are difficult to set up, require significant amount of computational power, and their results are difficult to use. Typically, to achieve an accuracy that justifies the effort, values of relevant physical parameters of a fabrication process contemplated for implementing the design are required as input data to the 3-dimensional field solver. In addition, because the computation is so complex even for the analysis of a small portion of the integrated circuit, practical solutions require the surrounding lines of a space of interest be broken up by the user into small segments and be analyzed separately. The user must then collect and process the separate solutions of each analysis to be used in a subsequent delay calculation. As a result of its complexity, the 3-dimensional field solver approach cannot be extensively used with an existing design methodology, such as that illustrated in FIGS. 1 and 2.
Therefore, a need has arisen for a parasitic impedance calculation system and method that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for a method and system for extracting parasitic interconnect impedances, including inductance.
Accordingly, a novel parasitic extraction system is disclosed. In one embodiment, the parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library.
In another aspect of the present invention, a method for analyzing signal timing in a circuit is disclosed. The method includes receiving a description of a layout of the circuit, receiving an identification of a conductor to be analyzed in the circuit, tracing the conductor to be analyzed using the description of the layout of the circuit, determining parasitic impedance values including an inductance value for the conductor using an interconnect primitive library including a parameterized inductance function, creating a circuit description for the conductor using the parasitic impedance values, and performing a circuit timing simulation using the circuit description for the conductor.
An advantage of the present invention is that parasitic impedances, including inductance, may be extracted for an integrated circuit layout. Another advantage of the present invention is that more accurate modeling and timing analysis of the integrated circuit layout may be obtained.