1. Field of the Invention
The present invention relates to a method and apparatus for visually examining an array of objects disposed in a narrow gap and, more specifically, to such a method and apparatus wherein the array of objects to be visually examined are arranged to extend transversely of a small gap defined by parallel plates, one of which is light transmitting.
2. State of the Prior Art
As is well known, integrated circuit ("IC") packages conventionally are mounted on a substrate or circuit board, typically a printed circuit board ("PCB"), electrical connection being made between output leads of the IC package and corresponding connector pads, the latter formed as part of a wiring pattern on the PCB. As the trend continues toward large scale integration ("LSI") of such IC packages, the number of electrical connections which must be effected is increasing dramatically.
Currently, the most popular and most extensively employed packaging technology for conventional IC's is that known as DIP (dual inline package) and variations or equivalents thereof, wherein plural leads are formed so as to extend in generally parallel relationship from the parallel, longer side surfaces of the generally rectangluar IC package, transversely to the bottom surface of the DIP. Typically, in present usage, the largest number of leads formed on such an IC package or DIP, is 64; with current technology, it is difficult to contemplate that the number could be increased to any substantial extent, such as to 100 or more such leads.
Accordingly, there has been an effort to overcome the limitation in the maximum number of leads which are available for the conventional IC's, directed primarily to using the back surface of the package. An exemplary packaging technology directed to this configuration is disclosed in the Japanese patent application of the Provisional Publication Tokkaisho No. 59-151443, published August 29, 1984 (corresponding to U.S. Pat. application Ser. No. 579,127, filed February 10, 1984). In accordance with the technology disclosed in the referenced Japanese and corresponding U.S. patent applications, as many as 200 or more leads, or conductor pins, are secured to corresponding conductor pads formed on the back surface of the package, so as to extend in generally parallel relationship with one another downwardly from the back surface and in a substantially perpendicular relationship thereto. For convenience of terminology, the conductor pins are characterized as "vertical" in reference to a nominal "horizontal" orientation of the backside surface of the package. The IC package then is placed on a circuit board such that the free ends, or tips, of the conductor pins contact corresponding conductor pads associated with a wiring pattern formed on the circuit board, the pins then being connected to the pads by soldering. This type of packaging technology advantageously permits increasing the packing density of IC's on a circuit board.
Circuit boards having IC's mounted thereon, sometimes referred to as "cards," generally are subjected to a visual inspection of the condition of the soldered connections between each of the pins and the corresponding pads, prior to being subjected to functional electrical tests. The visual inspection is important to eliminate latent defects, or faults of the cards which may occur due to poor, or defective, soldered connections, which can result in faulty operation which otherwise might not become apparent until operation of system incorporating the cards in field testing.
The conventional visual inspection procedure for examining the condition of the soldered connections, however, is not applicable to cards comprising IC's fabricated and mounted on circuit boards in accordance with the packaging technology disclosed in the referenced patent applications. The reason is that the soldered joints or connections are hidden in the small gap between the package and the PCB on which it is mounted, and thus cannot be observed directly, either from the top side (i.e., through the package itself) or from the backside of the circuit board (i.e., the surface of the PCB opposite that on which the package is mounted). By contrast, in the case of cards comprising conventional IC's of the DIP type, for example, the condition of the soldered connections can be examined readily by observing the corresponding through holes on the back surface of the card. Accordingly, it is crucial to the practical use of IC's, based on the packaging technology disclosed in the referenced applications, that a new method of visual examination be provided to examine the condition of the soldered connections of the connecting pins and the respective, corresponding pads.