1 Field of the Invention
The present invention relates to a logic circuit for a dynamic D-flip-flop, which uses complementary insulated grid field effect transistors.
2. Prior Art and Technical Considerations
Dynamic D-flip-flops are frequently used in electronics because, among other things, they are convenient to use in the production of dynamic shift registers.
The function of, as well as many types of dynamic, D-flip-flop circuits are well known. However, no existing embodiment of such circuitry guarantees the avoidance of operational failure with a minimum number of transistors and without using delay elements such as capacitors. One of the most elaborate circuits known thus far, disclosed in the IEEE Journal of Solid State Circuits vol. Sc-8 no. 6, Dec. 1973, under the title "Clocked CMOS Calculator Circuitry", does not satisfy all known applications for dynamic D-flip flops. In spite of the fact that this circuit has only ten transistors. In fact, this circuitry requires a clock signal H both in its true H form and also in a complementary H form. This is disadvantageous, because of area or space requirements when this circuit is integrated, power consumption when the high frequency signals H and H are applied. From an operational aspect this circuit cannot be looped as a dynamic divider, as opposed to a true dynamic D-flipflop. Accordingly, this circuit can function only as a shift register element.