This invention relates generally to logic level translators and more particularly, it relates to a logic translator device for converting ECL logic level signals to TTL logic level signals which has an active pull-down circuit, a high level voltage clamping circuit, and a ground bounce protection circuit so as to provide a higher speed of operation with minimal power dissipation and a significant reduction in ground bounce noise.
As is generally well known in the art, various types of digital logic circuits are widely used in the area of computer data processing systems in different parts of the processing system. In order to transfer data from one part of the processing system utilizing one logic type (i.e.. ECL) of integrated circuit devices to another part utilizing another logic type (i.e.. TTL) of integrated circuit devices, there is often required a translation from the one logic type to the other logic type. Since many of these processing systems are designed with both ECL and TTL logic circuits due to their superior switching speeds, there has been encountered a need for interface circuits such as ECL-to-TTL and TTL-to-ECL translators so that these two different types of logic circuits will be compatible with each other.
In FIG. 1, there is shown one such conventional translator which is known as an ECL-to-TTL translator 10 which provides an output capable of being either at an active high level or an active low level. The ECL-to-TTL translator typically uses first and second bipolar transistors connected in series between first and second power supply terminals. The first bipolar transistor T9 is coupled between the first power supply terminal and an output terminal 22, and the second bipolar transistor T4 is coupled between the output terminal and the second power supply terminal. In operation, the active high level is achieved at the output terminal by turning on the first bipolar transistor T9 and turning off the second bipolar transistor T4. On the other hand, the active low level can be obtained by turning off the first bipolar transistor T9 and turning on the second bipolar transistor T4. A high impedance tristate may be achieved by turning off both the first and second bipolar transistors through an enable gate (not shown).
The switching ON and OFF of the first and second bipolar transistors T9, T4 to realize the transitions on the output terminal causes sudden surges of current creating what is commonly known as current spikes or glitches. These current spikes or glitches will flow through the impedance and inductive components of power supply lines so as to cause inductive noise at internal power supply potential and ground potential nodes of the translator. In particular, when the second bipolar (pull-down) transistor is quickly turned ON a large instantaneous current cooperating with the line inductance to pull down the internal ground potential node A which is defined as "ground bounce noise". This ground bounce noise, if excessive, could affect the input signals of an internal logic circuit 16 which temporarily causes the output terminal 22 of the translator to change states, thereby resulting in an erroneous output.
It would therefore be desirable to provide an improved ECL-to-TTL translator which has a ground bounce protection circuit but yet has a greater switching speed with minimal power dissipation. The ECL-to-TTL translator of the present invention includes a ground bounce protection circuit coupled to a lower output transistor in the output stage for maintaining the same in its turned-off condition when the internal ground potential node is pulled down due to switching of the output terminal between a low logic level and a high logic level.