The recent information-oriented society has been remarkably developed. Along with this, small-sized, light-weight, high performance and high functional devices such as personal computers and portable telephones for public use are being developed and there is also a current need for an improvement in radio base stations, optical communication devices and relevant network devices such as servers and routers for industrial use irrespective of size. And, with an increase in the amount of information to be transferred, frequency of signals to be handled are becoming higher year by year and developments in high-speed processing and high-speed transfer technologies are being made. With regard to the packaging concerned, system-on-chip (SoC), system-in-package (SiP) and the like are being developed as new high-density packaging technologies in addition to the developments of high-speed and highly functional CPUs, DSPs and LSIs such as various memories. For this, as to substrates for mounted with semiconductor chips and mother boards, multilayer wiring boards on which fine wires (L/S; line/space of 30 μm/30 μm or less) are formed by buildup method have come to be used to cope with higher frequency, higher density wiring and higher functionality.
A substrate formed with fine wiring is obtained by forming the wiring by a subtractive method or a semi-additive method.
In a general process of forming the wiring using a subtractive method, an etching resist is formed on the surface of copper and then subjected to exposure to light and developed to form a resist pattern. Next, unnecessary copper is etched and the resist is peeled off to form the wiring.
In a general process of forming the wiring using a semi-additive method, a plating resist is formed on the surface of copper (seed layer) and then subjected to exposure to light and developed to form a resist pattern. Next, electroplating, peeling off the resist and etching are carried out to form the wiring.
Also, after the wiring is formed, a solder resist or a cover lay may be formed on the wiring to protect the wiring other than external connecting terminals, semiconductor chip connecting terminals and the like. In order to adjust the wiring size to those having a designed L/S width, it is necessary to form a resist pattern according to the design. However, there is the problem that in the formation of fine wiring having L/S of 30 μm/30 μm or less, it is difficult to obtain accuracy of a resist pattern by the influence of halation caused by the reflection of light on the shiny surface of copper when the resist is exposed to light.
Also, there is the problem that the adhesion between the surface of copper and the resist pattern is reduced with the result that the resist pattern is peeled off. There is also the problem that the adhesion between the wiring (copper) and the solder resist and between the wiring and the cover lay, on the other hand, is insufficiently obtained as the wiring is more fined. In order to solve these problems, it is therefore important to minimize the amount of dissolving copper when mat the surface of copper is treating to mat the copper surface for and to strengthen the adhesion between the surface of copper and the resist.
On the other hand, a buildup method multilayer wiring board is manufactured by repeatedly carrying out a layer insulating layer forming process and a wiring forming process alternately. In this production method, it is important to secure the adhesive strength between the wiring and an insulating resin and insulation reliability between the wires.
In order to satisfy the above characteristics (or demand), a method of treating the surface of copper as shown below is carried out conventionally.
Specifically, in this method, a rough shape of the order of micron is imparted to the surface of copper to mat the surface of copper and further, the adhesions between the surface of copper and the resist (for etching or soldering) and between the surface of copper and the insulating resin are obtained by an anchoring effect. Examples of the matting method include a method in which a rough shape of the order of micron is imparted to the surface of copper by using an aqueous solution containing a major agent containing an inorganic acid and a copper oxidant and an adjuvant agent containing at least one of azoles and at least one etching inhibitor (Japanese Patent Application Laid-Open No. 2000-282265) and a method in which continuous irregularities 1.5 to 5.0 μm in height are formed by micro etching and then chromate treatment and coupling agent treatment are carried out (Japanese Patent Application Laid-Open No. 9-246720).
There is also a method in which fine copper oxide needle crystals are provided to the surface of copper to form irregularities, thereby matting the surface of copper and obtaining the adhesion between the surface of copper and the resist or the insulating resin by an anchoring effect. There is, for example, a method in which the substrate is dipped at around 80° C. in an aqueous alkaline solution containing an oxidant such as sodium chlorite to form fine copper oxide needle crystals (Japanese Patent Application Publication No. 7-13304).
There is, besides the above methods, a method in which reducing treatment is carried out after irregularities are formed on the surface of copper by providing fine copper oxide needle crystals to the surface of copper to mat the surface of copper and also to obtain the adhesion between the surface of copper and the resist or the insulating resin by an anchoring effect. Examples of this method include a method in which the substrate is dipped at around 80° C. in an aqueous alkaline solution containing an oxidant such as sodium chlorite to provide fine needle crystals of copper oxide, and then the substrate is subjected to reducing treatment using an acidic solution prepared by mixing at least one of amineboranes with a boron type chemical to provide fine needle crystals of metal copper (Japanese Patent No. 2656622).