1. Field of the Invention
The present invention relates to the technology of generating an address signal for controlling a ROM circuit or a RAM circuit incorporated into a semiconductor integrated circuit device, more specifically to the technology of reducing power consumption in such a semiconductor integrated circuit device.
2. Description of the Related Art
As a conventional example, a conventional semiconductor integrated circuit device incorporating a ROM circuit and a circuit for controlling the ROM circuit will be explained with reference to FIG. 10 to FIG. 12.
FIG. 10 is a block diagram showing the configuration of such a conventional semiconductor integrated circuit device.
In FIG. 10, the semiconductor integrated circuit device incorporates a ROM circuit 1 and a control circuit 8 for controlling the ROM circuit 1. The ROM circuit 1 includes a memory cell array 2 where memory cells for storing data are arranged in an array, an address decoding circuit 3 for decoding an address signal 7 to be input from the external control circuit 8, and a data output circuit 4 for outputting the data.
The control circuit 8 includes an address generation circuit 9 for generating the address signal 7 based on a clock 11 to be input from the outside and a data processing circuit 10 for processing a data output signal 6 to be output from the data output circuit 4 in the ROM circuit 1.
The number of bits of the data output signal 6 is determined by the configuration of the memory cell array 2. For example, when the minimum unit of memory is a byte (8 bits) unit, the data output signal 6 has 8 bits (n=8, D7 to D0), whereas when the minimum unit of memory is a word (16 bits) unit, the data output signal 6 has 16 bits (n=16, D15 to D0). Furthermore, the number of bits of the address signal 7 is determined by the memory capacity of the memory cell array 2. For example, when the minimum unit of memory is the byte unit and the memory capacity is 1 K byte, the address signal 7 will have 10 bits (m=10, A9 to A0), whereas for memory capacity of 64 K bytes, the address signal 7 will have 16 bits (m=16, A15 to A0).
When the control circuit 8 reads out data from the ROM circuit 1, the control circuit 8 outputs a CS signal (chip select signal) 12 showing that the ROM circuit 1 is selected and the address signal 7. The address signal 7 is input to the address decoding circuit 3 in the ROM circuit 1 and converted into a word line 5 that selects a specific address in the memory cell array 2. Data of the specific address in the memory cell array 2 shown by the word line 5 are output through the data output circuit 4. The data output signal 6 is input to the data processing circuit 10 in the control circuit 8, where processing is performed in accordance with the data.
Here, timing of the CS signal 12, the address signal 7 and the data output signal 6 will be explained with reference to FIG. 11A and FIG. 11B.
FIG. 11A shows signal timing when the control circuit 8 reads out data only once from the ROM circuit 1. In FIG. 11A, first, the data processing circuit 10 in the control circuit 8 outputs the CS signal 12, and the address generation circuit 9 outputs the address signal 7. During a period in which the CS signal 12 is in the logic “H” level (ROM selective period), the ROM circuit 1 judges that the input address signal 7 is a valid address and outputs valid data to the data processing circuit 10 in the control circuit 8.
Furthermore, FIG. 11B shows signal timing when the control circuit 8 reads out data continuously from the ROM circuit 1. In FIG. 11B, once the CS signal 12 reaches the logic “H” level, the logic “H” level is maintained during a period in which data are read out continuously. The address signal 7 is incremented every time data are read out from the ROM circuit 1 (that is, for each cycle). FIG. 11B shows the timing of change of only four low-order bits (A3 to A0). As an example, the four low-order bits (A3 to A0) in the address signal change from 1111→0000→0001→0010. Valid data corresponding to these address signals are output to the data processing circuit 10 in the control circuit 8 in a sequential order.
Here, a period during which the CS signal 12 is in the logic “H” level is determined to be the ROM selective period, whereas a period during which the CS signal 12 is in the logic “L” level is determined to be a ROM non-selective period, but the polarity is optional and depends on the ROM circuit 1.
Next, the address generation circuit 9 in the control circuit 8 will be explained further with reference to FIG. 12A and FIG. 12B. FIG. 12A is a block diagram showing the configuration of the address generation circuit 9, and FIG. 12B is a timing chart of the address signal 7 with respect to the clock 11. In addition, only four low-order bits of A3 to A0 are shown as examples as the address signal 7 in FIG. 12B.
In FIG. 12A, the address generation circuit 9 includes a counter circuit 16 that divides the clock 11 entering from the outside. When the address signal 7 has m bits (m is an integer), the number of stages in the counter circuit 16 is m. The clock 11 is divided by ½ into a signal A0, divided by (½)2 (=¼) into a signal A1, divided by (½)3 (=⅛) into a signal A2, divided by (½)4 (= 1/16) into a signal A3 and divided further by ½ in a sequential order until it reaches a signal of A (m−1), which is a signal divided by (½)m. These signals respectively are output through an output buffer 17.
As shown in FIG. 12B, the counter circuit 16 performs a count-up operation at the trailing edge of the clock 11, so that each address signal changes. In addition, it is also possible to count at the leading edge of the clock 11.
However, in the conventional semiconductor integrated circuit device as described above, when data are read out continuously from the ROM circuit 1, the probability that the address signal 7 changes becomes approximately 50%. Thus, there was a problem that current consumed in the address decoding circuit 3 of the ROM circuit 1 and in the address generation circuit 9 of the control circuit 8 is increased.
This aspect will be explained with reference to FIG. 13, FIG. 14, FIG. 16A, FIG. 15B, FIG. 15C and FIG. 15D.
FIG. 13 is a transition table for the address signal 7 in the address generation circuit 9 of FIG. 12A. Here, only four low-order bits of A3 to A0 are shown as examples as the address signal 7. In FIG. 13, when the address signal 7 changes from 0000 to 0001, the number of changing bits is 1 since only the lowest-order bit A0 has changed from 0 to 1. When the address signal 7 changes from 0111 to 1000, the number of changing bits is 4 since all the bits have changed. Furthermore, with respect to the state of 0000 in the first line of FIG. 13, the number of changing bits also is 4 since the prior state is 1111.
Therefore, when data are read out continuously from the ROM circuit 1, the average number of changing bits of the address signal during 16 cycles showing FIG. 13 becomes (4+1+2+1+3+1+2+1+4+1+2+1+3+1+2+1)/16=30/16≈2 bits.
Furthermore, the average probability of change becomes 2 bits/4 bits=50%. Also when the number of bits of the address signal 7 increases, the probability of change of the address signal 7 becomes 50% in average.
Next, the effects of such changes in the address signal on current consumption will be explained with reference to FIG. 14.
FIG. 14 is a circuit diagram showing a configuration example of the address decoding circuit 3 in the ROM circuit 1, in which only decoding circuits of the four low-order bits of A3 to A0 in the address signal 7 are shown. In FIG. 14, each signal A3 to A0 is controlled by the CS signal 12 showing that the ROM circuit 1 is selected and becomes effective when the CS signal 12 is in the logic “H” level.
When the CS signal 12 is in the logic “H” level, inverse signals and non-inverse signals of A3 to A0 are generated by a NAND circuit group 20 including 4 pieces of two-input NAND circuits and an inverter circuit group 30 including 4 pieces of inverter circuits. A NAND circuit group 40 serves as the decoding circuit for A1 and A0, and a NAND circuit group 41 serves as the decoding circuit for A3 and A2. The signals decoded in the NAND circuit groups 40, 41 are converted to 16 lines of decoding signals of A3 to A0 by a NOR circuit group 50 further including 16 pieces of two-input NOR circuits.
For example, a two-input NOR circuit 501 outputs the logic “H” level (that is, showing that this is selected, and other combinations are not selected) when A3 to A0 are all in the logic “L”, whereas a two-input NOR circuit 502 outputs the logic “H” level (that is, showing that this is selected, and other combinations are not selected) when A3 to A0 are all in the logic “H” level.
These 16 lines of signals are combined with the decoded results of higher-order address signals and finally become a signal of the word line 5.
Here, when the control circuit 8 reads out data continuously from the ROM circuit 1, the CS signal 12 is always in the logic “H” level. Therefore, along with changes in the address signal 7, signal inversions inevitably occur in the two-input NAND circuits of the NAND circuit group 20 described above and in the inverter circuits of the inverter circuit group 30 connected thereto, and current is consumed. Furthermore, signal inversions occur also in the NAND circuit groups 40, 41 and in the NOR circuit group 50 due to combinations of signals.
Furthermore, when a plurality of address signals change simultaneously, circuits that are not inverted statically may be inverted dynamically. This aspect will be explained with reference to FIG. 15.
FIG. 15A is a circuit diagram showing the decoding part related to A1 and A0 excerpted from the address decoding circuit 3 shown in FIG. 14. FIG. 15B, FIG. 15C and FIG. 15D respectively are timing charts of output signals from two-input NAND circuits 401 to 404, in which FIG. 15B shows a case where A1 and A0 change simultaneously, FIG. 15C shows a case where A1 changes later than A0, and FIG. 15D shows a case where A0 changes later than A1.
As shown in FIG. 15B, when A1 changes from 0 to 1 and A0 changes from 1 to 0 exactly at the same time, an output signal S402 from the two-input NAND circuit 402 only changes from 1 to 0, and an output signal S403 from the two-input NAND circuit 403 only changes from 0 to 1.
However, as shown in FIG. 15C and FIG. 15D, the two-input NAND circuits 401 and 404 also operate during a period in which either one of the two input signals is slightly delayed due to a difference in the wiring delay arising from the mask layout or a difference in the number of stages in the circuit from the address signal to the input, and current is consumed (this is generally called a hazard). In addition, the output signals (the output signal S401 in FIG. 15C, and the output signal S404 in FIG. 15D) are inverted twice during this slight delay.
In the case where the average probability of change in the address signal is as high as 50%, such hazards occur frequently inside the address decoding circuit 3. In this way, current consumption in the address decoding circuit 3 is increased. Usually, 20 to 30% of the current consumed in the ROM circuit 1 is consumed inside the address decoding circuit 3.
Furthermore, wiring for the address signal 7 installed between the control circuit 8 and the ROM circuit 1 tends to be long in distance due to the mask layout, and the load capacitance is increased. The higher the average probability of change in the address signal 7, the more current is consumed in the output buffer 17 (a total of m pieces) of the address generation circuit 9.