The present invention relates to non-volatile memory devices and methods for operating them. More particularly it relates to a NAND-type flash memory device capable of shortening a copy-back program time by changing an operation of a page buffer, and a method for operating the page buffer.
Recently, there has been increasing demand for semiconductor memory devices which do not require periodic refresh operations and are electrically programmable and erasable. A program operation writes data to the memory cells.
To achieve high integration of semiconductor memory devices, NAND-type flash memory devices have a plurality of memory cells that share a common connection. In other words, neighboring cells share a drain and source with each other. Unlike NOR-type flash memory cells, NAND-type flash memory cells are capable of reading out information sequentially.
NAND-type flash memory devices employ a page buffer in order to store large quantities of information or read out stored data within a short time. The page buffer receives a large amount of data from I/O (Input/Output) PAD to provide the data to a memory cell or store the data in the memory cell to output it. In general, page buffers are comprised of a single register so as to temporarily store data. Recently, NAND-type flash memory devices with a dual register have been introduced for the purpose of improving programming speed when programming a large amount of data.
Copy-back program operation refers to transmitting data stored in a defective cell to a normal cell utilizing page buffers.
FIG. 1 is a block diagram illustrating a copy-back program operation of a conventional NAND-type flash memory device.
With reference to FIG. 1, a conventional copy-back program operation is carried out as follows. Data stored in a defective cell is read out to a first latch unit 24 of a page buffer 20. The data read out from the first latch unit 24 is transmitted to a second latch unit 25. The transmitted data in the second latch unit 25 is programmed to another memory cell that presumably functions properly (or “normal cell”).
FIG. 2 is a block diagram illustrating program, read, and verification operations of a conventional NAND-type flash memory device.
With reference to FIG. 2, if the first latch unit 24 is selected from the first and second latch units 24 and 25, the second latch unit 25 is inactivated, and program operation 51 and read and verification operation 52 are carried out in the first latch unit 24. In contrast, if the second latch unit 25 is selected, the first latch unit 24 is inactivated, and program operation 61 and read, and verification operation 62 are carried out in the second latch unit 25.
In the above-mentioned copy-back program operation, there is a high probability that errors occur in transmitting data between the first latch unit 24 and the second latch unit 25. Accordingly, a timing margin may not be sufficiently secured during a copy-back program operation.