In computer architectures similar to the IBM Z/Architecture and its predecessors there are provisions made about access to computer storage. In this architecture, as defined in the IBM Z/Architecture Principles of Operation, Publication SA22-7832-00, numerous instructions exist that have one or more data operands that are longer than eight bytes (the basic operand length processed from the cache in the execution units). For each of these instructions as defined in the architecture there is a description of the storage rules. It is also common place in the computer processor or microprocessor that implement this architecture to have a cache storage with data organized on line boundaries.
To prevent system deadlocks in multiprocessing configurations the processor cache can not hold a cache line for the duration of instruction execution of instructions that take many cycles to execute. As a result there are cases where even if the processor units are still actively fetching data from this cache line the cache must release this line to another processor or processors in the system. When the line has been released to another processor, this other processor may update part or all of the line. This architecture allows for this behavior with some storage access rules. The architecture does not specify at what point in the operand for a given instruction execution that the update is detected. The architecture does specify that at what ever point the update to the operand data has been detected, all data for that operand prior to that point must be old data and all data after that point must be new data. The architecture does not allow access to old data for that operand data past a point in the operand where new data has been used.
The size of the unit of storage that an update to operand data must be detected in is dependent on the instruction. The size may be as small as one byte or as large as eight bytes. In U.S. Pat. No. 5,185,871 (owned by the assignee as the subject application) entitled “Coordination of Out-Of-Sequence Fetching Between Multiple Processors Using Re-execution of Instructions” discloses a processor that executes instructions out of order and can cancel any instruction right up to the point where the instruction can reach completion, the point at which the instruction's results are committed. U.S. Pat. No. 5,185,871 discloses that the cache monitors invalidates against lines in the cache and if data from one of those lines is being used by the cache it is reported to the processor and the entire instruction is canceled and re-executed. In this case, data is fetched again from the start of the operand. In this scheme, all of the data from a given line will always be from the same instant copy of the data.
However, it is contemplated in a future processor, for example a zSeries processor, to execute instructions in program order with an out of order operand fetch. This type of processor can not abort execution of an instruction once the instruction has started execution unless the entire contents of the processor including all cache contents are cleared and all architected state is restored from a protected check point copy, which is called a recovery action. In this type of processor this action is called processor recovery.
In normal program execution on a multiprocessor computer system it is likely to have data that has been fetched that will need to be invalidated. It is also likely that such invalidated data would be fetched out of order for instructions with long data operands. Furthermore, it is unacceptable processor performance to undergo a processor recovery action to deal with this.
Thus a solution is desirable that allows the instruction with long operands to continue execution and comply with the storage access rules without undergoing a processor recovery action.