FIG. 1 shows circuitry for controlling a flash memory cell. The memory cell 2 comprises a single transistor 4, having a control gate CG and a floating gate FG, a source S and a drain D. The source S is connected to a node 10, itself connected to a source voltage switch 14, which permits the source S to be connected either to a ground voltage V.sub.GND, or to a programming voltage, V.sub.pp, according to a signal applied to an erase control input 28. The drain D of transistor 4 is connected to a bit line 6, itself connected to a bit line switch 31, which permits bit line 6 to be connected either to a sense amplifier circuit 29 or to a programmable load circuit 32, according to a select control signal applied to a select input 21. The programmable load circuit 32 receives as input, load control signals 38. The sense amplifier circuit 29 provides an output to a data line 23. The control gate of transistor 4 is connected via word line 8 to a gate voltage switch 12. This gate voltage switch permits the control gate CG to be connected to the ground voltage V.sub.GND, the programming voltage V.sub.pp, or a supply voltage V.sub.cc, according to control signals applied to program and erase control inputs 30, 28 respectively. V'.sub.cc, is 5 V for a memory device operating with a 5 V supply, and about 5 V for a memory device operating with a 3 V supply.
The flash memory cell 2 has three modes of operation. In program mode, the floating gate FG is negatively charged, the transistor 4 becomes less conductive, and a 0 is considered to be written to the cell. In erase mode, the floating gate FG is discharged, the transistor 4 becomes more conductive. A 1 is then considered to have been written to the cell. In read mode, suitable voltages are applied to transistor 4 such that a relatively low current will flow when a 0 is written into the cell, and a relatively high current will flow when a 1 is written into the cell. The contents of each memory cell may thus be determined.
To select program mode, the program control signal 30 is set, causing the word line 8 and the control gate CG to be connected to the program voltage V.sub.pp. The erase control signal 28 is not set, and the source S of transistor 4 is connected to the ground voltage V.sub.GND by source voltage switch 14. The select control signal 21 is set so as to connect the bit line 6 to the programmable load circuit 32. The load control signals 38 are set to place the drain D of transistor 4 at about 5 V.
This combination of bias voltages on transistor 4 causes the floating gate FG to become negatively charged. This changes the apparent threshold of the transistor, making it less conductive for a given control gate voltage. The charge accumulates during the time that the program control signal is set. A common method of achieving programming is to apply several pulses to the program control signal (program pulses), with a verify step in between each of them, to detect when the cell in question has been properly programmed.
In the erase mode, the erase control signal 28 is set to connect the control gate CG of the transistor 4 to the ground voltage V.sub.GND, by means of gate voltage switch 12 and wordline 8. The source S is connected to the program voltage V.sub.pp by the source voltage switch 14 as controlled by the erase control signal 28. The select control signal 21 is set to control the bit line switch 31 to allow the bit line 6 to float at around 1 V. With these bias conditions, the charge on the floating gate FG reduces, the amount of charge removed depending on the duration of the erase control signal. This reduction in stored charge makes the cell more conductive. After a sufficient time, a 1 is written into the cell. A common way of achieving this erasure is to apply several pulses on the erase signal 28 (erase pulses), with a verify signal between each one to determine whether the erase is complete.
In read mode, neither the erase control signal 28 nor the program control signal 30 are active. This causes the control gate CG and the wordline 8 to be connected to the supply voltage V'.sub.cc by the gate voltage switch 12. The source of the transistor 4 is connected to ground V.sub.GND by the source voltage switch 14. Bit line 6 is connected to the sense amplifier circuit 29, which biases the bit line 6 to around 1 V. The amount of current flowing through the transistor 4 depends on its programmed or erased state. An erased cell will allow substantially more current to flow than a programmed cell. The sense amplifier 29 detects the level of the current through transistor 4, and places the bit line 23 in a logic state indicative of the state of the cell 2.
In a flash memory device, many cells such as that shown in FIG. 1 are connected together, and provided with addressing circuitry. Each cell, however, functions as described above, in its three possible states.
Within such circuits, it is necessary to measure several different time delays, each with equal accuracy. In the example of a flash EPROM memory circuit, very short time periods of the order of 10 .mu.s may be needed for timing program pulses, whereas much longer periods, of the order of 10 ms may be needed for timing erase pulses.
A known circuit for timing both long and short time periods uses a linear feedback shift register (LFSR) in an autonomous mode, whereby the LFSR has no data inputs, and is supplied only with a clock signal. A LFSR is a shift register composed of a series of storage elements, such as D-type latches, wherein the outputs of certain latches are combined in a linear manner, and the resulting signal is applied to the input of a first latch.
The circuit is very similar to a normal shift register, except that a certain `linear` function is introduced by including a linear element, for example an exclusive-OR or exclusive-NOR gate, in the circuit. Such gates pass or invert the output (Q) of one latch to the input (D) of the next depending on the output (Q) of another of the latches.
Linear feedback shift registers are discussed in "Digital Systems Testing and Testable Design", by Abramovici, Breuer and Friedman, Computer Science Press, 1990; "Shift Register Sequences", by S. W. Golomb, Aegean Park Press, 1982, and "Error Correcting Codes", Peterson & Weldon, MIT Press, 1972.
Typically, such LFSR timers are made from a loop comprising a series of latches, supplied with a clock signal input and no data input. This is called the autonomous mode of operation. By supplying a clock signal of sufficiently high frequency, for example 1 MHz, and detecting a certain combination of outputs of the latches, a range of periods such as described may be timed.
With a 1 MHz clock signal, a series of 14 latches are required to time the 10,000 clock cycles which constitute 10 ms.
FIG. 2 shows an LFSR timer comprising a number of digital storage devices, DO-D4 connected in a loop. Each digital storage device, which is typically a D-type latch, has a data input D, an output Q, an inverted output Q, a clock input CK and a reset input R. Clock inputs CK and reset inputs R of the D-type latches are respectively connected together and receive timing pulse T and reset R signals respectively from external circuitry. The timing pulse signal T preferably consists of a series of pulses of constant frequency and width. Other types of pulses could, however, be used. The data input D of each D-type latch is connected to the output Q of the respectively preceding D-type latch, the data input of the first latch D0 being connected to the output of the last latch D4 by a feedback path 40, with the exception of the data input of D-type latch D2, which is connected to the output 42 of exclusive-NOR gate 44, which has two inputs 46, 48. The first input 46 is connected to the output Q1 of D-type latch D1, and the second input 48 is connected to the feedback path 40. The inverted and non-inverted outputs of D-type latch Dr. are designated Q, Q respectively, and outputs of the other D-type latches are similarly designated.
The truth table of an exclusive-NOR gate with inputs A, B and output N is shown in Table 1.
TABLE 1 ______________________________________ A B N ______________________________________ 0 0 1 0 1 0 1 0 0 1 1 1 ______________________________________
The exclusive-NOR gate 44 therefore outputs the inverse of one input (B; 46) when the other (A; 48) is at 0, and passes the first input (B; 46) when the other (A; 48) is at 1. Comparable functionality is obtained from including an exclusive-OR gate in the circuit instead of an exclusive-NOR. There may be any number of D-type latches in the loop.
By using the exclusive NOR gate in the loop, the data input to D-type latch D2 is the inverse of the output of D-type latch D1 whenever the output of D-type latch D4 is zero.
Applying a positive pulse to the reset input R to each of the D-type latches causes each of the D-type latches to be placed in the 0 output state.
Table 2 shows the sequence of outputs Q4 to Q0 from the D-type latches of the circuit of FIG. 2, during the clock cycles following a reset to zero of the D-type latches. For each clock cycle where a 0 is present at the output of Q4, the output of Q1 in the same cycle is inverted to become the output of Q2 in the following cycle. The sequence follows through all possible combinations, except `11111`, before returning to its original state `00000`, 31 clock cycles later, and resuming the same sequence. The state `11111` is excluded, as no change of state in the LFSR would occur with clocking. The LFSR would be stuck at this value. The circuit of FIG. 2 is thus a special case of LFSR, known as a maximal length shift register, at it cycles though all possible states, being (2.sup.n -1) in number, where n is the number of D-type latches. The positioning of the exclusive-NOR gate 44 in the circuit is critical to achieving a maximal length sequence, in this case 31 cycles.
TABLE 2 ______________________________________ Cycles after Reset Q4 Q3 Q2 Q1 Q0 ______________________________________ 0 0 0 0 0 0 1 0 0 1 0 0 2 0 1 1 0 0 3 1 1 1 0 0 4 1 1 0 0 1 5 1 0 0 1 1 6 0 0 1 1 1 7 0 1 0 1 0 8 1 0 0 0 0 9 0 0 0 0 1 10 0 0 1 1 0 11 0 1 0 0 0 12 1 0 1 0 0 13 0 1 0 0 1 14 1 0 1 1 0 15 0 1 1 0 1 16 1 1 1 1 0 17 1 1 1 0 1 18 1 1 0 1 1 19 1 0 1 1 1 20 0 1 1 1 1 21 1 1 0 1 0 22 1 0 1 0 1 23 0 1 0 1 1 24 1 0 0 1 0 25 0 0 1 0 1 26 0 1 1 1 0 27 1 1 0 0 0 28 1 0 0 0 1 29 0 0 0 1 1 30 0 0 0 1 0 ______________________________________
Were a loop of six D-type latches used, a series of 63 different combinations could have been produced, if the exclusive-NOR gate is placed correctly. Other loop sizes could also be chosen, according to the number of clock cycles required to be timed. For the example described above, to time 10 ms with a 1 MHz clock, 14 latches would be required, giving a maximal length of 16,383 cycles.
If an exclusive-OR gate were used instead of the exclusive-NOR, then for each clock cycle where a 1 is present at the output of Q4, the output of Q1 in the same cycle would be inverted to become the outpro of Q2 in the following cycle. The reset inputs to the D-type latches Dr. to D4 would also have to be arranged so that they reset to the 1 state upon application of the signal R, as the state `00000` is excluded, for the reason discussed above for the `11111` state in the case of an exclusive-NOR gate.
LFSR timers must detect a certain combination of outputs to determine the expiry of the required time period. With reference to Table 2, if the combination 00111 is detected, 6 clock cycles have elapsed since the reset to zero. Similarly, a combination of 01111 represents 20 clock cycles after the reset to zero. By providing a number of detectors, a number of periods may be timed, which can run concurrently from the reset to zero time. Equally, the time elapsed between two detections may be used as a measure of a period of time commencing after the reset to zero, or the counter may be reset to zero after each detection to time independent periods. Such detection requires the use of an n-bit detector for each timing period. A detector may simply be an n-input NAND gate, suitably connected. To detect the occurrence of `00000`, a 5-input NAND is required, whose inputs are Q0, Q1, Q2, Q3, Q4. In the example given above, where 14 series latches are required to time both 10 ms and I.mu.s, two 14-input gates would be required, which would consume a large amount of surface area in an integrated circuit implementation.
A known method enables such LFSR circuits to measure very short periods of time, using simple one bit detectors, by including logic which effectively shorts out the linear (exclusive-OR or exclusive-NOR) function.
In FIG. 3, pass gates 50, 52 are included between the input to D-type latch D2 and: the output 42 of the exclusive NOR gate 44; and the output Q of the D-type latch D1, respectively. The pass gates are supplied with command signal SHORT and its inverse, SHORT. The signal SHORT indicates that a short time delay is to be measured. A short delay may be defined as a time period lasting for a number of clock cycles which is less than the number of latches in the circuit. A time period lasting longer than this will be referred to as a `long` period.
The pass gates 50, 52 serve to connect the data input D of D-type latch D2 to the output of the exclusive-NOR gate 44 when SHORT is low, and to connect the data input D of the D-type latch D2 to the output of D-type latch D1 when SHORT is high. An OR gate 53 is included in the feedback path 40, having a first input connected to the output of D4, and a second input receiving a signal RR, which is high at and following the application of reset signal R. Signal RR is reset to a low state at the first clock signal after the reset signal R becomes inactive.
FIG. 4 shows an alternative circuit for achieving the same result. The circuit is similar to that of FIG. 3 and identical features have identical reference labels. The reset and timing pulse signals R, T and the associated inputs to each of the latches D0 to D4 are omitted from the diagram for clarity, but should be understood as being included in the circuit as described above. The output 42 of the exclusive NOR gate 44 is connected to an input of NAND gate 54. The output Q1 of D-type latch D1 is connected to an input of NAND gate 56. The outputs of gates 54, 56 are connected to inputs of a further NAND gate, 58. A second input of gate 56 is connected to the signal SHORT; an inverter 60 receives SHORT on an input, and has its output connected to a second input of gate 54. When the signal SHORT is high, gate 56 is enabled, permitting the signal Q1 to be transmitted to the input D of D-type latch D2, via gate 58. The output 42 of the exclusive NOR gate 44 is not transmitted, as gate 54 is held in a high state by a low on its second input. Conversely, when SHORT is low, the output 42 of gate 44 is transmitted via gate 58 to D2, whereas the output Q1 of latch D1 is not transmitted, the gate 56 being held at a high state by the low on its second input.
Thus, by setting SHORT high, the exclusive-NOR gate is excluded from the circuit, removing the linear element and causing the circuits of FIGS. 3 and 4 to function as a normal shift register which may be used for timing very short delays. By setting the contents of the register to 00001, and detecting the transition 0 to 1 at Q4, when the LFSR holds 10000, a period of four cycles may be measured, using a single bit detector.
The contents of the LFSR may be set to 00001 by applying an active reset pulse R to the reset inputs of the D-type latches, and an active signal RR to the second input of OR gate 53.
By setting SHORT low, periods of up to 31 cycles may be measured as described above. This method has the advantage that short time delays need only a single bit detection circuit, but have the drawback that the extra logic circuitry required for operating the two different modes occupies a relatively large surface area. Further, using the circuit in the short delay mode, only short periods may be measured. If both a short delay and a long delay need to be measured concurrently, beginning at the same reset, this circuit cannot be used. This solution applies to cases where several short timings need to be made, as the additional logic circuitry is made up for in the savings made by using smaller decoders.
The object of the current invention is to provide a timing circuit for timing a plurality of time periods without adding to the complexity of the timer circuit.