A FIR (Finite Impulse Response) filter is one element of an adaptive filter. It is generally implemented with a DSP (Digital Signal Processor) using memory, and the inner product between a set of stored coefficients and stored previous history of an input signal. Reduced power consumption and storage requirements are desirable in multi-channel applications such as echo cancellation, as the dominant cost and power dissipation is due to memories embedded on chip. There is a need to reduce the amount of memory storage required for echo cancellation and other applications that use FIR filters.
Prior art implementations typically use one storage location for every coefficient in the FIR filter. An example is shown in FIG. 1. In this example, filter coefficients are stored in Coef-RAM 10, which typically consists of 128 Kbytes (2 Kbytes @128 ms/channel). Associated data are stored in Data-RAM 12, and an address counter 14 is used to supply an address to sequentially read out the coefficients one by one from the RAM 10.
The counter address is also split into a 10-bit segment and a 6-bit segment. An offset from modulo counter 15 is added to the 10-bit address segment so as to implement a circular buffer memory for each channel in the Data-RAM 12. The 6 bit address segment is used to select the current circular buffer for each channel that is implemented, as well as to select the appropriate accumulator 21 for each filter output.
Expanded G.711 data from block 17 is convolved in convolution block 20 with coefficients to form the accumulated filter outputs.
Some prior art implementations attempt to reduce the number of stored coefficients by eliminating the zero valued coefficients in order to reduce the required amount of memory storage. Unfortunately with these prior art implementations it sometimes happens that more coefficients are required to model the system than can be handled by the resources available to each particular channel.