Semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, when fabricating field effect transistors (FETs), such as fin-like FETs (FinFETs), device performance can be improved by using a metal gate electrode instead of a typically polysilicon gate electrode. One process of forming, a metal gate stack is termed a replacement-gate or “gate-last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that is performed after formation of the gate. Metal gate electrode generally includes a gate dielectric layer, a work function metal layer, and a gate metal electrode. The work function metal layer may use different materials for different types of transistors, such as p-type FinFET or n-type Fin FET, to fine tune threshold voltage (Vt) of the transistor and thus enhance device electrical performance as needed. However, there are challenges to depositing the work function metal layer, especially with scaled down IC features and complex surface topology in advanced process nodes and beyond. One challenge is that deposition of work function metal in small gate length is complicated and costly as it requires multiple hardmask deposition/patterning, metal wet etch, hardmask removal, and post cleaning processes for threshold voltage (Vt) manipulation for NMOS or PMOS. In the meantime, the thickness of work function metal to be deposited is limited due to smaller CD for advanced process nodes. Furthermore, metal patterning processes may damage metal barrier layers provided between the metal gate electrode and a gate dielectric layer. Consequently, metal materials, may intrude into the gate dielectric layer, causing device defects.