1. Field of the Invention
The present invention relates to a DRAM controller for accessing a dynamic RAM (DRAM).
2. Description of the Related Art
Most computers have a dynamic RAM, a microprocessor, and a DRAM controller. A dynamic RAM has various access modes such as read mode, write mode, refresh mode, readmodify-mode, and the like. The DRAM controller is connected between the DRAM and the microprocessor. It generates various control signals in a predetermined sequence under the control of the microprocessor, and supplies these signals to the dynamic RAM, thereby controlling the dynamic RAM. More specifically, the DRAM controller receives an address signal A, an address strobe signal AS, a read/write control signal R/W, data D, and a data strobe signal DS from the microprocessor, and generates a row-address strobe signal RAS, a column-address strobe signal CAS, a memory address signal MA, an output enable signal OE, and a write enable signal WE, which are supplied, as control signals, to the dynamic RAM.
The operation of the conventional DRAM controller will be explained, with reference to FIGS. 1(A) to 1(M) which form a timing chart. A clock signal CLK shown in FIG. 1(A) is supplied to the microprocessor and the DRAM controller, both incorporated in a computer. The DRAM controller sets the dynamic RAM used in the computer to the read-modify-write mode while it is received the first to fifth clock pulses. As long as the dynamic RAM is set to the read-modify-write mode, data RMD is read from the dynamic RAM. This data RMD and the data D supplied from the microprocessor are subjected to an operation such as AND operation or OR operation, and the result of this operation is written into the dynamic RAM. To be more specific, the microprocessor first outputs an address signal A as is illustrated in FIG. 1(B), and then outputs a address strobe signal AS and a read/write control signal R/W, both at low level, as is shown in FIGS. 1(C) and 1(D). Thereafter, the microprocessor generates data D, as can be seen from FIG. 1(E), and then outputs a data strobe signal DS at the low level as is shown in FIG. 1(F).
After the address strobe signal AS has fallen to the low level, the DRAM controller supplies the dynamic RAM with a memory address signal MA which consists of the upper bits of the address signal A, as can be understood from FIG. 1(I). Further, it outputs a row-address strobe signal RAS at the low level. Thereafter, the DRAM controller supplies the dynamic RAM with a memory address signal MA which consists of the lower bits of the address signal A. Also, it outputs a column-address strobe signal CAS at the low level, at the trailing edge of the third clock pule, as is shown in FIG. 1H. At the same time the DRAM controller outputs an output enable signa OE at the low level, as is shown in FIG. 1(J). Hence, when data RMD is read from that region of the dynamic RAM which is designated by the memory address signal MA, the DRAM controller performs an operation on this data RMD and the data D. The results of this operation, or write data WMD, are supplied to the dynamic RAM. Then, the DRAM controller outputs a write enable signal WE at the low level. The write enable signal WE is supplied to the dynamic RAM, whereby the write data WMD is stored in that region of the dynamic RAM which has been designated by the memory address signal MA.
Assuming that the machine cycle of the microprocessor is a 4-clock pulse period, the read-modify-write operation is terminated at the leading edge of the fifth clock pulse. Therefore, the DRAM controller brings the microprocessor into the wait state at the leading edge of the fifth clock pulses, thereby causing the microprocessor to operated in synchronism with the dynamic RAM.
The time during which the dynamic RAM is accessed can be shortened by, for example, operating the microprocessor at a higher speed. However, this method cannot eliminate the wait period of the microprocessor, and does not serve to increase the data-processing speed of the computer very much.