This invention relates to fabrication operations and, more specifically, to a system and a method for monitoring progress during fabrication of a part.
Fabrication of components often involves removal of material in order to create a feature or reduce a dimension. By way of example, both microelectronic machining and semiconductor device fabrication involve formation of layers of material followed by operations which then remove the material to create vias or planarize a surface. Frequently these fabrication steps are performed chemically or mechanically, and sometimes with the assistance of charged particles such as a plasma or ion beam. Common examples in semiconductor processing include etching of openings such as contact vias and isolation trenches. Also, layers may be thinned by chemical mechanical polishing (CMP) of surfaces to remove material, e.g., material deposited to fill a via, until a surface of one material composition is along the same plane as an adjoining surface of different composition.
Frequently, in these and many other types of fabrication steps material is removed from a surface region to a critical depth which should not be exceeded. However, the ability to directly measure progress of the activity may be difficult or cost prohibitive. For example, while it may be desirable to perform direct measurement of such progress, the fabrication activity may have to be stopped in order to obtain the measurement. Because many contemporary manufacturing operations are capital intensive it is undesirable to reduce throughput by temporary removal of a work piece from an operation in order to perform such measurement. On the other hand, when there is no alternative to removing a work piece from manufacture in order to perform measurement or other analysis, the removal is done on a limited basis (e.g., spot checking) in order to maximize throughput.
During manufacture, the in-line monitoring of product and analysis of process features assures that an operation is providing results within acceptable limits of variability. For example, during fabrication of semiconductor devices, when an opening is being etched through one layer of material to a second layer, it is possible to detect completion of the opening, i.e., end point, by analysis of removed material to identify material of the second layer. The usefulness of such an approach depends on the amount of over etch which can be tolerated. If the etch selectivity is low, the critical depth may be exceeded before end point is detected.
When a process step is well characterized and repeatable it is common to apply the process for a fixed time in order to reach an end point. As the depths of material removal become smaller the margin of error associated with timed operations remains constant such that it becomes more likely that critical depth or end point does not coincide with completion of the timed operation.
In this regard, endpoint detection for CMP operations has been particularly problematic. The two basic methods in use today are the timed operation and a technique of monitoring the change in frictional force associated with the polishing pad and the work piece. The timed technique may be considered largely a trial and error determination.
For CMP operations, changes in frictional force are detectable by measuring the responsive change in motor drive current as the motor turning the polishing pad encounters increased friction. By way of example, when polishing a silicon oxide dielectric layer in a semiconductor product, the friction detection method may incorporate an otherwise unnecessary CMP stop layer such as silicon nitride. As the CMP process initially removes only the silicon oxide, the drive force of the CMP motors remains relatively constant. When the polishing pad comes into contact with the silicon nitride the change in friction is detectable and this signals an opportunity to stop the CMP process before over polish occurs.
The drawback to each of these methods again relates to dimensional tolerances, or the lack of a soft landing at polish stop. Resultant over polishing or under polishing leads to non-uniformity between product wafers in the same lot as well as between wafer lots. Another undesirable effect is consequent damage to alignment marks from over polishing. If the ability to detect the alignment marks is lost, subsequent levels of deposited material cannot be properly processed, resulting in lot scrap or yield loss due to misalignment of features.
According to an exemplary embodiment of the invention, a method is provided for making a structure by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in composition and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion.
In an alternate embodiment of the method a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.