1. Field of the Invention
The present invention relates to a low power, high signal-to-noise ratio (SNR), high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
FIG. 1 shows a process for converting an analog signal “x[n]” 102 to a digital signal “z[n]” 104 using an exemplary ADC 106. ADC 106 receives analog signal x[n] 102 and produces digital signal z[n] 104. Analog signal x[n] 102 comprises variations of a parameter (e.g., voltage) continuously with time. The variations in the parameter of analog signal x[n] 102 are maintained within a range between a lower value “LOW” 108 and a higher value “HIGH” 110. This is referred to as the “swing” of analog signal x[n] 102. Typically, analog signal x[n] 102 is characterized by a carrier frequency. Digital signal z[n] 104 comprises a sequence of discrete quantized values that, over time, tracks the parameter variations of analog signal x[n] 102. Typically, the quantized values of digital signal z[n] 104 are represented by binary numbers. A maximum value “MAX” 112 is defined by the number of different quantized values that can be produced by ADC 106.
FIG. 2 is a block diagram of ADC 106. ADC 106 comprises a sampling functional component 202 and a quantization functional component 204. Sampling functional component 202 records, at a sampling frequency, discrete values of analog signal x[n] 102. Typically, the sampling frequency is greater than or equal to the Nyquist frequency, which is twice the carrier frequency of analog signal x[n] 102. Quantization functional component 204 assigns a quantized value to represent each discrete sampled value, thereby producing digital signal z[n] 104.
The difference between digital signal z[n] 104 and analog signal x[n] 102 is referred to as quantization error e[n]. Ideally, there is a direct relationship between the values of analog signal x[n] 102 and digital signal z[n] 104 at corresponding points in time. In reality, the use of a limited number of quantized values for digital signal z[n] 104 dictates that, in some instances, values of analog signal x[n] 102 must be approximated. It is desirable to minimize quantization error e[n], which is an unwanted byproduct of the quantization process.
FIG. 3 illustrates the process within quantization functional component 204. The range of parameter variations of analog signal x[n] 102 is divided into a number of equal-sized subranges. The number of equal-sized subranges is defined by the value of MAX 112. If, for example, MAX 112 equals four, then the range of parameter variations of analog signal x[n] 102 is divided into four subranges, each measuring one-quarter of the range between LOW 108 and HIGH 110. A subrange “A” 302 extends from LOW 108 to a value at a point “Q1” 304. A subrange “B” 306 extends from Q1304 to a value at a point “Q2” 308. A subrange “C” 310 extends from Q2308 to a value at a point “Q3” 312. A subrange “D” 314 extends from Q3312 to HIGH 110.
Both analog signal x[n] 102 and digital signal z[n] 104 are usually biased by specific values that can obscure the underlying relationship between the two signals.
This relationship is more readily explained when analog signal x[n] 102 is understood to be centered at a point measuring one-half of the range between LOW 108 and HIGH 110. In the present example, this point is Q2308. By translating the actual value of Q2308 to zero and the remaining points in analog signal x[n] 102 accordingly, the bias value is removed from analog signal x[n] 102. Therefore, quantized values derived from this translated analog signal x[n] 102 correspond to digital signal z[n] 104 with its bias value removed.
To minimize quantization error e[n], a quantized value is located in each subrange at a point measuring one-half of the subrange. Each quantized value can be represented by a binary number. For example, a first quantized value “a” 316, represented by binary number zero, is located at the midpoint of subrange A 302. A second quantized value “b” 318, represented by binary number one, is located at the midpoint of subrange B 306. A third quantized value “c” 320, represented by binary number two, is located at the midpoint of subrange C 310. A fourth quantized value “d” 322, represented by binary number three, is located at the midpoint of subrange D 314.
The number of subranges determines the degree of resolution of ADC 106. Degree of resolution is typically expressed as the number of binary digits (i.e., bits) in the quantized values that can be produced by ADC 106. ADC 106 is characterized by its sampling frequency and its degree of resolution. The ability of ADC 106 to digitize analog signal x[n] 102 faithfully is a direct function of both of these. As the sampling frequency is increased, analog signal x[n] 102 is sampled at more points in time. As the degree of resolution is refined, the differences between digital signal z[n] 104 and analog signal x[n] 102 are minimized.
FIG. 4 is a graph 400 of bias-free values of digital signal z[n] 104 as a function of bias-free values of analog signal x[n] 102. A dashed line 402 represents the ideal direct relationship between the values of analog signal x[n] 102 and digital signal z[n] 104. The slope of dashed line 402 corresponds to the gain of ADC 106. A shaded portion 404 between graph 400 and dashed line 402 corresponds to quantization error e[n]. The same error pattern applies to each subrange. The measure of each subrange is referred to as the measure of a Least Significant Bit (LSB).
Statistical methods are often used to analyze quantization error e[n]. FIG. 5 is a graph 500 of a probability density “P(p)” 502 of a subrange of digital signal z[n] 104 as a function of the parameter “p” 504 of analog signal x[n] 102. Probability density P(p) 502 is centered at the midpoint of the subrange (i.e., at a 316, b 318, c 320, or d 322). Probability density P(p) 502 corresponds to quantization error e[n]. Probability density P(p) 502 shows that digital signal z[n] 104 has the same value throughout the subrange, where the subrange extends on either side of its midpoint for a measure equal to one-half of the LSB. The constant value of digital signal z[n] 104 within each subrange and its relationship to quantization error e[n] is also shown by graph 400.
Further analysis of quantization error e[n] is often performed in the frequency domain. FIG. 6 is a graph 600 of probability density P(p) 502 in the frequency domain. Graph 600 shows an “absolute value of p” 602 as a function of frequency “freq” 604. In the frequency domain, quantization error e[n] is recast as quantization noise n[n]. Quantization noise n[n] has a constant value for all frequencies. This is referred to as “white noise.” The white noise of ADC 106 is directly proportional to the measure of the LSB and indirectly proportional to the square root of the sampling frequency. Thus, quantization noise n[n] (and, by transformation, quantization error e[n]) can be minimized by increasing sampling frequency or decreasing the measure of the LSB. The measure of the LSB can be reduced by increasing the number of subranges into which the range of analog signal x[n] 102 is divided (i.e., increasing the number of bits that can be produced by ADC 106).
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including “flash,” “pipelined,” “successive approximation,” and “delta sigma.” These designs are well known to those skilled in the art and their functional components vary in some respects from those of exemplary ADC 106. Each architecture has its benefits and drawbacks. Paramount among these is a tradeoff between bandwidth and degree of resolution. FIG. 7 is a graph 700 that shows the tradeoff between bandwidth and degree of resolution for the various ADC architectures. Graph 700 comprises a “degree of resolution” axis 702 and a “bandwidth” axis 704. The relative positions of the different ADC architectures are plotted with respect to axes 702, 704: a “flash” region 706, a “pipelined” region 708, a “successive approximation” region 710, and a “delta sigma” region 712.
In the design of network technologies, data conversion has often presented itself as a bottleneck that impedes the rate at which information is transmitted. Traditionally, those ADC architectures that can support large bandwidths for rapid transfers of data have been favored for network applications. Because much of the circuitry of a delta sigma ADC architecture is analog, its bandwidth is limited by the processing speed of its analog circuits.
However, emerging applications, such as full-motion video and voice over Internet, require high resolution data conversion. Fortunately, improvements in the methods of fabricating integrated electronic circuits have increased not only the processing speed and number of devices, but also the variety of devices (such as linear capacitors) that can be fabricated on a given area of substrate material. Delta sigma ADCs have benefited from these developments, which have facilitated the use of delta sigma ADCs in network applications.
FIG. 8 is a block diagram of a first-order, single-stage, single-bit delta sigma ADC 800. ADC 800 comprises a first-order, single-stage, single-bit delta sigma modulator 802 and a digital decimator 804 connected at a node “N0” 806 along a signal path 808. Modulator 802 comprises a summing node “Σ0” 810, an integrator 812, a single-bit quantizer 814, and a DAC 816. Summing node Σ0 810, integrator 812, and quantizer 814 are connected, respectively, in series along signal path 808. Integrator 812 has a gain “a1”. Gain a1 is determined empirically and is set to a value such that modulator 802 functions with stability to process analog signal x[n] 102. Typically, gain a1 has a value between zero and one. DAC 816 is connected in parallel with signal path 808 between node N0 806 and summing node Σ0 810. Decimator 804 comprises a lowpass digital filter 818 and a downsampler 820 connected, respectively, in series along signal path 808. Analog signal x[n] 102 is received by ADC 800, at an input 822, and converted into digital signal z[n] 104, produced at an output 824.
Initially, analog signal x[n] 102 passes through summing node Σ0 810 and is sampled by integrator 812. Integrator 812 integrates analog signal x[n] 102 over a given period of time to produce an integrated signal “v[n]” 826. Integrated signal v[n] 826 is transmitted to single-bit quantizer 814. Single-bit quantizer 814 rounds integrated signal v[n] 826 to the closest of two preset levels (i.e., a single bit) to produce a quantized signal “y[n]” 828. To minimize the difference between quantized signal y[n] 828 and analog signal x[n] 102, quantized signal y[n] 824 is transmitted to DAC 816 and converted to produce an analog feedback signal “fbk[n]” 830, which is fed back to summing node Σ0 810. Quantizer 814 and DAC 816 have a combined gain “k1” defined as shown in Eq. (1):k1≡fbk[n]/v[n],  Eq. (1)where both analog feedback signal fbk[n] 830 and integrated signal v[n] 826 are analog signals.
At summing node Σ0 810, analog feedback signal fbk[n] 830 is subtracted from analog signal x[n] 102 to produce an analog difference signal “u[n]” 832. Analog difference signal u[n] 832 passes into integrator 812 to repeat the process described above. Essentially, integrator 812 integrates the difference between quantized signal y[n] 828 and analog signal x[n] 102. Over a large number of samples, integrator 812 forces this difference to approach zero. Thus, analog signal x[n] 102 is received by modulator 802, at input 822, and converted into quantized signal y[n] 828, produced at node N0 806. Input 822 is an input and node N0 806 is an output of modulator 802.
FIG. 9 is a graph 900 of bias-free values of quantized signal y[n] 828, produced by single-bit quantizer 814, as a function of bias-free values of analog signal x[n] 102. With analog signal x[n] 102 centered at a point measuring one-half of the range between LOW 108 and HIGH 110 (e.g., point Q2308 from the example above), quantizer 814 divides analog signal x[n] 102 into two subranges. Quantizer 814 assigns a lower value “LOWER” 902 to those values of analog signal x[n] 102 that are less than the midpoint (e.g., Q2308) value, and a higher value “HIGHER” 904 to those values of analog signal x[n] 102 that are greater than the midpoint (e.g., Q2308) value. Typically, LOWER 902 is the lowest quantized value and HIGHER 904 is the highest quantized value that can be produced by quantizer 814.
Because single-bit quantizer 814 does not produce any quantized values that are in between LOWER 902 and HIGHER 904 (its lowest and highest quantized values), gain k1 is essentially indeterminate. However, for analysis purposes, it is desirable to set an overall gain of modulator 802, the product of gain a1 and gain k1, equal to one.
Returning to FIG. 8, quantized signal y[n] 828 from modulator 802 comprises a stream of quantized values. Each quantized value is either LOWER 902 or HIGHER 904 (i.e., a single bit of resolution). Typically, this stream is produced at a modulator frequency that is several times greater than the carrier frequency of analog signal x[n] 102. The ratio of the modulator frequency to the Nyquist frequency is referred to as the oversampling ratio (OSR).
Decimator 804 acts to lowpass filter and downsample quantized signal y[n] 828. Quantized signal y[n] 828 is transmitted to lowpass digital filter 818, which performs a sophisticated form of averaging on the data stream to produce a high resolution signal “w[n]” 834. A maximum value “MAXIMUM” is defined by the number of different quantized values that can be produced by filter 818. High resolution signal w[n] 834 also comprises a stream of quantized values. However, each quantized value can be any of the different quantized values (i.e., multiple bits of resolution) that can be produced by filter 818.
High resolution signal w[n] 834 emerges from filter 818 at a frequency too high for subsequent digital signal processing. High resolution signal w[n] 834 is transmitted to downsampler 820, which resamples high resolution signal w[n] 834 to produce digital signal z[n] 104. Digital signal z[n] 104 enjoys the same high resolution as high resolution signal w[n] 834, but at a digital processing frequency. Typically, the digital processing frequency is greater than or equal to the Nyquist frequency. Thus, quantized signal y[n] 828 is received by decimator 804, at node N0 806, and converted into digital signal z[n] 104, produced at output 824. Node N0 806 is an input and output 824 is an output of decimator 804.
The usefulness of the high resolution of ADC 800 turns on its ability to minimize quantization noise n, which is an unwanted byproduct of the quantization process. Fortunately, it is a feature of modulator 802 that it acts as a highpass filter for quantization noise n, much of which can be removed by lowpass digital filter 818. This capability is more readily explained by analyzing modulator 802 in the discrete time domain.
FIG. 10 is a block diagram of first-order, single-stage, single-bit delta sigma modulator 802 recast as a discrete time domain model 1000. Model 1000 comprises a sampling and integration delay element 1002, summing node Σ0 810, a discrete time integrator 1004, a gain element 1006, a second summing node “Σ1” 1008, and a feedback delay element 1010. Sampling and integration delay element 1002, summing node Σ0 810, discrete time integrator 1004, gain element 1006, second summing node Σ1 1008 are connected, respectively, in series along signal path 808. Sampling and integration delay element 1002 has a transfer function of “z−1”. Discrete time integrator 1004 has a transfer function of “z−1/(1−z−1)” and gain a1. Gain element 1006 has gain k1. Feedback delay element 1010 is connected in parallel with signal path 808 between node N0 806 and summing node Σ0 810. Feedback delay element 1010 has transfer function z−1.
In model 1000, quantization noise n[n] 1012 is added at second summing node Σ1 1008. Recalling that gain a1 is set equal to the inverse of gain k1, quantized signal y[n] 828 can be expressed as shown in Eq. (2):y[n]=x[n]z−1+n[n](1−z−1).  Eq. (2)Eq. (2) shows how modulator 802 acts as a highpass filter for quantization noise n[n] 1012. This characteristic is also referred to as noise shaping.
The coupling of modulator 802 with lowpass digital filter 818 of decimator 804 enables ADC 800 to enjoy a relatively high signal-to-noise ratio (SNR) in comparison with other ADC architectures. As a “rule of thumb”, the SNR for ADC 800 improves by 9 dB for every doubling of its OSR.
SNR is an important figure of merit for ADC performance. Improvements in the methods of fabricating integrated electronic circuits have reduced the size of electron devices. This has enabled ADC 800 to be designed to consume less power. However, reduced power consumption is often realized in part by using lower power supply voltages. Integrator 812 is implemented using an operational amplifier. Because some of the range between supply voltages to an operational amplifier must be consumed to support holding active load devices and current sources in saturation, only the remaining portion of this range is available for the output swing of the operational amplifier. This remaining portion is referred to as the dynamic range of the operational amplifier. So that ADC 800 does not suffer from nonidealities caused by the operational amplifier that implements integrator 812, it is important that the swing of integrated signal v[n] 826 remain within the dynamic range of the operational amplifier.
First order, single-stage, single-bit delta sigma modulator 802 is a basic design for a sigma delta modulator. Variations to this basic design have been introduced to improve various figures of merit.
FIG. 11 is a block diagram of a second-order, single-stage, single-bit delta sigma modulator 1100. Modulator 1100 comprises first summing node Σ0 810, first integrator 812, a second summing node “Σ2” 1102, a second integrator 1104, single-bit quantizer 814, and DAC 816. First summing node Σ0 810, first integrator 812, second summing node Σ2 1102, second integrator 1104, and quantizer 814 are connected, respectively, in series along signal path 808. First integrator 812 has a gain of “a3”. Second integrator 1104 has a gain of “a4”. Gains a3 and a4 are determined empirically and are set to values such that modulator 1100 functions with stability to process analog signal x[n] 218. Typically, gains a3 and a4 have values between zero and one. DAC 816 is connected in parallel with signal path 808 between node N0 806 and summing nodes Σ0 810 and Σ2 1102. Quantizer 814 and DAC 816 have a combined gain k1. For analysis purposes, k1=1/a3a4. A higher order compensation gain element “2a3” 1106 is connected between DAC 816 and second summing node Σ2 1102. Higher order compensation gain element 2a3 1106 has a gain of “2a3”. Analog signal x[n] 218 is received by modulator 1100, at input 224, and converted into quantized signal y[n] 828, produced at node N0 806. Input 224 is an input and node N0 806 is an output of modulator 1100.
In a discrete time implementation (see FIG. 15A), second integrator 1104 acts as a second highpass filter for quantization noise n[n] 1012. Higher order compensation gain element 2a3 1106 enables quantized signal y[n] 828 to be expressed strictly as a second order function as shown in Eq. (3):y[n]=x[n]z−2+n[n](1−z−1)2.  Eq. (3)Thus, a delta sigma ADC that incorporates modulator 1100 can enjoy a better SNR than ADC 800. As a rule of thumb, the SNR for a delta sigma ADC that incorporates modulator 1100 improves by 15 dB for every doubling of its OSR. A similar analysis can be used to assess higher order delta sigma modulators. However, empirical studies have shown that, while delta sigma ADCs that incorporate higher order modulators are relatively insensitive to nonidealities in their functional components, the stability of these circuits rapidly deteriorates beyond the second order.
As mentioned above, exemplary ADC 106 comprises sampling functional component 202 and quantization functional component 204. Often sampling functional component 202 is realized as a switched capacitor sampling network. High performance switch capacitor sampling networks are typically configured as differential circuits. As compared with single-ended designs, a differential embodiment enjoys improved power supply noise rejection, double the output range, and cancellation of even-order distortion components.
FIG. 12A is a schematic diagram of a typical differential switched capacitor sampling network 1200 as could be used as an input circuit with modulator 802. Network 1200 comprises ten switches: “S1” 1202, “S2” 1204, “S3” 1206, “S4” 1208, “S5” 1210, “S6” 1212, “S7” 1214, “S8” 1216, “S9” 1218, and “S10” 1220. Collectively, S1 1202, S2 1204, S3 1206, S4 1208, S5 1210, and S6 1212 are referred to as signal conducting switches, while S7 1214, S8 1216, S9 1218, and S10 1220 are collectively referred to as summing junction switches.
FIG. 12B illustrates a two-phase nonoverlapping clock 1222 defined by four clock waveforms: “φ1” 1224, “φ1D” 1226, “φ2” 1228, and “φ2D” 1230. The position of each switch at any given time is determined by its corresponding clock waveform. In a representative embodiment, a switch is open when its corresponding clock waveform is “off” and closed when its corresponding clock waveform is “on.” One skilled in the art would recognize that network 1200 could be configured with other relationships between the state of the switches and their corresponding clock waveforms.
Clock 1222 is configured so that φ1 1224 and φ1D 1226 are on when φ2 1228 and φ2D 1230 are off. Clock waveforms φ1D 1224 and φ2D 1226 are similar to, respectively, clock waveforms φ1 1224 and φ2 1228. However, the falling edges of φ1D 1226 and φ2D 1230 are not initiated until after φ1 1224 and φ2 1226 have returned to their “off” states. Together, clock waveforms φ1 1224 and φ1D 1226 define a sampling phase of clock 1222 while clock waveforms φ2 1228 and φ2D 1230 define a integration phase.
Network 1200 further comprises a positive voltage sampling capacitor “C1+” 1232, a negative voltage sampling capacitor “C1−” 1234, and integrator 812. Integrator 812 comprises an operational amplifier 1236 with an inverting terminal “T−” 1238 and a noninverting terminal “T+” 1240. T−1238 and T+1240 together comprise summing node Σ0 810. Integrator 812 produces integrated signal v[n] 826, which comprises a positive voltage output signal “Vo+” 1242 and a negative voltage output signal “Vo−” 1244. A positive voltage integrator feedback capacitor “C2+” 1246 is connected in parallel with operational amplifier 1236 between T−1238 and Vo+1242. A negative voltage integrator feedback capacitor “C2−” 1248 is connected in parallel with operational amplifier 1236 between T+1240 and Vo−1244. Analog signal x[n] 102, which comprises a positive voltage input signal “Vi+” 1250 and a negative voltage input signal “Vi−” 1252, is received by network 1200.
In a preferred embodiment, the value of C1+1232 equals the value of C1−1234, and the value of C2+1246 equals the value of C2−1248. For each of the positive and negative portions of network 1200, the sampling and integrator feedback capacitors determine the gain (e.g., a3) of the corresponding integrator (e.g., first integrator 812) as shown in Eq. (4):Gain=Cs/Cf,  Eq. (4)where “Cs” is C1+1232 for the positive portion of network 1200 and C1−1234 for the negative portion of network 1200, and “Cf” is C2+1246 for the positive portion of network 1200 and C2−1248 for the negative portion of network 1200.
For each of the positive and negative portions of network 1200, the sampling and integrator feedback capacitors also determine a feedback factor as shown in Eq. (5):Feedback Factor=Cf/[Cf+Cs].  Eq. (5)The feedback factor directly affects the bandwidth of the operational amplifier used to implement integrator 812. A larger bandwidth corresponds to a faster response (or settling) time of the operational amplifier. Settling time is proportional to the product of the feedback factor and the power consumed by the operational amplifier used to implement integrator 812.
In network 1200, switch S1 1202 is disposed between a negative reference signal “ref” 1254 and C1+1232. Switch S2 1204 is disposed between a positive reference signal “ref+” 1256 and C1+1232. Switch S3 1206 is disposed between Vi+1250 and C1+1232. Thus, switches S1 1202, S2 1204, and S3 1206 are connected in parallel with each other at a node “N1” 1258 upstream of C1+1232. Likewise, switch S4 1208 is disposed between ref+1256 and C1−1234. Switch S5 1210 is disposed between ref 1254 and C1−1234. Switch S6 1212 is disposed between Vi−1252 and C1−1234. Thus, switches S4 1208, S5 1210, and S6 1212 are connected in parallel with each other at a node “N2” 1260 upstream of C1−1234.
Switch S7 1214 is disposed between a node “N3” 1262 downstream of C1+1232 and T−1238. Switch S8 1216 is disposed between node N3 1262 and a network common mode voltage “VCM” 1264. Likewise, switch S9 1218 is disposed between a node “N4” 1266 downstream of C1−1234 and T+1240. Switch S10 1220 is disposed between node N4 1266 and VCM 1264.
Operation of network 1200 can be explained by tracing the circuits that are established in response to the cycling of the clock waveforms of clock 1222.
At a time “t0”, clock waveforms φ1 1224 and φ1D 1226 cycle to the on state while clock waveforms φ2 1228 and φ2D 1230 remain in the off state. In response to the on state of φ1 1224, switches S8 1216 and S10 1220 close. In response to the on state of φ1D 1226, switches S3 1206 and S6 1212 close. With S3 1206 and S8 1216 closed, a circuit is established between Vi+1250 and VCM 1264 through C1+1232. This circuit allows Vi+1250 to be sampled as a charge on C1+1232. Likewise, with S6 1212 and S10 1220 closed, a circuit is established between Vi−1252 and VCM 1264 through C1−1234. This circuit allows Vi−1252 to be sampled as a charge on C1−1234.
At a time “t1”, clock waveform φ1 1224 cycles to the off state, while φ1D 1226 remains in the on state. Clock waveforms φ2 1228 and φ2D 1230 remain in the off state. In response to the off state of φ1 1224, switches S8 1216 and S10 1220 open. Opening switch S8 1216 breaks the circuit between Vi+1250 and VCM 1264. This isolates the charge stored on C1+1232, thus effectively sampling Vi+1250. Likewise, opening switch S10 1220 breaks the circuit between Vi−1252 and VCM 1264. This isolates the charge stored on C1−1234, thus effectively sampling Vi−1252.
At a time “t2”, clock waveform φ1D 1226 cycles to the off state. Clock waveforms φ1 1224, φ2 1228, and φ2D 1230 remain in the off state. In response to the off state of φ1D 1226, switches S3 1206 and S6 1212 open. By delaying the opening of switches S3 1206 and S6 1212 until after switches S8 1216 and S10 1220 have been opened, and thus isolating the charges stored on C1+1232 and C1−1234, the sampled signals are unaffected by the charge injections that occur after switches S8 1216 and S10 1220 have been opened. Particularly, the sampled signals are not distorted by any charge injection resulting from the opening of switches S3 1206 and S6 1212.
At a time “t3”, clock waveforms φ2 1228 and φ2D 1230 cycle to the on state while clock waveforms φ1 1224 and φ1D 1226 remain in the off state. In response to the on state of φ2 1228, switches S7 1214 and S9 1218 close. In response to the on state of φ2D 1230, either switch S1 1202 or S2 1204 and either switch S4 1208 or S5 1210 close. (In a delta sigma modulator, the polarity of the data in the feedback loop determines which one of switches S1 1202 and S2 1204 and which one of switches S4 1208 and S5 1210 close.)
With switches S7 1214 and S1 1202 closed, a circuit is established between ref 1254 and inverting terminal T−1238 through C1+1232. This circuit enables the charge on C1+1232 to be transferred to C2+1246. The transferred charge “Q+” at inverting terminal T−1238 is defined by Eq. (6):Q+=C1+(Vi+−ref−).  Eq. (6)Similarly, with switches S9 1218 and S4 1208 closed, a circuit is established between ref+1256 and noninverting terminal T+1240 through C1−1234. This circuit enables the charge on C1−1234 to be transferred to C2−1248. The transferred charge “Q−” at noninverting terminal T+1240 is defined by Eq. (7):Q−=C1−(Vi−−ref+).  Eq. (7)
Alternatively, with switches S7 1214 and S2 1204 closed, a circuit is established between ref+1256 and inverting terminal T−1238 through C1+1232. This circuit enables the charge on C1+1232 to be transferred to C2+1246. The transferred charge Q+ at inverting terminal T−1238 is defined by Eq. (8):Q+=C1+(Vi+−ref+).  Eq. (8)Similarly, with switches S9 1218 and S5 1210 closed, a circuit is established between ref−1254 and noninverting terminal T+1240 through C1−1234. This circuit enables the charge on C1−1234 to be transferred to C2−1248. The transferred charge Q− at noninverting terminal T+1240 is defined by Eq. (9):Q−=C1−(Vi−−ref−).  Eq. (9)
At a time “t4”, clock waveform φ2 1228 cycles to the off state, while φ2D 1230 remains in the on state. Clock waveforms φ1 1224 and φ2 1228 remain in the off state. In response to the offstate of φ2 1228, switches S7 1214 and S9 1218 open. Opening switch S7 1214 breaks the circuit between inverting terminal T−1238 and either ref−1254 or ref+1256. This isolates the charge transferred to C2+1246. Likewise, opening switch S9 1218 breaks the circuit between noninverting terminal T−1240 and either ref+1256 or ref−1254. This isolates the charge transferred to C2−1248.
At a time “t5” clock waveform φ2D 1230 cycles to the off state. Clock waveforms φ1 1224, φ1D 1226, and φ2 1228 remain in the off state. In response to the off state of φ2D 1230, either switch S1 1202 or S2 1204 and either switch S4 1208 or S5 1210 open. By delaying the opening of either switch S1 1202 or S2 1204 and either switch S4 1208 or S5 1210 until after switches S7 1214 and S9 1218 have been opened, the transferred signals are unaffected by the charge injection that occur after switches S7 1214 and S9 1218 have been opened. Particularly, the transferred signals are not distorted by any charge injection resulting from the opening of either switch S1 1202 or S2 1204 and either switch S4 1208 or S5 1210.
At a time “t6”, clock waveforms φ1 1224 and φ1D 1226 cycle to the on state while clock waveforms φ2 1228 and φ2D 1230 remain in the off state. The response of network 1200 to the on state of φ1 1224 and φ1D 1226 is identical to the response to the on state at time t0 as explained above. Likewise, at times subsequent to t6, network 1200 operates in the manner explained above. Thus, the time between t0 and t6 defines the period of clock 1222.
In a more typical embodiment, the switches of FIG. 12A are implemented with metal oxide semiconductor field effect transistors (MOSFETs). FIG. 13 is a schematic diagram of a differential switched capacitor sampling network 1300 implemented with MOSFET switches. This circuit is described in Stephen R. Norsworthy et al., Delta-Sigma Data Converters: Theory, Design, and Simulation, The Institute of Electrical and Electronics Engineers, Inc. 1997, which is incorporated herein by reference. Although network 1300 is configured different from network 1200, the principles for implementing switches with MOSFETs are the same for both networks 1200 and 1300. For each MOSFET switch of FIG. 13, the signal path is between its source and drain terminals. The state of the MOSFET switch is controlled by a clock waveform applied to its gate terminal. Typically, the clock waveform has a voltage equal to one of the supply voltages.
Where a switch in a differential switched capacitor sampling network is implemented as a MOSFET, the resistance “R” of the switch is defined by Eq. (10):R=1/[kW/L(VGS−VT−VDS)],  Eq. (10)where “k” is a constant, “W” is the width of the channel region of the MOSFET, “L” is the length of the channel region of the MOSFET, “VGS” is the voltage potential between the gate and source terminals, “VT” is the threshold voltage, and “VDS” is the voltage potential between the drain and source terminals of the MOSFET. These parameters are well understood in the art.
While delaying the opening of the signal conducting switches (e.g., S1 1202, S2 1204, S3 1206, S4 1208, S5 1210, and S6 1212) until after the summing junction switches (e.g., S7 1214, S8 1216, S9 1218, and S10 1220) have been opened isolates the sampled signal from distortions due to charge injections from the signal conducting switches, clock 1222 does not protect the sampled signal from distortions due to charge injections from the summing junction switches.
Furthermore, clock 1222 causes charge injections from the signal conducting switches (e.g., S1 1202, S2 1204, S3 1206, S4 1208, S5 1210, and S6 1212) into ref−1254 and ref+1256. Typically, ref−1254 and ref+1256 are produced by constant voltage buffers. In order for a modulator using network 1200 to attain a desired degree of linear performance, the circuits that produce ref−1254 and ref+1256 must be designed to meet certain settling requirements. Charge injections into ref−1254 and ref+1256 can complicate these designs such that the circuits that produce ref−1254 and ref+1256 consume significant power.
As mentioned above, integrator 812 comprises operational amplifier 1236. It can be shown that the common mode input signal “Vic” of operational amplifier 1236 can be expressed as shown in Eq. (11):Vic=[(Vi++Vi−)/2−(ref++ref−)/2+VCM].  Eq. (11)In traditional implementations, (Vi++Vi−)/2, (ref++ref−)/2, and VCM, are maintained at values midway between the two supply voltages to facilitate maximum signal swing. Unfortunately, where the summing junction switches (e.g., S7 1214, S8 1216, S9 1218, and S10 1220) are implemented as MOSFETs, maintaining (Vi++Vi−)/2, (ref++ref−)/2, and VCM at values midway between the two supply voltages causes VGS of these switches to have relatively small values. By application of Eq. (10), this causes the summing junction switches to have relatively large resistances, which typically are associated with relatively large switches. Large switches can cause correspondingly large charge injections.
What is needed is a mechanism that reduces distortions due to charge injections. Preferably, such a mechanism should also reduce the power consumed by a delta sigma modulator.