1. Field of the Invention
The invention relates in general to a flat display and display panel thereof, and more particularly to a flat display with a cell test function, which can reduce power consumption of an ESD protection circuit in a normal dynamic display mode.
2. Description of the Related Art
FIG. 1A shows a conventional ESD protection circuit. Referring to FIG. 1A, a thin film transistor (TFT) display panel 100 includes a positive ESD protection circuit 112 and a negative ESD protection circuit 114 coupled to each of signal lines 110 (scan lines or data lines) for respectively discharging positive and negative electrostatic charges generated as a driving chip 120 is bonded to the display panel 100. The negative ESD protection circuit 114 includes a diode-connected TFT transistor M. The source of the TFT transistor M is coupled to the signal line 110 and the gate and drain of the TFT transistor M are coupled to a common electrode (having a common voltage Vcom) of the display panel 100.
The driving chip 120 (scan or data driving chip) couples to the signal-line bump of the display panel 100 at module process. In the process when the driving chip 120 bonds to the display panel 100, the negative electrostatic charges generated on the signal lines 110 can be transmitted to the common electrode Vcom for discharge via the transistor M so as to prevent the negative electrostatic charges from flowing into the signal lines 110 and damaging TFT devices of the display panel 100.
However, for example, the signal lines 110 are scan lines. When the display panel 100 bonds to the driving chip 120 for operating in a normal dynamic display mode, as shown in FIG. 1B, in a period T1, the driving chip 120 outputs a scan signal Scan1 with a voltage Vgh, such as +10V, via the first-stage scan signal line 110 and in the same period T1, the scan signal on the second-stage scan signal line 110 has a low voltage Vgl, such as −10V, in the meanwhile the common voltage Vcom has an AC voltage Vch, such as +5V. Therefore, the TFT transistor M coupled to the first-stage scan signal line 110 is turned off because its negative-electrode voltage (=Vgh) is higher than its positive-electrode voltage (=Vch). Besides, the TFT transistors M of other scan signal lines 110 are turned on to generate currents I, which increases the power consumption as shown in FIG. 1A because their negative-electrode voltage Vgl (=−10V) are lower than their positive-electrode voltage Vch or Vcl (0V).
Supposed there are N scan lines in a panel, there would be power-consuming currents (N−1)*I flowing by the negative ESD protection circuits in the period T1. Similarly, in the period T2, only the TFT transistor M of the second stage scan signal line 110 is turned off and the other (N−1) TFT transistors M are all turned on, which generates (N−1)*I power-consuming currents through the negative ESD protection circuits. Therefore, although the conventional negative ESD protection circuits 114 can achieve the purpose of ESD protection, these protection circuits 114 increase power consumption of the display panel 100 in a dynamic display mode.