As process technology reaches the optical shrink limitation, it becomes more difficult to increase gate density at the rate predicted by Moore's Law using a monolithic, integrated circuit (IC) architecture. Three dimensional (3D) die stacking has becomes an alternative to the monolithic IC architecture for increasing gate density.
An established 3D die stacking technique in IC assembly involves use of die-to-die interconnects, such as micro bump interconnects (which are also referred to as μ-bumps) and through silicon via (TSV) interconnects. However, having a large number of die-to-die interconnects places a challenge on assembly yield. As the die-to-die interconnect count increases, the assembly yield for the 3D stacked die IC decreases. Generally, die-to-die interconnect counts for 3D stacked die ICs range from a 1000 to tens of 1000 s. Based on some industry estimates, a 3D stacked die IC with a die-to-die interconnect count of greater than 250 has a yield of approximately 60%.
Furthermore, die-to-die interconnect failures can only be detected after die assembly and at a final electrical test. Once one of the die-to-die interconnects fails, all the dies in the 3D stacked die IC will be identified as defective devices and will need to be rejected.