1. Field of the Invention
The present invention relates to methods for manufacturing integrated circuit structures and, in particular, to methods for manufacturing integrated circuit metal interconnect lines.
2. Description of the Related Art
Typical integrated circuits (ICs) include metal interconnect structures that serve a variety of purposes, including carrying electrical signals between individual device elements in the IC, as well as providing power, a connection to ground and a connection to external apparatus.
FIG. 1 illustrates a portion of a typical metal interconnect structure 10 disposed above an insulating layer 12 on a semiconductor subs interconnect structure 10 includes interconnect dielectric material layer 18, as well as a patterned metal layer, which is made up of individual metal interconnect lines 16A and 16B. Metal interconnect lines 16A and 16B, among other things, carry signals and provide power. Interconnect dielectric material layer 18 provides electrical isolation both between metal interconnect lines (e.g. between metal interconnect lines 16A and 16B) within a given patterned metal layer and between multiple patterned metal layers in a multi-level metal interconnect structure (not shown in FIG. 1). The conventional interconnect dielectric material that constitutes the interconnect dielectric material layer 18 is silicon dioxide (SiO.sub.2), although other dielectric materials, such as silicon nitride and low k materials (i.e. materials with a low dielectric constant), are also known to those of skill in the art. Additional metal interconnect structures, such as interconnect contacts and interconnect vias, are known to those skilled in the art, however, they are not shown in FIG. 1 to avoid obscuring those metal interconnect structures that are most relevant to the present invention.
State-of-the art metal interconnect lines often take the configuration of a multi-layer metal stack. FIG. 2 illustrates a typical metal interconnect structure 20 that includes such a multi-layer metal stack interconnect line 22. Multi-layer metal stack interconnect line 22 includes a first layer 24 of titanium, a second layer 26 of titanium-nitride (TiN), a third layer 28 of aluminum with 0.2 to 4.0 wt. % copper, and a fourth layer 30 of TiN. Similar to FIG. 1, the multi-layer metal stack interconnect line 22 is disposed on an insulating layer 12 and covered by an interconnect dielectric material layer 18.
Conventional processes for manufacturing metal interconnect structures with multi-layer metal stack interconnect lines include the steps of first depositing an insulating layer over device elements, such as diodes, transistors and resistors (not shown in FIGS. 1 and 2), that were previously formed in a semiconductor substrate, followed by planarizing the insulating layer. The insulating layer is planarized using, for example, chemical mechanical polishing (CMP) or resist-based etch-back techniques. Interconnect contacts (not shown in FIGS. 1 and 2) are subsequently formed in the insulating layer. A multi-layer metal stack is then formed on the insulating layer. The multi-layer metal stack is composed of, for example, a titanium (Ti) layer with a thickness in the range of 50 angstroms to 400 angstroms. which is underlying a titanium-nitride (TiN) layer with a thickness in the range of 50 angstroms to 400 angstroms, which is in turn underlying an aluminum (Al) layer containing 0.2-4.0 wt. % copper (Cu) with a thickness in the range of 1,000 angstroms to 20,000 angstroms, which is in turn underlying a TiN layer with a thickness in the range of 50 angstroms to 1000 angstroms. Next, the multi-layer metal stack is patterned, using conventional photolithographic and etching techniques, to form a patterned metal layer with metal interconnect lines. An interconnect dielectric material layer is then deposited over the patterned metal layer.
This conventional process of forming metal interconnect lines, however, can lead to several problems. First, if the metal interconnect lines are heated subsequent to the interconnect dielectric material layer deposition step, an undesirably high level of stress (compressive or tensile) can be produced in the metal interconnect lines due to thermal expansion mismatch between the metal interconnect lines and the interconnect dielectric material layer. A high compressive stress can cause a fracture in the interconnect dielectric material layer. A high compressive stress can also cause the metal from the interconnect metal lines to extrude through vias cut in the interconnect dielectric material layer. A high tensile stress can, on the other hand, result in the creation of voids in the metal interconnect lines. Whether under a high compressive stress or under a high tensile stress, the integrity of the metal interconnect structure is compromised.
There is, therefore, still a need in the art for a process for manufacturing low stress metallic interconnect lines.