The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a logic macro and random access memory (RAM) macros.
In the present specification, a logic macro refers to a group of logic gates constituted by cells, and a RAM macro refers to a group of memory cells and circuits making up a RAM device.
In semiconductor integrated circuit devices having a logic macro and RAM macros, there are cases where a large number of gates are required so as to improve the function of the circuit device. In addition, it is essential that the logic macro can be designed with ease.
When customizing a semiconductor integrated circuit device having a logic macro and a plurality of RAM macros by forming predetermined fixed interconnections thereon, all of the RAM macros may be used or at least one of the RAM macros may not be used.
FIG. 1 shows an essential part of the conventional semiconductor integrated circuit device having a logic macro and two RAM macros. In FIG. 1, a semiconductor chip 10 has a logic macro 11 and two RAM macros 12.sub.1 and 12.sub.2. A channel region 13 is provided between the logic macro 11 and the RAM macros 12.sub.1 and 12.sub.2 and between the mutually adjacent RAM macros 12.sub.1 and 12.sub.2.
The logic macro 11 has a plurality of latch circuits 15. On the other hand, each of the RAM macros 12.sub.1 and 12.sub.2 have a memory cell array 16, an X-address decoder driver 17, a Y-address decoder driver 18 and a sense/write amplifier 19.
Predetermined latch circuits 15 indicated by hatchings are used as latch circuits exclusively for use by the RAM macros 12.sub.1 and 12.sub.2, while unhatched latch circuits 15 are used as latch circuits exclusively for use by the logic macro 11.
An input data received from a gate array of the logic macro 11 is written into a predetermined memory cell of the memory cell array 16 by the sense/write amplifier 19 based on an address designated by the X-address decoder driver 17 and the Y-address decoder driver 18. An output data read out from the predetermined memory cell of the memory cell array 16 by the sense/write amplifier 19 based on the address designated by the X-address decoder driver 17 and the Y-address decoder driver 18 is outputted to the outside of the RAM macro. The predetermined latch circuits 15 indicated by the hatchings are used to synchronize the timings of various signals such as the address, the input data and a write enable signal to a clock signal.
The interconnections connecting the predetermined latch circuits 15 indicated by the hatchings to the RAM macros 12.sub.1 and 12.sub.2 are fixed regardless of the kind or model of the semiconductor integrated circuit device, that is, the function to be carried out in the circuit device, and the interconnections cannot be changed.
On the other hand, the number of logic gates provided in the logic macro 11 is generally determined by the size of the RAM macros 12.sub.1 and 12.sub.2, the size of the semiconductor chip 10 and the like. There are cases where latch circuits are required in the logic macro 11 in order to match timings of signals. In such cases, the latch circuits are provided in the logic macro 11, and a region within the logic macro 11 where the gates may be provided is reduced by the area occupied by the latch circuits. In other words, a region of the logic macro 11 is occupied by the predetermined latch circuits 15 indicated by the hatchings provided exclusively for use by the RAM macros 12.sub.1 and 12.sub.2, and the need to provide the required latch circuits in the logic macro 11 for use therein further reduces the region in which the gates of the logic macro 11 may be provided. For this reason, there are problems in that it is impossible to sufficiently increase the number of gates within the logic macro 11 and the freedom of design of the logic macro 11 is limited.