1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an integrated circuit with ESD protection circuit fabricated using deep sub-micron complementary metal-oxide-semiconductor (CMOS) technique.
2. Description of the Related Art
In the process of fabricating or assembling an integrated circuit (IC), electrostatic discharge (ESD) is often a critical factor leading to irreversible damages to the IC. At present, electrostatic discharge is one of the major causes of damage in the fabrication of deep sub-micron IC. To combat the problems resulting from ESD, on-chip ESD protection circuits are added to the input/output (I/O) pads of IC such as the complementary metal-oxide-semiconductor (CMOS) integrated circuit. However, the protective function of ESD protection circuits has seen quite a significant drop in its effectiveness with the rapid development of IC fabrication process. Hence, how to boost the effectiveness of ESD protection circuit is now a common goal in the electronics industry.
A number of ESD protection circuits has been proposed for protecting integrated circuits. For example, Charvaka Duvvury, S. Ramaswamy, A. Amerasekera, R. A. Cline, B. H. Anderson, and V. Gupta et. Al have issued an article called “Substrate Pump NMOS for ESD Protection Application”, PP7-17 in EOS/ESD Symposium, 2000. In it, a gate coupling NMOS ESD protection circuit has been proposed. However, this circuit does not have a pad-to-VDD ESD protection plan. Moreover, the input capacitor is non-uniform when the pad voltage changes. To address the input capacitor non-uniformity problem, Jerry Lin, C. Duvvury, B. Haroun, I. Oguzman, & A.Somoyalji et al have issued an article called “A Fail-Safe ESD Protection Circuit with 230 fF Linear Capacitance for High-Speed/High-precision 0.18 CMOS I/O Application”, PP 349-352 in IEEE IEDM, December 2002. Thus, an improved gate coupling NMOS ESD protection circuit has been developed. Yet, the design still has no specific arrangement for providing pad-to-VDD ESD protection.
To give more examples, Tung-Yang Chen & M. Ker have issued an article called “Substrate-Triggered ESD Protection Circuit without Extra Process Modification”, PP 295-501 in IEEE Journal of Solid-State Circuits, Vol. 38, No. 2, 2003. In the article, a substrate-triggered ESD protection circuit has been proposed. Thus, the feasibility of using a substrate bias to increase the ESD threshold value has been verified. In U.S. Pat. No. 6,072,219 and U.S. Pat. No. 6,465,768, some actual improvements or improved substrate-triggered ESD protection devices have been proposed. In others, such as the U.S. Pat. No. 5,652,689, U.S. Pat. No. 6,157,065 and U.S. Pat. No. 6,603,177, a number of structures having an ESD protection circuit formed underneath the bonding pad have been proposed. Furthermore, in U.S. Pat. No. 6,867,461, an ESD protection circuit that can be applied to an integrated circuit with power-down mode has been proposed.
Nevertheless, a pin-to-pin discharge sometimes occurs. That is, one particular pin may serve as a positive node while another pin may serve as a negative node so that an ESD zapping signal is added to the bonding pads of the positive and negative node. Due to the indirect ESD dissipation path in many conventional design techniques, only a weaker ESD threshold value can be provided. Furthermore, some of the integrated circuits may have a multiple of power sources. Since the multiple power sources are in separated and non-connected areas, an electrostatic discharge through a continuous charge dissipation path may be destroyed. Ultimately, an even worse ESD threshold value is obtained.