1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an MIS (Metal-Insulator-Semiconductor) structure.
2. Description of the Background Art
Improvements in both short channel characteristics and drive capability of MOSFETs are becoming increasingly difficult as device dimensions shrink. As a method to resolve this problem, a replacement sidewall technique has been suggested (in, for example, Japanese Patent Application Laid-open No. 2000-168323). The replacement sidewall technique is a technique for removing a sidewall after deep source/drain (deep S/D) implantation and activation annealing and then performing extension implantation and activation annealing for extension. This technique aims to resolve the problem of a conventional process that heat required for activation of deep S/D is applied also to extensions, and to satisfy both shallow junctions and low parasitic resistance.
In the replacement sidewall process, it is essentially preferable that a sidewall has a SiN/SiO2 multilayer structure. This is because, in the case of a SiO2 single-layer structure, an isolation oxide film also is etched at the time of removal of a sidewall, which arouses concern that an isolation region might recede significantly and thereby junction leakage properties might be worsened. In the case of the SiN/SiO2 multilayer structure, on the other hand, the SiO2 sidewall is thinner than in the case of the single-layer structure, and the gate edge is to be etched as well.
FIGS. 35 to 41 are schematic diagrams illustrating a process sequence of conventional MOSFET fabrication.
 less than Element Isolation Process greater than 
FIG. 35 shows a cross-section after completion of an element isolation process. On the major surface of a semiconductor substrate 1, an isolation oxide film 2 is formed for element isolation. The isolation oxide film 2 sections an element region of the semiconductor substrate 1. The isolation oxide film 2 may adopt trench isolation. In the structure shown in FIG. 35, well and channel are formed by impurity implantation. The well and channel, however, have no direct relation to the replacement sidewall process and thus not shown herein.
 less than Gate Insulating Film Formation Process greater than 
The element region of the semiconductor substrate 1 is subjected to gate oxidation.
 less than Gate Electrode Deposition Process greater than 
A polysilicon layer is formed on the upper surface of a film produced by the gate oxidation.
 less than Gate Electrode Formation Process greater than 
A resist is applied to a predetermined area of the upper surface of the polysilicon layer and a mask pattern of a gate electrode is transferred and developed. Polysilicon and oxide film are then etched (referred to as xe2x80x9cgate etchingxe2x80x9d) to form a gate electrode 3 as shown in FIG. 36. The gate electrode 3 is formed of a gate insulating film 4 and a polysilicon layer 5.
 less than Dummy Sidewall Formation Process greater than 
A dummy sidewall 6 (eventually to be removed) is formed as shown in FIG. 37. In the present example, the dummy sidewall 6 of a multilayer structure is formed by depositing an oxide film 7 and then a nitride film 8 on the whole surfaces of the gate electrode 3 and the semiconductor substrate 1 and etching back the films.
 less than Source and Drain Formation Process greater than 
Source and drain regions 9 (FIG. 38) are formed by ion implantation. This process is performed individually for NMOS and PMOS structures, for example by covering either one of the structures with a resist. Following this, thermal processing is performed to activate implanted impurities.
 less than Dummy Sidewall Processing Process greater than 
The nitride film 8 of the dummy sidewall 6 shown in FIGS. 37 and 38 is etched using phosphoric acid and completely removed (FIG. 39). After that, the oxide film 7 of the dummy sidewall 6 may be removed and reoxidation (referred to as xe2x80x9cgate reoxidationxe2x80x9d) may be performed for protection of the gate insulating film 4 at the gate edge.
 less than Source and Drain Extension Process greater than 
In the structure shown in FIG. 39, source and drain extension regions 10 are formed (FIG. 40). This process is performed individually for NMOS and PMOS structures, for example by covering either one of the structures with a resist. Following this, thermal processing is performed to activate implanted impurities.
 less than Sidewall Formation Process greater than 
A sidewall 11 is formed as shown in FIG. 41, for example by depositing and etching a nitride film 18 on the whole surface.
 less than Silicide Process greater than 
A metal such as cobalt or titanium is deposited to form a silicide layer on the upper surfaces of the source and drain regions 9 and the gate electrode 3.
 less than Interlayer Film Formation Process greater than 
Thereafter, an interlayer film, interconnections and the like are formed according to an ordinary semiconductor integrated circuit manufacturing method.
A sidewall of the SiN/SiO2 multilayer structure has another problem in that Si-exposed source/drain and gate have surface roughness, which is schematically illustrated with triangles in FIGS. 39 to 41. This is because phosphoric acid, which is commonly used in wet etching for removal of a SiN film, removes also a Si film (especially an impurity-doped Si film).
This surface roughness inhibits proper formation of silicide such as CoSi or TiSi and thus can become a cause of an abnormal increase in junction leakage current. Further, if silicide such as CoSi or TiSi is not formed properly and a pin hole is formed in the gate, for example, Co or Ti that was left without silicide formation will reach the gate insulating film, leading to degradation in the reliability of the gate insulating film.
An object of the present invention is to provide a method of manufacturing a semiconductor device which, by forming a protective oxide film, can prevent surface roughness of a semiconductor substrate and a gate electrode due to phosphoric acid and can achieve both reductions in junction leakage current (low power consumption) and improvements in the reliability of a gate oxide film (high reliability), without losing original advantages of a replacement sidewall process.
According to the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (f). The step (a) is to form a gate insulating film on a major surface of a semiconductor substrate and a gate electrode on the semiconductor substrate through the gate insulating film. The step (b) is to form a dummy sidewall to cover side surfaces of the gate electrode and the gate insulating film and a predetermined area of the major surface which extends laterally from the side surfaces. The step (c) is to form an impurity region by introducing an impurity into the major surface using the dummy sidewall and the gate electrode as masks. The step (d) is to form a protective oxide film on an upper surface of the gate electrode and on the major surface using the dummy sidewall as a mask and is performed either prior to or after the step (c). The step (e) is to reduce a thickness of the dummy sidewall and is performed after the step (d). The step (f) is to extend the impurity region under part of the gate insulating film using a dummy sidewall left after the step (e) and the gate electrode as masks.
When the dummy sidewall and the impurity region are once formed and then the dummy sidewall is removed to extend the impurity region, the removal of the dummy sidewall is performed after formation of a protective film on the gate electrode and on the major surface of the impurity region or semiconductor substrate. This efficiently prevents conventional surface roughness of the upper surface of the gate electrode and the impurity region due to the removal of the dummy sidewall. By avoiding surface roughness of the semiconductor substrate and the gate electrode, both reductions in junction leakage current (low power consumption) and improvements in the reliability of the gate insulating film (high reliability) can be achieved without losing original advantages of the replacement sidewall process (e.g. suppression of short channel effect and improvements in drive capability).
Preferably, the step (d) is performed after the step (b) and prior to the step (c).
Since heat of protective oxidation is not applied to the impurity region introduced by impurity implantation and also impurities in the impurity region and the gate electrode are activated in a later step, compatibility between suppression of impurity diffusion and an increase in the rate of activation can be increased with ease. By in this way, preventing excess impurity diffusion in, for example, the source and drain regions, it is possible to prevent a reduction in threshold voltage and an increase in variation of threshold voltage due to a deterioration in short channel characteristics and excess impurity diffusion in the gate electrode (caused by surface roughness of the gate insulating film due to gate impurities).
Preferably, the method of manufacturing a semiconductor device further includes the step (g) of accelerating oxidation by implanting an impurity into the gate electrode and the major surface using the dummy sidewall as a mask. The step (g) is performed after the step (b) and prior to the step (d).
Since, by executing the step (g), the protective oxide film of a predetermined film thickness can be formed in short time in the step (d), excess impurity diffusion in the impurity region and in the gate electrode can be suppressed. By in this way, preventing excess impurity diffusion in, for example, the source and drain regions, it is possible to prevent a reduction in threshold voltage and an increase in variation of threshold voltage due to a deterioration in short channel characteristics and excess impurity diffusion in the gate electrode (caused by surface roughness of the gate insulating film due to gate impurities). Besides, channel impurity diffusion can also be suppressed, which makes it easy to form an advanced channel structure.
Preferably, the method of manufacturing a semiconductor device further includes the step (h) of raising the major surface by epitaxial growth using the dummy sidewall and the gate electrode as masks. The step (h) is performed after the step (b) and prior to the step (d). In the step (d), a protective oxide film is formed on a structure obtained by the step (h), using the dummy sidewall as a mask.
Since the protective oxide film is formed after raising the impurity region or the major surface by epitaxial growth, only raised portions are eroded and the semiconductor substrate and the like are protected from erosion.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.