The present invention relates to a technique for fabricating a semiconductor integrated circuit device and a testing apparatus therefor; and, more specifically, the invention relates to a technique that can be applied, for example, to a burn-in test and probe test of a semiconductor integrated circuit device, and effectively can be applied particularly to a burn-in test of a semiconductor device in the wafer condition, that is, to a so-called wafer level burn-in test.
The present invention relates to a test technique and a fabrication technique applicable to a semiconductor integrated circuit device. According to investigations carried out by the inventors of the present invention regarding burn-in test techniques, for example, the official gazette of the Japanese Laid-Open Patent Applications Nos. HEI 11(1999)-97494, 9(1997)-148389 and xe2x80x9cNIKKEI MICRO-DEVICExe2x80x9d, January 2000, pages 148 to 153 have been found to be relevant.
The official gazette of Japanese Laid-Open Patent Application No. HEI 11(1999)-97494 discloses a technique used to equalize the pushing pressure during testing by dividing the pushing member in order to share the pushing load between a plurality of places on the plane on the opposite side of the wafer relative to the pushing member when a plurality of probes provided on a membrane are pushed toward the wafer using the pushing member in the burn-in test of the wafer.
The official gazette of Japanese Laid-Open Patent Application No. HEI 9(1997)-148389 discloses a technique that uses a beam that maintains it elasticity toward the upper and lower directions on a silicon substrate with a micro-machining technique and also employs a micro-contact pin at an end of this beam in the layout provided at a position opposed to the electrode of a wafer, with a conductive thin film process being executed at the end of such micro-contact pin.
The reference xe2x80x9cNikkei MICRO-DEVICE, January, 2000xe2x80x9d describes a system using a TPS (Three Parts Structure) probe, consisting of three parts including a multilayer wiring board, a thin film sheet with a bump and an anisotropic conductive rubber member, and a system in which a multilayer wiring board and a probe terminal are provided, the probe terminal having a structure in which a copper post is provided through a resin sheet, so that when pressure is applied, this copper post is crushed, whereby an unequal height of electrodes is equalized.
The inventors of the present invention have considered the technique used in the burn-in test as explained above and have established following conclusions.
For example, available semiconductor integrated circuit device test techniques include a burn-in test for screening a chip that may change to a defective chip when subjected to temperature and voltage stresses under a higher temperature atmosphere, a function test to check whether a device operates as specified for a predetermined function, and a probe test for determining good/no-good products by executing a test to determine the DC operation characteristic and AC operation characteristic thereof.
In recent years, in the burn-in test of a semiconductor integrated circuit device, the wafer level burn-in technique used to conduct a burn-in test in the wafer condition has been based on the requirement for coverage of wafer delivery (discrimination of quality) and KGD (Known Good Die)(improvement of yield of MCP (Multi-Chip Package)) and for relief of a no-good product for burn-in, feed-back of test data of a no-good product for burn-in and reduction of total cost or the like.
In this wafer level burn-in process, it is essential to solve certain technical problems, such as provision of a pushing mechanism that is able to realize equal pressurizing of the entire surface of a wafer, the provision of a wafer heating and temperature control mechanism, the requirement for a probe of ten thousand or more pins for covering the entire surface of the wafer, the need for absorption of warp and wave of the wafer surface and unequal heights of the probe, the dependence on the thermal expansion coefficient under higher temperature conditions, the layout of many wires, the necessity for gathering of input signals, the requirement for probe alignment to the entire surface of the wafer, the disconnection of a defective chip and cut-off of an over-current, and a contact check for the entire surface of wafer.
In regard to the burn-in test, to solve such technical problems, there has been proposed, for example, a technique described in the xe2x80x9cNIKKEI MICRO-DEVICE, January, 2000xe2x80x9d. However, this technique is assumed to include various problems, in that a film forming apparatus to eliminate a defective chip is required in the system utilizing the TPS probe described in the above publication, the wafer level burn-in may be executed only in the last stage of a probe test and laser relief, the contact resistance of a thin film sheet with a bump may be increased easily depending on the number of times of contact, a partial repair is impossible in the integrated structure, and the operation life of anisotropic conductive rubber is rather short.
Moreover, in the system utilizing the technique including the multilayer wiring board and probe terminal described in xe2x80x9cNIKKEI MICRO-DEVICE, January, 2000xe2x80x9d, there is assumed to be a problem in that a resin sheet is used only for a gold pad and this sheet is thrown away after it is once used.
It is an object of the present invention to provide a method of fabricating a semiconductor integrated circuit device and a method of testing the same device for realizing reduction in cost by employing a divided contactor integrating system, for example, in the burn-in test and probe test, particularly in wafer level burn-in, thereby realizing uniform contact of the divided contactors on the entire surface of the wafer, thereby enabling individual repair for each divided contactor and reducing the manufacturing cost through improvement of the yield of divided contactors.
The above and the other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
The typical aspects of the invention among those disclosed in this specification will be briefly explained below.
(1) A testing apparatus of a semiconductor integrated circuit device comprises the following structural elements:
(a) a plurality of test styluses used to conduct an electric test in contact with a plurality of terminals provided on the first main plane of a wafer on which a plurality of semiconductor integrated circuit devices are formed;
(b) a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses; and
(c) a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each tip thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate.
(2) In the testing apparatus of the semiconductor integrated circuit device of item (1), each plate of a plurality of wiring/stylus composite plates allocates test styluses to measure a plurality of chip regions formed on the first main plane of the wafer.
(3) In the testing apparatus of the semiconductor integrated circuit device of item (2), a plurality of terminals of the first chip region in a plurality of chip regions formed on the first main plane of the wafer are allocated to measure in contact with both test styluses of the first and second wiring/stylus composite plates among a plurality of wiring/stylus composite plates.
(4) In the testing apparatus of the semiconductor integrated circuit device of item (3), the number of wiring/stylus composite plates is 4 or more.
(5) In the testing apparatus of the semiconductor integrated circuit device of item (3), the number of wiring/stylus composite plates is 9 or more.
(6) In the testing apparatus of the semiconductor integrated circuit device of item (5), the number of chip regions to be measured with each plate among a plurality of wiring/stylus composite plates is 9 or more.
(7) In the testing apparatus of the semiconductor integrated circuit device of item (5), the number of chip regions to be measured with each plate among a plurality of wiring/stylus composite plates is 16 or more.
(8) In the testing apparatus of the semiconductor integrated circuit device of item (7), a plurality of the wiring/stylus composite plates includes a plate member mainly composed of silicon as the main structural element.
(9) In the testing apparatus of the semiconductor integrated circuit device of item (8), the wafer includes a plate member mainly composed of silicon as the main structural element.
(10) In the testing apparatus of the semiconductor integrated circuit device of item (9), the electric test is a burn-in test.
(11) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) preparing for a plurality of test styluses used to conduct electric test in contact with a plurality of terminals provided on the first main plane of wafer on which a plurality of semiconductor integrated circuit devices are formed, a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses, and a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each end point thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate; and
(b) conducting an electric test of a plurality of chip regions with a plurality of test styluses of each plate among a plurality of wiring/stylus composite plates in contact with a plurality of terminals of the plurality of chip regions formed on the first main plane of the wafer.
(12) In the method of fabricating the semiconductor integrated circuit device of item (11), the electric test is a burn-in test.
(13) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) preparing for a plurality of test styluses used to conduct electric test in contact with a plurality of terminals provided on the first main plane of wafer on which a plurality of semiconductor integrated circuit devices are formed, a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses, and a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each end point thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate; and
(b) conducting an electric test by bringing a plurality of styluses of both first and second wiring/stylus composite plates among a plurality of wiring/stylus composite plates into contact with a plurality of terminals of the first chip region among a plurality of chip regions formed on the first main plane of the wafer.
(14) In the method of fabricating the semiconductor integrated circuit device of item (13), the electric test is a burn-in test.
(15) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) preparing for a plurality of test styluses used to conduct electric test in contact with a plurality of terminals provided on the first main plane of wafer on which a plurality of semiconductor integrated circuit devices are formed, a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses, and a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each end point thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate; and
(b) conducting an electric test for a plurality of chip regions by bringing a plurality of test styluses of each plate among a plurality of wiring/stylus composite plates into contact with a plurality of terminals of a plurality of chip regions including a BIST circuit formed on the first main plane of the wafer.
(16) In the method of fabricating the semiconductor integrated circuit device in item (15), the electric test is a burn-in test.
(17) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
(a) preparing for a plurality of test styluses used to conduct electric test in contact with a plurality of terminals provided on the first main plane of wafer on which a plurality of semiconductor integrated circuit devices are formed, a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses, and a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each end point thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate; and
(b) conducting an electric test for a plurality of chip regions by bringing a plurality of test styluses of each plate among a plurality of wiring/stylus composite plates into contact, under a vacuum or evacuated condition, with a plurality of terminals of a plurality of chip regions formed on the first main plane of the wafer.
(18) In the method of fabricating the semiconductor integrated circuit device of item (17), the electric test is the burn-in test.
(19) There is provided a wiring/stylus composite plate on which a plurality of test styluses are provided and the plate is divided into a plurality of regions for a sheet of test wafer.
(20) In the testing apparatus of the semiconductor integrated circuit device of item (19), guide frames are provided to integrate the divided wiring/stylus composite plate and the wiring/stylus composite plate integrated with one guide frame forms an integrated contactor on the entire surface of one wafer corresponding to a sheet of test wafer (hereinafter referred to as a test wafer).
(21) In the testing apparatus of the semiconductor integrated circuit device of item (20), the divided wiring/stylus composite plate is formed of a material having the same thermal expansion coefficient as that of the test wafer.
(22) In the testing apparatus of the semiconductor integrated circuit device of item (21), the test wafer is formed of a silicon substrate and the divided wiring/stylus composite plate is composed of a silicon substrate.
(23) In the testing apparatus of the semiconductor integrated circuit device of item (21), the test wafer is formed of a silicon substrate and the divided wiring/stylus composite plate is formed of a silicon membrane sheet.
(24) In the testing apparatus of the semiconductor integrated circuit device of item (20), the guide frame is formed of a material having a thermal expansion coefficient that is approximated to that of the test wafer.
(25) In the testing apparatus of the semiconductor integrated circuit device of item (24), the test wafer is formed of a silicon substrate and the guide frame is formed of 42 alloy or nickel alloy.
(26) In the testing apparatus of the semiconductor integrated circuit device of item (20), a plurality of probes of the divided wiring/stylus composite plate are respectively formed in a pyramidal shape with a micro-machining technique, such as an anisotropic etching process.
(27) In the testing apparatus of the semiconductor integrated circuit device of item (26), the probes of the wiring/stylus composite plate may respectively be deformed at the periphery thereof with pressure.
(28) In the testing apparatus of the semiconductor integrated circuit device of item (27), the periphery of each probe of the wiring/stylus composite plate may be deformed with a mechanical pressurizing system and the probe is brought into electrical contact, under the deformed condition, with each test pad of each chip of the test wafer with a predetermined pressure.
(29) In the testing apparatus of the semiconductor integrated circuit device of item (27), the periphery of each probe of the wiring/stylus composite plate may be deformed with a vacuum or evacuation pressurizing system and each probe is electrically brought into contact, in the deformed condition, with each testing pad of the test wafer.
(30) In the testing apparatus of the semiconductor integrated circuit device of item (20), the divided areas of the divided wiring/stylus composite plate are deviated in the position from the scribe area of each chip of the test wafer.
(31) In the testing apparatus of the semiconductor integrated circuit device of item (20), the respective plates of the divided wiring/stylus composite plate correspond to a plurality of chip units of the test wafer.
(32) In the testing apparatus of the semiconductor integrated circuit device of item (20), the respective plates of the divided wiring/stylus composite plate may be repaired individually.
(33) In the testing apparatus of the semiconductor integrated circuit device of item (20), the divided wiring/stylus composite plates respectively have positioning marks.
(34) In the testing apparatus of the semiconductor integrated circuit device of item (20), the respective chips of the test wafer have a BIST circuit.
(35) In the testing apparatus of the semiconductor integrated circuit device of item (34), a plurality of testing pads on the chip hold the other pads and are allocated separately in the periphery.
(36) In the testing apparatus of the semiconductor integrated circuit device of item (19), there are comprised a plurality of divided wiring/stylus composite plates, a guide frame for integrating the divided wiring/stylus composite plates, a multilayer wiring substrate electrically connected to the divided wiring/stylus composite plates, an elastomer for absorbing a fluctuation of probe heights of the divided wiring/stylus composite plates and an upper cover and a lower cover for packing, by holding from the upper and lower sides, the test wafer via the wiring/stylus composite plates, guide frame, multilayer wiring substrate and elastomer.
(37) In the testing apparatus of the semiconductor integrated circuit device of item (36), there is comprised a burn-in substrate that is electrically connected to the multilayer wiring substrate to execute the burn-in test for the test wafer.
(38) In the testing apparatus of the semiconductor integrated circuit device of item (36), the guide frame, elastomer and upper and lower covers are positioned with a positioning mechanism.
(39) In the testing apparatus of the semiconductor integrated circuit device of item (36), the multilayer wiring substrate has a structure to lay many wirings and focuses the input signal.
(40) In the testing apparatus of the semiconductor integrated circuit device of item (36), the multiple wiring substrate is provided with a protection resistor and capacitor.
(41) In the testing apparatus of the semiconductor integrated circuit device of item (36), the upper cover and lower cover are provided with a vacuum or evacuation absorbing mechanism to equalize warp and wave of the test wafer.
(42) In the testing apparatus of the semiconductor integrated circuit device of stem (36), the upper cover and lower cover are provided with a temperature control mechanism for controlling the temperature condition of the test wafer.
(43) In the testing apparatus of the semiconductor integrated circuit device of item (37), the burn-in substrate is provided with an over-current cut-off circuit.
(43) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
preparing for a wiring/stylus composite plate that is provided with a plurality of test styluses and divided into a plurality of plates for a sheet of test wafer; and
testing the electrical characteristics of each chip by integrating the divided wiring/stylus composite plates with a guide frame and bringing each probe of each wiring/stylus composite plate integrated with the guide frame into electrical contact with each testing pad of each chip of a sheet of test wafer.
(45) In the method of fabricating the semiconductor integrated circuit device of item (44), the step of testing the electrical characteristics is a burn-in test process.
(46) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
preparing for a wiring/stylus composite plate that is provided with a plurality of test styluses and divided into a plurality of plates for a sheet of test wafer with this dividing line deviated in position from the scribe line for each chip of the test wafer; and
testing the electrical characteristics of each chip by integrating the divided wiring/stylus composite plates with a guide frame and bringing each probe of each wiring/stylus composite plate integrated with the guide frame into electrical contact with each testing pad of each chip of a sheet of test wafer.
(47) In the method of fabricating the semiconductor integrated circuit device of item (46), the step of testing the electrical characteristic is a burn-in test process.
(48) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
preparing for a wiring/stylus composite plate that is provided with a plurality of test styluses and is divided into a plurality of plates for a sheet of test wafer; and testing the electrical characteristics of each chip by integrating the divided wiring/stylus composite plates with a guide frame and bringing each probe of each wiring/stylus composite plate integrated with the guide frame into electrical contact with each testing pad of each chip including a BIST circuit of a sheet of test wafer.
(49) In the method of fabricating the semiconductor integrated circuit device of item (48), the step of testing the electrical characteristic is a burn-in test process.
(50) A method of fabricating a semiconductor integrated circuit device comprising the steps of:
preparing for a wiring/stylus composite plate that is provided with a plurality of test styluses and is divided into a plurality of plates for a sheet of test wafer; and
testing the electrical characteristics of each chip by integrating the divided wiring/stylus composite plates with a guide frame and bringing each probe of each wiring/stylus composite plate integrated with the guide frame into electrical contact with each testing pad of each chip of a sheet of test wafer under the vacuum or evacuated condition.
(51) In the method of fabricating the semiconductor integrated circuit device of item (50), the step of testing the electrical characteristic is a burn-in test process.
Therefore, the testing apparatus and the method of fabricating the semiconductor integrated circuit device provide the following effects.
(1) The wiring/stylus composite plate is produced by dividing it into a plurality of plates for a sheet of test wafer by providing a plurality of divided wiring/stylus composite plates and then forming a full wafer surface simultaneous contactor through integration of these divided wiring/stylus composite plates with one guide frame. Thereby, fabrication becomes much easier and the fabrication yield is enhanced. As a result, the fabrication cost can be reduced.
Moreover, since the divided wiring/stylus composite plates are free from the size of a test wafer, the existing facilities may be used also for a wafer of large size. Thereby, the fabrication cost of the contactor used by the full wafer surface simultaneous contactor system can be reduced.
In addition, the divided wiring/stylus composite plates can individually move when they are integrated with the guide frame. These plates can therefore independently equalize the warp and wave of the test wafer.
(2) Since the fabrication facilities of the LSI may be used and a fine processing accuracy, such as that of LSI fabrication, is not required, by forming the divided wiring/stylus composite plates with a material having a thermal expansion coefficient that is the same as that of the test wafer, the existing facilities for fabrication of the LSI may be used as the facilities for fabricating the wiring/stylus composite plate, and thereby the fabrication cost can be reduced.
Moreover, since the test wafer and silicon contactor exhibit a similar thermal expansion, even for the temperature condition of a burn-in process, sufficient probe alignment accuracy for the full surface of a wafer can be obtained.
(3) Since the guide frame also has a thermal expansion coefficient similar to that of the test wafer, by forming the guide frame with a material having a thermal expansion coefficient similar to that of the test wafer, the probe alignment to the full surface of the wafer can be controlled within an allowable range.
(4) The probe can be formed with a pyramidal shape corresponding to employment of a multi-pin structure or narrow-in structure by forming the probe of the divided wiring/stylus composite plates with a micro-machining technique, such as anisotropic etching or the like.
(5) The probe can be equally brought into contact with the test wafer with a predetermined pressure by deforming the surrounding portion of the probe of the divided wiring/stylus composite plates using a mechanical pressurizing system or a vacuum or evacuation pressurizing system.
(6) A large size guide frame for integrating the wiring/stylus composite plates can be attained, without relation to the trend to reduce the scribe area of the test wafer, by deviating the dividing area of the divided wiring/stylus composite plates from the scribe area of each chip of the test wafer.
Moreover, the scribe area tends to be reduced to improve the number of chips to be obtained from the test wafer, but such tendency can be covered without any problem.
In addition, since the size and cutting accuracy of the divided wiring/stylus composite plates is not restricted by the scribe area, the degree of freedom of design can be much improved.
(7) Since the wiring/stylus composite plate may be set to a certain size in response to the trend to reduce the size of a chip by providing the divided wiring/stylus composite plates depending on the unit of a plurality of chips of the test wafer, each wiring/stylus composite plate may be fabricated easily.
(8) Since a fault of a burn-in cassette in the fabrication process can be recovered easily, and, moreover, a fault during use in the mass-production line can also be repaired in a unit of each wiring/stylus composite plate by individually repairing the divided wiring/stylus composite plates, the fabrication cost and maintenance cost can also be reduced.
(9) Since each divided wiring/stylus composite plate has a positioning mark, assembling for integrating the wiring/stylus composite plates with the guide frame can be done easily.
(10) Since each chip of the test wafer has a BIST circuit, a test pattern can be generated within each chip. Thereby, the number of test pads of each chip can be reduced and allocation of test pads can be optimized.
Moreover, since the number of probes of the divided wiring/stylus composite plates can be minimized, allocation of probes can also be optimized.
(11) Since the test pads can be allocated by keeping a certain interval for the narrow pitch structure by holding the test pads on each chip with the other pads and allocating these test pads in isolation in the peripheral area, the influence on the fabrication of wiring/stylus composite plate can also be minimized.
(12) The wafer full surface simultaneous contact system based on use of a divided contactor integration type device can be structured as a cassette structure by pressing the test wafer with upper and lower covers from the upper and lower directions via the divided wiring/stylus composite plates, guide frame, multilayer wiring substrate and elastomer.
(13) The burn-in substrate can be connected easily to the cassette structure testing apparatus by comprising a burn-in substrate connected to the multilayer wiring substrate.
(14) Since the guide frame, elastomer, and upper and lower covers can be positioned easily by using a positioning mechanism for these elements, the cassette structure testing apparatus can be assembled easily.
(15) Since the input/output signals between the wiring/stylus composite plate and burn-in substrate can be inputted or outputted together, because the multilayer wiring substrate has a structure which is able to lay many wirings and gather the input signals, the number of signal lines between the multilayer wiring substrate and burn-in substrate can be reduced, and a signal line may be laid easily.
(16) Malfunction due to variation of the power supply voltage and noise can be prevented by mounting a protection resistor and capacitor on the multilayer wiring substrate.
(17) The test wafer is attracted with the flat surface of the lower cover, and thereby warp and wave of the test wafer can be equalized by providing a vacuum or evacuation attracting mechanism for the upper and lower covers.
(18) Since the test wafer can be heated up to a predetermined temperature by providing a temperature control mechanism for the upper and lower covers, the temperature condition of the test wafer can be controlled.
(19) Since an over-current of each chip of the test wafer can be cut off by providing an over-current cut-off circuit for the burn-in substrate, damage and breakdown of the integrated circuit and wiring/stylus composite plate formed on each chip can be prevented by isolating a defective chip and controlling generation of latch-up.