Traditional field effect transistors (FET's) are familiar conventional devices commonly incorporated as a fundamental building block into the intricate circuitry of integrated circuit (IC) chips. Downward scaling of FET dimensions has improved circuit performance and increased the functional capability of FET's packed on an IC chip. However, continued dimensional reductions may be hampered by the size limitations associated with traditional materials and the costs associated with lithographic patterning.
Carbon nanotubes are nanoscale high-aspect-ratio cylinders consisting of hexagonal rings of carbon atoms that may assume either a semiconducting electronic state or a conducting electronic state. A conventional method for synthesizing carbon nanotubes suitable for forming FET arrays utilizes a chemical vapor deposition (CVD) process. Specifically, the CVD process directs a flow of a carbonaceous reactant to a catalyst material located on the planar substrate, where the reactant is catalyzed to synthesize the carbon nanotubes. The carbon nanotubes grow and lengthen by insertion of activated carbon atoms at the interface with the catalyst material. The carbon nanotubes are then harvested for use in various end applications.
FET's have been successfully fabricated using a semiconducting carbon nanotube as a channel region and forming contacts at opposite ends of the semiconducting carbon nanotube extending between a gold source electrode and a gold drain electrode situated on the surface of a substrate. A gate electrode is defined in the substrate underlying the carbon nanotube and generally between the source and drain electrodes. An oxidized surface of the substrate defines a gate dielectric situated between the buried gate electrode and the carbon nanotube.
Nanotube FET's should switch reliably while consuming significantly less power than a comparable silicon-based device structure due to the small dimensions of the carbon nanotube. Such FET's have been successfully formed under controlled laboratory conditions by manipulating single semiconducting carbon nanotubes using an atomic force microscope for precision placement between the source and drain electrodes. Nanotube FET's have also been formed by coincidental placement of a single semiconducting carbon nanotube between the source and drain electrodes from among a randomly dispersed group of semiconducting carbon nanotubes.
Large arrays of FET's are demanded in the fabrication and mass production of IC chips. Conventional manipulation or coincidental placement of carbon nanotubes cannot satisfy the requirements for mass production. Unfortunately, as the carbon nanotubes lengthen, the flow of CVD reactant(s) to the catalyst material becomes restricted, which slows or even halts nanotube synthesis. In certain FET designs, the catalyst material may be located at the base of a high-aspect-ratio opening, which further restricts reactant flow.
What is needed, therefore, is a method of synthesizing an array of FET's incorporating carbon nanotubes compliant with mass production techniques and in which a CVD nanotube-synthesis process transpiring at a catalyst material integrated into the FET structure is not limited by reactant flow restrictions.