FIG. 14 illustrates a schematic cross section of a semiconductor device having contact holes for capacitors manufactured according to a conventional method. FIG. 15A through FIG. 15C, FIG. 16A through FIG. 16C and FIGS. 17A through 17C are cross sectional views illustrating, in order of manufacturing processes, the conventional method of fabricating lower electrodes of capacitors of a semiconductor device. FIG. 18 illustrates a conventional exposure mask used for fabricating capacitor contact holes.
As shown in FIG. 14, in a conventional semiconductor device 100, element forming regions are defined on a semiconductor substrate 101 by using an insulating film 102 for element isolation, i.e., an element isolation film or an element isolation insulating film. In each of the element forming regions, source/drain regions 104 and a gate region 105 are formed. Each of the source/drain regions 104 is a region used as a source region or a drain region. On the gate electrode 105, a lower electrode 111 is formed, and the lower electrode 111 is coated with a capacitor insulator film 112. Also, on the capacitor insulator film 112, there is formed an opposing electrode 113. The source/drain regions 104 are wired by using a wiring layer 114.
Now, an explanation will be made on a method of manufacturing the above-mentioned conventional semiconductor device. First, as shown in FIG. 15A, the insulating film for element isolation 102 is formed on the surface of the semiconductor substrate 101. Then, in each of the element forming regions defined by the insulating film for element isolation 102, the source/drain regions 104 and the gate electrode 105 are formed. Also, on whole surface of the semiconductor substrate 101, a first insulating film 103 is formed. Further, a first resist film 106 is formed on the first insulating film 103. The first resist film 106 is used to form a mask for forming a capacitor contact hole 108 (FIG. 16A) in the first insulating film 103.
Next, by using an exposure mask 115 shown in FIG. 18, which exposure mask has a minute opening 116, an opening portion 107 is formed by performing an exposure on the first resist film 106, after registering the opening 116 of the exposure mask 115 with the location of the capacitor contact hole 108. That is, as shown in FIG. 15B, the opening 107 of the first resist film 106 is formed at a location of the first insulating film 103 in which the capacitor contact hole 108 is to be formed.
Then, as shown in FIG. 15C, by using the first resist film 106 as a mask, portions of the first insulating film 103 are selectively removed by etching and so on.
Thereafter, the first resist film 106 is removed, and, as shown in FIG. 16A, the capacitor contact holes 108 are formed in the first insulating film 103.
As shown in FIG. 16B, a conductive film 109 is then formed on the first insulating film 103 such that the capacitor contact holes 108 are filled with the material of the conductive film 109. On the conductive film 109, a second resist film 110 is formed. The second resist film 110 is used as a mask when the conductive film 109 is patterned to form the lower electrode 111.
The second resist film 110 is exposed by using an exposure mask not shown in the drawing after registering the exposure mask with the structure already formed on the semiconductor substrate to form a resist pattern of the second resist film 110 as shown in FIG. 16C.
Next, as shown in FIG. 17A, portions of the conductive film 109 are selectively removed by etching and so on by using the resist pattern of the second resist film 110 as a mask.
Then, as shown in FIG. 17B, the remainder of the second resist film 110 are removed and the lower electrodes 111 constituted of the remainder portion of the conductive film 109 are formed.
Thereafter, an insulating film and a conductor film are sequentially formed on whole surface of the substrate, and are patterned by using photolithography and etching. Thereby, as shown in FIG. 17C, a capacitor insulator film 112 on the lower electrode 111 and an opposing electrode 113 on the capacitor insulating film 112 are formed. Then, an interlayer insulating film 117 is formed on whole surface of the substrate. At each location of the interlayer insulating film 117 corresponding to the source/drain region 104, a through hole 118 is formed by using photolithography and etching, and the like. A wiring layer 114 is formed such that the through holes 118 are filled therewith, and is patterned by using photolithography and etching, and the like. By these processes, a semiconductor device shown in FIG. 17C is fabricated.
However, in the conventional method of manufacturing a semiconductor device, minute opening patterns had to be formed in an exposure mask 115 to fabricate minute capacitor contact holes, i.e., contact holes for coupling capacitor electrodes 111 with the drain/source regions 104. Since the size of each opening of the exposure mask was very small and resist patterns formed on a substrate by using such exposure mask was also very small, it was difficult to obtain sufficient exposure margin. Therefore, it was difficult to realize high yield of semiconductor manufacturing.