1. Technical Field
The present invention relates to integrated circuits in general, and in particular to Chalcogenide memory devices. Still more particularly, the present invention relates to a method for manufacturing contacts for a Chalcogenide memory device.
2. Description of the Prior Art
The use of phase change materials that can be electrically switched between a generally amorphous first structural state and a generally crystalline second structural state for electronic memory applications is well-known in the art. Phase change materials may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states.
Some phase change materials exhibit different electrical characteristics according to their state. For example, Chalcogenide materials exhibit a lower electrical conductivity in its amorphous state than it does in its crystalline state. The Chalcogenide materials for making memory cells are typically selected from the group of tellurium, selenium, antimony, and germanium. Such Chalcogenide materials can be switched between numerous electrically detectable conditions of varying resistivity in nanosecond time periods by using picojoules of energy. The resulting memory cell is truly non-volatile and will maintain the integrity of the stored information without the need for periodic signal refresh.
The operation of Chalcogenide memory cells requires that a region of the Chalcogenide memory material, called the Chalcogenide active region, be subjected to a current pulse with a current density typically between 105 and 106 amperes/cm2. Such current density may be accomplished by making a small opening, such as a via or contact, in a dielectric material that is itself deposited onto a lower electrode material. The Chalcogenide material is then deposited over the dielectric material and into the via to contact with the lower electrode material. A top electrode material is then deposited over the Chalcogenide material. Carbon is a commonly used electrode material although other materials, such as molybdenum and titanium nitride, have also been used.
The size of the Chalcogenide active region is primarily defined by the volume of Chalcogenide material that is contained within the via delineated by the opening in the dielectric material. The upper portion of the Chalcogenide material not contained within the via acts as an electrode that in turn contacts with the upper electrode material. The Chalcogenide active region makes contact with the lower electrode at an interface area that is substantially equal to the cross sectional area of the via. As a result of such configuration, the interface area of the Chalcogenide material within the Chalcogenide active region is subjected to the high current density required for the operation of the Chalcogenide memory cell. This is an undesirable situation because the high current density at the interface area of the Chalcogenide active region with the lower electrode causes mixing of the lower electrode material with the Chalcogenide material of the Chalcogenide active region due to heating and electrophoretic effects. More specifically, the mixing of the electrode material with the Chalcogenide material in the Chalcogenide active region causes instability of the Chalcogenide memory cell during operation.
The switching voltages, currents, and powers of a Chalcogenide memory element are believed to be scalable with device size or contact area. With current semiconductor processing technology, the minimum achievable dimension of a contact for a small area Chalcogenide memory device is limited by lithography tools, which is approximately 0.15 umxc3x970.15 um. Such dimension will cause switching currents, voltages, and switching times to be too large and cycle life to be too small for integration with leading edge silicon semiconductor processing. Consequently, it is desirable to provide an improve method for manufacturing smaller contacts for a Chalcogenide memory device.
In accordance with a preferred embodiment of the present invention, a via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer.
Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer. After directionally removing the nitride layer to form a spacer at the exposed edge of the third oxide layer, the third oxide layer is removed to expose the spacer. The conductive layer is then etched to remove a portion of the conductive layer not underneath the spacer. The portion of the conductive layer underneath the spacer resembles a matchstick. The spacer is then removed to expose the matchstick-like conductive layer portion with a small top surface contact area. A final oxide layer is deposited on the exposed matchstick-like conductor and surrounding oxide layer. A chemical-mechanical polishing process is used to remove the final oxide to a depth that exposes the small top area of the matchstick-like conductor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.