1. Field of the Invention
The present invention generally relates to a method of making nonvolatile semiconductor memory devices such as an EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory) or a flash memory. More particularly, it relates to a method of fabricating a nonvolatile memory device having a reduced capacitance between floating gate and substrate.
2. Description of the Related Arts
High-density nonvolatile memory devices have been receiving much attention in many fields. One of the most important factors is the low cost of the reduced size of each memory cell. However, it is very difficult to shrink the cell size in the fabrication of nonvolatile memory cells when conventional local oxidation (LOCOS) isolation technique is used. The isolation structure formed by this technique has very large dimensions and thus limits the miniaturization of memory cells.
Another isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of nonvolatile memory devices to reduce the cell size. The conventional field oxides are replaced by STI structures so that the device integration can be effectively improved. However, as component dimensions continue to shrink, the surface area of floating gates also shrinks. This leads directly to a decrease in capacitance of the effective capacitor formed between the floating gate layer and the control gate layer. This decrease in effective capacitance results in a reduction of the capacitive coupling ratio, a parameter that describes the coupling to floating gate of the voltage applied to control gate. The poorly-coupled voltage to floating gate limits the programming and accessing speed characteristics of the memory device.
The capacitive coupling ratio Cp is defined by:   Cp  =      Ccf          Ccf      +      Cfs      
where Ccf is capacitance between the control gate and the floating gate; and Cfs is capacitance between the floating gate and the semiconductor substrate.
In order to gain programming and accessing speeds in nonvolatile memories, many attempts have been made to increase the coupling ratio. It can be understood from the above equation that when the capacitance Ccf between the control gate and the floating gate increases, the coupling ratio Cp increases. Therefore, the coupling ratio Cp is generally increased by increasing the capacitor area between the floating gate and control gate, which increases the capacitance Ccf, and therefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909 discloses a method for forming a stacked gate of a flash memory cell. The coupling ratio of the stacked gate is increased by forming a conductive spacer. The conductive spacer, which is a portion of the floating gate, increases the capacitor area between the floating gate and control gate. As further background for the manufacture of a nonvolatile memory device, attention is directed to U.S. Pat. Nos. 6,172,396 and 6,180,459.
In the present invention, a high coupling ratio is accomplished by reducing the capacitance Cfs between the floating gate and the semiconductor substrate. The effect is the same as increasing the capacitance Ccf between the control gate and the floating gate.
An object of the invention is to provide a method of making a nonvolatile memory device having a reduced capacitance between the floating gate and the substrate. The reduction of capacitance between the floating gate and the substrate results in a high capacitive coupling ratio of the memory device.
Another object of the invention is to provide a method for making a nonvolatile device having a reduced size floating gate with a gate width beyond lithography limits.
The above objects are accomplished by providing a method of making a nonvolatile memory device comprising the steps of: providing a substrate with shallow trench isolation (STI) structures protruding above the substrate and a conductive layer confined between the STI structures; recessing the conductive layer below a top surface of the STI structures to leave a recess; forming a spacer on the sidewalls of the recess, the spacer covering a portion of the conductive layer to serve as an oxidation mask; growing an thermal oxide layer on the conductive layer where it is not covered by the spacer; removing the spacer to expose the conductive layer; etching an opening through the conductive layer using the oxide layer as an etch mask to define a floating gate; removing the oxide layer; forming an inter-gate dielectric layer conformally lining the opening and the floating gate; and forming a control gate layer over the inter-gate dielectric layer and filling the opening.