In the application of video signal transferring and video image displaying process, the phase adjustment of a timing pulse signal or a synchronizing signal plays an important role in providing correct images. In general, video images are transferred and displayed by providing a series of synchronizing signal and image data. The synchronizing signal can include a horizontal synchronizing signal and a vertical synchronizing signal. For achieving a correct timing on latching the data signal, one of the horizontal synchronizing signal and the vertical synchronizing is adjusted with its phase. Most frequently, the horizontal synchronizing signal is picked and adjusted in phase for latching the data signal with a correct clock pulse to correct the problem like image distortion, which is came from the incorrect timing on latching the image data signal after it is transferred and processed.
Referring to FIG. 1, a schematic timing diagram of a horizontal synchronizing signal (Hsync) and a data signal (Data) is illustrated. A clock pulse can be generated by referencing the horizontal synchronizing signal. The clock pulse is employed to latch the data signal with correct timing. The timing of the clock pulse can be adjusted by adjusting the phase delay of the horizontal synchronizing signal. A circuit for adjusting the phase delay is shown in FIG. 2. A phase delaying circuit 10 is employed to generate a phase delayed horizontal synchronizing signal (Hsync2). A phase lock loop (PLL), which is well known in the art, is responsive to the phase delayed horizontal synchronizing signal to generate a clock pulse (Dot clock), as illustrated in the figure.
In the prior art applications, the phase delaying circuit 10 is a RC delay circuit with a resistor R1 and a capacitor C1. The phase delay of the horizontal synchronizing signal can be adjusted by varying the time constant of the RC delay circuit 10. The phase of the clock pulse is then changed according to the phase delayed horizontal synchronizing signal in order to latch the data signal. The artificial process of adjusting the RC delay circuit 10 is time-consuming and the best clock timing is hard to achieve exactly with the manual operated adjusting process.
What is needed is a time-efficient phase correction method and apparatus to provide the best clock timing in latching the data signal, thus the distortion of the video image can be minimized and the quality and the accuracy of the image can be improved.