(1) Field of the Invention
The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically to the polishing of semiconductor wafers by applying Chemical Mechanical Planarization (CMP) of Inter Level Dielectric (ILD) and Inter Metal Dielectric (IMD).
(2) Description of the Prior Art
The increasing need to form planar surfaces in semiconductor device fabrication has led to the development of a process technology known as Chemical Mechanical Planarization (CMP). In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to increased use in the fabrication of complex integrated circuits.
A common requirement of all CMP processes is that the substrate be uniformly polished. In the case of polishing an electrical insulating layer, it is desirable to polish the layer uniformly from edge to edge on the substrate. To ensure that a planar surface is obtained, the electrically insulating layer must be uniformly removed. Uniform polishing can be difficult because several machine parameters can interact to create non-uniformity in the polishing process. For example, in the case of CMP, misalignment of the polishing wheel with respect to the polishing platen can create regions of non-uniform polishing across the diameter of the polished surface. Other machine parameters, such as non-homogeneous slurry compositions and variations in the platen pressure, can also create non-uniform polishing conditions.
The present invention relates specifically to the damascene process that is used for the formation of semiconductor surfaces. Damascene derives its name from the ancient art involving inlaying metal in ceramic or wood for decorative purposes. In Very Large-Scale Integrated circuit applications, the damascene process refers to a similar structure.
The damascene process has been demonstrated on a number of applications. The most commonly applied process is first metal or local interconnects. Some early Damascene structures have been achieved using RIE but CMP is used exclusively today. Metal interconnects using damascene of copper and of aluminum is also being explored.
Specifically, applying the CMP process to Inter Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections (micro-scratch) typically present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1000 EA for 200 mm. wafers, where an imperfection typically has a depth from 500 to 900 A0 and a width of from 1000 to 3000 A0. As part of the polishing process of the ILD and IMD, a tungsten film is deposited; the surface imperfections will be filled with tungsten during this deposition. For devices within the semiconductor wafer with a dimension of 0.35 um. or larger, an etching process is used where the tungsten that has entered the imperfections within the wafer surface can be removed. For the larger size devices within the semiconductor wafer there is therefore no negative impact on the yield of these devices. For device sizes within the semiconductor wafer of 0.25 um or less, the indicated procedure of etching the tungsten layer is no longer effective. This results in relative large imperfections within the surface of the wafer, large with respect to the size of the semiconductor devices. These imperfections will cause shorts between the metal lines within the devices while the imperfections also have a severe negative impact on device yield and device reliability.
FIG. 1 shows Prior Art removal of the Damascene residue. FIG. 1a shows the micro-scratch 40 within a substrate 14 that is filled with tungsten 45 after the deposition of a layer of tungsten 45. A typical micro-scratch is approximately 500-900 A0 deep and 1000-3000 A0 wide. FIG. 1b shows how the tungsten residue 45 is partially removed by CMP at the ILD and IMD but leaving a layer 50 that can readily cause electrical shorts between the metal plugs 10 adjacent to the micro-scratch 40.
U.S. Pat. No. 5,759,917 (Grover) shows a composition for on oxide CMP.
U.S. Pat. No. 5,665,202 (Subramanian) xe2x80x98Multi-Step Planarization process using polishing at two different pad pressuresxe2x80x99 teaches a process for polish planarizing a fill material overlying a semiconductor substrate and includes a multi-step polishing process.
U.S. Pat. No. 5,611,941 (Booth) shows a CMP metal over oxide process.
U.S. Pat. No. 5,766,992 (Chou et al.) shows an oxide ILD planarization.
A principle objective of the present invention is to reduce the defect count for semiconductor wafer polishing using the CMP process.
Another objective of the present invention is to improve semiconductor wafer throughput during wafer polishing using the CMP process.
Another objective of the present invention is to reduce shorts between metal lines within the devices contained within the semiconductor wafer.
Another objective of the present invention is to improve reliability of the devices contained within the semiconductor wafer.
Another objective of the present invention is to reduce wafer surface irregularities (micro-scratch) within the surface of Inter Level Dielectric (ILD).
Yet another objective of the present invention is to reduce oxide film on the surface of the Inter Metal Dielectric (IMD).
Yet another objective of the present invention is to enhance the use and applicability of tungsten deposition as part of the process of semiconductor wafer CMP.
Yet another objective of the present invention is to enable reduction of semiconductor device dimensions.
Yet another objective of the present invention is to enable reduction of semiconductor device dimensions to the quarter-micro range.
Yet another objective of the present invention is to enhance the removal of tungsten damascene residue during semiconductor wafer polishing.
According to the present invention, a CMP process is provided for the reduction of tungsten damascene residue. A three step polishing procedure is followed by a two step buffing procedure. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput.