The present invention relates generally to programming systems with registers that in operation have synchronized clock input signal lines and one or more asynchronous reset input signal lines.
Programming systems that include an interface controller coupled to a programming interface have registers with reset and clock inputs. If the clock inputs are asynchronous then there is the possibility of circuit meta-stability. This meta-stability is due to asynchronous clock domain crossing (CDC), which can cause corrupt data to be stored in one or more of the registers. It is therefore generally desirable to provide for synchronous clock inputs to the registers so that asynchronous clock domain crossing is eliminated.
In programming systems the reset inputs of registers may provide for a synchronous or an asynchronous reset configuration. When considering synchronous reset configurations it is difficult to ensure proper timing of reset operations throughout the system. In contrast, asynchronous reset configurations are such that there is no synchronization with a system clock and thus asynchronous reset assertion may cause an immediate change in the state of a register. However, if a system has a source register supplying data to a destination register, and reset inputs of the registers are asynchronous with respect to each other, a meta-stable asynchronous crossing path can result. As a consequence, corrupt data may be stored in the destination register.
Therefore, it is an object of the present invention to alleviate at least one of the problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems.