1. Technical Field
The embodiments described herein relate to a semiconductor device, and more particularly, to a diode that can be used for adjusting a pin resistance of a semiconductor product.
2. Related Art
In a semiconductor device, an input/output circuit will often comprise a plurality of components such as an electrostatic protection circuit, an input buffer and an output buffer. Each of these components will include their respective resistance components and capacitance components. The pin resistance is then is obtained by adding the resistance component of the input/output circuit and the resistance component of the associated package. The pin capacitance is obtained by adding the capacitance component of the input/output circuit and the capacitance component of the package.
With respect to the pin resistance, the resistance of a package is as small and can often be neglected.
In order to maintain signal integrity during operation of a semiconductor circuit, a predetermined level of pin resistance is required. As a result, the minimum value and the maximum value of pin resistance are often regulated in a specification associated with the semiconductor circuit.
FIG. 1 illustrates a typical example of an input circuit used in a conventional semiconductor integrated circuit. Referring to FIG. 1, it can be seen that the input circuit includes an input pad 100, a first electrostatic discharge section 110 and a second electrostatic discharge section 120 for protecting an internal circuit 170 from static electricity generated from the input pad 100, a power clamp circuit 130 for providing an electrostatic discharge path between a power voltage supply line Vcc and a ground voltage supply line Vss when static electricity is generated, an input buffer 160 for transmitting a signal, input through the input pad 100 to the internal circuit 170, and a resistor 140 and a MOS transistor 150 for protecting the input buffer 160.
During normal operation, the electrostatic discharge sections 110 and 120 and the power clamp circuit 130 are turned off to exert no influence on normal circuit operation. In the event that static electricity is generated between the input pad 100 and power pads, then discharge sections 110 and 120 will enter an operation mode and provide the electrostatic discharge path so that the input buffer 160 and the internal circuit 170 can be protected from transient electrostatic current.
Currently, a MOS transistor and a diode are widely used as the first electrostatic discharge section 110 and the second electrostatic discharge section 120. Since a diode is significantly better in terms of electrostatic protection as function of parasitic capacitance than a MOS transistor, the diode is more appropriate for a circuit operating at a high speed, and therefore, the number of products using a diode is increasing. However, because a diode has smaller resistance and capacitance than those of a MOS transistor, the pin resistance is markedly decreases and therefore may not satisfy the specified pin resistance.
FIGS. 2a and 2b illustrate the structure of the first electrostatic discharge section 110 in a conventional semiconductor circuit. FIG. 2a is a plan view and FIG. 2b is a sectional view taken along the line A-B of FIG. 1.
The first electrostatic discharge section 110 includes a P-type well 111 formed in the surface of a P-type semiconductor substrate, one or a plurality of N+ impurity areas 112 formed in the surface of the substrate within the P-type well 111, one or a plurality of insulation areas 113 formed in the surface of the substrate to surround the respective N+ impurity areas 112, and a P+ impurity area 114 formed in the surface of the substrate to surround the insulation areas 113.
The N+ impurity areas 112 and the P-type well 111 constitute a PN diode. In the case that this diode is used as the first electrostatic discharge section 110 of FIG. 1, the N+ impurity areas 112 are connected to the input pad 100 through contacts 115, and the P+ impurity area 114 is connected to the ground voltage supply line (Vss) through contacts 115.
Referring to FIG. 2b, it can be observed that the P-type well 111 is formed in the substrate, the plurality of N+ impurity areas 112 and the P+ impurity area 114 are formed in the P-type well 111, and the insulation areas 113 are formed between the N+ impurity areas 112 and the P+ impurity area 114. Further, in order to connect the input pad 100 and the ground voltage supply line (Vss), the contacts 115 are formed on the N+ impurity areas 112 and the P+ impurity area 114.
In a conventional diode structure as described above, the contacts 115 are arranged in the N+ impurity areas (cathodes) 112 and the P+ impurity area (anode) 114 to have minimum pitches D1 and D2 permitted by an associated design rule in order to minimize the operation resistance of the diode. Also, the distance D3 between the N+ impurity area 112 and the P+ impurity area 114 is set as a minimum distance permitted by the design rule.
Accordingly, when a conventional diode is laid out according to the minimum design rule, the pin resistance of a semiconductor product, which uses the diode as an electrostatic protection element, is likely to be less than regulated minimum pin resistance, since the diode parasitic resistance is small and therefore the degree to which the diode contributes to pin resistance is also small.
In particular, in order to reduce parasitic capacitance to allow high speed operation of a semiconductor product, the decrease in pin resistance will raise a serious problem, because the electrostatic discharge section cannot but be minimized.