1. Field of the Invention
This invention relates to output buffer circuits and specifically to output buffer circuits having optimized ground-bounce characteristics.
2. Description of the Relevant Art
Output buffers are commonly used within integrated circuits to allow the coupling of data or control signals to external pins and thereby to circuits external to the integrated circuit. Four basic types of output buffers exist. One type is a non-inverting output buffer with an enable control line. Another type is an inverting output buffer with an enable control line. A third type is a non-inverting, non-enabling output buffer, and a fourth type is an inverting, non-enabling output buffer.
An important consideration in the design of each type of output buffer is the power required to drive the signal-receiving circuitry. Another important consideration is the signal propagation delay introduced by the output buffer. Particularly for output buffers used in high-speed applications, low propagation delays are desirable.
A typical output buffer includes an output stage comprised of a pair of field-effect transistors (FETs). One of the FETs, hereinafter called the pull-up transistor, is connected in a source-follower configuration between a logic high voltage source (i.e., 5 volts) and an output terminal. When the pull-up transistor is switched on by a signal at its associated control gate, the logic high voltage is provided through the transistor's low impedance path to the output terminal to thereby drive the signal-receiving circuitry.
The other FET in the output stage, hereinafter called the pull-down transistor, is connected in a common-source configuration between the output terminal and ground. When the pull-down transistor is switched on by a signal at its associated control gate, the output terminal is coupled to ground through the transistor's low impedance path and thereby provides a logic low signal to drive the signal-receiving circuitry.
A common problem associated with output buffers is the occurrence of a phenomenon known as "ground-bounce". Ground-bounce is a particular problem in integrated circuits that use high speed transistors, and occurs as a result of the parasitic inductance of the integrated circuit and packaging interconnect technology. Ground-bounce occurs when the pull-down transistor switches on during the period when the output terminal makes a transition from a logic high to a logic low state. When the pull-down transistor turns on, a surge of current flows from the output terminal through the pull-down transistor and through the parasitic inductance to ground. Since the voltage across an inductor is directly proportional to the derivative of current with respect to time, a decrease in the gate-to-source voltage in the pull-down transistor occurs. In the case where the pull-down transistor turns on very quickly, the derivative of current with respect to time is high and thus a relatively large decrease in gate-to-source voltage results. This decrease in gate-to-source voltage, called ground-bounce, in turn causes an increase in the overall propagation delay of the output buffer and can further cause corruption of the internal logic and ringing.