The present disclosure is generally directed to time to digital converters and a method of converting a measured time period representing a difference in receipt of the leading edges of a pair of signals, to a digital representation thereof. More specifically, the subject system is directed to a time to digital converter that includes a phase-frequency detection circuit that generates up and down control signals having respective pulse widths wherein the pulse width of one of the two control signals represents a time difference in receipt of rising edges of two signals input thereto. Further, the system is directed to a time to digital converter incorporating a current switching unit that generates up and down current signals, each being switched on for a time period equivalent to the pulse width of a corresponding one of up and down control signals output by the phase-frequency detection circuit. Still further, the time to digital converter includes a successive approximation analog to digital converter circuit having a capacitor digital to analog converter for generating a respective voltage corresponding to each of the up and down current signals. The successive approximation analog to digital converter circuit generates a digital representation of the difference between the voltages, which corresponds to the measured time period. Additionally, the time to digital converter includes a current switching unit that has programmable sensitivity that allows for generating the digital representation of the measured time with greater precision.
Still further, the present disclosure is directed to a method of converting a time period corresponding to a time difference between receipt of rising edges of two signals to a digital representation thereof. In particular, the method includes detection of a rising edge of each of two input signals and measuring a time difference therebetween and generating two control signals having a difference in pulse width therebetween equivalent to the measured time difference. Further, the method includes redistributing charge, respectively, with respect to a pair of arrays of binary-weighted capacitors responsive to the two control signals to establish corresponding voltages across each array. The voltages across the two arrays are successively compared and the results thereof stored in a register to generate the digital representation of the measured time difference.
Analog phase locked loops have been in use for many years. A basic block diagram for a typical analog phase locked loop (PLL) 100 is shown in FIG. 1. In an analog PLL 100, the PLL 100 “locks” the apparent phase between a reference clock 12 and a divided down feedback clock 52. The difference in apparent phase between the leading edge of these two clocks 12 and 52 is determined by a phase-frequency detector 10 and which generates an “up” pulse 14 and a “down” pulse 16 that is output by the phase-frequency detector 10 to a charge pump 20. The charge pump adds or subtracts charge using a well-known circuit called a charge pump. The charge pump 20 outputs the pulses of charge on coupling line 22 to a loop filter 30 which filters these pulses of charge. The output of the loop filter 30 is fed to the input of a voltage controlled oscillator (VCO) 40 via the coupling line 32. The output 42 of the VCO is fed to a feedback divider 50 which divides down the output of the VCO 40 to feed the divided signal back to the phase-frequency detector 10 through the coupling line 52 to thereby close the “loop” of the PLL 100.
The wide use of digital processing in systems that heretofore were constructed of analog circuits has driven the demand for digital systems to replace those that had been constructed from analog circuits. The architecture of a typical digital PLL 200 is shown in FIG. 2. In a digital PLL 200, the leading edge of the reference clock 202 is compared to the leading edge of the divided feedback clock 242 coming from the feedback divider 240, which divides the output 232 of the digitally controlled oscillator (DCO) 230. The circuit which makes this comparison is called a time to digital converter (TDC) 210. The output of the TDC 210 on coupling line or bus 212 is a digital word which fed into a digital loop filter 220 that then outputs through the coupling line or data bus 222 to drive the DCO 230 with a digital word.
The digital PLL 200 has several advantages over an analog PLL 100. For example, the loop filter is now a digital filter whose loop characteristics can be precisely controlled. Also a digital filter is often much smaller in chip area than that of an analog loop filter. Further, the digital loop filter can be easily adjusted to allow for a rapid lock time, and the digital loop allows for easy insertion of modulation if a spread spectrum output clock is desired. However, in order to gain these benefits from a Digital PLL 200 in state of the art systems, a TDC 210 must exist which can convert the time difference of the reference clock 202 leading edge and the feedback clock 242 leading edge to a digital word to drive the digital loop filter, both with precision and at high speed.