This invention relates to print engines and more specifically to a pulse width position modulation circuit and clock skew synchronizer circuit that generates and synchronizes subpixels without requiring high clock frequencies.
A marking engine is an electro-mechanical device that takes digital video data and marks a paper media with the image represented by the video data. A native pixel is the inherent single pixel size of the marking engine in a scan direction of, for example, 600 dots per square inch (dpi). A subpixel is a portion (usually 1/N where N=2M) of a native pixel. Gray-scale is a scale of gray tones graduating from black to white. A gray-scale also denotes tone scales in color.
Marking engines, color or black and white, commonly have little ability to mark paper with gray-scale images. This presents little or no problem when printing black or solid color text and line-art. For images, the story is different. To mark graphic images, the ability to print gray-scales, or something that is perceived by the human eye to be gray-scale, is crucial. This is accomplished by controlling the placement, size and pattern of pixels and letting the human eye integrate the pattern to a perceived shade. Control is needed for manipulation of subpixels at a finer resolution than provided for in marking engines"" native pixels.
A native pixel of a particular marking engine may be generated, for example, every 64 nano seconds (ns). A very accurate system is needed to apply video data to the print output logic every 64 ns. A typical digital circuit oscillator or crystal derived clock would need to operate at a frequency of 15.625 MHz. To produce subpixels for the system at 4 subpixels/native pixel, a subpixel period of 16 ns or 62.5 MHz is needed. If the desired subpixel frequency is higher than the clock frequency in which the printing device technology can support, the subpixels are very difficult to generate. For example, outputting 16 subpixels in a standard 20-100 ns pixel time period, requires a clock rate two-four times faster than a typical 0.35 xcexcm CMOS integrated circuit fabrication process will support. Thus making it difficult to generate subpixels at many desired subpixel frequencies.
In many bit-serial laser printer interfaces, a Line Sync (LS) signal is used to mark the beginning of each pixel-wide imaging row. The LS signal is alternatively referred to as a horizontal sync or beam detect signal and allows the marking engine to synchronize video generation logic with the marking mechanism. The video data must be synchronized to the LS signal in order to get horizontal alignment of data placement on the page. The video generation logic is typically a clocked digital system and the LS signal is typically generated asynchronously with the digital system.
A common method of synchronizing circuitry with the LS signal uses a sampling circuit that runs on a faster clock. The sampling circuit samples the phase relationship of the LS signal with the native pixel clock and then makes a one-time phase shift of the native pixel clock to phase align it to the arriving LS signal. Other synchronizing circuits generate an array of phase shifted native pixel clocks (typically taps off a series of delay elements) and then uses a LS signal phase detector that picks which phase-shifted version to use.
Accurate synchronization between the native pixel clock and the LS signal is often not possible using the systems described above because of the high sampling rate required to accurately detect the LS signal.
U.S. Pat. No. 5,109,283 entitled: Raster Scanning Engine Driver Which Independently Locates Engine Drive Signal Transistors Within Each Cell Area and U.S. Pat. No. 5,122,883 entitled: Raster Scanning Engine Driver Which Independently Locates Engine Drive Signal Transitions Within Each Pixel, each to Carley, discuss a raster print engine driver that generates modulated drive signals from incoming image data. Drive signal transitions cause a print engine to reproduce the image data as a series of modulated print lines.
The system in Carley uses an analog ramp generator to control the position and width of the digital video signal that controls printing of line segments on a printing medium. Only one line segment is generated during each cell clock period. Because Carley cannot increase subpixel resolution without increasing the frequency cell clock, high resolution subpixel output is not possible. Further, the analog ramp generators in Carley are expensive and less consistent in different operating conditions and between different print engines.
Accordingly, a need remains for printing video image data at high subpixel frequencies without increasing the native clock frequency and more accurately synchronizing printer circuitry with asychronous line synchronization signals.
A pulse width position modulator (PWPM) includes a digital delay circuit that outputs multiple subclocks according to a native pixel clock. The multiple subclocks are each skewed to different phases of the native clock. A skew pulse generator receives the multiple subclocks from the digital delay circuit and outputs multiple subpixels according to different logical combinations of the multiple subclocks thereby providing increased subpixel output resolution using the native pixel clock frequency.
The skew pulse generator includes a pulse generator for generating different skewed clock pulses from the subclocks. The different clock pulses are each used to control the output for one of the subpixels. In one embodiment, the pulse generator comprises multiple AND gates that logically combine two different subclocks together to form one of the clock pulses. The skew pulse generator also includes output buffers that each receive an associated one of the subpixels and are output enabled by an associated one of the clock pulses.
Registers clock the subpixels input to the skew pulse generator. A first set of registers supply a first half of the subpixels to the skew pulse generator after a falling edge of the native pixel clock and a second set of registers supply a second half of the subpixels to the skew pulse generator after a rising edge of the native pixel clock. The registers eliminate race conditions between the native pixel clock and the subpixels.
The PWPM can operate in an associative mode, where an associative shift register generates addresses associated with different pixel values. A lookup table is coupled between the associative shift register and the skew pulse generator. The lookup table generates subpixel patterns for the native pixel according to the address generated by the associative shift register. The associative shift register is programmable to generate addresses according to a selectable number of bits per pixel. The associative shift register also varies the number of native pixels combined to generate the subpixel address according to the number of bits per native pixel. The PWPM also operates in a literal mode where the associative shift register outputs a group of bits representing one native pixel value. A bit expander expands each bit in the group into one or more subpixels. The shift register and the bit expander are programmable to operate in different bit per pixel modes.
A clock skew synchronizer aligns the subpixels with a line synchronization signal. The clock skew synchronizer uses the digital delay circuit skewed subclock output. Multiple registers each have a data input coupled to one of the subclocks and a clock input coupled to the line synchronization signal. An edge detector is coupled to data outputs of the multiple registers. The edge detector generates a shift value according to which of the registers first detect actuation of the line synchronization signal. A shift register then uses the shift value to shift the subpixels into alignment with the line synchronization signal. The clock skew synchronizer aligns subpixels in a printed image with the line synchronization signal at high subpixel resolution without using high frequency sampling circuity.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.