A recent electronic device has been refined and multilayered, furthermore, its logic has become complicated, and therefore the manufacturing process has become complicated. Accordingly, a defect due to the manufacturing process is generated, and therefore it is expected to efficiently and accurately inspect a circuit pattern of the electronic device. Especially, it is important to accurately inspect a circuit pattern with high and low points such as a hole having a high aspect ratio of the depth and bore diameter and a circuit having a multilayer structure.
For inspection of such a circuit pattern, apparatuses such as a CD-SEM (Critical Dimension Scanning Electron Microscope) and DR-SEM (Defect Review Scanning Electron Microscope) are used.
These apparatuses send a charged particle radiation such as an electron beam to a circuit pattern formed on a silicon wafer or reticle (mask), convert a secondary electron released from the circuit pattern into an image signal (hereinafter, referred to as “secondary electron image”), analyze the secondary electron image and inspect the circuit pattern.
To accurately inspect a circuit pattern, a secondary electron image that accurately reflects an actual circuit pattern image is required. However, in the above-noted circuit pattern with high and low points, it is difficult to complement a secondary electron released from a circuit pattern in a lower position. Therefore, the observation image contrast of a circuit pattern in a higher position may be degraded.
The following Patent Literature 1 suggests a method of correcting the contrast of a secondary electron image.
The following Patent Literatures 2 and 3 suggest a pattern matching method using a position determination image registered in advance, design data or data generated by a wafer manufacturing process simulation, as a template, in order to accurately specify a circuit pattern of an inspection target on a secondary electron image.