1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to a semiconductor device with a pad structure formed within an interlayer insulating layer to prevent a short circuit between conductive lines on the interlayer insulating layer and a method for manufacturing the same.
2. Description of the Related Art
A lower conductive layer of a semiconductor memory device is connected to an active area of a semiconductor substrate via plugs provided in an interlayer insulating layer interposed between the lower conductive layer and the semiconductor substrate and is connected to an upper conductive layer via plugs provided in an interlayer insulating layer formed on the lower conductive layer. In a case where bit lines make up the lower conductive layer, a metal interconnection layer is used as the upper conductive layer corresponding to the lower conductive layer. In a case where local bit lines are accommodated in the lower conductive layer, global bit lines are used as the upper conductive layer.
As the integration density of semiconductor devices increases, various methods of increasing the capacitance of capacitors, which are devices that store electric charges, have been studied. Among these methods is a method of increasing the height of capacitors in order to enlarge the area of the capacitors. Thus, semiconductor devices have adopted capacitor over bit line (COB) structures so that capacitors are formed on lower conductive layers. The thicknesses of interlayer insulating layers interposed between lower and upper conductive layers have been increased. In other words, interlayer insulating layers between lower and conductive upper layers have become much thicker than interlayer insulating layers between lower conductive layers and semiconductor substrates. Consequently, the process for forming contact holes for plugs connecting lower conductive layers and semiconductor substrates is simple whereas the process for forming contact holes for plugs connecting lower and upper conductive layers is difficult. Also, since interlayer insulating layers interposed between lower and upper conductive layers are thick, contact holes in the interlayer insulating layers are small near lower conductive layers or semiconductor substrates but become larger during the process of forming contact holes.
However, if the contact holes become larger than the pitch of the upper conductive layers (as the upper width of the contact holes becomes greater), the upper conductive layers are short-circuited to adjacent upper conductive layers via plugs.
In semiconductor memory devices having bit lines of a hierarchical structure, the pitch of global bit lines can be increased in order to solve the short-circuiting problem in upper conductive layers. However, if the pitch of the global bit lines is increased, it is difficult to achieve needed high integration density in semiconductor memory devices.