The present invention relates to a memory module, and more particularly to a memory module which is available even if the memory module has a plurality of random access memories, at least one of which has at least a defective address.
In recent years, the requirement for increase in capacity of memory in electronic devices such as personal computers has been on the increase. The memory devices are, however, limited in size and required to have an extensibility, in the light of which it is not preferable to mount random access memories particularly dynamic random access memories on a board of a computer. In place, it has been often carried out to mount the random access memories on a multi-layer printed circuit board with connective terminals to form a memory module so that a plurality of such memory modules are inserted into sockets on a mother board of the computer. This means that it is required to provide only sockets on the mother board for the memory modules. Each of the multilayer printed circuit boards extends in a vertical direction to the plane mother board and a plurality of the random access memories are provided on each of the multilayer printed circuit boards. The vertically extending multilayer printed circuit boards, on each of which a plurality of the random access memories are provided, are provided on the mother board of the computers. This means that the random access memories are accommodated in a three dimensional space over the mother board of the computer. The use of the three dimensional space for providing the random access memories reduces the necessary area of the mother board of the computer. This allows a compact size of the computer. The provision of the random access memories in the form of the plural memory modules ensures a high extensibility since the individual memory modules are easily attached into and detached from the sockets on the mother board of the computer.
FIG. 1 is a front view illustrative of a conventional multilayer printed circuit board on which eight dynamic random access memories are mounted along with a single electrically erasable programmable read only memory.
The conventional multilayer printed circuit board 31 has a bottom side on which connective terminals are provided so that the conventional multilayer printed circuit board 31 are electrically and mechanically connected to the mother board through sockets on the mother board. Eight dynamic random access memories 33 are mounted to be aligned in a lateral and longitudinal direction of the multilayer printed circuit board 31. The individual eight dynamic random access memories 33 are electrically connected through a first set of interconnections 32-1 to the connective terminals 35. A single electrically erasable programmable read only memory 34 is also mounted on a side portion of the multilayer printed circuit board 31. The single electrically erasable programmable read only memory 34 is electrically connected through a second set of interconnections 32-2 to the connective terminals 35.
The individual dynamic random access memories 33 have a 64 M-bits size of 8 M-words.times.8-bits. The individual memory module has eight dynamic random access memories 33. Thus, the individual memory module is in the form of 8 M-words.times.64 M-bits size.
In JEDEC (Joint Electron Device Engineering Council), there has been known a memory module on which a 2 k-bit serial electrically erasable programmable read only memory is mounted for storing configurations and characteristics of the module.
In recent years, the prices of the random access memories have been reduced whilst the capacity of the memory has been increased. For this reason, the dynamic random access memories are used to store large amounts of informations in place of the conventionally used magnetic disk memory. In this field, the random access memories have recently been about to be used in the form of the memory modules.
The memory modules may be classified into two types. The first type is an error correct code type memory module capable of detecting any defect during operation and also possessing bits for correcting the defects, The second type is a non-error correct code type memory module incapable of correcting any defects even the defects appear in operation. For the non-error correct code type memory module, just 64-bits data-bus width is required without any extra bits. For example, it is possible to realize the non-error correct code type memory module by use of eight of 8-bits dynamic random access memories. By contrast, in accordance with the error correct code type memory module, the error correct code requires further 8-bits. This means that the error correct code type memory module requires not only the 64-hits bus but also the additional 8-bits for error correct code. Namely, nine 8-bits dynamic random, access memories are required to be mounted on each memory module. The error correct code type memory module needs to use at least one additional dynamic random access memory to the basic 64-bits bus necessary for the non-error correct code type memory module. For this reason, the error correct code type memory module is somewhat expensive as compared to the non-error correct code type memory module.
In general, immediately after the power-on of the computer, an operating system stored in a magnetic disk memory is transferred into a random access memory so that a central processing unit utilizes data of the transferred operating system for operations. If, however, any defect exists in the random access memory to which the operating system is to be transferred, it is impossible to store the exact programs of the operating system into the defective random access memory. As a result; the central processing unit is inoperable. This means that all of the random access memories to be mounted on such the memory module for this purpose are absolutely required to be complete.
If, however, the random access memories having a few bits of defective addresses are used for storing voices to use an audio device, there is raised substantially no problem in use of the random access memories. Of course, the random access memory having the defective address is cheaper than the random access memory free of any defective address. For those reasons, it is preferable to use the cheaper random access memories with the defective address.
Actually, the unit price for one bit of the random access memory has been on the drop due to increase in capacity of the memory. If, however, there is any defective address which is hard to be relieved by a redundancy circuit, then this random access memory would be unusable. If, for example, the 64 M-bits dynamic random access memory has 67,108,863 bits effective memory cells and only one bit defective memory cell, then the 64 M-bits dynamic random access memory is likely to be disposed.
Namely, in the cost case, only the complete random access memories are mounted on the memory module, for which reason the memory module tends to still be expensive.
Further, the yield of the random access memories is low, for which reason the unit price of the random access memories is likely to be expensive.
In the above circumstances, it had been required to develop a novel memory module free from the above problems and disadvantages.