The present invention relates generally to the fabrication of semiconductor integrated circuits, and more particularly to the fabrication of very large-scale integration (VLSI) circuits.
Recent developments in MOS VLSI integrated circuits have resulted in integrated circuits capable of operating at higher speeds and characterized by reduced-size geometries and greater packing densities. This trend toward increasingly complex MOS devices has pushed the limits of existing materials and fabrication processes. As the geometries of MOS devices have shrunk to one micron and even less, circuit densities have increased, contact holes have become smaller, and line widths have become narrower. The 15 resistance of the MOS devices fabricated in these integrated circuits has tended to increase, which increases RC time constants and thereby limits the overall speed of the MOS devices. Much effort has been directed to achieving lower resistances of the MOS device structures in an attempt to obtain higher device operating speeds.
One proposed solution to this problem has been the use of refractory metal, such as tungsten, and their silicides, as a high-conductive, low-resistance interconnect material. The use of these materials provides an alternate to polysilicon for first-level interconnections and gate electrodes and an alternate to aluminum for multi-level interconnects, and a way of planarizing contacts and via holes without the need for troublesome sloped contact etching.
As device dimensions are scaled and the number of devices per chip increases, there is also a need for additional levels of interconnection. Double metal processes are now practiced widely, three-layer processes are used occasionally, and four-layer processes are under development. One of the main factors limiting the advance of VLSI multilevel interconnection is the topography on the wafer. Present process research is aimed at circumventing or eliminating the problems associated with wafer topography. A certain amount of planarization is required to overcome the topography created by the underlying structures. The achievement of desired planarization, however, typically requires precise process control, increased process complexity, and a reduction in product yield.
In a conventional process used to fabricate a multilevel MOS integrated circuit, a dielectric layer is deposited on a surface of a substrate, a contact hole is formed in the dielectric, and a first metal layer is deposited and then etched. A second dielectric layer (interdielectric) is then deposited over the metal and a photoresist layer is deposited over the second dielectric layer. The structure is then subjected to a blanket etch back in an attempt to achieve planarization of the interdielectric. A via hole is then formed in the interdielectric to the upper level of the first metal layer. Thereafter, a passivation layer is deposited and etched.
There are, however, numerous problems associated with this conventional multilevel process, such as severe topography resulting in metal step coverage problems and residual metal problems, which may cause electrical opens for the interconnects and intra level electrical shorts between adjacent interconnects. Other drawbacks associated with this conventional process include electromigration on narrow interconnects (particularly when aluminum is used), and the need for a metal overlap around the via and contact holes (dogbone structure), which results in the reduction of device packing density and in a degraded circuit performance.
Two approaches for dealing with these problems have been described by the present inventor in application Ser. No. 107,573, now U.S. Pat. No. 4,764,484, and in pending application Ser. No. 107,487, both of which have been assigned to the assignee of the present application. Common to the processes described in these prior patent applications is the use of a blanket layer of silicon film to separate the upper and lower dielectric layers. Although these prior processes are useful in fabricating high-density VLSI circuits with improved topography, the silicon film utilized in these processes, if not well controlled during its deposition, may become contaminated.
One possible form of contamination of the silicon film is the formation of clusters of particles in the silicon film. If those particles become located between two metal lines, they could cause a short circuit between those metal lines. The present invention provides a process in which there is no continuous connection of silicon from one metal line to another metal line, thereby preventing the formation of undesired electrical shorts between adjacent unconnected metal lines.
It is accordingly a general object of the present invention to provide a process for fabricating interconnects in an MOS integrated circuit in which planarization of the interdielectric and metal etching, which are typically required in the fabrication of VLSI devices, are eliminated.
It is a further object of the present invention to provide a process for fabricating more reliable VLSI devices with higher densities.
It is another object of the present invention to provide a process of the type described in which the creation of shorts from one metal line to another is eliminated.
To these ends, in the process of the present invention, a contact hole formed in a first dielectric layer on a substrate is filled with metal, after which the first dielectric layer and the metal-filled contact hole are covered with a second dielectric layer. A photoresist layer is then coated over the second dielectric layer and is subjected to photolithography to pattern the photoresist. A trench is formed in the exposed second dielectric layer and a thin layer of silicon or a metal such as tungsten is then sputter deposited or evaporated to form a layer of the silicon or metal as the case may be on the upper surface of the photoresist and the bottom and side walls of the trench. The patterned photoresist is then removed, as by a lift-off process, and the trench is filled with metal, which consumes the silicon or metal previously deposited on the bottom and side walls of the trench.