This invention relates to a semiconductor device and to a method of manufacturing such a device.
Semiconductor devices are known which comprise a semiconductor body having a first major surface and defining at least one active device, an electrically conductive region provided on the first major surface, a covering insulating region encapsulating the electrically conductive region, and a conductive track provided on the first major surface so as to make electrical contact with the electrically conductive region.
GB-A-2208965 describes such a device in which the encapsulated electrically conductive region forms the gate conductive region of the insulated gate of an insulated gate field effect transistor (IGFET or MOSFET). In particular, GB-A-2208965 describes a mixed bipolar-MOSFET technology, as shown a so-called BICMOS technology, in which bipolar transistors are formed with complementary conductivity type MOSFETs (CMOS). In the example discussed, the device areas for the bipolar transistor, n-channel IGFET and p-channel IGFET are defined by field oxide. A first doped and silicided polycrystalline silicon layer covered by an insulating capping layer is patterned to define the insulated gates of the n-channel and p-channel IGFETS, and to define a doped layer for contacting the first major surface for providing a source of impurities to form an outer or extrinsic subsidiary region of the bipolar base region. Impurities are implanted using this structure as a mask to form lowly doped source and drain extension regions and to provide a proportion of the dopants for forming the intrinsic or inner subsidiary region of the bipolar base region. The gate conductive regions and extrinsic base defining region are then encapsulated by the formation of insulating spacer regions on the exposed side walls. After introduction of impurities for forming the source and drain regions and the intrinsic subsidiary base region, a second doped and silicided polycrystalline silicon layer is provided for forming source and drain contact regions and for forming the emitter region of the bipolar transistor. The second doped polycrystalline silicon layer as provided extends over the encapsulated insulated gates and a planarisation step is then used in which a planarising layer is etched back to expose only the top surface of the second doped polycrystalline silicon layer which lies over the encapsulated insulated gate. The exposed doped polycrystalline silicon is then etched to remove only that portion extending over the encapsulated insulated gate so as to form separated doped polycrystalline silicon contact regions on the source and drain regions. After removal of the planarising layer, a dielectric layer is provided and contact windows opened to enable electrical contact to be made via subsequent metallisation to the bipolar transistor and to the source, drain and insulated gate of the IGFETS. The provision of the doped polycrystalline silicon contact regions on the source and drain regions enables the metallisation contact windows to be formed over the field oxide onto which the doped polycrystalline source and drain contact regions extend so that the metallisation contacts are not directly over the source and drain regions. The possibility of the metallisation accidently overlapping onto the insulated gate is thus much reduced which should enable alignment tolerances to be reduced and therefore provides a technology capable of producing devices with high packing density and which are adapted to computer aided design (CAD) techniques. It is, however, still necessary to enable contact holes to be made through the covering insulating region encapsulating the insulated gates to allow electrical contact to the insulated gates of the IGFETs.