Typical micron level integrated circuit manufacture requires extensive layout of components and pathways between components. The pathways between components carry signals and power back and forth between components. Some components do not require much power or do not carry much current. Pathways between these types of components can be made very small in width of the metal that carries the signals or the power. However, other components have higher power or current requirements.
As power and current requirements go up, a standard minimum line width for carrying power or current between or to those components is insufficient. Typical minimum line widths for components that do not draw much current are on the order of 0.2 microns wide. On the other hand, lines that carry power or current to or from supplies and large components may need to be on the order of 10 to 1000 microns wide. The wider lines are required to carry the current as well as to avoid resistive drops and electro migration problems.
Various software solutions exist to perform certain checking of parameters in schematics, layouts, and the like. A typical design process begins with schematic, moves to layout, and then to design and on to fabrication. Along the way, checks are typically made of parameters and the like. For example, a line width check program checks to see if the lines in the (schematic or layout) are at least at or above an absolute minimum width (usually 0.2 microns). When the layout is complete, aside from the line width check, an inspection is made, typically manually, of checking that the lines that are required or called for to be a width greater than the absolute minimum are indeed laid out at the required or called for widths. Since integrated circuits can be extremely complex, such a visual inspection is very time consuming, and is prone to human error.
Once the layout is complete, a layout versus schematic program is run. The layout versus schematic program compares the electrical circuit design (schematic) with the physical design (layout). Once the layout is complete and checked with the LVS, a design is extracted. When the design has been extracted, a design rule checker (DRC) program is run. The DRC measures spacing, overlap, and sizes of masking dimensions and the like on the layout to ensure that circuit dimensions will conform to the fabrication process capabilities. The DRC includes a check for line widths only to the extent that it checks to see that each line is at least an absolute minimum width. Lines requiring a greater width are not verified to that greater width.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved checking of layout line widths in integrated circuit layouts.