The present invention relates to a semiconductor memory device and particularly to a circuit for sensing a back-bias level generated from a back-bias generator.
Usually, a substrate of a semiconductor memory device is provided with a negative voltage of a predetermined level, so as to allow the threshold voltage of a MOS transistor included in the memory device to be stable, to prevent parasitic capacitance, and to prevent faulty operation of the memory device due to undershoot of an external signal. For example, in a case where a DRAM cell has an NMOS transistor as a memory cell, and an N-type conductive polysilicon capacitor (or a capacitor with an N-type conductive diffusion region), a specific voltage of -2.about.- 2.5V must be applied to the substrate (or to the plate electrode of the capacitor). This voltage is called the back-bias voltage or substrate voltage. Generally, a circuit for generating the back-bias voltage (hereinafter, referred to as the back-bias generator for short) has a pumping circuit for keeping the back-bias voltage at a constant negative voltage of a predetermined level, an oscillator for driving the pumping circuit, and a back-bias level sensor for sensing the current back-bias voltage level and controlling the oscillator in response to the sensing signal.
Referring to FIG. 1, such a back-bias generator is schematically illustrated, wherein an oscillator 100 is generally comprised of an inverter chain, and a pump circuit 300 includes a capacitor for pumping the back-bias voltage VBB in response to a pumping clock provided thereto from the oscillator 100 via a driver 200. Furthermore, the back-bias voltage VBB is fed back to the oscillator 100 through the back-bias level sensor 400. The back-bias level sensor 400 changes the output of the oscillator 100 in response to a sensing signal of the current back-bias voltage VBB. Namely, if the current back-bias level is lower than a desired level, (in this case the back-bias level must be increased) the back-bias level sensor 400 reflects this situation on the oscillator 100; thus the oscillator 100 generates a control signal (or pumping clock) for energizing the pump circuit 300 in response to the output signal from the back-bias level sensor 400. As a result, the pump circuit 300 performs the pumping operation, thereby increasing the low back-bias voltage level VBB up to the desired voltage level. It should be noted that, for convenience, in this specification the back-bias level refers to the absolute value. On the contrary, if the current back-bias voltage VBB is higher than the desired level, (in this case the back-bias level must be decreased) the oscillator 100 generates, in response to the sensing signal from the back-bias level sensor 400, a control signal for preventing the pump circuit 300 from performing the pumping operation.
It is essentially required that the back-bias level sensor senses the back-bias voltage VBB efficiently, without directly influencing the back-bias voltage VBB itself. An example of the conventional back-bias level sensor uses a voltage divider comprised of resistors or resistance elements. Such a device is disclosed in U.S. Pat. No. 4,471,290, issued on Sept. 11, 1984. In the disclosure of the patent, the back-bias level sensor includes a voltage divider comprised of series resistors R1, R2 connected between the back-bias voltage and the ground voltage. A connection node of the series resistors is coupled to the input of a level sensor.
Accordingly, the connection node of the voltage divider always has the back-bias voltage of ##EQU1## and then this divided voltage level is compared with a reference level at the level sensor. The level sensor reflects the comparison signal on the oscillator. However, the current flow is always formed between the back-bias voltage terminal and the ground voltage terminal via the series resistors R1 and R2, resulting in degradations of the back-bias voltage due to not only the hole currents in the semiconductor substrate but also the current flow through the series resistors (i.e., the current flow from the ground voltage terminal to the back-bias voltage terminal).
Another example of a conventional back-bias level sensor is shown in FIG. 2. This circuit utilizes the rectifying characteristics of the diode-connected MOS transistor. As illustrated, a PMOS transistor 21 and an NMOS transistor 23 are always turned on, and the voltage of a connection node 22 is determined by the voltage dividing means comprised of the MOS transistors 21, 23 and 24. The connection node 22, between the series connected MOS transistors 21 and 23 that are coupled to the power supply voltage Vcc, is connected to the oscillator 100 of FIG. 1 via a delay circuit 26. The PMOS transistor 24 is coupled between the NMOS transistor 23 and the back-bias voltage VBB, one end of the channel and the gate of the PMOS transistor 24 being coupled in common to the back-bias voltage VBB and the other end of the channel being coupled to the channel of the NMOS transistor 23. The voltage at the connection node 22 is applied to the oscillator 100 by way of the delay circuit 26 and moreover this voltage can be previously adjusted to a voltage VBBD by means of changing the size of the MOS transistors 21, 23 and 24, where VBBD is the voltage level at which the oscillator 100 is enabled.
With reference to FIGS. 3A to 3F, operation of the conventional back-bias level sensor will be considered hereinafter. In the drawings, the back-bias voltage VBB, the pass current Ix passing from the power supply voltage Vcc to the back-bias voltage terminal VBB, the voltage V22 at the connection node 22, the voltage output V28 of the delay circuit 26, the voltage output V.sub.osc of the oscillator 100, and detailed voltage characteristic curves of the back-bias level sensor are respectively illustrated. It is noted that the pass current Ix is proportional to the back-bias voltage VBB. As can be seen in FIG. 3A, up to time tI, the voltage VBB is a lower negative value (i.e., higher absolute value) than the voltage VBBD; therefore, the pass current Ix is also larger than the pass current Ix that at the time tl. This is because the pass current Ix flows into the back-bias voltage terminal VBB and, accordingly, the back-bias voltage level increases undesirably due to the pass current Ix (and the hole current of the substrate). This phenomenon is called the degradation of the back-bias voltage.
In the meantime, the voltages VBB and VBBD become identical to each other at time t1, and thereafter the voltage VBB has a gradually lower absolute value than the voltage VBBD; therefore, the pass current Ix flowing into the back-bias voltage terminal VBB decreases and the voltage level at the connection node 22 increases, thereby changing the voltage output V28 of the delay circuit 26 to the logic high level being applied to the oscillator 100 (see FIGS. 3C and 3D). Then, the oscillator 100 is enabled and consequently generates pumping clocks as shown in FIG. 3E, the pumping clocks being applied to the pump circuit 300, so that the pump circuit 300 performs the pumping operation for the back-bias voltage from time t2. In prosecution of the voltage pumping operation, if the voltage VBB crosses the voltage VBBD at time t3, the voltage V22 at the connection node 22 decreases, thereby finally changing the input voltage of the oscillator 100 to the logic low level at time t4 as shown in FIG. 3E, so that the pumping operation halts at time t4. Since the pass current Ix flows into the back-bias terminal VBB even for the time when the pumping operation halts at time t4, the absolute value of the back-bias voltage will decrease again. In the meanwhile, if the back-bias voltage VBB becomes lower than the voltage VBBD at time t5, the foregoing operations will be repeated.
Furthermore, reference will now be made to FIG. 3F for showing the concrete operational curves of the back-bias level sensor 4 of FIG. 2. In the drawing, the curves V22, V27 and V29 represent the voltages at the connection nodes 22, 27 and 29, respectively. Since the gate of the PMOS transistor 21 of the back-bias level sensor 4 is provided with the ground voltage Vss, the gate-source voltage Vgs is independent of the power supply voltage Vcc. Therefore, the voltage at the output node 22 is greatly influenced according to the variation of the power supply voltage as shown in FIG. 3F. In addition, it takes a relatively long time for the pass current Ix to pass through the two MOS transistors 23 and 24, so that the back-bias level sensor has slow response characteristics.
As described above, the conventional back-bias level sensor of FIG. 2 is designed such that the back-bias voltage terminal VBB is under the direct influence of the pass current Ix for sensing the back-bias voltage, therefore resulting in the degradations of the back-bias voltage which are mainly caused by the pass current (for sensing the back-bias level) as well as the hole current of the substrate. As a result, it is therefore unavoidable to frequently turn on/off the oscillator 100 and the pump circuit 300 in the conventional back-bias generator, so that the reliability thereof (particularly of the back-bias level sensor) is low and the total current consumption of the back-bias generator is high. Furthermore, as shown in FIG. 3A, in the event that the back-bias voltage VBB changes abruptly to a different voltage level due to the pumping operation, a peak current flow is formed at the back-bias voltage terminal VBB. If this peak current is often generated due to the very frequent pumping operation, the device may be subjected to faulty operation or defectiveness and in the worst case, the dielectric breakdown phenomenon of the PMOS transistor 24 may occur at the gate oxide layer thereof. Both of the back-bias level sensors of the U.S. Pat. No. 4,471,290 and FIG. 2, may cause the same bad situation as above, in the light of the fact that the back-bias voltage is under the direct influence of the sensing current therefor. In particular, because in the circuitry of FIG. 2, the voltage applied to the gate of the load PMOS transistor 21 is independent of the power supply voltage, this back-bias level sensor is considerably influenced according to the variation of the power supply voltage. It will be further appreciated by a person skilled in the art that any conventional back-bias generator which employs the back-bias level sensor as described above will have the same problems.