This invention relates to solid-state nonvolatile memories and in particular, the use of such memories with disk drives to provide improved memory systems.
Disk drives are commonly used as mass data storage devices. Host systems such as Personal Computers (PCs) may have one or more Hard Disk Drives (HDDs) connected so that data may be sent from the host system to the HDD and later retrieved from the HDD. The data is stored in the HDD in a digital format where bits of data are represented by the magnetic orientation of portions of a layer of a magnetic medium on a disk generally referred to as a “platter.” Typically multiple platters are used in a single HDD. The platters rotate at high speed (such as 7200 rpm) and an arm moves read/write heads over platters to access data. HDDs have certain limitations because of their physical structure. Because the platters must rotate, power consumption may be higher than desired. The moving parts are susceptible to damage from shock, such as from dropping the device. Moving parts may also cause failure after an undesirably short period of time due to mechanical wear of parts that are in frictional contact as the platters rotate. Access times may be undesirably slow because of the latency due to moving the read/write head and platter to the appropriate positions before accessing a particular location. In particular, when a read or write command is received by an idle HDD, the platter may be stationary. It is then necessary to spin-up the HDD (rotate the platters at a predetermined speed) before executing the command, causing a considerable delay. Even if the platters are spinning, moving the head to the appropriate position may take significant time.
Solid-state nonvolatile memories provide an alternative form of data storage for certain applications. Solid-state memories do not have moving parts and may therefore use less power and be made to have a longer working life than HDDs. Also, because access to particular data does not require moving parts to the appropriate positions, solid-state memories typically have faster access times. Solid-state memories have no requirement to spin up before data may be accessed. Thus, their access time is generally faster and more consistent than that of a HDD, which can vary considerably depending on the position of the head and whether the platters are spinning. One example of a solid-state nonvolatile memory is an Electrically Erasable Read Only Memory (EEPROM). A block-erasable flash EEPROM is a common example of an EEPROM. Systems employing flash EEPROM have been commercially successful in the form of removable memory cards, such as CompactFlash™ (CF) cards, MultiMedia cards (MMC), Secure Digital (SD) cards, Smart Media cards, personnel tags (P-Tag) and Memory Stick cards. Flash EEPROM is also widely used in embedded applications.
Flash memory systems include an array of floating-gate memory cells and a memory controller. The memory controller manages communication with the host system and operation of the memory cell array to store and retrieve user data. The memory cells are grouped together into blocks of cells, a block of cells being the smallest grouping of cells that are simultaneously erasable. Prior to writing data into one or more blocks of cells, those blocks of cells are erased. User data are typically transferred between the host and the memory in sectors. A sector of user data can be any amount that is convenient to handle, preferably less than the capacity of the memory block, often being equal to the standard disk drive sector size, 512 bytes. In one commercial architecture, the memory system block is sized to store one sector of user data plus overhead data, the overhead data including information such as an error correction code (ECC) for the user data stored in the block, a history of use of the block, defects and other physical information of the memory cell block. Various implementations of non-volatile memory system are described in the following United States patents and pending applications assigned to SanDisk Corporation: U.S. Pat. Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,180, 6,222,762 and 6,151,248. These patents, along with all other patents, patent applications or documents referred to in this application are hereby incorporated by reference in their entirety for all purposes.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of memory systems are found in U.S. Published applications 20040012998A1 and 20050003616A1, which applications are hereby incorporated in their entirety by this reference.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements are described in U.S. patent application publication No. 2003/0109093 of Harari et al.
Solid-state nonvolatile memories generally have dedicated controllers that manage data storage in the nonvolatile memory array. The controller may be formed on the same chip as the memory array or on a different chip. Such a controller typically includes a microprocessor, read-only memory (ROM), random-access memory (RAM) and specialized circuits such as those responsible for performing Error Correction Code (ECC) functions.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips.
Although it is currently common to store one bit of data in each floating gate cell by defining only two programmed threshold levels, it is becoming increasingly common to store more than one bit of data in each cell by establishing more than two floating-gate transistor threshold ranges. A memory system that stores two bits of data per floating gate (four threshold level ranges or states) is currently available. Such memories may be referred to as Multi Level Cell (MLC) memories. Of course, the number of memory cells required to store a sector of data goes down as the number of bits stored in each cell goes up. Generally, in such systems, a block holds many sectors of data. A block may comprise one or more rows of a memory array, with each row storing multiple sectors of data. The block structure can also be formed to enable selection of operation of each of the memory cells in two states (one data bit per cell) or in some multiple such as four states (two data bits per cell). Multiple state flash EEPROM structures and their operation are described in U.S. Pat. Nos. 5,043,940, 5,172,338, 5,930,167 and 6,222,762, which patents are incorporated herein by this reference.
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of metablocks is described in U.S. Pat. No. 6,763,424, which is incorporated herein in its entirety. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. A metapage is a unit. of programming of data in a metablock. A metapage is comprised of one page from each of the blocks of the metablock.
Due to the difference in size between a sector (512 bytes) and an erase block or metablock (sometimes more than 128 sectors), it is sometimes necessary to consolidate sectors from one or more erase blocks, or metablocks, to another. Such an operation is referred to as garbage collection. Garbage collection operations reduce the write performance of a memory system. For example, where some sectors in a metablock are updated, but other sectors in the metablock are not, the updated sectors may be written to a new metablock. The sectors that are not updated may be copied to the new metablock, either immediately or at some later time as part of garbage collection. Examples of garbage collection operations are provided in U.S. Pat. No. 6,763,424 and U.S. patent application Ser. No. 10/750,155, which are both hereby incorporated by reference in their entirety. Another background operation that may be performed is a “Scrub” operation. This operation is performed to copy data that has threshold voltage levels outside a desired range and write the data with threshold voltages within the desired range. Such operations are described in U.S. patent application Ser. No. 10/678,345, which application is hereby incorporated by reference in its entirety.
Solid-state nonvolatile memories have several advantages over HDDs. However, solid-state memories generally cost more per unit of storage than HDDs and so HDDs are still commonly used for mass storage applications, particularly where large amounts of data are to be stored. Because of their low cost and high capacity, HDDs are likely to be used for some time to come. It is therefore desirable to improve the performance of HDDs, particularly to reduce power consumption, extend lifetime and increase speed.
Certain prior systems have combined HDDs and solid-state nonvolatile memories in order to improve memory performance. FIG. 1 shows an example of a disk drive system having a solid-state nonvolatile memory according to the prior art. In this system, the solid-state memory is incorporated into a HDD unit 120 and is under the control of a common controller 152. This allows common controller 152 to direct data from a host 154 to a solid-state nonvolatile memory 156 or directly to disk storage 158 as desired. This arrangement requires the addition of a solid-state nonvolatile memory 156 to HDD unit 150 and requires a controller that has additional functionality that is not usually present in such a controller. Thus, both hardware changes and software changes are needed in HDD unit 120 to implement this solution. Examples of HDDs that include a solid-state memory are provided by U.S. Pat. No. 6,016,530 by Auclair et al., which patent is hereby incorporated by reference in its entirety.
Therefore, there is a need for a memory system that improves HDD performance and may be implemented using existing HDD hardware and software. There is a particular need to improve HDD performance in the areas of power-consumption and lifetime. There is also a need for a module to improve HDD performance that may be added by an end-user without significant reconfiguration.