1. Field of the Invention
This invention relates to packaging of semiconductor devices. More particularly, this invention relates to a semiconductor device having an array of parallel leads directly bonded to the integrated circuit die perpendicular to the die layers.
2. Background Art
Typical prior art lead packages for semiconductor devices, such as integrated circuit dies, comprise the so-called dual in-line type packages wherein the die is bonded face up to a mounting pad and peripheral leads, located parallel to the plane of the die and mounting pad, are connected to contact pads, such as shown in Denlinger et al U.S. Pat. No. 4,173,768, on opposite edges on the die. The device is then encapsulated in plastic and the lead ends are bent perpendicular to the device. Duffek et al U.S. Pat. No. 3,947,867 illustrates such devices.
Such lead packages may include the provision of leads on all four edges of the die when further lead connections are needed. Typical lead packages of this sort are illustrated in Hayakawa et al U.S. Pat. No. 4,280,132; Burns U.S. Pat. No. 4,330,790; Brown U.S. Pat. No. 4,400,714; Grabbe U.S. Pat. No. 4,408,218; and Chiba et al U.S. Pat. No. 4,415,917.
Variations of this type of lead connection do exist, such as shown in Shen et al U.S. Pat. No. 4,236,171, where wires are bonded directly to pads of a power transistor, and Anazawa et al U.S. Pat. No. 4,340,901 wherein the end of the lead is bend at a right angle to permit it to be fastened perpendicular to the die to provide a stronger mechanical bond between the die and the lead.
Another packaging technique involves the so-called "flip chip" approach wherein the die is bonded face down to an insulative substrate as shown in Hantusch U.S. Pat. No. 4,288,808 and Test U.S. Pat. No. 4,423,435. This approach has been described, in connection with the use of spring loaded cooling pistons applied to the backside of the die, by Blodgett in "Microelectronic Packaging" in volume 249 of Scientific American (July, 1983) at pages 86-89. In this article the author describes a package termed a module which may have as many as 100 to 133 high speed chips bonded by the "flip chip" method to a substrate comprising 33 conductive layers which, together with a grid of vias, interconnect the dies together. A grid of pins or leads is brazed perpendicular to the opposite surface of the substrate to provide interconnection of the module to other electrical devices.
However, regardless of the type of prior art method used to provide electrical connection to the die, as more functions are integrated on one chip, the number of pin connections or "pin-out" increases. At the same time, the area required by each device or gate on a chip decreases. Thus, the industry is approaching a point where further reduction of die size will be limited not by lithography constraints but rather by the number of wire bond pads which can be placed around the perimeter of the die. Unfortunately, reducing the bond pitch or spacing reduces assembly yields. Furthermore, the increasing demand for switching speed is not compatible with the present packaging practices for lead placement where a signal must be routed to the perimeter of a die, through a wire bond pad to a lead finger, and then out of the package and down the lead to a circuit trace on a PC board.
These considerations have led to an increasing need to provide better packaging in the form of more leads to the die without, however, overcrowding the lead spacing.