The realization of increased data rates and operation of processor intensive applications, including multimedia, Internet access, etc., in future generation wireless communication systems, for example 3rd Generation W-CDMA systems and beyond, will require substantial amounts of memory and processing performance, which are constrained by cost, power consumption, packaging and other considerations.
In prior art FIG. 5, a known wireless communication architecture comprising discrete basesband and application processing circuits provides relatively good performance, but at a high cost and high part count, and with a large footprint.
In prior art FIG. 6, another known wireless communication architecture comprising integrated baseband and application processing circuits has a reduced the part count and a reduced foot print in comparison to discrete architectures of the type illustrated in FIG. 5. The RISC core performance in the architecture of FIG. 5, however, is limited by the memory system implementation, and DSP expansion is limited by the amount of on-chip memory.
The various aspects, features and advantages of the present invention will become more fully apparent to those having ordinary skill in the art upon careful consideration of the following Detailed Description of the Invention with the accompanying drawings described below.