FIG. 1 shows a conventional SONOS (semiconductor oxide nitride oxide semiconductor) memory cell 100 formed on a semiconductor substrate 102. The SONOS memory cell 100 includes a source bit-line junction 104 and a drain bit-line junction 106 formed within the semiconductor substrate 102. For example, the semiconductor substrate 102 may be a P-well formed within a silicon wafer with the bit-line junctions 104 and 106 having N-type dopant therein.
The SONOS memory cell 100 also includes a stack of a bottom dielectric 108 (typically comprised of silicon dioxide SiO2), an intermediate dielectric 110 (typically comprised of silicon nitride SiN), and a top dielectric 112 (typically comprised of silicon dioxide SiO2). A control gate structure 114 typically comprised of polysilicon is disposed on the top dielectric 112.
For storing a first digital bit, the substrate 102, the bit-line junctions 104 and 106, and the control gate structure 114 are appropriately biased for storing charge within a first charge storing region 118. The bias on the source and drain bit-line junctions 104 and 106 are then reversed for storing charge within a second charge storing region 120. In this manner, the SONOS memory cell 100 is a “multi-bit” memory cell storing multiple data bits.
An array of such SONOS memory cells is formed for a SONOS memory device. The area of such an array of SONOS memory cells is desired to be minimized for attaining higher data density of the SONOS memory device. However, the diffusion bit-line junctions 104 and 106 limit the lowest achievable area of the SONOS memory device. The bit-line junctions 104 and 106 further diffuse from thermal processes during fabrication of the SONOS memory device.
In addition, with diffusion bit-line junctions 104 and 106 for the prior art SONOS memory cell 100 of FIG. 1, contacts are formed onto the diffusion bit-line junctions between the word-lines within a core region having an array of such SONOS memory cells. Such higher number of contacts formed within the core region disadvantageously increases the area of the core region in the prior art. Furthermore, in the prior art array of SONOS memory cells of FIG. 1, STI (shallow trench isolation) structures are used to electrically isolated diffusion bit-line junctions of adjacent SONOS memory cells. Such STI structures disadvantageously add to the area occupied by the array of SONOS memory cells of the prior art.
Nevertheless, the area of the array of SONOS memory cells is desired to be minimized for attaining higher data density.