1. Field of the Invention
The present invention relates to a semiconductor device which is configured to form an element isolation region on a semiconductor substrate thereby to provide an element forming region and a method of manufacturing the same.
2. Description of the Related Art
Flash memories have conventionally been known as one of semiconductor devices of the above-mentioned type. In the flash memories, a shallow trench isolation (STI) is formed on a semiconductor substrate so that an active area is separately formed. Transistors are formed in the active area. JP-A-2004-356428 discloses one of such techniques. In the disclosed technique, an STI is formed as follows. Firstly, a silicon oxide film, a polycrystalline silicon film and a silicon nitride film are sequentially formed on the silicon substrate. These films are etched by a photolithography process into a predetermined pattern. A trench is formed in the silicon substrate. A silicon oxide film is buried in the trench, whereby an STI is formed in the silicon substrate and a surface of the silicon substrate is divided into element forming areas.
A planarization process is carried out by a chemical mechanical polishing (CMP) method. Furthermore, a level of the silicon oxide film buried in the STI is adjusted by a reactive ion etching (RIE) method and subsequently, a silicon nitride film is removed. Thereafter, an oxide-nitride-oxide (ONO) film for forming a control gate, a polycrystalline silicon film, a tungsten silicide (WSi) film and a silicon nitride film are sequentially formed, and a silicon oxide film is formed. Successively, the silicon oxide film, silicon nitride film, WSi film, polycrystalline silicon film and ONO film are sequentially etched by a photolithography process in the RIE method, so that a gate electrode is formed.
Subsequently, a silicon oxide film is formed on a sidewall of the gate electrode. Furthermore, another silicon oxide film is formed and etched. A silicon nitride film is then formed on the etched silicon oxide film. Thereafter, a silicon oxide film is again formed and a planarization process is carried out by the CMP method. Successively, a silicon oxide film is formed and a mask is formed by the photolithography process. Contact holes are formed and conductors are buried in the contact holes.
In case position gap of the pattern occurs in forming contact holes, an area of a part of the contact hole opposed to the element forming area of the silicon substrate is reduced such that a part of the conductor in the contact hole coming into contact with the element forming area is also reduced, whereupon the contact resistance is increased.
The aforesaid phenomenon necessarily occurs in the process which assumes a position gap of the pattern. The increase in the contact resistance is so small that the increase can be ignored in view of the degree of refinement. However, a recent reduction in the design rules has increased the contact resistance, thereby ill-affecting the characteristics of the elements. Such an increase in the contact resistance renders the writing time longer in an electrical writing operation, decreasing the functions of the elements.