1. Field of the Invention
An exemplary aspect of the invention relates to a method of manufacturing a semiconductor device and a semiconductor device. More specifically, an exemplary aspect of the invention relates to a method of manufacturing a semiconductor device for manufacturing a. Fin type transistor in an active region surrounded by a device isolation (STI, Shallow Trench Isolation) region, and a semiconductor device.
2. Description of the Related Art
In recent years, miniaturization of semiconductor elements such as transistors has been progressing in semiconductor devices including DRAM (Dynamic Random Access Memory) to meet requests for a higher integration density and a higher operating speed. With respect to a transistor having a conventional planar structure, it has been difficult to suppress the short channel effect when the gate length of a transistor formed according to the minimum fabrication dimension is 90 nm or less. To overcome this, study has been made of use of a Fin type transistor wherein a Fin-shaped portion (also called a Fin channel) is formed by working a semiconductor substrate into a three-dimensional structure having island-like portions with projecting surfaces and wherein a side surface of such a projecting island is used as a channel.
Fin type transistors are described in Japanese Patent Application Laid-Open Nos. 2006-279010, 2006-310458, 2007-42790 and 2006-5344. Particularly, Japanese Patent Application Laid-Open Nos. 2006-279010, 2006-310458 and 2007-42790 each describes a process wherein a Fin channel is previously formed using a combination of a mask and RIE (Reactive Ion Etching) for example, for example; wherein a STI region or air insulation is provided on opposite sides of the Fin channel; and wherein the Fin channel is exposed in a later step.
Conventional Fin type transistors have a problem described below. FIG. 27 shows one exemplary plane layout of a memory cell array of DRAM. Memory cell array 100A of DRAM includes STI regions 102 and active regions 103 each surrounded by STI regions 102. One active region 103 is provided with two gate electrodes 104. Gate electrodes 104 each represented as a diagonally shaded area in FIG. 27 serve also as word lines. Source regions 105 are provided on opposite outer sides of two gate electrodes 104 forming a pair, while common drain region 106 is provided inside the pair.
Since STI regions 102 and active regions 103 are formed based on a minimum fabrication dimension determined by a resolution limit of lithography, there is no margin for working in the plane. For this reason, in forming a Fin channel with the narrow width Lg of gate electrode 104 (i.e., the width of a channel region) in active region 103, the width Ls of source region 105 and the width Ld of drain region 106, which are located adjacent to the channel region, are inevitably narrowed. As a result, the areas of the top surfaces of source regions 105 and drain regions 106 become smaller, so that the contact resistance between each of them and a respective one of contact plugs formed on the top surfaces increases, thereby raising a problem of a delayed circuit operation.
The techniques described in Japanese Patent Application Laid-Open Nos. 2006-279010, 2006-310458 and 2007-42790 have a problem that it is difficult to form a Fin channel as designed because the shape of a mask (film pattern) used in the formation of the STI regions for example is impaired by a later process.
An exemplary object of the invention is to provide a method of manufacturing a semiconductor device which is capable of forming a Fin channel as designed, as well as a semiconductor device.
Another exemplary object of the invention is to provide a method of manufacturing a semiconductor device which is capable of narrowing only the width of a Fin channel while maintaining the widths of source and drain regions located adjacent to a channel region, as well as a semiconductor device.