1. Field of the Invention
The present invention relates generally to electrical circuits and, more particularly, to the generation and synchronization of multiple clocks.
2. Related Art
Modern multi-channel data systems typically require parallel streams of data to be transmitted and received. The parallel data streams (or channels) can be aggregated into a smaller number of higher-bandwidth channels, which in data communications terms is commonly referred to as trunking. For the data to be aggregated, tight skew budgets are required of the system, where skew is defined as the phase relationship between each channel of data.
Serial data communications generally utilize a clock multiplier, such as a phase-locked loop (PLL) circuit. The PLL circuit phase and frequency locks to a reference clock and generates high-speed clocks to clock the data. To achieve low skew across multiple data paths (i.e., parallel data streams or data channels), the generated clocks must be carefully synchronized and aligned.
Typically, a PLL circuit or a delay-lock loop (DLL) circuit is utilized for each channel to reduce skew. For example, each PLL circuit is locked to a global reference signal whose distribution is tightly controlled. However, using numerous PLLs requires a significant amount of power and space, both of which are often very limited.
An alternative method utilizes a first-in first-out (FIFO) buffering scheme to cross clock domain boundaries for unsynchronized systems. One drawback is that a FIFO buffer introduces latency and skew. Also, for integrated circuits, the latency and skew may be uncontrolled over process, voltage, and temperature variations or corners. Furthermore, the FIFO buffers require additional logic to monitor and reset associated pointers and the FIFO buffers also consume valuable power and space.
Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. These benefits are preserved across process, voltage, and temperature variations. The FIFO buffering scheme of the prior art, which introduces latency and skew, can be eliminated and, for example, the ability to use a single clock source is provided, which offers a reduction in power and area requirements.
In accordance with one embodiment of the present invention, a system for synchronizing a plurality of data channels includes a core circuit having a clock distribution circuit, with the core circuit providing a plurality of data streams at a frequency of a core clock signal carried by the clock distribution circuit. A first phase-locked loop circuit generates a plurality of clock signals, wherein a first clock signal from the plurality of clock signals has the same frequency and substantially the same phase as the core clock signal carried by the clock distribution circuit. A plurality of channel circuits are coupled to the core circuit and to the first phase-locked loop circuit, with the channel circuits converting the plurality of data streams, received at a frequency of the first clock signal, into a plurality of serial data streams at a frequency of a second clock signal from the plurality of clock signals. The first phase-locked loop circuit or a second phase-locked loop circuit may provide the core clock signal to the clock distribution circuit.
In accordance with another embodiment of the present invention, a method of synchronizing a plurality of data channels includes receiving a reference clock signal; generating a plurality of clock signals based on the reference clock signal and providing a core clock signal from the plurality of clock signals to a core circuit, wherein data is transferred from the core circuit through a plurality of data paths at a clock rate of the core clock signal; receiving the data, transferred through the plurality of data paths, by corresponding channel circuits at a clock rate of a first clock signal from the plurality of clock signals, the first clock signal having the same frequency and substantially the same phase as the core clock signal; and transforming the data received by each of the channel circuits from a parallel to a serial data stream at a clock rate of a second clock signal from the plurality of clock signals.
A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.