The performance of logic has increased by orders of magnitude over the past decade. While the performance of memory has increased, such improvement substantially lags the increase in the performance of logic. Memory may be a bottleneck in systems ranging from servers to routers to communications equipment. For example, the Internet revolution dramatically accelerated network performance requirements, but the technological limits of dynamic random access memory (“DRAM”) and static random access memory (“SRAM”) have created a bottleneck defined by the slow speed of DRAMs and the low density of SRAMs.
System designers have struggled for years to find a solution that successfully matches the density of DRAM with the high speed of SRAM. In recent years, a memory cell based on Negative Differential Resistance (“NDR”) was developed as a form of thyristor-based SRAM cell. It generally provides SRAM speeds along with DRAM density. More detailed information about such memory cells can be found in U.S. Pat. Nos. 6,229,161 B1, 6,767,770 B1, and 6,690,039 B1.
However, charge leakage out of such a thyristor-based SRAM cell negatively impacts the restore rate of such cell. Additional details regarding periodically pulsing a thyristor-based SRAM cell to restore state of such a cell may be found in Patent Cooperation Treaty (“PCT”) International Publication WO 02/082504. Moreover, an access device associated with such thyristor-based SRAM cell increase the area, namely increase the cell “footprint.”