In a conventional type of frequency synthesizer, as shown in FIG. 6, a signal 2 indicating a reference frequency f.sub.0 generated from a reference signal generator 1 is supplied as input to a phase comparator 3, and a signal 7 obtained by dividing output from a voltage controlled oscillator (VCO) 5 with a frequency divider circuit 6 is connected to another input terminal of a phase comparator 3 for comparison of the phases. Output 8 from phase comparator 3 is supplied as input to a loop filter 4 and then connected to the VCO 5 to control the VCO, thus a feedback loop being completed. Frequency division ratio N of the frequency divider circuit 6 is programmable, so that it is possible to obtain output from the VcO as a synthesizer output of N.times.f.sub.0 due to convergence of the feedback loop. Generally a loop filter fully intercepts a reference frequency component, so that a time required for convergence of a feedback loop is limited to a value corresponding to a cycle of the reference frequency or below. For this reason, a conventional type of feedback loop can not be applied as it is to a synthesizer which requires a relatively high switching time.
As means for solving the problem in the conventional type of frequency synthesizer, a direct digital synthesizer (DDS) as shown in FIG. 7 is available. In this type of synthesizer, a frequency setting circuit 10 programs a phase increment 11 for unit clock corresponding to a frequency to be generated, the phase increase 11 is supplied as input to a phase accumulator 12, and accumulation of phase for unit clock of a clock signal 23 from the clock generator 21 is computed. A cumulative phase 13 is supplied as input to a ROM in which a value of sinusoidal waveform corresponding to each phase stored, and output from the ROM is connected to a D/A is convertor 15 and provided as output as a sinusoidal wave 16 converted into analog voltage. Analog output 16 is voltage sampled at a clock cycle, so that the waveform is as shown in FIG. 8A and includes many harmonic components. So a required synthesizer output 18 having a waveform as shown in FIG. 8B is obtained after removing the higher harmonic components by inserting a low-pass filter (LPF) 17. By introducing the configuration as described above which is not a feedback loop configuration, high speed switching has become possible.
However, the DDS shown in FIG. 7 uses a logic section (consisting of a phase accumulator and a ROM) and a D/A convertor to generate a signal, so that an operating speed of the DDS is limited by the two components above, and can hardly generate a relatively high frequency. Also, when trying to generate a relatively high frequency, the clock frequency must be made higher, which in turn makes power consumption in the logic circuit and the D/A convertor disadvantageously higher.