This invention relates to a voltage limiter apparatus employing MOSFETs and more particularly to a logic circuit employing a voltage limiter with inherent level shifting capabilities.
Voltage limiting is often employed to assure that a voltage at a given terminal remains relatively constant with respect to supply variations. Such voltage limiting circuits are well known and conventional circuits employ Zener diodes, cascaded strings of diodes, as well as other devices, to provide a relatively fixed potential across first and second terminals in spite of a varying power supply.
It is also known that level shifting capability is required in many circuit operations. For example, when interfacing one type of digital IC with another, attention must be given to the logic swing, output drive capability, DC input current, noise immunity, and speed of each device. Hence the prior art is replete with a number of various level shifting circuits for coupling, for example, MOSFETs to other types of logic including TTL and medium powered DTL logic circuits.
In employing such interfaces or level shifting devices, it is important that an output device will switch through the switch point of the succeeding logic stages. In this manner if the switch points are maintained then the circuits, as delay circuits and so on, will exhibit compatible switching and in spite of power supply variations the propagation delay through the logic circuits will remain constant. This will occur, for example, if the reference switching voltage is maintained at a relatively constant level with respect to variations in the positive and negative supply potentials.
It is of course understood that no matter which load and drive characteristics are involved for a digital MOS device, it may be necessary to include some form of level shifting between the devices to provide the necessary driving levels. This is especially true when the device data sheets show a very close tolerance. Thus, it is not practical to have a universal interfacing circuit for MOS devices of different manufacturers. Likewise, it is not even possible to have a universal circuit for interfacing between the MOS device of one manufacturer and all other logic families.
For example, the logic voltage levels, as 0 and 1, the supply voltages, and the temperature ranges vary with MOS manufacturers and with each logic family. For that reason most MOS manufacturers publish interfacing data for their particular product lines. Thus, as one can understand, interfacing even within the same logic families of MOS devices is an extremely difficult task as one must assure that the devices will switch between 0 and 1 for a wide range of input levels. This switching should occur for power supply variations as well.
It is therefore an object of the present invention to provide a voltage limiter which will establish a voltage difference to cause the switch point of a P- and N-MOS device to be optimumly controlled and to track with variations in supply voltages.
It is a further object to employ the above-noted voltage limiter as a source of supply for additional logic circuits to assure that the additional circuits will exhibit reliable switching relatively independent of variations of the main supply voltages and without the need for a separate level shifting device.