Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs. A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to implement vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes memory cell pillars extending through tiers of alternating conductive structures and insulative structures, with the conductive structures functioning as control gates. The memory cell pillars include a channel region positioned between a source region and a drain region. The configuration permits a greater number of electrical components (e.g., transistors) to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of electrical components.
To apply a potential to the memory device, a doped silicon wafer or an electrically conductive material above an interconnect is used as a source. To electrically connect the channel regions of the memory cells to the source, a so-called “pillar punch” etch process is conducted for each deck of tiers. A sacrificial polysilicon material is formed over a cell material to protect the cell material during the subsequently-conducted pillar punch etch process, which removes the sacrificial polysilicon material and underlying cell material at a bottom of the memory cell pillars. After conducting the pillar punch etch, the remaining sacrificial polysilicon material is removed, and channel material is formed over the cell material. In memory devices including multiple decks of tiers, a pillar punch etch process is conducted for each deck for proper alignment. However, as aspect ratios of the memory cell pillars continue to increase, alignment issues between the decks of tiers makes the pillar punch etch challenging.