Static RAM (SRAM) arrays are commonly used in digital data processing applications, e.g., as FIFO's in video displays and digital communication devices. This type of application frequently requires the SRAM array to be preset to a particular value. That is, each cell in the SRAM would be set to a logic 0 or a logic 1 by a write command. If the cells are preset sequentially by a series of write commands, the process can be very time consuming, especially for high density SRAM arrays. On the other hand, if all the cells in a high density SRAM are simultaneously preset, the resultant current surge can generate a significant amount of noise on the power supply rail. This power noise may cause significant malfunctions in both digital and analog circuit components, as well as causing inadvertent data alterations in various memory components of the system. Since industry trends require continuing increases in the number of memory bits per chip, thus increasing the density requirements of SRAM arrays, it is incumbent upon the chip designer to develop presetting techniques for high density SRAM arrays which are not excessively time consuming, and which do not cause the undesirable current surge problem noted above.
FIG. 1 shows a typical prior art SRAM structure, configured with p words and q bits. Each p word represents an access unit. In this example, q parallel bits are simultaneously accessed in response to a read or a write operation. The SRAM comprises an address decoder 1, an array 2, and an IO gateway 3. The array 2 has p by q entries. A single bit, e.g., BITO 20, comprises p cells of different addresses and companion devices on internal data lines for facilitating data access. Address decoder 1, in response to an address bus, decodes address lines for the p words. IO gateway 3 has q cells, each associated with a single bit, and provides a data path for writing data from a data bus to array 2, and also for reading data from array 2 to the data bus.
FIG. 2 shows address decoder 1 and single bit 20 of FIG. 1 in greater detail. The array cells of single bit 20 are organized in mn rows and n columns, where m.times.n=p. Address decoder 1 is divided into a row address decoder 11 and a column address decoder 12. Row address decoder 11 decodes m row address lines X0, X1, . . . , Xm-1 for the m rows. Column address decoder 12 decodes n column address lines Y0, Y1, . . . , Yn-1 for the n columns. Array cells of a same row share, and are cascaded by, a row address line, e.g., X0 . Array cells of a same column are shunted along a pair of data lines, e.g., C0 and CN0. The data lines of the n columns are combined into a pair of bit lines, B and BN, by n switches, each switch corresponding to one of the n columns. Each column address line outputted from column address decoder 12 (Y0, Y1, etc.) controls the turning on/off of the corresponding switch. Each pair of data lines (C0, CN0, etc.) is charged by a precharge cell, e.g., 201, which equalizes both data lines to a certain voltage level when no access event occurs. There is also a precharge cell 202, which performs the same voltage equalizing function on the pair of bit lines B and BN. An IO circuit 203, in response to a write control signal, passes data on the data bus to bit lines B, BN. In response to a read control signal, IO circuit 203 senses the voltage difference between the bit lines B, BN, and outputs a definite logic state to the data bus.
Each array cell is typically a six-transistor or a four-transistor memory cell within a CMOS circuit. Each switch is typically an NMOS pass transistor. The pairs of data lines Cj, CNj (j lies between 0 and n-1) and pairs of bit lines, B, BN are complementary. IO circuit 203 typically contains an input buffer and a sense amplifier operating exclusively in respective write and read access cycles.
In the special case where n=1, the array cells are constructed as p rows by one column, and the switches, the column address decoder 12, and the precharge cell 202 can be omitted. The row address lines Xi (i lies between 0 and m-1) represent exactly the word lines of the array cells, and the data lines Cj, CNj represent exactly the bit lines B, BN of the array cells.
As stated above, presetting each array cell sequentially can be very time consuming, whereas simultaneous presetting, or simultaneous resetting/clearing, may generate current surge noise problems.
One prior art technique to overcome the current surge problem when simultaneously resetting/clearing multibyte data is described in U.S. Pat. No. 5,212,663, by Leong. In this invention, an array of flag bits is added to the memory cell array of a SRAM, such that each word line of the memory cell array is associated with a corresponding flag bit. The flag bits are set to a "1" logic state for those word lines whose data was not previously altered. A reset control circuit is used to create a logical relationship between the flag bits and the sensed data bits, so that the resettable SRAM chip presents a "0" output logic state for all bits of the selected data when the selected data flag bit is set to a "1" logic state, irrespective of the actual content of the data in the memory cells. Thus, the need to reset all the memory cells in the array is eliminated through the use of flag bits.
This prior art technique, however, does not allow for the presetting of a SRAM array to a particular value without initially writing to each cell. Accordingly, it is an object of the present invention to overcome this limitation of the prior art; i.e., to preset a SRAM array to a particular value without initially writing to each cell. It is a further object of the present invention to avoid the problems of excessive time consumption (sequential preset) and noise generation from current surges (simultaneous preset), as described above.