A. Field of the Invention
The present invention relates to a semiconductor device. Particularly, it relates to a power semiconductor device such as an insulated gate bipolar transistor (IGBT), an insulated gate field effect transistor (MOSFET), etc. which is a semiconductor device having an insulated gate structure (MOS structure).
B. Description of the Related Art
FIG. 13 is a schematic plan view of an IGBT according to the background art. In the following description, “n” expresses that the conductivity type of an impurity is an n type, and “p” expresses that the conductivity type of an impurity is a p type.
In FIG. 13, reference numeral 101 designates an n semiconductor substrate; 102, a p base region; 106, gate electrodes made of polysilicon; 107, a polysilicon gate wiring connected to the gate electrodes 106; 111, an emitter electrode; 112, a metal gate wiring formed on the polysilicon gate wiring 107; 120, a gate pad connected to the metal gate wiring 112; and 140, a semiconductor chip (hereinafter simply referred to as chip).
As shown in FIG. 13, in the IGBT having striped cells according to the background art, gate electrodes 106 shaped like stripes are arranged regularly on the whole surface of chip 140. That is, gate electrodes 106 are arranged linearly at intervals of an equal pitch which is common to the central portion and the peripheral portion of chip 140. Such regular arrangement is common to all gate structures regardless of whether the gate structure is a planar structure or a trench structure. In addition, such regular arrangement also applies also to a power MOSFET.
FIGS. 14A and 14B are plan views schematically showing temperature distributions in a surface of the IGBT chip. FIG. 14A is an isothermal chart showing a situation where the temperature of the central portion is high. FIG. 14B is an isothermal chart showing a situation where the temperature of a half of the chip becomes high. In FIGS. 14A and 14B, dotted lines are isothermal lines 141.
As shown in FIG. 14A, in an ordinary IGBT, the temperature distribution in a surface of chip 140 is such a mountainous distribution that the temperature of the central portion of chip 140 is highest and the temperature decreases as the location goes from the central portion of chip 140 to the peripheral portion of chip 140.
Such a temperature distribution is caused by balance of heat generated due to a current flowing in chip 140 and heat radiated from a collector electrode in a rear surface not shown to the substrate in which chip 140 is mounted. The thermal path contributing to heat radiation in the central portion of chip 140 is only one path (vertical path) through which heat is transmitted in a depth direction of chip 140 mainly toward the collector electrode.
On the contrary, the thermal paths contributing to heat radiation in the peripheral portion of chip 140 are excellent in heat radiating property because the thermal paths are not only the aforementioned vertical path but also a path (horizontal path) through which heat is transmitted toward end portions of chip 140. Accordingly, the aforementioned mountainous temperature distribution is obtained. Such a temperature distribution is formed also in a power MOSFET.
On the other hand, the case where the temperature of a half (an upper half in FIG. 14B) of chip 140 reaches a high temperature as shown in FIG. 14B occurs when a bonding wire connected to emitter electrode 111 is fixed to only a lower half of chip 140 but there is no bonding wire in an upper half of chip 140.
If some void not shown is present in a solder layer under the collector electrode in the rear surface of chip 140, the thermal resistance of the void portion increases to generate heat so locally that the temperature distribution in a surface of chip 140 cannot be equalized.
A method of equalizing the temperature in the temperature distribution as shown in FIG. 14A has been described in JP-A-2004-363327. According to JP-A-2004-363327, in this method gate electrodes 106 are disposed sparsely in the central portion of chip 140 but are disposed densely in the vicinities of the end portions of chip 140 as shown in FIG. 15. Although the gate electrodes designated by broken lines in FIG. 15 are called “unit cells” in JP-A-2004-363327, the gate electrodes constituting the unit cells are extracted and shown here.
With this configuration, current density in the central portion becomes low but current density in the peripheral portion (the vicinities of the upper and lower end portions in FIG. 15) becomes high, so that the amount of heat generated in the central portion decreases but the amount of heat generated in the peripheral portion increases. On the other hand, the amount of heat radiated from the central portion decreases but the amount of heat radiated from the peripheral portion increases. Accordingly, the temperature distribution in a surface of chip 140 is equalized because of balance of the amount of generated heat and the amount of radiated heat.
In the method according to JP-A-2004-363327, the gate electrode (unit cell) densities in the peripheral portion and the central portion are determined at a manufacturing stage, so that it is however difficult to attain equalization of the temperature except in the case where the central portion of chip 140 rises in temperature.
Moreover, when current density becomes high as a current conducted becomes large, the difference between the amount of heat generated in the central portion and the amount of heat generated in the peripheral portion becomes so large that it is difficult to balance the amount of generated heat and the amount of radiated heat with each other in all the current density range on the whole surface of chip 140, that is, temperature unbalance can be merely improved in a limited current density range.
When the temperature distribution is as shown in FIG. 14B, it is necessary to dispose gate electrodes 106 in accordance with the temperature distribution, that is, it is unrealistically necessary to change the arrangement of the gate electrodes 106 in accordance with the temperature distribution at a manufacturing stage. Moreover, the method according to JP-A-2004-363327 cannot be applied to the case where the temperature distribution in a surface of chip 140 varies according to how to use.
Moreover, as for module 142 having a large number of chips 140 disposed therein as shown in FIG. 16, the method according to JP-A-2004-363327 cannot equalize the temperatures of chips 140.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.