1. Technical Field
This invention relates generally to hardware performance counters, and more particularly to multiple-counter value hardware performance counters.
2. Description of the Prior Art
Hardware performance counters are used in many computing systems to collect information on the operation of hardware. They typically are present in processors and/or chipsets that support the processors. A hardware performance counter typically includes an event specifier, various control bits, a register to hold the count value, and increment hardware. To maintain multiple count values, such as to count the occurrences of different events, multiple complete hardware performance counters usually have to be maintained. This is implementation inefficient, and requires redundant hardware components, such as redundant instances of the increment hardware, for the hardware performance counters.
As a result, typically only a limited number of counters are provided, relative to the number of events of which occurrences can be counted. This means that the occurrences of only a few events may be counted during a specific time period. To obtain correct results for a large number of events usually requires the operations to be constant across multiple time periods. A subset of the events is then measured within each time period. This limits the usefulness of the hardware performance counters, and may constrain the construction of computer programs that rely on the counters to count event occurrences.
Software-based performance counters may alternatively be employed. Such counters are typically defined using an array in a high-level language, or having individual variables for each event being counted. An array implementation may have one or more dimensions, depending on whether qualifiers to the events are to be considered when collecting count values. One dimension of the array is assigned to the events, and the second dimension is assigned to the qualifiers, for instance. High-level languages then store the multidimensional array within physical memory, which is conceptually a single dimensional array.
However, the programmer has no control over how the compiler and the hardware then translates a software index to the multidimensional array down to physical addresses. That is, the programmer has no control over how the multidimensional array maps to physical memory. This can lead to degradation in performance and/or in memory utilization, inhibiting the efficiency of software-based performance counters. Furthermore, software-based performance counters are likely to be inherently slower than hardware-based performance counters, since they really on general-purpose hardware and machine-level instructions for implementation and execution, as opposed to special-purpose hardware that has its operations coded into the hardware. Software-based performance counters are thus likely to be less efficient than hardware-based performance counters.
For these described reasons, as well as other reasons, there is a need for the present invention.