Computer systems or other electronic circuits typically include multiple electronic devices or chips to provide functionality. In systems where one or multiple devices or chips are enabled or disabled because the devices or chips share a communication bus or for other reasons, it is necessary to provide connections for a device/chip enable signal to each device/chip that needs to be enabled and disabled. One example is a group of memory devices/chips that share a bus in a computer system. “Memory” usually refers to a form of semiconductor storage, such as random access memory (RAM), read-only memory (ROM), flash memory, and other forms of fast but temporary storage. There are many computer memory types, including: 1) volatile memories such as Dynamic Random Access Memory (DRAM), e.g. Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), and Static Random Access Memory (SRAM); and 2) non-volatile memories such as Read-Only Memory (ROM), e.g. Programmable Read-Only Memory (PROM), Electrically Alterable Programmable Read-Only Memory (EAROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash memory. All of these types of memories commonly provide an enable/disable input, for selectively enabling or disabling the device.
To provide an enable signal for multiple memory devices/chips, the same number of physical signal lanes/traces as the number of memory devices/chips can be laid out from a memory controller to memory devices/chips. In the alternative, a buffer chip, e.g. a Complex Programmable Logic Device (CPLD), can be used between a memory controller and the memory devices, with reduced number of physical lanes between the memory controller and the buffer chip. The buffer chip can receive an encoded enable signal from the memory controller and send appropriate enable signals to the memory device based on the decoded enable signal. By encoding the selection of memory device to enable/disable, the number of enable signal traces can be reduced between the memory controller and the buffer chip that is located in relative proximity of the memory devices/chips. Each memory device can be enabled or disabled from the buffer chip output to each memory device.
However, it is desirable to further reduce the number of physical traces of enable signals for a group of memory devices/chips, to reduce cost and complexity of electronic circuit boards.