1. Field of the Invention
The present invention relates to a plasma display device using a plasma display panel.
2. Description of the Related Background Art
There is known an AC (alternating current) type PDP (plasma display panel) as one display panel in a scheme of matrix display. The AC type PDP has a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs which are arranged orthogonal to the column electrodes and which each form a scanning line. Each of the row electrode pairs and each of the column electrodes are covered by a dielectric layer for a discharge space, providing a structure forming a discharge cell, corresponding to one pixel, at an intersection of each of the row electrode pairs and each of the column electrodes.
Here, there is so-called a subfield method in which one field period is divided into N subfields to perform light emission for a time period corresponding to weighting for each bit figure of N-bit pixel data, as one method to realize halftone display on the PDP.
FIG. 1 shows a format of light emission drive in one field period of the subfield method.
In the example shown in FIG. 1, the light emission drive is implemented by dividing the one field period into six subfields of SF1, SF2, . . . , SF6 on an assumption the pixel data to be supplied has 6 bits. By performing light emission with the six subfields, expression is available with 64 gray-scale levels for an image of one field.
Each of the subfield is constituted by a reset stage Rc, an address stage Wc and a sustain stage Ic. By simultaneously generating discharge (reset discharge) in all the discharge cells of the PDP in the reset stage Rc, wall electric charge is formed uniformly in each of the discharge cells. In the next address stage Wc, discharge for selective erasure is caused for some of the discharge cells in accordance with the pixel data. The wall electric charge is canceled in discharge cells where the erasure discharge has been done, thus placing those discharge cells as “unlighted cells”. Meanwhile, the other discharge cells that the erasure discharge has not been done remain in a state the wall electric charge still stays, thus being rendered as “lighting cells”. In the sustain stage Ic, light emission is continued by sustain discharge as to the lighting cells for a time period corresponding to weighting in the subfield. Thus, in each of the subfields SF1-SF6, the light emission is done for a period corresponding to an emission period ratio of 1:2:4:8:16:32 in the order.
In the address stage Wc, in the case of adopting a selective-erasure address scheme to selectively erase the wall electric charge formed in the discharge cells, it is necessary to perform a reset stage Rc, shown by hatching in FIG. 1, in the beginning of each of the subfields. However, the reset discharge, which is performed in all the discharge cells in the reset stage Rc, is comparatively intense discharge, i.e. a high level of light emission. Thus, there is a problem that image contrast is lowered since the light emission occurs regardless of pixel data at six points shown by hatching in FIG. 1.
For this problem, there is a proposed sequence that reset discharge is generated to form wall electric charge in each discharge cell in the beginning of one field so that selective erasure addressing can be done only in one of the subfields thereby improving the contrast, as disclosed in Japanese Patent Application Kokai No. 2000-227778.
However, with the sequence, priming effect based on the reset discharge is reduced. Therefore, in order to reliably cause discharge by application of each drive pulse, it is necessary to increase the width of each drive pulse.