Prior art flash memory chips (also called simply “flash memories”) 101 and 102 (FIG. 1A) internally contain one or more arrays of cells that are formed of NAND logic gates or NOR logic gates or some combination thereof. Flash memories 101 and 102 are typically coupled to interface logic (also called “processor” or “flash controller”) 104A as illustrated in FIG. 1A. The combination of flash memory chips 101 and 102 and interface logic 104A (FIG. 1A) are typically used by other hardware (not shown) in a prior art device 100A (FIG. 1A), to store data in a flash manner. Examples of prior art device 100A are a music player, a cell phone, a personal digital assistant, or a computer. Note that the prior art device 100A of FIG. 1A includes a direct memory access (DMA) controller 105 in an electronic component (also called “processor” or “flash controller”) 104A which can operate faster than another electronic component 104B (FIG. 1B) that does not have a DMA controller, as shown in a similar prior art device 100B (FIG. 1B).
Prior art device 100A (FIG. 1A) typically includes a bi-directional bus (also called input-output bus or “I/O bus”) 103I that can be used at any given moment in time to transfer data and/or address signals (e.g. 8 bits at a time) between flash controller 104A and any one of flash memories 101 and 102. Prior art device 100A further includes multiple control buses 103C1, 103C2 that are typically used simultaneously at the given moment in time (during data/address transfer) to additionally transfer control signals between flash controller 104A and a corresponding one of flash memories 101 and 102. Typically, while flash controller 104A is communicating with one flash memory 101 by transferring commands and/or addresses and/or data over I/O bus 103I, the other flash memory 102 cannot use I/O bus 103I and vice versa. Hence, prior art flash controller 104A known to the inventors waits for flash memory 101 to complete before communicating with flash memory 102.
Prior art processor 104A may store data in flash memory 101 by executing a prior art method 110 of the type illustrated in FIG. 1C. Specifically, in a first act 111, flash controller 104A issues a write command to flash memory 101 (also called chip #1) including, for example toggling a write enable (WE) line once while driving active a chip enable (CE) line and a command latch enable (CLE) line to chip #1 via flash control bus 103C (FIG. 1A), and simultaneously driving command signals via I/O bus 103I (FIG. 1A). Next, by toggling the write enable (WE) line while driving active a chip enable (CE) line and an address enable (ALE) line and simultaneously driving address signals on I/O bus 103I, an act 112 is performed wherein flash controller 104A (FIG. 1A) writes an address to chip #1, via I/O bus 103I. Next, while toggling the write enable (WE) signal on the flash control bus 103C and driving the CE line active and simultaneously holding both CLE and ALE lines inactive, another act 113 is performed wherein flash controller 104A writes data to chip #1, also via I/O bus 103I. To summarize, data to be stored in a flash manner are transferred via the shared I/O bus 103I to chip #1, which temporarily holds the data in a buffer (also known as a “page buffer”).
Next, while toggling the WE signal and simultaneously driving active the CE and CLE signals on the flash control bus 103C, act 114 is performed wherein flash controller 104A issues a program command to chip #1 to write the data from the page buffer to its internal array of cells at an address that was specified in act 112 (and received via I/O bus 103I). Chip #1 responds to the program command from flash controller 104A after completing the write to its internal array of cells, followed by reading back the stored data from the specified address and comparing the read-back data with data in the page buffer. The result of comparison is stored by chip #1 in a readiness register that is accessible to flash controller 104 via I/O bus 103I.
Hence, to the knowledge of the current inventors, prior art flash controller 104A enters a loop to check on readiness of chip #1 as per act 116. The specific loop entered at this stage depends on the design of prior art device 100A. In one implementation, in act 115, flash controller 104 retrieves the value of a readiness register or status register in chip #1 and then in act 116 it checks whether the just-retrieved value from chip #1 indicates that chip #1 is ready. Alternatively, prior art flash controller 104A may monitor a ready/busy line in control bus 103C1, driven by chip #1 (as illustrated by branch 162 in FIG. 1C).
A ready signal of chip #1 typically becomes active after chip #1 completes the previously-issued commands, namely the program command in act 114. Hence, when the program command is completed, the ready signal from chip #1 goes active, and flash controller 104A then performs act 117 to check if the copy-back by chip #1 indicates a match in the comparison of data (between the internal array and the page buffer). If there was a match, the write command completed successfully, and flash controller 104A exits method 110, for chip #1.
Referring back to method 110, in case the program command is found in act 117 to have failed, prior art flash controller 104 goes to act 118 to perform error-handling actions, e.g. map out a block at the previously-specified address and issue another program command at a different address of another block in chip #1 (in order to re-write the same data), and thereafter exits. After exiting method 110, flash controller 104 may start performing method 110 again, for a new operation. For example, the new operation may be to store new data on either one of chip #1 and chip #2. Alternatively, the new operation may be to retrieve previously-stored data from any one of chips #1 and #2, for example. Note that prior art flash controller 104 performs method 110 (and hence an operation) on only one of chips #1 and #2 at any given time.
A data sheet entitled “1 G×8 Bit/2 G×8 Bit/4 G×8 Bit NAND Flash Memory” published in 2005 by SAMSUNG Electronics CO., LTD is incorporated by reference herein in its entirety. This data sheet discloses a prior art method of interleaving the programming of a page of data between two K9F4G08U0M dies that are identical to one another and are included in a single K9K8G08U0M package. The interleaving method of this data sheet is illustrated by a timing chart shown in FIG. 1D (attached hereto for convenience), for a page programming operation. As stated in the data sheet, a host can issue a page program command to chip #2 in state A while chip #1 is already executing a page program operation. In state C, the system should issue a F1h command to detect the status of chip #1. If chip #1 is ready, a bit 6 in the status register is set to “1” and the system can issue another page program command to chip #1. Although FIG. 1D illustrates just a write operation, the just-described data sheet also includes other interleaved operations, such as block erase, and two-plane page programming. Accordingly, the data sheet should be reviewed for further details.
The inventors of the current patent application note that above-described prior art interleaving method has certain limitations and constraints. Firstly, the inventors note that the same type of operation is described as being interleaved between chip #1 and chip #2, e.g. both chip #1 and chip #2 perform a write operation in FIG. 1D. This is an explicit limitation of prior art in the above-described data sheet, because the data sheet says that during interleave operations, the “70h” command (to read status register) is prohibited. Secondly, the method depicted in FIG. 1D can be used only in a specific prior art design where two dies share a single ready/busy line. This specific prior art design may use for example, 4 dies placed in the same package, with 2 dies sharing one chip enable (CE) line and one ready-busy (RB) line. Hence, only when both dies in a package are ready does the shared ready-busy (RB) line become active. However, a special command must be used to check the readiness of a specific die within a package that uses a single ready-busy (RB) line to signal the status of multiple dies therein. Also, the current inventors note a prior art need for the host to issue the F1h command in state C to detect status, which appears to require the host to poll each chip before issuing another command. Accordingly, the current inventors believe that improvements to such prior art methods and apparatuses are desired.