In recent years, miniaturization of electronic components have been advanced rapidly as the electronics technology has been developed. In the field of the monolithic ceramic capacitor as well, demands for miniaturization and increases in capacity have intensified. Consequently, development of ceramic materials having high relative dielectric constants, reduction in thickness, and multilayering of dielectric ceramic layers have been advanced.
For example, Patent Document 1 proposes a dielectric ceramic represented by a general formula: {Ba1-x-yCaxReyO}mTiO2+αMgO+βMnO (where Re represents a rare earth element selected from the group consisting of Y, Gd, Tb, Dy, Ho, Er, and Yb and α, β, m, x, and y satisfy 0.001≦α≦0.05, 0.001≦β≦0.025, 1.000≦m≦1.035, 0.02≦x≦0.15, and 0.001≦y≦0.06, respectively).
Patent Document 1 discloses a monolithic ceramic capacitor including the above-described dielectric ceramic. The monolithic ceramic capacitor can have a thickness of 2 μm per ceramic layer, the total number of effective dielectric ceramic layers of 5, and a relative dielectric constant ∈r of 1,200 to 3,000 can be obtained.
The monolithic ceramic capacitor of Patent Document 1 takes advantage of a dielectric action of the ceramic in itself. On the other hand, research and development on semiconductor ceramic capacitors based on a principle different from this have also been conducted intensively.
For example, Patent Document 2 proposes a SrTiO3-based grain boundary insulation type semiconductor ceramic element assembly having an average grain size of crystal grains of 10 μm or less and a maximum grain size of 20 μm or less.
This grain boundary insulation type semiconductor ceramic is produced by firing (primary firing) a ceramic compact in a reducing atmosphere to convert it to a semiconductor and, thereafter, conducting firing (secondary firing (reoxidation)) in an oxidizing atmosphere to convert the crystal grain boundaries to insulators, so that a capacitance is acquired at the crystal grain boundaries.
Consequently, in Patent Document 2, a semiconductor ceramic element assembly is obtained, which is a semiconductor ceramic capacitor having a single-layered structure and which has an apparent relative dielectric constant ∈rAPP of 9,000 in the case where the average grain size of crystal grains is 8 μm.
In addition, Patent Document 3 proposes a method for manufacturing a grain boundary insulation type monolithic semiconductor ceramic capacitor including a firing step to fire a laminate composed of layers formed from a semiconductor ceramic material, in which a composition containing (Sr1-x-yCax-yYy)m(Ti1-zNbz)O3 as a primary component contains at least one type of secondary component selected from a V oxide, a Mo oxide, and a W oxide within the range of 0.1 to 0.5 percent by mole based on the molar ratio of the total amount of oxides to the primary component after firing basis, and nickel internal electrode layers, a reoxidation product addition step to add a reoxidation product to the laminate, and a step to reoxidize the laminate after the addition, wherein the above-described reoxidation step is conducted through a heat treatment in a nitrogen atmosphere under a predetermined reoxidation condition.
In Patent Document 3, a SrTiO3-based grain boundary insulation type monolithic semiconductor ceramic having a thickness of 3 μm per semiconductor ceramic layer and an outside dimension of 3.2 mm in length, 1.6 mm in width, and 1.2 mm in height is prototyped, and characteristics of a voltage value, at which 1 mA of current passes, that is, a varistor voltage V1mA, of 2.49 V to 3.06 V and an apparent relative dielectric constant ∈rAPP of 2,500 to 4,100 are obtained.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 11-302072
Patent Document 2: Japanese Patent No. 2689439
Patent Document 3: Japanese Unexamined Patent Application Publication No. 2005-86020