Patent Document 1 describes a method of manufacturing a multi-layer board (printed circuit board) so that a chip component is embedded in an insulating substrate (or base member). Here, multiple single-sided conductive pattern resin films made of thermoplastic resin are provided with via holes. The via holes are disposed in positions corresponding to the embedded chip component (or electrical element) to have dimensions approximately equal to an outer dimension of the chip component. Then the multiple resin films are piled, and the chip component is inserted into a concave space (or hole) formed by the via holes. A heating press is then applied to the piled films from both the surfaces. Thus, the individual resin films are deformed while being thermally fused and mutually bonded to thereby produce the insulating substrate, enabling the chip component to be embedded in the insulating substrate.
Patent Document 1: JP2003-86949 A (U.S. Pat. No. 6,680,441 B2)
Here, the multiple resin films having the via holes are piled to have the same height as that of the chip component. To insert the chip component to the concave space with a high yield ratio, the dimensions of the via holes are formed to have slightly larger dimensions in consideration of a deviation of the outer dimension of the chip component, a processing accuracy of the via holes, and a mounting position accuracy of the chip component. In this case, a clearance is formed between the chip component and the inside wall of the concave space with the chip component being not fixed. The chip component may therefore deviate from a preset position, enter into an interval space between the piled films, or jump up out of the concave space because of vibration during insertion of the chip component or during transfer to a next manufacturing step.