1. The Field of the Invention
This invention relates to a semiconductor device and a method for fabricating the same. More particularly, this invention relates to a method for fabricating a semiconductor device and a structure capable of contributing to the simplification of the process, minimizing a failure of the metal contact and reducing the contact resistance.
2. Description of the Related Art
A semiconductor memory device such as a DRAM device is divided into a memory cell array region, a core region, and a peripheral region.
The memory cell array region includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, i.e., memory elements arranged in an area intersected by the lines. The memory cells are driven by selection of the word lines and the bit lines.
The core and peripheral regions include a circuit area formed on the periphery of the memory cell array region for driving and controlling the memory cells. The core and peripheral regions have different elements such as diodes, resistors, and transistors for driving the memory cells. Mostly, conductive layers or transistors are used as the resistors. Conventionally, a polysilicon gate has been used for the resistor by way of a metal contact or a bit line contact. In an attempt to reduce the resistance of the gate, a polycide gate comprised of polysilicon and metal silicide is substituted for the polysilicon gate. But the polycide gate is not suitable for resistors because its use results in a low unit area resistance of the gate. Currently, polysilicon is used to form resistors.
In general, the conventional polysilicon resistors are formed together with plate nodes or storage nodes in a step of forming a capacitor of the cell region. Namely, the resistors are formed by deposition of a physical layer constituting the storage nodes, such as a polysilicon layer extending to the peripheral region as well as the cell region and then patterning of the deposited physical layer, when forming the nodes constituting the capacitor.
Such a method of forming a resistor together with a storage node is disclosed in U.S. Patent Publication No. 2003/0127705, entitled “Semiconductor memory device having resistor and method of fabricating the same”.
On the other hand, the general semiconductor device has a multi-layer interconnection structure so as to utilize the surface area of the integrated circuits more efficiently. In the multi-layer interconnection structure, active elements and interconnects are formed in integration with each other, and the individual layers are connected by way of interlayer connections such as contact plugs or studs. Meanwhile, landing pads are formed on the studs or the contact plugs so as to support the alignment of the contact plugs and to lower the contact resistance. The landing pads are generally larger in surface area than circuitries or metal lines A method for supporting alignment and reducing a contact resistance using landing pads is disclosed in U.S. Patent Publication No. 2003/0015732, which claims the priority from Korean Patent No. 10-0385960, entitled “Integrated circuits having self-aligned metal contact structure and method of fabricating the same.” With a growing trend towards higher integration, the distance between the patterns becomes small enough to easily cause a short with adjacent conductive patterns. Particularly, bit lines are sometimes used as local interconnects in the core region in which sense amplifiers are formed. In this region, the circuit patterns are arranged very densely, making it difficult to secure a distance from the patterns and causing an increase in the contact resistance even with the formation of a contact.
FIG. 1 is a cross-section showing that a contact for the self-aligned metal lines is formed in the core region, and FIG. 2 is a plan view showing the formation of the contact.
As illustrated in FIGS. 1 and 2, a gate oxide layer 3a and a gate electrode 3b covered by a gate capping layer 3c are formed on a first insulation layer 4 on a semiconductor substrate 10 in which a device isolation layer 2 is formed. On a second insulation layer 5 formed on the first insulation layer 4, there are formed metal lines 14a corresponding to the bit lines in the cell array region and a metal line capping layer 14b corresponding to the bit lines. The metal lines 14a corresponding to the bit lines are connected to the transistors, which are formed below the metal lines 14a, through contacts or studs 13.
A third insulation layer 16 is formed on the metal lines 14a corresponding to the bit lines, and a contact hole 18 to connect to the upper metal lines is formed. Here, the contact hole 18 is misaligned, in which case it extends below the metal lines 14a, which correspond to the bit lines, to cause damage to the lower structure. This is because the overlap margin in the core region disappears with a decrease in the design rules, causing a device failure. Such damage to the lower structure that causes a failure may occur when forming the contact hole of a larger size besides misalignment. In an attempt to solve this problem, the design rules in the core region are increased, in which case, unfortunately, the chip is increased in size to reduce the number of chips available on one wafer, resulting in an increase in the manufacturing costs.