1. Field of the Invention
The invention relates to a contact process, and more particularly to a fabrication method for a damascene bit line contact plug.
2. Description of the Related Art
The self-aligned contact (SAC) process is a manufacturing method used to fabricate semiconductor devices such trench type DRAM, stacked DRAM, and FLASH memory. The SAC process reduces chip size by shortening the separation between adjacent polysilicon gates. In a conventional SAC process, a sidewall spacer of the gate is used to define a lightly doped drain (LDD) structure, and is also used to extend the oxide region at the gate edge and thereby improve source/drain leakage prevention.
FIGS. 1A to 1G are cross-sections of a conventional SAC process. In FIG. 1A, a gate insulating layer 12 is formed on a P-type silicon substrate 10, and a plurality of gate structures 14 is formed on the gate insulating layer 12. Next, a plurality of N-type ion-doped regions 16 is formed in the substrate 10 and laterally adjacent to the gate structures 14, respectively. Each of the gate structures 14 is a stack of a polysilicon layer 18 and a silicon nitride cap layer 20.
In FIG. 1B, a nitride sidewall spacer 22 is formed on the sidewall of the gate structure 14, and an N-type ion-doped region 24 is then formed on the exposed N-type ion-doped region 16 using the gate structure 14 and the nitride sidewall spacer 22 as the mask. The N-type ion-doped region 24 serves as a source/drain region, and the remaining part of the N-type ion-doped region 16 serves as an LDD structure. Next, a barrier layer 26 of silicon nitride is deposited to cover the entire surface of the substrate 10.
In FIG. 1C, an inter-layer dielectric (ILD) 28 is deposited on the barrier layer 26 to fill the gap between adjacent gate structures 14. Then, in FIG. 1D, a chemical-mechanical polishing (CMP) process is performed to level off the surface of the ILD 28. Next, in FIG. 1E, using a patterned photoresist layer (not shown) as a mask, the ILD 28 positioned between adjacent gate structures 14 is etched with the barrier layer 26 as an etching stop layer, resulting in an opening 29. However, in practical operation, the silicon nitride cap layer 20 and the nitride sidewall spacer 22 are over-etched, thus the profile of the opening 29 is shown as the dotted line.
In FIG. 1F, the barrier layer 26 at the bottom of the opening 29 is removed to expose the N+-type ion-doped region 24 between adjacent gate structures 14 so as to complete a contact hole 30. Next, in FIG. 1G, using deposition, photolithography and etching, the contact hole 30 is filled with a conductive material to serve as a bit line contact plug 32. Subsequently, a gate contact process and a source contact process are performed thereon.
The above-described SAC process, however, has the following disadvantages.
Step height between the active area (AA) and the shallow trench isolation (STI) is problematic as it can cause misalignment during photolithography or CMP and can result in an excessively thick ILD layer 28 with inadequate flatness. Hence, the etched profile of the contact hole 30 is affected, and causes problems in the interconnection structure, such as a short circuit between bit line and wordline or a blind window in the bit line contact hole 30.
The etching selectivity from the ILD layer 28 to the SiN liner 26 is not large enough to provide etching stop capability during the formation of the bit line contact hole 30, and seams will likely form in the STI region causing junction leakage between the bit line contact plug 32 and the substrate 10.
The silicon nitride cap layer 20 must maintain a certain thickness during the SAC process, thus the thermal budget is increased, and electrical properties, such as Vt, Idsat, Ioff, suffer.
When the SAC process is applied to the manufacture of a device with reduced size, problems encountered during photolithography become more acute.
Finally, the materials used for the cap layer 20 and the spacer 22 are limited to SiN or SiON, which exacerbate leakage in the polysilicon layer 18.