Generally, electronic devices are manufactured in large volumes in a wafer of semiconductor material. The wafer is a very thin disc, having a substantially cylindrical shape with a radius of the bases of the cylinder, which define its (main) front and rear surfaces, far greater than a height thereof.
In order to manufacture the electronic devices, the wafer is subject to various chemical and physical processes known in the art.
In particular, the manufacturing of the electronic devices often involves the formation of trenches in the wafers, each of which comprises a groove (e.g., rectilinear one) that extends from the front surface of the wafer.
The trenches may be of insulating type for electrically insulating distinct electronic elements (e.g., resistors, transistors, etc.) comprised in a same electronic device one from another. In this case, the trenches are filled with one or more (electrically) insulating materials (e.g., a silicon oxide).
Moreover, the trenches may be of conducting type to form active regions of the electronic devices. For example, in the case of trench-type MOS transistors (Trench-MOS) the trenches are used to form gate regions of the MOS transistors. For this purpose, a layer of (electrically) insulating material (or more) is formed in the trenches, and a layer of (electrically) conductive material (or more) is formed over the layer of insulating material (in such a way to define the gate region insulated from the semiconductor material of the wafer). In the particular case of power devices (adapted to deliver relatively large amounts of energy, generically used to supply power to other electronic devices), the MOS transistor typically has a cellular structure with a plurality of elementary cells interconnected one to another. More specifically, a plurality of gate regions is formed in rectilinear trenches parallel one to another; a source region is formed between each pair of adjacent trenches, in such a way to be shared between two adjacent cells (whereas a common drain region is formed on the rear surface of the wafer). Subsequently, all the gate regions and all the source regions are electrically interconnected by means of common gate and source terminals, respectively, comprising corresponding metallization layers formed on the front surface.
The formation of (conductive) trenches in the wafer and the subsequent processes of filling them with insulating and conductive materials entail certain drawbacks. Indeed, during a manufacturing process of the electronic devices in the wafer, the trenches may warp up to deviate from the designed direction. This depends on a density and on an extent of the trenches with respect to the size of the wafer, and on the differences in chemical-physical properties of the materials of the layers formed in the trenches and their manufacturing conditions (used masks, process temperatures, etc.).
This event involves a substantial accentuation of a warping of the wafer, whose main surfaces deviate from corresponding ideal geometric planes. In other words, the wafer takes a warped shape, with the main surfaces that may exhibit curvatures along different directions. The warping of the wafer is irregular and asymmetrical, and it has the effect of reducing the efficiency of subsequent planarization operations of the wafer; for example, the warping of the wafer may create depressions sufficiently pronounced to be not completely leveled during the planarization operations. Furthermore, the wafer warping (at least the warping remaining after the planarization operations) makes the operations of forming upper layers on its front surface (e.g., metallization layers) more prone to imperfections and non-idealities. This might also form empty pockets at the interface between stacked upper layers able to undermine both electromagnetic and mechanical robustness of the electronic devices.