Small electronic devices are today used in a wide variety of applications and have become a ubiquitous part of modern society. These applications include computers, telephony, and home entertainment, among many others. One reason for the widespread use of these devices is that recent advances in technology have expanded their capabilities while at the same time lowering their cost. A key part of this advancing technology has been the development of semiconductor devices.
Semiconductors are materials that conduct electricity only under certain conditions, which often include the presence of a small electrical charge. This enables the manufacture of solid-state switches—those that have no moving parts. Other standard (and new) electrical devices can be created out of semiconductors as well. In addition to having no moving component parts that are subject to fatigue or other mechanical failure, solid state devices can be fabricated in extremely small sizes. Very small, even microscopic electrical components are now used to provide the multitude of switches and capacitors necessary for today's electronics applications.
The processes used to fabricate these tiny semiconductor devices are numerous, but the basic process may be described generally. A material, such as silicon, is produced for use as a base, or substrate, upon which various electrical components will be built. This material is then formed into an appropriate shape, usually a thin slice called a wafer. The pure silicon is then selectively treated with one or more materials called dopants, such as ionized boron or phosphorus. The introduction of these impurities begins the process of creating the desired semiconductive properties. Various structures may then be formed at or near one surface of the wafer to construct the desired components.
These surface structures may be formed by etching, whereby the surface is exposed to an etching agent. Or, more typically, the surface is selectively etched using a process known as photolithography. In photolithography, a material called photoresist, or simply resist, is deposited evenly over the wafer surface. The resist is then selectively treated with a light source directed though a patterned mask so that some portions of the resist are exposed to the light energy while others are not. The exposed portions are developed to be either strengthened or weakened, depending on the type of resist material used, so that the weaker portions can be washed away using a solvent that will not otherwise affect the wafer or any structures already formed on it. The resist that remains however, will prevent the etching of the wafer surface in the areas it covers when a stronger etching agent is used in subsequent etching steps. When the desired wafer etching has been accomplished, the remaining photoresist is removed using an appropriate solvent.
Materials such as metals, other conductors, and insulators are added to the wafer surface using any of a variety of deposition methods, for example, chemical vapor deposition (CVD) or sputtering. Additional ion implantation may also be performed. By selectively adding and removing these various materials, layer after layer of electrical components can be formed on the wafer surface (or on top of previously formed structures).
A single wafer is usually populated with a number of dice, or portions of the wafer that will eventually be used separately. Frequently, all of the dice on a single wafer are formed identically, but this is not necessarily the case. After the fabrication is complete (and often at various intermediate steps as well), the wafer is inspected so that defective regions can be marked for discard or repair. The dice are eventually separated and those passing inspection are packaged, that is encapsulated in a hard plastic material and provided with external leads connected to various internal locations. The encapsulated die that has been provided with a number of leads is often referred to as a chip.
During the fabrication process itself, groups of the electrical components on the wafer may be formed at more or less the same time. That is, whenever a certain material is deposited or selectively etched away, the material may be used for a variety of devices—even if they are not the same kind of component. Naturally this requires careful planning, but has the advantage of economy where it can be done successfully.
For example, in a high voltage mixed mode (HV-M.M) application, a semiconductor device having a capacitor structure disposed between an NMOS low-voltage (LV) gate and an NMOS high-voltage (HV) gate may be formed in this fashion, as illustrated in FIGS. 1A through 1F. FIGS. 1A through 1F are cross-sectional representations illustrating a semiconductor device 10 at various stages of a conventional fabrication process. Note that as used herein the term “semiconductor device” will sometimes be used to refer to one or more dice for use in chips as described above, and at other times to a discreet portion of such a die that is being described to illustrate a particular device or process.
The semiconductor device 10 illustrated in FIGS. 1A through 1F is fabricated beginning with a substrate 12, which has been selectively doped to create three separate regions. These regions, illustrated in FIG. 1A, are P-well 15, N-well 20, and P-well 25. These three regions are created in this way to support the three devices mentioned above (shown as formed in FIG. 1F). In accord with the definition provided above, the semiconductor device of FIG. 1 encompasses these three components and their related structures. The process continues with the formation of the field oxide structures 30, 31, 32, and 33. At the same time (or subsequently) an HV gate oxide 35 is formed over P-well 15 as illustrated by FIG. 1B. This may be done, for example, by using a TEOS (tetraethyl orthosilicate) chemical vapor deposition (CVD) process followed by selective wet etching. The process of etching away portions of a deposited layer produces a desirable pattern and is sometimes referred to as ‘patterning’.
A second gate oxide layer 40 is then formed, this time over the entire exposed surface of the semiconductor device, as shown in FIG. 1C. A conductive layer, for example of polysilicon, is then formed and selectively etched away to form the conductive structures 45, 46, and 47 shown in FIG. 1D. Structure 46 forms the bottom conductive layer of a capacitor, and structure 45 is a HV gate electrode and structure 47 is a LV gate electrode. For the capacitor, an interpoly oxide/high-temperature oxide 50 is then formed over conductive structure 46, as shown in FIG. 1E. Finally, a second conductive layer 55 is deposited and formed over interpoly oxide/high-temperature oxide layer 50 to form the top conductor of the capacitor. The configuration of the semiconductor device 10 at this stage is illustrated in FIG. 1F.
This conventional method has the disadvantage of frequently producing less than satisfactory HV gate oxide reliability. This is apparently due at least in part to boron diffusion from P-well 15 during the TEOS process, resulting in a relatively weaker gate oxide. Needed then is a process to create a semiconductor device substantially equivalent to the one illustrated in FIGS. 1A through 1F, but with higher HV gate reliability. The present invention provides just such a solution.