1. Field of the Invention
The present invention relates to a MOS-type solid-state imaging device to be used for various types of equipment, such as home video cameras, digital still cameras, or cameras incorporated in cellular phones.
2. Description of the Background Art
With reference to FIGS. 9 and 10, a conventional sensor and a scheme of driving the conventional sensor are described below. FIG. 9 is a circuit diagram of the conventional sensor. The sensor illustrated in FIG. 9 includes photosensitive cells (each surrounded by a dotted line) arranged in a 2×2 matrix. Each photosensitive cell includes a photodiode 51, a transfer gate 52, a floating diffusion layer section 53, an amplifier transistor 54, a reset transistor 55, and an address transistor 56. Also, each photosensitive cell corresponds to one pixel for forming an image. Note that, for the purpose of simplifying descriptions, it is assumed herein that the photosensitive cells are arranged in a 2×2 matrix. In practice, however, the photosensitive cells are arranged in a matrix with several tens to thousands of rows and columns. Also, in FIG. 9, the components included in the same photosensitive cell are provided with the same suffix (a through d) for identification.
The scheme of driving the sensor illustrated in FIG. 9 is described below. In order to extract signals from the photosensitive cells on the first row, the address registers 56a and 56b included in the first photosensitive cells on the first row are first controlled by a vertical shift register 61 to be in an ON state. Next, the reset transistors 55a and 55b are controlled also by the vertical shift register 61 to be in an ON state. With this, the floating diffusion layer sections 53a and 53b are reset. At this time, the amplifier transistor 54a and a load transistor 63p form a source follower circuit, producing an output on a vertical signal line 62p. Similarly, the amplifier transistor 54b and a load transistor 63q form a source follower circuit, producing an output on a vertical signal line 62q. Here, voltages appearing on the vertical signal lines 62p and 62q are noise voltages irrespectively of signal electric charges stored in the photodiodes 51a and 51b. Next, the transfer gates 52a and 52b are controlled by the vertical shift register 61 to be in an ON state. Thus, the signal electric charges stored in the photodiodes 51a and 51b are transferred to the floating diffusion layer sections 53a and 53b, causing signal voltages corresponding to the signal electric charges stored in the photodiodes 51a and 51b to appear on the vertical signal lines 62p and 62q. 
Clamp capacitors 64p and 64q, clamp transistors 65p and 65q, sample/hold transistors 66p and 66q, and sample/hold capacitors 67p and 67q form a noise suppression circuit. This noise suppression circuit finds a difference between a pixel output with a signal electric charge being applied to the floating diffusion layer section 53 (that is, a signal output) and a pixel output with a signal electric charge not being applied thereto (that is, a noise output). Noise occurring at the sensor illustrated in FIG. 9 mainly includes noise caused by variations in threshold voltage at the amplifier transistor 54 and kTC noise, which is thermal noise occurring at the reset transistor 55. When noise outputs appear on the vertical signal lines 62p and 62q, the clamp transistors 65p and 65q and the sample/hold transistors 66p and 66q are controlled by control terminals 74 and 75 to be in an ON state. Also at this time, the sample/hold capacitors 67p and 67q are applied with a noise-suppressed clamp voltage through a clamp-voltage supply terminal 73. After a predetermined time has elapsed, the clamp transistors 65p and 65q are controlled by the control terminal 74 to be in an OFF state.
Next, voltages each being equal to a sum of the noise-suppressed signal voltage and the noise voltage appear on the vertical signal lines 62p and 62q. With this, the noise voltages on the vertical signal lines 62p and 62q are each changed to the sum of the signal voltage and the noise voltage, and each amount of change corresponds to each noise-suppressed signal voltage. Accordingly, the voltages at the sample/hold side of the clamp capacitors 64p and 64q are also changed by the amount corresponding to the noise-suppressed signal voltage. In practice, the voltages applied to the sample/hold capacitors 67p and 67q are each changed from a noise-suppressed clamp voltage by the amount corresponding to a voltage obtained by dividing the amount of change in the signal voltage on a corresponding one of the vertical signal lines 62p and 62q by a corresponding one of the clamp capacitors and a corresponding one of the sample/hold capacitors. Therefore, the voltage applied to each of the sample/hold capacitors 67p and 67q is the sum of the noise-suppressed clamp voltage and the divided signal voltage, and noise has been suppressed. After the sample/hold transistors 66p and 66q are controlled to be in an OFF state, horizontal transistors 68p and 68q are sequentially and selectively controlled by a horizontal shift register 69 to be in an ON state. With this, signals corresponding to the signal electric charges stored in the photodiodes 51a and 51b are sequentially output from an output terminal 70.
Next, in order to extract signals from the photosensitive cells on the second row, an operation similar to that performed on those on the first row is performed on those on the second row. With this, signals corresponding to the signal electric charges stored in the photodiodes 51c and 51d are output from the output terminal 70.
The above-described operation is illustrated in a timing chart as in FIG. 10. In FIG. 10, a period during which signals stored in one row of the photodiodes 51 are eventually output from the output terminal is called a horizontal effective period, while a period during which signals are output from the photodiode 51 to the vertical signal line 62 for suppression of noise included in the output signals is called a horizontal blanking period. Furthermore, the horizontal blanking period and the horizontal effective period are collectively called a horizontal period. The horizontal period is a time period actually required for reading signals of one row. A time period required for reading signals from the entire sensor is called one frame period. As illustrated in FIG. 10, the amount of signal electric charge stored in the photodiode 51 depends on a time interval of a transfer pulse being applied to the transfer gate 52. Also, the time interval of the transfer pulse is constant during one frame period. Therefore, the sensitivity of the photodiode 51 is constant.
In the sensor illustrated in FIG. 9, each photosensitive cell is formed by four transistors (the transfer gate 52, the amplifier transistor 54, the reset transistor 55, and the address transistor 56). By contrast, in some sensors recently devised for achieving size reduction, each photosensitive cell is formed by three transistors. Such a newly devised sensor has a structure in which the address transistor 56 is omitted from the sensor illustrated in FIG. 9 and a power source is shared among the photosensitive cells. In order to allow signals to be read from this sensor, a pulse-type source voltage is required to be supplied to each photosensitive cell.
The scheme of driving the sensor as illustrated in FIG. 9 is disclosed in, for example, Japanese Patent Laid-Open Publication No. 9-247537 (1997-247537). As for a sensor in which photosensitive cells are each formed by three transistors, no documents describing a specific layout of these photosensitive cells are known.
In the above sensor as well as a semiconductor integrated circuit, the circuit layout is a key to determine the size of the circuit, as well as the circuit configuration and design rules. In general, as the circuit size is smaller, yields of the circuit are improved more, thereby reducing the cost of the circuit. Therefore, laying out a circuit according to predetermined design rules is an important technical task in designing the semiconductor integrated circuit. However, as for a sensor in which photosensitive cells are each formed by three transistors, no specific layout of these photosensitive cells has been clearly known to public.