1. Field of the Invention
The invention relates to a semiconductor device, and more specifically to a semiconductor device capable of reducing the variability of characteristics.
2. Description of the Related Art
In recent years, fine structuring of constituent elements in semiconductor devices has been pushed forward for the purpose of increasing packing densities of the semiconductor devices. With the fine structuring of the constituent elements, dimensional variations in processing lead to variations in characteristic from element to element, causing degradation of the performance of semiconductor devices.
For example, in non-volatile semiconductor memories, such as EEPROMs and the like, that have dual-gate (floating gate/control gate) cells, the capacitive coupling ratio between static capacitance C1 associated with a gate insulating layer between the semiconductor substrate and the floating gate electrode and static capacitance C2 associated with an insulating layer between the floating gate electrode and the control gate electrode (hereinafter referred to the intergate insulating layer), i.e., C2/(C1+C2), varies from cell to cell. This is a serious problem. Hereinafter, the capacitive coupling ratio is referred simply to as the coupling ratio.
With memory devices in which a cell isolating insulating layer is formed by means of LOCOS (localized oxidation of silicon), the shape (area) of the gate insulating layer (tunnel oxide layer) on the substrate surface is determined by a width of cell isolation, while the shape (area) of the intergate insulating layer is determined by the width, thickness or the like of the floating gate electrode. Thus, the shape (area) of the gate insulating layer and the shape (area) of the intergate insulating layer are each determined by a separate factor, increasing variations in coupling ratio from cell to cell.
Even with memory devices in which cell isolation is practiced by buried cell isolation, on the other hand, the shape (area) of the gate insulating layer and the shape (area) of the intergate insulating layer are each determined by a separate factor. Thus, the coupling ratio will vary greatly from cell to cell.
Thus, if the area of the gate insulating layer and the area of the intergate insulating layer vary from cell to cell, the electric field applied to the gate insulating layer varies when a voltage is applied to the control gate electrode. This will cause a tunnel current that flows at writing/erasing time to vary from cell to cell. As a result, the writing/erasing characteristic will vary from cell to cell, causing malfunctions.
To attain further micro-miniaturization of an element, a method has also been proposed which forms a floating gate electrode so as to protrude from the substrate surface and then forms an intergate insulating layer on the protruding surface. That is, a gate insulating layer is first formed on the bottom of a groove lying between cell isolation insulating layers and then the floating gate electrode is formed so as to bury the groove and protrude from the top of the isolation insulating layer. An intergate insulating layer is formed on the exposed portion of the floating gate electrode and the control gate electrode is formed on the intergate insulating layer.
To increase the coupling ratio, the area of the intergate insulating layer could be increased by increasing the sidewall length (the thickness of the portion above the groove) of the floating gate electrode. In this case, however, it would become difficult to control the height of the floating gate electrode (the thickness of the portion within the groove plus the thickness of the portion above the groove) and the length of overlap between the floating gate electrode and the cell isolation insulating layer. This would result in great variations in the sidewall length of the floating gate electrode from cell to cell. In this case as well, variations in the coupling ratio would increase and the writing/erasing characteristic would vary from cell to cell, causing malfunctions.
Further, if the intergate insulating layer were formed for the above-described memory cell structure by using a usual technique, the average thickness of those portions of the insulating layer which border the cell isolation insulating layer would become thinner than the average thickness of the intergate insulating layer, resulting in a further increase in variations in coupling ratio.
The reason why the boundaries of the intergate insulating layer become small in thickness is that it becomes difficult to introduce oxidant or deposition species serving to form the intergate insulating layer into the boundaries between the exposed surface of the floating gate electrode and the surface of the cell isolation insulating layer because the distance between adjacent floating gate electrodes becomes short due to fine grooves. Therefore, the thickness of the boundary portions of the intergate insulating layer becomes smaller remarkably as the sidewall length of the floating gate electrode becomes longer, resulting in a further increase in variations in coupling ratio.
The above-described problems will arise in other semiconductor devices. For example, with a so-called mesa-shaped MOS transistor in which the source/drain regions and the channel region are formed in a convex portion of a substrate, the channel width varies for the same reason as above, which causes the current drive characteristic to vary from transistor to transistor.
With a semiconductor device having so-called buried capacitors in which capacitive elements are formed within grooves formed in the substrate surface, the capacitor area will vary because control of the groove depth is difficult. This results in variations in capacitance from element to element.