Integrated circuits which utilize IGFET devices are generally rated on the basis of the electrical performance of the device. Such rating parameters include the frequency response, electrical breakdown characteristics and the economy of wafer surface area. All of these are dependent on the method of formation of the device in the wafer.
One feature which limits the frequency response and circuit density is the depth of the source/drain diffusions. In previous arrangements, second level conductor interconnects were made to these diffusions requiring that the diffusions be of sufficient depth to prevent puncture to the underlying doped silicon body. As the source/drain diffusion increased in depth in correspondingly increased in width thus increasing the surface area occupied by the transistor. Additionally, an increase in the size of the source/drain diffusions increased the interelectrode capacitances and produced a corresponding decrease in the maximum frequency of the device. In many prior arrangements, conductive first level conductor runs are placed in the doped silicon body which results in a relatively high first level conductor to substrate capacitance. Further, when metalized second level conductor runs are placed, there is a chance of puncture and possible shorting to the underlying doped silicon body at the point of connection between first and second level conductor runs. The instant disclosure eliminates these problems by providing improved isolation between the first level conductors and the substrate and between the first and second level conductors. Additionally, the photoshaping operation defining the second level conductors does not require critical mask alignment on the wafer as the prior arrangements.