This application claims priority upon Korean Patent Application No. 2001-00346, filed on Jan. 4, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to a nonvolatile semiconductor memory device. More specifically, the present invention is directed to a nonvolatile semiconductor memory device capable of changing a column address while inputting/outputting a data column to/from the memory device and method for controlling data input/output thereof.
A rewritable nonvolatile semiconductor memory device, such as, a NAND-type flash memory device, has an array of strings formed from a plurality of memory cells that are serially connected between a string selection transistor and a ground selection transistor. In a writing (or programming) operation of the NAND-type flash memory device, as shown in FIG. 15, when signal of a data input command, successive column and row addresses for assigning memory cells are inputted. And, specific-unit data is synchronized with a successive low-to-high transition of a write enable signal {overscore (WE)}, as a data input signal, and is successively inputted through input/output pins I/Oi (i=0-7). The inputted data is temporarily stored in latches of a register or a page buffer circuit. Thereafter, the temporarily stored data is programmed. In a read operation of the NAND-type flash memory device, as shown in FIG. 16, upon a read command, successive column and row addresses for assigning memory are inputted. And then, data of the assigned column and row addresses is read or sensed during a low interval of an R/{overscore (B)} signal. The sensed data is temporarily stored in latches of a register or a page buffer circuit that is located in the memory device. Finally, specific-unit data stored in the register is synchronized with a successive high-to-low transition of a read enable signal {overscore (RE)}, as a data output signal, and is successively outputted through the input/output pins I/Oi (i=0-7).
In the NAND-type flash memory device, the specific-unit is conventionally called xe2x80x9cpagexe2x80x9d. The NAND-type flash memory device can be applied to a solid-state file storage, a digital voice recorder, a digital still camera or a portable system that needs nonvolatility. The NAND-type flash memory device can operate reading and programming operations at higher speed by expanding the number of memory cells to be sensed/programmed at the same time or expanding a page size to improve reading or programming speed per 1-byte.
FIG. 17 schematically illustrates a flash memory system, which includes a host 10, a memory controller 20, and an NAND-type flash memory device 30. The memory controller 20 includes a control unit 22 and a buffer memory 24. The buffer memory comprises a first data storage area (A) having 2 KB storage capacity and a second data storage area (B) having 64 B storage capacity. The NAND-type flash memory device 30 is controlled by a memory controller 20, and includes a memory cell array and a page buffer circuit 36 or a register. The memory cell array is divided into a main field array 32 and a spare field array 34. Normal data is stored in the main field array 32, while additional data information associated with the normal data is stored in the spare field array 34. The additional data information includes error correction and detection code (ECC) data, address mapping data, and wear levelling data. If a page size of the NAND-type flash memory device is xe2x80x9c2 KB+64 Bxe2x80x9d, memory cells corresponding to 64 B occupy one page of the spare field array 34. The use of wear levelling data is described in U.S. Pat. No. 5,568,423 entitled xe2x80x9cFLASH MEMORY WEAR LEVELLING SYSTEM PROVIDING IMMEDIATE DIRECT ACCESS TO MICROPROCESSORxe2x80x9d.
For example, when a size of a page being a specific-unit of a writing or reading operation in a memory device is xe2x80x9c2 KB+64 Bxe2x80x9d, 2 KB is allocated to store normal data, and 64 B is allocated to additional data. If a writing operation of the flash memory device is performed in the memory system shown in FIG. 17, the host 10 sequentially transmits normal data of 2 KB to the memory controller 20 with a unit of 512 B. The memory controller 20 temporarily stores the transmitted normal data of 2 KB in the first data storage area (A) of the buffer memory 24. A control unit 22 of the memory controller 20 generates additional data of 64 B, in which the additional data has error correction and detection code data, address mapping data, and wear levelling data by using the stored normal data of 2 KB in the first data storage area (A). Also, the control unit 22 temporarily stores the generated additional data in the second data storage area (B) of the buffer memory 24.
The memory controller 20 sequentially transfers normal data of 2 KB to the memory device, based upon an input/output structure of an NAND-type flash memory device. The NAND-type flash memory device 30 temporarily stores the sequentially transferred normal data of 2 KB in a page buffer area of 2 KB corresponding to the main field array 32. Thereafter, the memory controller 20 sequentially transfers additional data of 64 KB to the memory device, based upon the input/output structure of the NAND-type flash memory device. The NAND-type flash memory device 30 temporarily stores the sequentially transferred additional data of 64 B in a gate buffer area of 64 B corresponding to the spare field array 34. After completely inputting the xe2x80x9c2 KB+64 Bxe2x80x9d data, the data stored in the page buffer 36 or the register based upon the input of a program instruction is programmed at the same time.
FIG. 18 schematically illustrates another memory system having a flash memory device. in the system of FIG. 18, a memory controller 20 has a buffer memory 24xe2x80x2 that is smaller than a page size of a NAND-type flash memory device 30xe2x80x2. The buffer memory 24xe2x80x2 includes of a first data storage area (Axe2x80x2) of 512 B for storing normal data and a second data storage area (Bxe2x80x2) of 16 B for storing additional data. The NAND-type flash memory device 30xe2x80x2 has the same page size ofxe2x80x9c2 KB+64 Bxe2x80x9d as that shown in FIG. 17, and is controlled by a memory controller 20xe2x80x2. When a NAND-type flash memory device having a page size larger than a buffer memory 24xe2x80x2 of the memory controller 20xe2x80x2 is applied to the system, the following problem occurs.
If a writing operation of a flash memory device is performed in a memory system as shown in FIG. 18, a host 10xe2x80x2 transfers normal data of 512 B to a memory controller 20xe2x80x2. The memory controller 20xe2x80x2 temporarily stores the transferred normal data of 512 B in a first data storage area (Axe2x80x2) of a buffer memory 24xe2x80x2. By using the stored normal data of 512 B, a control unit 22xe2x80x2 of the memory controller 20xe2x80x2 generates additional data of 16 B that includes error correction and detection code data, address mapping data, and wear leveling data. Also, the control unit 22xe2x80x2 temporarily stores the generated additional data in a second data storage area (Bxe2x80x2) of the buffer memory 24xe2x80x2.
The memory controller 20xe2x80x2 sequentially transfers normal data of 512 B to a NAND-type flash memory device, based upon an input/output structure of the memory device. The NAND-type flash memory device 30xe2x80x2 temporarily stores the sequentially transferred normal data of 512 B in a page buffer circuit 36xe2x80x2 and a register. Thereafter, the memory controller 20xe2x80x2 sequentially transfers additional data of 16 B to the NAND-type flash memory device, based upon an input/output structure of the memory device. The NAND-type flash memory device 30xe2x80x2 temporarily stores the sequentially transferred additional data of 16 B to the page buffer circuit 36xe2x80x2 or the register. Since a page size of the NAND-type flash memory device 30xe2x80x2 is xe2x80x9c2 KB+64 Bxe2x80x9d, the additional data of 16 B is not allocated to a page buffer area of 64 B corresponding to the spare filed array 34xe2x80x2 of the NAND-type flash memory device 30xe2x80x2, but is successively allocated to the page buffer area of 2 KB corresponding to a main field array 32xe2x80x2, That is, as shown in FIG. 18, the additional data of 16 B is stored with the normal data of 512 B in the page buffer area of 2 KB.
Therefore, there is a need for a nonvolatile semiconductor memory device that is able to achieve high-speed reading and writing operations, and a data input/output control method thereof.
There is also a need for a nonvolatile semiconductor memory device that is able to change a column address during data input/output, and a data input/output control method thereof.
There is a further need for a nonvolatile semiconductor memory device that is able to freely expand a page size irrespective of a buffer memory size of a memory interface, and a data input/output control method thereof.
An object of the present invention is, therefore, to provide a nonvolatile semiconductor memory device capable of achieving high-speed read and write operations, and a method for controlling data input/output thereof
Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of changing a column address during data input/output, and a method for controlling data input/output thereof.
A further object of the present invention is to provide a nonvolatile semiconductor memory device capable of freely expanding a page size irrespective of a buffer memory size of a memory interface, and a method for controlling data input/output thereof.
The foregoing and other objects of the present invention will be achieved by providing a novel and improved nonvolatile semiconductor memory device including a memory and a memory controller, in which the memory includes memory cell arrays arranged in a matrix of rows and columns, and a plurality of latch groups temporarily storing data to be stored/read in/from the array.
In a preferred embodiment, the nonvolatile semiconductor memory device further comprises an address buffer circuit for receiving and storing external addresses data from a first input/output pins; a column address register for receiving the external address stored in the address buffer circuit as a column address, and sequentially increasing the column address; a selection circuit for selecting of a latch group of the plurality of latch groups in response to the column address sequentially outputted from the column address register; a data input/output circuit for transferring data inputted through a second input/output pins to the selected latch group by being synchronized with a data input signal provided from the memory controller, and transferring the data stored in the selected latch group to the second input/output pins by being synchronized with a data output signal provided from the memory controller; and a controller for controlling the address buffer circuit and column address register to store the external address in the column address register when the external addresses are applied to the first input/output pins while the data is transferred from the selected latch group to the second input/output pins or vice versa.
In one preferred embodiment, a flash memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in a matrix of rows and columns, and a memory controller, in which the memory cell array comprises a main field array and a spare field array. The flash memory device further comprises a plurality of latch groups for temporarily storing data to be stored/read in/from the memory cell array; an address buffer circuit for storing external addresses provided from a first input/output pins; a column address register for receiving and storing an address of the external addresses stored in the address buffer circuit as a column address, and for sequentially increasing the column address; a selection circuit for sequentially selecting a latch group of the plurality of latch groups in response to the column address outputted from the column address register; a data input/output circuit for transferring data sequentially inputted from a second input/output pins to the selected latch group by being synchronized with a data input signal provided from the memory controller, and for transferring the data from the selected latch group to the second input/output pins by being synchronized with a data output signal provided from the memory controller; a command register for generating a flag signal indicating column address change in response to a column-address change command; a short pulse generation circuit for generating a short pulse signal in response to the flag signal; an address input period setting circuit for enabling an address input period signal indicating a predetermined address input period in response to the short pulse signal; and a control logic for controlling the address buffer circuit and the column address register in response to the activation of the address input period signal so that the external address provided to the first input/output pins is stored in the column address register. In the embodiment, the data comprises normal data bits to be stored in the main field array and additional data bits, associated with the normal data bits, to be stored in the spare field array.
In another preferred embodiment, a system includes a memory controller that receives normal data from a host to internally generate additional data associated with the normal data, and has a buffer memory for temporarily storing the normal data and the additional data; and a flash memory device that is coupled to the memory controller, and stores a data comprising the normal data and the additional data.
In other preferred embodiment, a method for controlling data input/output of a nonvolatile semiconductor memory device according to one of the preferred embodiments of the present invention, comprises the steps of: (a) sequentially selecting a latch group of the plurality of latch groups in response to a column address outputted from the column address register; (b) transferring the data to the selected latch group by being synchronized with a data input signal provided from the memory controller; (c) storing an external address in the column address register as a new column address when the external addresses are applied to the memory device while the data is transferred/outputted to/from the selected latch group; and (d) performing the step of (b) according to the new column address.
Additional advantages of the present invention will become readily apparent from the following discussion, particularly when taken with the accompanying drawings.