Flip-chip technology is well known in the art. A semi-conductor chip having solder bumps formed on the active side of the semi-conductor chip is inverted and bonded to a substrate through the solder bumps by reflowing the solder. Structural solder joints are formed between the semi-conductor chip and the substrate to form the mechanical and electrical connections between the chip and substrate. A narrow gap is left between the semi-conductor chip and the substrate.
One obstacle to flip-chip technology when applied to polymer printed circuits is the unacceptably poor reliability of the solder joints due to the mismatch of the coefficients of thermal expansion between the chip, having a coefficient of thermal expansion of about 3 ppm/.degree. C., and the polymer substrate, e.g. epoxy-glass having a coefficient of thermal expansion of about 16 to 26 ppm/.degree. C., which causes stress build up in the solder joints. Because the structural solder joints are small, they are thus subject to failures. In the past, the solder joint integrity of flip-chip interconnects to a substrate has been enhanced by underfilling the volume between the chip and the substrate with an underfill encapsulant material comprised of a suitable polymer. The underfill material is typically dispensed around two adjacent sides of the semiconductor chip, then the underfill material slowly flows by capillary action to fill the gap between the chip and the substrate. The underfill material is then hardened by baking for an extended period. For the underfill encapsulant to be effective, it is important that it adhere well to the chip and the substrate to improve the solder joint integrity. Underfilling the chip with a subsequently cured encapsulant has been shown to reduce solder joint cracking caused by thermal expansion mismatch between the chip and the substrate. The cured encapsulant reduces the stresses, induced by differential expansion and contraction, on the solder joints.
The underfill process, however, makes the assembly of encapsulated flip-chip printed wire boards (PWB) a time consuming, labor intensive and expensive process with a number of uncertainties. To join the integrated circuit to the substrate, a flux, generally a no-clean, low residue flux, is placed on the chip or substrate. Then the integrated circuit is placed on the substrate. The assembly is subjected to a solder reflowing thermal cycle, soldering the chip to the substrate. The surface tension of the solder aids to self align the chip to the substrate terminals. After reflow, due to the close proximity of the chip to the substrate, removing flux residues from under the chip is such a difficult operation that it is generally not done. Therefore the flux residues are generally left in the space between the chip and the substrate. These residues are known to reduce the reliability and integrity of the encapsulant.
After reflow, underfill encapsulation of the chip generally follows. In the prior art, the polymers of choice for the underfill encapsulation have been epoxies, the coefficient of thermal expansion and moduli of the epoxies being adjusted with the addition of inorganic fillers. To achieve optimum reliability, a coefficient of thermal expansion in the vicinity of 25 ppm/.degree. C. is preferred and a modulus of 4 GPa or more. Since the preferred epoxies have coefficient of thermal expansions exceeding 80 ppm/.degree. C. and moduli of less than 4 GPa, the inorganic fillers selected generally have much lower coefficient of thermal expansions and much higher moduli so that in the aggregate, the epoxy-inorganic mixture is within the desired range.
The underfill encapsulation technique of the prior art has four principal disadvantages:
1. The reflowing of the solder bump and then underfilling and curing the encapsulant is a multi-step process that results in reduced production efficiency; PA1 2. To underfill a flip-chip assembly takes too long because the material must flow through the tiny gap between the chip and the substrate; PA1 3. The flux residues remaining in the gap reduce the adhesive and cohesive strengths of the underfill encapsulating adhesive, affecting the reliability of the assembly; and PA1 4. As the size of chips increase, the limiting effect of capillary action becomes more critical and makes the encapsulation procedure more time consuming, more susceptible to void formation and to the separation of the polymer from the fillers during application.
Clearly, many improvements to this process are feasible to increase reliability, reduce the time required and decrease the likelihood of producing a void in the encapsulant while providing the required low coefficient of thermal expansion and high modulus.
Other prior art methods of encapsulating the chip have attempted to overcome the above limitations by applying the encapsulating resin through a hole in the substrate located near the center of the chip. After the soldering and cleaning operations, the encapsulating resin is forced through the hole and around the periphery of the chip to ensure complete coverage of the chip surface. This method suffers from the need to reserve an area in the center of the substrate that is free of circuitry in order to provide an unused space for the hole. It also does not eliminate the problems of entrapped air bubbles.
Another prior art method in U.S. Pat. No. 5,128,746 (Pennisi) teaches a method wherein an adhesive material including a fluxing agent is applied to the chip or substrate. The chip is positioned on the substrate and the solder bumps are reflowed. During the reflow step, the fluxing agent promotes wetting of the solder to the substrate metallization pattern and the adhesive material is cured, mechanically interconnecting and encapsulating the substrate to the component. The limitation of this technique is that in order for the molten solder to readily wet the substrate metallization and also to allow the solder, through surface tension, to self-align the chip bumps to the substrate metallization pattern, the material must maintain very low viscosity during the reflow step. But the viscosity of these materials is severely increased by the presence of the required inorganic fillers. As a result, this approach has failed to produce a material that can serve as both the flux and the encapsulant with the required low coefficient of thermal expansion and high modulus for optimum reliability.
Referring to FIGS. 1 and 2, underfilling the chip 100 with a subsequently hardened encapsulant 102 has been shown to reduce solder joint cracking caused by thermal expansion mismatch between the chip and the substrate 104. The hardened encapsulant 102 transfers the stresses, induced by differential expansion and contraction, from the solder joints 106 to deformation of the chip 100 and substrate 104 as shown in FIG. 1 for expansion-induced strain at elevated temperatures and FIG. 2 for contraction-induced strain at reduced temperatures. In other words, the main effect of the hardened encapsulant during thermal expansion or contraction is to effectively force the chip and the substrate to take up the stress caused by the coefficients of thermal expansion mismatch by bending and bulging the chip and substrate. This bending and bulging reduces the stress on the solder joints and virtually eliminates solder fatigue failure.
Unfortunately, the effect of the encapsulant bending the substrate and the chip causes its own new set of problems. One such problem is that the bending makes the chips susceptible to cracking. Another such problem is that the degree of stress relief is highly dependent on the flexibility of the under-lying substrate and is thus an unpredictable function of the design of the printed circuit. Another limitation is that relying on such bending for stress relief on the solder joints prevents the placement of flip chips directly opposite one another on a double-sided printed circuit.
Another limitation of prior art flip-chip attachment is the difficulty of performing rework. Chip removal, once underfill has been performed, is very destructive to both the printed circuit board and the chip. Rework is almost impossible with prior art materials and processes. For example, the prior art procedure for removing an encapsulated die from a printed wire board is to grind it off manually.
Another limitation of the prior art is the expense of applying solder bumps to a chip. The solder bumps have been applied to chips by one of several methods. Coating the solder on the chip bumps by evaporation of solder metals through a mask is one such method. This method suffers from 1) long deposition times, 2) limitations on the compositions of solder that can be applied to those metals that can be readily evaporated, and 3) evaporating the metals over large areas where the solder is ultimately not wanted. Also, since most solders contain lead, a toxic metal, evaporation involves removal and disposal of excess coated lead from equipment and masks. Another common method in the prior art is electroplating of the solder onto the chip pads through a temporary sacrificial mask. Electroplating is a slow and expensive process that also deposits the solder over large areas where the solder is ultimately not wanted. Another method is to screen print solder paste on the chips pad through a stencil, then reflowing the solder to form a ball or bump on the pad. This technique is limited to bump dimensions that can be readily stencil printed, so it is not practical in bump pitches of 25 microns or less.
Another limitation of the prior art is the difficulty in distributing electrical signals from the small dimension of the chip to the large dimensions of the substrates. Most chips are manufactured with the electrical interconnection pads around their periphery with a pad pitch of 0.25 mm or less. On the other hand, printed circuits are manufactured with pad pitches of 0.25 mm and larger. This discrepancy in dimensions requires that the chip-to-substrate interconnection provide some method of redistributing the chip pad locations over a larger area so that they can match the dimensions of the printed circuit. Today, this discrepancy is bridged by creating expensive redistribution layers on the printed circuit. Few manufacturers are able to produce printed circuits at the tight dimensional tolerances required for redistribution, but those who are capable of doing so achieve this with significant production yield penalties. Another method to bridge the dimension discrepancy involves complete redesign of the chip to redistribute the electrical pads over the entire area of the chip, an expensive procedure that chip manufacturers generally want to avoid.