Conventionally, in order to inspect an electric function and performance of a semiconductor integrated circuit device formed on a wafer, probe pins are contacted to electrodes or solder bumps of a semiconductor chip. Each probe pin is electrically connected to an inspection apparatus main unit via a probe card for guiding wirings.
It is intended to realize a high operation speed, a low power consumption and a high performance for a semiconductor chip including a microprocessor and a memory. A semiconductor chip capable of high speed operation, particularly at an operation frequency reaching a GHz band, is formed with solder bumps (micro solder bumps) at a narrow gap. As the bumps are formed at a narrow pitch, it becomes necessary to narrow a gap of probe pins. For example, by adopting a buildup method, it becomes possible to form fine wiring layers in a partial area of a printed board, and dispose probe pins at a high density on the uppermost layer surface (refer to Japanese Laid-open Patent Publications Nos. 2000-304770 and 2004-69692).
It is preferable to inspect a semiconductor chip in a configuration close to a configuration in which the chip is fabricated on a package substrate. In order to make the configuration during inspection close to the configuration during fabrication, terminating resistors, decoupling capacitors, inductors and the like are fabricated on a probe card. In a probe card for a semiconductor chip having bumps at a narrow pitch, decoupling capacitors for suppressing noises are fabricated in a peripheral area of the probe card or on a bottom surface opposite to a surface facing the semiconductor chip (refer to Japanese Laid-open Patent Publications Nos. 10-132855 and 2004-233155).