The present invention is related to a semiconductor device, a method for manufacturing the semiconductor device, and a method for packaging the semiconductor device.
In consumer electronics, multifunctional electronic devices have become popular. For integrating chips of various functions on a circuit board of a multifunctional electronic device, a three-dimensional integrated circuit (3D IC) structure may be implemented.
In a 3D IC structure, chips may be stacked vertically and may be interconnected through leads and metal lines. The metal lines may undesirably complicate and/or enlarge the circuit board. For simplifying and/or minimizing a 3D IC structure, wafer-level copper-copper (Cu—Cu) bonding may be implemented.
FIG. 2 shows a flowchart that illustrates a wafer-level Cu—Cu bonding process. FIG. 3 shows a schematic cross-sectional view that illustrates a portion of a first wafer 10 and a portion of a second wafer 20 involved in the wafer-level Cu—Cu bonding process. Referring to FIG. 2, the process may include preparing two substrates, including a first substrate and a second substrate. For each of the wafers, the process may further include the following steps: forming an interlayer dielectric layer on the substrate, forming a mask on the interlayer dielectric layer, using the mask for patterning the interlayer dielectric layer to form a recess, forming a barrier layer and a seed layer in the recess (through deposition), forming a copper (Cu) member in the recess through electroplating (ECP), planarizing the Cu member through chemical-mechanical polishing/planarization (CMP) to form a Cu pad, and cleaning the wafer that includes the Cu pad.
As a result, the first wafer 10 and the second wafer 20 illustrated in FIG. 3 may be formed. Each of the first wafer 10 and the second wafer 20 may include an interlayer dielectric layer and a Cu pad embedded in the interlayer dielectric layer. For example, the second wafer 20 may include an interlayer dielectric layer 101 and a Cu pad 102 embedded in the interlayer dielectric layer 101. Each wafer may further include other Cu pads that are analogous to the Cu pad 102.
The wafer-level Cu—Cu bonding process may further include combining the Cu pads of the wafer 101 and the Cu pads of the wafer 102 through low-temperature thermocompression bonding. The process may further include performing annealing on the combined structure.
Given that spaces between Cu pads may be substantially small and that Cu has substantial ductility, as illustrated in FIG. 1B, unwanted connections may be formed as a result of the thermocompression bonding. FIG. 1B shows a diagram that illustrates a cross-section of a portion of a wafer combination involving face-to-face stacking of two wafers. In the wafer combination illustrated in FIG. 1B, unwanted connections may be formed as a result of combining Cu pads through thermocompression bonding. As a result, undesirable short circuits may occur in semiconductor devices that are manufactured using the wafer combination, such that the semiconductor devices may be defective.
FIG. 1A shows a diagram that illustrates a cross-section of a portion of a wafer combination involving face-to-face stacking of two wafers. The wafer combination illustrated in FIG. 1A may have substantially no unwanted short circuits. Nevertheless, a result of combining Cu pads through thermocompression bonding, defects may be formed in Cu pads of the wafer combination illustrated in FIG. 1A. As a result, reliability of semiconductor devices manufactured using the wafer combination may be unsatisfactory.