1. Field of the Invention
The present invention relates generally to a method of forming semiconductor devices and more specifically to a method of forming a nonvolatile memory device.
2. Background of the Invention
Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose the entire data stored in their memory cells when the power supply is cut. Meanwhile, nonvolatile memory devices sustain data stored in their memory cells even if the power is cut. For example, DRAM and SRAM are types of volatile memory devices, and flash memory device is a type of non-volatile memory device.
The flash memory device can electrically erase and remove data. A stack gate type of flash memory device makes it possible for highly integrated semiconductor devices. The stack gate type flash memory device comprises a tunnel insulation layer, a floating gate electrode, a control gate insulation layer, and a control gate electrode.
Meanwhile, as semiconductor devices become more highly integrated in a chip, there is an increasing need for lower operation voltages and smaller line widths. Accordingly, the coupling ratio of the flash memory device becomes an issue. The coupling ratio is a ratio of induced voltage of the floating gate electrode to operation voltage supplied to the control gate electrode. That is, as the coupling ratio increases, the voltage that is induced to the floating gate electrode by the operation voltage applied to the control gate electrode also increases. As a result, the operational voltage of the flash memory device can be decreased. The coupling ratio can be raised by increasing the capacitance between the floating gate electrode and the control gate electrode. Consequently, methods have been proposed to broaden an area of the floating gate electrode so as to raise the capacitance between it and the control gate electrode.
FIGS. 1-3 are cross-sectional views showing steps of forming a traditional nonvolatile memory device.
Referring to FIG. 1, a buffer oxide layer, a first floating gate conductive layer, and a first hard mask layer, which are not shown in the drawing, are sequentially formed on a semiconductor substrate 1. The first hard mask layer, the first floating gate conductive layer, and the buffer oxide layer are successively patterned to expose a predetermined region of the semiconductor substrate 1, thereby forming a buffer oxide pattern 2, a first floating gate pattern 3, and a first hard mask pattern 4 that are sequentially stacked. The buffer oxide pattern 2 is formed of thermal oxide and the first floating gate pattern 3 is formed of doped polysilicon. Additionally, the first hard mask pattern 4 is formed of silicon nitride. Using the first hard mask pattern 4 as an etch mask, the exposed semiconductor substrate 1 is selectively etched to form a trench 5 having a predetermined depth from the top of the semiconductor substrate.
Referring to FIG. 2, a device isolation insulating layer (not shown) is formed on the surface of the semiconductor substrate 1 to fill in the trench 5. Then, the device isolation insulating layer is planarized until the first hard mask pattern 4 is exposed. This forms a device isolation layer 6 within the trench 5. Next, the exposed first hard mask pattern 4 is etched until the first floating gate pattern 3 is exposed. A second floating gate conductive layer 7 and a second hard mask layer 8 are sequentially formed on the surface of the semiconductor substrate 1 with the exposed first floating gate pattern 3. The second floating gate conductive layer 7 is formed of doped polysilicon and the second hard mask layer 8 is formed of silicon oxide. A photoresist pattern 9 is then formed on the second hard mask layer 8. The photoresist pattern 9 is formed over the first floating gate pattern 3.
Referring to FIG. 3, using the photoresist pattern 9 as a mask, the second hard mask layer 8 is etched to expose the second floating gate conductive layer 7, thereby forming a second hard mask pattern 8a. The photoresist pattern 9 is removed and spacers 10 are formed on both sidewalls of the second hard mask pattern 8a. The spacers are formed of silicon nitride. Using the second hard mask pattern 8a and the spacers 10 as a mask, the second floating gate conductive layer 7 is etched to expose the device isolation layer 6, thereby forming a second floating gate pattern 7a. 
According to the above method, the area of the second floating gate pattern 7a is widened by the spacers 10. That is, the surface area of the second floating gate pattern 7a increases by the width of the bottom areas of the spacers 10. However, in region “a” the second floating gate conductive layer 7 may not get completely etched because of the tight dimensions in region “a.” This in turn leaves a bridge between the adjacent second floating gate patterns 7a. This bridge may be even more prominent with higher device integration because of even tighter dimensions in region “a.”