Power consumption is important in conventional double data rate data buffer circuit designs and registered clock driver circuit designs. Power reduction is a challenge for receiver circuits as synchronization signal frequencies go above 2.2 gigahertz (GHz) to 3.2 GHz and higher. The synchronization signals commonly lag behind corresponding data signals due to clock trees in the receiver circuits.
Conventional circuitry that delays the data signals to account for the synchronization signal lag often consumes significant power. Common fold buffer and differential-to-single-end latch designs are power consuming designs. Furthermore, an equalizer frequency performance is often affected by decision feedback equalizer circuitry.
It would be desirable to implement a low power delay buffer between an equalizer and a high sensitivity slicer