This application is related to CMOS imaging sensors.
Background: CMOS Imagers
For the past 20 years or so, the field of optical sensing has been dominated by the charged couple device ("CCD"). However, CCD sensors have a number of problems associated with their manufacture and use. CCD imagers require a special manufacturing process which is incompatible with standard CMOS processing. Thus CCD imagers cannot be integrated with other chips that provide necessary support functions, but require independent support chips to perform, for example, CCD control, A/D conversion, and signal processing. The operation of a CCD imager also requires multiple high voltage supplies varying from, e.g. 5V to 12V. The higher voltages produce higher power consumption for CCD devices. Consequently, costs for both the CCD image sensor and ultimately the system employing the sensor, remain high.
The recent advances in CMOS technology have opened the possibility of imagers offering significant improvements in functionality, power, and cost of, for example, digital video and still cameras. Advances in chip manufacturing processes and reductions in supply voltages have encouraged revisitation of CMOS technology for use in image sensors. The advent of submicron CMOS technology allows pixels which contain several FETs, and are circuits in their own right, to be comparable in size to those existing on commercial CCD imagers. Fabrication on standard CMOS process lines permits these imagers to be fully integrated with digital circuitry to create single-chip camera systems. A CMOS area array sensor (or CMOS imager) can be fabricated with other system functions, e.g. controller, A/D, signal processor, and DSP. Hence, the cost of the CMOS process is more economical than that of the CCD process. CMOS imagers can operate with a single low supply voltage, e.g. 3.3V or 5V. This provides lower power consumption than CCD imagers.
Background: Fixed Pattern Noise
One significant disadvantage with CMOS imagers has previously limited their widespread application--Fixed Pattern Noise ("FPN"). FPN is a built-in characteristic of X-Y addressable devices and is particularly an issue with any sort of CMOS imaging chips. FPN is noise that appears in a fixed pattern because the noise level is related to the position of the pixel in the array, the geometry of the column bus, and the proximity of other noise sources. (In addition, there is purely random noise not correlated to the pixel position, but due to inherent characteristics of the detector.) The effect of FPN is like viewing a scene through a window made of photo negatives. FPN occurs when process limitations produce device mismatches and/or non-uniformities of the sensor during fabrication on a wafer. FPN consists of both pixel FPN and column FPN. Each pixel circuit comprises at least a photodiode and a sensing transistor (operating as source-follower) as shown in FIG. 3. Mismatches of the sensing transistor between pixels may produce different output levels for a given input optical signal. The variations of these output levels is called pixel FPN. Additionally, each column (or row) has separate read circuitry. Driver mismatches between different columns (or rows) produce column FPN. Most device mismatches are caused by threshold voltage (V.sub.T) mismatches among CMOS transistors across the wafer.
A conventional solution for FPN suppression is to use a memory block to store the signal data for a whole frame and to subtract the FPN by sampling a reset voltage for the whole frame. The subtraction is done on a frame-by-frame basis which results in very slow frame rates.
Background: Correlated Double Sampling
Correlated Double Sampling ("CDS") plays an important role in removing several kinds of noise in high-performance imaging systems. Basically, two samples of the sensor output are taken. First, a reference sample is taken that includes background noise and noise derived from a device mismatch. A second sample is taken of the background noise, device mismatch, and the data signal. Subtracting the two samples removes any noise which is common (or correlated) to both, leaving only the data signal. CDS is discussed in greater detail in the following paper by Chris Mangelsdorf, Analog Devices, Inc., 1996 IEEE International Solid-State Circuits Conference, and is herein incorporated by reference.
Sequential Correlated Double Sampling Technique for CMOS Area Array Sensors
The present application discloses a technique which suppresses FPN in a CMOS image sensor. The technique uses an integrated Sequential Correlated Double Sampling ("SCDS") architecture to suppress both pixel and column FPN during pixel readout, and demonstrates that the FPN level can be reduced to 0.2 mV--essentially the same FPN level of CCD technology. In general, in a CDS architecture, a pixel sensing NMOS transistor (as shown in FIG. 3) performs double sampling. First, the photodiode voltage is sensed. Then a known, fixed voltage, e.g. V.sub.RES, is sensed. Subtraction is then performed to suppress the mismatch effect caused by the pixel sensing NMOS transistor threshold variations across the wafer. Whereas conventional schemes incorporate the slower frame-subtraction method to suppress FPN, the innovative technique performs FPN suppression sequentially on a faster pixel-by-pixel and column-by-column basis.
An advantage is that the SCDS technique uses a maximum of five clock cycles (five steps--Table I) for every pixel and column read cycle, whereas conventional methods utilize two to three times the number of clock cycles to perform the same function. The innovative method performs both readouts sequentially (pixel first, then column) enabling a faster readout rate (number of pixels per second). This method simplifies system design, and reduces power consumption, and ultimately, system cost. Another advantage is that the readout and comparison function is performed internal to the basic sensor whereas conventional methods require extra circuitry to perform the comparison function. Another advantage is that CMOS technology allows imaging support functions to be integrated onto a single chip. Another advantage is that the innovative SCDS technique significantly improves suppression of FPN in CMOS imagers (amounting to approximately 1/25-1/20 the level attained without the use of SCDS) encouraging widespread application of CMOS imagers.