1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM (Static Random Access Memory) cell having six transistors.
2. Description of the Related Art
A SRAM cell generally has a latch and two transistors (word transistors). On-off operations of the transistors are controlled based on the voltage applied to a word line and thereby connection between each of two memory nodes of the latch and a bit line is made or broken. SRAM cells can be broadly divided into two types, namely, a MOS transistor load type and a high resistance load type, based on a difference in a load element of the latch. SRAM cells of the MOS transistor load type, configured with six transistors, fall into two known types: a P-channel MOS transistor (called pMOS in the followings) load type and a TFT (Thin Film Transistor) load type, according to the type of its load transistor.
FIG. 6 shows an example of a configuration pattern of a SRAM cell of the pMOS load type according to the related art. In FIG. 6, a SRAM cell is shown provided with a gate of the transistor. Wire connection inside the cell or upper wiring layers such as bit lines are omitted.
The SRAM cell 100 of the pMOS load type has two p-type active regions 101a and 101b, and two n-type active regions 102a and 102b. In the p-type active regions 101a and 101b, an n-channel MOS transistor (called nMOS in the followings) as a drive transistor is formed. In the n-type active regions 102a and 102b, a p-channel MOS transistor (called pMOS in the followings) as a load transistor is formed. The p-type active regions 101a and 101b, and the n-type active regions 102a and 102b are surrounded by an element separation insulating region 103 of LOCOS (Local Oxidation of Silicon) or trench construction, for example.
In the SRAM cell 100 of the related art, the two p-type active regions 101a and 101b are provided in a parallel arrangement, one above the other as seen in the figure. Each of the p-type active regions 101a and 101b has a step 106. In the p-type active region 101a , a drive transistor Qn1 and a word transistor Qn3 are formed on opposite sides of the step 106 to sandwich the step 106. In the p-type active region 101b, a drive transistor Qn2 and a word transistor Qn4 are formed on opposite sides of the step 106 to sandwich the step 106. A word line (WL1) 194a, which also works as a gate electrode of the word transistor Qn3, is provided orthogonal to the p-type active region 101a. A word line (WL2) 104b, which also works as a gate electrode of the word transistor Qn4, is provided orthogonal to the p-type active region 101b. On the other hand, a common gate line 105a (GL1), which also works as a gate electrode of the drive transistor Qn1, is provided in the vertical direction viewing FIG. 6 and orthogonal to the p-type active region 101a. A common gate line 105b (GL2) is provided in the same direction and orthogonal to the p-type active region 101b. The common gate lines 105a and 105b, and the word lines 104a and 104b are all made of a first polysilicon layer containing impurities.
The common gate line 105a is also orthogonal to the n-type active region 102a. The common gate line 105b is also orthogonal to the n-type active region 102b. Thereby, pMOS (load transistors Qp1 and Qp2) are formed in the n-type active regions 102a and 102b. The load transistor Qp1 and the drive transistor Qn1 constitute a first inverter. The load transistor Qp2 and the drive transistor Qn2 constitute a second inverter. The first inverter and the second inverter constitute a latch. The common gate line 105a is in line with the word line 104b. The common gate line 105b is in line with the word line 104a. Each of the p-type active regions 101a and 101b is electrically connected to a bit line (not shown) or a Vss (common potential) supply line (not shown) via a contact 107. Each of the n-type active regions 102a and 102b is commonly connected to a Vcc (source voltage) supply line via a contact (not shown).
In the SRAM cell with the above-described six-transistor configuration of the related art, the relationship between the word transistors and the drive transistors is given by DT.L=WT.L, where DT.L denotes a channel length of the drive transistors Qn1 and Qn2, and WT.L denotes a channel length of the word transistors Qn3 and Qn4; to be specific, DT.L=WT.L=0.18 xcexcm, as will be shown in Table 1 later. In addition, denote a channel width of the drive transistors Qn1 and Qn2 by DT.W. Denote a channel width of the word transistors Qn3 and Qn4 by WT.W. Then, DT.W equals to 0.64 xcexcm while WT.W equals to 0.49 xcexcm. A channel width as used herein refers to the length of a transistor measured vertical to the direction of channel current flows.
According to the general practice in such a SRAM cell, the drive transistors Qn1 and Qn2 have the same dimensions (i.e., channel length and channel width) as the word transistors Qn3 and Qn4; that is, DT.W/WT.W=DT.L/WT.L=1.0.
However, this is not the case in a cell design intended for ensuring stability of cell operation such as static noise margin (hereinafter referred to as SNM). In such a cell design, the channel width DT.W of the drive transistors Qn1 and Qn2 is larger than the channel width WT.W of the word transistors Qn3 and Qn4. In other words, a cell is designed so that the word transistors Qn3 and Qn4 have relatively larger resistance to channel current compared to the drive transistors Qn1 and Qn2, thereby pull down current decreases. For this purpose, as shown in FIG. 6, in the SRAM cell 100 of the related art as described above, the patterns of the p-type active regions 101a and 101b have steps 106 to cause a difference between the channel width of the drive transistors Qn1 and Qn2, and the channel width of the word transistors Qn3 and Qn4. The height of the steps 106, that is, a difference between DT.W and WT.W (DT.Wxe2x88x92WT.W), equals to 0.15 xcexcm.
On the other hand, to achieve higher integration, the selfalign contact technique is introduced in such a SRAM cell, or alternatively, the pattern of the contact is formed in accurate alignment with respect to a first polysilicon base layer (i.e., the word lines 104a and 104b, and the common gate lines 105a and 105b). This reduces space between the polysilicon layer and the contact 107 to scale down a cell.
In general, however, the corners of the steps 106 of the patterns of the p-type active regions 101a and 101b are rounded (corner rounding) through the resist patterning process; forming the patterns to precise design dimensions is impossible. If space between the polysilicon layer and the contact 107 is reduced as described above, the distance between the drive transistor Qn1 or Qn2, and the word transistor Qn3 or Qn4 decreases. This causes a decrease in the distance between the steps 106 and the drive transistor Qn1, the drive transistor Qn2, the word transistor Qn3 or the word transistor Qn4. The steps 106 are provided between the drive transistor Qn1 and the word transistor Qn3, and between the drive transistor Qn2 and the word transistor Qn4. In other words, the drive transistors Qn1 and Qn2, and the word transistors Qn3 and Qn4 are formed in or in the neighborhood of the areas with occurrences of corner rounding (corner rounding areas 106a) as shown by the dash-double dot lines in FIG. 6. This causes a problem that the drive transistors and the word transistors of the SRAM cell of the related art cannot be formed with an exact channel width to design dimensions.
For this reason, in the SRAM cell of the related art, even if space between the polysilicon layer and the contact is reduced by introducing the selfalign contact technique or by forming the pattern of the contact in more accurate alignment with respect to the polysilicon base layer, it is necessary to increase space between the drive transistor and the word transistor to the extent that would prevent the influence of the corner rounding areas. This limits a scale down of a cell.
The present invention is made in view of such a problem. An object of the invention is to provide a semiconductor memory device making it possible to suppress the occurrence of corner rounding, to reduce the size of cells and to achieve higher integration.
A semiconductor memory device according to the present invention comprises a drive transistor and a word transistor, wherein the relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by:
(DT.W/WT.W)/(WT.L/DT.L) less than 1.2
A channel width as used herein refers to a length of a transistor measured vertical to the direction in which channel current flows.
In the semiconductor memory device according to the present invention, the relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given as stated above. Making DT.W/WT.W closer to 1.0 while making WT.L/DT.L larger than 1.0, that is, making a channel length WT.L of the word transistor larger than a channel length DT.L of the drive transistor, reduces or eliminates the steps of the patterns in active regions. This suppresses the occurrence of corner rounding through the resist patterning process.
Other and further objects, features and advantages of the invention will appear more fully from the following description.