1. Technical Field
Embodiments of the present disclosure relate to a semiconductor device which performs a domain crossing operation between an external clock and an internal clock.
2. Related Art
In general, in the case of a semiconductor device including a double data rate synchronous dynamic random-access memory (DDR SDRAM), an internal clock is generated based on an external clock and is used as a reference clock for matching various operation timings in the semiconductor device. Thus, an internal clock generation circuit for generating the internal clock is disposed in the semiconductor device. Generally, because a skew occurs between the external clock and the internal clock due to an internal delay of the semiconductor device, a phase-locked loop (PLL) and a delay-locked loop (DLL) are used in the internal clock generation circuit.
Meanwhile, the semiconductor device receives a read command synchronized with the external clock, and outputs data stored therein, to an external source, in response to the internal clock. That is to say, the semiconductor device, when outputting data, uses not the external clock but the internal clock. Due to this fact, in a read operation, an operation of synchronizing the read command with the internal clock is performed. Such an operation of synchronizing a signal, which has been synchronized with a certain clock signal, with another clock signal is referred to as domain crossing.