The present disclosure relates to semiconductor memories and, more particularly, to a nonvolatile memory system including a nonvolatile memory device and a memory controller and an operating method of the memory controller.
Semiconductor memory device are memory devices implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). In general, semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.
Volatile memory devices lose their stored data when their power supplies are interrupted. Nonvolatile memory devices may include a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM). Nonvolatile memory devices are memory retain their stored data even when their power supplies are interrupted. Nonvolatile memory devices may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).
Flash memories have been used in a variety of applications due to low noise, low power consumption, and high-speed operation. For example, a mobile system such as a smartphone and a tablet PC uses a high-capacity flash memory as a storage medium.
A flash memory includes semiconductor elements such as a floating gate memory cell and a charge trap flash (CTF) memory cell. In particular, the CTF memory cell traps charges to a charge storage layer such that a threshold voltage of a memory cell is changed to store data. However, a threshold voltage of the CTF memory cell is changed as charges stored in the charge storage layer migrate to a channel layer with the lapse of time. This physical characteristic is called initial verify shift (IVS). Due to the IVS, data stored in CTF memory cells is lost.
In order to overcome the above disadvantage, a memory system implemented with a CTF memory cell separately manages program time. However, although the memory system separately manages the program time, threshold voltage change caused by IVS varies depending on characteristics (e.g., erase count, external temperature, etc.) of the respective memory cells. Accordingly, there is a need for a separate management method.