As continuously increasing demands are placed on computers, the capability of a single processor (primary frequency, line width, etc.) also increases continuously. However, it can be predicted that such increases in the capability of the single processor will finally reach a high-point. Thus, when the capability of a single processor increases to a certain point, in order to continuously obtain higher microprocessor performance, it has to be developed in a different direction. The main factors for promoting the continuous increases in microprocessor performance are rapid progress in semiconductor manufacturing technology and the continuous development of the processor architecture. By using the current semiconductor manufacturing technology, the number of transistors integrated in a microprocessor can reach several hundred million, and the structure of a microprocessor is ensured to develop in a more complicated direction. Thus, under such technical development and demands, the multi-core (multiprocessor) architecture becomes essential.
The multi-core architecture enhances the parallelism of program execution by integrating a plurality of microprocessor cores on a chip. Each microprocessor core is a relatively simple single-thread microprocessor or a comparatively simple multi-thread microprocessor in nature. In the multi-core architecture, the plurality of microprocessors can execute tasks in parallel, so that the parallelism at the thread level is relatively high. Further, the multi-core architecture can obtain such advantages as high primary frequency, short design and validation period, simple control logic, good expansibility, easy implementation, low power consumption, and low communication delay, by adopting relatively simple microprocessors as the processor cores. Therefore, in the future development trend, no matter whether it is a mobile application, an embedded application, a desktop application or a server application, the multi-core architecture will be adopted.
However, while the multi-core architecture has a lot of advantages, it also creates system and program design challenges and other challenges. That is, because the multi-core architecture encapsulates a plurality of processor “execution cores” in a single processor, as long as the design of software is appropriate, the complete parallel execution of a plurality of threads of the software can be supported by the multi-core architecture. Accordingly, the design of such a multi-core architecture forces the development of software to go in the parallelization direction, so as to realize the advantages of the multi-core architecture.
However, under the x86 architecture, developers of application programs still remain in the single thread development mode. As the multi-core architecture is being gradually employed on PCs, servers, embedded systems, game consoles, and so on, traditional sequential programming concepts under the x86 architecture will be weakened by the concurrency and synchronization. Especially for a programmer on CELL multi-core architecture like heterogeneous memory constraint systems (in which each processor core has a limited 256 KB local storage), the programmer should transform from a sequential programming design concept to a parallel one. That is, programmers should learn how to design application programs for a multi-core architecture like CELL (i.e., learn how to carry out parallel program design). However, in parallel program design, identification of parallelism and partition of parallel tasks of the functions in program code are always considered as a kind of art that is highly dependent on the programmers' domain knowledge, experience and architectural understanding. Without enough support tools, parallelism analysis and task partitioning greatly reduce the overall parallel software development productivity.
Therefore, there is a need for an efficient and accurate technology for analyzing parallelism of program code to facilitate the design of parallel programs to perform parallelism analysis and task partitioning of program code more efficiently with respect to a multi-core architecture so as to increase the efficiency of the development of parallelism software.