Often, in computer systems, a single data rate transfer technique is used to transfer data between a memory and a data processing chip by using a clock cycle. The data transfer is supported with the help of a control over some signals. Data between the data processing chip and the memory chip changes on a single edge in the single data rate devices.
In the existing techniques the computer systems use a double data rate to transfer the data between memory and the data processing chip. Double data rate allows twice the data to be transferred on each clock cycle as compared to the single data rate transfer technique and the data between the data processing chip and the memory chip changes on both edges of a reference clock signal. As an example there exists a method wherein, a Delay Locked Loop uses a timing signal. An example of the timing signal is a control signal to the memory chip that can be synchronized with respect to an internal reference signal. This is accomplished by delaying a desired signal by a particular amount and then comparing the delayed signal to the reference signal. The delay can be adjusted until the reference signal and the delayed signal have a desired timing relationship. The existing technique may not support to achieve a fine delay resolution. Also, more gates are used for delaying the desired signal.
In another example, the Delay Locked Loop in double data rate memory interfaces use analog circuit to delay or compare signals. The analog circuits are difficult to implement and control using standard digital logic processes as the analog circuits require additional characterization and prototype work.
In light of the foregoing discussion, it is desirable to have an efficient system and method for precise control of timing signals between the memory and the processing chip in Digital Delay Locked Loop.