The Dynamic Random Access Memory (DRAM) cells are typically composed of two main components, a storage capacitor for storing charges and an access transistor for transferring charge to and from the storage charge. The storage capacitor can be either a planar capacitor on the surface of a semiconductor substrate or a trench capacitor etched into the semiconductor substrate. As the technologies advance, the size of the semiconductor device is continuously scaled down. Because the layout of the trench capacitor results in a dramatic reduction in the space without sacrificing capacitance, the trench capacitors are predominantly used in the semiconductor device.
For DRAM cells, the electrical connection between the storage capacitor and the access transistor is critical for maintaining their functionality. The electrical connection between the trench capacitor and the transistor is generally a buried strap structure, which is formed between a source/drain junction of the access transistor and the electrode of storage capacitor. However, the traditional buried strap is often subjected to several subsequent thermal processes that cause lots of dopant to out-diffuse from the buried strap resulting in serious sub-threshold leakage. Additionally, the traditional buried strap also bears relative high connection resistance, and the process steps are very complicated. Moreover, for an array type configuration, the buried strap generally only locates in a single side and has the disadvantages, such as complicated manufacturing processes and a high defect density caused by the etching/refilling processes etc.
Therefore, there is a need to provide a method for forming a single-sided buried strap to effectively inhibit the dopant out-diffusion and reduce the defects resulted from the etching/refilling steps.