1. Technical Field
The present disclosure relates to a clock and data recovery method and corresponding device.
The description particularly, but not exclusively, relates to a clock and data recovery method for an ASIC chip designed for telecom/datacom applications and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
An ASIC (acronym from Application-Specific Integrated Circuit) is a chip designed for a particular application. It typically consists of a core logic, where the specific application is implemented, and an in/out interface, that connects the specific application to the overall system.
An ASIC for telecom/datacom applications generally includes, as an input/output interface, a SERDES interface (serial-to-parallel/parallel-to-serial interface). Its goal is to adapt high speed serial data rate of a data line to a low speed parallel data rate of the chip core. Line data rate is linked to bandwidth requirements of communication systems and limited by technology. Core data rate is linked to the available technology (for instance, the CMOS technology presently used) in terms of both maximum operating frequencies and digital design tools.
Apart from the individual trends of line and core data rates (the former growing up faster than the latter), new applications typically require a certain degree of back-compatibility with respect to old applications.
Hence, an ASIC is generally able to treat a high data rate as well as a low data rate through the very same SERDES interface. It should be noted that the low data rate is usually an integer sub-rate of the high data rate.
More particularly, for telecom/datacom applications in data transmission through ASICs, the reliability and the quality of a data link or generally of a communication line depends on the timing control.
In addition, the transmission of a clock signal from one end to the other of a communication line in a telecom/datacom system is expensive, both because the clock signal is not a payload and because of technology limitations due to its bandwidth.
Nowadays, the latter issue is usually solved in the field by double data rate interfaces. According to this solution, both the rising and the falling edges of the clock signal are used as reference events (in contrast with normal data rate interfaces where only one type of edge, the rising or falling one, of the clock signal is used as a reference event). In this way data and clock signals have the very same physical bandwidth. However, the known solutions are still affected by the former problem.
Moreover, communication lines with a clock signal transmitted therethrough have strong timing budget requirements, which become harder and harder to meet when the data rate increases, since the bit period becomes smaller and smaller.
The most popular way to control timing is by embedding a clock signal into the transmitted data and recovering the timing information at the receiver side of the communication line by means of a clock and data recovery device (CDR in the following). In particular, the CDR recovers the timing information based on the transitions of input data, under the assumption that the nominal bit period is constant, thus producing a recovered data signal as well as a recovered clock signal.
Then, taking recovered data and clock signals from the CDR, a serial to parallel converter matches the line data rate and the core data rate.
Traditionally, analog phase-locked loops (PLL) have been used to implement CDR devices. Although, in general, an analog PLL can operate at high frequencies, it suffers from problems such as, for instance, the frequency drift during long sequences of identical bits (also indicated as CID, Consecutive Identical Digits) and the difficult lock acquisition process (at the power on or after a loss of synchronization).
Being a CDR using analog PLL a fully analog solution, high performances are expected, but they are paid in terms area and power consumption. Another drawback is a hardly portable design through technologies. CDRs of this kind are described in the following references:                U.S. Pat. No. 4,949,051 issued on Aug. 14, 1990 to J. P. Viola and concerning a “Phase lock clock recovery with aided frequency acquisition”;        “A monolithic 622 Mb/s clock extraction data retiming circuit”, Benny Lai, Richard C. Walker, ISSCC Dig. Tech. Papers, pp. 144-145, February 1991; and        “An analog PLL-based clock and data recovery circuit with high input jitter tolerance” Sam Y. Sun, IEEE JSSC vol. SC-24, pp. 325-330, April 1989.        
Another approach to timing or clock recovery is the digital one. Here, the smallest possible analog front end is used to generate timing information that feeds a recovery algorithm. This algorithm is usually described and implemented using a high level language (VHDL).
In this way, a certain degree of portability through technologies is possible as well as some area and power saving. On the other hand, it is difficult to obtain high performance devices.
Digital timing recovery in a serial connection line is typically done by a CDR device in two ways that are by tracking and by oversampling.
In a tracking CDR, an optimum sampling phase is chosen among a discrete set, by an appropriate algorithm, and the output data is the input data which is sampled by the selected sampling phase. CDRs of this kind are described in the following references:                U.S. Pat. No. 5,812,619 issued on Sep. 22, 1998 to Runaldue and concerning a: “Digital phase lock loop and system for digital clock recovery”;        “A tracking clock recovery receiver for 4-Gbps signaling”, J. Poulton, W. I. Dally, S. Tell, IEEE Micro Vol. 18 Issue 1, pp. 25-27, January/February 1998; and        “A semi-digital delay-locked loop using an analog-based FSM”, W. Rhee, B. Parker, D. Friedman, IEEE Trans. on Cir. and Sys. II: E. B. Vol. 51 Issue: 11, pp. 635-639, November 2004.        
In an oversampling CDR, the input data are sampled by more than one phase at the same time and an algorithm takes the decision of which value has been sampled. CDRs of this kind are described in the following references:                U.S. Pat. No. 6,611,219 issued on Aug. 26, 2003 to Lee et al. and concerning an: “Oversampling data recovery apparatus and method”;        “A 1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method” J.-Y. Park, J. K. Kang, IEICE Trans. Fund. Vol. E83 No. 6, June 2000; and        “A 0.5 um CMOS 4.0 Gb/s serial link transceiver with data recovery using oversampling”, C.-K. K. Yang, R. Farjad-Rad, M. A, Horowitz, IEEE JSSC Vol. 33 No. 5, May 1998.        
A strong difference between tracking and oversampling CDRs is that the former solution recovers the clock while the latter recovers the data. In other words, the output of a tracking CDR is a data-clock pair with a known phase relationship, while the output of an oversampling CDR is typically a data signal.
The main drawbacks of the above described solutions are as follows:                custom design is still rather dominant so technology portability is difficult;        efforts and tradeoffs are required to cover wide data rate ranges;        the scalability is more and more difficult with increasing data rate.        
The technical problem underlying the present description is that of providing a clock and data recovery method and corresponding device having structural and functional characteristics which allow to improve the scalability with different technologies and frequencies, in this way overcoming the limits which still affect the conventional methods and devices.