The following patents/patent applications are hereby incorporated herein by reference:
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a ferroelectric memory device.
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM. The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example.
Two types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
As illustrated in prior art FIG. 1, a 1T/1C FeRAM cell 10 includes one transistor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1T/1C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bitline 18 of the transistor 12 is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 2, a 2T/2C memory cell 30 in a memory array couples to a bit line (xe2x80x9cbitlinexe2x80x9d) 32 and an inverse of the bit line (xe2x80x9cbitline-barxe2x80x9d) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and 42, respectively. The first transistor 36 couples between the bitline 32 and a first capacitor 40, and the second transistor 38 couples between the bitline-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bitline 32 and the bitline-bar line 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the bitline-bar line 34, respectively. A differential signal (not shown) is thus generated across the bitline 32 and the bar-bar line 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) which provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
A first step in the formation of the FeRAM cell is the formation of a capacitor stack. Typically, such a stack is formed by consecutively forming layers such as the bottom diffusion barrier layer, the bottom electrode layer, the dielectric layer and the top electrode layer, as illustrated in prior art FIG. 3. Subsequently, a hard mask layer is formed thereover and defined in accordance with a desired dimension of the capacitor structure. The defined hard mask is then employed in a subsequent, multi-step etch process by which the various layers are patterned so as to be relatively self-aligned with respect to the hard mask. Therefore the capacitor stack structure is defined in accordance with a single lithography step by which the hard mask is defined. Accordingly, an alignment associated with such lithography step is important in minimizing FeRAM cell size. That is, since the capacitor structure typically makes contact to an underlying transistor structure via a tungsten (W) contact, an accurate alignment of the capacitor with respect thereto permits the FeRAM cell size to be minimized.
The alignment of the capacitor structure is dictated primarily by the lithography step employed to define the hard mask layer, and such alignment is achieved using an alignment mark.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to the fabrication of an FeRAM device that is either a stand-alone device or one which is integrated onto a semiconductor chip that includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and backend processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
The following discussion is based on the concept of creating the ferroelectric capacitors in an FeRAM process module that occurs between the front end module (defined to end with the formation of tungsten, which has the chemical symbol W, contacts) and backend process module (mostly metallization). Other locations of the FeRAM process module have also been proposed. For example, if the FeRAM process module is placed over the first layer of metallization (Metal-1) then a capacitor over bitline structure can be created with the advantage that a larger capacitor can be created.
Another possible location for the FeRAM process module is near the end of the back-end process flow. One advantage of this approach is that it keeps new contaminants in the FeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools. This solution is most practical if the equipment used after deposition of the first FeRAM film is dedicated to the fabrication of the FeRAM device structures and, therefore, is not shared. However, this solution may have the drawback of requiring FeRAM process temperatures compatible with standard metallization structures (suggested limitations discussed above). In addition, the interconnection of the FeRAM capacitor to underlying transistors and other needs of metallization may not be compatible with a minimum FeRAM cell size.
The requirements for the other locations will have many of the same concerns but some requirements may be different.
The FeRAM process module is preferably compatible with standard logic and analog device front-end process flows that include, for example, the use of tungsten contacts as the bottom contact of the capacitor. The FeRAM thermal budget is preferably low enough so that it does not impact substantially the front end structures such as the low resistance structures (which includes the tungsten plugs and silicided source/drains and gates) employed in many logic devices. In addition, transistors and other front end devices, such as diodes, may be sensitive to contamination. Contamination from the FeRAM process module, either direct (such as by diffusion in the chip) or indirect (cross contamination through shared equipment), should be addressed so as to avoid transistor and diode degradation. The FeRAM devices and process module should also be compatible with standard backend process flow. Therefore the FeRAM process module should have minimum degradation of logic metallization""s resistance and parasitic capacitance between metal and transistor. In addition, the FeRAM devices should not be degraded by the backend process flow with minimal, if any modification. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen degradation and most logic backend process flows utilize hydrogen and/or deuterium in many of the processes (such as in the formation of SiO2 and Si3N4, CVD tungsten deposition, SiO2 via etch, and forming gas anneals).
Commercial success of FeRAM also advantageously addresses minimization of embedded memory cost. Total memory cost is primarily dependent on cell size, periphery ratio size, impact of yield, and additional process costs associated with memory. In order to have cost advantage per bit compared to standard embedded memories such as embedded DRAM and Flash it is desirable to have FeRAM cell sizes that are similar to those obtained with standard embedded memory technology. Some of the methods discussed in this patent to minimize cell size include making the process flow less sensitive to lithography misalignment, forming the capacitor directly over the contact, and using a single mask for the capacitor stack etch. Some of the methods discussed in this patent, to reduce the added process cost, may require two additional masks for the FeRAM process module and a planar capacitor which reduces the complexity of the needed processes.
Although this patent focuses on using a planar capacitor, a three dimensional capacitor using post or cup structure can be fabricated using many of the same concepts and processes. The planar structure is illustrated because it uses a simpler process and is cheaper to make. The 3D capacitor is preferred when the planar capacitor area needed for minimum charge storage considerations limits the cell size. In this situation, the capacitor area enhancement associated with the 3D configuration allows a smaller planar cell size. DRAM devices have used this approach for many years in order to reduce cell area.
The present invention relates to a method of forming an FeRAM capacitor. In particular, the present invention relates to a method of establishing a reliable alignment mark in conjunction with the formation of an FeRAM capacitor. In general, an alignment mark is employed in a lithography step to properly align a mask used to define the capacitor stack using, for example, a hard mask layer. With proper and accurate alignment, the capacitor stack width (and thus its size) can be minimized without concern of losing electrical contact to an underlying transistor structure, for example, via a conductive contact. Therefore by ensuring an accurate alignment of the capacitor stack, an FeRAM capacitor size can be minimized, thereby facilitating an increase in memory density when such FeRAM capacitors are employed in an FeRAM array.
The present invention establishes a reliable alignment mark by effectively smoothing a sidewall surface roughness of a tungsten layer within an alignment mark via. With the tungsten sidewall surface roughness reduced, a step coverage of a subsequent barrier layer over the tungsten sidewall within the alignment mark via is improved substantially. Accordingly, the barrier layer is substantially more effective in preventing the tungsten layer within the alignment mark via to oxidize (which tungsten will do aggressively), thus preventing a substantial volume expansion which may otherwise accompany such oxidation. Therefore the barrier layer permits subsequent layers such as the capacitor stack layers to form in a substantially conformal manner in the alignment mark via which causes a top portion of the capacitor stack layers to exhibit a topography difference associated therewith. Such a topography difference is then employed as the alignment mark for the lithography step used to pattern the capacitor stack layers to thereby form the capacitor stack.
According to one aspect of the present invention, a method of forming an FeRAM capacitor over one or more transistors associated with a semiconductor substrate is disclosed. The method comprises forming a dielectric layer over the one or more transistors and forming a contact via and an alignment mark via, respectively, in the dielectric layer. A tungsten layer is the formed over the substrate, covering the dielectric layer, filling the contact via, and covering the alignment mark via in a substantially conformal manner, wherein the tungsten layer has a sidewall surface within the alignment mark via. The method further comprises reducing a roughness associated with the sidewall surface of the tungsten within the alignment mark via. Accordingly, the step coverage of a subsequently formed barrier layer over the smoothed tungsten within the alignment mark via is improved substantially due to the reduced tungsten sidewall surface roughness.
The method further comprises patterning the tungsten layer to thereby remove portions overlying the dielectric layer and thus electrically isolate the contact via from the alignment mark via. Capacitor stack layers are then formed over the substrate and overlying the alignment mark via in a substantially conformal manner. In the above manner, the alignment mark via is reflected in a top portion of the capacitor stack layers as a topology variation. Such a topology variation or difference is then employed as an alignment mark in the subsequent lithography step used to pattern the capacitor stack layers to define the capacitor stack. The improved step coverage of the barrier layer within the alignment mark via prevents an oxidation of the underlying tungsten layer during subsequent processing steps, for example, during the deposition of the capacitor stack layers. By preventing the oxidation of the tungsten, the shape integrity of the alignment mark via is maintained, thus permitting a topology difference in the top of the capacitor stack layers to accurately reflect the position of the alignment mark via. In the above manner, the alignment mark and its position is reliably established.
In accordance with another aspect of the present invention, the sidewall surface roughness of the tungsten layer in the alignment mark via is reduced by forming a smoothing layer over the tungsten layer prior to the formation of a barrier layer thereover. The smoothing layer is then patterned so as to remove a portion thereof which overlies the dielectric layer and the contact via, leaving another portion of the smoothing layer on the sidewall surface of the tungsten layer within the alignment mark via. In accordance with one example, the smoothing layer is patterned via a chemical mechanical polish process, while in another example, such patterning occurs via a chemical etch process. The remaining portion of the smoothing layer on the sidewall surface of the tungsten layer in the alignment mark via results in a smooth sidewall surface, thus substantially improving a step coverage of the subsequently formed barrier layer thereover. The improved barrier layer step coverage prevents any potential tungsten oxidation during subsequent processing steps.
According to another aspect of the present invention, a reduction of the tungsten sidewall surface roughness within the alignment mark via comprises removing a portion of the tungsten layer therein. In one example, substantially all of the tungsten layer within the alignment mark via is removed using an extra mask step in which a region over the alignment mark via is defined and the tungsten therein is removed substantially via etching. In another example, an exposed surface portion of the tungsten layer has a surface roughness associated therewith reduced via a preliminary etch process. For example, in adding Ar to the etch process, portions of etched tungsten redeposit on the tungsten sidewall surface within the alignment mark via. Subsequently, a chemical mechanical polish is employed to remove remaining portions of tungsten which overlie the dielectric layer and the contact via, respectively, thereby leaving the smoothed tungsten sidewall layer within the alignment mark via. The smooth tungsten sidewall surface facilitates improved step coverage for a subsequently formed barrier layer, thereby preventing oxidation of the tungsten within the alignment mark via.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.