1. Field of the Invention
The present invention relates to methods for fabricating a semiconductor device, and in particular to a technology for preventing dishing of a dielectric film which serves as an insulating film in a chemical mechanical polishing (CMP) process of a conductive layer for a contact plug.
2. Description of the Background Art
A conventional CMP process isolates a plug by using a basic slurry. A nitride film is typically used as a hard mask layer of a word line, and an oxide film is typically used as a planarization and gap fill material. In a polishing process of a plug material, the plug material and the oxide film are dished more than the nitride film due to differences in an etching selectivity ratio of the three materials. It is thus necessary to deposit additional oxide film.
When CMP process residues fall into the dished region of the plug material and the oxide film, the residues may not be removed in a succeeding cleaning process. As a result, a bridge may be generated between a bit line contact plug and a storage electrode contact plug. Such a bridge undesirably reduces device yield.
FIGS. 1 and 2 are diagrams for explaining disadvantages of a conventional method for fabricating a semiconductor device.
Referring to FIG. 1, a word line is formed having a mask insulating film pattern composed of a nitride film at its upper portion, and a nitride film spacer at its side walls. An interlayer insulating film composed of BPSG is formed to planarize the upper portion of the resultant structure. A storage electrode contact hole and a bit line contact hole are formed by etching the interlayer insulating film in a self aligned type according to a photolithography process using an exposure mask for forming the storage electrode contact hole and the bit line contact hole. A conductive layer is formed over the resultant structure, filling up the contact holes. The conductive layer is etched to expose the interlayer insulating film, and a contact plug is formed by performing the CMP process until the mask insulating film is exposed.
Here, the CMP process is performed by using differences in an etching selectivity ratio of the nitride film, which is the mask insulating film, the BPSG, which is the silicon oxide film, and the conductive layer for the contact plug.
In FIG. 1, (a) denotes dished regions of the conductive layer for the contact plug due to over-etching in the CMP process. Also in FIG. 1, (b) denotes dished regions of the BPSG, which is the interlayer insulating film, due to over-etching in the CMP process.
FIG. 2 is a photograph showing device failure generated due to the dishing of FIG. 1. The bit line contact plug and the storage electrode contact plug are shorted out in a succeeding process by residues generated in the CMP process of a landing plug poly (LPP).
In FIG. 2, (c) denotes column failure and (d) denotes bit failure.
As described above, the conventional method for fabricating semiconductor devices has a disadvantage in that a property and yield of the device are deteriorated due to dishing effects.
Accordingly, the present invention provides methods for fabricating a semiconductor device which can improve a property, reliability and a yield of the semiconductor device by reducing dishing in a CMP process for forming a contact plug. In one embodiment, the fabrication method includes performing a first CMP process using a basic slurry having a higher polishing speed to a silicon layer and an oxide film than to a nitride film, and performing a second CMP process using an acid slurry to decrease the dishing.
One such method for fabricating a semiconductor device according to the present invention includes forming a gate insulating film on a semiconductor substrate, and forming a conductive interconnection on the gate insulating film to overlap with a mask insulating film pattern composed of a nitride film. An insulating film spacer is formed at the side walls of the conductive interconnection and the mask insulating film pattern. An interlayer insulating film consisting of an oxide film is formed to planarize the surface of the resultant structure. A storage electrode contact hole and a bit line contact hole are formed to expose the semiconductor substrate by etching the interlayer insulating film and the oxide film according to a photolithography process using a contact mask. The method further includes forming a contact plug consisting of silicon to fill the contact holes, performing a first CMP process using a basic slurry to etch the contact plug and the interlayer insulating film by a predetermined thickness, and performing a second CMP process using an acid slurry to etch the contact plug and the interlayer insulating film, thereby exposing the mask insulating film pattern.
In one aspect of the present invention, the basic slurry has pH 6xcx9c12, and the acidic slurry has pH 6 and below. In addition, the acid slurry has the polishing selectivity (silicon layer/oxide film layer) of 0.5xcx9c2.
In another aspect of the present invention, an antireflection film composed of a silicon oxide nitride film (SiON) is formed on the mask insulating film, and an organic bottom antireflection film is formed on the conductive interconnection.
In yet another aspect of the present invention, the contact plug includes amorphous silicon, polysilicon or epitaxially-grown silicon, and is landed in a circular shape or a T-shape.
In still another aspect of the present invention, the CMP process is performed using the acidic slurry of pH 6 and below only.