The present invention concerns an encoding circuit for a recordable compact disc system, and particularly a circuit for cross interleaving digital audio data so as to adapt for the compact disc format by using a PROM.
Generally, the compact disc has been exclusively used for reproduction. However, a recordable compact disc is recently developed which requires a compact disc player to have a circuit for encoding audio data so as to be compatible with the conventional recordable compact disc.
Referring to FIG. 1, there is briefly described a conventional system for encoding audio data. The analog signals of the L and R channel audio sources are respectively passed through the first and second low pass filters 10 and 20 to produce the signals below 20 KHz, which signals are sampled by the first and second sampling circuits 30 and 40 at the period of 44.1 KHz. The sampled signals are respectively applied to the first and second analog/digital converters (A/D converters) 50 and 60 quantized into digital data of 16 bits at every sampling period (quantization ratio=44.1K sample/sec.times.2 symbol/sample=88.2K symbol/sec, where 1 symbol=one byte). The 16 bits digital data of the two L and R channels are selected by the multiplexer 70 (88.2K symbol/sec.times.2CH=176.4K symbol/sec). The data output from the first multiplexer 70 is applied to the error correction circuit 80 to produce a parity of 8 bytes by adding a parity of 4 bytes to 12 bytes when receiving the data of 24 bytes.
The control and display encoding circuit 90 produces 1 byte of the control data for the microcomputer to process music selection, etc. per 1 frame. The second multiplexer 100 generates 1 frame data of 8 symbols consisting of 1 symbol of the control and display, 12 symbols of the L channel (16 bits.times.6), 12 symbols of R channel (16 bits.times.6) and 8 symbols of the parity. At this time, the selection order is 1 symbol of the control and display data.fwdarw.12 symbols of the audio data (alternately output in L channel high, L channel low, R channel high, R channel low).fwdarw.4 symbols of the parity.fwdarw.12 symbols of the audio data (alternately output in L channel high, L channel low, R channel high, R channel low).fwdarw.4 symbols of the parity.
The EFM modulator 120 modulates each of the symbols synchronized with a frame according to the output of the synchronization signal generator 110 into the channel signal of 14 bits per 8 bits, which channel signal is delivered to the disc. The form of the 1 frame data recorded on the disc is as shown in FIG. 2. Namely, 1 symbol recorded on the disc is the channel signal of 14 bits, the synchronization pattern of 24 bits is recorded in the first position of the frame, and sequentially recorded are the control and display symbol, data symbol, and parity symbol.
Between the symbols is recorded the merge signal of 3 bits. Thus, one frame consists of totally 588 channel bits. Referring to FIG. 2, the merge signal serves to maintain the run length to be within the range of 3 T to 11 T when the channel bits are merged together.
Referring to FIG. 3 for illustrating the error correction circuit 8, the first delay circuit 81 delays 16 bits 2'S complemented data by two frames so as to produce the symbol data of 8 bits.
The first encoder 82 encodes the output of the first delay circuit 81 to generate C2(28,24) RS parity. The second delay circuit 83 delays the data output from the first encoder 82 by the frames corresponding to a multiple of 4. The second encoder 84 encodes the data output from the second delay circuit 83 to generate C1(32,28) RS parity. The third delay circuit 85 delays the data output from the second encoder 84 by one frame.
Referring to FIG. 4 for illustrating the construction of one frame data output from the encoder of FIG. 3, the data output from the error correction circuit 80 of FIG. 1 is laid out on the basis of one frame input into the encoder. For example, to represent the construction of one frame, the symbol number 27 consists of M=12n+11-12(27D), which means that a word of the audio data should be delayed by 11-12.times.27.times.4=1,296 words to be output.
Such a conventional error correction circuit may not directly included in a compact disc player because the encoder should process the data prior to recording on the compact disc without manufacturing the disc in real time.