An integrated circuit (IC) logic cell typically consists of a pre-designed layout of transistors or non-specific collection of logic gates which are configured according to a set of rules such as Design Rules (e.g. minimum wire widths, minimum spacing between structures, etc.), timing rules, and antenna rules, among others. A plurality of such pre-designed or standard IC cells, each having a unique configuration and/or logical function, is referred to as a cell library. To form an IC, such as an application specific IC (ASIC), standard cells are selected from the cell library and arranged in a desired layout. The terminals of the arranged cells are then connected to each other and to external terminals by metal wires or traces to achieve the desired logical function of the IC. This is often referred to as the “place and route” step of IC design.
The “place and route” step is typically performed by automated “place and route tools” or “routers”. Unfortunately, the wires created by routers are not always ideal for manufacturing and yield. For example, even when thicker wires could be used, routers often employ minimum width wires which are more sensitive to defect induced interruptions (“opens”) than thicker wires. Also, routers also often place wires at minimum separation distances even when larger distances, which are less sensitive to defect induced bridges (“shorts”), could be employed. Additionally, because routers typically assign wires to routing tracks which are at a regular pitch, multiple jogs are often created in wires when connecting wire to pin shapes.
Furthermore, interaction between the wires and structures of the standard cell and those added by the router sometimes create complicated shapes, referred to as “ugly shapes”, which are often, but not exclusively, near wire ends where the wire connects to via holes that vertically connect layers of the IC. These ugly shapes can introduce several problems. First, they increase data volume (i.e. file size) and runtimes of subsequent algorithms, such as those employed for optical proximity correction (OPC). They can also confuse such downstream algorithms or cause them to be more complicated and error-prone. For example, when optimizing a wire end, an OPC algorithm must detect first the wire end and then make appropriate modifications. Both stops are more complicated if wire ends come in many and unpredictable variants.
Ugly shapes also create multiple variants of a structure within a cell. Because different variants of a structure have different “acceptance regions” (i.e. the manufacturing parameter space within which a structure is successfully fabricated), the “total acceptance region” (i.e. the intersection of all individual acceptance regions) will shrink. The main manufacturing parameters of the lithography processes used to form the ICs are exposure dose, focus, and misalignment. Ugly shapes which reduce or limit the acceptance region of the lithography parameters are called “litho hot spots” and can reduce the reliability of the IC (by increasing the sensitivity to opens and shorts) and reduce manufacturing yield.
Several techniques have been employed to address the above described router shortcomings. One technique employs an algorithm which widens wires identified as being unnecessarily narrow (i.e. wires which are at a minimum width when more space is available) and increases spacing between wires which are unnecessarily close to one another (i.e. at minimum spacing when more space is available). Another commonly employed technique is to perform a lithography simulation to predict the actual shape of the wires and structures formed in a wafer in which the IC is created by optical imaging processes. Any shapes identified as being problematic (i.e. litho hot spots) are automatically modified in hopes of eliminating the litho hot spot.
While the above described techniques have achieved a certain degree of success in higher metal layers, they are not effective in lower metal layers, such as metal-1 layers, as wire shapes are often complicated and densely packed such that the fixing of one problem often creates another.