The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for the capacitor plates is conductively doped polysilicon. Such material is so utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying typography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such techniques are inherently unpredictable or inconsistent in the production of a rugged polysilicon film.
One type of polysilicon film which maximizes outer surface area is hemispherical grain polysilicon. Such can be deposited or grown by a number of techniques. One technique includes direct LPCVD formation at 590.degree. C. Another includes formation by first depositing an amorphous silicon film at 550.degree. C. using He diluted SiH.sub.4 (20%) gas at 1.0 Torr, followed by a subsequent high temperature transformation anneal. Hemispherical grain (HSG) polysilicon is typically not, however, in situ doped during its deposition due to undesired reduction in grain size in the resultant film. Accordingly, alternate techniques are utilized to conductively dope the hemispherical grain polysilicon after its deposition. To provide such doping, an underlayer of doped polysilicon can be provided, with subsequent doping of the HSG polysilicon layer occurring by an annealing step to drive the dopant outwardly. Alternately, dopant can be implanted into the polysilicon after its deposition from above, although such can have a tendency to smoothen the deposited HSG layer.
One example method for providing doped HSG poly is as follows. A doped layer of amorphous or polycrystalline silicon is provided atop substrate wafers by chemical vapor deposition within a suitable reactor. The wafers are removed from the reactor in ambient air which results in oxidation to produce a native oxide layer typically of 20 Angstroms or greater. During such fabrication, various wafers may remain in ambient air conditions for varying time periods of several hours to a few days prior to subsequent processing for forming an HSG polysilicon layer. To accommodate such varying thickness native oxide layers, the wafers are collectively cleaned in multiple HF dipping steps to remove the native oxide back to an exposed silicon layer. Then within two hours of the final strip, the wafers are provided within a chemical vapor deposition reactor.
With all wafers being processed having the common two hour or less exposure, each will have a substantially uniform thickness native oxide layer of 20 Angstroms. This native oxide layer is a requirement for formation of HSG polysilicon. Within the chemical vapor deposition reactor, the respective wafers are subjected to conditions suitable for formation of a continuous HSG polysilicon layer. At this point, the HSG layer is undoped and is subsequently subjected to suitable conditions in an effort to drive conductivity enhancing dopant ions from the underlying silicon layer through the native oxide layer and into the HSG layer. Such does not, however, typically provide a desired uniform and high dopant concentration within the HSG layer as would otherwise be provided were in situ HSG doping practical.
Needs remain for providing improved methods of producing roughened conductively doped polysilicon films for utilization in improved capacitor constructions.