The present invention relates to semiconductor latches and Static Random Access Memory (SRAM) devices.
A latch is a data storage unit in a semiconductor device comprising of two inverters. An inverter has an input and an output having a voltage of opposite polarity to said input. The inverter is connected between a system power voltage level and system ground voltage level. Two such inverters connected back-to-back have self sustaining voltages at their inputs and outputs. A static random access memory (SRAM) device is a type of semiconductor memory device that has low power consumption and fast access time relative to a dynamic random access memory (DRAM) device. An SRAM cell comprises a latch and one or more access devices. The latch stores binary data, and the access device provides the capability to read and write data into the latch. Multiple access devices provide multiple access paths to read and write the single latch data. An SRAM memory device is essentially an array of SRAM cells. They are classified by the type of inverter in the latch, by the total transistor count in the SRAM cell and by the number of access devices to configure the latch. Typical latches do not have mixed inverters as the latch transistors depend on the fabrication process technology. There are two common types of inverters used for SRAM latches: a high load resistor cell employing a high resistor or a depletion load resistor as a pull-up device of the inverter, and a CMOS type cell employing a PMOS transistor as a pull-up device of the inverter. The CMOS type cell can be further sub-divided into a thin-film transistor (TFT) cell employing a thin-film PMOS transistor (TFPT) as the pull-up device, and a full CMOS cell employing a bulk PMOS transistor as the pull-up device. In all cases the pull-down device of the inverter is a bulk NMOS transistor in SRAM construction.
SRAM classified by the total transistor count include 5T (five transistor) SRAM cells, 6T (six transistors) SRAM cells, 2T/2R (two transistor, two resistor) SRAM cells, among many others. Some labels are misnomers as the full transistor count excludes capacitors and resistors needed to make the SRAM cell function correctly. In all cases, each cell includes a bi-stable latch, with two self consisting stable output values: logic 0 (voltage VS) and logic 1 (voltage VD). The output of the SRAM latch can be set to zero or one through the access transistors. The number of access transistors connected to an SRAM latch defines single port, dual port and multi port memory functionality. Multi-port feature is useful to read and write data in latches at different locations simultaneously.
An SRAM cell in single crystal Silicon (Si) has three different methods of fabrication. The most popular 6T SRAM cell, FIG. 1, has six MOSFET transistors. Fabrication is kept simple with no special processing needed by using standard CMOS transistors for the SRAM cell. All six transistors are located in substrate Silicon, and all have high mobility for electron and hole conduction. They are strong devices. The cell area is large, standby current is negligible and the access time is very fast. This configuration is used for high cost, least power, fastest access SRAM memory. In 5T SRAM memory, transistor 111 is not used.
In FIG. 1A, the SRAM cell contains a latch comprised of two switching devices (inverters) 104 and 107 back to back and two access transistors 110 and 111 that allow the data terminal 101 and/data (not data) terminal 102 to write and store 0 or 1 in the latch. The two stable operating points of the latch are alterable through the two access transistors 110, 111 via a common gate terminal 103. A single inverter 104 cannot hold data indefinitely as an isolated gate node would lose charge from junction leakages. A feedback inverter provides a current drive to the first inverter gate node to replenish lost charge. Each inverter charges the other. The use of CMOS inverters allow both logic xe2x80x9c0xe2x80x9d state and logic xe2x80x9c1xe2x80x9d state at the input of the inverter 104 and its opposite state at the input of the inverter 107 indefinitely while power is on. Internally, the inverters 104, 107 use NMOS transistors 106, 109 and PMOS transistors 105, 108 as shown in the latch in FIG. 1B. Latch transistor dimensions are scaled to ensure proper writing of these two states into the latch, cell stability against alpha particles and noise.
For a number of reasons, among them controllability and consistent current drive being the foremost, the high speed, low power SRAM memory latch is conventionally fabricated on single crystal Silicon using standard CMOS transistors for the SRAM cell. The resulting transistor consumes a relatively large amount of Silicon area. FIGS. 2A and 2B show top view and cross sectional view of a conventional CMOS inverter fabricated using a logic twin well process. An NMOS transistor 205 is inside a P-well 208, while a PMOS transistor 206 is inside an N-well 207 shown in dotted line. PMOS source 211 and drain 212 diffusions are P+ diffusion regions, while NMOS source 214 and drain 213 diffusions are N+ diffusion regions. Due to potential latch-up conditions, a separation distance Y in FIG. 2 is maintained between the two transistors 205 and 206. Both Nwell 207 and Pwell 208 are constructed on a substrate 200 of the device, which could be P-type or N-type. Latch-up arises from the P+/N-well/P-Well regions 212/207/208 and N+/P-Well/N-well regions 213/208/207 bipolar parasitic transistors near the well boundary as shown in FIG. 2B. Due to this separation, the Silicon conducting path for current flow can not be constructed in a single active semiconductor geometry. In FIG. 2B, PMOS source 211 and body 207 are tied to VD 203, and NMOS source 214 and body 208 are tied to VS 204. In other applications, the body may be separately biased. The Pwell 208 has to be biased to the lowest potential, while the Nwell 207 has to be biased to the highest potential.
In addition to the single crystal Silicon approach, an SRAM latch can be fabricated as a Resistor-load latch and a TFT PMOS-load latch, both of which have the pull-up device vertically integrated, requiring special poly-crystalline (poly) Silicon for the load device. The resistor-load latch, FIG. 3A, has poly Silicon resistors 305 and 308 as pull up devices, instead of PMOS devices. The vertically integrated single poly Silicon film allows elimination of N-wells in the substrate, and a smaller cell area construction. Only four NMOS transistors 110, 111 in FIG. 1 and 306, 309 in FIG. 3A are built on substrate Silicon, a reduction from six in full CMOS. These cells consume standby power as one inverter is always conducting, and the power consumption is determined by the resistor value. For 1 Meg density of latches and 1 mA standby current, a resistor value of 1 GOhms is needed. High value intrinsic poly-Silicon resistors are hard to build, and TFT PMOS devices offer better manufacturability. As shown in FIG. 3B, TFT PMOS can be also used as active weak PMOS pull-up devices similar to regular PMOS in FIG. 1 to eliminate stand-by current. As the pull-up device 305 or 315 current drive is very weak, these inverters cannot drive a strong logic one. These configurations of inverters are only used to build latches to construct low cost, high density, higher power, and slower access time SRAM memory. Such memories need complex dual ended sense amplifiers to read the latch data, and are sensitive to noise. As a result, embedded memory and multi-port memory is mostly constructed with CMOS latches.
In all cases the four NMOS transistors 110, 111 and the two more in inverters 104 and 107 in FIG. 1A (106, 109 in FIG. 1B or 306, 309 in FIG. 3A or 316, 319 in FIG. 3B) are strong. Metal Oxide Semiconductor Field Effect Transistors (MOSFET) fabricated on single crystal Silicon. This is due to the popularity of MOSFET devices over JFET, and the ability to form complementary MOSFET (known as CMOS) gates. MOSFET and JFET transistors are discussed next.
The MOSFET operates by conducting current between its drain and source through a conducting surface channel created by the presence of a gate voltage. FIG. 4 shows a cross section of an N-MOSFET (NMOS) conducting channel 410 with a depletion region shown shaded. In FIG. 4, an NMOS transistor body 400 is Pxe2x88x92 doped, isolating an N+ doped source region 414 and an N+ doped drain region 413. Source and drain diffusions are connected to terminals 404 and 403 respectively. The result is the formation of two N+/Pxe2x88x92 back-to-back reverse-biased diodes. For this discussion, the source 404 is assumed at zero (VS). When the voltage 402 at gate 412 is zero, the N+/Pxe2x88x92 back-to-back reverse-biased diodes do not conduct and the transistor is off. There is no surface channel 410, and the body surface under insulator 405 next to gate 412 is in accumulation of majority hole carriers. The conduction path between source and drain is now substantially non-conductive. In the embodiment of FIG. 4, the gate 412 includes a salicided region 422. A spacer 420 is formed adjacent to gate 412. Source and drain salicidation is not shown in FIG. 4. When the gate voltage 402 is greater than a threshold voltage (VT) of the transistor, an inversion occurs near the surface, shown by channel 410, completing an electron carrier path between the source 414 and drain 413 regions causing current flow. The conducting path now include source 414, channel 410 and drain 413 and is substantially conductive. In addition to the inversion layer, charge depletion occurs adjacent to the body region 400 due to the gate, source and drain voltages. The component of this depleted charge from the gate voltage determines the magnitude of the VT. Trapped oxide charge and Silicon defects affect the VT transistor parameter. The more positive the voltage is at the gate, the stronger is the conduction. At all levels, the substrate 400 potential is kept at the lowest voltage level. In most applications, the substrate and source are held at VS. Substrate can be pumped to negative voltages for special applications.
A PMOS device is analogous to an NMOS device, with the device operational polarity and doping types reversed. PMOS source is typically tied to VD. A PMOS is on when the gate is at VS, and off when the gate is at VD. Conducting path includes a P+ doped source and drain, and a surface inversion layer in the Nwell body region. The Nwell is biased to the highest potential, and in most applications the source and Nwell are held at VD. The PMOS and NMOS in a CMOS inverter share a common gate with identical voltage range. When the CMOS inverter input (or gate) is at VD, the inverter output is at VS, and visa-versa.
As discussed in U.S. Pat. No. 5,537,078, conventional JFET transistors are of two main types: P-channel (PJFET) and N-channel (NJFET). The NJFET in FIG. 5 has a semiconductor channel 506 doped Nxe2x88x92 and positioned between two N+ diffusions 513 and 514. Conducting path includes diffusion 513, resistive channel 506 and diffusion 514. Terminals 503 and 504 are coupled to diffusions 513 and 514. The terminal supplying the majority carrier to the channel (which is the lowest potential) is designated the source (S) while the other terminal is designated the drain (D). Across the Nxe2x88x92 channel 506 there are two diffused gates which are referred to as the top gate 512 and the bottom gate 522. Those are connected to terminals 502 and 532 respectively. Each gate is doped with P+ type dopant to create two back to back P+/Nxe2x88x92xcex1diodes. When drain and source voltages are different, the drain to source current passes entirely through the conducting Nxe2x88x92 channel 506. This current increases with higher voltage drop between the terminals, reaching a saturation value at high biases. The gates are biased to keep the gate to channel P+/Nxe2x88x92 junctions reversed biased. The reversed biased voltage creates depletion regions 510 and 520 that penetrate into the channel reducing the channel height available for current flow. The depletion regions merge at drain end 530 to cause current saturation at high drain bias. The gate voltages also control the flow of current between the source and drain by modulating the channel height. When the gate reverse bias is sufficiently large, the entire channel is pinched-off causing no current flow between drain and source. Conducting path is then substantially non-conductive. In both on and off states of a JFET, there is no current flow through the gate terminal due to reverse bias junction voltages, except for junction leakage current. For the device in FIG. 5 a negative gate voltage (lower than VS) creates the channel off condition. Such a negative gate voltage increases the operating voltage of this process, a draw back for JFET scheme.
A PJFET device is analogous to an NJFET device, with the device operational polarity and doping types reversed. PJFET source is held at VD. A PJFET is on when the gate is at VD, and off when the gate is more positive than VD increasing the voltage level of the process. Conducting path includes P+ doped source and drain regions, and a Pxe2x88x92 doped channel sandwiched between two N+ doped gate regions. For terminals at voltages VS and VD, operating range of NJFET gate is less than VS to VS, while the operating range for PJFET gate is VD to more than VD. Non-overlapping gate voltages prevent having a common gate input.
Compared to the non-conducting body 400 of MOSFET on FIG. 4, the JFET has a conducting channel 406 between source and drain. Due to non-overlapping gate voltages and the high voltage range thus needed, a complementary JFET process is impractical to realize. Hence there is no low cost process that provides CJFET devices analogous to CMOS devices. Compared to the MOSFET in FIG. 4, a JFET conducting channel is formed inside the body of the switching device. This channel current is not affected by trapped oxide charges near the gate, a draw back with MOSFETs. Compared to MOSFETs, JFETs also have poorer switching characteristics due to higher depleted charge stored in the channel and the transient times required to accumulate and disperse this depletion charge. Reverse biased junctions hurt JFET device ease of use and popularity in modern day ICs.
FIG. 6A illustrates the conventional CMOS inverter shown in FIG. 2A constructed with MOSFET transistors. There is no equivalent JFET construction due to gate voltage limitations. In the conventional CMOS inverter shown in FIG. 6A, the conducting path 610 allows current flow between terminal 603 and output 602, while conducting path 620 allows current flow between terminal 604 and output 602. The conducting paths 610 and 620 are constructed in single crystal semiconductor active geometries and have strong current drive. These active geometries are physically separated to allow for the latch up related well rules discussed earlier. First device comprises gate 612 and conducting path 610. Second device comprises common gate 612 and conducting path 620. Conducting path 610 couples output 602 to first voltage source 603. Conducting path 620 couples output 602 to second voltage source 604. Voltage level at common gated input 601 selects which of the two voltage sources 603 or 604 is coupled to output 602. While construction in FIG. 6A allows for high speed memory applications, the Silicon foot-print is large and expensive.
FIG. 6B illustrates the conventional R-load inverter shown in FIG. 3A constructed with a NMOS transistor. In this conventional resistor load inverter the conducting path for current flow is via the resistor and the single crystal active region. The conducting path 630 is the resistor or the TFT resistor itself. This resistance is very high and the drive current is very weak. Second device comprises gate 632 and conducting path 640. Conducting paths 630 and 640 are physically separated to facilitate the vertical integration. Conducting path 630 permanently couples a first voltage source 623 to output 622 very weakly. Strong conducting path 630 is able to couple output 622 to second voltage source 624 when activated. Voltage level at input 621 couples the output 622 to one of two voltage sources 623 or 624. While construction in FIG. 6B allows a smaller Silicon foot-print, the weak pull-up resistor makes this memory cell not suitable for high speed applications. In both cases the two conducting paths are constructed in two separate semiconductor geometries and connected together at the common node by either metal contacts, or buried contacts.
FIG. 7 illustrates a conventional 6T-SRAM cell shown in FIG. 1A. Two inverters 750 and 760 in the conventional embodiment as shown in FIG. 6A share common power supplies 708 and 707. These may be power and ground voltages respectively. Very often the power supplies are shared at a common node by two adjacent PMOS or NMOS transistors, as shown by node 708 in FIG. 7. First inverter 750 has a common gate 712 and two conducting paths 710 and 720 connected to power supplies 707 and 708. The common output is 715. Similarly a second inverter 760 has a common gate 732 and two conducting paths 730 and 740 connected to power supplies 707 and 708. The common output is 716. Conducting paths are physically separated due to latch up considerations as discussed earlier. Both inverters 750 and 760 have conducting paths in a single crystal high mobility semiconductor layer. In standard CMOS, these are Silicon active geometries for PMOS and NMOS. These active geometries have multiple doped regions in the conducting path and have isolation oxide separating the geometries For PMOS the Silicon conducting path includes P+ source, P surface inversion layer in Nwell and P+ drain. For NMOS the Silicon conducting path includes N+ source, N surface inversion layer in Pwell and N+ drain. Access device 770 couple data path 701 to inverter 750 output, while access device 780 couple data path 704 to inverter 760 output. These data paths have a plurality of access devices connections in a memory array. Gate 706 activates device 780, while gate 703 activates device 770 by turning those devices on or off. Typically these devices 770 and 780 are strong NMOS transistors. Gates 706 and 703 are coupled to row lines 705 and 702 respectively that may have a plurality of access device connections. Data paths 701 and 704 and row lines 705 and 702 are arranged in orthogonal column and row orientation to allow unique access to each cell in a cell array. Conducting paths 755 and 765 of the access devices are also constructed in the same semiconductor layer as in inverters 750 and 760. In CMOS, conducting paths 710, 730, 755, 765 are NMOS active areas and share a common geometry. Conducting paths 720 and 740 are PMOS active areas sharing another common geometry separated from NMOS by an isolation oxide region. In this configuration the two inverters are constructed as two geometries in a single layer.
In one aspect, a latch comprises two back to back inverters formed on two separate semiconductor layers. A high performance inverter is constructed on a high mobility semiconductor layer. A lower performance inverter is constructed in a lower mobility semiconductor layer. The two inverters are stacked one above the other to reduce the latch area, and connected back-to-back to provide the necessary feed-back. This arrangement allows fast access times at a reduced foot-print for high density memory. A semiconductor latch for integrated circuits is adapted to have a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage. The latch comprises a first and a second semiconductor layer, substantially different from each other; a first inverter having, a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said first semiconductor layer; and a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said second semiconductor layer.
In a second aspect, a latch comprises two lower performance back to back inverters formed on a second semiconductor thin film layer, substantially different from a first semiconductor substrate layer used for logic transistor construction. This latch is stacked above the logic circuitry for slow memory applications with no penalty on Silicon area and cost. A semiconductor latch for integrated circuits is adapted to have a first supply voltage and a second supply voltage substantially at a lower voltage level than said first supply voltage. The latch comprises a semiconductor thin film layer, substantially different from a semiconductor substrate layer; a first inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said semiconductor thin film layer; and a second inverter having a first conducting path coupled to said first supply voltage and an output, and a second conducting path coupled to said second supply voltage and said output, and said first and second conducting paths constructed in said semiconductor thin film layer.
Advantages of the invention may include one or more of the following. A smaller area latch is constructed in one semiconductor geometry by eliminating the latch-up spacing requirement. The latch is constructed in a second semiconductor plane, different from a first plane used for logic transistor construction. The latch is embedded above logic transistors taking no effective Silicon area. The latch contains all MOSFET transistors. The latch contains all Gated-FET transistors as discussed in xe2x80x9cInsulated-Gate Field-Effect Thin Film Transistorsxe2x80x9d. The latch contains mixed MOSFET and Gated-FET transistors. The transistors are fully depleted thin film devices. The transistors have fully salicided source and drain regions adjacent to lightly doped tip regions to reduce source and drain resistance. A smaller area SRAM cell is constructed with a latch having a smaller area. A split level SRAM cell is constructed with a split level latch: one inverter in a first plane, and a second inverter in a second plane. An SRAM cell has a first inverter in the substrate layer, and a second inverter in a thin film layer substantially above said first inverter. The first semiconductor layer is single crystal Silicon. The substrate layer has high performance strong transistors. The SRAM cell has one or more access transistors to access memory data. Access device for high performance inverter is also high performance. The high performance inverter is fabricated as SOI inverter, or thinned down SOI inverter. The second thin film layer is polycrystalline Silicon. The poly-Silicon inverter is low performance, and only acts to hold the data state in the high performance inverter. The access device for low performance inverter is also low performance. A latch is constructed with all thin film semiconductor transistors. The thin film is poly-crystalline Silicon containing weak thin film transistors (TFT). TFT layer is stacked above a logic layer and takes no extra Silicon real estate. TFT memory blocks are vertically integrated to a logic process for Field Programmable Gate Array (FPGA) or Field Programmable Video Graphics (FPVG) applications. The split SRAM memory cells are used for high density stand alone and embedded memory applications. The split SRAM memory cells are used for high memory content Look-Up-Table applications.
Advantages of the invention may further include one or more of the following. The latch and SRAM memory cells consume less Silicon. Large memory blocks have a lower cost in spite of the added wafer cost for process complexity. The split level memory cells have very high performance similar to full CMOS SRAM memory. The split level memory cells have very low power consumption similar to full CMOS SRAM memory. High performance new SRAM cells have lower complexity single ended sensing circuitry. New cells are more stable and have better noise immunity. New SRAM cells can be used for very fast access embedded memory applications. Thinned down SOI memory has very high performance. Thin down split SRAM SOI memory allows very high memory densities. Memory cells contain complementary transistors with no stand-by power consumption. The complete memory cell in TFT layers can be stacked above logic transistors. This leads to buried memory configuration. Buried memory has reduced Silicon area and lower cost. Full TFT SRAM memory cells have slower access times, and useful for slow configuration memory applications. Both programmable products can be subsequently mapped to ASICs (Application Specific Integrated Circuit). The SRAM memory is used for prototyping and low volume production, while hard wired ASICs are used for high volume production. The invention thus provides an attractive solution for two separate industries: (i) very high density stand alone or embedded memory for low power, fast access applications and (ii) high-density, buried memory for low cost, slow access programmable applications.