1. Field of the Invention
This invention relates to a video signal processing apparatus and more particularly to an apparatus which processes an interlaced video signal.
2. Description of the Related Art
The apparatuses of the kind mentioned above include, for example, a rotary two-head helical scanning type video tape recorder (hereinafter referred to as VTR) which is designed for home use. The home VTR of this kind is capable of reproducing a still picture by repeatedly tracing the surface of a video tape with a rotary reproducing head with the tape brought to a stop.
However, if the still picture reproduction is performed with the tape simply brought to a stop, the reproduced signal deteriorates in its S/N ratio and hardly gives an adequate still picture, because the tracing locus of the reproducing head is not in parallel to the recording track formed on the tape. Then, noise bars would appear on the reproduced picture plane if the pausing position of the tape is not accurately controlled. Further, in case where the VTR is arranged to perform the so-called azimuth recording with two rotary heads, it is possible to reproduce only the records that are in tracks having one of different azimuth angles. In that case, a still picture thus reproduced is formed alternately by images having a time difference corresponding to one field between them. Such a reproduced picture is hardly presentable as a still picture.
It is, therefore, practiced to have a reproducing head specially arranged for reproduction of a still picture to repeatedly reproduce the record of one and the same track. This method, however, also requires accurate control over the pausing position of the tape. Even if the position control can be accurately accomplished, however, the S/N ratio of signal parts reproduced from the two end parts of the track is inevitably deteriorated to a greater degree than in the standard mode of reproduction (motion picture reproduction). Besides, it is necessary to take into consideration an adverse effect of a difference in relative speeds of the head and the tape between recording and reproduction.
To solve this problem, a VTR which has been recently announced is arranged to obtain a still picture by writing into a memory one field portion of a video signal reproduced during standard reproduction and by repeatedly reading it out from the memory.
This VTR is arranged as follows: FIG. 1 of the accompanying drawings shows in outline the arrangement of the reproducing system of the VTR. FIGS. 2(a-i) to 2(d-iii) show in a timing chart the operation of the various parts of the FIG. 1. Rotary heads HA and HB are arranged to revolve at a phase difference of 180 degrees along the outer circumferential surface of a rotary head cylinder with a tape wrapped at least 180 degrees around the cylinder. These heads HA and HB have different azimuth angles from each other. Another head 2 is arranged to detect the rotation phases of the heads HA and HB and to produce a rectangular wave signal (hereinafter referred to as PG signal) as shown in FIG. 2(a-l). If the recorded signal is, for example, an NTSC TV signal, the PG signal is of 30 Hz. A head switch 4 is controlled by the PG signal. A reproduced video signal is continuously obtained from the head switch 4. The reproduced video signal is supplied to a Y/C separation circuit 6 which is arranged to separate the signal into a frequency modulated luminance signal (hereinafter referred to as a signal FM-Y) and a low-band converted carrier chrominance signal (hereinafter referred to as a low-band signal C). The signal FM-Y which is separated by the circuit 6 is supplied to a luminance signal processing circuit 8 to undergo such processes as frequency demodulation, etc. The low-band signal C is supplied to a chrominance signal processing circuit 10 to undergo such processes as frequency conversion, etc. The base-band luminance signal and the carrier chrominance signal thus obtained are mixed together at a mixer 12 to obtain a reproduced composite color video signal. In carrying out a standard reproducing operation which is motion picture reproduction, the connecting position of a switch 14 is on one side N thereof. Then, the output of the mixer 12 is produced via the switch 14 to an output terminal 16.
In the case of a still picture reproduction, the VTR operates as follows: A terminal 18 is arranged to receive a still instruction signal the level of which becomes high when an instruction is given for still picture reproduction by means of an operation part which is not shown during the standard reproduction. Another terminal 20 is arranged to receive a clock signal of a color subcarrier frequency (hereinafter referred to as a frequency fsc) obtained by means of, for example, the chrominance signal processing circuit 10, etc. The frequency of the clock signal thus received is stepped up by a PLL 22 into driving pulses to be used for driving a timing controller 26. Meanwhile, a clock signal which is obtained by frequency-dividing the output of the PLL 22 by a frequency divider 24 is also supplied to the timing controller 26. The timing controller 26 is arranged to control the timing of operation of the various parts on the basis of these clock signals.
D-flip-flops (hereinafter referred to as D-FFs) 28 and 30 are arranged such that. The above stated PG signal is supplied to the terminal D of the D-FF 28 and the Q output of the D-FF 28 is supplied to the terminal D of the D-FF 30 respectively. To the clock terminals of the D-FFs 28 and 30 is supplied from the timing controller 26 a clock signal which is of a sufficiently high frequency, such as the frequency fsc. Pulses produced from the Q terminal of the D-FF 30 are of an inverse phase and a delay of 1/fsc relative to that of pulses produced from the Q terminal of the D-FF 28. Therefore, when these pulses are supplied to an exclusive OR (EXOR) circuit 32, low level pulses are obtained only at the edge parts of the PG signal. Further, the logical sum of the output of the EXOR circuit 32 and the PG signal is obtained at an OR gate 34. By this, there is obtained a pulse signal (hereinafter referred to as frame pulse) which is of a two-field period and is at a low level only at the fall edge of the PG signal.
The still instruction signal supplied to the terminal 18 is synchronized at a D-FF 36 with the frame pulse produced from the OR gate 34. A monostable multivibrator (hereinafter referred to as MM) 38 is triggered by the rise of the Q output of the D-FF 36. Then, the MM 38 produces a one-shot pulse. The one-shot pulse produced from the MM 38 sets a set-reset flip-flop (hereinafter referred to as SR-FF) 40. The Q output of the SR-FF 40 is arranged to effect switching between writing and reading actions on a memory 42. In other words, the memory 42 is arranged to be rendered writable at a fall of the PG signal immediately after the level of the still instruction signal becomes high.
The frame pulse which is produced from the OR gate 34 is arranged to be supplied via an AND gate 44 to the reset terminal RST of an address counter 46 and also to the clear terminal CL of a 263 H detection circuit 48 which will be described later herein. By this, the address counter 46 and the circuit 48 are set into their initial states respectively.
Writing into the memory 42 is performed in the following manner: The composite color video signal which is produced from the mixer 12 is supplied to a front low-pass filter (LPF) 50 to have the frequency band thereof limited there. After the LPF 50, the composite video signal is digitized by an analog-to-digital (A/D) converter 52. Input-output interfaces (IFs) 54 and 56 are arranged to control the data transfer speed, the transfer timing, the mode, etc. of the memory 42.
An NTSC signal consists of 262.5 horizontal scanning lines for one field. Assuming that the video signal is of the NTSC color system, if the memory 42 is simply arranged to store a 262.5 horizontal scanning line portion of the video signal, repeated reading of the stored signal from the memory 42 would bring about a skew as shown in FIGS. 2(a-i) to 2(b-iii). FIGS. 2(a-ii) and 2(a-iii) show the vertical synchronizing signal (hereinafter referred to as a VD signal) and the horizontal synchronizing signal (hereinafter referred to as an HD signal), respectively, of a composite color TV signal supplied to the LPF 50. FIG. 2(b-i) shows a writing/reading change-over signal to be obtained in case that the 262.5 H portion of the signal is to be stored in synchronism with the PG signal (FIG. 2(a-i)). FIGS. 2(b-ii) and 2(b-iii) show the VD and HD signals of a signal obtained by writing and reading in and from the memory 42 in this case. As shown, there arises a skew of 1/2 H.
In view of this, a period has been set for writing into the memory 42 at 263 H and to alternately read out for a period of 262 H and for a period of 263 H. FIG. 2(c-i) shows a writing/reading change-over signal which is arranged on the above stated concept. FIGS. 2(c-ii) and 2(c-iii) respectively show the VD and HD signals obtained in this instance.
In the case of FIG. 1, the writing period is set at 263 H according to the above stated method. When the address counter 46 counts the addresses for the period of 263 H, the 263 H detection circuit 48 produces a pulse, which resets the SR-FF 40 and also resets the address counter 46. As a result, the level of the Q output of SR-FF 40 becomes high. Then, data stored at the address of the memory 42 designated by the address counter 46 is read out.
The data read out from the memory 42 is supplied via the IF 56 to a digital-to-analog (D/A) converter 58 to be converted into an analog signal. The analog signal thus obtained is supplied to a switch terminal on one side M of the switch 14 after the band thereof is limited by a rear LPF 60. The switch 14 is controlled by the output of an AND gate 62 which is arranged to obtain a logical product of the Q output of the D-FF 36 and the Q output of the SR-FF 40. When the reading action on the memory 42 begins, the connecting position of the switch 14 is shifted to the side M thereof. Further, the A/D converter 52, the IFs 54 and 56 and the D/A converter 58 are under the control of clock pulses produced from the timing controller 26.
After the lapse of the period of 262 H following the reading action on the memory 42, a frame pulse is supplied from the OR gate 34 to the reset terminal of the address counter 46 to reset the reading address of the memory 42. For a next field, the address counter 46 operates until a pulse is produced from the 263 H detection circuit 48. Then, data for 263 H is read out from the memory 42. After that, data for 262 H and data for 263 H are alternately read out until the level of the still instruction signal becomes low. Then, the connecting position of the switch 14 is shifted to the other side N thereof and the VTR comes back to the standard reproduction mode thereof by a frame pulse first produced after the level of the still instruction signal is shifted to the low level.
The VTR arranged in the above stated manner is capable of giving an adequate still picture having no skew. However, in case that a still picture is to be appreciated over a long period of time with this VTR, the rotary head traces the same part of the tape for a long period of time and tends to damage the tape. If the rotary head is brought to a stop to avoid the trouble, the video signal to be reproduced from the tape cannot be synchronized any longer with the still picture signal being produced and, under such a condition, an output image would be greatly disturbed at the time of change-over from the still picture reproducing state to a standard reproducing state.
Further, in case where a video signal having such VD and HD signals that are shown in FIGS. 2(c-ii) and 2(c-iii) is supplied to an image receiver, the presence of the VD signal at every period of 262 H or 263 H causes the horizontal scanning lines of the first and second fields to appear in the same position on the picture plane. In case that the image receiver has a large picture plane, a still picture thus obtained becomes excessively coarse as the horizontal scanning lines are spaced too much.
To solve this problem, the video signal has inserted therein such pulses (artificial VD signal) which are separately generated in a cycle of 262.5 H. However, this solution necessitates an artificial VD signal insertion circuit to be disposed behind the memory and is not desirable as it causes an increase in the hardware arrangement of the VTR.