The present invention relates to a high-speed semiconductor memory device, and more particularly, to a semiconductor memory device and a method for transferring data at high speed in data read and write operations.
In a system including a plurality of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells corresponding to addresses inputted together with the data.
As the operating speed of the system is increasing and the semiconductor integrated circuit (IC) technology is advanced, the semiconductor memory device is required to input/output data at higher speed. In order for a stable and high-speed operation of the semiconductor memory device, various circuits inside the semiconductor memory device should operate at high speed and transfer data or signals between circuits at high speed.
Practically, the operation of the semiconductor memory device is delayed by various control circuits for reading data from memory cells or transferring external data to selected memory cells, connection lines and connection circuits for transferring the data, and so on. Delay time occurs when the data outputted from the semiconductor memory device is transferred to a data requesting device of the system. In the system operating at high speed, delay time in transferring signals and data causes to deteriorate the performance of the system, and operation reliability and stability. Delay time in a data transfer path is variable depending on operation environment, which affects the operation of the semiconductor memory device.
Generally, the operation performance of the semiconductor memory device is further improved as a semiconductor memory device outputs data stored in memory cells in a read operation after a command is inputted from an external device. Particularly, in a semiconductor memory device used for graphic work in which a large amount of data is processed, a time required for outputting data becomes a critical performance index. In addition, when the data outputted from the semiconductor memory device are accurately transferred to various processors, the system effectively operates.
FIG. 1 is a timing diagram illustrating a read operation of a conventional semiconductor memory device. Specifically, FIG. 1 illustrates a data exchange process between a related art double data rate (DDR) semiconductor memory device for graphic work and a graphic processing unit (GPU) for processing image data.
Referring to FIG. 1, in the read operation, the DDR semiconductor memory device outputs data DRAM DATA corresponding to a request of the GPU in synchronization with a rising edge and a falling edge of a memory clock DRAM_CLK. The GPU reads a data value received at a rising edge and a falling edge of a graphic clock GPU_CLK. In this case, when the rising edge and the falling edge of the graphic clock GPU_CLK exist in an effective window of data outputted from the DDR semiconductor memory device, the GPU can receive the data.
In a data transfer process, a data delay time from t1 to t2 occurs due to physical factors between the DDR semiconductor memory device and the GPU. In the DDR semiconductor memory device, data is outputted in synchronization with each edge of a clock, but in the GPU, the data can be accurately received in the case where an edge of a clock is positioned in an effective window of the data and more precisely at the center of the effective window. Accordingly, an optimal phase difference between the memory clock DRAM_CLK and the graphic clock GPU_CLK becomes 0.5×UI, wherein the UI indicates the effective window. In this case, a data delay time becomes t2−t1+0.5×UI.
As illustrated in FIG. 1, the DDR semiconductor memory device operates in synchronization with the memory clock DRAM_CLK, and the GPU operates in synchronization with the graphic clock GPU_CLK having a phase different from that of the memory clock DRAM_CLK. Like this, when a clock environment of a semiconductor memory device is different from a clock environment of a graphic processing unit, a clock signal (i.e., data trigger signal) for recognizing transferred data is mismatched to a clock signal for the transferred data.
In order to overcome the mismatch, a semiconductor memory device or a system including the semiconductor memory device presets a delay time between the semiconductor memory device and a GPU. For this purpose, separate clocks such as a read strobe signal RDQS and a write strobe signal WDQS are used. Also, specifications of the semiconductor memory device, such as an output access time tAC and a DQS output access time tDQSCK based on a reference clock, or a time difference tDQSQ between an edge of a data strobe signal and an edge of a data output signal, are used.
However, since the above-described specifications are set to preset fixed values stored in the semiconductor memory device and the GPU, it is difficult to ensure reliable data transfer when environments of an actual implemented system change. Particularly, in a high-speed to system, the size of an effective data window is very small and but the amount of data existing in the channel between the semiconductor memory device and the GPU is very large, so that it is difficult to ensure accurate data transfer.
Recently, in order to overcome a limitation related to ensure the accurate data transfer, using a data training, data can be accurately transferred between the semiconductor memory device and the GPU. The data training means a technology that adjusts a skew between data by using a preset data pattern in the semiconductor memory device and a controller in order to transfer data accurately which are required for a read operation and a write operation. For example, specifications for the performance of a DDRIII semiconductor memory device includes a WRITE leveling technology for compensating a time difference between a clock signal HCLK and a DQS due to delay time effect. Programmable delay elements are used for providing data strobe signals in order to satisfy timing requirements of the semiconductor memory device, which include tDQSS, tDSS and tDSH, by compensating the skew between a strobe signal and a clock signal using the WRITE leveling technology.
Recently proposed semiconductor memory devices for graphic work are designed to transfer data at rates higher than 4 Gbps, and in order to ensure high-speed data transfer, the specifications of the semiconductor memory device includes the data training.