The present invention relates to phase-locked loop circuits for communication system of digital data transmission in which a phase deviation is detected and removed from a received signal having been phase deviated by phase errors generated due to the frequency off-set or signal rise in burst transmission, and more particularly to a phase-locked loop circuit, which can be used together with a signal estimator for correctly detecting and correcting a phase deviation in even a received signal which has been extremely deteriorated due to a transmission line distortion, and can also ensure stable operation even in such a bad receiving circumstances that the signal estimator makes erroneous signal estimation.
A phase-locked loop of the pertaining kind, is disclosed in, for instance, Japanese Patent Application No. 9-135454 prior to the present application. In addition, as an adaptive maximum likelihood sequence estimator for correcting the phase variation over a wide frequency off-set range, has been proposed one, which comprises a phase rotator for rotating the phase of a received signal to correct phase variations of the received signal, a Viterbi algorithm processor, a transmission line estimator, and a phase estimator for estimating the phase and providing the estimated phase value to the phase rotator, and in which the phase variation is compensated by the phase estimator and the phase rotator, while at the same time an integrating means in loop filter corrects the phase variation due to frequency off-set or phase jitter using a second-degree phase-locked loop, thereby compensating constant phase rotation due to the frequency off-set.
FIG. 16 shows an example of the construction of a prior art phase estimator with a phase-locked loop. Referring to the Figure, a DDFSE (delayed decision feedback sequence estimator) 303 estimates a transmitted signal series from the received signal which has been distorted. A replica generator 305 generates a replica of the received signal through convolution of a preliminarily obtained transmission line impulse response and a series signal estimated by the DDFSE 303. In this prior art signal estimator, a phase deviation signal for phase control in phase-locked loop computation is generated by comparing the phases of a replica signal obtained from an estimation signal of the DDFSE 303 and the received signal. Thus, it is possible to obtain highly accurate phase error compensation even with a received signal containing a large transmission line distortion.
A delaying element 304 delays a received signal to make up for a delay generated in the DDFSE 303. It is thus possible to cause generation of the output signals of the replica generator 305 and the delaying element 304 at the same timing.
A phase detector 306 obtains a phase deviation between the output signals of the replica generator 305 and the delaying element 304. When a frequency off-set has been provided to the received signal at this time, the phase difference between the transmitted and received signals is varied with the lapse of time, and the phase deviation obtained in the phase detector 306 is also varied with the lapse of time. With a constant transmission line impulse response used for the computation, the replica generator 305 outputs a signal free from phase deviation unless an estimation error is generated in the DDFSE 303. However, the phase of the output of the delaying element 304 is changed instantaneously. Therefore, the phase detector 306 outputs a phase deviation between these signals.
The output signal of the phase detector 306 is bandwidth limited through a filter 307, and then inputted to a VCO 308. The output signal of the VCO 308 is supplied to a phase rotator 302 for phase rotation of the received signal. Control is thus provided in a direction of reducing a phase deviation appearing in the phase detector 306, and it is thus possible to absorb phase changes due to the frequency off-set or like cause.
The above prior art phase-locked loop circuit, however, has a problem that an estimation error generated during signal estimation in the DDFSE results in sudden deterioration of the phase tracking characteristic of the base-synchronized loop circuit. This is so because the generation of an estimation error in the DDFSE results in a wrong value of the replica signal itself which is generated by using the estimation signal, thus resulting in an extremely large phase deviation between the replica signal and the received signal.
More specifically, while in the absence of any estimation error in the DDFSE the phase deviation between the replica signal and the received signal is a very small value of 10 degrees or less, the generation of an estimation error results in the generation of a phase deviation of up to 180 degrees in the worst case. Therefore, with frequent generation of estimation errors in the DDFSE, the phase detector can not only correctly detect a phase deviation, but outputs a phase deviation signal of a greatly wrong value. In this case, the phase deviation of the signal inputted to the DDFSE is increased, causing the DDFSE to generate a further estimation error. In such a vicious circle, the phase deviation between the replica signal and the received signal is further increased, thus ultimately resulting in dispersion.
As a measure for preventing such unsteadiness, it is necessary to delay the response of the phase-locked loop, thus providing for difficult dispersion of the phase synchronization as a result of the provision of a wrong phase deviation signal. By delaying the response of the phase-locked loop, however, the intrinsic phase tracking capacity itself is reduced, thus narrowing the scope of application.
The present invention was made in view of the above problems, and it has an object of providing, in a system for estimating a received signal having received a great transmission line distortion in a DDFSE (delayed decision feedback sequence estimator) or an MLSE (maximum likelihood sequence estimator), a signal estimation circuit with a phase-locked loop, in which the phase-locked loop circuit can highly accurately and fast tracking and correct phase changes due to the frequency off-set or the like even in such a bad environment that the DDFSE or the MLSE may do wrong signal estimation.
According to an aspect of the present invention, there is provided a signal estimator comprising a phase-synchronized rotating means for rotating the phase of a received signal, a maximum likelihood sequence estimator for estimating a received signal, a replica generating means for generating a replica signal of an input signal to the maximum likelihood sequence estimator, a delaying means for causing delays of the received signal in the maximum likelihood sequence estimator and the replica generating means, a phase detecting means for detecting a phase difference between the signal from the delay means and the replica signal from the replica generating means, a low-pass filter and a voltage-controlled oscillating means, the phase rotating means rotating the phase of the received signal according to the output of the voltage-controlled oscillating means, wherein a limiter means is provided between the phase detecting means and the filter, the limiter means being operable to limit the output of the phase detecting means to amplitude limit a phase difference signal obtained from the received signal and the replica signal, thereby suppressing phase deviations to be within a predetermined value.
According to the present invention, the phase deviation is held within a predetermined value by amplitude limiting a phase deviation signal obtained from a received signal and a replica signal. Thus, the phase deviation signal is free from a large error irrespective of generation of an estimation error in the MLSE or DDFSE. The control of the phase-locked loop is thus stabilized, thus obtaining the phase tracking with less dispersion. Thus, even in a bad environment giving rise to an estimation error in the MLSE or DDFSE, it is possible to evade such bad cycles as to further deteriorate the estimation capacity of the MLSE or DDFSE due to capacity deterioration of the phase-locked loop.
According to another aspect of the present invention, there is provided a signal estimator comprising a phase-synchronized rotating means for rotating the phase of a received signal, a delayed decision feedback sequence estimator for estimating a received signal, a replica generating means for generating a replica signal of an input signal to the delayed decision feedback sequence estimator, a delaying means for causing delays of the received signal in the delayed decision feedback sequence estimator and the replica generating means, a phase detecting means for detecting a phase difference between the signal from the delay means and the replica signal from the replica generating means, a low-pass filter and a voltage-controlled oscillating means, the phase rotating means rotating the phase of the received signal according to the output of the voltage-controlled oscillating means, wherein a limiter means is provided between the phase detecting means and the filter, the limiter means being operable to limit the output of the phase detecting means to amplitude limit a phase difference signal obtained from the received signal and the replica signal, thereby suppressing phase deviations to be within a predetermined value.
The limiter means includes an overflow detecting means for detecting an overflow of the input signal, an underflow detecting means for detecting an underflow of the input signal, and a data correcting means for receiving the input signal and detection signals from the overflow and underflow detecting means; the data correcting means outputting a predetermined first value irrespective of the value of the input signal upon detection of an overflow by the overflow detecting means, and also directly outputting the input signal when neither an overflow nor an underflow is detected by the overflow or underflow detecting means and outputting a predetermined second value irrespective of the value of the input signal upon detection of an underflow by the underflow detecting means.
The phase detecting means includes two multiplying means for obtaining rxpy and rypx with respect to the output (r=rx+jry, j2=xe2x88x921) of the delay means and the output (p=px+jpy) of the replica generating means, and an adding means for adding the product results of the two multiplying means.
According to other aspect of the present invention, there is provided a system for receiving, in digital communication, a received signal with the frequency off-set thereof having received distortion due to phase rotation and transmission line distortion, estimating the received signal by correcting the frequency offset to output the digital signal, a signal estimator with phase-locked loop comprising: a voltage-controlled oscillating means; a phase-rotating means for causing rotation of the phase of the received signal according to the phase of the output signal of the voltage-controlled oscillating means; a maximum likelihood series estimating means for estimating the received signal by receiving the output signal of the phase rotating means; a replica generating means for generating a replica signal of the input signal to the maximum likelihood series estimating means by receiving the estimation result; a delaying means for receiving the output signal of the phase rotating means and generating a delay corresponding to a delay time until the maximum likelihood series estimating means outputs the result of estimation; a phase detecting means for obtaining the phase difference between the output signal of the replica generating means and the output signal of the delaying means; a limiter for receiving the output signal of the phase detecting means and holding the output signal at a predetermined value by clipping the output signal when the amplitude of the output signal exceeds a predetermined range; and a filter for frequency band limiting the output signal of the limiter; the voltage-controlled oscillating means generating a sinusoidal wave at a frequency proportional to the output of the filter.
According to still other aspect of the present invention, there is provided a system for receiving, in digital communication, a received signal with the frequency off-set thereof having received distortion due to phase rotation and transmission line distortion, estimating the received signal by correcting the frequency offset to output the digital signal, a signal estimator with phase-locked loop comprising: a voltage-controlled oscillating means; a phase-rotating means for causing rotation of the phase of the received signal according to the phase of the output signal of the voltage-controlled oscillating means; a delay determination feedback series estimating means for estimating the received signal by receiving the output signal of the phase rotating means; a replica generating means for generating a replica signal of the input signal to the delay determination feedback series estimating means by receiving the estimation result; a delaying means for receiving the output signal of the phase rotating means and generating a delay corresponding to a delay time until the delay determination feedback series estimating means outputs the result of estimation; a phase detecting means for obtaining the phase difference between the output signal of the replica generating means and the output signal of the delaying means; a limiter for receiving the output signal of the phase detecting means and holding the output signal at a predetermined value by clipping the output signal when the amplitude of the output signal exceeds a predetermined range; and a filter for frequency band limiting the output signal of the limiter; the voltage-controlled oscillating means generating a sinusoidal wave at a frequency proportional to the output of the filter.
According to further aspect of the present invention, there is provided a signal estimator with a phase-locked loop comprising: an estimator for estimating a transmitted signal series from a received signal; a replica generator for generating a replica of the received signal through convolution of a preliminarily obtained transmission line impulse response and a series signal estimated by the estimator; a delaying element for delaying the received signal to make up for a delay generated in the estimator; a phase detector for obtaining a phase deviation between the output signals of the replica generator and the delaying element; a limiter for limiting the output of the phase detector to amplitude limit within a predetermined value; a filter for making bandwidth limitation of output signal of the limiter; a voltage-controlled oscillator for generating a signal of frequency controlled by the output of the filter; a phase rotator for making phase rotation of the received signal on the basis of the output of a voltage-controlled oscillator in a direction of reducing a phase deviation appearing in the phase detector.
The estimator is a delayed decision feedback sequence estimator or a maximum likelihood sequence estimator.
According to still further aspect of the present invention, there is provided a signal estimating method with a phase-locked loop comprising: estimating a transmitted signal series from a received signal; generating a replica of the received signal through convolution of a preliminarily obtained transmission line impulse response and a series estimated signal; delaying the received signal to make up for a delay generated in the estimation; obtaining a phase deviation between the replica signal and the delaying element; limiting the obtained phase deviation to amplitude limit within a predetermined value; making bandwidth limitation of the limited phase deviation; generating a signal of frequency controlled by the signal obtained by the bandwidth limitation; making phase rotation of the received signal on the basis of the frequency controlled signal in a direction of reducing a phase deviation appearing in the phase detector.
The estimation is a executed by delay determination feedback series estimation or a maximum likelihood series estimation.