This invention relates to a simulator for simulating electromagnetic behaviour of an electrical conductor pattern. The invention also relates to a method of operating such a simulator in the design of a circuit and to design apparatus comprising such a simulator. The invention provides a simulator which can be used for the computer-aided design (CAD) of an integrated circuit of passive circuit components. The invention further relates to circuits designed using such a simulator and/or by such a method.
The paper "FASTERIX, an Environment for PCB simulation" by R du Cloux et al in the published papers of the 10th International Zurich Symposium on "Electromagnetic Compatibility 1993" pages 213 to 218 discloses a simulator for simulating electromagnetic behaviour of an electrical conductor pattern, by a process which includes the steps of:
creating a geometric model of a surface of the pattern, PA1 forming a matrix representation of Maxwell's equations with values associated with electric and magnetic field couplings between locations each of which is centred on a main geometrical element, which main geometrical elements are a subset of geometrical elements in the geometric model, and PA1 correlating values of matrix coefficients of the equations with coefficients of an admittance matrix representative of an equivalent circuit model for the pattern in terms of sub-circuits which are interconnected with each other via main nodes having a one-to-one correspondence with the main geometrical elements. PA1 a first branch includes a capacitor which models an electric field contribution, PA1 a second branch includes an inductor in series with a capacitor which together model a magnetic field contribution, and PA1 at least one further branch includes at least one resistor modelling a contribution to energy loss of the electric and magnetic fields, the energy loss occurring in dielectric material and conductive material of the integrated circuit. PA1 a first branch includes a capacitor which models an electric field contribution, PA1 a second branch includes an inductor in series with a capacitor which together model a magnetic field contribution, and PA1 at least one further branch includes at least one resistor modelling a contribution to energy loss of the electric and magnetic fields, the energy loss occurring in dielectric material and conductive material of the integrated circuit.
This type of simulator is herein designated as being of the REC type, which stands for Reduced Equivalent Circuit model type. Specific examples and uses of a REC type simulator for simulating a printed circuit board (PCB) layout are disclosed in this 1993 Zurich Symposium paper, in the papers "Reduced Equivalent Circuit Model for PCB" by R F Milsom et al., in Philips Journal of Research, Vol 48, Nos 1-2, 1994, pages 9 to 35, and "EMC Simulations and Measurements" by R du Cloux et al. in the published papers of the 11th International Zurich Symposium on "Electromagnetic Compatibility 1995", pages 185 to 190 and published European Patent Application EP-A-0 615 204 (and its United States equivalent 08/207,531). The whole contents of all these three papers and EP-A-0 615 204 are hereby incorporated herein as reference material. The REC type simulator is based on reducing an equivalent circuit model of the conductor pattern whose size corresponds to the number of geometrical elements, by correlating with an admittance matrix whose rank closely corresponds to the much smaller number of main geometrical elements (and main nodes). The smallest possible set of main geometrical elements is chosen to meet the criterion that the physical locations of the centres of the main elements are separated by no more than a short electrical length measured along conducting paths. This separation is a fraction (typically about 1/10th) of the wavelength (.lambda.min) corresponding to the maximum operating frequency of the circuit. Typically, when used to simulate a PCB layout whose dimensions are of the order of a wavelength or less at the operating frequency (such as in a mobile phone), an effective reduction of four orders of magnitude in computer processing time can be obtained by using this reduced equivalent circuit model, without substantial loss of model accuracy.
The REC type simulator embodiment described in EP-A-0 615 204 and the said three papers is suitable for simulating a PCB layout, which has one or more conductor patterns of a uniform conductivity and thickness which may be on one or more layers on or within an insulating substrate of uniform dielectric constant, and in which electromagnetic energy loss in the conductor patterns and in the dielectric substrate is low. Such a REC-type simulator package is available under the Trade Mark "FASTERIX" from product divisions and associated companies of Philips Electronics N.V. of Eindhoven, the Netherlands. The standard model in the current FASTERIX (Trade Mark) form of REC-type simulator is, however, very inaccurate when used directly for simulating a so-called "passive integration IC", which is an integrated circuit (i.e. IC) having thin-film passive circuit components. The predominant reasons for this inaccuracy are that energy losses are greater than in a PCB, the loss mechanisms are different, and the layer thicknesses differ much more widely.
Particular examples of Passive Integration ICs are disclosed in PCT Patent Applications International Publication Nos WO96/27210, WO95/05678 and WO94/20988 and in the article "Passive Schaltungen per Stempeldruck" in Elektronik 2/1995 pages 50-56. The whole contents of these patent applications and this article are hereby incorporated herein as reference material.