text: An emulator for the APEXC series has been developed by MESS. They describe its functioning as follows:
  <blockquote>The APEXC is an incredibly simple machine.
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  Instruction and data words are always 32 bits long. The processor uses integer arithmetic with 2's complement representation. Addresses are 10 bits long. The APEXC has no RAM, except for a 32-bit accumulator and a 32-bit data register (used along with the 32-bit accumulator to implement 64-bit shift instructions and hold the 64-bit result of a multiplication). Instructions and data are stored in two magnetic drums, for a total of 32 circular magnetic tracks of 32 words. Since the rotation rate is 3750rpm (62.5 rotations per second), the program execution speed can go from as high as the theoretical maximum of 1 kIPS to lower than 100IPS if program instructions and data are not contiguous. Nowadays, many say a pocket calculator is faster.
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  One oddity is that there is no program counter: each machine instruction includes the address of the next instruction. This design may sound weird, but it is the only way to achieve optimal performance with this cylinder-based memory.
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  The machine code is made of 15 instructions only, namely addition, subtraction, multiplication, load (3 variants), store (2 variants), conditional branch, right arithmetic bit shift, right bit rotation, punched-card input, punched-card output, machine stop, and bank-switching (which is never used on the APEXC, since it only has 1024 words of storage, and addresses are 10-bit-long). A so-called vector mode enables to repeat the same operation 32 times with 32 successive memory locations. Note the lack of bitwise and/or/xor and division. Also, note the lack of indirect addressing modes: dynamic modification of opcodes is the only way one may simulate it.
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  Another oddity is that the memory bus and the ALU are 1-bit-wide. There is a 64 kHz bit-clock and a 2 kHz word-clock, and each word memory and arithmetic operation is decomposed into 32 1-bit memory and arithmetic operations: this takes 32 bit cycles, for a total of 1 word cycle.
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  The processor is fairly efficient: most instructions take only 2 word cycles (1 for fetch, 1 for read operand and execute), with the exception of stores, shifts and multiplications. The APEXC CPU qualifies as RISC; there is no other adequate word.
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  Note there is no read-only memory (ROM), and therefore no bootstrap loader or default start-up program whatsoever.  It is believed that no executive or operating system was ever written for the APEXC, although there were subroutine libraries of sorts for common arithmetic, I/O and debug tasks. 
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  Operation of the machine is normally done through a control panel which allows the user to start, stop and resume the central processing unit, and to alter registers and memory when the CPU is stopped. When starting the machine, the address of the first instruction of the program to be executed must be entered in the control panel, then the run switch must be pressed. Most programs end with a stop instruction, which enables the operator to check the state of the machine, possibly run some post-mortem debugging procedures (a core dump routine is described in an APEXC programming book), then enter the address of another program and run it.
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  Two I/O devices were supported: a paper tape reader, and a paper tape puncher. The puncher output could be fed to a printer (teletyper) unit when desirable. Printer output is emulated and is displayed on screen. Tape input was either computer-generated by the APEXC, or hand-typed with a special 32-key keyboard (each tape row had 5 data holes (