text: reverting again to fig3 a switched capacitor adc is shown in the form of a multi - stage pipelined adc which includes multiple stages 11 through 12 each providing one or more bits of digital data to a digital correction circuit 15 which resolves the digital output from each stage into an overall digital output 16 that corresponds to an analog input 17 . each stage is a switched capacitor circuit operating in response to clock signal φ 1 for a sample phase and clock signal φ 2 for an amplifying phase , and comparing an analog voltage input to thresholds based on reference signals vrefp and vrefn so as to produce the digital outputs as well as a residual analog signal . the residual analog signal is provided as input to a subsequent stage . generator 20 provides phase and timing signals including clock signals φ 1 and φ 2 . generator 100 generates reference voltages vrefp and vrefn for use by each of multiple stages 11 through 12 . as shown in fig3 generator 100 generates reference voltage vrefp which is output from the source terminal of follower 132 which is connected between voltage supply v + and a current source 135 which in turn is connected to ground . follower 132 is driven in negative feedback relationship to vrefp through amplifier 134 whose reference is reference signal vref . the negative feedback leg for amplifier 134 is provided through filter 200 which is a switched capacitor filter operating in synchronism with phase and timing signals φ 1 and φ 2 so as to sample and filter reference voltage vrefp during known quiescent periods of the φ 1 sample phase and the φ 2 amplification phase . the gate of follower 132 is driven by current sink 300 , which accepts as its input the output from amplifier 134 . current sink 300 has an effective resistance which is low relative to other effective resistances in the circuit , thereby providing a low resistance path to sink current through follower 132 and thereby providing further immunization from the effects of high frequency noise . a voltage source for current sink 300 is provided by charge pump 400 which provides an effectively higher voltage to current sink 300 than is otherwise available through supply voltage v +. because of the higher effective voltage provided by charge pump 400 , it is possible to supply a reference voltage vrefp which is very close to supply voltage v +, in spite of the existence of voltage drop vgs across follower 132 . a complementary reference voltage generator 101 is provided for vrefn . circuit 101 involves components similar to switched capacitor filter 200 , current sink 300 and charge pump 400 , but operates those components in complementary relationship to those of generator 100 in correspondence to the reversed roles of φ 1 and φ 2 in the generator . each of the components of switched capacitor filter 200 , current sink 300 and charge pump 400 , are described in more detail below . fig4 a and 4b are views for explaining switched capacitor filter 200 , which provides a final and settled value of the reference vrefp signal for the feedback leg of amplifier 134 . one difference between fig4 a and 4b involves the presence in fig4 a of current sink 300 and charge pump 400 , whereas those components are absent in the view of fig4 b . these views are therefore intended to reinforce the notion that less than all three components ( i . e ., switched capacitor filter 200 , current sink 300 and charge pump 400 ) may be used in a generator for reference voltages , still with advantageous results . general operating features of a switched capacitor filter 200 will be described with reference to fig4 c through 4e . a source signal waveform is illustrated in each of these figures . as shown in fig4 c and 4d , a combination of switches φ 1 and φ 2 ( e . g ., switches driven by clocks φ 1 and φ 2 , respectively ) and capacitor cp 1 is modeled as a resistor r = 1 /( f · cp 1 ), where f is the frequency of the φ 1 and φ 2 clocks . when φ 1 and φ 2 are non - overlapping clocks ( e . g ., as shown in fig5 ), rcp 2 low pass feedback is provided by the configuration shown in fig4 e , with r = t / cp 1 = 1 /( fcp 1 ). fig4 e illustrates the settling of the source signal . in a situation where the source or excitation to such a switched capacitor filter is a glitch type signal for example v 1 , v 2 and v 3 , e . g ., every t / 2 seconds , as shown in fig4 f , the height of the initial glitch is signal dependent . hence , the average of this signal over one t period ( e . g ., low pass filtering the signal ) can vary depending on signal value . to minimize this dependence , φ 1 is preferably skewed such that the network rcp 2 does not see a glitch . instead the network preferably sees a partially settled signal . as a result , the signal dependency is reduced to the feedback amplifier . referring to fig4 a and 4b , filter 200 includes switched capacitors cp 1 and cp 2 switched in accordance with clock signals φa and φb . clock signals sa and φb are , in turn , timed relative to clock signal φ 1 ( sample ) and clock signal φ 2 ( amplify ) for adc 10 . preferably , the value of cp 2 is much greater than cp 1 . for example , cp 2 is advantageously ten times the size of cp 1 , such as cp 2 = 1 picofarad and cp 1 = 100 femtofarads . the purpose of this relationship is explained in more detail below . in general , ha is driven in synchronism with φ 2 ( amplification ), but only after a time t 1 from when amplification commences . the purpose for this delay t 1 is to ensure that vrefp has recovered to a relatively stable value after any initial noise spikes generated during initial stages of amplification by multiple stages 11 through 12 . when φa closes , cp 1 samples the value of vrefp , and holds that value after φa opens , during which time φb remains open . φb , on the other hand , is driven in synchronism with φ 1 ( sample ), or more precisely is driven out of synchronism with φa . φb closes while φa is open , thereby allowing any charge accumulated on capacitor cp 2 to mix with the charge newly acquired by capacitor cp 1 , which reflects the current voltage level of vrefp . it is the voltage accumulated on cp 2 that is provided to the negative feedback leg of amplifier 134 , and that value is maintained even after φb opens . fig5 is a timing diagram showing operation of switched capacitor filter 200 . as previously described , φ 1 and φ 2 are sample and amplification signals , respectively , φa is driven in synchronism with amplification phase φ 2 but commencing a short time t 1 after amplification begins , and φb is driven out of synchronism with φa and preferably in synchronism with φ 1 . immediately after amplification phase φ 2 commences , vrefp is subjected to a voltage spike which is quickly accommodated by follower 132 so as to return to a nominal value . t 1 is selected at design time so that it is timed for this nominal value . after time t 1 , φa closes thereby allowing the voltage on capacitor cp 1 ( designated as vcp 1 ) to follow any change in voltage level that might have occurred since the last closure of φa . φa then opens , followed by closure of φb , at which time the charge on capacitor cp 1 is mixed with the charge currently stored on capacitor cp 2 , thereby resulting in a change in voltage impressed across capacitor cp 2 ( designated as vcp 2 ). as further shown in fig5 the output value of vrefp follows the change in voltage across capacitor cp 2 by virtue of the negative feedback relationship caused by amplifier 134 . the value for capacitor cp 2 is much greater than that for cp 1 because the purpose of capacitor cp 1 is to sample the voltage of vrefp quickly , whereas the purpose of capacitor cp 2 is to accumulate charge over a longer period of time and to provide a reasonable damping effect with good response time . this relationship is obtained with the previously - described 10 : 1 ratio between capacitances for cp 2 and cp 1 . in a preferred embodiment , the pole ( p ) of the cp 2 capacitor is p ( cp 1 / cp 2 )· f , where f equals 125 mhz , cp 1 / cp 2 equals 0 . 1 , yielding a pole ( p ) of 12 . 5 mhz . because capacitor cp 2 is filtered from high frequency noise injected by adc 10 onto vrefp , noise rejection from amplifier 134 ( and onto follower 132 ) is greatly enhanced with respect to conventional feedback relationships . that noise rejection is reflected by the absence of any external capacitor such as cext found in conventional voltage generators , because such an external capacitor is ordinarily not required . charge pump 400 is provided so as to produce an artificially elevated voltage level for follower 134 , so that it is possible to run the reference voltages vrefp and vrefn very close to supply voltage v +, in spite of the presence of the voltage drop vgs from gate to source of follower 132 . fig6 shows the operational principles of charge pump 400 . as shown in fig6 the reference voltage vrefp for adc 10 is generated from the source terminal of follower 132 which is connected between supply voltage v + and a current source , which , in turn , is connected to ground . vrefp is monitored through a negative feedback relationship to amplifier 134 whose reference is provided by a reference voltage vret and whose feedback leg is connected to switched capacitor filter 200 . alternatively , switched capacitor filter 200 need not be supplied . the output of amplifier 134 is provided to the gate of sink 135 , whose source is connected to the gate of follower 132 . sink 135 is provided to allow a sink of current from drain to gate of follower 132 , thereby providing an effectively low impedance looking inwardly toward sink 135 and amplifier 134 . the source terminal of sink 135 is supplied by charge pump 400 . in principle , charge pump 400 operates to artificially elevate source voltage v + through capacitive switching and capacitive biasing , as explained more fully below . specifically , charge pump 400 takes voltage source v + through a current source and a biasing resistor r 3 and connects to two pairs of diagonally complementary switches s 1 and s 2 . these switches operate in connection with capacitors c 1 and c 1 a which are biased in synchronism with operation of switches s 1 and s 2 through biasing pulse vpulse . in more detail , and focusing on the left leg of charge pump 400 , when switch s 1 is closed and in the absence of a biasing pulse on vpulse , capacitor c 1 charges to the level of supply voltage v +. thereafter , switch s 1 closes and vpulse issues , thereby biasing the voltage at v 4 upwardly from v + by the value of vpulse . preferably , vpulse is the same value as supply voltage v +, thereby effectively doubling the voltage at v 4 . in synchronism with the issuance of vpulse , switch s 2 closes , thereby providing a voltage at v 5 which is elevated relative to supply voltage v +. diagonally complementary operations of switches s 1 and s 2 occur in the right leg of charge pump 400 . thus , while switch s 2 in the left leg is open , switch si in the right leg is closed , thereby providing a biased voltage previously - impressed on capacitor c 1 a to voltage v 5 . this diagonally - complementary operation of switches ensures that the voltage at v 5 is artificially elevated relative to supply voltage v +. in practice , of course , the biased voltages across capacitors c 1 and c 1 a are depleted by operation of current sink 135 . this is shown in the waveforms of fig7 . as shown in fig7 and as previously described , switches s 1 and s 2 operate complementarily , and vpulse operates in synchronism with closure of switch s 2 . during the time when switch s 1 is closed , the voltage from capacitor c 1 at v 4 charges to the value of supply voltage v +. thereafter , when switch s 1 opens and switch s 2 closes , and the voltage of capacitor c 1 is biased by issuance of vpulse , the voltage at v 4 increases to an elevated level relative to supply voltage v + as signified by v ++. operation of current sink 135 , however , discharges capacitor c 1 , thereby resulting in a charge / discharge cycle signified at v 5 in fig7 . notably , although the voltage v 5 does not maintain its highest level at v ++, it nevertheless maintains an average level which is elevated with respect to v +. because the voltage at v 5 is elevated relative to supply voltage v +, it is possible to operate vrefp at a value very close to supply voltage v +, in spite of the gate - to - source voltage drop vgs across follower 132 . in practice , however , it turns out to be difficult to build switches s 1 and s 2 because those switches must be turned on and off with voltages on the order of the supply voltage v +, yet must control voltages of values elevated with respect to v +. fig8 is a detailed schematic diagram for a practical implementation of charge pump 400 . as shown in fig8 and focusing on the left leg of charge pump 400 , switch s 1 is formed by fet 401 , and switch s 2 is formed by a back - to - back connection of fet 402 and pmosfet 404 . switch s 1 is driven inversely from vpulse through inverter 405 , and capacitor c 1 is biased in coordination with vpulse through dual inverters 406 . in addition , a helper capacitor c 3 is switched and biased in coordination with capacitor c 1 through fet 407 which operates as a switch . in operation of the circuitry shown in fig8 when switch s 1 closes , capacitor c 1 is charged to a voltage level corresponding to voltage supply v +. correspondingly , capacitor c 3 is charged through fet 407 . then , upon issuance of vpulse , switch s 1 opens and capacitor c 1 is biased by the value of vpulse . corresponding , fet 407 opens and capacitor c 3 is also biased by vpulse . closure of switch s 2 is a two - part operation . in the first part , since the value of v 4 is approximately twice the value of reference voltage v +, it is not possible for fet 402 to turn on and allow capacitor c 1 to discharge to current sink 135 . however , by virtue of the diagonally complementary operation of the switches in the right and left legs of charge pump 400 , fet 409 is currently on and voltage at v 4 is currently the same as supply voltage v +. the supply voltage drives the gate of pmosfet 404 which therefore turns on and allows discharge of capacitor c 1 to current sink 135 . as capacitor c 1 discharges , voltage at v 4 decreases and will eventually decrease to a point where pmos 404 can no longer remain on . however , by that time , the biased voltage from capacitor c 3 allows fet 402 to turn on , thereby maintaining an “ on ” state for switch s 2 and continuously allowing capacitor c 1 to discharge to sink 135 . as will be appreciated by one of ordinary skill in the art , capacitor c 2 and buffer 405 are configured as a level shifter . charge pump 400 can be modeled as a resistor rcp and a voltage supply that preferably supplies a voltage of approximately two times ( e . g ., 2v +) a voltage source ( e . g ., v +), as shown in fig1 . a voltage v 5 ( i . e ., v 5 = vrefp + vgs ) is established such that the current ( i ) through the charge pump ( e . g ., rcp ) can be approximated by i =( 2v +−( vrefp + vgs ))/ rcp . fig9 is a detailed schematic view showing current sink 300 . referring to the model shown in fig1 , the voltage v 5 varies continuously according to the charge / discharge cycle shown at vs in fig7 . accordingly , if charge pump 400 is used , it is advantageous also to utilize a current sink 300 so as to reject noise generated by charge pump 400 in accordance with action of its switches s 1 and s 2 . as shown in fig9 current sink 300 includes a low pass filter 301 which may include a simple rc circuit , which provides an input impedance ( as viewed from the charge pump ) that is low for high frequencies and higher for lower frequencies . the output of low pass filter 301 is provided to follower 132 . the input to low pass filter 301 is provided by a buffer composed of the combination of pets 302 , 303 and 304 and capacitors c 1 and c 2 . operation of this buffer is described in more detail below . generally speaking , however , the buffer provides a buffered output based on the output of amplifier 134 and further provides an input impedance ( as viewed from the charge pump ) which is low for low frequencies and higher for high frequencies , thereby acting as a current sink for the output of charge pump 400 . the buffer is referred to generally at reference numeral 310 . at low frequency operation of buffer 310 , the impedance thereof is influenced primarily by the transconductance of fet 302 since capacitor c 1 is essentially open . specifically , at low frequencies the impedance of buffer 310 is the inverse of the transconductance of fet 302 , divided by the gain provided by fets 303 and 304 . as a consequence , low frequency impedance of buffer 310 is lower than that of current sink 135 ( fig6 ) because of the amplifying effect of fets 303 and 304 . at mid to high frequencies , capacitor c 1 shorts . consequently , in the absence of low pass is filter 301 , the input impendence of buffer 310 would increase to approximately the inverse of the transconductance of fet 302 ( i . e ., not divided by the gain of fets 303 and 304 ). however , the presence of low pass filter 301 effectively ensures that at higher frequencies , the overall input impedance of current sink 300 remains low . by virtue of the coordination in input impedances of low pass filter 301 and buffer 310 , it is possible to ensure that the overall input impedance of current sink 300 remains low throughout the frequency range of interest . as a consequence , because the input impedance is low , noise from charge pump 400 is rejected efficiently . the invention has been described with respect to particular illustrative embodiments . it is to be understood that the invention is not limited to the above - described embodiments and that various changes and modifications may be made by those of ordinary skill in the art without departing from the spirit and scope of the invention .