text: in referring to fig1 there will first be described the block diagram of an installation wherein the present invention can be applied . this installation comprises two central units uca and ucb , several peripheral units dr1a to drmb associated in pairs , as well as units to be controlled such as og1 and ogn which can be the units of a telephone installation . the central units uca and ucb are connected by a transmission link ipl . in each central unit , at the end of that link ipl , there is provided a transmitter - receiver ( era , erb ) enabling transmitting and receiving any information to the other central unit . moreover , each central unit has control circuits ( cca , ccb ) and a memory ( ma , mb ) made up of memory cells . in that memory , two cells are assigned to each peripheral unit and they contain various information concerning that unit . for instance , in the central unit uca , the cells bpe0 and bt1a are assigned to the peripheral unit dr1a . namely , in cell bpe0 , the bit number 0 has a value 0 when no order has been transmitted to the peripheral unit dr1a . it is set on 1 when an order is transmitted to unit dr1a or when , unit uca not having access to unit dr1a , an order is transmitted to central unit ucb so that this latter might retransmit it to dr1b . bit number 2 has normally a value 0 ; it is set upon 1 when an order , received from central unit ucb , is transmitted to unit dr1a for execution . cell bt1a contains a bit number i which has for value 1 when the central unit uca has access to the peripheral unit dr1a , and which has for value 0 in the contrary case . memory ma also has , for each peripheral unit , cells such as nl0a for dr1a , containing orders to transmit to that unit . a peripheral unit , say for instance dr1a , has as a function to receive control orders from the central unit uca and to retransmit them to the controlled units og1 to ogn . it is duplicated by the peripheral unit dr1b which receives orders from the central unit ucb and retransmits them to those same controlled units og1 to ogn . two associated peripheral units such as dr1a and dr1b are connected by a link exm and possess a mutual exclusion system enabling the control of a controlled unit only for one central unit at a time . this system -- not shown in the figure -- is such that as long as the two peripheral units do not operate they would transmit at regular intervals impulses , so - called interruption signals , onto the central units uca and ucb respectively . immediately a peripheral unit , say for instance dr1a , receives an order from its central unit uca , it blocks the operation of the other peripheral unit dr1b and controls the execution of the order . when the order is executed , the peripheral unit dr1a sends an &# 34 ; end of job &# 34 ; signal to the central unit uca and releases the operation of the peripheral unit dr1b which will then be able to execute an order blocking the operation of the peripheral unit dr1a . the central unit uca undertakes every operation resulting from that &# 34 ; end of job &# 34 ; and transmits to unit dr1a a next order to be executed . unit dr1a will execute that order as soon as it is released . in referring to fig1 there will now be described the general operating process of an embodiment of the data transfer system to the present invention and more particularly the operating process of the central unit uca . it will first be assumed that the two central units uca and ucb have access to peripheral units dr1a and dr1b respectively . peripheral unit dr1a is released and has not received any order to be executed . central unit uca has in its memory cells , such as hl0a , at least one order to be executed . in memory ma the bits 0 and 2 of cell bpe0 have a value 0 , and , the bit i of bt1a has a value 1 . when central unit uca receives an interruption signal from peripheral unit dr1a , the control circuits cca will identify this unit . with the help of the obtained identity , they will read the contents of the memory cell bpe0 assigned to unit dr1a . they will test the value of bit 0 of bpe0 and will deduce therefrom -- since its value is 0 -- that unit dr1a has not any order to be executed . circuits cca will insure that there exists in a memory cell hl0a , and then will insure that bit i of bt1a has a value 1 signifying that unit uca has access to unit dr1a . they will then control the transmission of the order to peripheral unit dr1a and will set the bit 0 of bpe0 to the value 1 . when the transmitted order has been executed , unit dr1a transmits again an interruption signal to central unit uca . circuits cca identify the unit dr1a and consult , in the same way as before , the value of bit 0 of bpe0 . this value being 1 , the circuits cca deduce therefore that an order previously transmitted to dr1a has been executed . the circuits cca will then consult the value of bit 2 of bpe0 . this value being 0 , they will deduce that the executed order , transmitted by unit uca , was executed for its own account and not for the account of unit ucb . the contents of the cells , such as hl0a , is set up to date and bits 0 and 2 of bpe0 are restored to 0 . then , circuits cca will insure that there is in a memory cell hl0a an order to have executed by dr1a , and the operation proceeds as was described above . it will now be assumed that a central unit , say uca for instance , does not have access to its peripheral unit dr1a , bit i of bt1a has for value 0 . the central unit has , nevertheless , orders to transmit to dr1a . the control circuits cca generate at regular intervals , with the help of means which are not within the scope of the present invention , a signal which acts as an interruption signal . the same operating process as above is undertaken until the circuits cca consult the value of the bit i of bt1a . at that instant , this value being 0 , the circuits cca will control the transmission through link ipl , to central unit ucb , of a message identifying the peripheral unit ( dr1a ) and the order to be executed . central unit ucb receives this message . subsequently , in response to the reception of an interruption signal from unit dr1b , it will transmit the message to the peripheral dr1b as described above . moreover , circuits ccb set the bit 2 of bpe0 &# 39 ; to the value 1 . when unit dr1b finishes executing the order , it transmits an interruption signal to the central unit ucb . circuits ccb accomplish the same functions as those accomplished previously by circuits cca . however , since bit 2 of bpe0 &# 39 ; has for value 1 , they deduce that the executed order , transmitted by ucb , was executed for the account of uca . circuits ccb will then transmit to the central unit uca , through link ipl , a message identifying the order processed and indicating that it has been executed . unit ucb proceeds with the execution of another function . receiving this message , the central unit uca sets up to date the contents of its memory ma . it then examines whether it has another order to have executed by dr1a . if so , it transmits it as before to unit ucb ; if not , it goes on with the execution of another function . by referring to fig2 to 5 , the description will be given of a detailed embodiment of the system in the present invention . fig2 is a simplified diagram of the circuits of a central unit ( uca ) making it possible to set into operation the system in present invention . these circuits include a processing unit cca and a memory me . the processing unit cca comprises mainly : memory me is made up of memory cells provided for storing data ( cells bpe0 to hl0a ) and instructions ins1 to insn . each memory cell is provided for storing 16 bits numbered from 0 to 15 . there are available as many address cells bpe0 , bpe3 and hl0 as there are peripheral units such as dr1a . it will be assumed here that cells bpe0 , bpe3 and hl0 are assigned to the peripheral unit dr1a . address bpe0 corresponds to the identity of unit dr1a . addresses bpe3 and hl0 are obtained from bpe0 by the increase of one and four units respectively . in cell bpe0 , only bits 0 , 1 , 2 and 4 are used within the scope of the following description . bits 0 and 2 have the meanings which are provided above in the description of fig1 . bit 1 is set upon 1 when an order is put into waiting condition in memory me for the account of central unit ucb . bit 4 is set upon 1 when central unit uca transmits an order to central unit ucb which undertakes to retransmit it to the peripheral unit dr1b . cell bpe3 helps to store an order received from central unit ucb and to transmit to the peripheral unit dr1a . cell bt1a includes one bit per each peripheral unit ( dr1a ) associated with uca . a bit of value 1 means that the corresponding unit is accessible by central unit uca . suppose bit i corresponds to peripheral unit dr1a . cell bt1b also includes one bit per each peripheral unit ( dr1b ) associated with ucb . a bit of value 1 means that the corresponding unit is accessible by central unit ucb . suppose bit i corresponds to peripheral unit dr1b . cell hl0a belongs to a series of cells making up a waiting gueue wherein are stored the orders to be transmitted to a peripheral unit . cell hl0 contains the address of a cell such as hl0a . there are as many cells hl0 and waiting queues as there are peripheral units . since operation control of these waiting queues is currently well known , it will be considered here , for simplification purposes , that contents of hl0 are reduced by one unit each time that a cell from the waiting queues is read . when the waiting queues are empty , the content of hl0 is null . an instruction , say for instance ins1 , is made up of a 7 - bit instruction code ci and of a 9 - bit address ar . the program counter cp contains at every instant the address of an instruction cell ins1 to insn . under the control of circuits cc , the contents of cp are transferred into the register y and the instruction cell corresponding to this address is read . the instruction code ( ci ) is stored in register f and the address ( ar ) is stored in register m . the instruction code ci is decoded by decoder dec . this latter provides , in response , on its outputs , control signals for controlling various operations of the circuits cc and of the block add . it can control the transfer onto one of the registers a , b or x -- or the reverse -- of the contents of a cell in memory me whose address is deduced from the address contained in register m ( 9 bits address ar contained in the instruction ) by combination with the contents of the index register x . it can control the permutation of the contents of registers a and b . it can control the examination , by block add , of the value ( 0 or 1 ) of a bit of register a whose rank ( 0 to 15 ) is contained in the address part of the instruction , and , control according to the result of the examination , the stepping of counter cp onto a determined position . finally , it can enable detecting that the value of all the bits of register a is 0 , and , according to the case , also control the stepping of counter cp onto a determined position . the instructions stored in memory me are changed to ones after the others by the stepping of counter cp under the control of circuits cc at the execution of each one of them . nevertheless , some instructions can be skipped , by the stepping of counter cp , in the course of instructions having for purpose , as was already seen above , the examination of bits of register a . the flow - chart in fig4 illustrates the operating process of the circuits in fig3 . the indications noted on that flow - chart correspond each to a phase of operation in relation to information contained in the data memory cells and in the registers a , b and x . it is worth noting that an indication . contained in a rectangle corresponds to a phase of transfer - of - information between registers or between memories and registers ; or else , to a phase of modification of contents of the registers . an indication such as &# 34 ; bpe0 → x &# 34 ; means that the information bpe0 is stored in the register x . an indication &# 34 ;( bpe0 ) → a &# 34 ; means that the information contained in the address cell bpe0 is being read and then transferred into register a . and , inversely , the indication &# 34 ;( a ) → bpe0 &# 34 ; means that the information contained in register a is transferred into the address memory cell bpe0 . finally , the indication &# 34 ; 1 → ( a ) 0 &# 34 ; means that the bit 0 of register a is set to 1 . the indications contained in the diamond - shaped areas correspond to phases of examination of values of the bits of register a or of the entire value of the contents of register a . the indication &# 34 ;( a ) 0 = 1 ?&# 34 ;, for instance , means that there is being examined whether bit 0 of register a has 1 for value . the indication &# 34 ;( a ) = 0 ?&# 34 ; means that there is being examined whether the entire contents of register a has 0 for value . the circles containing reference numbers of same value are supposed to be linked one to another . from this flow - chart , it will therefore be easy to reconstitute all the instructions enabling the setting into operation of the system in fig1 . this flow - chart might also give place , in a wired embodiment , to a sequential stepping in the manner of counter cp and providing various control order to the circuits in fig2 . description will therefore be given here of the circuits in fig2 with reference mainly to the flow - chart in fig3 . it will be assumed initially that the two central units uca and ucb have access each to their respective peripheral units dr1a and dr1b ; bits i of cells bt1a and bt1b have therefore the value 1 . having access to unit dr1a , the central unit uca has not therefore transmitted any order to central unit ucb ; and bit 4 of cell bpe0 has therefore for value 0 . unit uca has not any order in course of excecution by dr1a ; bits 0 and 2 of cell bpe0 have the value 0 . finally , unit uca has no job awaiting for transmission to dr1a for the account of unit ucb and bit 1 of cell bpe0 has the value 0 . whereas , unit uca has an order waiting in a cell , such as hloa , of its queuing file ; the contents of hl0 are therefore different from 0 and has , for instance , the value hl0a . when unit uca receives an interruption signal int from the peripheral unit dr1a , the circuits cc will -- during the phase which is noted &# 34 ; interrupt &# 34 ; in fig3 and through means not shown in that figure -- control the identification of the calling peripheral unit . they deduce therefrom the address bpe0 of the memory cell bpe0 and store it in the register x wherein it will be held during the entire processing that follows ( phase &# 34 ; bpe0 → x &# 34 ;). under the control of circuits cc , the address memory cell bpe0 is read . its contents is stored in the register a ( phase &# 34 ;( bep0 ) → a &# 34 ;). the block add will then analyse the value of bit 0 of the information bpe0 contained in a ( phase &# 34 ;( a ) 0 = 1 ?&# 34 ;). since this bit has the value 0 , it means then that the calling peripheral unit dr1a had no order to execute . the interruption signal provided by the peripheral unit dr1a therefore simply corresponds to a request for a job . on the flow - chart in fig4 the operation of the system is routed onto the branch &# 34 ; no &# 34 ; originated from the diamond - shaped square containing the indication ( a ) 0 = 1 ?. contents hl0a of memory cell hl0 is then read and is stored into register a ( phase &# 34 ;( hl0 ) → a &# 34 ;). contents of register a is examined . its contents being different from zero , it means that a job is in awaitance in the unit uca for its own account . the operation of the system is routed onto branch &# 34 ; no &# 34 ; originated from the diamond - shaped square containing the indication ( a ) = 0 ?. the contents of a is transferred into b ( phase ( a ) → b ). then , the contents of b , reduced by one unit , is transferred into cell hl0 so as to provide the address of a next cell of the waiting queue ( phase ( b )- 1 → hl0 ). memory cell hl0a , whose address has been held in a , is read . its contents is transferred into a , and this is noted ( hl0a ) → a on the flow - chart of fig4 . the contents of a is then transferred into b . the contents of the memory cell bt1a is read and is stored into a . from the address bpe0 held in x , a bit of a determined rank -- say i for instance -- of the register a is being examined ( phase &# 34 ;( a ) i = 1 ?&# 34 ;). the central unit uca having access to the peripheral dr1a , the examined bit has therefore for value 1 . the operation is routed onto the branch &# 34 ; yes &# 34 ; of the diamond - shaped square &# 34 ;( a ) i = 1 ?&# 34 ; in fig4 . the contents of b ( order 0rd ) is transferred into a ( phase &# 34 ;( b ) → a &# 34 ;). at the next phase ( 0rd ), the order 0rd contained in a is sent upon link rd onto the peripheral dr1a . the contents of cell bpe0 is then read and stored into the register ( phase ( bpe0 ) → a ). the bit 0 of a is set upon 1 ( phase 1 → ( a ) 0 ). the contents of a is then stored again into bep0 ( phase &# 34 ;( a ) → bpe0 &# 34 ;). the central unit uca will then examine ( phase &# 34 ; interrupt &# 34 ;) whether there is another interruption originating from a peripheral unit . if so , the operation is resumed as from mark 1 in order to process this interruption . if not , the central unit is made available ( phase &# 34 ; end &# 34 ;) in order to accomplish any other function which is not within the scope of present invention . it will now be assumed that both central units uca and ucb having still access to their peripheral units dr1a and dr1b ; and , central unit uca , having sent an order to the peripheral unit dr1a , this latter will terminate the execution of the order . bits i of memory cells bt1a and bt1b have for value 1 . bit 0 of memory cell bpe0 has for value 1 . bits 1 , 2 and 4 of memory cell bpe0 have for value 0 . when peripheral unit dr1a has executed the order transmitted by unit uca , it transmits an interruption signal to unit uca . this latter identifies the peripheral unit dr1a and stores its identity bep0 into the register x ( mark 1 ). the contents of cell bpe0 is read and stored into a ( phase &# 34 ; bep0 a &# 34 ;). value of the bit 0 of a is examined ( phase &# 34 ;( a ) 0 = 1 ?&# 34 ;). this value being 1 , it means that the unit dr1a has had an order to execute ; this is therefore the case of an end of job of the peripheral unit dr1a , and the operation of the system is routed onto mark 6 . the bit 4 of register a is analysed ( phase &# 34 ;( a ) 4 = 1 ?&# 34 ;). its value being 0 , since the central unit uca has transmitted the preceding order to dr1a ( and not to central unit ucb ), the operation is routed onto branch &# 34 ; no &# 34 ; originated from the diamond - shaped square corresponding to the present phase . bit 2 of register a is then analysed ( phase &# 34 ;( a ) 2 = 1 ?&# 34 ;). its value being null since the central unit uca has transmitted the preceding order for its own account , the operation is routed onto the phase &# 34 ; t0rd &# 34 ; of the end of job processing during which the contents of memory me is set up to date in accordance with the executed order . then , bit 1 of register a is analysed ( phase &# 34 ;( a ) 1 = 1 ?). its value is supposed to be null , and this means that unit uca has no job in awaitance originating from unit ucb . the operation is routed onto mark 8 . contents of cell ( hl0 ) is read and is transferred into a ( phase &# 34 ;( hl0 ) → a &# 34 ;). contents of a is examined . if its contents is null , it means that unit uca has no job in awaitance to be executed by unit dr1a . the operation is routed onto mark 17 and proceeds by the searching of another interruption ( phase &# 34 ; interrupt &# 34 ;) as described above . if its value is different from 0 , it means that the unit uca has an order to be executed for unit dr1a and the contents of a provides the address of a cell such as hl0a . the operation is routed onto mark 3 and proceeds as described above . therefore , the operating process of the present system has been described above only in the case of a normal putting of the system into operation wherein both central units have each access to their peripheral units dr1a and dr1b . the central unit uca has transmitted an order to unit dr1a and has been informed that the order was executed . as from the above description , there will now be described process of operating cases resulting from the non - accessibility of a central unit to one of its peripheral units . first it will be assumed that a central unit , uca for instance , has not access to its peripheral unit dr1a and has nevertheless an order to transmit to it . the central unit ucb has access to its peripheral unit dr1b . bits i , of cells bt1a and bt1b , have therefore for value 0 and 1 respectively . when an interruption signal is originated in central unit uca , this latter accomplishes the same operation as that described above , either by considering that this is the case of a job request or that it is the case of an end of work ; and this , up to the mark 9 . indeed , at phase &# 34 ;( a ) i = 1 ?&# 34 ;, the value of bit i of register a ( bit i of contents of bt1a ) is being analysed . that value is 0 , the operation is therefore routed onto mark 4 . contents of bt1b is read and transferred into a ( phase &# 34 ;( bt1b → a &# 34 ;). the value of bit i of register a is analysed . its value is 1 since central unit ucb has access to unit dr1b . contents of bpe0 is then read ond transferred into a ( phase &# 34 ;( bpe0 ) → a &# 34 ;). bits 0 and 4 of register a are set upon 1 ( phase &# 34 ; 1 → ( a ) 0 ; 1 → ( a ) 4 ); this will indicate subsequently that an order was transmitted by unit uca to unit ucb . indeed , after transfer of the contents of a into cell bpe0 ( phase &# 34 ;( a ) → bpe0 &# 34 ;), a message , so - called message ipl51 , containing the identity ( bpe0 ) of peripheral unit dr1a and the order to be transmitted to it , is elaborated , and , is sent to central unit ucb through the link ipl ( phase &# 34 ; ipl51 &# 34 ;). operation of central unit uca returns then to mark 17 and proceeds as already described above . it will now be assumed that central unit ucb has not access to the peripheral unit dr1b and has nevertheless an order to transmit to it , whereas central unit uca has access to peripheral unit dr1a . bits i of memory cells bt1a and bt1b have for value 1 and 0 respectively . bit 1 of memory cell bpe0 has for value 1 . the value of the other bits of the memory cell bpe0 are of little importance within the scope of the present process - of - operation . central unit ucb performs the operation described above and transmits a message ipl51 to central unit uca . this message comprises the identity bpe0 of units dr1a and dr1b and an order 0rd to be transmitted . central unit uca receives the message ipl51 ( phase &# 34 ; ron ipl51 &# 34 ; on the flow - chart in fig5 ). the identity bpe0 is stored into register x and the order 0rd is stored into the memory cell bpe3 ( phase &# 34 ; bpe0 → x &# 34 ; and &# 34 ; 0rd → bpe3 &# 34 ;). contents of bpe0 is then read and transferred into register a ( phase &# 34 ; bpe0 → a &# 34 ;)). bit 1 of register a is set upon 1 ( phase &# 34 ; 1 → ( a ) 1 &# 34 ;) and this will indicate , subsequently , that an order is in awaitance for the account of unit ucb . contents of a is then transferred into cell bpe0 ( phase &# 34 ;( a ) → bpe0 &# 34 ;). moreover , bit 0 of register a is analysed . if its value is 1 , it means that central unit uca has provided an order to unit dr1a . it cannot therefore consider to provide another one as long as the preceding one is not terminated . central unit uca is made available for accomplishing another function . the sending of the order received from ucb will be described subsequently . if bit 0 of a has for value 0 , it means that the central unit has no job in course of execution by the peripheral dr1a . it will therefore proceed with the transmission of an order . operation of the system is resumed as from mark 1 in fig 3 , and , it reproduces itself as described above . it will be assumed , moreover , that unit uca has no order to send to unit dr1a . contents of hl0 is therefore null and , at phase &# 34 ;( a ) = 0 ?&# 34 ; in fig3 the operation is routed onto mark 5 . contents of bpe0 is transferred into a ( phase &# 34 ; bpe0 → a &# 34 ;). bit 1 of the read information is examined ( phase &# 34 ;( a ) 1 = 1 ?&# 34 ;). this value is 1 and the operation is routed onto branch &# 34 ; yes &# 34 ; of the diamond - shaped square corresponding to the present phase . moreover , if that value were 0 , unit uca would conclude that this is a case of incompatibility since , having brought about the course - of - processing of a job request it must evidently have at least one order in awaitance and unit uca would pass onto phase shoa , during which , this case is being processed by means outside the scope of present invention . being routed onto branch &# 34 ; yes &# 34 ; of the diamond - shaped square containing the indication &# 34 ;( a ) 1 = 1 ?&# 34 ;, at the next phase &# 34 ;( bt1a → a &# 34 ;, the contents of bt1a is transferred into register a . bit i of a is analysed . having assumed that unit uca has access to unit dr1a , the value of bit i is therefore 1 . it is worth noting , meanwhile , that if this value were 0 , the unit uca would not have access to the unit dr1a and the operation would be routed onto mark 17 and the searching of another interruption . in next phase &# 34 ;( bpe0 ) → a &# 34 ;, the contents of cell bpe0 is transferred into register a . then , in the register a , bits 0 and 2 receive each the value 1 ( phase &# 34 ; 1 → ( a ) 0 ; 1 → ( a ) 2 &# 34 ;). finally ( phase &# 34 ;( a ) → bpe0 &# 34 ;), the contents of register a is restored into cell bpe0 . the contents of cell bpe0 is thus set up to date so as to indicate subsequently that an order has been transmitted to unit dr1a ( 1 → ( a ) 0 ) for the account of the other central unit ucb ( 1 → ( a ) 2 ). indeed , order 0rd contained in cell bpe3 is transferred into register a ( phase &# 34 ;( bpe3 ) → a &# 34 ;); then is considered again the operating process described above during which the order is transmitted to unit dr1a . now will be considered the case where central unit ucb has not access to the peripheral unit dr1b . central unit uca has access to peripheral unit dr1a . the central unit ucb has transmitted an order to central unit uca which has retransmitted it to peripheral unit dr1a . bits i of the memory cell bt1a and bt1b have for value 1 and 0 respectively . bits 0 and 2 of memory cell bpe0 have for value 1 , and bit 4 has for value 0 . when unit dr1a has executed the order , it transmits an interruption signal to unit uca . receiving this signal , unit uca , after identification of unit dr1a , consults the value of bit 0 of cell bpe0 ( phase &# 34 ;( a ) 0 = 1 ?&# 34 ;); that value is 1 . unit uca therefore consults the value of bit 4 of the same information ( phase &# 34 ;( a ) 4 = 1 ?&# 34 ;) and ascertains that this value is 0 . it consults , at last , the value of bit 2 ( phase &# 34 ;( a ) 2 = 1 ?&# 34 ;) and ascertains that the value is 1 ; this causes the transmission of a message , so - called message ipl52 , to the central unit ucb ( phase &# 34 ; ipl52 &# 34 ;). this message comprises the identity bpe0 of unit dr1a and an indication of end - of - order execution . the contents of register a is restored to zero ( phase &# 34 ; 0 → a &# 34 ;) and the contents of register a is transferred into cell bpe0 , which amounts to setting to zero the contents of that cell . then , the operation proceeds onto the mark 8 as described above . now will be described the operating process proceeding from the reception of a message ipl52 in a central unit , say uca for instance . it is therefore assumed that unit uca , not having access to unit dr1a , has transmitted an order , through message ipl51 , to unit ucb . unit ucb has transmitted the order to unit dr1b which has executed it ; and unit ucb has then informed of it unit uca by the transmission of a message ipl52 . unit uca therefore receives a message ipl52 during the phase noted &# 34 ; ron ipl52 &# 34 ; in fig4 . the indication bpe0 contained in that message is stored into the register x . contents of a is restored to zero ( phase &# 34 ; 0 → a &# 34 ;) and then is transferred into cell bpe0 ( phase &# 34 ;( bpe0 ) → a &# 34 ;), and this cancels the contents of cell bpe0 . then , during a phase &# 34 ; i0rd &# 34 ; of end - of - work processing , the contents of memory me is set up to date according to the order executed through means not within the scope of present invention . contents of cell hl0 is then transferred into register a ( phase &# 34 ;( hl0 ) → a &# 34 ;); and the contents of register a is examined . if this contents is null , the unit uca has no order to have executed by unit dr1a . the operation is routed onto phase &# 34 ; end &# 34 ;, releasing the unit uca for the accomplishment of another function . if the contents of register a is not null , the operation is routed onto the mark 1 in fig3 and proceeds as desbrided above by taking into account that the contents of cell bpe0 is null . therefore it is seen that the information contained in the memory cell bpe0 , bpe3 , bt1a , bt1b , hl0 , hl0a , associated with means for setting up to date and means for analysing their respective contents , do indeed enable the central unit to control the execution of an order in a controlled unit even if it has not access to its intermediate peripheral unit . it is simply necessary that the other central unit should itself have access to its own peripheral unit . the information contained in the memory cells of a central unit ( uca ) and associated with a peripheral unit ( dr1a ) enable knowing , namely , whether this central unit ( uca ) as well as the other central unit ( ucb ) have access to their respective peripheral units ( dr1a and dr1b ) and , whether an order received from the other central unit ( ucb ) has been transmitted to the peripheral unit ( dria ) and is in course of execution , and , whether an order has been transmitted to the other central unit ( ucb ) for being transmitted to the peripheral unit ( dr1b ). consulting this information in memory determines the transmission of an order to the peripheral unit , or , the transmission of a message ( ipl51 or ipl52 ) to the other central unit for communicating an order to be executed or for signalling the end of execution of an order received previously from that other central unit for communicating an order to be executed or for signalling the end of execution of an order received previously from that other central unit . on the other hand , when a central unit , ucb for instance , has not access to its peripheral unit dr1b , the adequate arrangement of the tests of information contained in memory enables the other central unit uca to alternate the sending of orders to its peripheral unit dr1a for its own account , and , for the accunt of unit ucb . indeed , when central unit uca ascertains that its peripheral unit dr1a has executed an order which it had previously transmitted to it for the account of the other central unit , it sends to it preferably -- in as much as there is one in awaitance ( test of contents of hl0 , mark 8 ) -- an order for its own account . whereas , when the order has been transmitted and executed for its own account , it sends to it , preferably - in as much as there is one in awaitance ( phase &# 34 ;( a ) 1 = 1 ?&# 34 ;) - an order for the account of the other central unit uca by accomplishing the phases bpe0 → a , 1 → ( a ) 0 ; 1 → ( a ) 2 ; ( a ) → bpe0 , etc . such as described above . it is understood that the foregoing description of a specific embodiment of this invention is made by way of non - limiting example only and is not to be considered as a limitation on its scope .