text: fig3 a and 3 b show band diagrams along the channel of the nmos device described with respect to fig1 and 2 a . fig3 a corresponds to the “ off ” device and fig3 b corresponds to the “ on ” device . referring to fig3 a , the presence of n + source / drain extensions causes band bending 301 within the p - well . when gate lengths were longer in previous device generations , band bending 301 represented only a small fraction of the energy band profile within the p well beneath the gate . however , with continued gate length reductions , band bending 301 represents a larger and larger percentage of the energy band profile beneath the gate , and , the effects of band bending 301 are becoming increasingly noticeable . for instance , the presence of band bending 301 is believed to contribute to a reduced threshold voltage . referring to fig3 b , the presence of the n + drain extension causes sharp band bending 302 near / at the interface of the p well and the n + drain extension . the sharp bending 302 corresponds to an extremely high electric field that is believed to be the cause of a number of problems associated with “ hot carriers ” such as substrate currents , avalanche breakdown , lowered energy barriers and threshold shifting . fig4 a and 4 b show a design for an nmos device having improved band bending characteristics beneath the gate electrode as compared to the nmos device of fig3 a and 3 b . fig4 a shows the device in the off state and fig4 b shows the device in the on state . notably , the gate structure of the device can be viewed as having three sections : 1 ) outer sections 402 a and 402 b ; and , 2 ) inner section 403 . in an embodiment , for an n type device as observed in fig4 a and 4 b , the outer sections 402 a and 402 b are composed of p type device gate metal , and , the inner section 403 is composed of n type device gate metal . thus , outer sections 402 a , 402 b have a higher work function than inner section 403 . in this case , the effect of the higher work function material at the outer regions 402 a , 402 b of the gate have a similar effect as observed for the pmos device of fig1 . that is , the higher work function material induces band bending that pulls the conduction and valence bands “ up ” relative to the fermi level as compared to the levels observed in fig3 a . as such , the off device of fig4 a has less band bending 401 at the p well / extension interface regions than the band bending 301 observed in the device of fig3 a . as a consequence , the threshold voltage reduction caused by the presence of the n + source / drain extensions is practically eliminated or reduced . similarly , referring to fig4 b , the upward pull on the valence and conduction bands induced by the higher work function material 402 b causes less sharp band bending 404 at / near the p well / n + drain extension in an on device as compared to the on device of fig3 b . the less sharp band bending 404 corresponds to a weaker electrical field which should reduce “ hot carrier ” effects . band bending is also created at the p well / n + source extension . as observed in fig4 b a small barrier is created however this barrier may be minimized or eliminated with appropriate selection of doping levels and gate metal material . fig5 a and 5 b show a design for a pmos device having improved band bending characteristics beneath the gate electrode as compared to prior art pmos devices . fig5 a shows the device in the off state and fig5 b shows the device in the on state . notably , the gate structure of the device can be viewed as having three sections : 1 ) outer sections 502 a and 502 b ; and , 2 ) inner section 503 . in an embodiment , for a p type device as observed in fig5 a and 5 b , the outer sections 502 a and 502 b are composed of n type device gate metal , and , the inner section 503 is composed of p type device gate metal . thus , outer sections 502 a , 502 b have a lower work function than inner section 503 . in this case , the effect of the lower work function material at the outer regions 502 a , 502 b of the gate have a similar effect as observed for the nmos device of fig1 . that is , the lower work function material induces band bending that pulls the conduction and valence bands “ down ” relative to the fermi level . as such , the off device of fig5 a has less band bending 501 at the n well / extension interface regions than the corresponding band bending at the n well / extension interface regions in prior art ( single gate metal ) pmos devices . as a consequence , the threshold voltage reduction caused by the presence of the p + source / drain extensions is practically eliminated or reduced . similarly , referring to fig5 b , the downward pull on the valence and conduction bands induced by the lower work function material 502 b causes less sharp band bending 504 at / near the n well / p + drain extension in an on device as compared to a prior art ( single gate metal ) pmos device . the less sharp band bending 504 corresponds to a weaker electrical field which should reduce “ hot carrier ” effects . band bending is also created at the n well / p + source extension . as observed in fig5 b a small barrier is created however this barrier may be minimized or eliminated with appropriate selection of doping levels and gate metal material . it is pertinent to point out that , although the terms “ nmos ” and “ pmos ” are used above in reference to fig4 a , b and 5 a , b ( which are typically understood to refer to n type metal oxide semiconductor and p type metal oxide semiconductor devices , respectively ), for convenience , these terms should be understood to also apply to devices having a gate dielectric that is not technically an oxide . the terms “ n type device ” and “ p type device ” may also be utilized . moreover , although the term “ gate metal ” is used above in reference to fig4 a , b and 5 a , b , the term “ gate metal ” should be understood to apply to gate materials that are not technically a metal ( such as heavily doped polysilicon ). the term “ gate material ”, “ gate electrode ”, “ gate electrode material ” and the like may also be utilized . also , for convenience , the device diagrams do not depict well known device structures such as source / drain electrodes ( which are understood to be electrically coupled to their respective source / drain extensions ), metal gate fill material residing upon the depicted gate metal of a device , sidewall spacers , etc . fig6 a through 6 f show a prior art process for manufacturing nmos and pmos devices having different , respective gate metals . fig6 a shows the nmos and pmos devices up through deposition of the gate dielectric 601 a , b . in fig6 b , the gate metal 602 a , b for the nmos device is deposited on the gate dielectric 601 a , b of both devices . then , as observed in fig6 c , photoresist 603 a , b is coated on the wafer and patterned to form an opening 604 over the gate region of the pmos device such that the nmos gate metal 602 b residing in the pmos device is exposed . the nmos gate material 602 a over the nmos device is covered with photoresist 603 a . as observed in fig6 d , the exposed nmos gate metal 602 b in the gate region of the pmos device is etched away . the nmos gate metal 602 a in the gate region of the nmos device is protected by the photoresist 603 a during the etch . as observed in fig6 e , the pmos gate metal 605 is deposited over the gate dielectric of the pmos device . the photoresist 603 a , b is removed , as observed in fig6 f , leaving nmos gate material 602 a in the gate region of the nmos device and pmos gate material 605 in the region of the pmos device . as observed in fig6 f , the manufactured devices only have one gate metal on the gate dielectric . fig7 a through 7 f shows a process that , by contrast , can manufacture devices having more than one gate material on the gate dielectric of a single device . fig7 a shows the n type and p type devices up through deposition of the gate dielectric 701 a , 701 b . in fig7 b , n type gate material 702 a , b is deposited on the gate dielectric of both devices . as observed in fig7 c , photoresist 703 a , b is coated on the wafer and patterned to form a pair of openings 704 over the gate edges of the n type device , and , a single opening 705 over the gate center of the p type device . each of the openings expose underlying n type gate material 702 a , b . the exposed n type gate material 702 b is then etched . the etch may be performed by a dry etch such as an hcl based or sf - 6 based etch . when the exposed n type gate material is removed , p type gate material 706 a , b is deposited in its place as observed in fig7 e . the photo resist is subsequently removed leaving devices having n and p type gate metal on a gate dielectric . notably , in alternate approaches , p type gate material may be deposited before the n type gate material . in this case , the phororesist patterns are “ switched ” in comparison to fig7 b ( that is , the p type device will have a pair of openings and the n type device will have a single opening ). the type of materials used for the gate material may vary from embodiment . as discussed above , according to one approach , the gate material used for a p type device (“ p type gate material ”) is deposited not only on the gate dielectric of a p type device but also on the gate dielectric of an n type device . likewise , the gate material for an n type device (“ n type gate material ”) is deposited not only on the gate dielectric of an n type device but also on the gate dielectric of a p type device . generally , as discussed above , the p type gate material has a higher work function than the n type gate material . suitable gate materials may include but are not limited to polysilicon , tungsten , ruthenium , palladium , platinum , cobalt , nickel , hafnium , zirconium , titanium , tantalum , aluminum , titanium carbide , zirconium carbide , tantalum carbide , hafnium carbide , aluminum carbide , other metal carbides , metal nitrides , and metal oxides . as is known in the art , the gate materials may be deposited by various processes such as chemical vapor deposition or atomic layer deposition or sputtering . although efficiency in terms of the number process steps is achieved when p type gate material is deposited on both p type and n type devices and n type gate material is deposited on both n type devices and p type devices — alternate approaches may use a gate metal that is used on only one of the devices ( n type or p type ) to engineer the desired band bending . those of ordinary skill will be able to determine the application and materials when such an approach is warranted . also , in an embodiment , the gate lengths of the devices are longer than the minimum gate length that is achievable with the manufacturing process . for instance , in a logic process , typically , the smallest manufactured feature of the logic transistors is the gate length . thus , devices having gate structures as described herein have longer gate lengths than the logic transistors ( because multiple features are formed on a single gate as discussed above rather than a single , smallest manufactured feature as in the case of a logic transistor ). for instance , according to one implementation , devices having gate structures as described herein are used to implement higher voltage analog and / or mixed signal circuits . such devices may be integrated on the same semiconductor device having logic transistors with minimum feature gate lengths . for example , a system on chip ( soc ) having digital components ( e . g ., processing core , memory , etc .) and analog / mixed signal components ( e . g ., amplifiers , i / o drivers , etc .)) may use devices having gate structures as described herein for the analog / mixed signal components . it is also pertinent to point out that although the examples discussed above show strict alignment of the outer gate edge metal with the underlying source / drain extension tips , such an approach is merely exemplary . the positioning of the boundary between the inner gate metal and the outer gate metal of a dual gate metal structure may vary so long as appropriate band bending is achieved . moreover , as is indicated by fig8 a ( discussed in more detail immediately below ), some device designs may have different outer edge gate material on only one of the edges — e . g ., only on the source side or only on the drain side . for example , a device design that is mostly concerned with hot carrier effects may choose to place different outer edge gate material on the drain side of the gate but not the source side of the gate . likewise , a device design that is less concerned about hot carrier effects and more concerned about a substantially non flat energy band structure beneath the source end of the gate may choose to only add different gate material on the source side of the gate and not the drain side of the gate . further still , although the examples discussed above indicate that , in cases where different outer edge gate material exists at both the source and the drain the same gate material is used at both edges , alternative device designs may exist where the pair of outer edge gate materials are different as between themselves . for instance , a first outer edge gate material may be used at the source side of the gate to control the height of the barrier beneath the source side of the gate ( observed in fig4 b ), and , a second outer edge gate material — that is different than the gate material used on the source side — may be used at the drain side to diminish the electric field between the well and the drain junction . fig8 a through 8 c show various kinds of transistors that may be formed with dual metal gate structures as described herein . fig8 a shows an n type asymmetrical device and a p type asymmetrical device . notably , these devices only contain a different outer edge metal near the drain side and not the source side ( specifically , the p type gate metal for the n type device , and , the n type gate metal for the p type device ). as such , these devices only attempt to impart band bending that reduces the electric field near the well / drain extension . fig8 b shows a vertical drain nmos device ( vdnmos ) device having a dual metal gate structure . as is known in the art , a vdnmos device addresses the problem of a high electric field between the well and drain junction by inserting insulation material 801 beneath the drain edge of the gate . this insertion of a trench 801 creates a high resistance path from the extrinsic drain contact to the gate edge , thereby decreasing the electric field at the region under the gate . in addition , the highly doped drain implants and tips are prevented from encroaching under the gate , which also reduces the peak electric field . these reductions in the field translate to lower carrier energies , and enhanced device reliability . fig8 c shows a laterally diffused mos ( ldmos ) device having a dual metal gate structure . as is known in the art , an ldmos device addresses the problem of having a high electric field between the well and drain junction by extending the drain extension ( dex ) beneath a field plate 802 . a field plate 802 acts to spread the field over a larger drain distance , effectively lowering the peak field and enhancing the device lifetime through reduction of hot carrier effects . in the foregoing specification , the invention has been described with reference to specific exemplary embodiments thereof . it will , however , be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims . the specification and drawings are , accordingly , to be regarded in an illustrative rather than a restrictive sense .