text: the present invention aims to provide an improved method for fabricating a low temperature polysilicon thin film transistor without residues of photoresist and chemicals . [ 0019 ] fig2 a to 2 j are cross - sectional views showing the sequential process steps of the method for fabricating a low temperature polysilicon thin film transistor in accordance with one preferred embodiment of the present invention . referring first to fig2 a , a buffer layer 202 and a polysilicon layer 204 are sequentially formed on a substrate 200 . the buffer layer 202 can be a silicon oxide layer or a silicon nitride layer , and the substrate 200 can be a glass substrate or a plastic substrate . the polysilicon layer 204 can be formed by annealing amorphous silicon using excimer laser . the polysilicon layer 204 can have a thickness between about 200 angstroms and 1000 angstroms . next , a gate oxide layer 208 is formed on the polysilicon layer 204 . the gate oxide layer 208 can be made of silicon dioxide , and can have a thickness between about 500 angstroms and 1500 angstroms . then , a patterned photoresist layer 205 is formed on the polysilicon layer 204 , and the gate oxide layer 208 and the polysilicon layer 204 are etched using the patterned photoresist layer 205 as a mask . the removal of the residues of the photoresist layer 205 on the gate oxide layer 208 is performed by using chemicals , such as wet dip . the structure after wet dip is shown in fig2 b . in fig2 b , there are three stack structures having the gate oxide layer 208 and the polysilicon layer 204 . the middle and the left ones respectively function as the nmos device and the pmos device of the cmos transistor . the stack structure on the right of the three stack structures is the nmos device in the pixel area . compared with the conventional manufacturing process , the manufacturing process of the invention has no step between the formation of the polysilicon layer 204 and the gate oxide layer 208 . the conventional process includes steps such as forming the photoresist layer 105 on the polysilicon layer 104 and removing the photoresist layer 105 by using chemicals , which do not exist in the method of the present invention . thus , the problem of photoresist and chemical residues between the gate oxide layer 208 and the polysilicon layer 204 is overcome by applying the process of this invention . this improvement further benefits the quality of the low temperature polysilicon tfts . referring to fig2 c , a conductive layer is disposed on the gate oxide layer 208 . photolithography and etching processes are then performed to define the patterned conductive layer and form a gate 210 . the material of the gate 210 can be molybdenum ( mo ), chromium ( cr ), thallium / aluminum / thallium ( ti / al / ti ) or their combination . next , referring to fig2 d , a patterned photoresist layer 212 is formed on the gate 210 and on the gate oxide layer 208 . then , a heavily doping process , using high dosage of phosphorus , is performed to form source / drain regions 204 a , 204 b , 204 c , 204 d of a nmos transistor . the dosage of phosphorus implanted can be between about 1e14 dose / cm 2 and 5e15 dose / cm 2 . the photoresist layer 212 then is removed . low dosage of phosphorus is then implanted into the substrate 200 to form a lightly doped source / drain regions 104 m , 104 n , 104 x , 104 y of the nmos transistor , as shown in fig2 e . the dosage of phosphorus implanted is between about 8e12 dose / cm 2 and 5e13 dose / cm 2 . next , referring to fig2 f , a photoresist layer 214 is formed over the substrate 200 on the gate 210 and the gate oxide layer 208 . using the photoresist layer 214 as a mask , high dosage of boron is implanted in the substrate 200 to form source / drain region 204 i , 204 j of a pmos transistor . the dosage of boron implanted is between about 1e14 dose / cm 2 and 5e15 dose / cm 2 . referring to fig2 g , the photoresist layer 214 is removed . an interlayer dielectric 216 is formed on the gate 210 and on the gate oxide layer 208 . there are a number of openings formed within the gate oxide layer 208 and within the interlayer dielectric 216 thereon . the interlayer dielectric 216 can be made of silicon dioxide , and can have a thickness between about 2000 angstroms and 7000 angstroms . then , referring to fig2 h , a conductive layer , filling the openings within the gate oxide layer 208 and the interlayer dielectric 116 , is formed on the interlayer dielectric 216 . the conductive layer forms electrodes 218 electrically connecting the gate 210 , the source / drain regions 204 a , 204 c , 204 i , 204 b , 204 d and 204 j . referring to fig2 , a passivation layer 220 is formed on the electrodes 218 and on the interlayer dielectric 216 . an opening formed within the passivation layer 220 exposes a part of the electrodes 218 . next , a transparent electrode 222 is formed on the passivation layer 220 and fills in the opening through the passivation layer 220 to electrically connect the electrode 218 , as shown in fig2 j . the transparent electrode 222 can be made of a conductive transparent material such as indium tin oxide ( ito ). with the abovementioned manufacturing process , the residues of photoresist and chemicals on the polysilicon layer 204 can be effectively prevented . the electron mobility of the low temperature polysilicon tft is improved as a result of the improved smooth interface between the polysilicon layer 204 and the gate oxide layer 208 . some other defects occurring on the devices manufactured by the conventional method , such as abnormal shifting of the threshold voltage and sub - threshold swing , are effectively prevented . while the invention has been described by way of example and in terms of a preferred embodiment , it is to be understood that the invention is not limited thereto . on the contrary , it is intended to cover various modifications and similar arrangements and procedures , and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures .