text: fig1 illustrates a data storage device 100 which may be authenticated using the principles taught by the present invention . the device 100 includes an eeprom 102 communicating with a microcontroller 104 . the microcontroller 104 includes a processor 106 and memory , such as a rom 108 and a ram 110 . the rom 108 includes instructions and other data for controlling the operation of the processor 106 , while the ram 110 is used by the processor 106 to store values and data during the operation of the processor 106 . the microcontroller 104 also includes an input / output ( i / o ) port 111 , used to transfer data in and out of the data storage device through communication with the processor 106 . the processor 106 communicates with the eeprom through a data bus 112 , control bus 114 and address bus 116 . the processor 106 directs operation of the eeprom by placing instructions on the control bus 116 and reads and writes data to and from addresses in the eeprom by placing the desired address on the address bus 118 and either placing data on or reading data from the data bus , depending on whether a read or write operation is being performed . data storage here is shown accomplished through the use of a eeprom , but any number of suitable alternatives may be used to perform the present invention . data such as financial data may be stored in the data storage device 100 by providing appropriate data and instructions to the microcontroller 104 through the i / o port 118 . the microcontroller 104 will store the data in the eeprom 102 . a data storage device such as the device 100 may be embodied as a stored value card or other identification card which may present an attractive target for counterfeiting or unauthorized modification . for example , a customer given possession of a stored value card implemented as a data storage device such as the device 100 may wish to add value to the card by storing new data to the eeprom 102 . alternatively , a counterfeiter may wish to create additional copies of a stored value card by copying data from the eeprom of a legitimate card to the eeprom of a card constructed by the counterfeiter . in order to detect unauthorized modifications or counterfeiting of the data storage device 100 , it is important to provide a reliable means to distinguish between an authentic device and a copied or modified device . writing data to a semiconductor memory device such as the eeprom 102 of fig1 creates trapped charges in cells of the memory device . it is not possible to choose a level of charges to be stored in a cell of a memory device , but once the data has been written and the charge level has been established , the charge level can then be accurately determined . fig2 illustrates a memory cell 200 which may be advantageously employed according to the teachings of the present invention . the memory cell 200 may comprise a transistor integrated on a p - type substrate 202 . the transistor comprises a source ( s ) 204 and a drain ( d ) 206 which are fabricated using well known techniques by the diffusion of n + impurities on the substrate 202 . the transistor includes a field oxide layer 208 that overlays the source 204 and the drain 206 , and a floating gate 210 fabricated from a first layer of polysilicon that overlays the oxide layer 208 . the transistor further comprises a gate 212 fabricated from a second layer of polysilicon that overlays the floating gate 210 . data may be programmed in the memory cell 200 for purposes of data storage according to the well known technique of floating - gate charge injection . for example , a potential which is typically greater than 12 volts is applied to the drain 206 to create a strong electric field that energizes electrons to jump from the drain 206 region to the floating gate 210 region . the electrons attracted to the floating gate 210 become trapped in the floating gate 210 when the potential is removed from the drain 206 . when charges are trapped in the floating gate 210 , the threshold of the memory cell 200 changes from a relatively low value , which is associated with the memory cell 200 when no charge or a small charge is present and is called an erased condition , to a higher value , which indicates that programming of the memory cell 200 has occurred . if a low voltage potential for programming a logic level low or “ 0 ” in the memory cell 200 is applied to the gate 212 , then electrons are not attracted to the floating gate 210 , and thus the floating gate 210 remains uncharged . on the other hand , if a high voltage potential for programming a logic level high or “ 1 ” is applied to the gate 212 , then a large number of electrons will be attracted to the floating gate 210 , thereby charging the floating gate 210 . it is well known to one of skill in the art that typical voltages for programming high and low logic levels depend upon the type and design of the semiconductor memory device being used . the level of charges that will be trapped in the memory cell 200 as a result of programming depends upon the characteristics of the semiconductor material and the geometry of the structures in the memory cell 200 . for instance , variations in doping levels and dopant purities and the thickness of doped regions of a semiconductor substrate will cause inherent random variations in the level of charges that are trapped in a memory cell when a specific voltage level is applied for a specified amount of time during programming . these inherent random variations make reproduction or duplication of the same relative level of trapped charges in a second memory cell for purposes of obtaining an identical level of trapped charge in the second memory cell very difficult , if not impossible . the level of charges which will be trapped in a memory cell also depends on environmental conditions , such as temperature and the presence of stray static charges , existing at the time that the memory cell is programmed . in addition , the previous level of trapped charges for the memory cell and the total number of write cycles applied to the memory cell , known as the history of the memory cell , contribute to the level of charges trapped in the memory cell . therefore , with each programming event the pattern of the trapped charges in memory cells of a memory array will vary in a manner which cannot be reproduced , even when the same memory cell is programmed with the identical data . the pattern of trapped charges in memory cells of the array can be used to provide reliable authentication for a memory device employing an array of memory cells such as the cell 200 . fig3 illustrates a process 300 for writing data according to the present invention . the data written can then be used to determine charge levels of memory cells to which the data has been written . the process of determining the charge levels is discussed below in connection with fig4 . the process may suitably be employed with a data storage device such as the device 100 , employing a processor , eeprom and data , address and control buses similar to those illustrated in fig1 above . while illustrated in the presently preferred context of a processor communicating with an eeprom , it will be recognized that the techniques of the present invention may be employed with any memory device employing trapped charges within memory cells . at step 302 , a list of selected memory cells to which data is to be written is created . at step 304 , a value of “ 1 ” or “ 0 ” is associated with each memory cell of the list , as the data to be written to that memory cell . at step 304 , the first entry in the list is examined to determine the destination . address where the data is to be written . at step 306 , the destination address is placed on the address bus . at step 308 , a voltage representing a modified nominal “ 0 ” or “ 1 ” is placed on the data bus , depending on whether a “ i ” or a “ 0 ” is to be written to the destination address . the nominal value of the “ 1 ” or “ 0 ” is offset by a small random intentional error , suitably on the order of +/− 10 % of the nominal voltage signal . the introduction of an intentional offset error to the nominal voltage signal level used for writing data provides additional security for the stored data , because it makes it more difficult for a counterfeiter or other unauthorized user to predict the level of trapped charges in a memory cell , and thus renders it more difficult to recreate that same level in copying or modifying a memory cell . at step 308 , the control bus is set to enable a write operation . at step 310 , the data is written to the destination address . at step 312 , the entry for which the data was written is removed from the list . at step 314 , the list is examined to determine if it is empty . if the list is not empty , the process proceeds to step 316 and the next entry on the list is examined to determine the destination address where data is to be written . the process then returns to step 306 . if the list is empty , the process terminates at step 350 . fig4 illustrates a process 400 for obtaining and storing data representing levels of trapped charges in selected programmed memory cells of a memory array according to the present invention . at step 402 , a list of selected memory cells is established . at step 404 , an initial logical “ 1 ” threshold level is established for each cell containing a logical “ 1 ”. this threshold level is chosen to be below the expected level for any cell containing a logical “ 1 ”. for example , if a logical “ 1 ” is expected to have a voltage level of 4 . 0 volts or above , the initial threshold level may be set to 3 . 9 volts . at step 406 , an initial logical “ 0 ” threshold level is established for each cell containing a logical “ 0 ”. this threshold level is chosen to be above the expected level for any cell containing a logical “ 0 ”. for example , if a logical “ 0 ” is expected to have a voltage level of 1 . 0 volts or below , the initial threshold level may be set to 1 . 1 volts . at step 408 , a read operation is performed for the selected memory cells . at step 410 , each of the selected cells which was read in the read operation of step 408 as having a different logical value than the logical value actually contained is assigned the level of trapped charges indicated by the threshold , and a value representing the assigned level of trapped charges is stored for each cell . a cell which contains a logical “ 1 ” but which was read as a logical “ 0 ” in the read operation of step 408 or a cell which contains a logical “ 0 ” but which was read as a logical “ 1 ” in the read operation of step 408 is assigned the level of trapped charges indicated by the threshold and a value at step 412 , each of the cells which was written as a “ 0 ” and recognized as a “ 1 ”, and which was written as a “ 1 ” and recognized as a “ 0 ” is removed from the list of selected memory cells . at step 414 , the list of selected cells is examined to determine if it is empty . if the list is not empty , the process proceeds to step 416 . if the list is empty , the process proceeds to step 420 . at step 416 , the logical “ 0 ” threshold level is examined to determine if it falls below a predetermined minimum and the logical “ 1 ” threshold level is examined to determine if it exceeds a predetermined maximum . if the logical “ 0 ” threshold level does not fall below the predetermined minimum , or the logical “ 1 ” threshold level does not exceed the predetermined maximum , the process proceeds to step 418 and the logical “ 0 ” threshold level and the logical “ 1 ” threshold level are decremented as appropriate . . the process returns to step 406 . if the logical “ 1 ” threshold level exceeds the predetermined maximum and the logical “ 0 ” threshold level does not fall below the predetermined minimum , the process returns to step 406 . returning now to step 416 , if the logical “ 1 ” threshold level exceeds the predetermined maximum and the logical “ 0 ” threshold level falls below the predetermined minimum , the process proceeds to step 420 . at step 420 , the stored representations of the levels of trapped charges for the selected cells are retrieved and assembled to create a reference fingerprint which can be used to identify the memory array . fig5 illustrates a process 450 for obtaining and storing data representing levels of trapped charges in selected programmed memory cells of a memory array according to the present invention . at step 452 , a list of selected memory cells is established . at step 454 , an initial threshold level is established for recognizing a logical “ 1 ”. at step 456 , a read operation is performed for the selected memory cells . at step 458 , each of the selected cells which is recognized as a “ 1 ” is presumed to have the level of trapped charges indicated by the threshold . at step 460 , a value representing the level of trapped charges is stored for each of the cells which was recognized as a “ 1 ”. at step 462 , each of the cells which was recognized as a “ 1 ” is removed from the list of selected memory cells . at step 464 , the list of selected cells is examined to determine if it is empty . if the list is empty , the process proceeds to step 466 . if the list is empty , the process proceeds to step 468 . at step 466 , the threshold level is examined to determine if it exceeds a predetermined maximum . if the threshold level does not exceed the predetermined maximum , the process proceeds to step 467 , the threshold level is incremented and the process returns to step 466 . if the threshold level exceeds the predetermined maximum , the process proceeds to step 468 . at step 468 , the stored representations of the levels of trapped charges for the selected cells are retrieved and assembled to create a reference fingerprint which can be used to identify the memory array . fig6 illustrates a process 500 for writing data to and reading data from selected cells of a memory array in order to generate a reference fingerprint comprising data representative of levels of trapped charges in the array . the fingerprint is generated immediately after data is written to the array . at step 502 , data is written to selected cells of the memory array using the process illustrated in fig3 . at step 504 , the levels of trapped charges of the selected cells are determined using the process of fig4 . at step 506 , representations of the levels of trapped charges are used to create a reference fingerprint which uniquely identifies the memory device which was written to , and the characteristics of the writing event . for example , the reference fingerprint for a data string of “ 0101 ” may be numerically represented as 4 . 6 for a “ 1 ”, 0 . 5 for a “ 0 ”, 4 . 75 for a “ 1 ” and 0 . 45 for a “ 0 ” for a particular memory device . these numbers represent the actual voltage levels of the referenced memory cells . alternatively , the reference fingerprint may comprise a sequenced data string , known as a condensed sequence , which includes selected numerical representations of the measured levels of trapped charges obtained in step 504 . in a further alternative , the numerical representations of the memory cells read in step 504 may be selected for inclusion in the fingerprint by the use of fuzzy logic . for example , fuzzy logic techniques may be used to generate a fuzzy set of data , which by definition is a subset of the set of numerical representations obtained in step 504 . the fuzzy set primarily includes significant numerical representations , defined as those representations which are most valuable to the fuzzy set . conventional mathematical operations associated with processing and analyzing a fuzzy set of data may be used . for instance , the ratios of the levels of trapped charges of adjacent memory cells in a semiconductor device that contains the same programmed data bit may be used as the significant numerical representations which are included in the reference fingerprint . in addition , fuzzy logic can be used , for example , to compensate for temperature variations that may distort the numerical representations obtained in step 504 . such a result would be possible because a fuzzy set could be generated that contains values which , from prior experience , compensate for the effects of temperature on adjacent cells . other forms of compensation using fuzzy logic could also be used . in a further alternative , a condensed sequence of the numerical representations may be stored as the reference fingerprint using fuzzy logic techniques . at step 508 , the numerical representations included in the reference fingerprint are stored for use in subsequently authenticating the stored data in the memory array . the reference fingerprint may be stored in a chosen location within the memory array , or alternatively may be passed to an output of the memory device for external storage . for further security , the reference fingerprint may be encrypted before storage . fig7 illustrates a process 600 for authenticating a memory device according to the present invention . at step 601 , the selected memory cells from which the reference fingerprint was created are read using a normal read process to determine which cells were written as logical “ 1s ” and which cells were written as logical “ 0 s ”. at step 602 , the selected memory cells from which the reference fingerprint was created are read using the process illustrated in fig4 or alternatively the process illustrated in fig5 in order to determine the charge levels of the memory cells . at step 604 , an authentication fingerprint is created using the data obtained at step 602 . at step 606 , the previously created reference fingerprint is retrieved . at step 608 , the authentication fingerprint is compared to the reference fingerprint . if the authentication fingerprint matches the reference fingerprint , the process proceeds to step 610 and the memory device passes authentication . if the authentication fingerprint does not match the reference fingerprint , the process proceeds to step 612 and the memory device fails authentication . while the present invention is disclosed in the context of a presently preferred embodiment , it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below .