text: the elements of an image analysis system have been described in the before mentioned morton u . s . pat . no . 3 , 805 , 028 the disclosure of which is incorporated herein by reference . for convenience and for completeness in this specification , fig4 shows the major elements of an image analysis system in a block diagram form . the image to be measured or analyzed is viewed by television camera 401 to generate a video signal on line 402 representing the image . this video signal is then analyzed in detection circuit 403 to define the boundary of the feature to be analyzed . the signal representing the boundary is termed the binary video signal and appears on line 404 . this signal then passes to the digital analysis block 405 , referred to in greater detail in fig5 which processes the signal to produce the desired count data , the results of which pass along line 406 to a data processing function 407 . specifically , in the case of counting operations , the data on line 406 corresponds to count tags assigned to specific features . the video signal also passes to the display 408 to display the image viewed by the television camera , as well as the detected image of the boundary of the feature or features to be measured , the count tags on line 406 , and the results of the measurement in the count register , on line 409 , to be presented on the display . count tags can be visually represented , for example , by tags 10 and 12 of fig1 . of specific interest in the current invention is the digital analysis block 405 , which is shown in greater detail in fig5 . the function of the count circuit , shown in fig5 is to produce one pulse on output line 130 for each feature in the field , in response to data consisting primarily of the incoming binary video signal on line 131 . the binary video signal enters the binary video signal pre - processor 501 , which processes the binary video signal so that transitions of the binary video signal are not closer than the timing resolution of the subsequent circuitry . thus , in some cases , very narrow features oriented substantially transversely to the new format are scanned and produce leading and trailing edge signals so close together that the system cannot resolve them and these signals appear to the system as one signal . this can cause all the remaining edge signals of that scan line to be out - of - phase . to avoid this , the select circuit of fig6 is incorporated to implement the function of pre - processor 501 and operates on such signals to cause closely spaced leading and trailing edge signals to be ignored . therefore , all signals which are spatially so close that they cannot be resolved , are not considered . the circuit to do this can comprise , as shown in fig6 two flip - flops synchronously clocked , for example , at a 20 mhz rate , by a clocking signal on line 601 generated from a system clock . flip - flops 604 and 605 are of the d - type and can be , for example , texas instruments component sn74s74 . the flip - flops receive the incoming video signal on line 602 and a clock signal on line 601 . flip - flop 604 produces a binary video signal on line 603 identical to the incoming binary video signal except that it is delayed by one clock pulse . flip - flop 605 , in response to the signal on line 603 , produces a signal , similar to the binary video signal but delayed by a further clock pulse , on output line 606 and its inverted form on output line 607 . nand gate 608 , through line 609 , sets set / reset flip - flop 610 whenever flip - flops 604 and 605 are in the set or &# 34 ; 1 &# 34 ; state . similarly , nand gate 612 , in receipt of the inverted signal on line 607 and a signal on line 614 which is the invert of the signal on line 603 , produces an output on line 613 to reset flip - flop 610 whenever flip - flops 604 or 605 are in the reset or &# 34 ; 0 &# 34 ; state . thus , the output of the flip - flop 610 on line 611 corresponds to the incoming binary video on line 601 , except that transitions closer than two clock pulses apart do not occur . the flip - flop 610 can comprise , for example , texas instruments component sn74s74 . the nand gates 608 and 612 can comprise texas instrument component sn74soo . with respect to fig5 the function of optional circuit 502 is to inject signals corresponding to the oversize count as in gates 5802 and 5803 of fig2 of the before mentioned morton u . s . pat . no . 3 , 805 , 028 , when the circuit is in the oversize count mode . as a consequence of this , circuit line 521 is in the low state when in the count mode , and corresponds to the inverted signal when the system is in the oversize count mode . the frame circuit 504 is associated with border correction in the counting operation , and can be implemented in the same manner as the half - frame inject circuit 5804 of fig2 of the before mentioned morton patent . in the alternative , it can simply be implemented by modification of the incoming binary video signal on line 131 to inhibit the binary video signal entering from the signal inject circuit 502 when it corresponds to areas outside the field of view by combining the binary video signal with the blanking signal from line 503 generated by the television camera in an and gate driving line 522 . when the system is in the count mode line 522a is a direct connection to line 522 . thus , on line 522 , the pre - processed binary video , processed for border correction , passes to the count logic gate 505 to set the set / reset flip - flop comprising gates 506 and 507 whenever the binary video signal on line 522 goes to the &# 34 ; 1 &# 34 ; or high state , corresponding to the leading edge intercept of a feature . line 521 can be ignored and assumed to be low , except in the oversize count mode . consequently set / reset flip - flop comprised of gates 506 and 507 resets when line 522 is low , or in the &# 34 ; 0 &# 34 ; state , corresponding to being outside the feature intercept , and when the output on line 703 from the line - to - line memory 511 is also low , to produce a high or &# 34 ; 1 &# 34 ; value signal at the output of inverter 512 . this in combination , produces a low signal at the output of gate 510 to reset the flip - flop comprised of gates 506 and 507 . thus , the flip - flop comprised of gates 506 and 507 is set whenever line 522 is high , and reset whenever both line 522 and the output line 703 of line - to - line memory 511 are low . in operation , the one line scan delayed binary video signal from memory 511 , which may have resulted from a modified video signal as for reentrant feature g as shown in fig2 is combined with the current binary video signal of the next line scan on line 522 to produce on line 533 yet another modified binary video signal having a leading edge corresponding to that of the current binary video signal and a trailing edge corresponding to the last - to - occur of the trailing edges of the current and delayed signal . the nand gates in the herein described preferred embodiment can be , for example , texas instruments component sn74s00 and the nor gates can be texas instruments component sn74s02 and the and gates can be , for example , texas instrument component sn7408 . the inverters can be texas instruments component sn74s04 . the system of fig7 which implements the functions of memroy 511 , includes a pair of random access memories 704 and 705 which store the intercept data which is to be delayed one line scan and then employed to generate a delayed binary video signal . one memory is used to store such data for a current line scan while the data for the previous line scan is being outputted from the other memory to generate the delayed signal , and vice - versa . the switching of the memories from the input or store state to the output state is controlled by jk flip - flop 720 which switches its outputs responsive to the receipt of the line scan horizontal sync pulse via line 721 . the flip - flop 720 can be , for example , texas instruments component sn74s74 . thus , when flip - flop 720 produces on line 715 a signal which is asserted high , or in the &# 34 ; 1 &# 34 ; state , it enables memory 704 via gate 740 to assume an output mode and output is stored data via line 712 to multiplexer 714 which can be , for example , texas instruments component sn74s157 . at such time , the signal asserted by flip - flop 720 on line 725 will be low so as to enable memory 705 to assume a store mode via gate 741 and store data . reversal of the state of the flip - flop 720 reverses the above modes . a clock generator 710 generates reference clock signals using a crystal osctillator , for example , texas instruments component sn74s124 . the clock generates a standard clock signal clk on line 790 and a memory read / write clock w / rcl on line 730 . the modified binary video input on line 533 , which are the pulses generated by flip - flop 507 / 506 in fig5 is processed by d - type flip - flop 701 synchronously with the clocking signal clk to produce an output to the second d - type flip - flop 761 . outputs of both flip - flops 701 and 761 pass to exclusive or gate 763 and through delay 762 so that for any transition of the signal on line 533 , a positive pulse occurs on line 760 , whose duration is equal to the period of a clk clock signal . the appropriate magnitude of these periods can be determined from integrated circuit application data , the speed of scan and the clock rate of clock generator 710 . flip - flops 701 and 761 can be texas instruments component sn74s74 and exclusive or gate 763 can be texas instruments component sn74s86 . this pulse then passes to data demultiplexer 750 which , under the control of flip - flop 720 via line 715 , routes the pulse along lines 743 to random access memory 705 , when line 715 is low . thus , unity data appears on the data - in line of the memory 705 , and also gate 741 passes this pulse to the me ( memory enable ) line on memory 705 so that a true signal is stored at the location defined by the address lines 709 driven by the counter 707 . the timing for these events can be readily ascertained , for example , from the data sheets for the memory component sn74s200 by texas instruments . the demultiplexer unit 750 can be made by appropriately connecting the inputs and outputs of two sections of a multiplexer such as texas instruments component sn74s157 . counter 707 can be a group of three synchronous binary counters such as the texas instruments component sn74s163 , connected in the manner suggested by the manufacturer at page 333 of &# 34 ; the ttl data book &# 34 ; published by texas instruments incorporated , first edition copyright 1973 . the address on line 709 from counter 707 is determined by the strobe signal on line 786 . this signal is generated by passing the current binary video signal via line 522a to flip - flop 702 , similar to flip - flop 701 , which passes the incoming video signal to flip - flop 764 similar to flip - flop 761 and thence to exclusive or gate 765 similar to element 763 , to produce on line 786 a positive pulse similar to that on line 760 , whenever a transition occurs on line 522 . this positive pulse , if line 715 is high , will cause nand gate 767 to produce a pulse into the load or ld terminal of counter 707 to load this counter synchronously with clock line 790 at clk terminal with the contents of the data on the parallel data line 770 , driven from counter 771 which can be similar in design to counter 707 . counter 771 , which is reset or cleared by the horizontal sync pulse on line 721 at the beginning of each line , counts using clock clk , an increasing count across the scan line , so that its contents at any instance can correspond to the x - position of the scanning spot along a horizontal scan line . thus , the address to which data is assigned in memory 705 corresponds to the time at which the last transition at a leading or trailing edge of the current video signal occurred on current video line 522 , i . e ., the last pulse on 786 . if line 715 is low , line 769 is high . a similar operation would occur with memory 704 , nor gate 740 , parallel data lines 708 , counter 706 , responding again to line 770 , the counter 706 being set through nand gate 766 and line 768 . in the output mode , assuming as before that line 715 is high , counter 706 is counting . counter 706 is cleared at the beginning of a horizontal scan line by line 722 , corresponding to the horizontal sync pulse on line 721 . thus , addresses , corresponding approximately to the x - coordinate of the scanning point , appear on line 708 for input into the address input of random access memory 704 . the memory 704 is enabled , by nor gate 740 responding to the high or &# 34 ; 1 &# 34 ; signal at line 715 . consequently , the data - out line 712 produces a pulse whenever the address on line 708 addresses a cell or location within the memory , which is in the true , &# 34 ; 1 &# 34 ; or asserted state . this pulse on line 712 passes into data multiplexer 714 , which is selected in response to line 715 to pass the data from input line 712 to output line 716 . the pulse which occurs at each address location triggers flip - flop 717 , to produce an output line 703 a pulse whose transitions occur at the time defined by the addresses of the true or &# 34 ; 1 &# 34 ; locations in memory 704 thereby generating a true binary signal . in order to ensure that the flip - flop 717 has a correct initial state at the beginning of each scan line , horizontal sync is fed into its reset terminal by line 721 . during the store mode for either memory , which is dependent upon flip - flop 720 , only memory locations corresponding to those loaded into counter 707 , or into the other counter 706 have entries made into them . thus , other locations were left undisturbed . it consequently becomes a further responsibility of the output mode to write into every location which has been read , a zero (&# 34 ; 0 &# 34 ;) or null data . this is done by virtue of the w / rcl line 730 generated by the clock generator 710 . therefore in the output mode , every read operation is followed by a write cycle , before address counter 706 is incremented . in order to ensure that this event occurs , data demultiplexer 750 , in response to a high on line 715 , ensures that data in line 722 is low and that zeroes (&# 34 ; 0 &# 39 ; s &# 34 ;) will be written into the memory 704 . as will be appreciated , this read / write clocking requirement , when applied also is the store mode of the line - to - line memory circuit , does not unvalidate the operation of this mode and accordingly the w / rcl line 730 connects to both memories . whenever line 715 is low and line 725 is high , due to flip - flop 720 setting the state opposite to line 715 , and memory 705 will be in the output mode . in such a mode , an input address data line 709 , counter 707 , nor gate 741 , and the counterparts of the other components hereinbefore discussed with rspect to memory 704 , function similarly to those described for memory 704 . referring again to fig5 the output delayed video signal on line 703 from line - to - line memory 511 , as described with respect to fig7 passes through inverter 512 to gate 510 . gate 510 produces a pulse whenever the signal on line 703 is low or &# 34 ; 0 &# 34 ; and the signal on line 522 is low or &# 34 ; 0 &# 34 ;, whichever is the latest , so that both have a level corresponding to the condition when the scanning spot is not traversing a feature . this causes flip - flop 507 / 506 to reset corresponding to the &# 34 ; last trailing edge of a feature &# 34 ; and in preparation for the next intercept which will produce a high level signal initially on line 522 . whenever a negative transition &# 34 ; 1 &# 34 ; to &# 34 ; 0 &# 34 ; occurs on line 703 , corresponding to the trailing edge of a feature , it passes through delay 513 into positive differentiator 516 to produce at the output of the positive differentiator 516 , a positive pulse . the positive differentiator may be implemented using a singal resistor , a single capacitor and a single diode in a manner well known to those in the art . delay 508 receives the output of set / reset flip - flop 506 / 507 at gate 506 , delays it for a significant time , which is greater than the time delay of delay 513 and passes it to nand gate 515 . the significant time approximates 1 or 2 clock pulses . whenever the output from delay 508 is high , coincident with a positive pulse from differentiator 516 , a low or &# 34 ; 0 &# 34 ; output occurs from nand gate 515 and this corresponds to the generation of a count pulse . the resulting pulse passes to nor gate 517 where , with vertical sync pulses on line 525 , it is ensured that count pulses from outside the field of view , are not able to pass or are inhibited . in the alternative , on line 525 there could be present the signal corresponding to a frame signal which is asserted inside the frame which defines the field of measurement , thereby ensuring that only counting pulses that occur within that frame or field of measurement are allowed to pass . in any event , those pulses which do not pass reach monostable 516 to produce an elongated pulse on line 130 which passes subsequently to a counter in data processor 407 , as shown in fig4 for generating a result on line 409 corresponding to the number of pulses generated in the field of view . this result passes to display 408 , to display a count of the number of features in the field of view , as disclosed , for example , in the morton u . s . pat . no . 3 , 805 , 028 . in operation , the circuit of fig7 on a specific feature , functions as follows . the video horizontal sync on line 721 clears counter 771 so that it can begin counting along the next scan line . during that line scan , current binary video transitions are converted into strobe signals on line 786 , as hereinbefore explained . upon occurrence of each strobe signal , the count then is counter 771 , representing the x - coordinate of that particular transition , is loaded into either counter 706 or counter 707 , dependent upon which is in the output mode . further , provided there is a signal on line 760 corresponding to a transition of the modified binary video signal , it is loaded into either memory 704 or memory 705 . thus referring to fig2 when a transition occurs in the modified video signal , the count at points 1 and 4 will be loaded into memory from line n because they are the first and last intercept points and therefore are either in the counter 706 or counter 707 . thus , there is provided means for generating and successively temporarily storing the x - coordinates of the intercepts of the scanning beam with a feature in the current line scan , as well as means for reading those x - coordinates , which are currently temporarily stored , in response to transitions of the modified video signal . the operation of the circuit of fig5 of this disclosure in the oversize count mode is similar to the operation of the circuit disclosed in fig2 of the beforementioned morton patent . signal inject unit 502 of fig5 contains gates similar to 5802 and 5803 of fig2 of the referred to morton patent . an oversize count pulse enters on line 670 of fig5 which is equivalent to line 6705 of fig2 of the beforementioned morton patent , and the signal on line 820 , which is equivalent to 5820 of fig2 of the morton patent , inhibits passage of the binary video signal to inverter 505 and gate 509 , when the delayed video is not asserted . in addition , in the oversize count mode , and gate 540 is inserted to pass on the continuation of line 522a the current video signal to the line - to - line memory 511 . it will be appreciated that in the count mode a direct connection is made from line 522 to line 522a . thus , no modified video signal will occur for a feature on line 533 until an oversize pulse first occurs on line 670 . when such a pulse does occur , storage will occur in line - to - line memory 511 at x - coordinates corresponding to the current video signal . on the next scan line the resulting delayed video on line 820 passes to line 522 to give a video signal corresponding to the full length of the previous intercept . as a result , storage data in line - to - line memory 511 will again correspond to a full length and current intercept . referring to the disclosure of fig2 of the beforementioned morton patent , the disclosed operation of the present invention results in a modified binary video on line 533 of fig5 which corresponds to the shaded area of the feature of fig2 except that the angle of the straight line starting at the point of the &# 34 ; first intercept accepted pulse &# 34 ; or first oversize pulse on line 670 will be horizontal and the line will be displaced downward by one scan line spacing . the benefits of this operation can be seen in fig3 of this disclosure . assuming an oversize count pulse first occurs at point 301 of feature 302 , the stored binary signal when applied to the reset scan line will be asserted from point 303 to 304 , thus producing a signal which overlaps the current video existing from point 305 to point 306 on line 311 and thereby ensuring that the feature does not break - up and produce multiple counts with individual counts from each projection . on features with extreme re - entrances , such as the one shown in fig3 multiple counts could occur unless the paralysis angle is effectively zero .