text: [ 0027 ] fig3 is a circuit diagram of a data output buffer that includes a driver driving control unit 100 for controlling an output of a data output driver 200 , which transmits read data to a data output terminal according to a control signal of the driver driving control unit 100 . the driver driving control unit 100 includes a fourth level shifter 111 and a second output control unit 112 . fourth level shifter 111 includes pmos transistors p 9 and p 10 having a cross coupled structure and nmos transistors n 11 and n 12 receiving an output enable signal oe and an inverted output enable signal / oe inverted by an inverter iv 5 , respectively . also , the second output control unit 112 includes an inverter iv 6 , a nand gate nd 1 and an inverter iv 7 . an inverter iv 6 inverts a deep power down signal dpd , a nand gate nd 1 performs a nand logic function on an inverted deep power down signal / dpd inverted through an inverter iv 6 and an output signal of the fourth level shifter 111 to produce an output control signal doff , and an inverter iv 7 inverts an output control signal doff of the nand gate nd 1 to produce an output control signal doffz . the second output control unit 112 for controlling an output of the data output driver 200 uses an external power voltage since all the internal power voltages are off upon a deep power down mode . further , the data output driver 200 includes a fifth level shifter 201 , a sixth level shifter 202 , a second pull - up control unit 203 , a second pull - down control unit 204 and a second output driver 205 . first , the fifth level shifter 201 includes pmos transistors p 11 and p 12 having a cross coupled structure , nmos transistors n 13 and n 14 for respectively receiving a data signal rdo and an inverted data signal / rdo inverted by an inverter iv 8 and a nmos transistor n 15 for controlling the output of the data signal rdo depending on an input of a pipe counter signal pcnt . also , the sixth level shifter 202 includes pmos transistors p 13 and p 14 having a cross coupled structure , nmos transistors n 16 and n 17 for respectively receiving the data signal rdo and the inverted data signal / rdo inverted by an inverter iv 9 and a nmos transistor n 18 for controlling an output of the data signal rdo depending on an input of the pipe counter signal pcnt . the second pull - up control unit 203 includes a pmos transistor p 15 for outputting a pull - up signal upz depending on the output control signal doffz applied from the second output control unit 112 in the driver driving control unit 100 . the second pull - down control unit 204 includes a nmos transistor p 19 for outputting a pull - down signal dn depending on the output control signal doff applied from the second output control unit 112 in the driver driving control unit 100 . the second output driver 205 includes a pmos transistor p 16 and a nmos transistor n 20 , and receives the pull - up signal upz and the pull - down signal dn to output an output data . an operation of the data output buffer having the construction illustrated in fig3 will be described with reference to the timing diagram of fig4 . first , in the case where the data output buffer is not the deep power down mode , and a read command read is inputted , the output enable signal oe is enabled to be high and the output of the fourth level shifter 111 becomes a high level . also , in the case where the data output buffer is in the deep power down mode , the deep power down signal dpd enabled to be hgih is inputted with low and is then inverted by the inverter iv 6 so that a signal of high is inputted to the nand gate nd 1 . the nand gate nd 1 in the second output control unit 112 performs a nand logic function on the signals from the fourth level shifter 111 and the inverter iv 6 to produce the output control signal doff with a low level . the output control signal doff is inputted to the inverter iv 7 and the output control signal doffz becomes a high level . therefore , the second pull - up unit 203 and the second pull - down unit 204 in the data output driver 200 are turned off depending on the output control signal doff and the output control signal doffz . also , the data signal rdo applied from a memory cell of a semiconductor device is applied to the output driver 205 through the fifth level shifter 201 and the sixth level shifter 202 , respectively , so that data is outputted by the output driver 205 . further , in the case where the data output buffer is not the deep power down mode , the deep power down signal dpd is inputted with low and a signal of high inverted by the inverter iv 6 is inputted to the nand gate nd 1 . also , in case of nop , when a command that does not include a read is inputted , the output enable signal oe is disabled to be low so that the output of the fourth level shifter 111 with a low level is inputted to the nand gate nd 1 of the second output control unit 112 . due to this operation , the nand gate nd 1 outputs a high signal as the output control signal doff and the output control signal doffz becomes low by the inverter iv 7 . therefore , a low signal is inputted to the second pull - up unit 203 in the data output driver 200 and a high signal is inputted to the second pull - down unit 204 , so that the pull - up signal upz and the pull - down signal dn are inputted with high and low , respectively . as a result , the pmos transistor p 16 and the nmos transistor n 20 in the output driver 205 are turned off so that the output data becomes a high impedance state . meanwhile , when the data output buffer is set into the deep power down mode , all the internal power voltages become off . if the deep power down signal dpd is enabled to high , a low signal is applied to the nand gate nd 1 via the inverter iv 6 . therefore , the nand gate nd 1 outputs a high signal as the output control signal doff and the output control signal doffz is inverted by the inverter iv 7 , which is then outputted as a low level . if the output control signal doff and the output control signal doffz in the second output control unit 112 become high and low respectively , the pmos transistor p 15 and the nmos transistor n 19 in the second pull - up control unit 203 and the second pull - down control unit 204 are turned on . if the pull - up signal upz having a high level is inputted to the pmos transistor p 16 of the output driver 205 and a pull - down signal dn having a low level is inputted to the nmos transistor n 20 of the output driver 205 , the pmos transistor p 16 and the nmos transistor n 20 are all turned off . therefore , upon a deep power down mode , it is possible to maintain the output of the output driver 205 at a high impedance state . as a result , upon a deep power down mode , it is possible to prevent the generation of unnecessary output data , thereby reducing consumption of current . [ 0034 ] fig5 is a circuit diagram of a data output buffer according to another embodiment of the disclosure . the data output buffer of fig5 includes a driver driving control unit 300 for controlling an output of a data output driver 400 , which transmits read data to a data output terminal depending on a control signal of the driver driving control unit 300 . the driver driving control unit 300 includes a seventh level shifter 301 and a third output control unit 302 . first , the seventh level shifter 301 includes pmos transistors p 17 and p 18 having a cross coupled structure , and nmos transistors n 21 and n 22 for respectively receiving an output enable signal oe and an output enable signal / oe inverted by an inverter iv 10 . also , the third output control unit 302 includes a nmos transistor n 23 and an inverter iv 11 connected between an output terminal of a seventh level shifter 301 and ground . the nmos transistor n 23 receives a deep power down signal dpd through its gate , and an inverter iv 11 inverts an output control signal doffz from the seventh level shifter 301 to produce an output control signal doff . further , the data output driver 400 includes an eighth level shifter 401 , a ninth level shifter 402 , a third pull - up control unit 403 , a third pull - down control unit 404 and a third output driver 405 . first , the eighth level shifter 401 includes pmos transistors p 19 and p 20 having a cross coupled structure , nmos transistors n 24 and n 25 for respectively receiving the data signal rdo and an inverted data signal / rdo inverted by an inverter iv 12 and a nmos transistor n 26 for controlling the output of the data signal rdo depending on an input of the pipe counter signal pcnt . also , the ninth level shifter 402 includes pmos transistors p 21 and p 22 having a cross coupled structure , nmos transistors n 27 and n 28 for respectively receiving the data signal rdo and an inverted data signal / rdo inverted by an inverter iv 13 and a nmos transistor n 29 for controlling the output of the data signal rdo depending on an input of the pipe counter signal pcnt . the third pull - up control unit 403 includes a pmos transistor p 23 for outputting a pull - up signal upz depending on an output control signal doffz applied from the third output control unit 302 of the driver driving control unit 300 . the third pull - down control unit 404 includes a nmos transistor p 30 for outputting a pull - down signal dn depending on the output control signal doff applied from the third output control unit 302 of the driver driving control unit 300 . the third output driver 405 includes a pmos transistor p 24 and a nmos transistor n 31 both of which are serially connected between the power voltage terminal and the ground voltage terminal . and pmos transistor p 24 receives the pull - up signal upz and a nmos transistor n 31 receives the pull - down signal dn to produce an output data . in the data output buffer having the construction of fig5 the deep power down signal dpd is enabled to be high so that the nmos transistor n 23 is turned on , upon the deep power down mode . at this time , the output control signal doffz is disabled to be at a low level and the output control signal doff is enabled to be at a high level by the inverter iv 11 . also , if a low level signal is inputted to the third pull - up unit 403 , the pmos transistor p 23 is turned on . further , if a high level signal is inputted to the third pull - down unit 404 , the nmos transistor n 30 is turned on . as a result , the pmos transistor p 24 and the nmos transistor n 31 in the output driver 405 are turned off by the pull - up signal upz and the pull - down signal dn so that the output of the output driver 405 can be maintained at a high impedance state during the deep power down mode . [ 0038 ] fig6 is a circuit diagram of a data output buffer according to still another embodiment of the disclosure . the data output driver 500 of fig6 includes a logic unit 501 , a fourth output control unit 502 and a fourth output driver 503 . a logic unit 501 logically combines the output control signal doff and the data signal do to output the pull - up signal upz and the pull - down signal dn , a fourth output control unit 502 controls the output of the output driver 503 depending on the pull - up signal upz and the pull - down signal dn applied from the logic unit 501 , and the deep power down signal dpd , and a fourth output driver 503 controls the output of the output data depending on a control signal from the fourth output control unit 502 . the logic unit 501 includes an inverter iv 14 , a nand gate nd 2 and a nor gate nor 1 . the inverter iv 14 inverts an output control signal doff , a nand gate nd 2 performs a nand logic function on a signal applied from the inverter iv 14 and the data signal do to output a pull - up signal upz , and a nor gate nor 1 performs a nor logic function on the output control signal doff and the data signal do to output a pull - down signal dn . also , the fourth output control unit 502 includes an inverter iv 15 , a pmos transistor p 25 and a nmos transistor n 32 . the inverter iv 15 inverts the deep power down signal dpd . a pmos transistor p 25 is connected between the power voltage terminal and the output terminal of the nand gate nd 2 and has a gate to which is inputted an inverted deep power down signal / dpd . nmos transistor n 32 is connected between an output terminal of the nor gate nor 1 and a ground voltage terminal and has a gate to which is inputted the deep power down signal dpd . further , the fourth output driver 503 includes a pmos transistor p 26 and a nmos transistor n 33 serially connected between the power voltage terminal and the ground voltage terminal . the fourth output driver 503 receives the pull - up signal upz and the pull - down signal dn from the fourth output control unit 502 via a gate of pmos transistor p 26 and a gate of nmos transistor n 33 , respectively , to produce an output data . the logic unit 501 with the above - described construction outputs the pull - up signal upz and the pull - down signal dn due to a logic combination of the output control signal doff and the data signal do . upon a deep power down mode , the deep power down signal dpd is enabled to be high . thus , the nmos transistor n 32 in the fourth output control unit 502 is turned on and the pmos transistor p 25 is turned off by the inverted deep power down signal / dpd inverted by the inverter iv 15 . therefore , a high signal is inputted to the pmos transistor n 26 of the output driver 503 and a low signal is inputted to the nmos transistor n 33 so that the output data can be kept at a high impedance state . as mentioned above , according to the present disclosure , the final driver of a data output driver is placed in an off state in a deep power down mode wherein all power voltage devices internally used are in off states in order to reduce the power consumption in a device using a low power . therefore , the presently disclosed devices can prevent a data problem at a data output terminal by placing the output data at a high impedance state and prevent unnecessary power consumption by preventing a formation of a current path . while the teachings of the invention have been explained with respect to particular examples , it will be apparent to - those of ordinary skill in the art that the scope of this patent is not limited to those examples . on the contrary , this patent covers all apparatuses and methods falling within the spirit and scope of the appended claims , either literally or under the doctrine of equivalents .