text: throughout the specification , like reference numerals refer to like elements . referring to the plan view of a liquid crystal display shown in fig1 , lcd 100 includes an lcd panel 30 comprised of a first substrate 10 , a second substrate 20 facing the first substrate 10 , and a liquid crystal layer ( not shown ) interposed between the first substrate and the second substrate . lcd panel 30 includes a display region da that displays an image and a first peripheral area pa 1 and a second peripheral area pa 2 that are adjacent to the display region da . in the display region da , a plurality of gate lines gl 1 - gln extend in a first direction d 1 and a plurality of data lines dl 1 - dlm extend in a second direction d 2 transverse to the first direction d 1 . pixel regions are formed in a matrix defined by the intersection gate lines and data lines . in the display region da , a plurality of repairing lines rl 1 - rln are formed in parallel with the plurality of gate lines gl 1 - gln . each of the pixel regions includes a thin film transistor ( tft ) 60 and a liquid crystal capacitor c 1 c connected thereto . in tft 60 , a gate electrode is connected to a corresponding gate line , a source electrode is connected to a corresponding data line , and a drain electrode is connected to the liquid crystal capacitor c 1 c . a first gate driving circuit 40 for sequentially outputting a gate driving signal to the plurality of gate lines gl 1 - gln is formed on the left area of the first peripheral area pa 1 , which is adjacent to the left end of the plurality of gate lines gl 1 - gln . a second gate driving circuit 45 is formed on the right - hand area of the first peripheral area pa 1 as a redundancy circuit for driving first gate driving circuit 40 via the right - hand end of the plurality of gate lines gl 1 - gln . in other words , the first gate driving circuit 40 and the second gate driving circuit 45 are arranged symmetrically in areas of the first peripheral area pa 1 located to the left and right of the display region da . the second peripheral area pa 2 is adjacent to one end of the plurality of data lines dl 1 - dlm . a data line driving chip 55 mounted on the second peripheral area pa 2 provides an image signal to the plurality of data lines dl 1 - dlm . a flexible printed circuit board 50 is attached to one side of the second peripheral area pa 2 and serves to electrically connect an external device ( not shown ) for driving the lcd panel 30 . the flexible printed circuit board 50 is electrically connected with the data driving chip 55 . the first gate driving circuit 40 and the second driving circuit 45 may be connected to the flexible printed circuit board 50 through the data driving chip 55 or connected directly to the flexible printed circuit board 50 . fig2 a is a block diagram of a first gate driving circuit 40 and a second gate driving circuit 45 of fig1 according to an embodiment of the present invention . referring to fig2 a , the first gate driving circuit 40 includes a shift register comprised of a plurality of stages src 1 - scrn + 1 cascade - connected with one another . in other words , the first gate driving circuit 40 includes first through n th stages src 1 - srcn for outputting a gate signal ( or scan signal ) to n gate lines gl 1 - gln and a “ dummy ” stage srcn + 1 which does not drive one of the gate lines but merely provides a control signal to a previous stage . each of the stages src 1 - scrn + 1 includes a first clock terminal ck 1 , a second clock terminal ck 2 , a first input terminal in 1 , a second input terminal in 2 , an output terminal out , and a ground voltage terminal vss . the first clock signal ckv is provided to the first clock terminal ck 1 of each of the odd - numbered stages src 1 , src 3 , . . . , srcn + 1 and a second clock signal ckvb having an inverted phase to the first clock signal ckv is provided to the first clock terminal ck 1 of each of even - numbered stages src 2 , src 4 , . . . , srcn . the second clock signal ckvb is provided to the second clock terminal ck 2 of each of the odd - numbered stages src 1 , src 3 , . . . , srcn + 1 and the first clock signal ckv is provided to the second clock terminal ck 2 of each of the even - numbered stages src 2 , src 4 , . . . , srcn . the output terminal out of each of the odd - numbered stages src 1 , src 3 , . . . , srcn + 1 outputs the first clock signal ckv and the output terminal out of each of the even - numbered stages src 2 , src 4 , . . . , srcn outputs the second clock signal ckvb . the output terminal out of each of the n stages src 1 - srcn is electrically connected to each of the corresponding gate lines gl 1 - gln included in the display region ( da of fig1 ). thus , the shift register sequentially drives the n gate lines gl 1 - gln . a signal output from the output terminal out of a previous stage is input to the first input terminal in 1 and a signal output from the output terminal of a next stage is input to the second input terminal in 2 . however , a scan trigger signal stv , instead of a signal output from a previous stage , is provided to the first input terminal in 1 of the first stage src 1 . in addition , the scan trigger signal stv , instead of a signal output from a next stage , is provided to the second input terminal in 2 of the ( n + 1 ) th stage srcn + 1 , which outputs its output signal to the second input terminal in 2 of the n th stage srcn . hereinafter , the structure and operation of each of the stages src 1 - srcn + 1 will be described . as mentioned above , each of the stages src 1 - srcn + 1 includes the first clock terminal ck 1 , the second clock terminal ck 2 , the first input terminal in 1 , the second input terminal in 2 , the output terminal out , and the ground voltage terminal vss . here , the first input terminal in 1 is connected to the output terminal out of a previous stage through a first input line il 1 , the second input terminal in 2 is connected to the output terminal out of a next stage through a second input line il 2 , the output terminal out of each of the stages src 1 - srcn are connected to the plurality of gate lines gl 1 - gln , respectively , and a ground voltage vss is input to the ground voltage terminal vss . more specifically , the first stage src 1 receives the first clock signal ckv externally supplied through the first clock terminal ck 1 , the second clock signal ckvb externally supplied through the second clock terminal ck 2 , the scan trigger signal stv through the first input terminal in 1 , and a second gate signal gout 2 , which is provided from the second stage src 2 via the second input line il 2 , through the second input terminal in 2 and outputs a first gate signal gout 1 for selecting the first gate line gl 1 through the output terminal out . the first gate signal gout 1 is also output to the first input terminal in 1 of the second stage src 2 via the first input line il 1 . the second stage src 2 receives the second clock signal ckvb externally supplied through the first clock terminal ck 1 , the first clock signal ckv externally supplied through the second clock terminal ck 2 , the first gate signal gout 1 , which is provided from the first stage src 1 via the first input line il 1 , through the first input terminal in 1 , and a third gate signal gout 3 , which is provided from the third stage src 3 via the second input line il 2 , through the second input terminal in 2 , and outputs the second gate signal gout 2 for selecting the second gate line gl 2 through the output terminal out . the second gate signal gout 2 is also output to the first input terminal in 1 of the third stage src 3 via the first input line il 1 . similarly , the n th stage srcn receives the second clock signal ckvb externally supplied through the first clock terminal ck 1 , the first clock signal ckv externally supplied through the second clock terminal ck 2 , an ( n − 1 ) th gate signal goutn − 1 , which is provided from the ( n − 1 ) th stage srcn − 1 via the first input line il 1 , through the first input terminal in 1 , and a ( n + 1 ) th gate signal goutn + 1 , which is provided from the ( n + 1 ) th stage srcn + 1 via the second input line il 2 , through the second input terminal in 2 , and outputs an nth gate signal goutn for selecting the n th gate line gln through the output terminal out . the n th gate signal goutn is also output to the first input terminal in 1 of the dummy stage srcn + 1 via the first input line il 1 . referring to fig2 a , the first gate driving circuit 40 and the second gate driving circuit 45 are symmetrically arranged to the left and right of the display region in which the plurality of gate lines gl 1 - gln are formed . in other words , the second gate driving circuit 45 includes another shift register having a plurality of stages src 1 ′- scrn + 1 ′ cascade - connected with one another . that is to say , the second gate driving circuit 45 includes first through n th stages src 1 ′- scrn + 1 ′ for outputting a gate signal ( or scan signal ) and a “ dummy ” stage srcn + 1 ′ whose output does not drive on of gate lines but instead merely provides a control signal to a previous stage . like each of the stages src 1 - srcn + 1 of the first gate driving circuit 40 , each of the stages src 1 ′- scrn + 1 ′ includes a first clock terminal ck 1 , a second clock terminal ck 2 , a first input terminal in 1 , a second input terminal in 2 , an output terminal out , and a ground voltage terminal vss . the signals ckv , ckvb , vss , and stv , which are the same as in the first gate driving circuit 40 , are provided to the second gate driving circuit 45 . the second gate driving circuit 45 has similar structure to that of the first gate driving circuit except that the output terminal out of each of the stages src 1 ′- scrn + 1 ′ is not electrically connected to any of the plurality of gate lines gl 1 - gln , respectively . it is preferable that a first input line il 1 ′ or a second input line il 2 ′ connected to the output terminal out of each of the stages src 1 ′- scrn + 1 ′ be arranged to overlap with the plurality of gate lines gl 1 - gln , respectively , in order to connect the plurality of gate lines gl 1 - gln and the first input lines il 1 ′ or the second input lines il 2 ′ of the stages src 1 ′- scrn + 1 ′. although the invention is described with regard to an example in which the plurality of gate lines gl 1 - gln overlap with the first input lines il1 ′ as shown in fig2 a , the present invention is not limited thereto and the plurality of gate lines gl 1 - gln may overlap with lines connected to the output terminal out of each of the stages src 1 ′- scrn + 1 ′. for example , as shown in fig2 b , the plurality of gate lines gl 1 - gln may overlap with the second input lines il 2 ′. fig2 b shows a modified example of fig2 a . hereinafter , the present invention will be described with reference to fig2 a for brevity . as shown in fig2 a , the plurality of repairing lines rl 1 - rln are arranged in parallel with the plurality of gate lines gl 1 - gln and are electrically disconnected from other lines , e . g ., the plurality of gate lines gl 1 - gln , the first input lines il 1 , the second input lines il 2 , the first input lines il 1 ′, and the second input lines il 2 ′. the plurality of repairing lines rl 1 - rln may be arranged to correspond respectively to the plurality of stages of the first gate driving circuit 40 and the second gate driving circuit 45 . it is preferable that the plurality of repairing lines rl 1 - rln overlap with the input lines il 1 and il 2 of the stages src 1 - srcn + 1 , respectively , and with the input lines il 1 ′ and il 2 ′ of the stages src 1 ′- scrn + 1 ′, respectively . in this way , the first gate driving circuit 40 is connected directly to the plurality of gate lines gl 1 - gln to sequentially output a gate driving signal , and the second gate driving circuit 45 is not connected directly to the plurality of gate lines gl 1 - gln , but is used , together with the plurality of repairing lines rl 1 - rln , as a redundancy circuit for the first gate driving circuit 40 to repair the lcd when a defect occurs in the first gate driving circuit 40 . hereinafter , the repairing method of the liquid crystal display device will be described with reference to fig1 a and 3 in detail . fig3 is a block diagram for explaining a method of repairing the first gate driving circuit and the second gate driving circuit of fig1 . in general , in a structure where a gate driving circuit is formed directly on an lcd panel using a plurality of amorphous - silicon thin film transistors ( a - si tfts ), it is difficult to repair an lcd when a defect occurs in the gate driving circuit . however , by symmetrically arranging the first gate driving circuit 40 and the second gate driving circuit 45 in areas of the first peripheral area pa 1 located to the left and right of the display region da of the lcd panel 30 and forming the plurality of repairing lines rl 1 - rln in parallel with the plurality of gate lines gl 1 - gln , the lcd 100 can be easily repaired . for example , when a defect occurs in the second stage src 2 of the first gate driving circuit 40 , the lcd 100 is repaired as follows . as shown in fig3 , the first repairing line rl 1 arranged between the second stage src 2 having a defect and the first stage src 1 intersects the first input line il 1 that connects the first input terminal in 1 of the second stage src 2 with the output terminal out of the first stage src 1 and intersects the first input line il 1 ′ that connects the first input terminal in 1 of the second stage src 2 ′ with the output terminal out of the first stage src 1 . here , an intersection “ a ” short - circuits the first repairing line rl 1 and the first input line il 1 of the second stage src 2 from each other using a laser beam , and an intersection “ b ” short - circuits the first repairing line rl 1 and the first input line il 1 ′ of the second stage src 2 ′ from each other . the intersections “ a ” and “ b ” perform short - circuiting using a laser beam . a spot “ c ” connecting the second gate line gl 2 and the output terminal out of the second stage src 2 is open - circuited using a laser beam . here , it is preferable that the spot “ c ” be positioned between a node connecting the second gate line gl 2 and the first input line il 1 and the output terminal out and between a node connecting the second gate line gl 2 and the second input line il 2 and the output terminal out . the second gate line gl 2 is electrically disconnected from and intersects a line connected to the output terminal out of the second stage src 2 ′. the line connected to the output terminal out of the second stage src 2 ′ may be the second input line il 2 ′ that connects the output terminal out of the second stage src 2 ′ with the second input terminal in 2 of the first stage src 1 ′ or the first input line il 1 ′ that connects the output terminal out of the second stage src 2 ′ with the first input terminal in 1 of the third stage src 3 ′. an intersection “ d ” short - circuits the line connected to the output terminal out of the second stage src 2 ′ and the second gate line gl 2 from each other using a laser beam . the second repairing line rl 2 arranged between the second stage src 2 and the third stage src 3 intersects the second input line il 2 that connects the second input terminal in 2 of the second stage src 2 with the output terminal out of the third stage src 3 and intersects the second input line il 2 ′ that connects the second input terminal in 2 of the second stage src 2 ′ with the output terminal out of the third stage src 3 ′. here , an intersection “ e ” connecting the second repairing line rl 2 and the second input line il 2 of the second stage src 2 and a intersection “ f ” connected the second repairing line rl 2 and the second input line il 2 ′ of the second stage src 2 ′ from each other using a laser beam . the repaired lcd operates as follows . the second stage src 2 ′ of the second gate driving circuit 45 operates instead of the defective second stage src 2 of the first gate driving circuit 40 . thus , the first gate signal gout 1 output from the first stage src 1 is provided to the first input terminal in 1 of the second stage src 2 ′ from the output terminal out of the first stage src 1 via the first input line il 1 , the intersection “ a ”, the first repairing line rl 1 , the intersection “ b ”, and the first input line il 1 ′. the second gate signal gout 2 output from the second stage src 2 ′ is provided to the first input terminal in 1 of the third stage src 3 from the output terminal out of the second stage src 2 ′ via the first input line il 1 ′, the intersection “ d ”, the second gate line gl 2 , and the first input line il 1 . the third gate signal gout 3 output from the third stage src 3 is provided to the second input terminal in 2 of the second stage src 2 ′ from the output terminal out of the third stage src 3 via the second input line il 2 , the intersection “ e ”, the second repairing line rl 2 , the intersection “ f ”, and the second input line il 2 ′. as such , the second stage src 2 ′ receives the first clock signal ckv externally supplied through the first clock terminal ck 1 , the second clock signal ckvb externally supplied through the second clock terminal ck 2 , the first gate signal gout 1 , which is provided from the first stage src 1 via the first repairing line rl 1 , through the first input terminal in 1 , and the third gate signal gout 3 , which is provided from the third stage src 3 via the second repairing line rl 2 , through the second input terminal in 2 , and outputs the second gate signal gout 2 for selecting the second gate line gl 2 through the output terminal out . the second gate signal gout 2 is also output to the first input terminal in 1 of the third stage src 3 through the first input line il 1 . in this way , a separate current path going round a stage having a defect is formed using the plurality of repairing lines rl 1 - rln , thereby easily repairing a defect of a gate driving circuit . while the present invention has been particularly shown and described with reference to exemplary embodiments thereof , it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims . therefore , it is to be understood that the above - described embodiments have been provided only in a descriptive sense and will not be construed as placing any limitation on the scope of the invention .