text: before a detailed description of this invention , prior - art apparatuses will be described for a better understanding of this invention . fig1 shows a prior - art ofdm signal transmitter . with reference to fig1 a digital information signal is fed via an input terminal to a serial - to - parallel ( s / p ) conversion circuit 70 . an error correction code may be added to the digital information signal . output signals from the s / p conversion circuit 70 are fed to an ifft ( inverse fast fourier transform ) circuit 71 . output signals from the ifft circuit 71 are fed via a guard interval circuit 72 to a d / a converter 73 . the output signals of the ifft circuit 71 are processed by the guard interval circuit 72 for reducing multipath effects . output signals of the guard interval circuit 72 are changed by the d / a converter 73 into corresponding analog signals . only components of the analog signals in a desired frequency band are passed through an lpf ( a low pass filter ) 74 . output analog signals from the lpf 74 which correspond to a real part and an imaginary part ( an i signal and a q signal ) are fed to a quadrature modulator 75 as baseband signals , being converted into an if ofdm ( intermediate frequency ofdm ) signal . the if ofdm signal has multiple if orthogonal carriers which are modulated as indications of the output baseband signals of the lpf 74 . the if ofdm signal is changed by a frequency converter 76 into an rf ofdm ( radio frequency ofdm ) signal in a desired frequency band for transmission . the rf ofdm signal has multiple rf orthogonal carriers which are modulated as indications of the output baseband signals of the lpf 74 . the rf ofdm signal is fed from the frequency converter 76 to a transmitting section 77 . the rf ofdm signal is transmitted via a linear amplifier and a transmission antenna composing the transmitting section 77 . an output signal of a local oscillator 78 which has a given frequency is fed to the quadrature modulator 75 and a 90 ° phase shifting circuit 78a . an output signal of the 90 ° phase shifting circuit 78a is fed to the quadrature modulator 75 . in this way , a pair of local oscillator signals having a quadrature relation are fed to the quadrature modulator 75 . the output signal of the local oscillator 78 is also fed to a clock signal generating circuit 79 . the circuit 79 generates clock signals in response to the output signal of the local oscillator 78 , and outputs the generated clock signals to the s / p conversion circuit 70 , the ifft circuit 71 , the guard interval circuit 72 , and the d / a converter 73 as operation timing control signals respectively . fig2 shows a prior - art ofdm signal receiver . with reference to fig2 a receiving section 80 includes a reception antenna which catches an rf ofdm signal transmitted from the ofdm signal transmitter of fig1 . the rf ofdm signal has multiple rf orthogonal carriers which are modulated in accordance with transmitted baseband signals respectively . the receiving section 80 includes an rf amplifier which enlarges the caught rf ofdm signal . an output rf ofdm signal from the rf amplifier in the receiving section 80 is fed to a frequency converter 81 , being converted into a corresponding if ofdm signal thereby . the if ofdm signal has multiple if orthogonal carriers which are modulated in accordance with transmitted baseband signals respectively . the if ofdm signal is fed from the frequency converter 81 to a quadrature demodulator 83 and a carrier detecting circuit 90 via an if amplifying circuit 82 . a local oscillator 89 reproduces a local oscillator signal in response to an output signal of the carrier detecting circuit 90 . the local oscillator signal is fed to the quadrature demodulator 83 and a 90 ° phase shifting circuit 89a . an output signal of the 90 ° phase shifting circuit 89a is fed to the quadrature demodulator 83 . in this way , a pair of reproduced local oscillator signals having a quadrature relation are fed to the quadrature demodulator 83 . the if ofdm signal is demodulated by the quadrature demodulator 83 into baseband signals corresponding to a real part and an imaginary part ( an i signal and a q signal ). output signals from the quadrature demodulator 83 are fed via an lpf 84 to an a / d converter 85 , being changed into corresponding digital signals thereby . one of the output signals from the quadrature demodulator 83 is fed to a sync signal generating circuit 91 . the circuit 91 reproduces and generates sync signals or clock signals in response to the output signal of the quadrature demodulator 83 . output signals from the a / d converter 85 are fed via a guard interval circuit 86 to an fft qam ( fast fourier transform , quadrature amplitude modulation ) decoding circuit 87 . the circuit 87 subjects output signals of the guard interval circuit 86 to processing which corresponds to complex fourier transform . according to the complex fourier transform processing , the circuit 87 derives the levels of baseband carriers in the real - part signal and the imaginary - part signal outputted from the guard interval circuit 86 . thus , the transmitted digital information is recovered . output signals of the fft qam decoding circuit 87 are fed to a parallel - to - serial ( p / s ) conversion circuit 88 . an output signal of the p / s conversion circuit 88 is fed to an external device ( not shown ) as an output signal of the prior - art ofdm signal receiver . the sync signals and the clock signals are fed from the sync signal generating circuit 91 to the a / d converter 85 , the guard interval circuit 86 , the fft qam decoding circuit 87 , and the p / s conversion circuit 88 as operation timing control signals respectively . in the prior - art ofdm signal transmitter of fig1 and the prior - art ofdm signal receiver of fig2 transmitted data can be accurately recovered by the receiver when the frequencies of the carriers in the receiver are exactly equal to the frequencies of the carriers in the transmitter . a difference in frequency between the output signal of a local oscillator in the frequency converter 76 in the transmitter and the output signal of a local oscillator in the frequency converter 81 in the receiver causes a disagreement between the carriers in the transmitter and the carriers in the receiver . in addition , a difference in frequency between the output signal of the local oscillator 78 in the transmitter and the output signal of the local oscillator 89 in the receiver causes a disagreement between the carriers in the transmitter and the carriers in the receiver . such a disagreement results in an increased symbol error rate related to data recovered by the receiver . in the prior - art ofdm signal transmitter of fig1 and the prior - art ofdm signal receiver of fig2 transmitted data can be accurately recovered by the receiver when the clock signal fed to the ifft circuit 71 in the transmitter accurately corresponds to the clock signal fed to the fft qam decoding circuit 87 in the receiver . a disagreement between the clock signal fed to the ifft circuit 71 and the clock signal fed to the fft qam decoding circuit 87 results in an increased symbol error rate related to data recovered by the receiver . fig3 shows a signal transmitting apparatus using orthogonal frequency division multiplexing ( ofdm ) according to a first embodiment of this invention . digital data transmitted by the signal transmitting apparatus of fig3 agrees with , for example , a compressed audio signal and a compressed video signal . ofdm uses multiple carriers having an orthogonal relationship with each other . in ofdm data transmission , independent digital information pieces are transmitted by using multiple carriers respectively . since the carriers are orthogonal with each other , the levels of the spectrums of carriers neighboring a given carrier are nullified at a point corresponding to the frequency of the given carrier . an ifft ( inverse fast fourier transform ) circuit is used to enable the generation of a set of multiple orthogonal carriers . a baseband ofdm signal can be generated by executing inverse discrete fourier transform ( inverse dft ) using n complex numbers during a time interval t . points of the inverse dft correspond to modulation signal outputs respectively . basic specifications of the signal transmitting apparatus of fig3 are as follows . the central carrier frequency in an rf band is equal to 100 mhz . the number of carriers for data transmission is equal to 248 . the modulation is of the 256 - qam ofdm type . the number of used carriers is equal to 257 . the transmission band width is equal to 100 khz . the used band width is equal to 99 khz . the transmission data rate is equal to 750 kbps . the guard interval is equal to 60 . 6 μsec . with reference to fig3 a digital information signal in the form of a bit stream is fed via an input terminal 1 to a serial - to - parallel ( s / p ) conversion circuit 2 . the digital information signal results from , for example , compressing an audio information signal or a video information signal according to an mpeg encoding process . an error correction code may be added to the digital information signal . the digital information signal , that is , the digital input signal , is divided by the s / p conversion circuit 2 into blocks corresponding to modulating signals for 256 qam . the s / p conversion circuit 2 outputs the modulating signals . according to 256 qam , 16 different levels are defined in an amplitude direction while 16 different levels are defined in an angle direction . in addition , 256 different digital states are assigned to the 256 levels ( 16 levels multiplied by 16 levels ) respectively . as previously described , 248 carriers among 257 carriers are used for transmitting data information . the 9 remaining carriers are used for transmitting calibration signals and other helper signals ( other auxiliary signals ). the s / p conversion circuit 2 outputs 248 - byte digital data for every 1 - symbol interval . in more detail , the s / p conversion circuit 2 outputs a first set of 248 parallel digital signals each having 4 bits , and a second set of 248 parallel digital signals each having 4 bits for every 1 - symbol interval . the first set and the second set correspond to a real part and an imaginary part ( an i signal and a q signal ) respectively . the 248 output signals from the s / p conversion circuit 2 in each of the real part and the imaginary part are fed to a combination 3 of an ifft ( inverse fast fourier transform ) circuit and a pilot signal generating circuit . the ifft and pilot signal generating circuit 3 operates in response to a clock signal fed from a clock signal generating circuit 10 . regarding each of the real part and the imaginary part , the operation of the ifft and pilot signal generating circuit 3 corresponds to subjecting 248 carriers to 256 qam responsive to the 248 output signals from the s / p conversion circuit 2 respectively . the ifft and pilot signal generating circuit 3 generates the 248 modulation - resultant signals in each of the real part and the imaginary part . the ifft and pilot signal generating circuit 3 combines the 248 modulation - resultant signals of the real part into a multiplexing - resultant signal corresponding to the real part . also , the ifft and pilot signal generating circuit 3 combines the 248 modulation - resultant signals of the imaginary part into a multiplexing - resultant signal corresponding to the imaginary part . in the ifft and pilot signal generating circuit 3 , discrete frequency points corresponding to the respective carriers are generated in response to the clock signal fed from the clock signal generating circuit 10 . discrete frequency point information is transmitted as nyquist frequency information representing a value equal to a half of a period n . since the nyquist frequency information agrees with a half of the discrete frequency point information in period , a sample position signal for operating an fft ( fast fourier transform ) circuit can be generated in a receiver side by reproducing the nyquist frequency information and executing a frequency multiplying process ( a frequency doubling process ). the nyquist frequency information is generated or added by applying a given - level signal to an n / 2 real - part input terminal r ( and / or an n / 2 imaginary - part input terminal i ) of the ifft and pilot signal generating circuit 3 . for example , the given - level signal is produced by a suitable signal generator provided in the ifft and pilot signal generating circuit 3 . the output signals of the ifft and pilot signal generating circuit 3 are fed to a guard interval setting circuit 4 including a ram ( random access memory ) 4a . as shown in fig4 the guard interval setting circuit 4 provides a guard interval &# 34 ; gi &# 34 ; of a given length for every symbol of the output signals of the ifft and pilot signal generating circuit 3 . specifically , each guard interval &# 34 ; gi &# 34 ; has a temporal length of 60 . 6 μsec . in addition , each transmission symbol interval &# 34 ; ta &# 34 ; is composed of a guard interval &# 34 ; gi &# 34 ;, and an effective symbol interval &# 34 ; ts &# 34 ; following the guard interval &# 34 ; gi &# 34 ;. each transmission symbol interval &# 34 ; ta &# 34 ; corresponds to 2646 . 6 μsec while each effective symbol interval &# 34 ; ts &# 34 ; corresponds to 2586 μsec . the guard intervals are designed to reduce multipath distortions caused by a transmission line . the guard interval setting circuit 4 operates in response to a clock signal fed from the clock signal generating circuit 10 . in the guard interval setting circuit 4 , final portions of the output signals of the ifft and pilot signal generating circuit 3 in every window interval ( every symbol interval ) are copied , and the copy - resultant signal portions are moved to temporal positions immediately preceding window interval signals ( effective symbol interval signals ). to implement the above - indicated process , the guard interval setting circuit 4 functions as follows . specifically , the output signals of the ifft and pilot signal generating circuit 3 are stored , sequentially sample by sample , into the ram 4a for every window interval ( every symbol interval ). then , finally - stored portions of the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a so that signals occupying a guard interval &# 34 ; gi &# 34 ; are generated . subsequently , the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a in a sequence starting from the firstly - stored portions thereof so that signals occupying an effective symbol interval &# 34 ; ts &# 34 ; are generated . the previously - indicated nyquist frequency information can be transmitted by using not only an effective symbol interval but also a guard interval . regarding the nyquist frequency information , to maintain the continuity with preceding and following ifft window interval signals , it is preferable that the pilot signal corresponding to one wavelength multiplied by a given integer is present in a guard interval . in this case , the pilot signal in a symbol interval is continuously present over a guard interval and an effective symbol interval . thus , an actually - transmitted pilot signal , that is , the pilot signal up - converted into a transmission rf range , has a monochromatic frequency spectrum ( a single - line frequency spectrum ). in this embodiment , the pilot signal has the nyquist frequency . it should be noted that the frequency of the pilot signal may differ from the nyquist frequency as long as there is a relation in frequency between the pilot signal and the sample position signal which is denoted by a simple ratio between integers . the pilot signal may use transmitted highest - frequency information . in the case of ifft having a period m , a pilot signal is located at a frequency position equal to a half of a nyquist frequency corresponding to each of a period m / 4 and a period 3m / 4 . in addition , carriers transmitted bit ofdm use those corresponding to first to m / 4 - th output signals from the ifft , and those corresponding to 3m / 4 - th to m - th output signals from the ifft . thus , it is possible to generate signals equivalent to those generated in the case of m = 2n . accordingly , a continuous pilot signal can be transmitted by using an effective symbol interval as well as a guard interval . the sample position signal can be generated by recovering the pilot signal and multiplying the frequency of the recovered pilot signal by 4 . in the case where window interval signal information of fft can be recovered separately , fft calculations for an ofdm signal can be implemented by combining the window interval signal information and the sample position signal . thus , in this case , the ofdm signal can be decoded . a description will now be given of a symbol interval &# 34 ; ta &# 34 ; related to the guard interval setting circuit 4 . in the case where the used frequency band is equal to 99 khz and the period n is given as n = 256 , an effective symbol frequency &# 34 ; fs &# 34 ; and an effective symbol period &# 34 ; ts &# 34 ; are expressed as follows . when the guard interval &# 34 ; gi &# 34 ; for removing multipath effects is set to six times the sample period ( six times the reciprocal of the used frequency band ), the guard interval &# 34 ; gi &# 34 ; is given as follows . in this case , the symbol interval &# 34 ; ta &# 34 ; and the symbol frequency &# 34 ; fa &# 34 ; are given as follows . output signals of the guard interval setting circuit 4 are fed to a d / a converter 5 , being converted into corresponding analog signals thereby . the d / a converter 5 outputs the resultant analog signals to an lpf ( a low pass filter ) 6 . only components of the output signals of the d / a converter 5 in a desired frequency band are passed through the lpf 6 . output signals of the lpf 6 which correspond to the real part and the imaginary part are fed to a quadrature modulator 7 as baseband signals . a local oscillator 9 outputs a given - frequency signal , for example , a 10 . 7 - mhz signal , to the quadrature modulator 7 . the frequency of the output signal of the local oscillator 9 corresponds to a given intermediate frequency ( if ). the local oscillator 9 also outputs the given - frequency signal to a 90 ° phase shifting circuit 8 . the circuit 8 shifts the phase of the given - frequency signal by 90 °, and outputs the phase - shift resultant signal to the quadrature modulator 7 . in this way , a pair of given - frequency signals having a quadrature relation are fed to the quadrature modulator 7 . in the quadrature modulator 7 , the quadrature given - frequency signals are modulated in accordance with the baseband signals outputted from the lpf 6 so that the baseband signals are converted into an if ofdm ( intermediate frequency ofdm ) signal . the if ofdm signal has multiple if orthogonal carriers which are modulated as indications of the output baseband signals of the lpf 6 . the if ofdm signal is changed by a frequency converter 11 into an rf ofdm ( radio frequency ofdm ) signal in a desired frequency band for transmission . the rf ofdm signal has multiple rf orthogonal carriers which are modulated as indications of the output baseband signals of the lpf 6 respectively . the frequency converter 11 includes a local oscillator and a mixer . in the frequency converter 11 , the if ofdm signal and the output signal of the local oscillator are mixed by the mixer so that the if ofdm signal is converted into the rf ofdm signal . the rf ofdm signal is fed to a transmitting section 12 from the frequency converter 11 . the transmitting section 12 includes a linear power amplifier and a transmission antenna . the rf ofdm signal is fed via the linear power amplifier to the transmission antenna , being radiated by the transmission antenna into a transmission line ( the air ). the output signal of the local oscillator 9 is also fed to the clock signal generating circuit 10 . the circuit 10 generates clock signals in response to the output signal of the local oscillator 9 by frequency dividing processes , and outputs the generated clock signals to the s / p conversion circuit 2 , the ifft and pilot signal generating circuit 3 , the guard interval setting circuit 4 , and the d / a converter 5 as operation timing control signals respectively . in this embodiment , during every 1 - symbol period , 248 parallel digital data pieces each having 8 bits ( 4 bits plus 4 bits ) are transmitted together with 248 carriers . accordingly , the transmission data rate corresponds to 248 bytes per symbol interval . thus , the transmission data rate per second is approximately equal to 750 kilo - bits . fig5 shows a signal receiving apparatus using orthogonal frequency division multiplexing ( ofdm ) according to a second embodiment of this invention . the signal receiving apparatus of fig5 is able to accept an rf ofdm signal transmitted by the signal transmitting apparatus of fig3 . with reference to fig5 a receiving section 20 includes a reception antenna which catches an rf ofdm signal transmitted from , for example , the signal transmitting apparatus of fig3 . the rf ofdm signal has multiple rf orthogonal carriers which are modulated in accordance with transmitted baseband signals respectively . the receiving section 20 includes an rf amplifier which enlarges the caught rf ofdm signal . an output rf ofdm signal from the rf amplifier in the receiving section 20 is fed to a frequency converter 21 , being converted into a corresponding if ofdm signal thereby . the if ofdm signal has multiple if orthogonal carriers which are modulated in accordance with transmitted baseband signals respectively . the frequency converter 21 includes a local oscillator and a mixer . in the frequency converter 21 , the rf ofdm signal and the output signal of the local oscillator are mixed by the mixer so that the rf ofdm signal is converted into the if ofdm signal . the if ofdm signal is fed from the frequency converter 21 to an if amplifying circuit 22 , being enlarged to a desired level thereby . the output if ofdm signal from the if amplifying circuit 22 is fed to a quadrature demodulator 23 and a carrier detecting circuit 29 . the carrier detecting circuit 29 includes a pll ( phase locked loop ) circuit having a combination of a phase comparator ( a multiplier ), an lpf , a vco ( a voltage - controlled oscillator ), and a 1 / 4 frequency divider . the pll circuit recovers the carriers in the if ofdm signal . an output signal of the carrier detecting circuit 29 , which corresponds to the recovered carriers , is fed to a local oscillator 31 . the local oscillator 31 is designed to extract the central carrier among the carriers in the if ofdm signal with a negligible phase error . the local oscillator 31 outputs a signal corresponding to the extracted central carrier . thus , the local oscillator 31 reproduces a local oscillator signal used in a transmitter side . in this embodiment , the if ofdm signal ( or the rf ofdm signal ) is based on the information - transmitting carriers with frequencies which are spaced at intervals of 378 hz equal to the symbol frequency . the frequencies of the information carriers neighboring the central carrier are spaced from the frequency of the central carrier by only 378 hz . accordingly , it is preferable that the extraction of the central carrier is executed by a high - selectivity circuit . the local oscillator 31 uses a high - selectivity circuit . specifically , the local oscillator 31 includes a pll circuit for extracting the central carrier from the carriers outputted by the carrier detecting circuit 29 . a voltage - controlled oscillator ( vco ) in the pll circuit in the local oscillator 31 uses a voltage - controlled crystal oscillator ( vcxo ) which can oscillate at a frequency variable in a given small range ( for example , ± 200 hz ) around the frequency of the central carrier . in addition , an lpf in the pll circuit has a cut - off frequency adequately low with respect to 378 hz . the output signal of the local oscillator 31 is fed to the quadrature demodulator 23 . the output signal of the local oscillator 31 is also fed to a 90 ° phase shifting circuit 30 . the circuit 30 shifts the phase of the output signal of the local oscillator 31 by 90 °. the phase - shift resultant signal is outputted from the circuit 30 to the quadrature demodulator 23 . in this way , a pair of reproduced local oscillator signals having a quadrature relation are fed to the quadrature demodulator 23 . in response to the quadrature signals , the if ofdm signal is demodulated by the quadrature demodulator 23 into baseband signals corresponding to a real part and an imaginary part ( an i signal and a q signal ) respectively . output signals from the quadrature demodulator 23 are fed to an lpf 24 . only components of the output signals of the quadrature demodulator 23 , which occupy a desired frequency band , are passed through the lpf 24 . output signals of the lpf 24 which have analog forms are fed to an a / d converter 25 . the output signals of the lpf 24 are subjected to sampling processes and are converted by the a / d converter 25 into corresponding digital signals . one of the output signals of the quadrature demodulator 23 is fed to a sample sync signal generating circuit 32 . the output signal of the local oscillator 31 is fed to the sample sync signal generating circuit 32 . the sample sync signal generating circuit 32 includes a pll circuit phase - locked with respect to a pilot signal in the output signal of the quadrature demodulator 23 . it should be noted that the pilot signal is transmitted as a continuous signal during every symbol interval containing a guard interval . the sample sync signal generating circuit 32 derives pilot signal frequency information , and reproduces the pilot signal . in a transmitter side , the frequency of the pilot signal is set to correspond to a given ratio between integers with respect to the frequency of the sample clock signal . the sample sync signal generating circuit 32 includes a frequency multiplier operating on the reproduced pilot signal at a multiplying factor corresponding to the above - indicated frequency ratio . a sample clock signal ( a clock sync signal ) is recovered through the frequency multiplication . the output signals of the a / d converter 25 are fed to a guard interval processing circuit 26 . the guard interval processing circuit 26 extracts time - portions of the output signals of the a / d converter 25 which occupy every effective symbol interval . output signals of the guard interval processing circuit 26 are fed to an fft qam ( fast fourier transform , quadrature amplitude modulation ) decoding circuit 27 . a symbol sync signal generating circuit 33 connected to the sample sync signal generating circuit 32 detects a symbol interval in response to the sample clock signal , and generates a symbol sync signal related to the detected symbol interval . the fft qam decoding circuit 27 receives the clock sync signal and the symbol sync signal from the sample sync signal generating circuit 32 and the symbol sync signal generating circuit 33 . in response to the clock sync signal and the sample sync signal , the circuit 27 subjects the output signals of the guard interval processing circuit 26 to processing which corresponds to complex fourier transform . according to the complex fourier transform processing , the circuit 27 derives the levels of baseband carriers in the real - part signal and the imaginary - part signal outputted from the guard interval processing circuit 26 . in the fft qam decoding circuit 27 , the derived real - part levels and the derived imaginary - part levels are compared with reference demodulation output levels so that the states of transmitted digital signals are determined . in this way , the transmitted digital information is recovered . output signals of the fft qam decoding circuit 27 which correspond to the recovered digital signals are fed to a parallel - to - serial ( p / s ) conversion circuit 28 . the output signals of the fft qam decoding circuit 27 are rearranged and combined by the p / s conversion circuit 28 into a serial - form digital signal . the serial - form digital signal is transmitted from the p / s conversion circuit 28 to an external device ( not shown ) via an output terminal 34 . the sample sync signal generating circuit 32 and the symbol sync signal generating circuit 33 produce sync signals and clock signals in response to the output signal of the quadrature demodulator 23 and the output signal of the local oscillator 31 , and feed the produced sync signals and the produced clock signals to the a / d converter 25 , the guard interval processing circuit 26 , the fft qam decoding circuit 27 , and the p / s conversion circuit 28 as operation timing control signals . the pilot signal in the output signal of the quadrature demodulator 23 is continuous , and is free from jitter components . therefore , the pilot signal is recovered without jitter , and the sample clock signal is accurately reproduced in response to the recovered pilot signal . the clock signal fed to the fft qam decoding circuit 27 in the receiver side accurately corresponds to the clock signal fed to the the ifft and pilot signal generating circuit 3 in the transmitter side . thus , the fft process in the receiver side can be exactly inverse with the ifft process in the transmitter side so that the transmitted data can be accurately recovered in the receiver side . fig6 shows a portion of a signal receiving apparatus using orthogonal frequency division multiplexing ( ofdm ) according to a third embodiment of this invention . the signal receiving apparatus of fig6 is similar to the signal receiving apparatus of fig5 except for design changes indicated later . the signal receiving apparatus of fig6 includes the following circuits in place of the quadrature demodulator 23 , the carrier detecting circuit 29 , the 90 ° phase shifting circuit 30 , the local oscillator 31 , and the sample sync signal generating circuit 32 of fig5 . with reference to fig6 a multiplier 41 , an lpf 42 , a vco circuit 43 , and a 1 / 4 frequency divider 45 compose a pll circuit serving as a carrier extracting circuit . the vco circuit 43 is designed to oscillate at and around a frequency ( 42 . 8 mhz ) equal to four times the central intermediate - frequency ( 10 . 7 mhz ). the vco circuit 43 output quadrature oscillation signals to a 1 / 4 frequency divider 44 and the 1 / 4 frequency divider 45 respectively . the devices 44 and 45 divide the frequencies of the output signals of the vco circuit 43 by four respectively . the output signal of the frequency divider 44 is fed to a multiplier 40 . the output signal of the frequency divider 45 is fed to the multiplier 41 . the if ofdm signal outputted from the if amplifying circuit 22 ( see fig5 ) is applied to the multipliers 40 and 41 . the multipliers 40 and 41 compose a quadrature demodulator . the multipliers 40 and 41 mix the if ofdm signal with the output signals of the 1 / 4 frequency dividers 44 and 45 so that the if ofdm signal is demodulated into baseband signals corresponding to a real part and an imaginary part respectively . the output signal of the multiplier 41 which corresponds to the imaginary part is fed via the lpf 42 to the vco circuit 43 as a control signal . as previously described , the multiplier 41 , the lpf 42 , the vco circuit 43 , and the 1 / 4 frequency divider 45 compose a pll circuit which is locked with respect to the central carrier in the if ofdm signal . the vco circuit 43 outputs a signal with a fixed frequency ( a locked frequency ) equal to four times the central intermediate - frequency ( 10 . 7 mhz ). the locked - frequency signal is fed from the vco circuit 43 to a variable frequency divider 50 . a variable frequency divider 50 receives the locked - frequency signal from the vco circuit 43 . the device 50 divides the frequency of the output signal of the vco circuit 43 by a value variable in the rage of 1 / 426 to 1 / 438 . the output signal of the variable frequency divider 50 is fed to a 1 / 2 frequency divider 51 . the 1 / 2 frequency divider 51 halves the frequency of the output signal of the variable frequency divider 50 . the output signal of the 1 / 2 frequency divider 51 is applied to a multiplier 52 . in addition , the output signal of the multiplier 40 which corresponds to the real part is applied to the multiplier 52 . the multiplier 52 serves as a phase comparator operating on the output signals of the multiplier 40 and the 1 / 2 frequency divider 51 . the output signal of the multiplier 52 is fed via an lpf 53 to a delay circuit 54 and an adding circuit 55 . the lpf 53 serves to pass only components of the output signal of the multiplier 52 which correspond to a phase error signal effective in frequency control . the circuit 54 delays the output signal of the lpf 53 by a given time . the circuit 54 outputs the delay - resultant signal to the adding circuit 55 . the circuit 55 adds the output signal of the lpf 53 , that is , the non - delayed signal , and the delayed signal fed from the circuit 54 . the delay circuit 54 and the adding circuit 55 compose a filter which is designed to attenuate neighboring carrier components . the frequency response characteristics of the filter have a dip point at 387 hz corresponding to a symbol frequency . the output signal of the adding circuit 55 is fed to the variable frequency divider 50 as a control signal . the variable frequency divider 50 serves as a vco circuit . the vco circuit 50 , the 1 / 2 frequency divider 51 , the multiplier 52 , the lpf 53 , the delay circuit 54 , and the adding circuit 55 compose a pll circuit locked with respect to a continuous pilot signal in the output signal of the multiplier 40 in the quadrature demodulator . thus , the vco circuit 50 outputs a sample clock signal in response to the reproduced pilot signal ( the recovered pilot signal ). the sample clock signal has a frequency of 99 khz . a fourth embodiment of this invention relates to a modification of the signal transmitting apparatus of fig3 and a modification of the signal receiving apparatus of fig5 or fig6 . the fourth embodiment executes ifft having a period n equal to 512 . in the fourth embodiment , a pilot signal frequency is set to a given high - order frequency having a preset relation with a sample position signal which is denoted by a simple ratio between integers . in the case of ifft having a period m , a pilot signal is located at a frequency position equal to a half of a nyquist frequency corresponding to each of a period m / 4 and a period 3m / 4 . in addition , carriers transmitted by ofdm use those correspond to first to m / 4 - th output signals from the ifft , and those corresponding to 3m / 4 - th to moth output signals from the ifft . thus , it is possible to generate signals equivalent to those generated in the case of m = 2n . accordingly , a continuous pilot signal can be transmitted by using an effective symbol interval as well as a guard interval . the sample position signal can be generated by recovering the pilot signal and multiplying the frequency of the recovered pilot signal by 4 . in the fourth embodiment , the frequency of a sample clock signal for driving the fft qam decoding circuit 27 is equal to 198 khz . accordingly , in the fourth embodiment , the variable frequency divider 50 is designed to provide a frequency division factor variable in the rage of 1 / 213 to 1 / 219 , and the frequency divider 51 is designed to provide a frequency division factor of 1 / 4 . a fifth embodiment of this invention is similar to the first embodiment thereof except that the guard interval setting circuit 4 ( see fig3 ) is modified to provide the following processes . the output signals of the ifft and pilot signal generating circuit 3 ( see fig3 ) are fed to the guard interval setting circuit 4 including the ram 4a ( see fig3 ). as shown in fig7 the guard interval setting circuit 4 provides a guard interval &# 34 ; g &# 34 ; of a given length for every symbol of the output signals of the ifft and prior signal generating circuit 3 . each transmission symbol interval is composed of a guard interval &# 34 ; g &# 34 ;, and an effective symbol interval &# 34 ; ifft &# 34 ; following the guard interval &# 34 ; g &# 34 ;. the effective symbol interval &# 34 ; ifft &# 34 ; is also referred to as the ifft interval . the guard interval setting circuit 4 operates in response to a clock signal fed from the clock signal generating circuit 10 ( see fig3 ). in the guard interval setting circuit 4 , final portions of the output signals of the ifft and pilot signal generating circuit 3 in every window interval ( every symbol interval ) are copied , and the copy - resultant signal portions are moved to temporal positions immediately preceding window interval signals ( effective symbol interval signals ). to implement the above - indicated process , the guard interval setting circuit 4 functions as follows . specifically , the output signals of the ifft and pilot signal generating circuit 3 are stored , sequentially sample by sample , into the ram 4a for every window interval ( every symbol interval ). then , finally - stored portions of the output signals of the ifft and pilot signal generating circuit 3 which correspond to one cycle or one wavelength are read out from the ram 4a so that signals occupying a guard interval &# 34 ; g &# 34 ; are generated . subsequently , the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a in a sequence starting from the firstly - stored portions thereof so that signals occupying an effective symbol interval &# 34 ; ifft &# 34 ; following the previously - indicated guard interval &# 34 ; g &# 34 ; are generated . as shown in fig7 pilot signals ( sync signals ) are generated at equal phases for ifft intervals respectively . to this end , a voltage signal applied to a given input terminal of the ifft and pilot signal generating circuit 3 is held constant for ifft intervals . the given input terminal corresponds to the pilot signal frequency ( the sync signal frequency ). furthermore , the pilot signal ( the sync signal ) corresponding to one wavelength multiplied by a given integer is present in every ifft interval while the pilot signal ( the sync signal ) corresponding to one wavelength is present in every guard interval &# 34 ; g &# 34 ;. accordingly , the pilot signal is continuously present over a plurality of successive transmission symbol intervals . thus , an actually - transmitted pilot signal , that is , the pilot signal up - converted into a transmission rf range , has a monochromatic frequency spectrum ( a single - line frequency spectrum ). it should be noted that the pilot signal ( the sync signal ) corresponding to one wavelength multiplied by a given integer may be present in every guard interval &# 34 ; g &# 34 ;. a sixth embodiment of this invention is similar to the first embodiment thereof except that an arrangement including the guard interval setting circuit 4 ( see fig3 ) is modified to provide the following processes . the output signals of the ifft and pilot signal generating circuit 3 ( see fig3 ) are fed to the guard interval setting circuit 4 including the ram 4a ( see fig3 ). as shown in fig8 the guard interval setting circuit 4 provides a guard interval &# 34 ; g &# 34 ; of a given length for every symbol of the output signals of the ifft and pilot signal generating circuit 3 . each transmission symbol interval is composed of a guard interval &# 34 ; g &# 34 ;, and an effective symbol interval &# 34 ; ifft &# 34 ; following the guard interval &# 34 ; g &# 34 ;. the effective symbol interval &# 34 ; ifft &# 34 ; is also referred to as the ifft interval . the guard interval setting circuit 4 operates in response to a clock signal fed from the clock signal generating circuit 10 ( see fig3 ). in the guard interval setting circuit 4 , final portions of the output signals of the ifft and pilot signal generating circuit 3 in every window interval ( every symbol interval ) are copied , and the copy - resultant signal portions are moved to temporal positions immediately preceding window interval signals ( effective symbol interval signals ). to implement the above - indicated process , the guard interval setting circuit 4 functions as follows . specifically , the output signals of the ifft and pilot signal generating circuit 3 are stored , sequentially sample by sample , into the ram 4a for every window interval ( every symbol interval ). then , finally - stored portions of the output signals of the ifft and pilot signal generating circuit 3 which correspond to a half cycle or a half wavelength are read out from the ram 4a so that signals occupying a guard interval &# 34 ; g &# 34 ; are generated . subsequently , the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a in a sequence starting from the firstly - stored portions thereof so that signals occupying an effective symbol interval &# 34 ; ifft &# 34 ; following the previously - indicated guard interval &# 34 ; g &# 34 ; are generated . as shown in fig8 pilot signals ( sync signals ) are generated alternately at opposite phases for ifft intervals . to this end , a voltage signal applied to a given input terminal of the ifft and pilot signal generating circuit 3 is alternately changed for ifft intervals . the given input terminal corresponds to the pilot signal frequency ( the sync signal frequency ). furthermore , the pilot signal ( the sync signal ) corresponding to one wavelength multiplied by a given integer is present in every ifft interval while the pilot signal ( the sync signal ) corresponding to a half wavelength is present in every guard interval &# 34 ; g &# 34 ;. accordingly , the pilot signal is continuously present over a plurality of successive transmission symbol intervals . thus , an actually - transmitted pilot signal , that is , the pilot signal up - converted into a transmission rf range , has a monochromatic frequency spectrum ( a single - line frequency spectrum ). it should be noted that the pilot signal ( the sync signal ) corresponding to a half wavelength multiplied by a given odd integer may be present in every guard interval &# 34 ; g &# 34 ;. a seventh embodiment of this invention is similar to the first embodiment thereof except that the guard interval setting circuit 4 ( see fig3 ) is modified to provide the following processes . the output signals of the ifft and pilot signal generating circuit 3 ( see fig3 ) are fed to the guard interval setting circuit 4 including the ram 4a ( see fig3 ). as shown in fig9 the guard interval setting circuit 4 provides a guard interval &# 34 ; g &# 34 ; of a given length for every symbol of the output signals of the ifft and pilot signal generating circuit 3 . each transmission symbol interval is composed of a guard interval &# 34 ; g &# 34 ;, and an effective symbol interval &# 34 ; ifft &# 34 ; following the guard interval &# 34 ; g &# 34 ;, the effective symbol interval &# 34 ; ifft &# 34 ; is also referred to as the ifft interval . the guard interval setting circuit 4 operates in response to a clock signal fed from the clock signal generating circuit 10 ( see fig3 ). in the guard interval setting circuit 4 , final portions of the output signals of the ifft and pilot signal generating circuit 3 in every window interval ( every symbol interval ) are copied , and the copy - resultant signal portions are moved to temporal positions immediately preceding window interval signals ( effective symbol interval signals ). to implement the above - indicated process , the guard interval setting circuit 4 functions as follows . specifically , the output signals of the ifft and pilot signal generating circuit 3 are stored , sequentially sample by sample , into the ram 4a for every window interval ( every symbol interval ). then , finally - stored portions of the output signals of the ifft and pilot signal generating circuit 3 which correspond to a half cycle or a half wavelength are read out from the ram 4a so that signals occupying a guard interval &# 34 ; g &# 34 ; are generated . subsequently , the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a in a sequence starting from the firstly - stored portions thereof so that signals occupying an effective symbol interval &# 34 ; ifft &# 34 ; following the previously - indicated guard interval &# 34 ; g &# 34 ; are generated . as shown in fig9 pilot signals ( sync signals ) are generated at equal phases for ifft intervals respectively . to this end , a voltage signal applied to a given input terminal of the ifft and pilot signal generating circuit 3 is held constant for ifft intervals . the given input terminal corresponds to the pilot signal frequency ( the sync signal frequency ). furthermore , the pilot signal ( the sync signal ) corresponding to one wavelength multiplied by a given integer is present in every ifft interval while the pilot signal ( the sync signal ) corresponding to a half wavelength is present in every guard interval &# 34 ; g &# 34 ;. as shown in fig9 the phase of the pilot signal ( the sync signal ) is inverted each time an ifft interval is replaced by a guard interval &# 34 ; g &# 34 ;. it should be noted that the pilot signal ( the sync signal ) corresponding to a half wavelength multiplied by a given odd integer may be present in every guard interval &# 34 ; g &# 34 ;. an eighth embodiment of this invention is similar to the first embodiment thereof except that an arrangement including the guard interval setting circuit 4 ( see fig3 ) is modified to provide the following processes . the output signals of the ifft and pilot signal generating circuit 3 ( see fig3 ) are fed to the guard interval setting circuit 4 including the ram 4a ( see fig3 ). as shown in fig1 , the guard interval setting circuit 4 provides a guard interval &# 34 ; g &# 34 ; of a given length for every symbol of the output signals of the ifft and pilot signal generating circuit 3 . each transmission symbol interval is composed of a guard interval &# 34 ; g &# 34 ;, and an effective symbol interval &# 34 ; ifft &# 34 ; following the guard interval &# 34 ; g &# 34 ;. the effective symbol interval &# 34 ; ifft &# 34 ; is also referred to as the ifft interval . the guard interval setting circuit 4 operates in response to a clock signal fed from the clock signal generating circuit 10 ( see fig3 ). in the guard interval setting circuit 4 , final portions of the output signals of the ifft and pilot signal generating circuit 3 in every window interval ( every symbol interval ) are copied , and the copy - resultant signal portions are moved to temporal positions immediately preceding window interval signals ( effective symbol interval signals ). to implement the above - indicated process , the guard interval setting circuit 4 functions as follows . specifically , the output signals of the ifft and pilot signal generating circuit 3 are stored , sequentially sample by sample , into the ram 4a for every window interval ( every symbol interval ). then , finally - stored portions of the output signals of the ifft and pilot signal generating circuit 3 which correspond to one cycle or one wavelength are read out from the ram 4a so that signals occupying a guard interval &# 34 ; g &# 34 ; are generated . subsequently , the output signals of the ifft and pilot signal generating circuit 3 are read out from the ram 4a in a sequence starting from the firstly - stored portions thereof so that signals occupying an effective symbol interval &# 34 ; ifft &# 34 ; following the previously - indicated guard interval &# 34 ; g &# 34 ; are generated . as shown in fig1 , pilot signals ( sync signals ) are generated alternately at opposite phases for ifft intervals . to this end , a voltage signal applied to a given input terminal of the ifft and prior signal generating circuit 3 is alternately changed for ifft intervals . the given input terminal corresponds to the pilot signal frequency ( the sync signal frequency ). furthermore , the pilot signal ( the sync signal ) corresponding to one wavelength multiplied by a given integer is present in every ifft interval while the pilot signal ( the sync signal ) corresponding to one wavelength is present in every guard interval &# 34 ; g &# 34 ;. as shown in fig1 , the phase of the pilot signal ( the sync signal ) is inverted each time an ifft interval is replaced by a guard interval &# 34 ; g &# 34 ;. it should be noted that the pilot signal ( the sync signal ) corresponding to a half wavelength multiplied by an even integer ( different from two ) may be present in every guard interval &# 34 ; g &# 34 ;. a signal receiving apparatus according to a ninth embodiment of this invention is designed to accept an rf ofdm signal transmitted by a signal transmitting apparatus of the seventh embodiment or the eighth embodiment . the ninth embodiment is similar to the second embodiment except that the sample sync signal generating circuit 32 ( see fig5 ) and the symbol sync signal generating circuit 33 ( see fig5 ) are modified to include an arrangement of fig1 . the arrangement of fig1 includes phase comparators 111 and 112 , an amplifier 113 , an lpf ( a low pass filter or a loop filter ) 114 , a vco circuit 115 , and an exclusive - or circuit 116 . first input terminals of the phase comparators 111 and 112 are connected to the quadrature demodulator 23 ( see fig5 ) via an input terminal 110 . a second input terminal of the phase comparator 111 is connected to a first output terminal of the vco circuit 115 . the output terminal of the phase comparator 111 leads to a first input terminal of the exclusive - or circuit 116 . a second output terminal of the vco circuit 115 leads to a second input terminal of the exclusive - or circuit 116 . signals which appear at the first and second output terminals of the vco circuit 115 have a quadrature relation with each other . the output terminal of the exclusive - or circuit 116 leads to a second input terminal of the phase comparator 112 . the output terminal of the phase comparator 112 is connected to a control terminal of the vco circuit 115 via the amplifier 113 and the lpf 114 . the phase comparator 112 , the amplifier 113 , the lpf 114 , and the vco circuit 115 compose a pll circuit in which the exclusive - or circuit 116 is interposed . the pll circuit is phase - locked with respect to a pilot signal in an output signal of the quadrature demodulator 23 ( see fig5 ). the phase comparator 111 executes synchronous detection between the output signal of the quadrature demodulator 23 ( see fig5 ) and a first output signal of the vco circuit 115 , thereby reproducing and outputting a symbol sync signal ( a symbol interval signal or a symbol clock signal ) which has a waveform such as shown in the portion b of fig1 . the symbol sync signal is transmitted from the arrangement of fig1 via an output terminal 118 . the exclusive - or circuit 116 executes exclusive - or operation between the output signal of the phase comparator 111 and a second output signal of the vco circuit 115 which has a quadrature relation with the first output signal of the vco circuit 115 . the output signal of the exclusive - or circuit 116 is applied to the phase comparator 112 . the exclusive - or circuit 116 serves to invert the phase of the second output signal of the vco circuit 115 for every other symbol interval . as a result , the pll circuit is continuously phase - locked with respect to the pilot signal in the output signal of the quadrature demodulator 23 ( see fig5 ). the first output signal of the vco circuit 115 constitutes a reproduced pilot signal which has a waveform such as shown in the portion a of fig1 . the reproduced pilot signal is transmitted from the arrangement of fig1 via an output terminal 117 . a frequency converter or a frequency multiplier ( not shown ) following the arrangement of fig1 changes the frequency of the reproduced pilot signal by a given factor , thereby converting the reproduced pilot signal into a sample clock signal . a signal receiving apparatus according to a tenth embodiment of this invention is designed to accept an rf ofdm signal transmitted by a signal transmitting apparatus of the seventh embodiment or the eighth embodiment . the tenth embodiment is similar to the second embodiment except that the sample sync signal generating circuit 32 ( see fig5 ) and the symbol sync signal generating circuit 33 ( see fig5 ) are modified to include an arrangement of fig1 . the arrangement of fig1 includes phase comparators 131 and 132 , an amplifier 133 , an lpf ( a low pass filter or a loop filter ) 134 , a vco circuit 135 , and an exclusive - or circuit 136 . first input terminals of the phase comparators 131 and 132 are connected to the quadrature demodulator 23 ( see fig5 ) via an input terminal 130 . a second input terminal of the phase comparator 131 is connected to a first output terminal of the vco circuit 135 . the output terminal of the phase comparator 131 leads to a first input terminal of the exclusive - or circuit 136 . a second output terminal of the vco circuit 135 leads to a second input of the phase comparator 132 . signals which appear at the first and second output terminals of the vco circuit 135 have a quadrature relation with each other . the output terminal of the phase comparator 132 leads to a second input terminal of the exclusive - or circuit 136 . the output terminal of the exclusive - or circuit 136 is connected to a control terminal of the vco circuit 135 via the amplifier 133 and the lpf 134 . the phase comparator 132 , the amplifier 133 , the lpf 134 , and the vco circuit 135 compose a pll circuit in which the exclusive - or circuit 136 is interposed . the pll circuit is phase - locked with respect to a pilot signal in an output signal of the quadrature demodulator 23 ( see fig5 ). the phase comparator 131 executes synchronous detection between the output signal of the quadrature demodulator 23 ( see fig5 ) and a first output signal of the vco circuit 135 , thereby reproducing and outputting a symbol sync signal ( a symbol interval signal or a symbol clock signal ) which has a waveform such as shown in the portion b of fig1 . the symbol sync signal is transmitted from the arrangement of fig1 via an output terminal 138 . the phase comparator 132 receives a second output signal of the vco circuit 135 which has a quadrature relation with the first output signal thereof . the device 132 executes phase comparison between the output signal of the quadrature demodulator 23 ( see fig5 ) and the second output signal of the vco circuit 135 . the exclusive - or circuit 136 executes exclusive - or operation between the output signal of the phase comparator 131 and the output signal of the phase comparator 132 . the output signal of the exclusive - or circuit 116 is transmitted to the vco circuit 135 via the amplifier 133 and the lpf 134 . the exclusive - or circuit 136 serves to invert the phase of the output signal of the phase comparator 132 for every other symbol interval . as a result , the pll circuit is continuously phase - locked with respect to the pilot signal in the output signal of the quadrature demodulator 23 ( see fig5 ). the first output signal of the vco circuit 135 constitutes a reproduced pilot signal which has a waveform such as shown in the portion a of fig1 . the reproduced pilot signal is transmitted from the arrangement of fig1 via an output terminal 137 . a frequency converter or a frequency multiplier ( not shown ) following the arrangement of fig1 changes the frequency of the reproduced pilot signal by a given factor , thereby converting the reproduced pilot signal into a sample clock signal .