text: referring to fig1 frequency synthesizers commonly employ standard phase - locked loop circuitry wherein a voltage controlled oscillator ( vco 30 ) output signal fo is divided by a loop divisor n 40 . to lock to a new frequency , the scaled synthesized frequency fn is compared to a reference frequency signal fr in a phase detector means 50 . the reference frequency fr can be provided by any suitable frequency generator , such as an oscillator or phase reference 53 . the phase detector means 50 generates up and down signals indicative of the phase relationship between the reference frequency fr and the scaled , synthesized frequency fn . the output of the loop divisor fn is compared to a reference frequency signal fr ( after division by an optional reference divider 42 ) in a phase detector 52 . in the preferred embodiment , the phase detector means 50 may be a motorola part mc14046 tri - state phase detector 52 with a charge pump 54 . the charge pump 54 generates a charging current io whose duration is proportional to the phase difference detected . the charge pump 54 generates a charging or discharging current io and supplies it to the capacitive elements at a loop filter 60 in response to up and down pulses received from the phase detector 52 . the charging current io is utilized to charge capacitive elements in the loop filter 60 , thereby developing a steering line control voltage vs for the voltage controlled oscillator ( vco 30 ). the result is that the phase - locked loop operates to acquire , and then maintain , the voltage controlled oscillator ( vco 30 ) frequency as an integral multiple ( n ) of a reference frequency fr . thus , a synthesized frequency fo is generated by the voltage controlled oscillator ( vco 30 ) and is proportional to the control voltage on its vco input vs . the charge pump 54 is switched by the phase detector 52 on output lines u and d . a current source 12 is provided for charging the capacitive elements of the loop filter 60 and thereby generates a steering line voltage control signal vs for the voltage controlled oscillator ( vco 30 ) when the synthesized frequency fo must be brought up from its current frequency . similarly , a current sink 36 is provided to discharge the capacitive elements of the loop filter 60 to reduce the steering line voltage control signal vs , when the synthesized frequency fo must be brought down from its current value . the charge pump 54 can be symbolically represented as a current source 12 in series with a first current sink 34 connected at their junction to a second current sink 36 via a diode 32 . in contrast to the turn - on operation of the current source 12 , both current sinks 34 and 36 turn on when a high signal is present and off for a low . the first current sink 34 is always on unless current sourcing is desired to increase the frequency of the vco 30 . on the other hand , the second current sink 36 is always off unless current sinking is desired to decrease the vco frequency . to provide the necessary control signal , an inverter 37 is coupled to the input of the second current sink 36 . the current source 12 is activated only when the charge pump 54 is needed to generate the output signal ( i o ). as illustrated by the preferred embodiment , a controller 14 turns the current source 12 on and off in response to the dividers 42 and 40 via lines 16 and 18 , respectively . when programming the dividers 42 and 40 by a number less than the current value of n , the divider lines 16 and 18 provide a signal via the controller 14 to anticipatively activate the current source 12 prior to the reference frequency fr and the synthesized frequency fn being received by the phase detector 52 . the controller 14 can maintain the active status of the current source 12 for a predetermined time so that the current source 12 will be on long enough to generate the required output signal ( i o ). since the current source 12 is a relatively slower pnp device , its inherent switching speed may be used in determining the time needed to keep the charge pump 54 actuated . alternately , once the current source 12 is turned on , the controller 14 can maintain this on status until the end of the signals from the longer pulse on line u or d has been detected from lines u and d . referring to fig2 an alternate embodiment for the activation of the current source 12 is illustrated . as one variation , an and gate 22 is provided to turn on the current source 12 before the charge pump output signal ( i o ) is generated . for this pnp current source 12 , the on condition corresponds to a low input signal ( 0 v ) and the off condition corresponds to a high input signal ( 5 v ). therefore , the current source 12 is turned on when a low or an inverted logic signal ( on corresponds to a low or 0 voltage ) from the phase detector 52 is present on either of lines u or d . meanwhile the phase detector up and down output pulses needed for output signal generation by the charge pump 54 are delayed by delay circuits 24 and 26 . the and gate 22 keeps the current source 12 on until the delayed low signals on lines u &# 39 ; and d &# 39 ; are no longer present . ( realistically , because of the inherent delay of the slower pnp current source 12 the charge pump 54 will still be on after the charge pump output signal i . sub . o is generated to ensure proper operation ). once the current source 12 is actuated by an appropriate method , the operation of the charge pump 54 in fig1 and 2 is the same . for clarification , the operation of the charge pump 54 will only be discussed with reference to fig2 . referring to fig3 a - e , a steady state signal is produced when the synthesized frequency fn is at its desired value and no phase difference exists . in this tri - state mode , both output up and down signals on lines u and d are off ( 5 v ) after the minimum pulse width interval as illustrated in fig3 a - b . preferably , the maximum delay is set for a time interval less than the minimum pulse width inherently generated by the phase detector 52 . the output of the and gate 22 of fig2 is illustrated in fig3 e . prior to generating the output signal i o , the current source 12 needs to be turned on . because the delayed and non - delayed signals are not at a high voltage at the same time as illustrated in fig3 a - d , the output of the and gate 22 will be at a low voltage for the duration of the delayed and non - delayed signals as illustrated in fig3 e . this low signal from the output ( 0 v ) of and gate 22 actuates the current source 12 . as illustrated by the delay as illustrated by fig3 c - e , the current source 12 will therefore be actuated before either of the current sinks 34 and 36 are switched by the delayed pulses on u &# 39 ; and d &# 39 ;. after a delay and inversion ( 37 ) of the off signal ( 5 v ) on line d &# 39 ; as illustrated in fig3 d , the second current sink 36 is deactivated . on the other hand , the current sink 34 is activated after the same delay by the off signal ( 5 v ) on the u &# 39 ; line of fig3 c . since the current sink 34 has the capacity to sink all of the current that the current source 12 can source , none of the sourced current will flow through the diode 32 to the loop filter 60 . in addition , the current from the steering control line vs is prevented from flowing back into the current sink 34 by the diode 32 . when the voltage controlled oscillator ( vco 30 ) is changed in frequency , the phase detector 52 furnishes appropriate phase indicative signals on line u and / or d causing the charge pump 54 to supply current to or sink current from the steering control line vs via the loop filter 60 . referring to fig4 a - e , when the frequency of the vco 30 needs to be increased , the phase detector 52 generates an on signal on line u . this on ( 0 v ) signal and a corresponding off ( 5 v ) signal on line d are illustrated in fig4 a and 4b , respectively . because both of the signals on lines u and d are not at a high voltage , the output of the and gate 22 will be at a low voltage for the duration of the delayed and undelayed signals as illustrated in fig4 e . as illustrated by the delay in fig4 c - e , the current source 12 will be activated before the delayed pulses are applied to the current sinks 34 and 36 . by the application of the low signal from the output ( 0 v ) of and gate 22 , the current source 12 is activated . the delayed signal present ( on = 0 v ) on line u &# 39 ; as illustrated in fig4 c deactivates the first current sink 34 . after inversion ( 37 ), the delayed signal pulse ( 5 v ) on line d &# 39 ; of fig4 d , activates the second current sink 36 . as the u &# 39 ; pulse is longer , the activated current source 12 applies current to the steering control line vs via the diode 32 to increase the frequency of the vco 30 . referring to fig5 a - e , when the frequency of the vco 30 needs to be decreased , the phase detector 52 generates an on signal on line d . this on ( 0 v ) signal and a corresponding off ( 5 v ) signal on line u are illustrated in fig5 a and 5b , respectively . because both the signals on lines u and d are not at a high voltage , the output of the and gate 22 wil be at a low voltage for the duration of the delayed and undelayed signals as illustrated in fig5 e . as illustrated by the delay in fig5 c - e , the current source 12 will be activated before the delayed pulses are applied to either of the current sinks 34 and 36 . by the application of the low signal from the output ( 0 v ) of and gate 22 , the current source 12 is activated . after the delay , the first current sink 34 is activated by the off ( 5 v ) signal of fig5 c . once activated , the current sink 34 sinks all of the current from the current source 12 . after the delay and inversion ( 37 ) of the on ( 0 v ) signal of fig5 d , the second current sink 36 is also activated . as the u &# 39 ; pulse has a shorter duration than the d &# 39 ; pulse , the first current sink 34 will turn back on , thereby permitting the second current sink 36 to sink current from the loop filter 60 to decrease the frequency of the vco 30 .