text: reference will now be made in detail to preferred embodiments of the present invention , examples of which are illustrated in the accompanying drawings . however , the present invention is not limited to the embodiments illustrated , and the embodiments are rather introduced to provide easy and complete understanding of the scope and spirit of the present invention . referring to fig1 in a functional mode setting circuit comprises a pin or pad 10 connected to a frequency detector 30 through a buffer 20 . an ac signal s 1 , input through the pin 10 , is converted into a digital signal s 2 by the buffer 20 having a complementary metal - oxide - semiconductor ( cmos ) logic . the digital signal s 2 is applied to the frequency detector 30 . as shown in fig3 the frequency detector 30 outputs a functional mode signal fm 0 if the digital signal s 2 oscillates between a high level and a low level for a predetermined duration . the frequency detector 30 is configured as shown in fig2 . the cmos digital signal s 2 provided from the buffer 20 is applied to the gates of a pmos transistor p 1 and an nmos transistor n 1 through inverters i 1 and i 2 connected in series . the pmos transistor p 1 and the nmos transistor n 1 are connected to each other in series between a power supply voltage vdd and an nmos transistor n 2 . the nmos transistor n 2 is connected to the nmos transistor n 1 and a ground voltage gnd . the gate of the nmos transistor n 2 is connected to a reference signal ref . when the reference signal ref is activated , the pmos transistor p 1 and the nmos transistor n 1 operate . the reference signal ref is at such a voltage level as to turn the nmos transistor n 2 on . node 31 is connected to the drain of the pmos transistor p 1 and the source of the nmos transistor n 1 , and is connected to the gates of a pmos transistor p 2 and an nmos transistor n 3 through an inverter i 3 . the nmos transistor n 3 is connected to the ground voltage gnd through an nmos transistor n 4 . the gate of the nmos transistor n 4 and the gate of the nmos transistor n 2 are connected to the reference signal ref . similarly , the pmos transistor p 2 and the nmos transistor n 3 act as an inverter when the nmos transistor n 4 is turned on in response to the reference signal ref . node 32 is connected to the drain of the pmos transistor p 2 and the source of the nmos transistor n 3 , and is connected to the input of a nor gate nr 1 through an inverter 14 . the digital signal s 2 is applied to the gates of a pmos transistor p 3 and an nmos transistor n 5 through an inverter 15 . the pmos transistor p 3 and the nmos transistor n 5 are connected to each other in series between the power supply voltage vdd and an nmos transistor n 6 . the nmos transistor n 6 is connected to the nmos transistor n 5 and the ground voltage gnd . the gate of the nmos transistor n 6 is connected to the reference voltage ref . when the reference signal ref is activated , the pmos transistor p 3 and the nmos transistor n 5 act as an inverter . node 33 is connected to the drain of the pmos transistor p 3 and the source of the nmos transistor n 5 , and is connected to the gates of a pmos transistor p 4 and an nmos transistor n 8 through an inverter i 9 . the nmos transistor n 8 is connected to the ground voltage gnd through an nmos transistor n 9 . the gate of the nmos transistor n 9 and the gate of the nmos transistor n 6 are connected to the reference signal ref . similarly , the pmos transistor p 4 and the nmos transistor n 8 act as an inverter in response to the reference signal ref when the nmos transistor n 9 is turned on . node 34 connected to the drain of the pmos transistor p 4 and the source of the nmos transistor n 8 , and is connected to the input of the nor gate nr 1 through an inverter i 10 . nmos transistors n 1 to n 9 are smaller in size than other mos transistors ( for example , pmos transistors p 1 to p 4 ). accordingly , the nmos transistors n 1 to n 9 have a low current driving power . the operation of the nmos transistors will be described in detail with reference to fig3 . referring to fig2 two nmos transistors ( for example , n 1 and n 2 ) are connected to each other in series in each inverter stage , but it should be noted that each inverter stage can be configured with one nmos transistor , for example , n 1 , connected to a pmos transistor , for example , p 1 . the nor gate nr 1 receives the outputs of the inverters i 4 and i 10 and outputs a functional mode signal fm 0 through inverters i 11 and i 12 connected in series . referring to fig3 when the signal s 2 is fixed at a high level or a low level ( tx ), the functional mode fm 0 is generated at a low level . when the signal s 2 is fixed at high level , nodes 32 and 33 go to a low level and a high level respectively . as the outputs a and b of the inverters i 4 and i 10 go to a high level and a low level respectively , the output of the nor gate nr 1 goes to a low level and the functional mode signal fm 0 goes to a low level . when the signal s 2 is fixed at a low level , the functional mode signal fm 0 is fixed at a low level as the outputs of the inverters i 4 and i 10 go to a low level and a high level respectively . however , the digital signal s 2 is responsive to an oscillation of the ac signal s 1 applied to the pin 10 with at least a predetermined frequency ( tf ), causing the functional mode signal fm 0 to be activated to a high level . as described above , if the signal s 2 oscillates between a high level and a low level with at least a predetermined frequency ( tf ), the pulse width of the high level of the output a ′ of the inverter 13 is short even though s 2 is at a high level since the current driving power of the nmos transistors n 1 and n 2 is small . the nmos transistors n 1 and n 2 with the low current driving power react slowly to a signal having a high level . similarly , since each of the nmos transistors n 3 and n 4 in a next stage has a low current driving power , the low level response to shortened high level pulse components does not appear at the node 32 . as a result , at the input a of the nor gate nr 1 , only a low level signal appears for the duration tf in which s 2 oscillates with at least a predetermined frequency . in addition , on the path from inverter i 5 to the input b of the nor gate nr 1 , the pulse width of the high level portions of the signal s 2 becomes shorter and only a low level signal appears at the input b according to the same process . as a result , for example , the functional mode signal fm 0 is maintained to be high level while the signal s 2 oscillates with at least a predetermined frequency ( tf ). the functional mode signal fm 0 detected to be at a high level during the duration tf drives predetermined inner circuits of an integrated circuit device to perform a test operation and the like . if the signal s 2 , or s 1 , oscillates with at least a predetermined frequency , activation of the functional mode signal fm 0 , e . g ., fm 0 has a high level , depends on the size of the nmos transistors n 1 to n 9 for pull - down . in addition , as shown in fig2 it should be noted that the high level pulse width can be shortened . on the other hand , when the signal s 2 oscillates with at most a predetermined frequency , the functional mode signal fm 0 also oscillates in response to the signal s 2 . however , the frequency of the signal s 2 may not be used . the circuit configuration and input / output characteristics of the frequency detector 30 shown in fig2 and 3 are used in an embodiment to be described . according to an embodiment of the present invention , the functional mode setting circuit shown in fig4 uses the configuration shown in fig1 to generate a plurality of functional mode signals . referring to fig4 cmos digital signal s 2 output from a buffer 20 is applied to a frequency detector 30 and transferred to a register chain comprising registers reg 1 to reg 4 connected in series . the registers reg 1 to reg 4 send respective outputs r 1 to r 4 to a decoder 40 in response to a clock signal clk that has a predetermined frequency and a predetermined synchronous period . whenever the clock signal clk passes one period , the signal s 2 passes each register stage . each register is used in , for example , a general delay loop and a general phase loop . each register includes a latch comprising a pair of inverters and a transfer gates turned on or off in response to the clock signal clk . as mentioned above with respect to fig3 a frequency detector 30 generates a functional mode signal fm 0 having a high level when a signal s 2 oscillates with at least a predetermined frequency , e . g ., it represents that the signal input state to set a functional mode is valid . in fig4 the signal fm 0 is used in controlling the decoder 40 . the decoder 40 receives transfer signals r 1 to r 4 from registers reg 1 to reg 4 and generates functional mode signals fm 1 to fm 3 while the signal fm 0 is at a high level . in fig4 there are four registers and three functional mode signals but the number of function mode signals can depend on the desired functions . referring to fig5 a decoder 40 comprises nand gates nd 1 to nd 17 for responding to a combination of the register transfer signals r 1 to r 4 . methods for generating the function mode signal according to the combinations of r 1 to r 4 can vary . according to an embodiment of the present invention , the functional mode signal fm 1 is activated when one of the transfer signals r 1 to r 4 has a high level . the functional mode signal fm 2 is activated when two of the transfer signals r 1 to r 4 have a high level . the functional mode signal fm 3 is activated when three of the transfer signals r 1 to r 4 have a high level . the signals r 1 b to r 4 b are inverse logic signals of the transfer signals r 1 to r 4 . the nand gate nd 1 receives r 1 , r 2 b , r 3 b , and r 4 b . the nand gate nd 2 receives r 1 b , r 2 , r 3 b , and r 4 b . the nand gate nd 3 receives r 1 b , r 2 b , r 3 , and r 4 b . the nand gate nd 4 receives r 1 b , r 2 b , r 3 b , and r 4 . the outputs of the nand gates nd 1 to nd 4 are input to the nand gate nd 15 . the nand gate nd 15 generates the functional mode signal fm 1 . since the other inverse logic signals remain at a high level while one of the transfer signals r 1 to r 4 is at a high level , one of the outputs of the nand gates nd 1 to nd 4 goes to a low level , and the nand gate nd 15 generates the activated functional mode signal fm 1 having a high level . the nand gate nd 6 receives r 1 , r 2 b , r 3 , and r 4 b . the nand gate nd 7 receives r 1 , r 2 b , r 3 b , and r 4 . the nand gate nd 8 receives r 1 b , r 2 , r 3 , and r 4 b . the nand gate nd 9 receives r 1 b , r 2 , r 3 b , and r 4 . the nand gate nd 10 receives r 1 b , r 2 b , r 3 , and r 4 . the outputs of the nand gates nd 5 to nd 10 are input to the nand gate ndi 6 . the nand gate nd 16 generates the functional mode signal fm 2 . since the other inverse logic signals remain at a high level while two of the transfer signals r 1 to r 4 are at a high level , one of the outputs of the nand gates nd 5 to nd 10 goes to a low level , and the nand gate nd 16 generates the activated functional mode signal fm 2 of a high level . the nand gate nd 11 receives r 1 , r 2 , r 3 and r 4 b . the nand gate nd 12 receives r 1 , r 2 , r 3 b , and r 4 . the nand gate nd 13 receives r 1 , r 2 b , r 3 , and r 4 . the nand gate nd 14 receives r 1 b , r 2 , r 3 , and r 4 . the outputs of the nand gates nd 11 to nd 14 are inputted to the nand gate nd 17 . the nand gate nd 17 generates the functional mode signal fm 3 . since the other inverse logic signals remain at a high level while three of the transfer signals r 1 to r 4 are at a high level , one of the outputs of the nand gates nd 11 to ndl 4 goes to a low level , and the nand gate nd 17 generates the activated functional mode signal fm 3 of a high level . referring to the waveform diagram shown in fig6 the functional mode signal fm 1 generated by the decoder 40 is activated every four cycles of clock signal clk when one of the transfer signals r 1 to r 4 is at a high level . the functional mode signal fm 2 is activated every four cycles of clock signal clk when two of the transfer signals r 1 to r 4 are at a high level . the functional mode signal fm 3 is activated every four cycles of clock signal clk when three of the transfer signals r 1 to r 4 are at a high level . according to an embodiment of the present invention , the functional mode setting circuit shown in fig7 uses a method in which each of reference voltages vr 1 to vrn ( e . g ., refer to fig8 ) set between the minimum high level voltage vih , less than vdd , and the maximum low level voltage vil , greater than gnd , are compared with the signal s 1 input from a pin 10 and coding signals are generated . here , the input signal s 1 is a dc signal that has a constant voltage level . referring to fig7 the input signal s 1 is simultaneously input to non - inverting input terminals (+) of differential amplifiers df 1 to dfn and compared with reference voltages vr 1 to vrn . the differential amplifiers df 1 to dfn amplify the voltage difference between the corresponding reference voltage and input signal s 1 and output the amplified signals d 1 to dn . the differential signals d 1 to dn are input to the decoder 50 . the decoder 50 has a combination logic as shown in fig6 and generates one or more functional mode signals fmi from the input differential signals d 1 to dn . it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention . thus , it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents . as described above , mode setting dc pin installed in the conventional integrated circuit is used to set the functions for tests in a packaging stage . accordingly , designers can set their desired functions without a separate available pin for setting functions .