text: the present invention is best understood by reference to the detailed figures and description set forth herein . embodiments of the invention are discussed below with reference to the figures . however , those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments . for example , it should be appreciated that those skilled in the art will , in light of the teachings of the present invention , recognized a multiplicity of alternate and suitable approaches , depending upon the needs of the particular application , to implement the functionality of any given detail described herein , beyond the particular implementation choices in the following embodiments described and shown . that is , there are numerous modifications and variations of the invention that are too numerous to be listed but that all fit within the scope of the invention . also , singular words should be read as plural and vice versa and masculine as feminine and vice versa , where appropriate , and alternatives embodiments do not necessarily imply that the two are mutually exclusive . the present invention will now be described in detail with reference to embodiments thereof as illustrated in the accompanying drawings . fig2 illustrates an exemplary circuit implementing a pwm controller ic chip 204 , in accordance with a first embodiment of the present invention . the circuit shown is a primary side controlled constant output current flyback converter . the converter shown comprises a transformer 201 ( which has three separate coil windings : primary with n p turns , secondary with n s turns , and auxiliary with n a turns ), a secondary side resistor 301 ( which represents the copper loss of transformer 201 ), a secondary rectifier 302 , an output capacitor 303 , and a peak current mode pwm control ic 204 . resistor 101 and capacitor 102 provide the initial start - up energy for ic 204 . once the flyback converter is stable , ic 204 is powered by the auxiliary winding of transformer 201 via rectifier 103 . resistor 109 programs the output current . resistor dividers 105 and 106 then provide an input signal for computing the transformer reset time ( t r ) via the t r detection circuit inside ic 204 . fig3 illustrates an exemplary block diagram of ic chip 204 shown in fig2 in accordance with an embodiment of the present invention . as illustrated , v cc supply 401 provides an internal power supply and reference voltage . current mirror 402 duplicates current i set to resistor 403 . t r detection 405 computes t r based on the v a voltage waveform coming from fb input pin . those skilled in the art , in light of the teachings of the present invention , will readily recognize that the feedback for the fb input pin may come from any other suitable source beyond the auxiliary winding of the transformer such as , by way of example , and not limitation , from the primary winding . in alternate embodiments of the present invention ( not shown ), the transformer does not have any auxiliary windings , and only has a primary and a secondary winding . those skilled in the art , will recognize a multiplicity of alternate and suitable transformer types and interface circuit configurations to be operable with connection to the fb input pin . in the embodiment shown , calculation unit 406 performs multiplication between i p — avg and t r , however , in other embodiments of the present invention , depending on the needs of the particular application , any suitable math function may be implemented instead of multiplication , as will be readily determined by those skilled in the art , in light of the present teachings . error amplifier 404 then compares the calculated output current with a programmed value across resistor 403 . resistor 407 and capacitor 408 are coupled to form an averaging circuit for the primary current . resistor 409 and capacitor 410 form a compensation network for amplifier 404 . comparator 412 serves as a peak current mode pwm comparator with an optional slope compensation input . in other embodiments of the present invention ( not shown ), the comparator may be configured by those skilled in the art to compare any suitable ramp signals depending upon the needs of the particular application . system oscillator 411 provides an optional frequency jittering function that widens the frequency spectrum and achieves a lower conducting emi emission . an example of a preferred frequency jittering circuit is described in connection with fig9 . alternate embodiments of the present invention may not include the frequency jittering function in system oscillator 411 and / or slope compensation . in many applications , slope compensation and the system oscillator jitter function can improve converter operation in certain input / output operating conditions ; however , these functions are completely optional , whereby alternate embodiments of the present invention may not include either one or both . pwm control unit 417 then generates the correct pwm waveform by utilizing a cycle - by - cycle current limiting function . mosfet 413 is a relatively high speed mosfet gate driver . power internal mosfet 415 serves as the main switch , while a small die size allocated internal mosfet 414 and resistor 416 form a current sense circuit . as will be readily apparent to the system designer , some applications may not require resistor 416 to generate the current sensing voltage feedback or it may be located in other circuit configurations , or embedded into other system components . as will be readily recognized by those skilled in the art , depending upon the needs of the particular application and current technology , the power mosfet may be formed in any suitable manner . by way of example , and not limitation , the power mosfet may be comprised of a multiplicity of smaller mosfet device to form a single power mosfet . in contrast with conventional approaches that only work in dcm , the present embodiment implements a method for using “ sampled auxiliary flyback voltage ” to control the primary current . sampling the auxiliary flyback voltage at a known time point provides a more accurate representation of the actual output voltage in most applications . the present embodiment is largely independent of auxiliary voltage and / or current by , for example , basing output current control only on primary current sensing and the ratio of t_r / t_on , which works in both dcm and ccm . hence , embodiments of the present invention preferably do not use auxiliary voltage to control primary current by essentially scaling the peak current ( ipeak ) as proportional to a square root of the output voltage , as is done in conventional approaches . fig4 illustrates exemplary ideal waveforms of the auxiliary winding voltage , primary switch current , and secondary rectifier current operating in continuous current mode ( ccm ) according to an embodiment of the present invention . main switch 415 turns on at t 1 , turns off at t 2 and turns on again at t 3 . the switching period is t , the turn - on time is t on and the turn - off time is t r . using known theory , the output current i out can be expressed as : i out =( ½ )·( i s1 + i s2 )·( t r / t ). ( 1 ) because i s1 =( n p / n s )· i p1 ( 2 ) and i s2 =( n p / n s )· i p2 , ( 3 ) i out may be expressed by combining ( 1 ), ( 2 ) and ( 3 ) as shown in ( 4 ) below . i out =( ½ )·( n p / n s )·( i p1 + i p2 )·( t r / t ). ( 4 ) furthermore , because i p — avg =( ½ )·( i p1 + i p2 )·( t on / t ) ( 5 ) equations ( 4 ) and ( 5 ) may be combined to express i out as shown in ( 6 ) below i out =( n p / n s )·( t r / t on )· i p — avg ( 6 ) fig5 illustrates ideal waveforms of the auxiliary winding voltage , primary switch current , and secondary rectifier current operating in discontinuous current mode ( dcm ) according to an embodiment of the present invention . main switch 415 turns on at t 1 , turns off at t 2 , and turns on again at t 4 . the switching period is t , the turn - on time is t on and the turn - off time is equal to ( t 4 - t 2 ). as shown in fig5 , the current at the secondary winding of transformer 201 discharges to zero at t 3 . because tr is equal to ( t 3 - t 2 ), the output current can be expressed as : because i s2 =( n p / n s )· i p2 ,( 8 ) i out may be expressed by combining ( 7 ) and ( 8 ) as shown in ( 9 ) below : i out =( ½ )·( n p / n s )· i p2 ·( t r / t ). ( 9 ) furthermore , because i p — avg =( ½ )· i p2 ·( t on / t ), ( 10 ) i out may be expressed by combining ( 9 ) and ( 10 ) as shown in ( 11 ) below i out =( n p / n s )·( t r / t on )· i p — avg ( 11 ) the output power of the converter generally depends only on the stored energy of the inductor in dcm operating mode , in accordance with the following formula ( 12 ), which neglects efficiency losses : in the ccm operating mode , at the output of the converter output , the voltage is dropping from v norm to zero . to keep io constant , f is preferably reduced proportionally to vo while maintaining a fixed ip . fig6 illustrates an exemplary schematic of a primary side controlled constant output current flyback converter in an emitter switching configuration using the first ic chip embodiment , in accordance with an embodiment of the present invention . for many low power applications , using current on - chip mosfet technology , no external power mosfet or current sense circuit is needed . for higher output power and / or higher switching frequency than the internal on - chip mosfet can properly handle , however , external power handling components may be required . for example , the approach of the present embodiment is to introduce npn bipolar transistor 105 that cooperates with ic chip 204 , of the present invention , in an emitter switching configuration as shown in the figure . in such a configuration , internal mosfet 415 drives the emitter of external npn transistor 105 which serves as the main switch . to further increase the power handling capability and switching frequency , an external mosfet is typically used as the main switch . fig7 illustrates an exemplary block diagram of a pwm controller ic chip 704 , in accordance with a second embodiment of the present invention . ic chip 704 does not include internal power mosfet 415 , current sensing mosfet 414 , and current sensing resistor 416 from the first ic chip embodiment of fig3 . in this second embodiment , the current driving capability of gate drive 413 results in improved control for larger mosfets . fig8 illustrates an exemplary schematic for implementing ic chip 704 with an external mosfet and a current sense resistor . the functional blocks shown in the prior embodiments may be implemented in accordance with known techniques as will be readily apparent to those skilled in the art . however , some embodiments of the present invention include implementation approaches that are not conventional . for example , without limitation , the foregoing jitter functional block may be implemented as follows . fig9 illustrates a schematic diagram of an exemplary system oscillator 411 having a digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block , in accordance with an embodiment of the present invention . the frequency jittering in the present embodiment is implemented by a digital control scheme , which departs from known approaches . an oscillator 817 is preferably a current controlled oscillator . there is preferably an uncontrolled , base - line , current source 801 , which , in one aspect , is present to set a minimum oscillator frequency , fmin , that the switched current sources will jitter from . in the embodiment shown , the current to oscillator 817 is controlled by a multiplicity of switched current sources 802 - 804 that carry out the jittering of the oscillator &# 39 ; s minimum frequency . the frequency of the system oscillator output signal is generally proportional to the total current entering into oscillator 817 . in alternate embodiments , any number of current sources may be implemented depending upon the needs of the particular application . the jitter behavior is generated by feeding back the output signal of oscillator 817 to a multiplicity of series connected flip - flops ( e . g ., 818 to 823 ). current sources 801 , 802 , 803 and 804 are presently preferred to be currents of magnitudes 100 μa , 2 . 5 μa , 5 μa and 10 μa , respectively . each switched current source is presently configured with four current control switches ( e . g ., control switches 805 , 806 , 811 and 812 for switched current source 802 ) that are arranged in two parallel legs with each leg having two switches in series . in this way , for current to flow into oscillator 817 at least one leg must have both of its switches turned on . in similar fashion , four switches ( 807 , 808 , 813 and 814 ) are connected to switched current source 803 and another four switches ( 809 , 810 , 815 and 816 ) are connected to switched current source 804 . all of these switches are closed or open by a control input from an output from the series connected flip - flop chain . in the example shown , the switch 805 is open when q 5 is at logic level “ 1 ” and is closed when q 5 is at logic level “ 0 ”. similarly , the 806 switch is open when q 5 is at logic level “ 0 ” and is closed when q 5 is at logic level “ 1 ”, and so on . when all the switched current sources are enabled , a maximum frequency , fmax , of the system oscillator output signal is achieved . as will be readily apparent to those skilled in the art , in light of the present teachings , the choice of which flip - flop outputs connect to which current control switch will determine a certain jittering pattern . an aspect of this digital frequency jittering scheme is that the period & amp ; the step of frequency variation may be relatively precisely controlled , and is largely insensitive to temperature variations . it should be appreciated that in contrast to conventional analog techniques for jittering the oscillator frequency , the digital jittering approach of the present embodiment always provide digitally calculated frequency step irrespective of the known shortcomings that analog based techniques suffer from ; such as , without limitation , temperature , input , output age dependences , etc . those skilled in the art , in light of the present teachings , will readily recognize a multiplicity of alternate and suitable implementations that implement the spirit of the present embodiment . by way of example , and not limitation , current based operation may be replaced with a voltage based approach , and the number and topology of the switches and / or current sources and / or flip - flop chain may be altered as needed for the particular application , and other suitable means to selectively control the pattern of current flowing into the current controlled oscillator . fig1 illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of fig9 , in accordance with an embodiment of the present invention . in the example shown , frequency variation from its maximum ( fmax ) to minimum ( fmin ) corresponding to the logic states “ 0 ” or “ 1 ” of q 2 , q 3 , q 4 and q 5 . having fully described at least one embodiment of the present invention , other equivalent or alternative methods of implementing a primary side constant output current controller according to the present invention will be apparent to those skilled in the art . the invention has been described above by way of illustration , and the specific embodiments disclosed are not intended to limit the invention to the particular forms disclosed . the invention is thus to cover all modifications , equivalents , and alternatives falling within the spirit and scope of the following claims .