text: in the industrial process control system shown in fig1 , a distributed architecture is designed to be used in different safety integrity level ( sil ) environments , so that if a high sil is required it can be provided , but if a low sil is all that is needed the system can be reduced in complexity in order to reduce unnecessary extra costs . an exemplary industrial process control system 10 , comprises a workstation 12 one or more controllers 14 and a gateway 16 . the workstation 12 communicates with the controllers 14 and the gateway 16 via ethernet connections 18 to one or more control networks 13 . multiple ethernet connections 18 provide redundancy to improve fault tolerance . the workstation 12 may be connected via a conventional ethernet connection 11 to another external network 15 . a controller 14 will now be described in more detail with reference to fig2 and 3 . fig2 illustrates a schematic diagram of the controller 14 comprising an input assembly 22 , a processor assembly 24 and an output assembly 26 . in this schematic illustration the input assembly 24 and output assembly 26 are on different backplanes but they may equally well share a single backplane . assemblies 22 , 24 , 26 are created from one or more communications backplane portions which have three slots to accommodate up to three modules together with termination assemblies which have one two or three slots , and which interface to field sensors and transducers . a termination assembly may straddle two contiguous backplane portions . a module comprises a plug in card with multiple connectors for plugging onto a communications backplane and a termination assembly . it will be appreciated that having three slots in a communications backplane portion is one design option and other design options with greater ( or fewer ) slots are possible without departing from the scope of the invention as defined in the appended claims . fig3 illustrates a possible physical configuration of the controller 14 . in this embodiment of the invention , the input assembly 22 , output assembly 26 and processor assembly 24 are physically separated from one another by grouping the modules of different types onto separate communications backplanes . in the example shown , the input assembly 22 comprises two communications backplane portions , 22 ′, 22 ″. the first backplane portion 22 ′ has a triplex input termination assembly and three input modules 22 a , 22 b , 22 c , the second backplane portion 22 ″ has a duplex input termination assembly 22 ″ and two input modules 22 c , 22 d . the processor assembly 24 comprises a single processor backplane portion 24 ′ having three processor modules 24 a , 24 b and 24 c . the output assembly 26 comprises two backplane portions 26 ′, 26 ″. the first backplane portion 26 ′ has a duplex output termination assembly with two output modules 26 a , 26 b and the second backplane portion 26 ″ has a simplex output termination assembly with a single output module 26 c . the flexibility of the input assembly 22 , will now be described , in more detail with reference to fig4 . an input assembly 22 comprises one or more backplane portions and termination assemblies 22 ′ 22 ″ 22 ′″ etc . for example , a triplex portion 22 ′ having three modules 22 a , 22 b , 22 c might be used to satisfy a high availability requirement , a duplex portion 22 ″ having two modules 22 d , 22 e might be provided for fault tolerant applications , and a simplex portion 22 ′″ with a single module 22 f might be provided for failsafe applications . the termination assemblies may be provided with different types of field conditioning circuits . for example assembly 22 ′ may be provided with a 24v dc field conditioning circuit 41 , assembly 22 ″ may be provided with a 120v dc field conditioning circuit 42 , and assembly 22 ′″ may be provided with a 4 - 20 ma field conditioning circuit 43 . similarly possible configurations are shown for an output assembly 26 . it will be appreciated that numerous configurations of backplane portions and termination assemblies with various different numbers of modules and various different types of field conditioning circuits are possible and the invention is not limited to those shown in these examples . where an assembly provides more than one module for redundancy purposes it is possible to replace a failed module with a replacement module whilst the industrial process control system is operational which is also referred to herein as online replacement ( ie replacement is possible without having to perform a system shutdown ). online replacement is not possible for a simplex assembly without interruption to the process . in this case various “ hold last state ” strategies may be acceptable or a sensor signal may also be routed to a different module somewhere else in the system . the processor assembly configures a replacement processor module using data from a parallel module before the replacement module becomes active . the field conditioning circuits 41 , 42 , 43 transform a signal received from a sensor to a desired voltage range , and distribute the signal to the input modules as required . each field conditioning circuit 41 , 42 , 43 is also connected to field power and field return ( or ground ) which may be independently isolated on a channel by channel basis from all other grounds , depending on the configuration of the input termination assembly . independent channel isolation is the preferred configuration because it is the most flexible . the field conditioning circuits 41 , 42 , 43 comprise simple non active parts and are not online replaceable . fig5 and fig6 illustrate the flexibility of the architecture described herein showing different configurations for a triplex system for generating a signal with a high availability requirement . referring to fig5 , a three module input assembly 51 receives a signal from a sensor 50 via a field conditioning circuit in termination assembly 54 . the field conditioning circuit 54 transforms the signal to a desired voltage range and distributes the signal to three replicated input modules 53 a , 53 b , 53 c . each input module processes the signal and the results are sent to a two out of three voter 52 to generate a result signal in dependence thereon . referring to fig6 , replicated sensors 60 a , 60 b , 60 c each send a signal to respective simplex assemblies 61 a , 61 b , 61 c via respective field conditioning circuits in termination assemblies 64 a , 64 b , 64 c . each input module 63 a , 63 b , 63 c processes the signal and sends an output to a two out of three voter 62 to generate a signal in dependence thereon . it will be appreciated that many variations and configurations are possible in addition to those illustrated here . fig7 illustrates schematically an output module in accordance with the present invention . an output module 70 comprises a power feed combiner 71 , a first field programmable gate array ( fpga ) and field effect transistor ( fet ) driver 72 , a second fpga and fet driver 73 . the drivers 72 , 73 control a plurality of channels each channel driving a load ( not shown ) each channel comprising a channel failsafe switch 75 connected to a respective reverse blocking circuit 76 each of which is driven by a respective charge pump ( only three channels are shown schematically for clarity ). it will be appreciated that the incorporation of the control logic into an fpga is not central to the invention ; it is just a convenient implementation . the logic could equally well be implemented in an application specific integrated circuit ( asic ), or a general purpose microcomputer without departing from the scope of the invention as defined in the appended claims . the current and voltages at various points in the channel are monitored by two arrays of current amplifiers and monitors and a / d converters 77 a , 77 b and two arrays of voltage monitors and a / d converters 78 a and 78 b . in a preferred embodiment of the invention there are eight output channels served by eight channel failsafe switches 75 and associated reverse blocking circuits 76 . the first fpga and fet driver 72 generates a plurality of signals 721 each of which drives a first fet 801 in each switch 75 . the second fpga and fet driver 73 generates a plurality of signals 731 each of which drives a second fet 802 in each switch 75 . each voltage monitor signal 781 , and each current monitor signal 771 is fed back into the first fpga and fet driver 72 , each voltage monitor signal 782 and each current monitor signal 772 is fed back to the second fpga and fet driver 73 where various functions are carried out in dependence thereon . in a preferred embodiment of the invention channel failsafe switches 75 can be automatically tested . one of the fpga and fet drivers 72 , 73 is instructed to initiate a sequence whereby a channel under test is partially driven to the opposite state to that which it is currently commanded to . the channel current and voltage are continuously monitored by current amplifiers and monitors 77 a , 77 b and voltage monitors 78 a , 78 b which in combination with hardware logic in the fpga and fet driver 72 , 73 determine whether or not a fet 801 , 802 in a channel failsafe switch 75 has reached a desired end state for the test . fig8 illustrates the fpga and fet driver 72 . the fpga and fet driver 72 contains an fpga 81 which controls a plurality of fet drivers 82 . for clarity only three drivers 82 are shown in this schematic illustration , in the preferred embodiment there are eight drivers to drive each top fet ( 801 , fig7 ) in each channel failsafe switch 75 using respective signals 721 . an enable signal 812 from the fpga 81 is used to control the plurality of fet drivers 82 . when the enable signal 812 is actively switching states at a high frequency the fet drivers 82 are enabled and when the enable signal 812 is not actively switching states the fet drivers 82 are disabled . fig9 illustrates the fet driver 82 in more detail although for clarity enabling circuitry receiving the enable signal 812 and generating shutdown signal 911 is omitted . the fet driver 81 is driven using two signals , a ramp signal 841 and a command signal 811 from the fpga 81 . the command signal 811 is applied to an operational amplifier 121 through a capacitor 122 . the ramp signal 841 is applied to the operational amplifier 121 through a resistor 123 . the command signal 841 and the ramp signal 811 are usually both set to ‘ 0 ’ when the channel is ‘ on ’ and are usually both set to ‘ 1 ’ when the channel is ‘ off ’. referring back to fig8 , the fpga contains a controller 85 which upon receipt of a ramp test command via command line 851 sends a corresponding command to a ramp generator 84 to cause the ramp generator 84 to activate the ramp signal 841 sent to the fet driver 82 in turn causing the fet driver 82 to generate a ramped driving signal 721 . the ramped driving signal 721 is sent to the fet 801 . the ramped driving signal may be either increasing or decreasing depending upon whether it is to partially turn on an fet 801 which is off to verify that it can be turned on , or to partially turn off an fet 801 to verify that it can be turned off as will be explained later with reference to fig1 and 11 . in the case of fpga and fet driver 72 comparators 83 receive a monitored current signal 771 from current amplifiers and monitors 77 a and a monitored voltage signal 781 from voltage amplifiers and monitors 78 a . in the case of fpga and fet driver 73 comparators 83 receive a monitored current signal 772 from current amplifiers and monitors 77 b and a monitored voltage signal 782 from voltage amplifiers and monitors 78 b . if either the monitored voltage or the monitored current reaches a threshold or predetermined maximum or minimum set in registers in the comparators 83 the test is terminated by causing the ramp generator 84 to cease activating the ramp signal 841 . referring now to fig1 , operation of this scheme is illustrated for a channel that is in the ‘ on ’ state before the test . initially command signals 811 and 841 are both in a steady state ‘ 0 ’ condition . upon receipt of a test command via the controller 85 , the fet drive gate voltage signal is ramped up by the application of a high frequency pulse width modulated ( pwm ) or equivalently pulse ratio modulated ( prm ) ramp signal on command signal 841 to the fet driver 82 . the duty cycle ( or logic ‘ 1 ’ density ) of the high frequency ramp signal 841 is increased until the comparators 83 detect that the predetermined maximum or minimum have been reached or the ramp signal has reached a steady logic ‘ 1 ’ ( this occurs after a predetermined time as the duty cycle of the high frequency ramp signal 841 is increased at a predetermined rate ). in the example shown in fig1 , the gate drive voltage signal 721 has a start value of − 10v , the resulting monitored voltage 781 is initially 23v and the resulting monitored current 771 is initially 1 a . when the high frequency ramp signal 841 is received by the operational amplifier 121 the gate drive signal 721 begins to rise and thus the monitored voltage 781 and the monitored current 771 begin to fall . in this example a predetermined voltage threshold 100 is set to 16v and a predetermined current threshold 101 is set to 750 ma . the illustration shows that the monitored current 771 reaches the predetermined current threshold 101 before the monitored voltage 781 reaches the predetermined voltage threshold 100 . at this point the test is terminated and the high frequency ramp signal 841 is ceased , causing the gate drive signal 721 to return to its original starting value . referring now to fig1 , operation of the scheme is illustrated for a channel in the ‘ off ’ state before the start of the test . initially the command signals 811 and 841 are both in a steady state ‘ 1 ’ condition . upon receipt of a test command via the controller 85 , the drive voltage signal 721 is ramped down by application of a high frequency pulse width modulated ( pwm ) or equivalently , pulse ratio modulated ( prm ) ramp signal 841 to the fet driver 82 . the logic ‘ 0 ’ density of the high frequency ramp signal 811 is increased until the comparators 83 detect that the current or voltage threshold has been crossed or a predetermined time limit has been exceeded ( ie when the ramp signal 841 reach a steady state logic ‘ 0 ’. in the example shown in fig1 , the gate drive voltage signal 721 has a start value of 0v , the resulting monitored voltage 781 is initially 0v and the resulting monitored current 771 is initially 0 a . when the high frequency ramp signal 841 is received by the operational amplifier 121 the gate drive signal 721 begins to fall and thus the monitored voltage 781 and the monitored current 771 begin to rise . in this example a predetermined voltage threshold 100 ′ is set to 3v and a predetermined current threshold 101 ′ is set to 50 ma . the illustration shows that the monitored voltage 781 reaches the predetermined voltage threshold 100 ′ before the monitored current 771 reaches the predetermined current threshold 101 ′. at this point the test is terminated and the high frequency ramp signal 841 is ceased , causing the gate drive signal 721 to return to its original staring value . it will be appreciated that for this test mode to operate correctly , the other fet in the channel failsafe switch 75 must be set to the ‘ on ’ state prior to commencing the test sequence , preferably with an over - voltage / over - current trap in place . this is performed by running the ramp test as described above , but with the expectation for the ramp to reach the terminal state without the current or voltage thresholds being reached , as that would signify the existence of a pre - existing short circuit fault in the other fet . when testing a channel which is ‘ off ’ it is desirable to avoid fully energizing the output channel , even briefly , during channel and field fault testing . using a partial - on test as described above allows detection of short circuit switch faults to be provided when the channel is ‘ off ’. it will be appreciated that the present invention has been described with reference to an fpga but the invention could equally well be implemented using discrete logic components , a microprocessor , or an asic . as shown in fig1 , the reverse blocking circuit 76 comprises a reverse blocking transistor 91 which is a high current n channel mosfet . the reverse blocking transistor 91 is driven using a charge pump signal 732 generated by a control circuit resident in the fpga and fet driver 73 . the current through the transistor 91 and the voltage across it is monitored and sent to the fpga and fet driver 73 via a / d converter channels and amplifiers 77 b , 78 b . when reverse current is detected flowing into the digital outputs , then the reverse blocking transistor 91 is turned off , to break the connection to the external power source . the use of a low voltage charge pump 74 to generate the positive turn - on bias voltage required by the reverse blocking transistor simplifies the power supply requirements for the output module . fig1 illustrates a simple low voltage implementation of a conventional charge pump ( sometimes referred to as a diode - capacitor voltage multiplier ). each transition of the charge pump signal 732 transfers some charge from a square wave driver into an output capacitor 93 as constrained by switching diodes 94 , 95 . the reverse blocking transistor 91 may also be turned off when channel diagnostic tests are to be run on the channel failsafe switch 75 . the reverse blocking transistor 91 may also be tested periodically on channel by turning it off and examining the change in channel voltage . two high resistance resistors 96 , 97 in series with the gate , together with a zener diode 98 from gate to source , allow the reverse blocking transistor 91 to be pulled down to 0v when the channel is in the off state . a backup diode 92 , consisting of a low forward drop schottky power diode is included in the circuit to allow operation if the reverse blocking transistor 91 fails or there is a failure in the charge pump path driving the gate . if only one or a small number of channels are in this faulted condition , a resulting temperature increase can be tolerated . this component also allows the reverse blocking transistor control to default the reverse blocking transistor 91 to the ‘ off ’ state for low load currents , and only turn it on via charge pump signal 732 for currents above a given threshold , where it is important to reduce heat dissipation in the output channel . for low currents the heat dissipation produced by the voltage drop of backup diode 92 is negligible , but if all channels were operating at high output currents the cumulative aggregate heat buildup would be excessive . a further aspect of the preferred embodiment of the invention is the protection of the digital output channels and their loads from over - voltage transients . the transient suppression module 99 will now be described in more detail with reference to fig1 . the transient suppression module 99 receives the channel output signal 753 via the reverse blocking transistor 91 and provides signal 761 to drive the channel load and signal 762 to the voltage monitors and a / d converters 78 b . the module comprises two avalanche diodes 131 , 132 in series , and two resistors 133 , 134 one parallel with each avalanche diode and forming a voltage divider across them . this allows the avalanche diodes to be continuously monitored for short circuit faults when the channel is in the energized state . short circuit failures are the predominant failure mode for this type of device , so the resulting diagnostic coverage is very beneficial . during the test sequence illustrated in fig1 , when the channel is in an ‘ on ’ state and is being tested for the ability to be de - energised , the reverse blocking circuit 76 may be used as described previously to break the connection between the channel failsafe switch 75 and the channel load prior to starting the test sequence . this enables the channel to be tested for the ability to be de - energised even when another parallel channel is energising the load . thus when the drive signal 721 is ramped up and the fet 801 , 802 under test starts to turn off the measured voltage 752 across a self - diagnostic “ turn - off test ” resistor 33 will drop as illustrated in fig1 to indicate that the fet 801 , 802 is successfully being de - energised . this voltage decrease is independent of the load current , and applies equally well to the case where another output channel is energizing the load in parallel . as a prerequisite to guard against latent open circuit failures of an output channel not being tested , and to prevent an inadvertent de - energisation of the load , the comparators 83 may be used to verify that when an output channel under test is turned off the load voltage stays up or is maintained at a desired value . thusly qualified , the output channel under test may simply be commanded to turn off one switch at a time and verify that the top vmon signal 752 ( fig1 ) decays when the reverse blocking circuit breaks the connection between the channel failsafe switch 75 and the channel load . an exemplary application of this method employs a software test executive operating as part of processor assembly 24 . the software test executive has the responsibility to set the current and voltage ( imon and vmon ) thresholds and to trigger the start of the ramp tests . after a given ramp test has completed , the software test executive examines the results to assess whether a threshold has been crossed . some tests are guard tests , or tests performed before the execution of the normal test , and a threshold crossing observed during the execution of a guard test indicates the presence of a fault in the other fet , and registers or provides an indication or instruction that the normal test should not be performed , or the load will experience an unintentional change of state . if the guard tests complete successfully , that is without a threshold crossing , then the normal ramp test may be performed without concern over bumping of the load . an expected result of the subsequent normal test is for the imon or vmon thresholds to be crossed during the ramp of the fet towards the opposite state . the absence of a threshold crossing would be indicative of a fault being present in the fet being ramped . one benefit of the above method is to provide accurate detection of short circuit load faults for a de - energized channel . this is done by storing both the imon and vmon a / d values when one or the other crosses the specified threshold . by computing the ratio of load voltage to load current at the time of the trip or crossing of the threshold , the load resistance can be estimated . if the estimated load resistance is below a determined threshold , for example 12 ohms for a 24v 1 amp nominal application , then the user may be alerted to an abnormal field condition so that repair operations may be performed before the load is actually energized . avoidance of such occurrences reduces the detrimental consequences commonly associated with such events . it will be appreciated that certain features of the invention , which are , for clarity , described in the context of separate embodiments , may also be provided in combination in a single embodiment . conversely , various features of the invention which are , for brevity , described in the context of a single embodiment , may also be provided separately , or in any suitable combination . it is to be recognized that various alterations , modifications , and / or additions may be introduced into the constructions and arrangements of parts described above without departing from the scope of the present invention as defined in the appended claims .