text: hereafter , examples will be provided to illustrate the embodiments of the present invention . other advantages and effects of the invention will become more apparent from the disclosure of the present invention . it should be noted that these accompanying figures are simplified . the quantity , shape and size of components shown in the figures may be modified according to practically conditions , and the arrangement of components may be more complex . other various aspects also may be practiced or applied in the invention , and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications . a copper sheet or a silicon wafer was used as a sample to be electroplated . in the case of using a silicon wafer as a sample to be electroplated , one or more conductive layers , such as a chromium layer , a titanium layer , a copper layer or a gold layer , must be formed on the surface of the silicon wafer in a single - layered or multi - layered structure as seeding layers . herein , the present test used a copper sheet manufactured by cold rolling as a sample to be electroplated , and the copper sheet was cut into a size of 2 × 2 mm so as to make the sequent observation and measurement more easily . sand paper no . 4000 was used to remove macroscopic defects on the surface of the copper sheet , such as oxide layers and scars , to enhance the surface flatness and electroplating properties . subsequently , 1 μm of aluminum oxide sand was used to reduce the surface roughness of the sheet to obtain the luminous surface . next , the ground and polished sheet was dipped in an acid degreasing fluid at 60 - 70 ° c . for 3 - 5 minutes to remove oil sludge generated from the process of cutting the copper sheet . the dipped copper sheet was washed by deionized water and then dried by nitrogen stream . subsequently , since the copper sheet is easy to be oxidized , the copper sheet has to be placed into an acid etching liquid to remove oxide layers before performing an electroplating process . accordingly , the copper sheet was in the order of being dipped in an etching liquid for about 1 - 3 minutes at room temperature , being washed by deionized water , and being dried by nitrogen stream . then , the washed copper sheet was placed at a cathode , and a platinized titanium mesh was used as an anode . the cathode and anode were placed into an electroplating bath , and the distance between the cathode and the anode was adjusted to be within 10 - 20 cm . accordingly , a ni — pd alloy layer was formed by electroplating at 25 ° c . with a current density of about 1 a / dm 2 . finally , the sheet was washed by deionized water and then dried by nitrogen stream . a surface profiler was used to measure the thickness of the ni — pd alloy layer ( about 5 . 06 um ). also , a person having ordinary knowledge in the art can form a ni — pd alloy layer of various thickness ( e . g . 3 - 6 um ) by modifying the electroplating time . in addition , a field emission electron probe x - ray micro analyzer ( fe - epma ) was used to analyze the amount of palladium in the ni — pd alloy layer . the table 1 below shows the amount of palladium in the ni — pd alloy layer manufactured under different electroplating conditions . as shown in fig2 , a substrate body 21 , including a plurality of first conductive pads 211 and a first solder mask 212 on a first surface thereof and a plurality of second conductive pads 213 and a second solder mask 214 on a second surface ( opposite to the first surface ) thereof , was provided . herein , the first solder mask 212 and the second solder mask 214 have a plurality of first openings h 1 and second openings h 2 to expose the first conductive pads 211 and second conductive pads 213 , respectively . subsequently , the first conductive pads 211 in the first openings h 1 and the second conductive pads 213 in the second openings h 2 were provided with a ni — pd alloy layer 221 , 231 in thickness of about 5 . 06 μm thereon by electroplating as a first surface finish layer 22 and a second surface finish layer 23 , respectively . herein , the second conductive pads 213 were arranged into a ball grid array . in detail , the process for electroplating the ni — pd alloy layer 221 , 231 according to the present example is illustrated as follows . the substrate body 21 was placed at a cathode , and a platinized titanium net was used as an anode . the cathode and anode were placed into an electroplating bath , and the distance between the cathode and the anode was adjusted to 10 - 20 cm . accordingly , a ni — pd alloy layer was formed by electroplating under a current density of about 1 a / dm 2 at 25 ° c . herein , the electroplating conditions as shown in the sheet a of table 1 was applied in the present example . finally , the packaging substrate 200 by the electroplating process was washed by deionized water and dried by nitrogen steam . accordingly , the ni — pd alloy layer 221 , 231 formed by the present example contains palladium in an amount of about 1 atom %. thereby , as shown in fig2 , the present example provide a packaging substrate 200 , including : a substrate body 21 including a plurality of first conductive pads 211 on a first surface thereof and a plurality of second conductive pads 213 on a second surface thereof ; and a first surface finish layer 22 and a second surface finish layer 23 , disposed on the first conductive pads 211 and the second conductive pads 213 , respectively , therewith each of the first surface finish layer 22 and the second surface finish layer 23 including a ni — pd alloy layers 221 , 231 . fig3 shows a cross - sectional view of a packaging substrate 200 according to another preferred example of the present invention . as shown in fig3 , a substrate body 21 , including a plurality of first conductive pads 211 and a first solder mask 212 on a first surface thereof and a plurality of second conductive pads 213 and a second solder mask 214 on a second surface ( opposite to the first surface ) thereof , was provided . herein , the first solder mask 212 and the second solder mask 214 have a plurality of first openings h 1 and second openings h 2 to expose the first conductive pads 211 and second conductive pads 213 , respectively . subsequently , the first conductive pads 211 in the first openings h 1 and the second conductive pads 213 in the second openings h 2 were provided with a ni — pd alloy layer 221 , 231 in thickness of about 5 . 06 μm and a gold layer 222 , 232 in thickness of about 0 . 02 μm thereon by electroplating as a first surface finish layer 22 and a second surface finish layer 23 , respectively . herein , the second conductive pads 213 were arranged into a ball grid array . in detail , the process for electroplating the ni — pd alloy layer 221 , 231 according to the present example is illustrated as follows . the substrate body 21 was placed at a cathode , and a platinized titanium net was used as an anode . the cathode and anode were placed into an electroplating bath , and the distance between the cathode and the anode was adjusted to 10 - 20 cm . accordingly , a ni — pd alloy layer was formed by electroplating under a current density of about 1 a / dm 2 at 25 ° c . herein , the electroplating conditions as shown in the sheet b of table 1 was applied in the present example . finally , the packaging substrate 200 by the electroplating process was washed by deionized water and dried by nitrogen steam . accordingly , the ni — pd alloy layer 221 , 231 formed by the present example contains palladium in an amount of about 3 atom %. thereby , as shown in fig3 , the present example provide a packaging substrate 200 , including : a substrate body 21 including a plurality of first conductive pads 211 on a first surface thereof and a plurality of second conductive pads 213 on a second surface thereof ; and a first surface finish layer 22 and a second surface finish layer 23 , disposed on the first conductive pads 211 and the second conductive pads 213 , respectively , therewith each of the first surface finish layer 22 and the second surface finish layer 23 including a ni — pd alloy layers 221 , 231 , and a gold layer 222 , 232 disposed on the ni — pd alloy layer 221 , 231 . fig4 shows a cross - sectional view of a chip 300 according to one preferred example of the present invention . as shown in fig4 , a chip body 31 , including a plurality of electrode pads 311 and a passivation layer 312 on a first surface thereof , was provided . herein , the passivation layer 312 has a plurality of openings h 3 to expose the electrode pads 311 . subsequently , the electrode pads 211 in the openings h 3 were provided with a ni — pd alloy layer 321 in thickness of about 5 . 06 μm thereon by electroplating as a first surface finish layer 32 . in detail , the process for electroplating the ni — pd alloy layer 321 according to the present example is illustrated as follows . the chip 31 was placed at a cathode , and a platinized titanium net was used as an anode . the cathode and anode were placed into an electroplating bath , and the distance between the cathode and the anode was adjusted to 10 - 20 cm . accordingly , a ni — pd alloy layer was formed by electroplating under a current density of about 1 a / dm 2 at 25 ° c . herein , the electroplating conditions as shown in the sheet a of table 1 was applied in the present example . finally , the chip 300 by the electroplating process was washed by deionized water and dried by nitrogen steam . accordingly , the ni — pd alloy layer 321 formed by the present example contains palladium in an amount of about 1 atom %. thereby , as shown in fig4 , the present example provide a chip 300 , including : a chip body 31 including a plurality of electrode pads 311 on a first surface thereof ; and a first surface finish layer 32 disposed on the electrode pads 311 and including a ni — pd alloy layers 321 . fig5 shows a cross - sectional view of a chip 300 according to another preferred example of the present invention . as shown in fig5 , a chip body 31 , including a plurality of electrode pads 311 and a passivation layer 312 on a first surface thereof , was provided . herein , the passivation layer 312 has a plurality of openings h 3 to expose the electrode pads 311 . subsequently , the electrode pads 211 in the openings h 3 were provided by electroplating in the order with a ni — pd alloy layer 321 in thickness of about 5 . 06 μm and a gold layer 322 in thickness of about 0 . 02 μm thereon as a first surface finish layer 32 . in detail , the process for electroplating the ni — pd alloy layer 321 according to the present example is illustrated as follows . the chip 31 was placed at a cathode , and a platinized titanium net was used as an anode . the cathode and anode were placed into an electroplating bath , and the distance between the cathode and the anode was adjusted to 10 - 20 cm . accordingly , a ni — pd alloy layer was formed by electroplating under a current density of about 1 a / dm 2 at 25 ° c . herein , the electroplating conditions as shown in the sheet c of table 1 was applied in the present example . finally , the chip 300 by the electroplating process was washed by deionized water and dried by nitrogen steam . accordingly , the ni — pd alloy layer 321 formed by the present example contains palladium in an amount of about 5 atom %. thereby , as shown in fig5 , the present example provided a chip 300 , including : a chip body 31 including a plurality of electrode pads 311 on a first surface thereof ; and a first surface finish layer 32 disposed on the electrode pads 311 and including a ni — pd alloy layers 321 and a gold layer 322 , therewith the gold layer 322 being disposed on the ni — pd alloy layers 321 . fig6 shows a cross - sectional view of a package structure according to one preferred example of the present invention . as shown in fig6 , the chip 300 prepared by example 3 was attached to the packaging substrate 200 prepared by example 1 via a plurality of first connecting units 51 in a flip - chip manner . in detail , the electrode pads 311 of the chip 300 electrically communicate with the first conductive pads 211 of the packaging substrate 200 via the first connecting units 51 . in addition , the second conductive pads 213 of the packaging substrate 200 electrically communicate with the third conductive pads 411 of the circuit board 400 via the second connecting units 52 . herein , the circuit board 400 includes : a circuit board body 41 including a plurality of third conductive pads 411 and a solder mask 412 on a first surface thereof , therewith the solder mask 412 having a plurality of openings h 4 to expose the third conductive pags 411 ; and a third surface finish layer 42 disposed on the third conductive pads 411 . in the present example , the third surface finish layer 42 of the circuit board 400 is an organic solderability preservative layer . thereby , as shown in fig6 , the present example provide a package structure , including : a chip 300 including a plurality of electrode pads 311 on a first surface thereof ; a packaging substrate 200 including a plurality of first conductive pads 211 on a first surface thereof and a plurality of second conductive pads 213 on a second surface thereof ; a plurality of first connecting units 51 through which the electrode pads 311 electrically communicate with the first conductive pads 211 ; a circuit board 400 including a plurality of third conductive pads 411 on a first surface thereof ; and a plurality of second connecting units 52 through which the second conductive pads 213 electrically communicate the third conductive pads 411 . herein , the packaging substrate 200 further includes a first surface finish layer 22 and a second surface finish layer 23 disposed on the first conductive pads 211 and the second conductive pads 213 , respectively ; the chip 300 further includes a first surface finish layer 32 disposed on the electrode pads 311 ; and the circuit board 400 further includes a third surface finish layer 42 disposed on the third conductive pads 411 . in the present example , the first surface finish layer 22 , 32 and the second surface finish layer 23 each include a ni — pd alloy layer 221 , 231 , 321 . fig7 shows a cross - sectional view of a package structure according to another preferred example of the present invention . as shown in fig7 , the chip 300 prepared by example 4 was attached to the packaging substrate 200 prepared by example 2 via a plurality of first connecting units 51 in a flip - chip manner . in detail , the electrode pads 311 of the chip 300 electrically communicate with the first conductive pads 211 of the packaging substrate 200 via the first connecting units 51 . in addition , the second conductive pads 213 of the packaging substrate 200 electrically communicate with the third conductive pads 411 of the circuit board 400 via a plurality of second connecting units 52 . herein , the circuit board 400 includes : a circuit board body 41 including a plurality of third conductive pads 411 and a solder mask 412 on a first surface thereof , therewith the solder mask 412 having a plurality of openings h 4 to expose the third conductive pads 411 ; and a third surface finish layer 42 disposed on the third conductive pads 411 . in the present example , the third surface finish layer 42 of the circuit board 400 is an organic solderability preservative layer . thereby , as shown in fig7 , the present example provide a package structure , including : a chip 300 including a plurality of electrode pads 311 on a first surface thereof ; a packaging substrate 200 including a plurality of first conductive pads 211 on a first surface thereof and a plurality of second conductive pads 213 on a second surface thereof ; a plurality of first connecting units 51 through which the electrode pads 311 electrically communicate with the first conductive pads 211 ; a circuit board 400 including a plurality of third conductive pads 411 on a first surface thereof ; and a plurality of second connecting units 52 through which the second conductive pads 213 electrically communicate the third conductive pads 411 . herein , the packaging substrate 200 further includes a first surface finish layer 22 and a second surface finish layer 23 disposed on the first conductive pads 211 and the second conductive pads 213 , respectively ; the chip 300 further includes a first surface finish layer 32 disposed on the electrode pads 311 ; and the circuit board 400 further includes a third surface finish layer 42 disposed on the third conductive pads 411 . in the present example , the first surface finish layer 22 , 32 and the second surface finish layer each include a ni — pd alloy layer 221 , 231 , 321 and a gold layer 222 , 232 , 322 . the above examples are intended for illustrating the embodiments of the subject invention and the technical features thereof , but not for restricting the scope of protection of the subject invention . the scope of the subject invention is based on the claims as appended .