text: fig1 a shows an electrical schematic circuit diagram of an sram ( static random access memory ) implementation of this invention . fig1 a shows a four transistor sram cell , which is a modified four transistor cell , in accordance with this invention in which the conventional load resistors have been replaced by integrated circuit capacitors formed by lower plate 21 ( lower layer 19 / contact layer 14 fig2 ) and upper plate 48 separated by a tunnel oxide dielectric layer 17 , as shown in an elevational cross - section in fig2 . the cell of fig1 a comprises an inverter with cross - coupled storage ( driver ) transistors t1 and t2 which serving as a storage flip flop circuit , and a pair of load capacitors c1 and c2 which provide in addition to capacitance , a leakage or tunneling current along with a minimal load resistance , as indicated by the equivalent circuit shown in fig1 b , and access ( pass / transfer ) transistors t3 and t4 . storage transistors t1 and t2 have their drain regions connected respectively to nodes a1 and a2 and their control gate electrodes cross - coupled respectively via polysilicon gate lines pl1 and pl2 to nodes a2 and a1 . both access transistors t3 and t4 have their control gate electrodes connected to the wordline wl . as stated above , the sram cell of fig1 a includes two load capacitors c 1 and c 2 which replace the resistors r1 and r2 shown in fig4 . load capacitor c 1 is connected between a terminal connected to power supply voltage vcc and via node a1 through a contact df2 to the drain region of transistor t1 and to the control gate electrode of transistor t2 . load capacitor c2 is connected between power supply voltage vcc and via node a2 through a contact df2 to the drain of transistor t2 . the source regions of transistors t1 are t2 are connected via node a5 to ground , i . e . reference potential . access transistor t3 has its control gate electrode connected to wordline wl and its s / d circuit connected between node a1 and node a4 which is connected to bit line bl . access transistor t4 has its control gate electrode connected to wordline wl and its s / d circuit connected between node a2 and node a3 which is connected to bit line bl - bar . the source region of access transistor t3 is connected to node a1 . the source region of access transistor t4 is connected to node a2 . the current i 1 flows from terminal vcc through load capacitor c1 towards node a1 . the current i 2 flows from terminal vcc through load capacitor c2 towards node a2 . fig1 b shows the equivalent circuit for the capacitors c1 and c2 which have a capacitor c and a resistor r which carries the leakage current through the capacitor c . the leakage current is a fraction of the current through a conventional resistor having a value of from about 10 7 ohms to about 10 13 ohms . the capacitor has a capacitance from about 0 . 01 femtofarads ( 10 - 15 farads ) to about 10 femtofarads ( 10 - 15 farads ). fig2 shows a sectional view of a portion of an sram device 8 in accordance with fig1 a and 1b taken along line 2 -- 2 &# 39 ; in fig3 . the p -- doped substrate 10 has a pair of field oxide ( fox ) regions 12 and 12 &# 39 ; formed thereon with a buried contact region 13 ( bc1 ) therebetween . the buried contact region is counterdoped with n - type dopant with respect to the p -- doped substrate 10 . a lower plate 21 of a capacitor 60 comprises laminated polysilicon conductor bottom layer 19 and contact layer 14 formed over a portion of the surface of substrate 10 between fox regions 12 and 12 &# 39 ;, and extending upon the curved upper surface of the fox region 12 &# 39 ; and extending beyond , partially across the flat surface of fox region 12 &# 39 ;. the contact layer 14 of the lower plate 21 reaches down into electrical and mechanical contact with the surface of region 13 . above the polysilicon contact layer 14 of the lower plate 21 is formed a tunnel oxide layer 17 composed of silicon dioxide formed by thermal oxidation with a mixture of n 2 / o 2 at a temperature from about 800 ° c . to about 900 ° c . the tunnel oxide layer 17 has a thickness from about 50 å to about 500 å . a second polysilicon conductor 48 has been deposited over the device covering the tunnel oxide layer 17 or has been patterned to extend across ( overlap ) an edge of the contact layer 14 above the tunnel oxide layer 17 above the flat surface of fox region 12 &# 39 ; split between covering the surface of layer 17 and covering the surface of the field oxide region 12 &# 39 ; beyond the tunnel oxide layer 17 . the tunnel oxide layer 17 is thin enough to provide a significant leakage current density j which as described in equations 1 and 2 below , which is an inverse function of t ox ( the thickness of the tunnel oxide ) and a direct function of the surface area of the overlap between polysilicon contact layer 14 and the polysilicon layer 48 for the capacitor 60 . a & amp ; b are constants ## equ1 ## where t ox = thickness of tunnel oxide layer 17 fig8 shows a sectional view of an alternative embodiment to fig2 of a portion of an sram device 200 in accordance with fig1 a and 1b . the p - doped substrate 210 has a field oxide ( fox ) region 212 formed thereon with an n + doped , buried contact region 213 ( bc1 ) formed in substrate 210 adjacent to the fox region 212 . a lower plate 214 ( contact layer ) of a capacitor 260 comprises a polysilicon conductor formed over fox region and over a corner of the surface of region 213 adjacent to fox region 212 extending partially across the flat surface of fox region 212 . in summary , the contact layer 214 is the lower plate of a capacitor 260 , and layer 214 , which overlies the fox region 212 reaches down into electrical and mechanical contact with the surface of buried contact region 213 . above the polysilicon contact layer 214 ( lower plate ) is formed a tunnel oxide layer 217 having a thickness from about 50 å to about 500 å composed of silicon dioxide formed by thermal oxidation with a mixture of n 2 / o 2 at a temperature from about 800 ° c . to about 950 ° c . a second polysilicon conductor 248 has been deposited over the device covering the tunnel oxide layer 217 and a portion of the gate oxide layer 216 above the flat surface of fox region 212 . fig3 shows a plan view of the device of fig2 showing the fox regions 12 , and 12 &# 39 ; with the buried contact region bc1 between the n + doped drain region 13 and the portion of the polysilicon contact layer 14 which comprises the lower plate 21 of a capacitor 60 such as capacitors c1 and c2 . the upper plate 48 is shown with the tunnel oxide opening area to . referring to fig8 an alternative design of the device of fig2 is shown . referring again to fig1 and 2 , the buried contact bc2 is defined by the steps as follows : 1 . deposit a gate oxide layer 16 , having a thickness between about 350 å and about 2 , 000 å . 2 . form a photoresist mask over layer 16 patterned to define a window for contact to . 3 . grow a tunnel oxide layer 17 having a thickness between about 50 å and about 500 å by means of a thermal growth process . 4 . deposit polysilicon layer 48 and form a mask to define the shape thereof . fig5 shows a chart of current density j vs . voltage v for the tunnel oxide in accordance with this invention . fig6 a - 6h are sectional views of the device of fig2 illustrating the process of forming the device of fig2 . in fig6 a , the device of fig2 and 3 is shown in an early stage of manufacture of device 8 . at this stage , device 8 includes a p - doped substrate 10 has a pair of field oxide ( fox ) regions 12 and 12 &# 39 ; formed on the surface thereof , with an n + doped buried contact region 13 therein . region 13 is counterdoped with respect to the p - doped substrate 10 with n - type dopant provided by ion implantation with n - type ions 13 &# 39 ; such as arsenic or phosphorus dopant with a dose from about 1 × 10 13 atoms / cm 2 to about 1 × 10 15 atoms / cm 2 at an energy level from about 40 kev to about 150 kev . in fig6 b , a gate oxide layer gox has been formed over the exposed surface of p - doped substrate 10 between the field oxide ( fox ) regions 12 and 12 &# 39 ;. gate oxide layer gox is formed by depositing a gate oxide layer having a thickness between about 50 å and about 200 å over the surface of substrate 10 . next , a bottom , doped polysilicon layer 19 ( part of the laminated lower capacitor plate 21 ) has been formed over the gate oxide layer gox and the exposed surfaces of the field oxide ( fox ) regions 12 and 12 &# 39 ;. bottom layer 19 has a thickness between about 400 å and about 4000 å . referring to fig6 c , a buried contact photoresist mask 31 has been formed over bottom layer 19 patterned to define a bc1 mask 31 with an opening 31 &# 39 ; above the gate oxide region between the fox regions 12 , 12 &# 39 ;, but covering the portion of bottom layer 19 above fox region 12 &# 39 ;. next , using the bc1 mask 31 , polysilicon bottom layer 19 and gate oxide layer gox are etched away over fox region 12 and between fox regions 12 , 12 &# 39 ;. then mask 31 is stripped from device 8 . referring to fig6 d , the doped polysilicon contact layer 14 of the lower capacitor plate 21 has been deposited in a blanket deposition having a thickness between about 1000 å and about 4000 å . contact layer 14 reaches down into contact with buried contact layer 13 ( bc1 ) and covers bottom layer 19 and fox region 12 &# 39 ; beyond bottom layer 19 . the contact layer 14 is in direct electrical and mechanical contact with the n + doped buried contact region 13 forming an electrical contact therewith . the contact layer 14 is covered with a photoresist mask 15 which covers the area where the lower plate 21 of the capacitor 60 is to be formed . then , referring to fig6 e , a mask 15 for shaping the lower capacitor plate 21 is formed over the contact layer 14 . mask 15 has a first opening 15 &# 39 ; over fox region 12 and the surface of buried contact region 13 which is to be exposed . the mask 15 has an opening 15 &# 34 ; over the portion of fox region 12 &# 39 ; which is to be exposed . using the mask 15 , the lower plate 21 of the capacitor 60 has been patterned by etching away the unwanted portions of contact layer 14 and layer 15 below the openings 15 &# 39 ; and 15 &# 34 ;. then the mask 15 is stripped away thereafter . referring to fig6 f , the device 8 of fig6 e is shown after a layer of oxide 16 having a thickness between about 350 å and about 2 , 000 å , was formed . then a photoresist mask 95 was formed over fox region 12 &# 39 ; and over the end of the upper surface of layer 14 leaving the remainder of layer 14 exposed with an opening 95 &# 39 ; over contact layer 14 . opening 95 &# 39 ; frames the pattern of the window to over the exposed portion of contact layer 14 . the surface of layer 16 exposed through opening 95 &# 39 ; in mask 95 will then be etched away down to contact layer 14 and fox region 12 &# 39 ; by diluted hydrogen fluoride ( hf ) chemical solution as can be seen in fig6 g . then , when mask 95 is stripped away from device 8 the window to remains leaving the right end of contact layer 14 and bottom layer 19 exposed as well as the upper surface of fox region 12 &# 39 ; on the right end of device 8 . as shown in fig6 g , in a process of thermal oxidation , a tunnel oxide layer 17 has been formed in window to covering the exposed surfaces of doped first polysilicon contact layer 14 including the sidewall over fox region 12 &# 39 ; exposed by the previous etching step in fig6 e , and the exposed surface of the field oxide region 12 &# 39 ;. the thermal oxidation is performed with a mixture of n 2 / o 2 at a temperature from about 800 ° c . to about 900 ° c . the tunnel oxide layer 17 has a thickness from about 50 å to about 500 å . referring to fig6 h , the upper plate of the capacitor 60 was formed by blanket deposition of a doped , second polysilicon layer 48 , which has been partially etched away . after upper plate layer 48 was formed by the blanket deposition over the product of fig6 g covering the exposed surfaces of fox regions 12 , 12 &# 39 ; and covering the tunnel oxide layer 17 , etc . a photoresist mask 49 was formed , as shown in fig6 h , covering the portion of the layer 48 which is to be employed as the upper plate of the capacitor 60 of fig2 . as shown in fig6 h the device 10 is shown after the step of etching away the portions of upper plate layer 48 unprotected by the mask 49 to pattern the upper plate 48 of the capacitor 60 . fig2 shows the finished device of fig6 h after stripping away the mask 49 . fig7 a - 7h are sectional views of a fragment of a device 100 , similar to the device of fig2 illustrating an alternative process of forming a device 100 in accordance with this invention in connection with other elements of the sram device of fig1 . in fig7 a , device 100 is shown in an early stage of manufacture . device 100 includes an n - doped substrate 100 in which a p - doped well 110 has been formed . in a portion of the well 110 , a conventional field oxide ( fox ) region 122 is formed extending above the surface of p - doped well 10 and down within the well 110 . above the remainder of the surface of the p - well 110 aside from the fox region 122 is formed a gate oxide layer gox comprising a silicon oxide layer having a thickness between about 50 å and about 200 å . next , a blanket , doped , polysilicon bottom layer 119 , which is part of the laminated lower capacitor plate 121 , has been formed over gate oxide layer gox and over the surface of fox region 122 . bottom layer 119 has a thickness between about 400 å and about 4000 å . next , a mask 131 for buried contact bc1 is formed over layer 119 with a buried contact window opening 131 &# 39 ; extending therethrough above the location where the buried contact region 134 ( bc1 ) is to be formed in well 110 . in fig7 b , the product of fig7 a is shown with window 131 &# 39 ; located to the left of the fox region 122 in the mask 131 . using the mask 131 , the polysilicon layer 119 is etched away below the window opening 131 &# 39 ; using a conventional anisotropic etching process . the gate oxide layer gox is also etched away through the opening window 131 &# 39 ; in a conventional anisotropic etching process extending the window 131 &# 39 ; down to the surface of p - well 110 . the layer 119 has been modified to the extent that layer 119 to the left of window 131 &# 39 ; remains in place for use in formation of a control gate electrode ( as shown in fig7 d ) and the lower layer 119 &# 39 ; of a lower plate 121 ( as seen in fig7 d ) of a capacitor 160 being formed ( as seen in fig7 g and 7h ), which overlies the fox region 122 . in the next step , using mask 131 , n - type ions 133 are ion implanted to form counterdoped n + region 134 ( bc1 ) in p - well 110 . the ions 133 pass through the buried contact window opening 131 &# 39 ; to form an n + doped buried contact region 134 ( bc1 ) adjacent to fox region 122 . the ions 133 are implanted with n - type dopant such as arsenic or phosphorus with a dose from about 1 × 10 13 atoms / cm 2 to about 1 × 10 16 atoms / cm 2 at an energy level from about 40 kev to about 150 kev . fig7 c shows the product of fig7 b after the mask 131 was stripped from device 100 , leaving the lower portion 119 of the control electrode 120 and the lower portion 119 &# 39 ; of capacitor plate 121 exposed , as well as the surface of buried contact region 134 ( bc1 ). next , a polysilicon contact layer 114 ( which is the upper portion of the lower capacitor plate 121 ) was deposited in a blanket deposition having a thickness between about 1000 å and about 4000å . contact layer 114 reaches down between layer 119 and bottom layer 119 &# 39 ; through window 134 &# 39 ; into contact with buried contact region 134 ( bc1 ) and covers bottom gate electrode layer 119 to the left of buried contact region 134 , as well bottom layer 119 &# 39 ; and fox region 122 beyond bottom layer 119 &# 39 ; over the buried contact region 134 . referring to fig7 d , the contact layer 114 was then covered with a photoresist mask 115 which was patterned with openings 115 &# 39 ; and 115 &# 34 ; therethrough . mask 115 covers the areas which are to be formed into the lower plate 121 of a capacitor 160 and the control gate electrode 120 for a transistor to be formed subsequently , as well as the contact layer 114 &# 39 ; of the lower plate 121 of a capacitor 160 of the kind shown in fig2 . control gate electrode 120 ( formed of layers 114 and 119 ) and bottom plate 121 ( formed of layers 119 &# 39 ; and 114 &# 39 ;) have been formed by etching away the unwanted portions of the contact layer 114 and bottom layer 119 leaving portions thereof ( upper gate layer 114 and contact layer 114 &# 39 ;) beneath the mask 115 between the center of buried contact region 134 and to the right of gate electrode 120 , and the gate electrode well to the left of buried contact region 134 . window 115 &# 39 ; is formed over the left side of the contact layer 114 &# 39 ; and to the right of the gate electrode 120 . window 115 &# 34 ; is formed to the left side of the gate electrode 120 . thus the gate electrode 120 ( upper gate layer 114 ) remains over gate oxide layer gox . the contact layer 114 &# 39 ; of the lower plate 121 is in direct electrical contact with the buried contact region 134 ( bc1 ). in addition layers 119 &# 39 ; and 114 &# 39 ; extend up the surface of fox region 122 onto a portion of the flat upper surface of fox region 122 . fig7 e shows the product of fig7 d after the mask 115 has been stripped from device 100 . a layer of silicon dioxide 116 having a thickness from above 350 å and about 2 , 000 å has been formed . then a photoresist mask 195 has been formed over silicon dioxide layer 116 . mask 195 is above a portion of fox region 122 , the gate oxide layer gox , upper gate layer 114 and a portion of the left end of contact layer 114 &# 39 ;, leaving the remainder of layer 116 above the upper surface of contact layer 114 &# 39 ; exposed with an opening 195 &# 39 ; located there , above layer 116 , over contact layer 114 &# 39 ;. an opening 195 &# 39 ; in mask 195 extends over a portion of buried contact 134 ( bc1 ) and a portion of fox region 122 . the exposed portion of silicon dioxide layer 116 below opening 195 &# 39 ; is etched off by a diluted hydrogen fluoride ( hf ) solution as can be seen by reference to fig7 f where layer 116 has been removed by etching . fig7 f shows the product of fig7 e after the mask 195 has been stripped therefrom . the next step is that the exposed surface of contact layer 114 &# 39 ; and layer 119 &# 39 ; of the lower capacitor plate 121 are coated with a tunnel oxide layer 117 which is formed by thermal oxidation as explained above in connection with fig6 g . referring to fig7 g , a second polysilicon layer 148 was deposited in a blanket deposition over the device 100 . then a mask 149 was formed over the layer 148 to form the upper electrode plate 148 of the capacitor 160 being deposited over the exposed portions of tunnel oxide layer 117 by etching away the unwanted remaining portions of layer 148 . fig7 h shows the product of fig7 g after the mask 149 has been stripped from the device and shows the completed capacitor 160 formed by lower plate 121 ( layers 114 &# 39 ;/ 119 &# 39 ;) tunnel oxide layer 117 and the upper plate layer 148 of capacitor 160 . then , n - type ions 192 are implanted into regions 196 / 198 self - aligned with the control gate electrode 114 / 119 to form source / drain regions 196 / 198 in p - well 110 . the source / drain regions 196 / 198 are electrically connected through well 110 via the buried contact 134 ( bc1 ) to the lower plate 121 of the capacitor 160 . fig9 a - 9d are sectional views of the device 200 of fig8 illustrating the process of forming the device 200 . in fig9 a , the device of fig8 is shown in a later stage of manufacture of device 200 since the earlier steps will be understood by the descriptions of the earlier embodiments . at this stage , device 200 includes a p - doped substrate 210 has a field oxide ( fox ) region 212 formed on the surface thereof , with an n + doped buried contact region 213 ( bc1 ) therein . region 213 was counterdoped with respect to the p - doped substrate 210 with n - type dopant provided by ion implantation with n - type ions such as arsenic or phosphorus dopant with a dose from about 1 × 10 18 atoms / cm 2 to about 1 × 10 21 atoms / cm 2 at an energy level from about 40 kev and about 150 kev . a doped polysilicon lower plate ( contact layer ) 214 , which comprises the lower capacitor plate , was deposited in a blanket deposition having a thickness between about 1000 å and about 4000 å and then etched to the pattern shown . at one end , lower plate 214 reaches down into contact with the buried contact layer 213 ( bc1 ) and covers fox region 212 . the lower plate ( contact layer ) 214 is in direct electrical and mechanical contact with the n + doped buried contact region 213 forming an electrical contact therewith . the lower plate 214 of the capacitor 260 has been patterned by etching away the unwanted portions of contact layer 214 as will be understood by the descriptions above of other embodiments . referring to fig9 b , then a silicon dioxide layer 216 , having a thickness between about 350 å and about 2 , 000å , is formed over the exposed surface of lower plate 214 . next , the device 200 of fig9 a has a photoresist mask 295 formed over the whole surface of device 200 except for a window 295 &# 39 ; formed over a portion surface of layer 216 above the upper surface of layer 214 . the silicon dioxide layer 216 below window 295 &# 39 ; is then etched off by a diluted aqueous solution of hydrogen fluoride ( hf ) chemical . then then , mask 295 is stripped off . then , as shown in fig9 c , following the stripping of mask 295 , a process of thermal oxidation follows in which a thinner tunnel oxide layer 217 having a thickness from about 50 å to about 500 å has been formed in the tunnel oxide window covering the exposed surfaces of doped first polysilicon contact layer 214 . the thermal oxidation is performed with a mixture of n 2 / o 2 at a temperature from about 800 ° c . to about 900 ° c . referring to fig9 d , the upper plate 248 of the capacitor 260 was formed by blanket deposition of a doped , second polysilicon layer 248 , which has been partially etched away . after upper plate layer 248 was formed by the blanket deposition over the product of fig9 g covering the exposed surfaces of fox regions 212 , and covering the tunnel oxide layer 217 , etc . a photoresist mask was formed , ( not shown ), covering the portion of the layer 248 which is to be employed as the upper plate of the capacitor 260 . the mask was used for etching away the portions of upper plate layer to pattern it into the upper plate 248 of the capacitor 260 , as shown . 1 . smaller contact resistance at a1 and a2 ( fig . i ) connection points . 1 . two capacitors c1 and c2 replace the conventional r1 and r2 ( fig4 ) resistors . 2 . the currents i1 and i2 through capacitors c1 and c2 are the tunneling leakage current ( or the tunneling current ) through the capacitors c1 and c2 . a . polysilicon gate lines pl1 and pl2 make connections with diffusion areas of transistors through buried contacts df1 and df2 . b . capacitors c1 and c2 are formed on polysilicon gate lines pl1 and pl2 . 4 . the only difference from conventional fabrication processes is the addition of a step of thermal oxidation , which greatly enhances the value of the product with minimal manufacturing cost . while this invention has been described in terms of the above specific embodiment ( s ), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims , i . e . that changes can be made in form and detail , without departing from the spirit and scope of the invention . accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow .