text: a pwm conversion system 50 for converting a digital modulating signal 52 to a pwm signal 54 is shown in fig4 . the system 50 includes a digital up / down counter ( u / d counter ) 56 that creates a carrier signal 58 and a digital comparator 60 that creates the pwm signal 54 based on a comparison of the modulating signal 52 with the carrier signal 58 . unlike prior art pwm conversion systems , the system 50 includes an analog - to - digital conversion stage 62 that converts a supply voltage vcc to a digital supply signal 64 that sets the maximum value of the carrier signal 58 . as will be shown in more detail below , converting the supply voltage vcc to the digital supply signal 64 and using that signal to set the maximum value of the carrier signal 58 enables the pwm signal 54 to be immune from changes in the supply voltage vcc . the analog - to - digital conversion stage 62 includes an analog - to - digital converter ( adc ) 65 and may include an adc signal processor 66 . the adc 65 receives the analog supply voltage vcc at an input 68 and converts it to an n - bit digital supply voltage 70 at an output 72 . the adc signal processor 66 converts the digital supply voltage 70 output by the adc 65 from an n - bit digital value to an n2 - bit digital value that is output as the digital supply signal 64 . the adc signal processor 66 is only needed if the n bits of the digital supply voltage 70 are different than the n2 bits that are acceptable by the u / d counter 56 . a couple of examples may be helpful to ensure an understanding of the operation of the adc signal processor 66 , first , if the u / d counter 56 can accept 8 - bit ( n2 = 8 ) signals and the adc 65 only outputs 6 - bit ( n = 6 ) signals , then the adc signal processor 66 sets the two most significant bits of the digital supply signal 64 to 1 and includes the 6 bits of the digital supply voltage 70 as the 6 least significant bits without changing them . second , if the u / d counter 56 can accept 8 - bit signals and the adc 65 outputs 10 - bit signals , then the adc signal processor 66 outputs the 8 most significant bits of the digital supply voltage 70 as the digital supply signal 64 . if n = n2 , then the adc signal processor 66 is not needed and the digital supply voltage 70 output by the adc 65 is transmitted directly to the u / d counter 56 as the digital supply signal 64 . the u / d counter 56 has a clock input 74 that receives a clock signal clk and a maximum value input 76 that receives the digital supply signal 64 . like the prior art u / d counter 28 of fig2 the u / d counter 56 counts upward one step at each pulse of the clock signal clk until an &# 34 ; end of count &# 34 ; ( eoc ) value is reached . upon reaching that value the u / d counter 56 counts downward one step at each pulse of the clock signal clk until reaching a minimum possible value , such as zero . upon reaching the minimum possible value , the counter again counts &# 34 ; up &# 34 ; and so forth . unlike the prior art u / d counter 28 , the eoc value for the u / d counter 56 is set to equal the digital supply signal 64 received at the maximum value input 76 . as a result , the carrier signal 58 output by the u / d counter 56 increases until reaching a digital value ( as expressed in the digital supply signal 64 ) corresponding to the analog value of the supply voltage vcc . it will be appreciated that the use of a uid counter is not the only possible choice . another possibility could be that of using an counter that generates a sawtooth profile . the system 50 also may include a modulating signal processor 76 that insures that the modulating signal 52 is expressed in a number of bits acceptable to the digital comparator 60 . for example , if the modulating signal processor 76 receives a modulating signal 78 having 10 bits and the digital comparator 60 requires 8 bits , then the modulating signal processor discards the two least significant bits to create the modulating signal 52 that is acceptable to the digital comparator 60 . if the modulating signal 78 is 7 bits and the comparator 60 requires 8 bits , then the modulating signal processor 76 may multiply by two ( shift left operation ) the modulating signal 78 to obtain the 8 bits of the modulating signal 52 that is input to the comparator 60 . of course , if the number of bits in the modulating signal 78 equals the number of bits acceptable to the comparator 60 , then the modulating signal processor is not needed and the modulating signal 78 is fed directly to the comparator 60 as the modulating signal 52 . the digital comparator 60 , which is powered by the analog supply voltage vcc , includes a first input in1 that receives the modulating signal 52 , a second input in2 that receives the carrier signal 58 , and an output 80 at which the pwm signal 54 is output . at each portion of the modulating signal 52 that is greater than a corresponding portion of the carrier signal 58 , the comparator 60 outputs a logic 1 for a corresponding portion of the pwm signal 54 . similarly , at each portion of the modulating signal 52 that is less than a corresponding portion of the carrier signal , the comparator 60 outputs a logic 0 for a corresponding portion of the pwm signal 54 . converting the supply voltage vcc to the digital supply signal 64 and using that signal to set the maximum value of the carrier signal 58 enables the pwm signal 54 to be immune from changes in the supply voltage vcc . that desirable result occurs because , as described above , the pwm signal 54 results from a logical subtraction of the carrier signal 58 from the modulating signal 52 . since the carrier signal varies directly with the supply voltage vcc and the comparator is powered by the supply voltage vcc , the negative effect of the carrier signal 58 cancels the effect of the supply voltage vcc on the pwm signal 54 . an example may help one to understand the compensation afforded by varying the carrier signal 58 with a digital version ( supply signal 64 ) of the supply voltage vcc . let &# 39 ; s assume that the supply voltage vcc can assume values of 12 v +/- 25 %, the comparator requires 8 bits , and the modulating signal assumes a digital value of 102 ( 01100110 ). configuring the adc 65 in a way that its output will be equal to 204 when the supply voltage is equal to 12v ( nominal value ) we will have that the extreme values of the digital supply signal 64 will be : the average value of the pwm signal 54 is equal to its duty cycle multiplied by the supply voltage vcc provided to the comparator 60 , where the duty cycle of the pwm signal 54 will be : when the supply voltage vcc equals its nominal value of 12 v , the pwm signal 54 has a duty cycle of 50 % ( 102 / 204 * 100 ) and an average value of 6 v ( 12 v * 50 %). when the supply voltage vcc increases to its maximum value of 15 v ( 12 v + 25 %), the pwm signal 54 has a duty cycle of 40 % ( 102 / 255 * 100 ) and an average value of 6 v ( 15 v * 40 %). when the supply voltage vcc decreases to its minimum value of 9 v ( 12 v - 25 %), the pwm signal 54 has a duty cycle of 66 . 67 % ( 102 / 153 * 100 ) and an average value of 6 v ( 9 v * 66 . 67 %). thus , the average value of the pwm signal 54 remains constant regardless of the fluctuations in the supply voltage vcc . fig5 a - c show the signals ( carrier signal , modulating signal , and pwm signal ) for the nominal value ( fig5 a ), maximum value ( fig5 b ), and minimum value ( fig5 c ) of the supply voltage vcc . as can be seen , maximum value of the carrier signal 58 varies directly with the variations of the supply voltage vcc . because the comparator 60 logically subtracts the carrier signal 58 from the modulating signal 52 , the duty cycle of the pwm signal 54 varies inversely with the carrier signal 58 and the supply voltage vcc . given that the average value of the pwm signal 54 is a function of the duty cycle multiplied by the supply voltage vcc powering the comparator 60 , the average value of the pwm signal 54 is immune from variations in that supply voltage vcc . the method and system 50 solve the problem of the variations in the average value of the output voltage of a circuit that converts a digital number to a pwm signal whenever those variations are caused by variations in the supply voltage . the method and system 50 obtain a dynamic profile of the carrier signal 58 that follows the variations of the supply voltage vcc . in other words , increases in the value of the supply voltage vcc tend to produce increases in the amplitude of the carrier signal 58 in such a way that , in parity with the modulating signal 52 , the duty cycle of the resulting pwm signal 54 is reduced . the proposed method is applicable to any converter of the type cited above that utilizes for the conversion a digital counter . the method is based on the observation of the value of the supply voltage by means of an analog digital converter ( adc ). once the value of the supply voltage is known , one can compute a better value for use as the value of the &# 34 ; end of count &# 34 ; ( eoc ) applicable to the digital counter . from the foregoing it will be appreciated that , although specific embodiments of the invention have been described herein for purposes of illustration , various modifications may be made without deviating from the spirit and scope of the invention . accordingly , the invention is not limited except as by the appended claims .