text: referring first to fig1 there is shown a bus driver failure detection system according to a first preferred embodiment of the present invention . the bus driver failure detection system shown is an improvement to the conventional bus driver failure detection system described hereinabove with reference to fig7 to 9 and includes first and second and circuits 121 and 122 , first and second bus drivers 106 and 107 which output different values to a bus 101 , and a receiver 109 for latching a value of the bus 101 , similarly to the conventional bus driver failure detection system of fig7 . the bus driver failure detection system of the present embodiment is different from the conventional bus driver failure detection system in that it additionally includes a bus holding circuit 301 for holding a value of the bus 101 . the first bus driver 106 outputs , when a first bus driver enable signal 104 is selected , a value of a first output signal 102 to the bus 101 in synchronism with a timing signal 108 . meanwhile , the second bus driver 107 outputs , when a second bus driver enable signal 105 is selected , a value of a second output signal 103 to the bus 101 in synchronism with the timing signal 108 . the receiver 109 latches a value of the bus 101 in synchronism with the timing signal 108 . the bus holding circuit 301 holds a value of the bus 101 only when a test signal 203 is active . the bus driver failure detection system of the present invention will be described in more detail below with reference to fig2 and fig3 which shows timing waveforms of several elements of the bus driver failure detection system . fig2 particularly shows a circuit construction of the bus driver failure detection system shown in block diagram in fig1 and shows an example of circuit constructions of the first and second bus drivers 106 and 107 and a circuit construction of the bus holding circuit 301 . it is to be noted that the circuit constructions of the first and second bus drivers 106 and 107 are similar to those of the conventional bus driver failure detection system described hereinabove with reference to fig8 and overlapping description of them is omitted here to avoid redundancy . further , in fig3 a waveform 108 indicates a driver enable signal , another waveform 117 indicates an output of a nand circuit 117 of the second bus driver 107 , a further waveform 111 indicates an output of a nor circuit 111 of the first bus driver 106 , a still further waveform 101 indicates a signal potential of the bus 101 , and a yet further waveform 109 indicates an output waveform of the receiver 109 . the bus holding circuit 301 includes a flip - flop formed from a pair of inverters 302 and 303 the input of each of which is connected to the output of the other inverters , and a transfer gate ( switch ) 304 formed from , for example , an n - channel mos transistor connected between the output terminal of the inverters 303 ( the input terminal of the inverters 302 ) and the bus 101 . the test signal 203 is inputted to the control terminal ( gate electrode ) of the transfer gate 304 . the dimensions ( channel width w and so forth ) of the mos transistor which forms the inverters 303 of the bus holding circuit 301 are smaller than those of the n - channel mos transistor 113 , p - channel mos transistor 114 and n - channel mos transistor 118 , p - channel mos transistor 119 which form the first and second bus drivers 106 and 107 , respectively , ( in other words , the transistor of the inverters 303 has a lower current driving capacity than the output transistors of the drivers ) so that , if the output of the inverters 303 and the level of the bus 101 collide with each other , then the level of the n - channel mos transistor 113 and the p - channel mos transistor 114 or the n - channel mos transistor 118 and the p - channel mos transistor 119 is outputted to the bus 101 . upon failure detection , the test signal 203 is rendered active to put the switch 304 into an on state to hold a value of the bus 101 then . in order to detect a &# 34 ; 0 &# 34 ; stuck failure ( called &# 34 ; sa0 &# 34 ;) of the gate input of the n - channel mos transistor 113 of the first bus driver 106 , a pattern wherein the second output signal 103 is set to &# 34 ; 1 &# 34 ; and the second bus driver enable signal 105 is rendered active so that the p - channel mos transistor 119 of the output stage of the second bus driver 107 is turned on in synchronism with the timing signal 108 to output &# 34 ; 1 &# 34 ; to the bus 101 , and then the first output signal 102 is set to &# 34 ; 0 &# 34 ; and the first bus driver enable signal 104 is rendered active so that the n - channel mos transistor 113 of the first bus driver 106 is turned on in synchronism with the timing signal 108 to output &# 34 ; 0 &# 34 ; to the bus 101 is produced . where this pattern is used , when the n - channel mos transistor 113 is normal , the bus 101 exhibits &# 34 ; 0 &# 34 ; within a period a in fig3 ( refer to a solid line portion of the waveform 101 of fig3 ). on the other hand , if the gate input of the n - channel mos transistor 113 exhibits a &# 34 ; 0 &# 34 ; stuck failure , then the n - channel mos transistor 113 whose gate potential is kept at a high level remains in an off state within the period a of fig3 and the bus 101 remains holding the value &# 34 ; 1 &# 34 ; of the preceding cycle ( refer to a broken line portion of the waveform 101 of fig3 ). a failure is detected thereby . in the present embodiment , since the bus 101 holds a value of a preceding cycle with certainty , a failure can be detected without relying upon the rate ( cycle ) or the layout of the timing signal 108 . further , since the bus holding circuit 301 is connected to the bus 101 only upon testing , the problem of an increase in electric current arising from collision of the level of the bus 101 does not arise in an ordinary operation of the system other than during testing . referring now to fig4 there is shown in block diagram a construction of a bus driver failure detection system according to another preferred embodiment of the present invention . also the bus driver failure detection system shown is an improvement to the conventional bus driver failure detection system described hereinabove with reference to fig7 to 9 and includes first and second and circuits 121 and 122 , first and second bus drivers 106 and 107 which output different values to a bus 101 , and a receiver 109 for latching a value of the bus 101 , similarly to the conventional bus driver failure detection system of fig7 . the bus driver failure detection system of the present embodiment is different from the conventional bus driver failure detection system in that it additionally includes a pull - up / pull - down circuit 201 for pulling up / down the bus 101 . the first bus driver 106 outputs , when a first bus driver enable signal 104 is selected , a value of a first output signal 102 to the bus 101 in synchronism with a timing signal 108 . the second bus driver 107 outputs , when a second bus driver enable signal 105 is selected , a value of a second output signal 103 to the bus 101 in response to the timing signal 108 . the receiver 109 latches a value of the bus 101 in synchronism with the timing signal 108 . the pull - up / pull - down circuit 201 connects a pull - up resistor or a pull - down resistor while a test signal 203 is active . the bus driver failure detection system of the second embodiment of the present invention will be described below with reference to a circuit diagram of fig5 and a time chart of fig6 . fig5 shows an example of a circuit construction of the bus driver failure detection system shown in block diagram in fig4 . the first and second bus drivers 106 and 107 have similar circuit constructions to those of the conventional bus driver failure detection system described hereinabove with reference to fig8 and overlapping description of them is omitted herein to avoid redundancy . the pull - up / pull - down circuit 201 includes a test mode register 202 , a nand circuit 208 to which the test signal 203 and an output of the test mode register 202 are inputted , a nor circuit 209 to which an inverted signal of the test signal 203 and the output of the test mode register 202 are inputted , a p - channel mos transistor 206 acting as a switch with the source thereof connected to a power supply , with the gate thereof connected to the output of the nand circuit 208 and with the drain thereof connected to the bus 101 via a pull - up resistor 204 , and an n - channel mos transistor 207 acting as another switch with the source thereof grounded , with the gate thereof connected to the output of the nor circuit 209 and with the drain thereof connected to the bus 101 via a pull - down resistor 205 . upon failure detection , the test signal 203 is rendered active ( changed over to a high level ) so that one of the switches 206 and 207 is turned on depending upon the value of the test mode register 202 . consequently , the pull - up resistor 204 or the pull - down resistor 205 is connected to the bus 101 . in order to detect a &# 34 ; 0 &# 34 ; stuck failure ( sa0 ) of the gate input of the n - channel mos transistor 113 , a pattern wherein the test mode register 202 is set to &# 34 ; 1 &# 34 ; and the test signal 203 is rendered active to connect the pull - up resistor 204 to the bus 101 , and thereafter , the first output signal 102 is set to &# 34 ; 0 &# 34 ; and the first bus driver enable signal 104 is rendered active so that the n - channel mos transistor 113 is turned on in synchronism with the timing signal 108 to output &# 34 ; 0 &# 34 ; to the bus 101 is produced . where the pattern just described is used , if the n - channel mos transistor 113 is normal , then the bus 101 exhibits &# 34 ; 0 &# 34 ; within a period a of fig6 ( refer to a solid line portion of the waveform 101 of fig6 but if the gate input of the n - channel mos transistor 113 exhibits a &# 34 ; 0 &# 34 ; stuck failure , then the bus 101 now exhibits &# 34 ; 1 &# 34 ; due to the presence of the pull - up resistor 204 ( refer to a broken line portion of the waveform bus 101 of fig6 ). a failure is detected thereby . in the present embodiment , since the pull - up resistor 204 or the pull - down resistor 205 sets the bus 101 to the logic level of &# 34 ; 1 / 0 &# 34 ; with certainty , a failure can be detected without relying upon the rate or the layout of the timing signal 108 . further , since the pull - up / pull - down circuit 201 is connected only upon testing , an increase of an electric current which arises from collision of the bus 101 does not occur other than upon testing . in the conventional bus driver failure detection system shown in fig7 or in the bus driver failure detection system of the first embodiment shown in fig1 where two or more bus drivers for which detection of a failure is performed are involved , in order to detect a failure of the nor circuit 111 ( refer to fig2 ) which provides an output driver control signal for the first bus driver 106 of fig1 it is necessary to first render the nand circuit 117 of the second bus driver 107 active and set the bus 101 to a high level and then render the nor circuit 111 active and place the n - channel mos transistor 113 into an on state . accordingly , in order to detect a failure for a plurality n of p - channel output drivers , it is necessary to drive the bus 101 by 2 × n times . however , with the bus driver failure detection system of the second embodiment of the present invention , detection of a failure for a plurality of n of p - channel output drivers can be realized by a single setting operation of pattern data to the test mode register 202 and n driving operations of the bus 101 . having now fully described the invention , it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth herein .