text: referring now to the figures of the drawing in detail and first , particularly , to fig1 thereof , there is shown a barrier layer 2 composed of aluminum oxide which is deposited by sequential gas phase deposition and is located on one substrate surface 10 of a base substrate 1 , in which first sections 11 and second sections 12 are formed from different materials . the first sections 11 are composed of tungsten , while the second sections 12 are composed of silicon , for example . the base substrate 1 is subjected to a heat treatment in an oxygen environment 9 in a tempering step . even the barrier layer 2 with a layer thickness of 5 nanometers prevents oxides from forming in the base substrate 1 . [ 0060 ] fig2 shows an interconnect structure 7 which runs in the insulating base substrate 1 , for example composed of silicon dioxide , and which is composed of a metal . the barrier layer 2 which is produced according to the invention is disposed between the insulating base substrate 1 and the interconnect 7 , having being deposited by sequential gas phase deposition on the substrate surface 10 which is structured in the form of a relief having a trench which is intended to accommodate the interconnect structure 7 . the barrier layer 2 prevents metal atoms from diffusing out of the interconnect structure 7 in a disadvantageous manner into the insulating base substrate 1 . in addition , the barrier layer 2 is suitable for use as an etching stop layer or etching stop signal layer during the course of etching back the metal that is deposited outside the trench . insulator sections 19 and transistor structures with source / drain sections 13 and channel sections 15 as areas of different doping in a monocrystalline semiconductor substrate , as well as gate electrode sections 18 that are formed in further insulator sections 19 ′, are formed in a base substrate 1 as shown in fig3 . a process layer 3 has contact structures 33 that pass through an insulator structure 32 , in order to connect the source / drain regions 13 to interconnects which are not shown but are disposed in the vertical direction above an intermediate layer dielectric 91 . in order to enlarge the surface area of the contact structures 33 , the contact structures 33 are widen over the second insulator sections 19 ′ and extend over their edges . the conformal barrier layer 2 which is deposited by sequential gas phase deposition covers the base substrate 1 reliably , even if the layer is thin , in the area of the edges of the insulator structures 19 ′, and prevents metal atoms from diffusing out of the contact structures 33 into the base substrate 1 . in the exemplary embodiment illustrated in fig4 extraneous atoms are prevented from diffusing out of a highly conductive section 34 of a gate electrode 6 into a semiconductor section 11 ( which is adjacent to a gate dielectric 14 ) of the gate electrode structure 6 by the barrier layer 2 . the gate electrode structure 6 also has a cap nitride 82 , which covers the highly conductive section 34 , as well as spacer structures 81 , which are composed of a dielectric material , on side walls . the base substrate 1 also has the source / drain sections 13 and channel sections 15 , which are formed as doped regions in monocrystalline silicon . [ 0063 ] fig5 shows a ferroelectric memory cell having a selection transistor and a ferroelectric memory device that is provided in series with the selection transistor . the selection transistor is composed of the source / drain sections 13 , which are formed as doped regions in monocrystalline silicon , and a channel section 15 as well as a gate dielectric section 14 , which is adjacent to the channel section 15 in the vertical direction , and the gate electrode section 18 that is disposed above the gate dielectric section 14 . an insulator section 19 ′, in which contact sections 11 , 11 ′ are incorporated in order to make contact with the source / drain sections 13 , is provided above the selection transistor . a first contact section 11 is intended to make further contact with a bit line bl , and is initially disconnected . a lower electrode section 16 is disposed on the second contact section 11 ′, with a ferroelectric memory section 17 of the ferroelectric memory device being disposed above it . at least one iridium layer is provided as an oxygen barrier layer , with an iridium oxide layer being provided as a diffusion barrier , between the lower electrode section 16 and the second contact structure 11 ′. the ferroelectric memory material , a perovskite such as strontium - bismuth tantalate sbt or lead - zirconium titanate , pzt , is subjected , after being deposited , to an annealing step in an oxygen environment for recrystallization of the perovskite . an upper electrode section 16 ′ is applied to the ferroelectric memory material . an aluminum oxide layer with a thickness of more than 5 nanometers and less than 20 nanometers is provided as the barrier layer 2 on the substrate surface , which is structured in the form of relief by the electrode structure of the memory cell and prevents reduction of the ferroelectric memory material due to hydrogen diffusing in during the hydrogen tempering process at a later time during the processing . a trench 4 is incorporated in the substrate material 1 , as illustrated in fig6 b . the trench 4 is clad with a collar insulator 5 underneath a collar upper edge 50 . a first structure 11 with a monocrystalline crystalline structure is also formed in the semiconductor substrate 1 and is adjacent to the trench 4 above the collar upper edge 50 . the trench 4 is also filled with a polycrystalline material , which forms a first subarea 311 of a second structure or filling structure 31 , which is to be produced in a subsequent process . the object in the following text is to electrically conductively connect to one another the electrically conductive first structure 11 , which corresponds for example to the drain region of a selection transistor of a 1t1c memory cell , and the first subarea 311 of a first electrode , which is formed in the interior of the trench 4 , of a memory capacitor of the 1t1c memory cell , in a very simple manner and with a minimum number of additional process steps . if the trench 4 were to be filled completely in a single operation with doped polycrystalline semiconductor material , this would result in a direct junction above the collar edge 50 between the polycrystalline semiconductor material of the second structure 31 and the monocrystalline semiconductor material of the first structure 11 . during further processing of the semiconductor substrate 1 and during operation of the 1t1c memory cell , migration or grain boundaries of the crystalline structure of the polycrystalline semiconductor material would increasingly continue in the monocrystalline material , disadvantageously changing its characteristics . if the first and second structures were to have different doping , doping atoms would diffuse into the respective other structure during subsequent process steps . thus , as is illustrated in fig6 b , a boundary area layer 21 is conventionally deposited by an lpcvd method . after this , sections of the conformal boundary area layer 21 which are disposed on a surface of the semiconductor substrate 1 are removed by a chemical mechanical polishing ( cmp ) method . sections of the boundary area layer 21 which are disposed on the first subarea 311 cannot be removed easily , so that the boundary area layer 21 is left in these sections . after the deposition of a second subarea 312 of the second structure , that section of the boundary area layer 21 that is formed between the two subareas 311 , 312 reduces the electrical and the chemical quality of the second structure 31 , which is formed from the two subareas 311 , 312 . thus , according to the invention , a conformal initial layer 20 is provided by sequential gas phase deposition . a conformal secondary layer can then be formed from a material whose etching resistance in sections which are horizontal with respect to one surface of the semiconductor substrate 1 can be reduced in comparison to vertical sections by ion implantation . the direction of the ion implantation is indicated schematically by arrows in fig6 c . in consequence , all the horizontal sections of the secondary layer or initial layer 20 can be etched selectively with respect to the vertical sections . when different materials are used , which are preferably removed by ion beam etching ( rie ) in horizontal sections of the boundary area layer , the arrows indicate the direction of the directional etching process . as is illustrated in fig6 d , only the vertical sections of the initial layer 20 , which form the boundary area layer 2 , remain after a subsequent etching step . the second structure 31 is homogenous and has better electrical and mechanical characteristics than a second structure 31 , as illustrated in fig6 a , which is composed of two subareas 311 , 312 on both sides of a boundary area layer 21 disposed between them . the transistor structures are completed on the surface of the semiconductor substrate 1 , and conductive bit line structures and word line structures bl , wl are formed for addressing and data transmission .