text: fig1 shows a first embodiment of a circuit in accordance with the invention . this circuit comprises a first bus line 20 and a second bus line 10 . by way of example , two sub - circuits 22 , 24 are connected to the first bus line 20 via a respective bus interface output 224 , 244 . each of the sub - circuits 22 , 24 comprises two supply inputs 222 , 220 , 242 , 240 which are connected to a first and a second supply terminal , v 0 and v 1 , respectively . the second supply terminal v 1 is connected to the first bus line 20 via a resistive element r1 . by way of example , two sub - circuits 12 , 14 are connected to the second bus line 10 via a respective bus interface output 124 , 144 . each of the sub - circuits 12 , 14 comprises two supply inputs 122 , 120 , 142 , 140 which are connected to a first supply terminal v 0 and a third supply terminal v 2 , respectively . the third supply terminal v 2 is connected to the second bus line 10 via a resistive element r2 . the first and the second bus line 20 , 10 are interconnected via the channel of a transistor 16 , shown as an n - channel fet . the control electrode of this transistor is connected to the third supply terminal v 2 . a diode 18 is shown in parallel to the channel of the transistor 16 . when transistor 16 is a mosfet ( or more generally an igfet ) its backgate ( substrate ) is preferably connected to its source . as a consequence , the backgatedrain drain diode will be in parallel to the channel of transistor 16 . this is expressed by diode 18 . a first supply voltage va = v 1 - v 0 is applied between the first and the second supply terminal , v 0 , v 1 , during operation . between the first and the third supply terminal , v 0 , v 2 , a second supply voltage vb = v 2 - v 0 is applied . the first supply voltage va is higher than the second supply voltage vb ; these voltages are , for example 5 v and 3 . 3 v , respectively (± 10 %). the transistor 16 is , for example an n - channel enhancement field effect transistor whose channel is not conductive when the potential on its gate ( connected to the third supply terminal ) is equal to the potential on its source ( connected to the second bus line 10 ) and lower than the potential on its drain ( connected to the first bus line 20 ). the channel is turned on only if the potential on the source and / or the drain is more than a threshold voltage vt ( for example , 1 . 5 v ) below the potential on the gate . for as long as none of the sub - circuits establishes a conductive path to the first supply terminal , therefore , the potential on the first bus line 20 will be a first supply voltage va higher than the potential on the first supply terminal v 0 whereas the potential on the second bus line 10 will be a second supply voltage vb higher than the potential on the first supply terminal v 0 . the potential on the second bus line 10 , therefore , is lower than the potential on the first bus line 20 ( for example , 1 . 7 v lower in the case of supply voltages of 5 v and 3 . 3 v ) and equal to the potential on the gate of the transistor 16 . when one of the sub - circuits ( for example , 12 ) establishes a conductive path between the second bus line 10 and the first supply terminal v 0 , the potential on the second bus line 10 will be pulled to the potential on the first supply terminal v 0 . as a result , the potential on the source of the transistor 16 will be lower than the potential on the gate by an amount which is sufficient to turn on the channel of the transistor 16 . as a result , the potential on the first bus line 20 is also pulled to the potential on the first supply terminal v 0 . when the sub - circuit 12 establishing the conductive path interrupts said path again , the potential on the bus lines 10 , 20 is pulled up again under the influence of the resistive elements r1 , r2 ( provided of course that none of the other sub - circuits establishes a conductive connection between the bus lines 10 , 20 and the first supply terminal v 0 ). the channel of the transistor 16 then remains turned on for the time being until the potential on the second bus line 10 has increased to such an extent that it is less than one threshold voltage vt below the potential on the gate of the transistor 16 . subsequently , the channel of the transistor 16 is turned off and the potentials on the first and the second bus line 20 , 10 increase further , in an independent manner , until the potential on the first bus line 20 reaches the potential on the second supply terminal v 1 again and the potential on the second bus line 10 reaches the potential on the third supply terminal v 2 again . when one of the sub - circuits ( for example 22 ) establishes a conductive path between the first bus line 20 and the first supply terminal v 0 , a similar effect occurs : the potential on the second bus line 10 is pulled down via the first bus line 20 . when the backgate of transistor is connected to its source , diode 18 will start to conduct , pulling second bus line 10 down . due to the diode 18 the potential on the drain cannot drop very far below the potential on the source . of course , the backgate of transistor 16 could also be kept at its own potential , for example v 0 , in this case the potential on the second bus line 10 will be pulled down when the potential on the first bus line 20 drops sufficiently below the potential on the gate of transistor 16 to make the channel of this transistor 16 conductive . when several sub - circuits simultaneously establish a conductive path between one of the bus lines 10 , 20 and the first supply terminal v 0 , both bus lines 10 , 20 will be pulled to the potential of the first supply terminal v 0 . this potential , therefore , corresponds to a dominant level of the potential on the bus lines 10 , 20 . the potentials of the second and the third supply terminal correspond to the recessive levels of the potential on the first bus line 20 and the second bus line 10 , respectively . the circuit is , therefore , suitable for data communication between the sub - circuits 12 , 14 , 22 , 24 utilizing dominant and recessive states of the bus ( by way of wired logic ). an example of a circuit and a protocol for such communication concerns the i2c bus as described , for example in &# 34 ; ic20 data handbook 1994 &# 34 ;, philips semiconductors , section 4 , which is incorporated herein by way of reference . this section also contains a number of examples of sub - circuits . the i2c bus utilizes a data line sda and a clock line scl , both of which are controlled by means of the dominant / recessive states . fig2 shows a circuit in accordance with the invention for use in conjunction with the i2c bus . herein , the first bus line 20 of fig1 is replaced by two conductive lines sda1 and scl1 , each of which is coupled to the second supply terminal v 1 via a respective resistive element r5 , r6 . the second bus line 10 of fig1 is replaced by two conductive lines sda2 and scl2 , each of which is coupled to the third supply terminal v 2 via a respective resistive element r3 , r4 . the conductive lines sda1 , scl1 are coupled to the conductive lines sda2 , scl2 , respectively , via the channel of a transistor 58 , 59 . the gates of the transistors 58 , 59 are coupled to the third supply terminal v 2 . sub - circuits 54 , 56 are coupled to the conductive lines sda1 , scl1 . sub - circuits 50 , 52 are coupled to the conductive lines sda2 , scl2 . the supply inputs of the sub - circuits 50 , 52 , 54 , 56 have been omitted for the sake of clarity . each of the conductive lines sda1 , sda2 , with the connecting transistor 58 , operates in the same way as described for the bus lines 10 , 20 in fig1 . the same holds for the lines scl1 and scl2 with the connecting transistor 59 . the logic use of these lines is described in the cited &# 34 ; data handbook &# 34 ;. the invention is not restricted to the i2c bus , but can also be used for other buses , for example parallel busses or point to point connections . fig3 shows a further embodiment of the circuit in accordance with the invention . correspondence exists between this figure and fig1 and corresponding components are denoted by corresponding references . the difference in relation to fig1 consists in that a switching circuit 30 is inserted between on the one side the third supply terminal v 2 and on the other side the resistive element r2 , the gate of the transistor 16 and the supply inputs 120 , 140 of the sub - circuits 12 , 14 coupled to the second bus line 10 . one of the sub - circuits ( 22 ) connected to the first bus line 20 has a control output which is connected to a control input of the switching circuit 30 . the switching circuit 30 serves to reduce the supply voltage of the sub - circuits 12 , 14 , connected to the second bus line 10 , without unnecessarily disturbing the data communication . a first embodiment of the switching circuit has two states : a conductive state and a non - conductive state . in the conductive state , the switching circuit 30 passes on the potential on the third supply terminal v 2 . in this conductive state the sub - circuits 12 , 14 and the second bus line 10 operate as described with reference to fig1 . in the non - conductive state , the potential on the gate of the transistor 16 , on the second bus line 10 and on the supply inputs 120 , 140 of the sub - circuits 12 , 14 assumes substantially the level of the potential on the first supply terminal v 0 . the sub - circuits 12 , 14 are then deactivated and the transistor 16 is turned off . as a result , energy is saved , whereas the sub - circuits 22 , 24 which are connected to the first bus line 20 and which are powered as usual can communicate as usual without being disturbed by the second bus line 10 , because the transistor 16 isolates the deactivated part of the circuit from the first bus line 20 . evidently , the collective deactivation of the energy supply for the sub - circuits 12 , 14 and the gate of the transistor 16 and the second bus line 10 can be carried out in a variety of ways ; it is not necessary for these elements to be connected directly to one another as is shown for the sake of simplicity in fig3 . the switching circuit 30 is preferably controlled by a sub - circuit 22 connected to the first bus line 20 . thus , the second bus line can be switched on and off under the control of the first bus line 20 . switching on and off of the switching circuit 30 , however , can also take place by means of a central control unit ( not shown ) or a manually operated switch . a further embodiment of the switching circuit 30 is arranged to apply , in dependence on a control signal , a reduced potential level ( between the level of the potential on the third supply terminal v 2 and the first supply terminal v 0 ) in an intermediate state to the gate of the transistor 16 , to the second bus line 10 and to the supply inputs 120 , 140 of the sub - circuits 12 , 14 . the sub - circuits 12 , 14 can thus be switched to a low - energy mode ( possibly a slower mode ) and still communicate with the other sub - circuits 22 , 24 via the bus lines 10 , 20 . fig4 shows a further embodiment of the circuit in accordance with the invention . the figure is similar to fig3 and corresponding components are denoted by corresponding references . a third bus line 44 is inserted between the first and the second bus line 20 , 10 . the third bus line 44 is connected to the first bus line 20 via the channel of a transistor 46 . a diode 48 is connected parallel to said channel . the third bus line 44 is connected to the second bus line 10 via the channel of the transistor 16 . the third bus line 44 is coupled to a fourth supply terminal v 3 via a resistive element r3 . the gate of the transistor 46 is connected to the supply inputs 220 , 240 of the sub - circuits 22 , 24 coupled to the first bus line 20 . this gate is also connected , via the resistive element r1 , to the first bus line 20 . the gate is coupled to the second supply terminal v 1 via a first switching element 42 . the sub - circuits 12 , 14 connected to the second bus line 10 can be driven to a low ( no ) energy consumption state and / or the sub - circuits 22 , 24 connected to the first bus line 20 can be driven to a low ( no ) energy consumption state . the sub - circuits 12 , 14 , 22 , 24 which receive energy can communicate with one another . a relationship is thus established between the levels of the potential on the first and the second bus line 20 , 10 on the one side and the level of the potential on the third bus line 44 on the other side . this relationship is analogous to the relationship described with reference to fig1 and existing between potential levels on the second bus line 10 on the one side and the first bus line 20 on the other side . furthermore , via connections which are analogous to the connection via the transistor 16 , an arbitrary number of further bus lines can be connected to the third bus line . each bus line can then be switched on and off , together with the sub - circuits connected thereto , independently of the other bus lines . furthermore , further bus lines can be coupled to the first or the second bus line in an analogous manner . even though the invention has been described on the basis of an nmos field effect transistor 16 , evidently other types of transistors or other switching elements can be used instead without departing from the scope of the invention . it suffices that the switching element isolates when the bus is in the recessive state and that it is conductive when the circuit is in the dominant state . for the resistive elements use can be made of , for example resistors , but other means ensuring that the potential on the bus lines assumes a predetermined level in the absence of dominant driving are also suitable , for example a load transistor .