text: in the following detailed description of the invention reference is made to the accompanying drawings which form a part hereof , and in which are shown , by way of illustration , specific embodiments in which the invention may be practiced . in the drawings , like numerals describe substantially similar components throughout the several views . these embodiments are described in sufficient detail to enable those skilled in the art to practice the invention . other embodiments may be utilized , and structural , logical , and electrical changes may be made , without departing from the scope of the present invention . the following detailed description is , therefore , not to be taken in a limiting sense , and the scope of the invention should be determined with reference to the appended claims , along with the full scope of equivalents to which such claims are entitled . relative direction terms as used in this description are defined with reference to the conventional horizontal , large plane or surface of a board , such as a motherboard , where electrical components have typically been attached , regardless of the orientation of the board . likewise , when referring to components that are adapted for use on circuit boards , terms such as “ top surface ” or “ bottom surface ” are defined as surfaces of components that are substantially parallel to the conventional horizontal , large plane or surface of the board . the term “ vertical ” refers to a direction perpendicular to the horizontal as defined above . an example of an information handling system is included to show an example of a higher level device application for the present invention . in one embodiment , a capacitor according to one embodiment of the invention is included in an information handling system as described below . in one embodiment , the capacitor is used in a voltage regulator circuit . fig1 is a block diagram of an information handling system 1 incorporating at least one capacitor in accordance with at least one embodiment of the invention . information handling system 1 is merely one example of an electronic system in which the present invention can be used . in this example , information handling system 1 comprises a data processing system that includes a system bus 2 to couple the various components of the system . system bus 2 provides communications links among the various components of the information handling system 1 and can be implemented as a single bus , as a combination of busses , or in any other suitable manner . electronic assembly 4 is coupled to system bus 2 . electronic assembly 4 can include any circuit or combination of circuits . in one embodiment , electronic assembly 4 includes a processor 6 which can be of any type . as used herein , “ processor ” means any type of computational circuit , such as but not limited to a microprocessor , a microcontroller , a complex instruction set computing ( cisc ) microprocessor , a reduced instruction set computing ( risc ) microprocessor , a very long instruction word ( vliw ) microprocessor , a graphics processor , a digital signal processor ( dsp ), or any other type of processor or processing circuit . other types of circuits that can be included in electronic assembly 4 are a custom circuit , an application - specific integrated circuit ( asic ), or the like , such as , for example , one or more circuits ( such as a communications circuit 7 ) for use in wireless devices like cellular telephones , pagers , portable computers , two - way radios , and similar electronic systems . the ic can perform any other type of function . in one embodiment , one or more circuits and components are located on a board such as a motherboard ( not shown ). information handling system 1 can also include an external memory 10 , which in turn can include one or more memory elements suitable to the particular application , such as a main memory 12 in the form of random access memory ( ram ), one or more hard drives 14 , and / or one or more drives that handle removable media 16 such as floppy diskettes , compact disks ( cd ), digital video disk ( dvd ), and the like . examples of main memory 12 include dynamic random access memory ( dram ), synchronous dynamic random access memory ( sdram ), double data rate synchronous dynamic random access memory ( ddr sdram ), rambus dynamic random access memory ( rdram ), flash memory , static random access memory ( sram ), etc . information handling system 1 can also include a display device 8 , one or more speakers 9 , and a keyboard and / or controller 20 , which can include a mouse , trackball , game controller , voice - recognition device , or any other device that permits a system user to input information into and receive information from the information handling system 1 . fig2 a shows a capacitor 200 . the capacitor 200 includes a plate assembly 210 having a number of plates 211 that are each joined at an end 212 . in one embodiment , the number of plates 211 are joined using a weld . other joining methods that provide a conductive joint , such as soldering , or conductive adhesives , etc . are within the scope of the invention . the capacitor 200 also includes a first terminal 220 and a second terminal 222 . in one embodiment , the first terminal is coupled to a first polarity connection of the plate assembly 210 . in one embodiment , the second terminal 222 is coupled to a second polarity connection of the plate assembly 210 . in one embodiment , the first polarity connection is an anode connection and the second polarity connection is a cathode connection . the capacitor 200 further includes a capacitor package 230 . in one embodiment , the capacitor package 230 includes a molded or cast polymer material . suitable materials include , but are not limited to , epoxies , other thermoset materials , etc . fig2 b shows a diagram of one embodiment of an individual plate such as plate 211 from fig2 a . a conductive plate 240 is shown in fig2 b . in one embodiment , the conductive plate 240 includes aluminum metal . in one embodiment , the conductive plate 240 is an aluminum foil . in one embodiment , the conductive plate is etched or patterned on at least a portion of its surface to increase surface area . a dielectric material 242 is shown over the conductive plate . in one embodiment , the dielectric material 242 includes a metal oxide layer . in one embodiment , the dielectric material 242 is formed by oxidizing the conductive plate 240 . in one embodiment , the dielectric material 242 includes aluminum oxide ( al 2 o 3 ). a conductive polymer layer 244 is included over the dielectric material 242 . in one embodiment , the conductive polymer 244 is formed by introducing a monomer layer to the dielectric material 242 and subsequently polymerizing the monomer layer . a conducting layer 246 is included over the conductive polymer 244 in one embodiment . in one embodiment , the conducting layer 246 includes a carbon layer . also shown in fig2 b is an outer conducting layer 248 . in one embodiment , the outer conducting layer 248 includes a good conductor such as a metal . in one embodiment , the outer conducting layer 248 includes a silver paint layer . fig3 a shows a first plate assembly 300 and a second plate assembly 302 according to an embodiment of the invention . a number of individual plates 310 are shown , with a connecting structure 320 . the number of plates 310 each include a first polar connection 312 and a second polar connection 314 . the two polar connections 312 and 314 are separated by a dielectric layer similar to the configuration described above , to form a basic capacitive structure for each individual plate 310 . in one embodiment , the first polar connection 312 is an anode connection , and the anode connections of a plurality of plates 310 are coupled together by the connecting structure 320 . fig3 b shows a capacitor 350 . the capacitor 350 incorporates embodiments of the first plate assembly 300 and the second plate assembly 302 from fig3 a . a first terminal 352 is shown coupled to the connecting structure 320 . a second terminal 354 is shown coupled to the second plate assembly 302 at the second polar connection 314 through conductor 356 . one of ordinary skill in the art having the benefit of the present disclosure will recognize that although the second terminal 354 is shown coupled to a distal end of an individual plate 310 , coupling at the distal end of the plate 310 is not required . as shown in figures and discussed above , in one embodiment , substantially all of an outer surface of the plates 310 defines one plate of a capacitor . several locations are therefore possible for coupling the second terminal to the plates 310 . likewise , a third terminal 358 is shown in fig3 b . in one embodiment , the third terminal 358 is coupled to a second polar connection 314 of the first plate assembly 300 through conductor 360 . a capacitor package 370 is shown containing the components of the capacitor 350 . as shown in fig3 b , multiple plate assemblies are coupled to the common first terminal 354 at their respective first polar connections , while each individual plate assembly is coupled to a separate terminal at their second polar connections . this configuration has been found to provide high capacitance capability for a capacitor , while reducing esl and esr for the capacitor . another embodiment of a capacitor 400 is shown in fig4 . fig4 shows a first plate assembly 410 and a second plate assembly 420 . the first plate assembly 410 includes a number of individual plates 412 similar to plates described above . in one embodiment , the plates 412 each include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . likewise , the second plate assembly 420 includes a number of individual plates 422 similar to plates described above . in one embodiment , the plates 422 each include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . the first plate assembly 410 and the second plate assembly 420 are coupled together in a fan - like arrangement at location 424 . in one embodiment , the first plate assembly 410 and the second plate assembly 420 are welded together , although other methods of electrically joining the first plate assembly 410 and the second plate assembly 420 are within the scope of the invention . in one embodiment , the first plate assembly 410 and the second plate assembly 420 are joined together at an anode connection and further coupled to a first terminal 434 . in one embodiment , the first plate assembly 410 is coupled to a second terminal 430 at a cathode connection of the first plate assembly 410 . in one embodiment , the second plate assembly 420 is coupled to a third terminal 432 at a cathode connection of the second plate assembly 420 . although two plate assemblies are shown in fig4 , the invention is not so limited . in one embodiment , three or more plate assemblies are included in a capacitor package 440 . further , in one embodiment as shown in fig4 , individual plates from plate assemblies vary in length to fill a space of the capacitor package 440 and to increase surface area of plates within the capacitor package 440 . in one embodiment , the plates are all the same length . similar to embodiments shown above , in fig4 , multiple plate assemblies are coupled to the common first terminal 354 at their respective first polar connections , while each individual plate assembly is coupled to a separate terminal at their second polar connections . this configuration has been found to provide high capacitance capability for a capacitor , while reducing esl and esr for the capacitor . the fan like arrangement shown in fig4 in particular , has been shown to reduce esl and esr for the capacitor 400 . fig5 a – 5d show a number of terminal configurations that can be used in embodiments of capacitors in the present disclosure . in one embodiment , at least one terminal includes a surface mount terminal designed for soldering or similar surface mount technology attachment to a circuit board . in one embodiment , all terminals are surface mount terminals . fig5 a shows a bottom of a capacitor 500 . a capacitor package 510 is shown housing plate assemblies as described in embodiments above . a first terminal 512 , a second terminal 514 and a third terminal 516 are shown . in one embodiment , the first terminal 512 is coupled to multiple plate assemblies . in one embodiment , the second terminal 514 is coupled to one of a number of multiple plate assemblies . in one embodiment , the third terminal 516 is coupled to one of a number of multiple plate assemblies . in one embodiment , the first terminal 512 is coupled to anodes from multiple plate assemblies . in one embodiment , the second terminal 514 and the third terminal 516 are coupled to cathodes from multiple plate assemblies . fig5 b shows a bottom of a capacitor 502 . a capacitor package 520 is shown housing plate assemblies as described in embodiments above . a first terminal 522 , a second terminal 524 , a third terminal 526 , a fourth terminal 528 , a fifth terminal 530 and a sixth terminal 532 are shown . in one embodiment , the first terminal 522 and the second terminal 524 are each coupled to multiple plate assemblies . in one embodiment , the third terminal 526 and the fourth terminal 528 are coupled to one of a number of multiple plate assemblies . in one embodiment , the fifth terminal 530 and the sixth terminal 532 are coupled to one of a number of multiple plate assemblies . in one embodiment , the first terminal 522 and the second terminal 524 are coupled to anodes from multiple plate assemblies . in one embodiment , the third terminal 526 , the fourth terminal 528 , the fifth terminal 530 and the sixth terminal 532 are coupled to cathodes from multiple plate assemblies . fig5 c shows a bottom of a capacitor 504 . a capacitor package 540 is shown housing plate assemblies as described in embodiments above . a first terminal 542 , a second terminal 544 and a third terminal 546 are shown . in one embodiment , the first terminal 542 is coupled to multiple plate assemblies . in one embodiment , the second terminal 544 is coupled to one of a number of multiple plate assemblies . in one embodiment , the third terminal 546 is coupled to one of a number of multiple plate assemblies . in one embodiment , the first terminal 542 is coupled to anodes from multiple plate assemblies . in one embodiment , the second terminal 544 and the third terminal 546 are coupled to cathodes from multiple plate assemblies . as shown in fig5 c , in one embodiment , the terminals span a width of the capacitor package 540 . fig5 d shows a bottom of a capacitor 506 . a capacitor package 550 is shown housing plate assemblies as described in embodiments above . a first terminal 552 , a second terminal 554 , a third terminal 556 , a fourth terminal 558 , a fifth terminal 560 and a sixth terminal 562 are shown . in one embodiment , the first terminal 552 and the second terminal 554 are each coupled to multiple plate assemblies . in one embodiment , the third terminal 556 and the fourth terminal 558 are coupled to one of a number of multiple plate assemblies . in one embodiment , the fifth terminal 560 and the sixth terminal 562 are coupled to one of a number of multiple plate assemblies . in one embodiment , the first terminal 552 and the second terminal 554 are coupled to anodes from multiple plate assemblies . in one embodiment , the third terminal 556 , the fourth terminal 558 , the fifth terminal 560 and the sixth terminal 562 are coupled to cathodes from multiple plate assemblies . similar to embodiments shown above , in fig5 a – 5d , multiple plate assemblies are coupled to at least one common terminal at first polar connections , while each individual plate assembly is coupled to at least one separate terminal at second polar connections . this configuration has been found to provide high capacitance capability for a capacitor , while reducing esl and esr for the capacitor . fig6 a – 6d show a number of configurations of plate assemblies for use in capacitors in embodiments of the present disclosures . fig6 a shows a first fan - like plate assembly 610 , a second fan - like plate assembly 612 , a third fan - like plate assembly 614 , and a fourth fan - like plate assembly 616 . similar to embodiments described above , the plate assemblies include individual plates 620 . in one embodiment , the individual plates 620 include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . in one embodiment , individual plates in each of the plate assemblies are coupled together at an end 622 . in one embodiment , the end 622 couples an anode of the plates 620 . plate assemblies as shown in fig6 a are coupled together into a single capacitor in configurations described below . in one embodiment , the plate assemblies form a cylinder shape as shown in fig6 e . fig6 b shows first fan - like plate assembly 632 and a second fan - like plate assembly 634 . in contrast to fig6 a , the fan - like plate assemblies in fig6 b are each half cylinders where the fan - like plate assemblies in fig6 a are quarter cylinders . similar to embodiments described above , the plate assemblies include individual plates 630 . in one embodiment , the individual plates 630 include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . in one embodiment , individual plates in each of the plate assemblies are coupled together at ends 633 and 637 respectively . in one embodiment , the ends 633 and 637 couple anodes of the plates 620 in each plate assembly 632 and 634 . fig6 c shows another embodiment of a plate assembly 640 according to an embodiment of the invention . the plate assembly 640 includes individual plates 642 . in one embodiment , the individual plates 642 include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . in one embodiment , individual plates in each of the plate assemblies are coupled together at an end 644 . in one embodiment , the end 644 couples an anode of the plates 642 . in one embodiment , a single plate assembly 640 forms a cylinder shape . fig6 d shows a capacitor 650 incorporating embodiments of multiple plate assemblies or single plate assemblies as described in embodiments above . a capacitor package 654 is shown housing the plate assemblies to form a cylindrical capacitor 650 . fig6 e further shows the capacitor 650 with cylindrical capacitor package 654 . fan like plate assemblies as described above have been shown to provide high capacitance while reducing esl and esr . multiple plate assemblies used in a single capacitor package are useful to provide high capacitance using smaller fan - like plate assemblies that are more manufacturable than plate assemblies with large numbers of individual plates . further plate assemblies mounted in a vertical fashion with respect to a circuit board have been found to provide high capacitance , within a small volume . fig7 a – 7d show embodiments of capacitors using plate assemblies as described above . fig7 a shows a capacitor 700 , including a plate assembly 702 housed in a capacitor package 704 . as shown in fig7 a the capacitor package 704 need not be cylindrical in shape to house a fan - like plate assembly . in one embodiment , the capacitor package 704 includes a rectangular shape . further , individual plates of a plate assembly 702 need not be the same length . in one embodiment , the individual plates of the plate assembly 702 are dimensioned with lengths that fill the available volume of the capacitor package 704 . configurations such as this increase capacitance within a smaller volume . fig7 b shows a capacitor 710 including a number of plate assemblies 712 . each plate assembly 712 is housed within a capacitor package 720 similar to embodiments described above . in one embodiment , the capacitor package 720 includes a cylindrical capacitor package . in one embodiment , individual plate assemblies 712 are electrically connected using conductors 714 such as wiring , metal traces , etc . a number of first polarity terminals 718 are shown on each of the plate assemblies 712 . likewise , a number of second polarity terminals 716 are shown on each of the plate assemblies 712 . in one embodiment , the first polarity terminals are anodes and the second polarity terminals are cathodes , although the invention is not so limited . in one embodiment , the terminals include at least one surface mount terminal . in one embodiment , all terminals are surface mount terminals . the use of multiple terminals in configurations such as fig7 b have been shown to reduce esl and esr while maintaining high capacitance . fig7 c shows a capacitor 730 including a number of plate assemblies 732 . each plate assembly 732 is housed within a capacitor package 738 similar to embodiments described above . in one embodiment , the capacitor package 738 includes a cylindrical capacitor package . in one embodiment , as shown in fig7 c , the individual plate assemblies are not electrically connected to each other in the capacitor package 738 . this configuration allows the individual plate assemblies to be used individually if desired . this configuration also allows a reduced complexity in manufacturing the capacitor 730 . in one embodiment , the plate assemblies 732 are electrically coupled together using traces or other conducting structures on a circuit board . similar to fig7 b , a number of first polarity terminals 736 are shown on each of the plate assemblies 732 . likewise , a number of second polarity terminals 734 are shown on each of the plate assemblies 732 . in one embodiment , the first polarity terminals are anodes and the second polarity terminals are cathodes , although the invention is not so limited . fig7 d shows a capacitor 740 including a capacitor package 746 and a number of terminals . a first terminal 744 is shown in a center of the capacitor 740 and a number of peripheral terminals 742 are shown . in one embodiment , multiple plate assemblies are coupled to the first terminal 744 at a first polarity connection such as an anode . in one embodiment , each plate assembly is coupled to a selected peripheral terminal 742 at a second polarity connection such as a cathode . fig8 a shows a capacitor 800 including a number of plate assemblies 802 housed within a single capacitor package 804 . in one embodiment , the plate assemblies include a number of plates as described in embodiments above . in one embodiment , the individual plates include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . a number of first polarity terminals 810 are shown alternating with a number of second polarity terminals 820 . in one embodiment , the first polarity terminals 810 are anodes and the second polarity terminals 820 are cathodes . in one embodiment , at least one plate assembly is oriented with the plates extending vertically with respect to a top of the capacitor package 804 . it has been shown that multiple plate assemblies mounted in this configuration with multiple terminals provides high capacitance with reduced esl and esr . in one embodiment , the capacitor package 804 and the arrangement of terminals in the capacitor 800 correspond to existing capacitor form factors for other varieties of capacitors . in one embodiment , the capacitor configuration corresponds to a form factor for a multi layer ceramic capacitor ( mlcc ). by designing to an existing form factor , it is easy to replace existing capacitor designs with improved capacitors without significantly changing other manufacturing processes . fig8 b shows a capacitor 830 including a number of plate assemblies 832 housed within a single capacitor package 834 . in one embodiment , the plate assemblies include a number of plates as described in embodiments above . in one embodiment , the individual plates include an aluminum foil with a metal oxide dielectric layer and a conductive polymer layer over the dielectric layer . a number of first polarity terminals 840 are shown alternating with a number of second polarity terminals 850 . in one embodiment , the first polarity terminals 840 are anodes and the second polarity terminals 850 are cathodes . in one embodiment , at least one plate assembly is oriented with the plates extending vertically with respect to a top of the capacitor package 834 . a number of electrically interconnecting structures 836 are included in the capacitor 830 to couple one pole such as a cathode of individual plate assemblies 832 . this configuration has been shown to provide high capacitance while reducing esl and esr . while a number of advantages of embodiments of the invention are described , the above lists are not intended to be exhaustive . although specific embodiments have been illustrated and described herein , it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown . this application is intended to cover any adaptations or variations of embodiments described above . it is to be understood that the above description is intended to be illustrative , and not restrictive . combinations of the above embodiments , and other embodiments will be apparent to those of skill in the art upon reviewing the above description . the scope of the invention includes any other applications in which the above structures and fabrication methods are used . the scope of the invention should be determined with reference to the appended claims , along with the full scope of equivalents to which such claims are entitled .