text: reference will now be made to the exemplary embodiments illustrated in the drawings , and specific language will be used herein to describe the same . it will nevertheless be understood that no limitation of the scope of the invention is thereby intended . alterations and further modifications of the inventive features illustrated herein , and additional applications of the principles of the inventions as illustrated herein , which would occur to one skilled in the relevant art and having possession of this disclosure , are to be considered within the scope of the invention . fig1 shows an exemplary ultra - high density data storage system 100 having electron emitters 102 and 104 and a phase - change data storage medium 106 . electron emitter 102 and 104 are mounted above the storage medium 106 , that has a number of storage areas , such as 108 , that are impacted by electron beams from the emitters . micromovers , based on micro - electromechanical systems ( mems ) technology , cause relative movement between the phase - change medium 106 and the electron emitters 102 . micromover 110 is connected to the storage medium 106 and moves it relative to the emitters 102 , 104 , so that each emitter can impact a number of different data storage areas . fig2 is a top view of the cross section a - a in fig1 , showing the micro - mover 110 fabricated to scan the medium 106 in the x and y directions . the storage medium 106 is supported two sets of thin - walled micro - fabricated flexible beams or springs 112 and 114 which flex to allow the medium 106 to move in the x direction with respect to a supporting frame 122 . a second set of springs 116 and 118 are connected between the supporting frame 122 and the outer casing 120 and flex to allow the medium 106 and frame 122 to move in the y direction with respect to the casing 120 . the field emitters scan over the medium , or the medium scans over the field emitters in the x - y directions by electrostatic , electromagnetic or piezoelectric means known in the art . fig3 shows an exemplary diode structure 140 comprising the phase - change layer 106 described above and a second diode layer 142 forming a diode junction 144 at the interface of the two layers . typically , phase - change layer 106 and second diode layer 142 have different electrical characteristics , to encourage the movement of carriers across the junction . for example , phase change layer 106 may be n - type and second diode layer 142 may be p - type . doping may be used to change or enhance the electrical characteristics of each layer . an external circuit 146 is connected to the diode to impress a voltage across the junction so as to create a bias , either in a reverse direction or in a forward direction , depending on the needs of the circuit . an output 148 is generated by circuit 146 and is representative of the magnitude of carrier flow across junction 144 . reading or detecting is carried out by directing a narrow beam of electrons 105 onto the surface of phase change layer 106 at data storage area 108 . the incident electrons excite electron - hole pairs 107 near the surface of the storage area 108 . the diode 140 is reversed - biased by external circuit 146 so that the minority carriers that are generated by the incident electrons drift toward the diode junction 144 . minority carriers that do not recombine with majority carriers before reaching the junction are swept across the junction , causing a current to flow in the external biasing circuit 146 . writing onto diode 140 is accomplished by increasing the power density of the electron beam 105 enough to locally alter some property of the diode at storage area 108 , such as collection efficiency of minority carriers . in fig4 , a schematic side view of a diode configuration 200 in accordance with one embodiment of the present invention is shown . a phase - change layer 202 is composed of indium and selenium in an indium selenide ( inse ) compound which can be reversibly changed from an amorphous to a crystalline state by heating and cooling the inse compound at suitable rates . this state change is useful for data storage , since the amorphous state is less conductive that the crystalline state . the inse compound may be any inse - type material . as used herein the terms “ inse compound ,” “ inse - type material ” and “ inse layer ” mean any compound of inse , in 2 se 3 or a material in the group having the formula in x se 1 - x . when the inse layer 202 is changed from the crystalline state to the amorphous state at the storage area 212 , the electrical properties of the inse layer significantly change . accordingly , the number of carriers swept across the diode junction will be significantly different in the amorphous state than when inse is in a crystalline state . in fig4 , the second diode layer 204 is disposed below the phase - change layer 202 to form a diode junction 206 . since polycrystalline inse - type materials are naturally n - type , the second diode layer 204 may be a p - type semiconductor layer or capable of being p - doped . the second diode layer 204 may be made of a material of copper indium selenide ( cuinse ), also known as cis . the terms “ cis ,” “ cis compound ” or “ cis material ” refer to a material having any ratio of copper , indium , and selenium , such as cuinse 2 , including but not limited to cis doped with gallium ( cigs ). the term “ cigs ” refers to cuinse doped with gallium to form various stoichiometric materials of copper indium gallium selenide including but not limited to ( cu ( in , ga ) se 2 ) and cu ( in 1 - x ga x ) se 2 . cis materials are desirable for memory diode materials for a number of reasons . cis compounds are similar to inse - type materials , differing in the additional cu element and a change in crystalline structure . although the structures of these two compounds are different , the diode interface between layers of the two compounds is effective . also , cis can be readily doped with a p - type dopant which is required to work with inse . further , the cis layer can be formed in the same vacuum system as an inse layer , enabling the formation of a clean high quality interface between the two layers . this diode structure also reduces processing costs , since the time required for an additional fabrication stage is eliminated . in addition , cis and cigs materials tend to have relatively high melting temperatures , compared to inse - type materials , so heat applied to the phase - change layer should not affect the cis or cigs layer . finally , cis materials tend to have good diode junction characteristics . the diode configuration 200 shown in fig4 may be used as a detection device in various data storage detection devices , such as photovoltaic devices , cathodovoltaic devices , photoluminescent devices and cathodoluminescent devices , all described above . fig5 discloses a method of fabrication 300 of the diode structure shown in fig4 . fabrication of the diode structure 200 starts at step 310 with the selection of a substrate layer 210 from silicon or various silicon oxide materials . in the present embodiment , substrate 210 is preferably of a material that can be doped with sodium , which promotes the growth of the subsequent layers . such material includes , but is not limited to , silicon , silicon oxide , soda lime glass , and other semiconductor materials . at step 312 , an electrical potential field layer , or back contact , 208 is fabricated on the surface of substrate 210 . field layer 208 is fabricated from molybdenum ( mo ) using a sputtering technique , known to those skilled in the art , to a thickness of 0 . 5 - 2 . 0 microns , with 1 micron being used in this embodiment . other suitable conductive materials are indium , titanium nitride , platinum , gold , zinc oxide , indium tin oxide and / or nickel . next , at step 314 , second diode layer 204 is fabricated on field layer 208 . other suitable phase - change materials may be used . in this embodiment , diode layer 204 is preferably fabricated with a cis compound and is doped with a p - type dopant . second diode layer 204 has a thickness range of about 1 to 6 microns with 3 . 5 microns being used in this embodiment , and is applied by elemental evaporation in a vacuum . other methods of fabrication can include sputtering or electrodeposition using an electrolyte of k 2 so 4 , cuso 4 , in 2 s ( so 4 ) 3 , and / or seo 2 . as previously mentioned , second diode layer 204 may also be doped with gallium to form cuingase 2 or other cigs compounds . at step 316 , after application of the second diode layer 204 , the first diode layer 202 is fabricated on layer 208 . in the present embodiment , first diode layer 202 is fabricated with in 2 se 3 , being a natural n - type material . first layer 202 has a thickness range of 50 - 200 nm , with 100 nm being used in this embodiment . first layer 202 may be applied by elemental evaporation in vacuum , which may be the same vacuum used to apply the second layer 204 . in an alternative embodiment , fabrication of first layer 202 can be performed with electrodeposition using an electrolyte . in an embodiment in which layer 204 is a cigs material , layer 204 may be grown using a three - stage co - evaporation process . first , an ( inga ) 2 se 3 layer is deposited at 400 ° c ., followed by evaporation of cu and se at 550 ° c . to make the film slightly cu - rich . the composition is restored to slightly cu - poor by the addition of ( inga ) 2 se 3 again . next , the inse layer is thermally evaporated from elemental sources onto a heated surface . inse is a natural n - type material , so no doping is required . further , cu can diffuse from the second diode layer of cuinse into the inse top layer to enhance the n - type doping . at step 318 , electric grid contacts 214 are fabricated on the surface of layer 202 because the first layer of inse 202 has a low electrical conductivity . contacts 214 are made of a conductive material the same as or similar to field layer 208 . for example , grid contacts 214 can be made of mo at a thickness ranging from 0 . 5 to 5 microns , with 1 micron used in this embodiment . alternately , the grids may be made of other suitable materials , such as au or in . the material may be sputter - deposited or made by any other suitable fabrication techniques known to those skilled in the art . grid contacts 214 and field layer 208 may be the connection points for applying a voltage source circuit to the diode 200 during a read operation . testing has been performed on sample diodes as embodied in the present invention . the tests have included measuring the i - v characteristics of the diodes , performing quantum efficiency ( optical ), and performing electron beam induced current ( ebic ) measurements , which simulate a “ read ” mode for data storage . fig6 contains bar graphs showing ebic gain as a function of emitter beam voltage for diodes having in 2 se 3 as the top layer with in or au contacts and si or cigs as a bottom layer . the ebic gain is diode current output divided by electron beam current . in the first two samples , in 2 se 3 was applied after the substrate was exposed to air . the second two samples ( in situ ) were fabricated by depositing both layers in a vacuum without exposure to air during the process . as shown in the fig6 graph , the ebic variations are not linear with variations in emitter beam energy , because more energetic electron beams result in both more electron - hole pairs and deeper penetration . although 5 kv beams may be used , beams of 1 kv or less may be utilized in most applications . beam current may vary from 0 . 5 na to as high as 200 na , with about 20 na being used in some applications . as seen from the graph , ebic gain is considerably better with cigs rather than si as a bottom diode layer . also , the gain is substantially higher if the diode is fabricated in a vacuum . fig7 shows the current - voltage characteristics for three samples of the first diode listed in fig6 . as shown in fig7 , the applied voltage causes essentially zero current until it reaches about 200 mv , after which there is a sharp increase in current . the open circuit voltage is 5 mv and the short circuit current density is about 2 to 3 ma cm 2 . it is to be understood that the above - referenced arrangements are illustrative of the application for the principles of the present invention . numerous modifications and alternative arrangements can be devised without departing from the spirit and scope of the present invention while the present invention has been shown in the drawings and described above in connection with the exemplary embodiments ( s ) of the invention . it will be apparent to those of ordinary skill in the art that numerous modifications can be made without departing from the principles and concepts of the invention as set forth in the claims .