text: the following detailed description will present a driving apparatus of an oled panel , and a driving method thereof according to a preferred embodiment of the invention in reference to the accompanying drawings . [ 0041 ] fig5 is a block diagram of an oled panel driving apparatus of the present invention . as shown in fig5 the oled panel 10 is composed of a plurality of common anode lines d 1 , . . . , dm and a plurality of common cathode lines s 1 , . . . , sn , which are aligned in a matrix shape , and an oled 12 is located in each of the intersecting points so as to form a pixel . a data driving circuit 20 ′ is connected to the common anode lines d 1 , . . . , dm , and a scan driving circuit 30 ′ is connected to the common cathode lines s 1 , . . . , sn . the scan driving circuit 30 ′ includes a scan output unit 32 ′, which selectively connects the common cathode lines s 1 , . . . , sn to a high voltage terminal . ( for example , 15v ) v h , a high impedance terminal hiz , and a grounding earth gnd in predetermined patterns in accordance with the control of a control unit ( not shown ). the high voltage terminal v h is provided to prevent the oled 12 from being degraded , which is caused from that the both ends of the oled 12 is continuously maintained in the same polarity , by inverting the polarity of a parasitic capacitor , that is , the voltage polarity of the both ends of the oled 12 . its operation will be described herein after . [ 0043 ] fig6 is a block diagram of a scan output unit relative to one common cathode line of fig5 . as shown in fig6 each scan output unit 32 ′ includes an inverter gate inv , its input end being connected to a high impedance control signal end c hiz , a nor gate , its input end being connected to a scan control signal end c scan , and its the other input end being connected to a high impedance control signal end c hiz , nand gate , its one input end being connected to a scan control signal end c scan , and its the other end being connected to the output end of an inverter gate inv , a first level shift ls 1 being connected to the output end of the nand gate nand to convert its logic level vcc to a high voltage level v h , a second level shift ls 2 being connected to the output end of the nor gate nor to convert its logic level vcc to a high voltage level v h , pmosfet pmt 1 , a gate being connected to the first level shift ls 1 , and a source being connected to the high voltage terminal v h , and nmosfet nmt 1 , a gate connected to the second level shift ls 2 , and a drain being connected to the drain of the pmosfet pmt 1 , and a source grounded , and the common cathode line sy is connected to the drains of pmosfet pmt 1 and nmosfet nmt 1 . in the structure described as above , if a logic signal “ 0 ” is output from an outer control unit ( not shown ) to the scan control signal end c scan and the high impedance control signal end c hiz respectively , a logic signal “ 1 ” is output from the nand gate nand and nor gate nor respectively , and the logic signal “ 1 ” is converted into a high voltage level v h in the first level shift ls 1 , and the second level shift ls 2 , and so , the common cathode line sy is connected to a grounding earth gnd with the pmosfet pmt 1 being “ off ”, but the nmosfet nmt 1 being on if a logic signal “ 1 ” is output to the scan control signal end c scan , and a logic signal “ 0 ” is output to the high impedance control signal end c hiz respectively , a logic signal “ 0 ” is output from the nand gate nand and nor gate nor respectively , and the logic signal “ 0 ” is converted into a low voltage level in the first level shift ls 1 and the second level shift ls 2 , and so , the common cathode line s y is connected to a high voltage terminal v h with the pmosfet pmt 1 being “ on ”, but the nmosfet nmt 1 being “ off ”. in the meantime , if a logic signal “ 1 ” is output to the high impedance control signal end c hiz , a logic signal “ 1 ” is output from the nand gate nand regardless the level of the logic signal input to the scan control signal end c scan , and a logic signal “ 0 ” is output from the nor gate nor . accordingly , the pmosfet pmt 1 and the nmosfet nmt 1 are all “ off ”, and the common cathode line s y gets into a state of being connected to the high impedance terminal hiz functionally , that is , in a floating state . table 1 is a truth table to show the above operation . in the meantime , a data output unit 22 ′ selectively connects each of the common anode lines d 1 , . . . , dm to a constant current source cc and a high impedance terminal hiz in accordance with the control of a control unit ( not shown ). fig8 is a block diagram of a data output unit relative to one common cathode line of fig5 . as shown in fig8 the data output unit 22 ′ includes two pmosfets forming current mirror circuits pmt 2 , pmt 3 , a constant current source cc being connected to the current mirror circuits , a third level shift ls 3 converting the logic level of an outer control signal pwm into a high voltage level v h , and a pmosfet pmt 4 for applying a constant current to the common anode line d x with the “ on ”/“ off ” by the third level shift ls 3 . in the drawing , a reference number nmt 2 presents nmosfet for grounding the common anode line d x turning “ on ” by an outer control signal reset in the “ off ” state of the pmosfet pmt 4 . [ 0049 ] fig9 is a block diagram of an oled panel driving apparatus of the present invention . as shown in fig9 the oled panel driving apparatus of the present invention mainly includes a scan driving circuit 20 ′, a data driving circuit 30 ′, and an oled control circuit 40 for outputting various clock signals pwm clk , data clk , etc . and display data and control signal v sync , h sync , etc . to the scan driving circuit 20 ′ and the data driving circuit 30 ′. in the aforementioned structure , the data driving circuit 20 ′ includes an aforementioned data output unit 22 ′ ( it is referred to as “ current output unit ” in the drawing after a typical term in the related art ), a shift register / latch unit 28 for sequentially shifting and storing r , g , b display data applied from the oled control circuit 40 with synchronized by a data clock signal clk , that is , the data finally applied to the common anode lines d 1 , . . . , dm , and a pwm generating unit 26 for converting the data supplied from the shift register / latch 28 into signal having different time width in accordance with the gray level , and supplying to the data output unit 22 ′. the oled control circuit 40 supplies pwm clock signal pwm clk to the pwm generating unit 26 . further , the scan driving circuit 30 ′ includes an aforementioned scan output unit 32 ′ ( it is referred to as “ high voltage output buffer unit ” in the drawing after a typical term in the related art ), a shift register unit 38 for generating a scan control signal c scan with respect to the common cathode lines s 1 , . . . , sn selected in accordance with a horizontal synchronization signal h sync supplied from the oled control circuit 40 , and a control logic unit 36 executing logic - processing for the scan control signal c scan supplied from the shift register unit 38 , and generating a scan control signal c scan and a high impedance control signal c hiz , and supplying to the scan output unit 22 ′. [ 0052 ] fig1 is a detailed circuit diagram of a scan driving circuit of fig9 . as shown in fig1 , the shift register unit 38 is configured such that unit shift registers sr 1 , . . . , srn having the same number as that of the common cathode lines , n , are aligned in series , and horizontal synchronization signals h sync are supplied to the clock ends of the all shift registers sr 1 , . . . , srn . then , to the data input end of the first row of the shift register sr 1 , a vertical synchronization signal , being output from the oled control circuit 40 , is supplied , and in the rest of the shift registers sr 1 , . . . , srn , the output of any row of the shift register sry is directly connected to a corresponding scan control signal end c scan of the scan output unit 32 ′, and at the same time , is connected to the data input end of the next row of the shift register sry + 1 . the shift registers sr 1 , . . . , srn are composed of negative - truth logic circuits , and structured to operate at the down - edges of the data signal and clock signal . a control logic unit 36 has 2 - inputs , and is also composed of unit xnor gates xnor 1 , . . . , xnorn as many as the number of the common cathode lines , n , and one input end of each row of the xnor gate xnory is connected to the output end of its corresponding row of the shift register sr y , and the other input end is connected to the output end of next row of the shift register sr y + 1 , and the output end is connected to the corresponding high impedance control signal end c hiz of the scan output unit 32 ′. now herein after , the operation of the oled panel driving apparatus of the present invention and its method will be explained in detail . [ 0055 ] fig1 is an operation timing diagram of a scan driving circuit and a data driving circuit to illustrate a method of driving an oled panel of the present invention . as shown in fig1 , a vertical synchronization signal v sync is generated every frame of display , and horizontal synchronization signals h sync , being as many as the number of the common cathode lines n , are generated in the vertical scan period between the vertical synchronization signals , and data is applied to the all common anode lines d 1 , . . . , dm in the horizontal scan period between the horizontal synchronization signals h sync at the same time . describing this in more detail , the vertical synchronization signal v sync generated from the oled control circuit 40 is supplied into the data input end of a first row of the shift register sr 1 of the scan driving circuit 30 ′, and at the same time , if the horizontal synchronization signal h sync is supplied to the clock end , the first row of the shift register sr 1 operates at the down edge of the vertical synchronization signal v sync and the horizontal synchronization signal h sync , and logic signal “ 0 ” is output to its output end , that is , a scan control signal end c scan . then , the signals output as above are supplied to a first row of the scan control signal end c scan of the scan output unit 32 ′ and to one input end of a first row of xnor gate xnor 1 , and since the other input end of the first row of xnor gate xnor 1 is connected to the output end of a second row of the shift register sr 2 , logic signal “ 0 ” is output to the output end of the first row of the xnor gate xnor 1 , that is , high impedance control signal end c hiz . then , logic signal “ 1 ” is output into the output ends of the shift registers sr 2 , . . . , srn and xnor gates xnor 2 , . . . , xnorn under a second row . in accordance with the states of the scan control signal c scan and the high impedance control signal c hiz , the scan output unit 32 ′ operates as shown in the truth table of the table 1 so as to connect the first row of the common cathode line s 1 to the grounding earth gnd in a high impedance state hiz , that is , in a floating state . then , in accordance with the control of the outer control signal pwm generated from the pwm generating unit 26 with synchronized by the horizontal synchronization signal h 1 in a horizontal scanning period with respect to the first row , with the pmosfet pmt 4 of the data output unit 22 ′ “ on ”, each of the common anode lines d 1 , . . . dm is connected to the constant current source cc for a predetermined pwm time in accordance with the pixel gray of the oled 12 connected thereto so that the oled 12 emits light , and then , with the pmosfet pmt 4 “ off ”, the common anode lines d 1 , . . . , dm maintain a high impedance state hiz . in the meantime , while the first row of the common cathode line s 1 is selected , the common cathode lines s 2 , . . . , sn of the row under the second row are maintained in a high impedance state hiz , and it can be illustrated as a truth table in table 2 . further , the letter and numbers presented as italic in the table 2 and the tables 3 and 4 mentioned later present the row selected at present . then , in the aforementhioned method , when a second row of the common cathode line s 2 is connected to the grounding earth gnd in a high impedance state hiz , that is , in a floating state , the oled 12 connected thereto emits light , and during the period , when the scan output unit 32 ′ connects the first row of the common cathode line s 1 to the high voltage terminal v h in accordance with the high impedance control signal c hiz and the scan control signal c scan , the polarity of the parasitic capacitor c of the oled 12 connected thereto is inverted , and the degradation of the oled 12 can be prevented ( refresh ). the operation can be shown in table 4 as a truth table . then , a three row of the common cathode line s 3 is connected to a grounding earth gnd , and while the oled 12 connected thereto emits light , the second row of the common cathode line s 2 is connected to a high voltage terminal v h , and the parasitic capacitor c of the oled 12 connected thereto is discharged . then , sequentially while the oled 12 connected to the last row of the common cathode line sn emits light , the oled 12 connected to the first row of the common cathode line s 1 maintains a high impedance state by an outer control signal chiz . the operation can be shown in table 4 as a truth table . as described above , in the oled panel driving method of the present invention , any one row of the common cathode line sy is sequentially scanned to the grounding level gnd in a high impedance state hiz , and while next row of the common cathode line s y + 1 is selected ( scanned ), the row of the common cathode line s y is connected to a high voltage terminal v h to invert the polarity of the parasitic capacitor c of the oled 12 connected thereto , and then , from the point when the next row after the above next row of the common cathode line s y + 2 is selected ( scanned ), the row of the common cathode line s y is maintained in a high impedance state hiz . as a result , according to the oled panel driving method of the present invention , the period , in which a parasitic capacitor c is formed between the anode and the cathode of the oled 12 , is only the state in which the common cathode line s y is connected to a high voltage terminal v h or the grounding earth gnd , and a parasitic capacitance does not exists in the state that it is connected to the high impedance terminal hiz . therefore , in the oled driving method of the present invention , since the parasitic capacitance exist only in the oled connected to one common cathode line connected to the grounding earth gnd , and the oled connected to one common cathode line connected to the high voltage terminal v h , desired gray can be expressed without the use of the precharge as in the conventional case , and further , its power consumption can be reduced down to 2 / n compared with that of the conventional case . this can be presented as equation 2 as follows . p d = 2 * m * c * v h 2 * f clk [ equation 2 ] in the equation 2 , c presents parasitic capacitor existing in the oled 12 , m presents the number of the common anode lines , v h presents the high voltage applied to the anode , and fclk presents the operation frequency of the scan driving circuit 30 ′. for example , in the case of an oled panel driving apparatus having a resolution of 128 × 160 , since the number n of the cathode lines of the oled is 160 , the power consumption can be reduced down to { fraction ( 1 / 80 )}. the oled panel driving apparatus and the driving method thereof of the present invention are not limited to the exemplary embodiments described as above , and it will be understood that various modifications and applications are possible within the sprit and scope of the present invention . as described above , according to the oled panel driving apparatus and the driving method thereof of the present invention , low gray processing is possible just by the pwm data current without the use of the precharge method , so as to reduce the power consumption generated due to the precharge , and allow speedy operation . while the invention has been shown and described with reference to certain preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims . for example , while the invention has been described in the specific content of an oled panel driving apparatus and a driving method thereof , those skilled in the art will appreciate that various applications are possible for the apparatus and method . the foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention . the present teaching can be readily applied to other types of apparatuses . the description of the present invention is intended to be illustrative , and not to limit the scope of the claims . many alternatives , modifications , and variations will be apparent to those skilled in the art . in the claims , means - plus - function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures .