text: as a preface to the detailed description , it should be noted that , as used in this specification and the appended claims , the singular forms “ a ”, “ an ”, and “ the ” include plural referents , unless the context clearly dictates otherwise . the embodiment example etch processes described herein were carried out in a centura ® integrated processing system available from applied materials , inc ., of santa clara , calif . this apparatus is described in detail below ; however , it is contemplated that other apparatus known in the industry may be used to carry out the invention . [ 0027 ] fig1 a shows an elevation schematic of the centura ® integrated processing system 100 . the centura ® integrated processing system 100 is a fully automated semiconductor fabrication system , employing a single - wafer , multi - chamber , modular design which accommodates a variety of wafer sizes . for example , as shown in fig1 a , the centura ® etch system may include decoupled plasma source ( dps ) etch chambers 102 ; deposition chamber 103 ; advanced strip - and - passivation ( asp ) chamber 104 ; wafer orienter chamber 106 ; cooldown chamber 108 ; and independently operated loadlock chambers 109 . [ 0028 ] fig1 b is a schematic of an individual centura ® dps ™ etch chamber 102 of the type which may be used in the centura ® integrated processing system , commercially available from applied materials , inc ., santa clara , calif . the equipment shown in schematic in fig1 b includes a decoupled plasma source ( dps ) of the kind described by yan ye et al . at the proceedings of the eleventh international symposium of plasma processing , may 7 , 1996 , and as published in the electrochemical society proceedings , volume 96 - 12 , pp . 222 - 233 ( 1996 ). the centura ® dps ™ etch chamber 102 is configured to be mounted on a standard centura ® mainframe . the centura ® dps ™ etch chamber 102 consists of an upper chamber 112 having a ceramic dome 113 , and a lower chamber 116 . the lower chamber 116 includes an electrostatic chuck ( esc ) cathode 110 . gas is introduced into the chamber via gas injection nozzles 114 for uniform gas distribution . chamber pressure is controlled by a closed - loop pressure control system ( not shown ) with a throttle valve 118 . during processing , a substrate 120 is introduced into the lower chamber 116 through inlet 122 . the substrate 120 is held in place by means of a static charge generated on the surface of electrostatic chuck ( esc ) cathode 110 by applying a dc voltage to a conductive layer located under a dielectric film on the chuck surface ( not shown ). the cathode 110 and substrate 120 are then raised by means of a wafer lift 124 and a seal is created against the upper chamber 112 in position for processing . etch gases are introduced into the upper chamber 112 via the ceramic gas injection nozzles 114 . the etch chamber 102 uses an inductively coupled plasma source power 126 operating at 2 mhz , which is connected to inductive coil 134 for generating and sustaining a high density plasma . the wafer is biased with an rf source 130 and matching network 132 operating within the range of 100 khz to 13 . 56 mhz ; more typically , within the range of 100 khz to 2 mhz . power to the plasma source 126 and substrate biasing means 130 are controlled by separate controllers ( not shown ). the temperature on the surface of the etch chamber walls is controlled using liquid - containing conduits ( not shown ) which are located in the walls of the etch chamber 102 . the temperature of the semiconductor substrate is controlled using the temperature of the electrostatic chuck cathode 110 upon which the substrate 120 rests . typically , a helium gas flow is used to facilitate heat transfer between the substrate and the pedestal . as previously mentioned , although the etch process chamber used to process the substrates described in the examples presented herein was an inductively coupled etch chamber of the kind shown in schematic in fig1 b , any of the etch processors available in the industry should be able to take advantage of the etch chemistry described herein , with some adjustment to other process parameters . ii . exemplary method of the invention : etching a deep trench having a sooth sidewall in a silison substrate for purposes of comparison , a first etch process was carried out in a manner previously demonstrated in the art , where a trench is anisotropically etched in a silicon substrate . a g - line or i - line photoresist was applied over the substrate and then patterned to produce a mask over the silicon surface . the masked silicon surface was then exposed to a reactive etching plasma generated from an sf 6 plasma source gas , as step one of the etching process . subsequently , in a second step , the etched silicon surface was contacted with a plasma generated from a polymer - forming gas ( c 4 f 8 ), to cover the etched silicon surfaces with a polymer layer . steps one and two were repeated a number of times to provide deep etching into the silicon substrate . the data for this comparative example is presented in table one as run # 1 . the appearance of the etched sidewalls of the trench is shown in fig2 a , and the degree of microloading which occurred is shown in fig3 a . with respect to fig2 a , the trench structure includes an i - line photoresist masking layer 202 and an underlying silicon substrate 204 . the sidewalls 205 of trench structure 200 exhibited significant “ scalloping ”, where the cycling between etch and polymer deposition steps one and two , respectively , causes a rough sidewall 205 . in particular , the depth “ d ” of scallops 206 was in the range of about 35 nm to 40 nm , while the height “ h ” of scallops 206 was in the range of about 180 nm to 190 nm . with respect to fig3 a , the trench structure 300 includes a series of trenches of different sizes , etched into silicon substrate 306 through i - line patterned photoresist mask 308 . trenches 302 are approximately 4 , 400 nm in width “ w 1 ”, and 17 , 300 nm in height “ h 1a ”. trench 303 is approximately 10 , 600 nm in width “ w 2 ”, and 20 , 200 nm in height “ h 2a ”. trenches 304 are approximately 3 , 200 nm in width “ w 3 ”, and 16 , 600 nm in height “ h 3a ”. the difference in etch depth observed between the 4 , 400 nm wide trenches 302 and the 10 , 600 nm wide trench 303 was about 2 , 900 nm , while the difference in etch depth observed between the 3 , 200 nm wide trenches 304 and 10 , 600 nm wide trench 303 was about 3 , 600 nm . this difference in etch depth , which is a function of the size ( width ) being etched , is an illustration of a microloading effect . data for one embodiment of the present invention , which makes use of a stabilizing etchant which is constantly present during the etch process , is presented in table one as run # 4 , the appearance of the etched sidewalls of the trench is shown in fig2 b , and the degree of microloading which occurred is shown in fig3 b . a patterned i - line photoresist mask was formed over a silicon substrate . in a first etch step , the exposed portion of the silicon substrate was contacted with a plasma generated from a stabilizing etchant gas in combination with a reactive etching gas . subsequently , in a second step , the etched silicon surface was contacted with a plasma generated from the same stabilizing etchant gas , in combination with a polymer - forming gas . steps one and two were repeated a number of times to provide deep etching into the silicon substrate . with respect to fig2 b , the trench structure 220 includes a patterned i - line photoresist masking layer 222 and an underlying silicon substrate 224 . the sidewalls 225 of trench structure 220 exhibited insignificant “ scalloping ”, providing a particularly smooth trench sidewall 225 . in particular , the depth of disturbances on the surface 226 of sidewall 225 was less than 13 nm . the spacing between disturbances was in the range of about 180 nm to 190 nm , indicating that these small disturbances were due to cycling during the etch process . however , the roughness of the sidewall surface of the trench had been reduced by about 65 % due to the presence of the plasma species generated from the stabilizing etchant gas which was present during the entire etch process . with respect to fig3 b , the trench structure 320 included a series of trenches of different sizes , etched into silicon substrate 326 through patterned mask 328 . trenches 322 are approximately 4 , 400 nm in width “ w 1 ”, and 18 , 800 nm in height “ h 1b ”. trench 323 is approximately 10 , 600 nm in width “ w 2 ”, and 20 , 200 nm in height “ h 2b ”. trenches 324 are approximately 3 , 200 nm in width “ w 3 ”, and 18 , 800 nm in height “ h 3b ”. the difference in etch depth observed between the 4 , 400 nm wide trenches 322 and the 10 , 600 nm wide trench 323 was about 1 , 400 nm . this compares with the difference in etch depth observed between the 4 , 400 nm wide trenches 302 and the 10 , 600 nm wide trench 303 shown in fig3 a representing the comparative example . this shows a reduction in etch depth difference of about 40 % was obtained using the present method rather than the prior art comparative method of example one . this percentage difference is illustrated by ( d 1a − d 1b )/ d 1a × 100 , with reference to fig3 a and 3b . in the present example two , the difference in etch depth observed between 3 , 200 nm wide trenches 324 and the 10 , 600 nm wide trench 323 was about 2 , 150 nm . a comparison with the prior art example one data shows that a reduction ( improvement ) in etch depth difference of about 36 % was obtained when the present invention etch method was used . this percentage etch depth difference is illustrated by ( d 2a − d 2b )/ d 2a × 100 . this decrease in the difference of etch depth as a function of the size of the trench is an indication of an improvement in microloading effect and is attributed to the use of a stabilizing etchant continuously throughout the etch process . table one presents a series trial etching processes , represented as runs # 1 through # 4 , where run # 1 is the comparative example . table one process conditions for various trench etching experiments plasma substrate bias plasma source no . of source gas power & amp ; substrate power & amp ; times flow rate time frequency voltage frequency pressure step was ( sccm ) ( sec ) ( w ) & amp ; ( khz ) (− v ) ( w ) & amp ; ( khz ) ( mtorr ) repeated run 1 step # 1 sf 6 - 200 5 0 w 5 - 10 1 , 000 & amp ; 1256 70 100 ( self bias ) step # 2 c 4 f 8 - 200 6 7 & amp ; 400 40 1 , 000 & amp ; 1256 70 100 run 2 step # 1 hbr - 6 5 0 w 5 - 10 1 , 000 & amp ; 1256 70 100 c 4 f 8 - 200 ( self bias ) step # 2 hbr - 6 6 7 & amp ; 400 40 1 , 000 & amp ; 1256 70 100 sf 6 - 200 run 3 step # 1 hbr - 12 5 0 w 5 - 10 1 , 000 & amp ; 1256 70 100 c 4 f 8 - 200 ( self bias ) step # 2 hbr - 12 6 7 & amp ; 400 40 1 , 000 & amp ; 1256 70 100 sf 6 - 200 run 4 step # 1 hbr - 20 5 0 w 5 - 10 1 , 000 & amp ; 1256 70 100 c 4 f 8 - 200 ( self bias ) step # 2 hbr - 20 6 7 & amp ; 400 40 1 , 000 & amp ; 1256 70 100 sf 6 - 200 [ 0040 ] table two structure after etch processing as described in table one etch depth etch depth patterned etch @ 4 . 4 μm @ 10 . 6 μm resist selectivity space space thickness si substrate : between between remaining scallop standard trenches trenches after etch size i - line micro - run # ( nm ) ( nm ) ( μm ) ( å ) photoresist loading 1 1 , 725 2 , 000 0 . 53 333 137 15 % 2 na 2 , 100 0 . 56 333 146 na 3 na 2 , 000 0 . 62 333 147 na 4 1 , 880 2 , 100 0 . 63 150 154 10 % [ 0041 ] table three process conditions for silicon etching step optimum range typical known of process process process process parameter conditions conditions conditions stabilizing etchant 1 1 - 200 2 - 100 20 flow rate ( sccm ) 2 sf 6 flow rate ( sccm ) 2 20 - 500 50 - 350 200 inert gas 3 flow rate ( sccm ) 2 0 - 100 20 - 70 unknown plasma source power ( w ) 700 - 2000 900 - 1300 1000 plasma source power 100 - 13 , 560 160 - 2000 200 - 400 rf frequency ( khz ) substrate bias power ( w ) 0 - 40 5 - 15 5 - 10 substrate bias power rf 100 - 500 200 - 500 400 frequency ( khz ) substrate bias voltage (− v ) 2 - 100 10 - 100 10 - 50 process chamber pressure 4 - 200 25 - 180 30 - 150 ( mtorr ) substrate temperature (° c .) 10 - 120 20 - 50 20 - 30 etch time period ( seconds ) 3 - 30 3 - 20 4 - 18 when a different intermittent fluorine - containing etchant gas such as nh 3 or cf 4 is substituted for sf 6 , it is necessary to adjust the flow rate of the etchant gas to maintain approximately the same concentration of fluorine etchant species . one skilled in the art can make this adjustment with minor experimentation in view of published kinetics data for the fluorine - containing gases mentioned . table four process conditions for polymer deposition step optimum range typical known of process process process process parameter conditions conditions conditions stabilizing etchant 1 1 - 200 2 - 100 20 ( sccm ) 2 fluorocarbon 3 ( sccm ) 2 50 - 200 25 - 220 100 - 220 or hydrofluorocarbon 4 50 - 200 25 - 220 180 - 220 ( sccm ) 2 or hydrocarbon 5 ( sccm ) 2 50 - 100 20 - 50 unknown inert gas 7 flow rate ( sccm ) 2 0 - 100 0 - 100 0 - 100 plasma source power ( w ) 700 - 3000 900 - 2000 1000 plasma source power rf 100 - 13 , 560 100 - 2000 200 - 400 frequency ( khz ) substrate bias power ( w ) 0 0 0 substrate bias power rf 160 - 560 200 - 500 400 frequency ( khz ) substrate bias voltage (− v ) 5 ( self bias ) ( self 5 ( self bias ) bias ) process chamber pressure 5 - 200 25 - 180 30 - 150 ( mtorr ) substrate temperature (° c .) 15 - 120 20 - 50 20 - 30 polymer deposition time 3 - 20 3 - 20 4 - 7 period ( seconds ) as previously mentioned , the stabilizing etchant species which is used constantly during the plasma etching process may be used in combination with an intermittent etch step etchant species during the etch step , followed by intermittent application of a polymer deposition step plasma species , or may be used in combination with an intermittent plasma comprised of admixed etchant species and polymer deposition species . the number of applications of intermittent etch step etchant species and intermittent polymer deposition species will vary depending on the depth of the recessed feature to be etched . typically , for example , for a trench which is about 20 μm deep , intermittent etching will be carried out from about 50 to about 100 times . when the polymer deposition is carried out separately from the intermittent etching , the polymer deposition step for the 20 μm deep trench will be carried out from about 50 to about 100 times . after completion of the etching of the recessed feature , it may be desirable to use a clean up step to remove residual masking materials and / or residual polymeric material from the etching process . one example of a clean up method is an oxygen plasma clean - up step which is particularly useful when a hard mask layer ( such as silicon oxide , silicon nitride , or silicon oxynitride ) is used in lieu of , or in combination with , a photoresist , due to the tendency of oxygen to rapidly etch conventional organic photoresists . table five process conditions for clean - up step optimum range typical known of process process process process parameter conditions conditions conditions o 2 flow rate ( sccm ) 50 - 500 100 - 300 200 plasma source power ( w ) 500 - 3000 700 - 2000 1000 plasma source power rf frequency ( khz ) 100 - 13 , 560 100 - 2000 200 - 400 substrate bias power ( w ) 0 - 100 0 - 50 5 - 10 substrate bias power rf 100 - 500 200 - 500 400 frequency ( khz ) substrate bias voltage (− v ) 0 - 200 20 - 150 40 - 100 process chamber pressure 20 - 200 25 - 100 30 ( mtorr ) substrate temperature (° c . )* 40 - 120 50 - 100 60 clean - up step time period 10 - 600 100 - 400 180 ( seconds ) the above described exemplary embodiments are not intended to limit the scope of the present invention , as one skilled in the art can , in view of the present disclosure expand such embodiments to correspond with the subject matter of the invention claimed below .