text: although this invention is described in terms of certain preferred embodiments , other embodiments that are apparent to those of ordinary skill in the art , including embodiments which do not provide all of the benefits and features set forth herein , are also within the scope of this invention . accordingly , the scope of the present invention is defined only by reference to the appended claims . one use of a coordinate rotation digital computer ( cordic ) algorithm is to generate functions such as trigonometric , logarithmic , hyperbolic and linear functions . another use of the cordic algorithm is to convert between polar and cartesian coordinates . the cordic algorithm performs vector coordinate rotations using simple iterative shifts and add / subtract operations . the general ( givens &# 39 ;) rotation transform expressed in equations 1a and 1b rotates a vector by an angle φ . y ′= y cos φ + x sin φ . eqs . 1a and 1b the transform can be rearranged as shown in equations 2a and 2b . the rotation angle s can be selected such that tan ( φ )=± 2 − i , i . e ., powers of two , which can be implemented by shift operations . an overall rotation angle can be reached by applying successively smaller rotations . at each iteration , i , the direction of rotation is decided . this further simplifies equations 2a and 2b to equations 3a and 3b . x i + 1 = k i ⁡ [ x i - y i ⁢ 2 - i ⁢ σ i ] ⁢ ⁢ y i + 1 = k i ⁡ [ y i + x i ⁢ 2 - i ⁢ σ i ] ⁢ ⁢ σ i ∈ { - 1 , 1 } eqs . ⁢ 3 ⁢ a ⁢ ⁢ and ⁢ ⁢ 3 ⁢ b since , k i is a constant multiplier that affects magnitude , k i can be pre - calculated and easily compensated . equation 4 illustrates the accumulation in the rotation angles at each iteration . z i + 1 = z i − σ i tan − 1 ( 2 − i ) eq . 4 conventionally , the values of tan − 1 ( 2 − i ) are stored in a relatively small read only memory ( rom ) lookup table ( lut ). the cordic algorithm can be applied in rotation mode or in vectoring mode . the rotation mode rotates the input vector by the angle specified through z 0 . successive iterations rotate in the direction to attempt to reduce this angle z i . therefore , the direction to rotate is dependent on z i and is expressed as equation 5 . σ i = { 1 z i ≥ 0 - 1 z i & lt ; 0 eq . ⁢ 5 the vectoring mode rotates the input vector through an angle such that the resulting vector lies on the x - axis . successive iterations rotate in the direction to reduce the y - component , y i . therefore , the direction to rotate is dependent on y i and is expressed as equation 6 . σ i = { 1 y i & lt ; 0 - 1 y i ≥ 0 eq . ⁢ 6 the initial values of the system variables , x 0 , y 0 , and z 0 determine the function computed . examples of uses for the vectoring mode include cartesian to polar conversion , calculation of arctangents , and calculation of vector magnitude . generally , if the cordic algorithm can compute a function , the inverse of the function can also be computed the cordic equations can be modified to introduce a coordinate system factor , m . the coordinate systems are hyperbolic ( m = 1 ), linear ( m = 0 ) and circular ( m =− 1 ). these extensions allow the cordic algorithm to compute linear and hyperbolic functions . one implementation of the cordic algorithm uses comparators for each stage to determine the direction of rotation a modified cordic algorithm for direct digital frequency synthesis ( ddfs ) or dds simplifies a cordic computation by determining the d ion of rotation directly from the bits r k representing the angle φ , as shown in equation 7 . r k = { 1 bit = 1 - 1 bit = 0 eq . ⁢ 7 the modified cordic algorithm uses φ = 2 − i instead of φ = tan − 1 ( 2 − i ) as sub - angles . this modifies the standard cordic equations to the equations expressed in equations 8a - d . x i + 1 = k i ⁡ [ x i - y i ⁢ ⁢ tan ⁡ ( 2 - i ) ] y i + 1 = k i ⁡ [ y i - x i ⁢ tan ⁡ ( 2 - i ) ] } ⁢ r k = 1 ⁢ ⁢ x i + 1 = k i ⁡ [ x i + y i ⁢ ⁢ tan ⁡ ( 2 - i ) ] y i + 1 = k i ⁡ [ y i + x i ⁢ tan ⁡ ( 2 - i ) ] } ⁢ r k = - 1 eqs . ⁢ 8 ⁢ a , 8 ⁢ b , 8 ⁢ c , and ⁢ ⁢ 8 ⁢ d table 1 illustrates that the values of tan ( 2 − i ) and 2 − i are similar for values of i & gt ;( wordlength / 3 ). the similarity can simplify the hardware to relatively simple hardwired shifts for values of i & gt ;( wordlength / 3 ). in one embodiment , the first ( wordlength / 3 ) stages are merged together and implemented with rom . fig1 illustrates an execution block 100 of a dsp with a cordic assist 104 according to an embodiment of the invention . the cordic assist 104 is pipelined such that a function generated output , such as a sine / cosine output , is available at every clock style of the cordic assist 104 . the execution block 100 further includes an instruction decoder 102 and a local register file 112 . the execution block 100 can further include other dsp functional units typical of a dsp , such as a multiplier accumulator ( mac ) 106 , an arithmetic logic unit ( au ) 108 , and a shifter 110 . in the illustrated embodiment , the cordic assist 104 shares the local register file 112 and the instruction decoder 102 with the other dsp functional units . in one embodiment , the core of the dsp has a scalable and configurable architecture , which allows the designer to plug - in a variety of functional units without changing the external interfaces of the block with the rest of the core . the instruction decoder 102 can be centralized or distributed . in one embodiment , the instruction decoder 102 is distributed , and a program sequencer of the core dispatches instructions to multiple execution blocks . the dispatched instructions are then decoded by the distributed instruction decoders of the specific blocks . in one embodiment , a function generation process , such as sine / cosine generation , is initiated early . in one embodiment , the function generation process is initiated early by approximately the amount of time equal to the initial latency of the pipelined process , such that an output of the function generation process is available in response to a read instruction . in one embodiment , the execution block 100 can execute two instructions per cycle . thus , the execution block 100 includes multiple read ports available from the local register file 112 . however , it will be understood by one of ordinary skill in the art that other embodiments of the execution block 100 according to the invention can execute a wide variety of instructions per cycle , and can even include multiple cycles per instruction . in one embodiment , the cordic assist 104 responds to at least two specific instructions . these instructions are a startcordic instruction and a readcordic instruction . in one embodiment , the startcordic instruction passes two parameters to the cordic assist 104 . these parameters are an initial phase angle and an increment value . after initial latency cycles , which vary depending on the number of stages or segments of the pipeline , the result of the first computation progresses through the stages or segments of the pipelined cordic assist 104 and to the output of the cordic assist 104 . in one embodiment , the result of the cordic computation is not automatically written to a register file in the local register file 112 . rather , the computed result is retained until an explicit read instruction , e . g ., a readcordic instruction , is applied to the cordic assist 104 , which then transfers the computed result to a register in the local register file 112 . the following sequence of instructions further illustrates how to use the cordic assist 104 . n : startcordic ( r1 , r2 ) n + 1 : & lt ; instr & gt ;, & lt ; instr & gt ; n + 2 : & lt ; instr & gt ;, & lt ; instr & gt ; n + 3 : & lt ; instr & gt ;, & lt ; instr & gt ; n + 4 : & lt ; instr & gt ;, & lt ; instr & gt ; n + 5 : readcordic ( r4 ) in the sample instructions shown above , an initial angle is specified in r1 , and the increment in angle is specified in r2 . in the illustrated embodiment , the sine and the cosine values of initial angle are ready in cycle n + 5 and are available to be read in cycle n + 5 or a later cycle , i . e ., the number of latency cycles is 5 . in the illustrated embodiment , the sine and the cosine of the next value ( r1 + r2 ) are immediately available to be read in the next cycle after the readcordic instruction is applied . another sample sequence of instructions is provided below : n + 6 : readcordic ( r4 ); sin / cos ( r1 + r2 ) n + 7 : readcordic ( r6 ); sin / cos ( r1 + 2 * r2 ) n + 8 : & lt ; instr & gt ; n + 9 : & lt ; instr & gt ; n + 10 : readcordic ( r4 ); sin / cos ( r1 + 3 * r2 ) in one embodiment , the cordic assist 104 also supports a register - interlocking mechanism , which stalls the pipeline if the user , dsp , controller , and the like , issues the first readcordic instruction before the end of the initial latency cycles . in one embodiment , if a startcordic instruction is issued after a subsequent startcordic instruction , then the second instruction result is received at the output . the cordic assist 104 can further be configured to respond to a resetcordic instruction . in one embodiment , the resetcordic instruction initializes the stages or segments in the cordic assist 104 that are computed such as cordic stages , but does not reset a stage where data is merely retrieved , as in a rom lookup table . fig2 illustrates a pipelined sine / cosine generation unit 200 according to an embodiment of the invention . the architecture of the illustrated pipelined sine / cosine generation unit 200 advantageously incorporates the instruction based control of the cordic assist 104 described earlier in connection with fig1 . the pipelined sine / cosine generation unit 200 includes an accumulator 202 , a π / 4 multiplier 220 , an output select unit 222 , a first quadrant π / 4 mirror 224 , a read only memory ( rom ) lookup table ( lut ) 226 , and a multi - stage butterfly pipeline 228 . the accumulator 202 generates the angle value for which the remaining portions of the pipelined sine / cosine generation unit 200 compute the sine function and cosine function . in the illustrated embodiment , the accumulator 202 includes a multiplexer 204 , a data register 206 , and an adder 208 . an initial angle 210 , i . e ., the stating angle , is provided as an input to the multiplexer 204 . when the pipelined sine / cosine generation unit 200 begins to process the sine function and the cosine function of the initial angle 210 , the multiplexer 204 is configured to select the initial angle 210 and to pass the initial angle 210 as an input to the data register 206 , which latches the state of the initial angle 210 . in one embodiment , the initial angle 210 is loaded into the data register 206 through a data bus 230 . an output 214 of the data register 206 , which contains the angle that enters the first stage of the computational stages , is provided as an input to the π / 4 multiplier 220 , the output select unit 222 , and the first quadrant π / 4 mirror 224 . the output 214 of the data register 206 is also provided as an input to the adder 208 . the adder 208 forms part of a feedback path that increments the angle output of the data register 206 . the adder 208 sums the output 214 of the data register 206 with a frequency control word 212 . in one embodiment , the frequency control word 212 is stored in a register that is loaded through the data bus 230 , and the frequency control word from the register is provided as an input to the adder 208 . the value of the frequency control word determines an amount of increment to the angle , i . e ., determines the step size of the angle . the adder 208 sums the frequency control word 212 with the output 214 of the data register 206 , and provides the sum as an input to the multiplexer 204 . the multiplexer 204 is configured to select the summed output of the adder 208 when the accumulator 202 is stepping the angle . the output of the multiplexer 204 is provided as an input to the data register 206 . when the data register 206 is triggered or re - latched , the data register latches the output of the multiplexer 204 , and the output 214 of the data register has incremented by the amount of the frequency control word . the output 214 of the data register 206 is again applied to the adder 208 , thereby allowing the accumulator 202 to continue to increment the angle provided by the output 214 of the data register 206 . due to the symmetry of sine and cosine waves , the cosines and sines of an entire 360 - degree range need not be computed . rather , a more limited range , such as 45 degrees or 90 degrees , can be computed , and the computed sines and cosines can be inverted and / or swapped to rotate the computed result by , for example , a multiple of 90 degrees . in one embodiment , the output 214 of the data register 206 containing the angle is provided with 20 bits of precision . in one embodiment , the two most significant bits of the output 214 of the data register 206 are provided as inputs to the output select unit 222 . the two most significant bits indicate the quadrant of the angle . the output select unit 222 inverts and swaps the output of the multi - stage butterfly pipeline 228 to rotate the cosine and sine computations of the multi - stage butterfly pipeline 228 to their original quadrant . the output 214 of the accumulator 202 is a normalized angle φ which is converted to an actual radian value φ [ 0 , π / 4 ]. in one embodiment , the output 214 of the accumulator 202 is provided as an input to the hardwired π / 4 multiplier 220 , which converts the normalized angle φ to radians . in one embodiment , the hardwired π / 4 multiplier 220 generates five partial products to achieve more than 16 bits of precision . in the illustrated embodiment , an output of the hardwired π / 4 multiplier 220 is provided as an input to the first quadrant π / 4 mirror 224 . in one embodiment , the first quadrant π / 4 mirror 224 is a subtractor that replaces the angle φ as [ 0 , π / 4 ] by [ π / 2 - π ] whenever the original phase accumulation angle θ , i . e ., the output of the third π / 4 multiplier 220 , is in the upper half of the first quadrant . in one embodiment , a third most significant bit of the output 214 of the data register 206 , which is illustrated in fig2 by a one - bit wide signal from the data register 206 to the first quadrant π / 4 mirror 224 , indicates whether the rotated angle is in the upper half or the lower half of the first quadrant . to achieve 16 bits of output precision , one embodiment of the pipelined sine / cosine generation unit 200 includes 16 butterfly stages . in the illustrated embodiment , the pipelined sine / cosine generation unit 200 substitutes the first four stages of the pipeline with a read only memory ( rom ) lookup table ( lut ) 226 and implements the next twelve pipelined stages by cascading 12 butterfly stages in the multi - stage butterfly pipeline 228 . in one embodiment , the rom lut 226 includes 16 words of data . table ii illustrates one example of the contents of the rom lut 226 . table ii x y 32745 1027 32617 3069 32363 5099 31983 7109 31473 9095 30845 11041 30096 12946 29230 14798 28245 16599 27155 18329 25957 19990 24659 21570 23261 23071 21777 24477 20205 25789 18557 26999 the outputs of the multi - stage butterfly pipeline 228 is provided as an input to the output select unit 222 . after the output select unit 222 rotates the outputs of the multi - stage butterfly pipeline 228 as dictated by indication of the original quadrant of the angle that is provided by the most significant bits of the output 214 of the data register 206 . the sample code , below , is written in an assembly language for a dsp core . the “∥ to the left of a line of code indicates an instruction that can execute in parallel with the prior instruction . the sample code illustrates how the pipelined sine / cosine generation unit 200 can simplify and accelerate an operation , such as a computation of a fast fourier transform ( fft ), in a dsp . the following sample code corresponds to a 16 - point fft implemented by a radix - 2 butterfly . // initial setup phase n = 16 ; k = 0 ; ns = n & gt ;& gt ; 1 ; ar0 = d [ k ] || ar1 = d [ k + ns ]; ar2 = store_buffer_address ; startcordic ( r10 , r11 ); for ns repeat { r0i = * ar0 || r2i = * ar1 ; r4 = add2 ( r0 , r2 ); * ar2 ++ = r4i || r6 = sub2 ( r0 , r2 ) || readcordic ( r10 , r11 ); r12 = dmac ( r6 , r10 ); r13 = idmac ( r6 , r10 ); * ar3 = r12i ; } fig3 illustrates a process 300 of quadrature modulation / demodulation with a pipelined sine / cosine generatoraccording to an embodiment of the invention . in a first step 310 , the process receives data from an input sequence . in one embodiment , the data is from a receiver . the data can be initially stored in a memory device and received by the process later in non real time . the process advances from the first step 310 to a second step 320 . in the second step 320 , the process generates values for a step of a cosine wave and a step of a sine wave . in one embodiment , the process computes the values of the cosine wave and the sine wave by computing the cosine function and the sine function in a pipelined cordic function generator . advantageously , a pipelined cordic function generator can generate steps of the cosine wave and the sine wave with relatively little latency and without having to generate or store a relatively large lookup table . in one embodiment , the pipelined cordic automatically starts and stops as described earlier in connection with fig2 . the process advances from the second step 320 to a third step 330 . in the third step 330 , the process multiplies the cosine wave and sine wave outputs of the pipelined cordic function generator with the received data to generate in - phase ( cosine ) or the quadrature - phase ( sine ) modulated or demodulated products . fig4 illustrates a process 400 of pipeline control according to an embodiment of the invention . the process advantageously controls a pipelined process , such as a pipelined cordic , such that the pipelined process can be easily integrated with a controller , digital signal processor , and the like . the illustrated process starts at a receive instruction step 401 . in the receive instruction step 401 , the process receives an instruction related to the control of the pipelined process . for example , a microprocessor , microcontroller , digital signal processor , and the like can access the pipelined process by issuing instructions to the pipeline control process . the process advances from the receive instruction step 401 to a reset decision block 402 . in the reset decision block 402 , the process determines whether the received instruction corresponds to a command to reset the cordic . where the received instruction is a reset instruction , such as a resetcordic instruction , the reset decision block 402 proceeds to a reset step 404 . where the command is other than the reset instruction , the reset decision block 402 proceeds to a start decision block 406 . in the reset step 404 , the process resets those circuits in the pipelined process that are calculated . in one embodiment , where the pipelined process is a cordic , the reset step 404 resets all the cordic stages or butterfly stages . in another embodiment , where the pipelined process is a combination of a lookup table stage and of cordic stages , the reset step 404 resets the cordic stages or butterfly stages but does not reset the lookup table stage . the process returns from the reset step 404 to the start of the process . in the start decision block 406 , the process determines whether the received instruction corresponds to a start instruction for the pipeline . typically , a start instruction is applied to a pipelined process when the starting data has changed . one example of an appropriate time to issue a start instruction is where the pipelined process synthesizes a frequency , and the synthesized frequency has changed by updating an amount of an angle increment when the received instruction is a start instruction , such as a startcordic instruction , the process proceeds from the start decision block 406 to a first advance pipeline step 408 . when the received instruction is other than the start instruction , the process proceeds from the start decision block 406 to a read decision block 412 . in the first advance pipeline step 408 , the process advances data from one stage or segment of the pipelined process to another . for example , a stage or segment can advance data in response to a rising or a falling edge of a clock signal . in one embodiment , the process controls the pulsing of the clock signal used to enable sequencing through the pipelined process . it will be understood by one of ordinary skill in the art that a variety of techniques can be used to control sequencing through the pipelined process , including for example , providing an enable signal as an input to the stages or segments of the pipelined process . the process advances from the first advance pipeline step 408 to a computation available decision block 410 . in the computation available decision block 410 , the process determines whether the new computation is available at the end of the pipelined process . that is , the process determines whether data has advanced far enough in the pipelined process to have progressed from the beginning stage or segment to the last stage or segment , i . e ., whether the initial latency of the pipelined process has concluded . in one embodiment , the process counts the number of activations of the pipeline sequencing and compares the count to a known count of the number of stages or segments to determine whether the new computation is available at the end of the pipelined process . when the new computation is available , the process returns from the computation available decision block 410 to the start of the process , and awaits the next instruction . when the new computation is not yet available , the process returns from the computation available decision block 410 to the first advance pipeline step 408 to continue to advance data through the pipelined process . in the read decision block 412 , the process determines whether the received instruction corresponds to a command to read data from the pipelined process . when the received instruction is a read instruction , the process proceeds from the read decision block 412 to an output computation step 414 . when the received instruction is other than the read instruction , such as a “ no operation ” instruction , the process returns from the read decision block 412 to the start of the process . in the output computation step 414 , the process enables an output of the pipelined process . for example , when the final data is stored in an output register , the process can enable a tri - stateable gate to couple the contents of the output register on a data bus , where the contents are read by a controller , dsp , mac , and the like . the process advances from the output computation step 414 to a second advance pipeline step 416 . in the second advance pipeline step 416 , the process advances the pipelined process by a single stage or segment , i . e ., data moves from one segment to the next segment . in one embodiment , the process advances data in the second advance pipeline step 416 by providing a single clock pulse to the pipelined stages or segments . the illustrated process repeats indefinitely . the skilled practitioner will appreciate that the reset decision block 402 , the start decision block 406 , and the read decision block 412 can appear in the process in any order . fig5 illustrates a pipeline control circuit 500 according to an embodiment of the invention . the illustrated pipeline control circuit 500 includes an instruction decoder 502 and a pipeline control unit 504 . the pipeline control circuit 500 controls the resetting and the progressing of data through the segments of a pipelined circuit , such as a pipelined cordic 550 . it will be understood by one of ordinary skill in the art that the pipeline control circuit 500 can control a wide variety of pipelined circuits and that the pipelined cordic 550 shown in fig5 is illustrative of but one example . other examples of pipelined circuits include divider circuits , relatively high - precision multiplier circuits such as 64 × 64 , relatively high - precision adder circuits , floating point units , and the like . the instruction decoder 502 receives instructions 506 from a microprocessor , digital signal processor , state machine , and the like . it will be understood by one of ordinary skill in the art that the instruction decoder 502 can be a part of a larger instruction decoder for a larger circuit such as the execution block 100 described earlier in connection with fig1 . the illustrated instruction decoder 502 generates a reset signal 510 , a read signal 512 , and a start signal 514 in response to the instructions 506 . in one embodiment , the instruction decoder 502 further includes a select input driven by , for example , an address decoder , that activates the instruction decoder 502 . the reset signal 510 is provided as an input to the pipelined circuit , which is shown in fig5 as the pipelined cordic 550 . the pipelined cordic 550 includes multiple stages or segments . in some pipelined circuits , not all of the segments of the pipeline need to be reset . for the purposes of example , the pipelined cordic 550 includes a lookup table ( lut ) circuit 552 as a first stage , a first cordic stage 554 as a second stage , a second cordic stage 556 as a third stage , and a third cordic stage 558 as a fourth stage . in the pipelined cordic 550 shown in fig5 , the reset signal 510 is applied as an input to the first cordic stage 554 , the second cordic stage 556 , and the third cordic stage 558 , but not to the lut circuit 552 . the read signal 512 and the start signal 514 are provided as inputs to the pipeline control unit 504 . a clock signal 508 is also provided as an input to the pipeline control unit 504 . in response to an activation of the read signal 512 , the pipeline control unit 504 activates the pipelined circuit so that data passes from one pipeline stage to another , such as from the first cordic stage 554 to the second cordic stage 556 . in one embodiment , the pipeline control unit 504 activates one pulse of a pipeline clock signal 516 in response to the activation of the read signal 512 . the pulse of the pipeline clock signal 516 is applied as an input to the stages of the pipelined circuit , which are activated in response to the pulse . a flip flop circuit can be used to generate a single pulse on the pipeline clock signal 516 in response to the activation of the read signal 512 . in one embodiment , the pipeline control circuit 500 includes a wait state generator that instructs the controller , dsp , mac , and like devices that reads the output of the pipelined circuit to temporarily wait until the data has propagated through the pipeline and is available to be read . the pipeline control unit 504 generates a series of pulses in response to an activation of the start signal 514 . the pipeline control unit 504 generates at least enough pulses on the pipeline clock signal 516 in response to the activation of the start signal 514 such that data can sequence through each stage of the pipelined circuit and a computation is available to be read at an output 560 . in one embodiment , the pipeline control unit 504 generates the same number of pulses on the pipeline clock signal 516 as the number of stages in the pipelined circuit . a variety of techniques can be used to generate the series of pulses by the pipeline control unit 504 . for example , one embodiment of the pipeline control unit 504 includes a counter to track the number of pulses that are applied by the pipeline clock signal 516 . the counter can be reset in response to the start signal 514 , and the counter can increment to a predetermined count . while the counter is counting , the pipeline control unit 504 provides clock pulses over the pipeline clock signal 516 by , for example , coupling the clock signal 508 to the pipeline clock signal 516 . in another embodiment , a counter is preloaded in response to the start signal 514 and decrements down to zero to track the number of pulses that are applied by the pipeline clock signal 516 . while the counter decrementing , the pipeline control unit 504 couples the clock signal 508 to the pipeline clock signal 516 to generate the series of pulses . when the counter counts down to zero , the counter is disabled and the pulsing of the pipeline clock signal 516 stops . in another embodiment , the stages of the pipelined circuit receive a continuous 5 clock signal such as the clock signal 508 , and the pipeline control unit 504 generates control signals that selectively enable and disable the stages of the pipelined circuit by controlling an enable input in the registers of the pipelined circuit . the pipelined circuits and the pipeline control circuits disclosed herein can be fabricated in a broad variety of ways . in one embodiment , the circuits are integrated into dedicated hardware such as a custom application specific integrated circuit ( asic ), a field programmable gate array ( fpga ), a programmable logic device ( pld ), and the like . in one embodiment , the pipelined circuits , the pipeline control circuits , or both are integrated with a digital signal processor ( dsp ) core . various embodiments of the present invention have been described above . although this invention has been described with reference to these specific embodiments , the descriptions are intended to be illustrative of the invention and are not intended to be limiting . various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims .