text: fig1 shows an embodiment of an electronic device for cryptographic processing , which is for example a part of a smartcard . the electronic device comprises a number of units , i . e . a bus interface unit biu , a cache controller cc , a data cache dc , an instruction cache ic , a memory management unit mmu , a translation lookaside buffer tlb , a core pipeline cp , a coprocessor cop and a multiply / divide unit mdu . the various units , i . e . electronic circuits , of the electronic device are coupled via a connection device as indicated by the arrows . for example , the coprocessor cop is coupled to the core pipeline cp for receiving data as well as instructions from , and outputting data to the core pipeline cp . the bus interface unit biu is coupled to a data bus , not shown in fig1 , for receiving input data , and for sending output data . for example , the data received by the bus interface unit biu is data that has to be encrypted by the electronic device , and the encrypted data is subsequently sent via the bus interface unit biu to the data bus . in operation , the instructions required for the encryption algorithm are stored in the instruction cache ic and / or a main memory , not shown in fig1 . the core pipeline cp requests an instruction by sending a virtual memory address to the memory management unit mmu . this virtual memory address is translated into a physical memory address by the memory management unit mmu using the translation lookaside buffer tlb . via the translation lookaside buffer tlb , the memory management unit mmu determines whether this instruction is available in the instruction cache ic . in case the instruction is available in the instruction cache ic , the instruction is retrieved from the instruction cache ic and sent to the core pipeline cp . otherwise , the instruction must be fetched from the main memory , via the bus interface unit biu . the required instruction and data to be processed are sent to the core pipeline cp for processing . the core pipeline cp determines whether the multiply / divide unit mdu or coprocessor cop should be invoked in the processing . the result data are sent either to the data cache dc or to the main memory via the bus interface unit biu . in different embodiments , the electronic device may comprise a different number of units and / or units with a different functionality . for example , more coprocessors may be present for executing dedicated instructions , or no translation lookaside buffer is present . fig2 schematically shows the interface between the cache controller cc and the instruction cache ic . the cache controller cc comprises storage elements 201 and 203 , respectively , while the instruction cache comprises storage elements 205 and 207 , respectively . storage elements 201 and 205 are coupled via address and data bus 209 , whereas storage element 207 and 203 are coupled via data bus 211 . data busses 209 and 211 are , for example , 32 bit - wide data buses . in alternative embodiments a different connection device for coupling electronic circuits may be present , for example one or more direct wires or one bus combining busses 209 and 211 . the storage elements 201 - 207 can be latches , i . e . known circuits that pass data elements from their inputs to their outputs when the clock signal , not shown in fig2 , has a first value and hold the output data when the clock signal has a second value . alternatively , different circuits such as flip - flops can be applied , that hold data on an edge of a clock signal . on a clock signal , the data and address stored in storage element 201 of the cache controller cc is latched on the address and data bus 209 . on the next rising edge of the clock , the data and addresses are read into storage element 205 of the instruction cache ic . in case anyone would like to derive secret information from the electronic device , a probe is placed on the address and data bus 209 to monitor the data signal , i . e . the current and / or voltage of the signal , between the cache controller cc and the instruction cache ic . however , the addition of the probe on the address and data bus 209 will modify the capacitance of the address and data bus 209 and will therefore also change the transition of a signal over the address and data bus . referring to fig3 , two electronic circuits 301 and 303 are shown interconnected by a connection device 305 . in the upper part of fig3 a typical signal transition is shown as voltage versus time in case no probe is attached to the connection device 305 . in the lower part of fig3 a probe 307 is attached to connection device 305 for monitoring the flow of signals between electronic circuit 301 and 303 , and a typical effect of the presence of the probe on the signal transition is shown in the voltage versus time diagram . such an effect is to be expected due to the increase of the capacitance of the combined node 305 and probe 307 , resulting in a slower slew - rate and increased delay in time of the signal . in case the increase in capacitance by the probe 307 is sufficiently high to cause a measurable change in signal transition , this change in signal transition can be detected . fig4 shows a part of the cache controller cc comprising a propagation delay detection circuit 401 . the cache controller further comprises a storage element 403 and a dummy storage element 405 . the storage elements 403 and 405 are used for storing the first address bit to be sent to the instruction cache , not shown in fig4 . it is noted that address bits are also considered to be data bits causing data signals when transferred via a connection device . the address and data bus 407 is coupled to storage element 403 and via this bus the first address bit is sent to the cache controller . both the address and data bus 407 and the dummy storage element 405 are coupled to the propagation delay detection circuit 401 . the circuitry comprising storage elements 403 and 405 as well as the propagation delay detection circuit 401 is be repeated for each address and data bit to be sent via the bus 407 , for example a 32 bit - wide bus . in alternative embodiments , the dummy storage element 405 and detection circuit 401 are not repeated for every address and data bit to be sent via the bus 407 , i . e . not all connections of data bus 407 are monitored . in operation , on a clock signal 413 generated by a synchronous clock generator , not shown in fig4 , the first bit of an address is stored via connection 415 in both storage element 403 and dummy storage element 405 , by the cache controller cc . on a next clock signal 413 , the first bit of the address stored in storage element 403 is latched on the corresponding connection of the address and data bus 407 while the same first bit of the address stored in dummy storage element 405 is latched on the connection device 409 . the delay propagation detection circuit 401 samples the signal transition on the corresponding connection of bus 407 as a pair of values ( v 1 , v 2 ) representing the voltage level of the signal at two points in time . the delay propagation detection circuit 401 samples the signal transition on connection device 409 as well as a pair of values ( e 1 , e 2 ) representing the voltage level of the signal at the same two points in time . the pair of values ( v 1 , v 2 ) is compared to the pair of values ( e 1 , e 2 ) and if the pairs do not match then an alert signal 411 is generated by the delay propagation detection circuit 401 . the pair of values ( e 1 , e 2 ) is the reference signal used for comparison with the actual signal ( v 1 , v 2 ), and therefore the capacitance of the connection device 409 should be comparable to that of the connection of the address and data bus 407 via which the address bit is sent to the instruction cache ic . in a similar way , each delay propagation detection circuit corresponding to another bit of the address and data bits compares its measured pairs of values ( v 1 , v 2 ) and ( e 1 , e 2 ) and generates an alert signal in case these do not match . the alert signal outputs of the propagation delay detection circuits can be combined using a tree of or gates in order to generate one alert signal in case one or more of the individual propagation delay detection circuits generates an alert signal . the alert signal is used to power down the core pipeline cp , see fig1 , and so stopping all execution performed by the electronic device . powering down includes both completely switching off as well as putting a unit in some form of a sleep mode . in case a probe is attached to the address and data bus 407 the signal transition over the corresponding connection of the bus is affected , as indicated in fig3 . the points in time for sampling by the propagation delay detection circuit can be chosen such that the pair ( v 1 , v 2 ) is equal to logical ( 0 , 1 ) while that of the pair ( e 1 , e 2 ) is equal to logical ( 1 , 1 ) for delays of the signal transition exceeding the natural variation in the signal transition , which then activates the alert signal 411 . otherwise , both pairs ( v 1 , v 2 ) and ( e 1 , e 2 ) are equal to ( 1 , 1 ) and no alert signal is generated . fig5 shows an embodiment of the propagation delay detection circuit 401 , sampling the signal transition of a connection of address and data bus 407 and that of connection device 409 . the propagation delay detection circuit comprises a fine - tuned delay matcher 501 and a mutual exclusion element 503 , and it arbitrates between the two received signals , i . e . the reference signal corresponding to connection device 409 and the actual signal corresponding to data bus 407 . in case a probe is present to monitor the data bus 407 , the actual signal is delayed when compared to the reference signal and as a result the mutual exclusion element 503 allows the reference signal to propagate , setting the alert signal 411 . in case no probe is present , the actual signal should be allowed to propagate , in case of which the alert signal 411 is not set . in order to take natural variations in the transition of the actual signal into account , the dummy signal is delayed by the fine - tuned delay matcher 501 . the fine - tuned delay matcher 501 delays the dummy signal such that for normal variations in delay of the actual signal no alert signal is generated , whereas in other cases an alert signal is generated . fig6 shows an embodiment of the mutual exclusion element 503 , comprising nand gates 601 and 603 and logical inverters 605 and 607 . between two signal transitions , both the reference signal 609 and the actual signal 611 on the first input ports of nand gates 601 and 603 , respectively , are low . as a result , the signal on the second input ports of the nand gates 601 and 603 is high . in case the actual signal 611 goes high before the reference signal 609 goes high , the signal on the second input port of nand gate 601 goes low , and as a result the reference signal is blocked by nand gate 601 . the alert signal 613 remains low . in case the dummy signal 609 goes high before the actual signal 611 , the actual signal 611 is blocked by nand gate 603 and the alert signal 613 is set to high . in an alternative embodiment the pair ( e 1 , e 2 ), representing the reference signal , is obtained from simulations using a monte - carlo analysis of the signal transitions on the address and data bus 407 . the calculated reference signal can be stored in a memory of the propagation delay circuit and used for comparison with the samples from the signal transition on the address and data bus 407 . in a further alternative embodiment , a propagation delay circuit may be coupled to connection device between different units of the electronic device in order to prevent the retrieval of secret information from the device . referring to fig1 , a propagation delay circuit is coupled to a connection device between the cache controller cc and the data cache dc , for example . alternatively , propagation delay circuits may be coupled to connection devices between more than one pair of units , for example one coupled to the connection device between the cache controller cc and the instruction cache ic , as well one coupled to the connection device between the core pipeline cp and the coprocessor cop . in another further alternative embodiment , the transition of the signal is monitored by a slew - rate detection circuit . the slew - rate detection circuit measures the slope of the transition of the signal , which represents the slew - rate . referring to fig2 , the presence of a probe will also affect the slew - rate of a signal and by comparing the slew - rate of the actual signal and a reference signal , obtained either as a dummy signal or from monte - carlo simulations , it can be detected if the deviation between the slew - rate of the actual signal and the reference signal is larger that than expected from the natural variations in the signal transition . if the deviation is larger , an alert signal is generated . circuit implementations for slew - rate deviation circuits , as well as alternative circuit implementations for propagation delay circuits , are given in “ a digital bist for operational amplifiers embedded in mixed - signal circuits ”, i . rayane et al ., proceedings of the ieee vlsi test symposium , 1999 , page 304 - 310 . in yet another further alternative embodiment , the capacitance of the connection for address and / or data transfer is monitored . due to the presence of a probe the capacitance of the connection device will increase , and if the monitored value of the capacitance increases above a chosen threshold value , an alert signal is generated . alternatively , the monitored value of the capacitance is compared with a reference value for the capacitance , stored in a memory , and if the deviation between the monitored value and the reference value is above a chosen threshold , an alert signal is generated . the capacitance of the connection device may be monitored continuously , or alternatively the capacitance is monitored at certain points in time . circuits for on - chip capacitance measurement are described in “ a new method and test structure for easy determination of femto - farad on - chip capacitances in a mos process ”, laquai b . et al ., proceedings of the international conference on microelectronic test structures , 1992 , page 62 - 66 ; “ on - chip measurement of interconnect capacitances in a cmos process ”, khalkhal a ., girard p . and nouet , p ., proceedings ieee 1994 int . conference on microelectronic test structures , vol . 7 , 1994 , page 130 - 134 ; “ an on - chip coupling capacitance measurement technique ”, nair p . a . et al ., proceedings of the international conference on vlsi design , 2001 , page 495 - 499 . alternatively , the monitoring circuit of the electronic device monitors two or more properties related to the capacitance of the connection device , for example both the slew - rate as well as the propagation delay of the signal . the invention can be applied in both synchronous and asynchronous electronic devices . in a synchronous device , at every clock signal new data is clocked into the storage elements , giving rise to a large current peak , which is relatively easily detectable by means of differential power analysis , for example . in case of asynchronous systems , data is stored in a storage element if a corresponding electronic circuit has finished its processing . as a result , the currents peaks are reduced and more spread in time compared to a synchronous system . however , also for an asynchronous device secret information can still be derived using techniques such as differential power analysis . it should be noted that the above - mentioned embodiments illustrate rather than limit the invention , and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims . in the claims , any reference signs placed between parentheses shall not be construed as limiting the claim . the word “ comprising ” does not exclude the presence of elements or steps other than those listed in a claim . the word “ a ” or “ an ” preceding an element does not exclude the presence of a plurality of such elements . in the device claim enumerating several means , several of these means can be embodied by one and the same item of hardware . the mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage .