Computers, Hardware, Electronics, Computer Science, Cpu.
following, module equal(input logic [31:0] srca, writedata, output logic equalD); logic zero; always_comb begin zero = srca-writedata; if(zero==1'b0) equalD = 1'b1; else equalD = 1'b0; end endmodule I prepared instructions that contain beq to test the branch dependency handler, The instruction beq