Fpga, Elections, Engineering, Digital Signal Processing, Ece.
m_axis_fir_tvalid; wire [3:0] m_axis_fir_tkeep; wire [31:0] m_axis_fir_tdata; /* * 100Mhz (10ns) clock */ always begin clk = 1; #5; clk = 0; #5; end always begin reset = 1; #20; reset = 0; #50; reset = 1; #1000000; end always begin s_axis_fir_tvalid = 0; #100; s_axis_fir_tvalid = 1; #1000;