Accelerated Computing, Fpga, High Level Synthesis.
offset = slave #pragma HLS INTERFACE mode = m_axi port = input2 depth = 1024 bundle = \ gmem0 offset = slave #pragma HLS INTERFACE mode = s_axilite port = input1 bundle = control #pragma HLS INTERFACE mode = s_axilite port = input2 bundle = control The arguments of the top-level function are