Vlsi, Semiconductors, Electronics, Semiconductor Market, Semiconductor Technology.
gate are shorted, because of that PMOS is in saturation region. This turns on NMOS and connects the output of the cell to Vss. So, out is connected to logic 0 or Vss. Vd = Vg Vsd = Vsg Vsd > Vsg - Vth (Condition of saturation for PMOS) End Cap cell Issue: There are high chance to get damaging the