Digital, Electronics, Verilog, Hdl, Basic Logic Gates.
use reg to store the output values reg output_and,output_or,output_not; always @(a,b) begin //we will use a as the select line. //Use if-else: as we have only two possibiles either 0 or 1 if(a==1'b0) begin output_and = 1'b0; output_or = b; output_not = 1'b1; end //else block will be executed when