Verilog, Fpga, Macos, Big Sur, Getting Started.
$(PROJ)_logs.txt gtkwave: simulate open io_signals.vcd -a gtkwave scansion: simulate open io_signals.vcd -a Scansion clean: rm -rf $(PROJ).vvp io_signals.vcd vvp_logs.txt In the make file, you can modify the sources name corresponding to your sources. You can also modify in the section all: which