Fpga, Elections, Engineering, Digital Signal Processing, Ece.
state_reg <= sendSample6; end else begin cntr <= cntr + 1; state_reg <= sendSample5; end end sendSample6 : //6 begin s_axis_fir_tdata <= 16'h8000; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample7; end else begin cntr <= cntr + 1; state_reg <= sendSample6; end end sendSample7 :