Fpga, Elections, Engineering, Digital Signal Processing, Ece.
sendSample4 = 5'd5; parameter sendSample5 = 5'd6; parameter sendSample6 = 5'd7; parameter sendSample7 = 5'd8; /* This state machine generates a 200kHz sinusoid. */ always @ (posedge clk or posedge reset) begin if (reset == 1'b0) begin cntr <= 4'd0; s_axis_fir_tdata <= 16'd0; state_reg <= init; end