Programming, Electronics, Fpga.
begin c <= a xor b; end Behavioral; And we can change testbench.vhdl to use the XOR-gate. Something like this will work: my_xor_gate : xor_gate port map(a => xor_a_sig, b => xor_b_sig, c => xor_c_sig); process begin wait for my_delay; xor_a_sig <= '1'; wait for my_delay; xor_a_sig <= '0'; xor_b_sig