Digital, Electronics, Verilog, Hdl, Basic Logic Gates.
the compiler. Note: Since we have used 2:1 Multiplexer, there are two input lines and one select line. We will use one input variable as the select line to realize the basic logic gate. module realizemux21(a,b,output_and,output_or,output_not); input a,b; output output_and,output_or,output_not; //we