Software Development, Fpga Design, Hardware, Programming, IoT.
guess we're staying put? case (r_Curr_State) LOCKED: if (i_Coin) r_Next_State <= UNLOCKED; // Cha-ching! Freedom! UNLOCKED: if (i_Push) r_Next_State <= LOCKED; // Pushed back to square one. endcase end assign o_Locked = (r_Curr_State == LOCKED); // It's a lock! endmodule And then there’s VHDL’s