Accelerated Computing, Fpga, High Level Synthesis.
interfaces. This is done with the bundle option. #pragma HLS INTERFACE mode = m_axi port = input1 depth = 9216 bundle = \ gmem0 offset = slave #pragma HLS INTERFACE mode = m_axi port = input2 depth = 9216 bundle = \ gmem1 offset = slave In High-Level Synthesis (HLS), we adhere to a structure