Accelerated Computing, Fpga, High Level Synthesis.
one consumer. #pragma HLS DATAFLOW read_data(input1, input2, in1, in2); calc_square(in1, squares); add_ten(in2, sum); multiply(squares, sum, product); write_data(product, output) Automating the Build Workflow The workflow in the Vitis HLS IDE can be automated using a TCL script, specifying the