Fpga, Elections, Engineering, Digital Signal Processing, Ece.
else begin case (state_reg) init : //0 begin cntr <= 4'd0; s_axis_fir_tdata <= 16'h0000; state_reg <= sendSample0; end sendSample0 : //1 begin s_axis_fir_tdata <= 16'h0000; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample1; end else begin cntr <= cntr + 1; state_reg <=