Fpga, Accelerated Computing, High Level Synthesis, Hpc.
out_dat << ys[i][0] << ", " << ys[i][1] << ", " << ys[i][2] << std::endl; } return 0; } Plotting the CSimulation result we can see the attractor, this verifies the functional working of the accelerator. CoSimulation will verify the generated RTL and capture information about the average latency of