Verilog, Uart, Protocol, Electroni, Fpga.
+ 1; if(bit_count == 3'd7) begin state <= STOP; bit_count <= 0; rx_done_tick <= 0; end end else begin counter <= counter + 1; end STOP: if(counter == 4'd15) begin rx_done_tick <= 1; state <= IDLE; counter <= 0; end else begin counter <= counter + 1; end endcase end Here a clever shifting of bits