Image Processing, Vhdl, Verification, Hls, High Level Synthesis.
so that we can use it as an IP in Vivado. Here is the generated IP. What I intend to do now is to write a top module for this IP by which I can feed this IP serially with the UART module so that I can run it on my Arty 7 FPGA Board. Transmit data serially to FPGA using UART The figure below shows