Verilog, Uart, Protocol, Electroni, Fpga.
4'd7) begin rx_done_tick <= 0; state <= DATA0; counter <= 0; dout <= 0; end else begin counter <= counter + 1; end DATA0: if(counter == 4'd15) begin state <= DATA1; counter <= 0; dout[0] <= rx; end else begin counter <= counter + 1; end DATA1: if(counter == 4'd15) begin state <= DATA2; counter <=