Programming, Vhdl, Fpga, Cpu.
downto 0); signal s_adderOutput: unsigned(15 downto 0); signal s_pcInput: unsigned(15 downto 0); signal s_addr: unsigned(15 downto 0); begin The adder with the i_mode12K control input: -- adder with multiplexer for second operand (1, 2, K) s_adderOutput <= s_adderInput1 + s_PC; s_adderInput1 <=