Verilog, Processors, Engineering, Enjoy Writing, Tech.
language we use latency only for simulation purposes. Now we will go and see coding. module alu(DATA1, DATA2, RESULT, SELECT,ZERO); //initializing the inputs and outputs input [7:0] DATA1; input [7:0] DATA2; input [2:0] SELECT; output [7:0] RESULT; output ZERO; reg [7:0] RESULT; reg ZERO; reg [7:0]