Programming, Vhdl, Fpga, Cpu.
loading PC and IR process (i_clk) begin if rising_edge(i_clk) then if i_reset = '1' then s_PC <= (others => '0'); s_IR <= (others => '0'); else if i_loadPC = '1' then s_PC <= s_pcInput; end if; if i_loadIR = '1' then s_IR <= i_PMDATA; end if; end if; end if; end process; end Behavioral; You can