Programming, Vhdl, Fpga, Cpu.
0) ); end CtrlFetch; The device contains two registers (s_PC, s_IR) and a small number of internal signals: architecture Behavioral of CtrlFetch is -- registers signal s_PC: unsigned(15 downto 0); signal s_IR: unsigned(15 downto 0); -- asynchronous internal signals signal s_adderInput1: unsigned(15