Vlsi, Semiconductors, Electronics, Semiconductor Market, Semiconductor Technology.
high-tie cells, NMOS drain and gate are shorted, because of that NMOS is in saturation region. This turns on PMOS and connects the output of the cell to Vdd. So, out is connected to logic 1 or Vdd. Vd = Vg Vds = Vgs Vds > Vgs - Vth (Condition of saturation for NMOS) In low-tie cells, PMOS drain and