Programming, Fpga, Microprocessor.
detects an ALU operation in the DECODE phase, it enters the new ALU1 state. In ALU1, the contents of the two registers Rr and Rd addressed by bits 9 to 0 of the instruction register appear at the register file output and are fed into the op1 and op2 inputs of the ALU. In addition, bits 13 to 10 of