Hardware, Computer Architecture, Xilinx, Vivado, High Level Design.
added to unroll the inner loop for further performance improvements. These directives help Vitis HLS optimize the code for FPGA implementation. Test Bench File for this function: #include <iostream> #include "matrixmul.h" using namespace std; int main(int argc, char **argv) { mat_a_t in_mat_a[3][3]