Digital, Electronics, Verilog, Hdl, Basic Logic Gates.
a=1'b1 i.e., 1. else begin output_and = b; output_or = 1'b1; output_not = 1'b0; end end endmodule Our Design block is written, and it has to be verified by feeding the input values. And this can be done by writing Stimulus/Verification block also known as Testbench(tb). We provide the different