Fpga, Elections, Engineering, Digital Signal Processing, Ece.
cntr <= 4'd0; state_reg <= sendSample3; end else begin cntr <= cntr + 1; state_reg <= sendSample2; end end sendSample3 : //4 begin s_axis_fir_tdata <= 16'h5A7E; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample4; end else begin cntr <= cntr + 1; state_reg <= sendSample3; end end