Software Development, Fpga Design, Hardware, Programming, IoT.
Turnstile_Example is port ( i_Reset : in std_logic; i_Clk : in std_logic; i_Coin : in std_logic; i_Push : in std_logic; o_Locked : out std_logic ); end entity Turnstile_Example; architecture RTL of Turnstile_Example is type t_State is (LOCKED, UNLOCKED); signal r_Curr_State, r_Next_State : t_State;