Verilog, Processors, Engineering, Enjoy Writing, Tech.
function 3'b001: #2 RESULT = DATA1 + DATA2; //Add and Sub function 3'b010: #1 RESULT = DATA1 & DATA2; //AND and Sub function 3'b011: #1 RESULT = DATA1 | DATA2; //OR and Sub function //setting 1XX selection inputs.As there are reserved for future references it doesn’t matter //for the time being the