Verilog, Processors, Engineering, Enjoy Writing, Tech.
begin regFile [i] = 8'b00000000 ; end end //this always block runs of the positive edge of the clock and write to the register if write is ennable always@(posedge CLK) begin if(WRITE == 1'b1 && RESET == 1'b0) begin #2 regFile [INADDRESS] = IN; //this includes the write reg delay //$monitor($time,”