Fpga, Elections, Engineering, Digital Signal Processing, Ece.
sendSample4 : //5 begin s_axis_fir_tdata <= 16'h0000; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample5; end else begin cntr <= cntr + 1; state_reg <= sendSample4; end end sendSample5 : //6 begin s_axis_fir_tdata <= 16'hA582; if (cntr == wvfm_period) begin cntr <= 4'd0;