Verilog, Uart, Protocol, Electroni, Fpga.
DATA7; counter <= 0; dout[6] <= rx; end else begin counter <= counter + 1; end DATA7: if(counter == 4'd15) begin state <= IDLE; counter <= 0; dout[7] <= rx; rx_done_tick <= 1; end else begin counter <= counter + 1; end endcase end Now if you look closely you may have realised that all states from