Verilog, Processors, Engineering, Enjoy Writing, Tech.
%b”,regFile [INADDRESS]); end end //this is for reading the inputs from the registers //this part was modified after the lab 5 part 3 submission assign #2 OUT1 = regFile[OUT1ADDRESS]; assign #2 OUT2 = regFile[OUT2ADDRESS]; endmodule Now we have seen the design of a simple alu and register file