Programming, Electronics, Fpga.
clk_period/2; end process; process <= this process generates the values on a_sig and b_sig begin wait for clk_period; a_sig <= '1'; wait for clk_period; a_sig <= '0'; b_sig <= '1'; wait for clk_period; a_sig <= '1'; b_sig <= '0'; wait for clk_period; b_sig <= '1'; wait; end process; end Behavioral;