Vlsi, Semiconductors, Semiconductor Market, Semiconductor Technology, Electronics.
number of macro pins x Pitch of metal layer)/ two macros(D) (Total number of metal layer) Total spacing between = D + EndCap boundary + Well Tap boundary 5. Priority 5: At least one pair of metal layer tracks must be between two macros. This pair of tracks will be used as Vss and Vdd in the power