Verilog, Uart, Protocol, Electroni, Fpga.
begin case(state) IDLE: if(rx == 0 && counter == 4'd7) begin rx_done_tick <= 0; state <= DATA; counter <= 0; bit_count <= 0; dout <= 0; end else begin counter <= counter + 1; end DATA: if(counter == 4'd15) begin state <= DATA; dout <= {rx, dout[7:1]}; bit_count <= bit_count + 1; counter <= counter