Xilinx, Fpga, Verilog, Pynq, Embedded Systems.
instruction so that you know what exactly we are trying to do. We are saying that please connect the FPGA pin with the LD[0] in the design. If you remember we created a bus of width 4 for LD i.e [3:0] LD. In the XDC file, we will have to define each wire separately if and only if we want to connect