Fpga, Elections, Engineering, Digital Signal Processing, Ece.
== 1'b0) begin enable_fir <= 1'b0; buff_cnt <= 4'd15; in_sample <= in_sample; end else if (buff_cnt == 4'd15) begin buff_cnt <= 4'd0; enable_fir <= 1'b1; in_sample <= s_axis_fir_tdata; end else begin buff_cnt <= buff_cnt + 1; in_sample <= s_axis_fir_tdata; end end always @ (posedge clk) begin