Image Processing, Vhdl, Verification, Hls, High Level Synthesis.
Once the FPGA receives 5 bytes of data, it filters and transmits the 4 bytes of filtered data. For 25 bytes I expect 5 filtered data(20 bytes). In the figure below, we can see the results. I used Hterm serial terminal to transfer data between FPGA and my Host PC. In the figure below, you can see