Computers, Hardware, Electronics, Computer Science, Cpu.
will forward the MEM result to the EX stage of add $t0, $s0, $s1 as it uses $s0. This instruction is right after the lw , so a stall cycle is inserted between the ID and EX stages. A stall cycle is also inserted between the IF and ID stage of the add $t1, $s2, $s0 ADDI $s1 $zero 0x1 SW $s1