Programming, Electronics, Fpga.
'0'; signal c_sig : std_logic; constant my_delay : time := 1 ms; begin my_and_gate : and_gate port map (a => a_sig, b => b_sig, c => c_sig); process begin wait for my_delay; a_sig <= '1'; wait for my_delay; b_sig <= '1'; wait for my_delay; a_sig <= '0'; wait; end process; end peekaboo; The first