Digital, Electronics, Verilog, Hdl, Basic Logic Gates.
dut(a,b,output_and,output_or,output_not); initial begin //2 input values = 4 possibilities a = 1'b0; b=1'b0;#10 a = 1'b0; b=1'b1;#10 a = 1'b1; b=1'b0;#10 a = 1'b1; b=1'b1;#10 $finish; //$finish=exits the simulation end endmodule Congrats you have finally reached the end and Happy learning!