Computers, Hardware, Computer Science, Cpu, Electronics.
controls as BEQ $display("BNE"); end 6'b001000: controls <= 9'b101000000; // ADDI 6'b000010: controls <= 9'b000000100; // J default: controls <= 9'bxxxxxxxxx; // illegal op endcase endmodule The full Verilog code can be found in my Github repo. FPGAprojects/bne_cpu.sv at main ·