Verilog, Processors, Engineering, Enjoy Writing, Tech.
//initializing outputs output [7:0] OUT1; output [7:0] OUT2; //initializing register variables integer i; //creating the register array reg [7:0] regFile [0:7]; //resetting the registers if the reset is 1 as a level triggered input always@(*) if (RESET == 1) begin #2 for (i = 0; i < 8; i = i + 1)