Programming, Electronics, Fpga.
std_logic := '0'; signal c_sig : std_logic; constant clk_period : time := 1 ms; begin my_cxg : clocked_xor_gate port map (clk=>clk_sig, a => a_sig, b => b_sig, c => c_sig); process -- <= this process generates the clock begin clk_sig <= '1'; wait for clk_period/2; clk_sig <= '0'; wait for