Verilog, Processors, Engineering, Enjoy Writing, Tech.
output was set to 0 when the select is 1XX 3'b100: RESULT = RshiftResult; 3'b101: RESULT = 8'b00000000; 3'b110: RESULT = 8'b00000000; 3'b111: RESULT = 8'b00000000; endcase end // creating the ZERO bit using the alu result //modified part always@(RESULT) begin ZERO =