Programming, Electronics, Fpga.
<= '1'; wait for my_delay; xor_a_sig <= '1'; -- this line is interesting xor_b_sig <= '0'; wait for my_delay; xor_b_sig <= '1'; wait for my_delay; wait; end process; When we now simulate the testbench, everything works the way we would expect. But when one synthesizes the design and programs an