Verilog, Processors, Engineering, Enjoy Writing, Tech.
write data. We can implement it in Verilog like this. module reg_file(IN, OUT1, OUT2, INADDRESS, OUT1ADDRESS, OUT2ADDRESS, WRITE, CLK, RESET) ; //Initalizing inputs input [2:0] INADDRESS; input [2:0] OUT1ADDRESS; input [2:0] OUT2ADDRESS; input WRITE; input CLK; input RESET; input [7:0] IN;