Xilinx, Fpga, Verilog, Pynq, Embedded Systems.
the FPGA I/O. First Right Click on the output pin of the module → Create Port → OK (The default values are ok). Note: These names are also in the XDC file which defines which ports are connected directly with FPGA pins. Create Port — Defining the endpoint (port) for the LD. Similarly, do the same