Mojo, Fpga.
Clk_50MHz )begin Dly_Counter <= Dly_Counter + 1'b1; if(Dly_Counter >= 6_250_000) begin Dly_Counter <= 0; if(state) state<=0; else state<=1; end end always@(rMode or state )begin case(rMode) 2'b00: RLED_Output = 8'b00000000; 2'b01: RLED_Output = 8'b11111111; 2'b10: begin if(state) RLED_Output =