Vhdl, Digital Electronics.
3 * (6 + 15) = 63, fx <= reg1 + ai; fx <= reg1 + a1 = 63+ 2= 65 3rd clock transition (+ve) trigger: (clk’EVENT AND clk =’1') ELSE reg1 = x * (ai +reg1); reg1 <= x * (a1 + reg1) = 3 * (2 + 63) = 195, fx <= reg1 + ai; fx <= reg1 + a0 = 195+ 0 = 195 The polynomial performs as expected! Refinement