Accelerated Computing, Fpga, High Level Synthesis.
|Scalar(pass by value)|Register|AXI4-Lite (s_axilite) | |Array |Memory |AXI4 Memory Mapped (m_axi) | |Pointer to array |Memory |m_axi | |Pointer to scalar |Register|s_axilite | |Reference |Register|s_axilite | |hls::stream |Stream |AXI4-Stream (axis) | The pragmas can configure different parameters