Accelerated Computing, Fpga, High Level Synthesis.
of the interface like depth, bundle, etc. // AXI Master #pragma HLS INTERFACE mode = m_axi port = input1 depth = 1024 bundle = \ gmem0 offset = slave // AXILite Slave #pragma HLS INTERFACE mode = s_axilite port = input1 bundle = control The mode parameter specifies the communication protocol.