Accelerated Computing, Fpga, High Level Synthesis.
using Vitis HLS for designing an accelerator. Designing an accelerator using HLS First we start with a top function, establishing the contract for the module. void top_function(int *input1, int *input2, int *output) { #pragma HLS INTERFACE mode = m_axi port = input1 depth = 1024 bundle = \ gmem0