Vhdl, Uvvm, Bfm.
widths (let’s call it ST_AXILite_32). Here is the subtype declaration in the architecture declarative region: Declare a signal of that subtype (let’s call it axilite_if) axilite_if signal declaration Assign AXI4 individual signals to the axilite_if, to allow BFM calls to actually drive DUT signals