Accelerated Computing, Fpga, High Level Synthesis.
open_project -reset arth_prg set_top top_function add_files example.cpp add_files -tb test.cpp open_solution "solution" -flow_target vivado set_part {xcvu37p-fsvh2892-2L-e} create_clock -period 4 -name default # Simulation csim_design # Synth to Verilog/VHDL csynth_design # Cosimulation (RTL