Vlsi, Semiconductors, Verilog, Coding, Gui̇de.
Verilog recommends using non-blocking statements to model sequential circuits. •”<=” sign is used for assignment. module block_test; reg [1:0] a=2'b01, b=2'b10, c=2'b11; initial begin a<=2b00; b<=a; c<=b; // Non- Blocking Assignments Sdisplay(" a=%b\n, b=%b\n, c=%b\n", a,b,c); end endmodule OUTPUT: