Verilog, Uart, Protocol, Electroni, Fpga.
0; dout[1] <= rx; end else begin counter <= counter + 1; end DATA2: if(counter == 4'd15) begin state <= DATA3; counter <= 0; dout[2] <= rx; end else begin counter <= counter + 1; end DATA3: if(counter == 4'd15) begin state <= DATA4; counter <= 0; dout[3] <= rx; end else begin counter <= counter +