Mojo, Fpga.
IEEE.STD_LOGIC_1164.ALL; entity moving_led_1 is port (sh, lr,reset, clk: in std_logic; yout : out std_logic_vector(7 downto 0)); end moving_led_1; architecture beh of moving_led_1 is signal q : std_logic_vector(7 downto 0); signal sq : std_logic; component DIVIDER is port (CLK : in std_logic; Q :