Fpga, Elections, Engineering, Digital Signal Processing, Ece.
begin if (s_axis_fir_tlast == 1'b1) begin m_axis_fir_tlast <= 1'b1; end else begin m_axis_fir_tlast <= 1'b0; end end // 15-tap FIR reg enable_fir, enable_buff; reg [3:0] buff_cnt; reg signed [15:0] in_sample; reg signed [15:0] buff0, buff1, buff2, buff3, buff4, buff5, buff6, buff7, buff8, buff9,