Fpga, Elections, Engineering, Digital Signal Processing, Ece.
//6 begin s_axis_fir_tdata <= 16'hA582; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample0; end else begin cntr <= cntr + 1; state_reg <= sendSample7; end end endcase end end endmodule Under the simulation sources in the Sources window, set the testbench module as the top level