Software Development, Fpga Design, Hardware, Programming, IoT.
begin -- Current state register process (i_Clk, i_Reset) is begin if i_Reset = '1' then r_Curr_State <= LOCKED; -- Reset with flair! elsif rising_edge(i_Clk) then r_Curr_State <= r_Next_State; -- Decisions, decisions. end if; end process; -- Next state determination process (r_Curr_State, i_Coin,