Verilog, Uart, Protocol, Electroni, Fpga.
1; end DATA4: if(counter == 4'd15) begin state <= DATA5; counter <= 0; dout[4] <= rx; end else begin counter <= counter + 1; end DATA5: if(counter == 4'd15) begin state <= DATA6; counter <= 0; dout[5] <= rx; end else begin counter <= counter + 1; end DATA6: if(counter == 4'd15) begin state <=