Programming, Vhdl, Fpga, Cpu.
std_logic; i_loadIR: in std_logic; -- data path i_K: in unsigned(15 downto 0); i_A: in unsigned(15 downto 0); i_Z: in unsigned(15 downto 0); o_IR: out unsigned(15 downto 0); o_PMDATA: out unsigned(15 downto 0); -- memory interface o_PMADDR: out unsigned(15 downto 0); i_PMDATA: in unsigned(15 downto