Fpga, Elections, Engineering, Digital Signal Processing, Ece.
buff11 <= buff11; buff12 <= buff12; buff13 <= buff13; buff14 <= buff14; end end /* Multiply stage of FIR */ always @ (posedge clk) begin if (enable_fir == 1'b1) begin acc0 <= tap0 * buff0; acc1 <= tap1 * buff1; acc2 <= tap2 * buff2; acc3 <= tap3 * buff3; acc4 <= tap4 * buff4; acc5 <= tap5 * buff5;