Vhdl, Digital Electronics.
(clk’EVENT AND clk =’1') IF res = ‘1’ THEN reg1 =’0’: reg1 <= 0, ELSE reg1 = x * (ai +reg1); reg1 <= x * (a3 + reg1) = 3 * (5 + 0) = 15, fx <= reg1 + ai; fx <= reg1 + a2 = 15 + 6 = 21 2nd clock transition (+ve) trigger: (clk’EVENT AND clk =’1') ELSE reg1 = x * (ai +reg1); reg1 <= x * (a2 + reg1) =