Mojo, Fpga.
[1:0]rMode; reg [3:0] Counter; always@(negedge Rst_OnBoard) begin if(rMode == 0) rMode <= rMode+1; else if(rMode == 1) rMode <= rMode+1; else rMode <= 0; end always@(posedge Clk_50MHz) begin Dly_Counter <= Dly_Counter + 1'b1; if(Dly_Counter >= 6_250_000) begin Dly_Counter <= 0; if(Counter >= 13)