Fpga, Elections, Engineering, Digital Signal Processing, Ece.
sendSample0; end end sendSample1 : //2 begin s_axis_fir_tdata <= 16'h5A7E; if (cntr == wvfm_period) begin cntr <= 4'd0; state_reg <= sendSample2; end else begin cntr <= cntr + 1; state_reg <= sendSample1; end end sendSample2 : //3 begin s_axis_fir_tdata <= 16'h7FFF; if (cntr == wvfm_period) begin