Fpga, Accelerated Computing, High Level Synthesis, Hpc.
iterations we add a conditional block. The decor keyword in Dahlia is to add inline decorative pragmas/labels. In this case the decor adds a label to the loop, so the in the final Vitis HLS synthesis report we can identify it. def rk2(ys: state[16384], dt: float, N: ubit<32>) = { let h = dt; let