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CM-PLL Clock Module: Configuration

The CM-PLL circuits are configured by two elements:

DIP Switch

The figures below depict switch settings for the 6-position DIP switch on the CM-PLL. Refer to the photo below for the orientation and switch numbering used throughout this guide. Reference Clock Output

Switch 1 controls the reference clock output pin on the external header:

Reference Clock Source

Switches 2 and 3 control the reference clock mux:

Application Specific Configuration

Switches 4-6 are connected to FPGA I/O. These switches do not directly affect any circuits on the CM-PLL board. The user-supplied FPGA design should read these switch values to configure clock modes at boot.

Refer to the w3_clock_controller documentation for details on the default use of these switches in the reference designs for WARP v3.

AD9511 SPI Control

The CM-PLL is built around the ​Analog Devices AD9511 PLL. The AD9511 is configured primarily via its internal register bank. Individual registers can be read and written via an SPI interface. The CM-PLL design connects this SPI interface to dedicated FPGA I/O. The AD9511 default register values do not result in a valid configuration for the WARP v3 + CM-PLL hardware. The user FPGA design must integrate an SPI controller to configure the AD9511 registers at boot. Refer to the ​AD9511 datasheet for details on the device's register bank.

We provide the w3_clock_controller core to manage the AD9511 interface from a MicroBlaze processor. This core also implements a standalone state machine to load configuration data into the AD9511 immediately following FPGA configuration, before the host MicroBlaze processor boots. This allows the MicroBlaze (and its interconnect and peripherals) to use clocks generated by the CM-PLL. The pre-boot configuration loaded by the w3_clock_controller core can be customized by writing configuration data to the WARP v3 EEPROM. Refer to the w3_clock_controller user guide for details.

Last modified 4 years ago Last modified on Mar 1, 2015, 1:37:13 PM
