CLMUL instruction set
Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathematically, the instruction implements multiplication of polynomials over the  finite field  GF(2) where the bitstring  represents the polynomial . The CLMUL instruction also allows a more efficient implementation of the closely related multiplication of larger finite fields GF(2k) than the traditional instruction set.

One use of these instructions is to improve the speed of applications doing block cipher encryption in Galois/Counter Mode, which depends on finite field GF(2k) multiplication.  Another application is the fast calculation of CRC values, including those used to implement the LZ77 sliding window DEFLATE algorithm in zlib and pngcrush.

ARMv8 also has a version of CLMUL. SPARC calls their version XMULX, for "XOR multiplication".

New instructions
The instruction computes the 128-bit carry-less product of two 64-bit values.  The destination is a 128-bit XMM register.  The source may be another XMM register or memory.  An immediate operand specifies which halves of the 128-bit operands are multiplied.  Mnemonics specifying specific values of the immediate operand are also defined:

A EVEX vectorized version (VPCLMULQDQ) is seen in AVX-512.

CPUs with CLMUL instruction set
 Intel
 Westmere processor (March 2010).
 Sandy Bridge processor
 Ivy Bridge processor
 Haswell processor
 Broadwell processor (with increased throughput and lower latency)
 Skylake (and later) processor
 Goldmont processor
 AMD:
Jaguar-based processors and newer 
 Puma-based processors and newer 
 "Heavy Equipment" processors 
 Bulldozer-based processors 
 Piledriver-based processors 
 Steamroller-based processors 
 Excavator-based processors and newer 
 Zen processors
 Zen+ processors
 Zen2 (and later) processors

The presence of the CLMUL instruction set can be checked by testing one of the CPU feature bits.

See also
 Finite field arithmetic
 AES instruction set
 FMA3 instruction set
 FMA4 instruction set
 AVX instruction set

References

X86 architecture
X86 instructions