## Processor RAS 

In the unlikely case of a permanent core failure, each core can be individually replaced by one of the available spares. Core sparing is transparent to the operating system and applications. 

## Vector and Floating point Unit Enhancements 

Each core has two Vector and Floating point Units (VFU) that contain subunits, such as single instruction multiple data (SIMD), binary floating-point units (BFUs), and decimal floating-point units (DFUs) that are enhanced with z14 in different ways. 

z14 has a new decimal architecture with Vector Enhancements Facility and Vector Packed Decimal Facility for Data Access Accelerator. Vector Packed Decimal Facility introduces a set of instructions that perform operation on decimal type data that uses vector registers to improve performance. z14 offers up to 2x throughput of vector Binary Floating Point double precision operations and RSA/ECC acceleration (Long Multiply Support). 

By using the Vector Packed Decimal Facility that allows packed decimal operations to be performed in registers rather than memory (by using new fast mathematical computations), compilers, such as Enterprise COBOL for z/OS, V6.2, Enterprise PL/I for z/OS, V5.2, z/OS V2.3 XL C/C++, the COBOL optimizer, Automatic Binary Optimizer for z/OS, V1.3, and Java, are optimized on z14. 

Much of today’s commercial computing uses decimal floating point calculus, so on-core hardware decimal floating point units meet the requirements of business and user applications. This ability provides greater floating point execution throughput with improved performance and precision. 

## Hot line speculation avoidance 

The new mechanism allows full out-of-order and branch speculation for any instruction that hits in L1/L2 caches, and allows for out-of-order TLB-miss handling. For known hot cache lines, the implementation does not allow sending requests to L3 speculatively and Load Store Unit (LSU) rejects the request until the instruction is next to complete. 

## Guarded Storage Facility 

Also known as less-pausing garbage collection, Guarded Storage Facility is a new architecture that was introduced with z14 to enable enterprise scale Java applications to run without periodic pause for garbage collection on larger heaps. This facility improves Java performance by for reducing program pauses during Java Garbage Collection. 

## Instruction Execution Protection 

Instruction Execution Protection (IEP) is a new hardware function that was introduced with z14 that enables software, such as IBM Language Environmentfi, to mark certain memory regions (for example, a heap or stack) as non-executable to improve the security of programs that are running on IBM Z servers against stack-overflow or similar attacks. 

## Simultaneous multithreading 

z/Architecture introduced SMT support with z13, that allows simultaneous running of two threads (SMT) in the same zIIP or IFL core, which dynamically shares processor resources, such as execution units and caches. SMT in z13 allowed a more efficient use of the core and increased capacity because while one of the threads is waiting for a storage access (cache miss), the other thread that is running simultaneously in the core can use the shared resources rather than remain idle. 

