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GLYPH<SM590000> Ability to spare the PU core upon non-L2 cache/DIR Core Array delete. 

GLYPH<SM590000> Improved error thresholding on PU cores, which avoids continuous recovery. 

GLYPH<SM590000> Memory Control Unit (MCU) Cache Symbol ECC. 

GLYPH<SM590000> L1 and L1+; L2 protected by PU sparing. 

GLYPH<SM590000> PU Core mandatory address checking. 

GLYPH<SM590000> Redundant parity on error in RU bit to protect wordline (WL). 

GLYPH<SM590000> On-Chip Compression 

The On-Chip Compression, which is new to z15 is a major improvement from the zEDC cards. The on-chip compression offers an industry-leading, hardware-based acceleration for data compression with faster single thread performance. 

This On-Chip Compression capability replaces the zEDC Express adapter on the IBM z14 and earlier servers, whereby all date interchange remains compatible. 

With zEDC cards the throughput was 1GBps per feature with a maximum of 16 features. 

With On-Chip Compression the throughput is improved to 12 GBps per PU, which equates to 48 GBps per drawer and 240 GBps for a fully populated z15. 

The On-Chip Compression can be virtualized between all LPARs on the z15, whereas the zEDC feature was limited to 15 LPARs. 

The On-Chip Compression module implements DEFLATE/gzip/lzip algorithms and works in a synchronous mode in problem state and an asynchnous mode for larger operations under z/OS. 

For more information about IBM Integrated Accelerator for z Enterprise Data Compression (zEDC - On-Chip Compression) on z15 servers, see Appendix C, “IBM Integrated Accelerator for zEnterprise Data Compression” on page 503. 

z15 processor memory and cache structure are shown in Figure 9-2. 

<img src='content_image/1010515.jpg'>

