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next. 

In order to fully leverage the scalability of PCM and thus achieve the very high densities needed for Storage Class Memory (SCM), the most ideal implementation of PCM would be a cross-point array architecture, where each memory element in the array is directly connected to two orthogonal lines (Figure 5). In fact, a novel architec- ture has been proposed for such a direct cross-point mem- ory, in which PCM devices are switched not between SET and RESET, but between the RESET state and an over- RESET state (strongly RESET state)[157]. Even though these resistances may differ, the difference in read current would be too low to support rapid read. But because the threshold voltage varies between these two states, the de- vice state can be sensed by detecting whether a “read” voltage intermediate between these levels produces an electrical switching event. While this scheme does clev- erly avoid an access device, it has several serious issues. The margins between the read and the two threshold voltages are uncomfortably tight, and it would be diffi- cult to detect the breakdown without potentially heating up the cell, which means that reads must be treated as destructive. Even so, typical RESET resistances are still 

## B. Access circuitry 

low enough that the leakage through “half-selected” de- vices (those that share either the same bit-line or the same word-line as the “selected” device) would be quite high, thus limiting the maximum array size (and the ef- fective memory density) that could be built. Worst of all, the strong negative correlation between switching en- ergy and endurance (which will be discussed in detail in Section IV C) means that improving the sense margin by increasing the resistance (and thus the threshold voltage) of the over-RESET state will sharply reduce endurance. 

Thus the integration of PCM into an array architec- ture seems to require the use of an access device: either a diode[43, 158], a field-effect transistor[159, 160], or a bipolar junction transistor[44, 61]). The main role of this device is to minimize the leakage current that would oth- erwise arise from the non-selected cells in the array. As has been mentioned, the most important unknown for the success of PCM technology is whether this memory ac- cess device is able to provide sufficient current to RESET the PCM cell. While a diode can provide a current-to- cell size advantage over a planar transistor down to the 16nm node[161], the diode scheme is more vulnerable to write disturbs due to bipolar turn-on of nearest-neighbor cells[43]. A 5.8F 2 PCM diode cell has been demonstrated using a 90nm technology in which the diode was able to supply 1.8mA at 1.8V[43]. In comparison, a 90nm 10F 2 tri-gate FET could only supply approximately half as much current[43]. 

Although the raw footprint of the access device is of primary concern for memory density, other considera- tions can also come into play. Peripheral circuits, such as charge pumps to increase the voltage supply level or special read and write circuitry for MLC operation[162], reduce the portion of the chip that can be dedicated to memory devices (the “area efficiency” of the chip). In addition, the effective area per cell can grow because of additional vias or wiring that may be required within the memory array. For instance, given the high currents required for PCM programming, the voltage drop along metal bit- and word-lines can become significant, further reducing the power that can be delivered to the actual PCM cell. Thus splitting an array in half to reduce the maximum line length is attractive because it reduces the worst-case line loss, but detrimental because chip real- estate is now being used for redundant wiring rather than memory devices. Particularly problematic is the wiring that must sit under the PCM layer (such as common source lines, as well as the word-lines to transistor gates), since these lines must typically use high-resistance tung- sten or polysilicon. Because of the significant voltage losses in such lines, a via must often be introduced ev- ery few (e.g., 4 or 8) cells in order to strap this line to an overlying low-resistance copper line. This extra via immediately increases the effective footprint per mem- ory cell. Although copper cannot be introduced near the transistors, lest the CMOS devices become degraded, one solution would be to move the PCM devices higher up away from the silicon so that a layer of copper intercon- 

