be extensively used in PCM. Moreover, careful adapta- tion of existing codes as well as development of new cod- ing technologies suited to the physical characteristics of PCM could prove essential to unlocking much of its in- herent potential. 

Although there are many different types of coding, the most prevalent technique is Error Correcting Cod- ing (ECC), which allows for the detection and correc- tion of bit or symbol errors. Other coding techniques, called modulation codes, are designed to ensure that the patterns stored in memory are adapted to particular characteristics of the physical medium. Here we discuss how both of these approaches might be incorporated into PCM, with emphasis on ECC. 

ECC technology is now a standard feature in most storage and high-end computing systems, finding appli- cations in caches and buffers built using SRAM, main memory which generally uses DRAM, and hard disks, solid state drives and tape. The sophistication of the coding technology employed at each layer is often in- versely related to the proximity of a memory technology to the computing element. Much of this depends on the speed with which such coding can be implemented — close to the processor, a few extra nanoseconds spent on decoding may represent a significant (and unacceptable) delay, while far from the processor those same nanosec- onds represent a tiny rounding error. Processor caches tend to utilize regular or extended binary Hamming codes[237], which are arguably among the simplest codes that can be found in a pervasive manner. In contrast, main memory uses symbol-based codes such as Reed- Solomon codes[238], while disks use extremely sophis- ticated constructions involving error correcting codes, modulation codes, and advanced signal-detection and signal-processing technology. Since PCM holds promise both as a storage and as a memory device, it is reasonable to expect that it will draw coding and signal processing ideas from all of these technologies. 

To begin with a relatively simple example, consider a single-bit PCM cell. Here, a zero or a one correspond to a cell being SET or RESET, with the dramatic difference in resistance that accompanies these two states. Detec- tion of a zero or one can be accomplished by a simple “hard decision” based on a resistance threshold in be- tween these two resistance states based on read current. In PCM, one of the complications is that the measured re- sistance may change over time (short term drift, see Sec- tion V A) or with the instantaneous temperature of the cell, requiring a threshold that can be shifted with time and temperature. However, since the short-term drift is associated with the amorphous phase, if the SET state resistance is sufficiently dominated by the crystalline re- sistivity, then its resistance can be considered relatively independent of elapsed time. (Note that temperature- dependent thresholds can be produced by circuits de- signed around inherent temperature-dependent changes in the silicon underlying the PCM devices.) Thus for bi- nary storage, simple thresholding may prove adequate. 

Another solution is to have “pilot cells” that are known to be in the RESET and/or SET states. These pilot cells are programmed and read at the same time as the data-bearing cells in the same block, and thus can convey the information necessary to construct a suitable thresh- old for discriminating between a zero and a one. This is where device-to-device variability in this short-term drift proves to be the real issue. 

Errors in data that has been retrieved can have their origin in either a failure of the cell to switch to the de- sired state, an erroneous reading caused by noise, quan- tization or resistance fluctuations, or in the state of a cell switching over time. As discussed in Section IV C, the most likely such state-change event is the gradual transition from RESET to SET caused by crystallization of the phase change material. Although it is difficult to place a definite bound on the number of errors that these problem sources will cause, it is likely a safe statement to say that standard coding and decoding techniques such as Reed-Solomon codes based on the BCH (Bose, Ray- Chaudhuri, and Hocquenghem) code family[239–241] will be adequate to address these problems for a good number of applications. 

Having stated this, it is entirely possible that more so- phisticated error control coding techniques may find their way even in single bit PCM. These techniques would al- low a greater number of errors to be corrected for a given number of redundant (“check”) bits. The benefits of this include extending of the lifetime of PCM. In fact, as currently happens in Flash memory, the error rate of PCM devices can be expected to increase gradually dur- ing the lifetime of the memory, due to wearout mecha- nisms whose physics are currently not completely under- stood. A higher error correction capability would imply, in this case, a longer lifetime for the memory. Other benefits include the possibility of more relaxed engineer- ing requirements on a cell’s expected physical behavior, which could greatly accelerate the introduction of PCM in the marketplace. Examples of such relevant coding techniques include enhancing traditional algebraic cod- ing techniques with soft decoding capabilities, as well as using powerful coding mechanisms such as Low Den- sity Parity Check (LDPC) codes with iterative decoding methods[242]. The additional complexity demanded by these newer techniques may be well within reach given the significant progress that has been achieved both from the algorithmic and logic device technology fronts. 

The development of Multibit PCM is a significant engi- neering challenge, in many ways similar to the challenges faced by multibit NAND Flash manufacturers. However, unlike block–based Flash memories, single PCM bits can be erased and re-programmed. As discussed previously, due to variability in the response of different cells to the same input signal, as well as the smaller yet still signif- icant variability in the response of the same cell to re- peated applications of the same input signal, it appears impractical, at least presently, to attain a desired resis- tance level in a PCM cell by the application of a single 

