## 3.7 Logical partitioning 

## 3.7.1 Overview 

The logical partitioning features are described in this section. 

Logical partitioning is a function that is implemented by the PR/SM on z15. z15 can run in LPAR mode, or in DPM mode. DPM provides a GUI for PR/SM to manage I/O resources dynamically. 

PR/SM is aware of the processor drawer structure on z15 servers. However, LPARs do not feature this awareness. LPARs feature resources that are allocated to them from various physical resources. From a systems standpoint, LPARs have no control over these physical resources, but the PR/SM functions do have this control. 

PR/SM manages and optimizes allocation and the dispatching of work on the physical topology. Most physical topology that was handled by the operating systems is the responsibility of PR/SM. 

As described in 3.5.9, “Processor unit assignment” on page 125, the initial PU assignment is done during POR by using rules to optimize cache usage. This step is the “physical” step, where CPs, zIIPs, IFLs, ICFs, and SAPs are allocated on the processor drawers. 

When an LPAR is activated, PR/SM builds logical processors and allocates memory for the LPAR. 

PR/SM assigns all logical processors to one CPC drawer that are packed into chips of that drawer and cooperates with operating system use of HiperDispatch. 

New for z15, all processor types can be dynamically reassigned except IFPs. 

Memory allocation changed from the previous IBM Z servers. Partition memory is now allocated based on processor drawer affinity and striped across processor clusters. For more information, see “Memory allocation” on page 128. 

Logical processors are dispatched by PR/SM on physical processors. The assignment topology that is used by PR/SM to dispatch logical processors on physical PUs is also based on cache usage optimization. 

Processor drawers and logical node level assignments are more important because they optimize L4 cache usage. Therefore, logical processors from a specific LPAR are packed into a processor drawer as much as possible. 

PR/SM optimizes chip assignments within the assigned processor drawers (or drawers) to maximize L3 cache efficiency. Logical processors from an LPAR are dispatched on physical processors on the same PU chip as much as possible. The number of processors per chip (up to 12) matches the number of z/OS processor affinity queues that is used by HiperDispatch, which achieves optimal cache usage within an affinity logical node. 

PR/SM also tries to redispatch a logical processor on the same physical processor to optimize private cache (L1 and L2) usage. 

