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## 2.3.3 PU characterization 

In each CPC drawer, PUs can be characterized for client use. The characterized PUs can be used in general to run supported operating systems, such as z/OS, z/VM, and Linux on z Systems. They also can run specific workloads, such as Java, XML services, IPSec, and some Db2 workloads, or functions, such as Coupling Facility Control Code (CFCC). For more information about PU characterization, see 3.5, “Processor unit functions” on page 109. 

The maximum number of characterized PUs depends on the z14 model. Some PUs are characterized by the system as standard system assist processors (SAPs) to run the I/O processing. By default, least two spare PUs per system are available that are used to assume the function of a failed PU. The remaining installed PUs can be characterized for client use. A z14 model nomenclature includes a number that represents the maximum number of PUs that can be characterized for client use, as listed in Table 2-2. 

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## 2.3.4 System Controller chip 

The System Controller (SC) chip uses the CMOS 14nm SOI technology, with 17 layers of metal. It measures 25.3 x 27.5 mm, and has 9.7 billion transistors. Each node of the CPC drawer has one SC chip. 

Figure 2-17 on page 53 shows a schematic representation of the SC chip. Consider the following points: 

GLYPH<SM590000> X-Bus (CP-CP and CP-SC): Significant changes to allow SC to fit more X-Bus connections 

GLYPH<SM590000> A Bus (SC-SC off drawer): Minor changes to reflect protocol improvements and new system topology 

GLYPH<SM590000> 672 MB shared eDRAM L4 Cache 

GLYPH<SM590000> L4 Directory is built with eDRAM 

GLYPH<SM590000> New L4 Cache Management: 

– Ratio of L3 to L4 cache capacity is increasing 

– New on-drawer Cluster-to-Cluster (topology change) management 

