However, the path length that is associated with the operating system or subsystem can vary based on the following factors: 

GLYPH<SM590000> Competition with other tasks in the system for shared resources. As the total number of tasks grows, more instructions are needed to manage the resources. 

GLYPH<SM590000> The number of logical processors ( n-way ) of the image or LPAR. As the number of logical processors grows, more instructions are needed to manage resources that are serialized by latches and locks. 

## 12.3.2 Instruction complexity 

The type of instructions and the sequence in which they are run interacts with the design of a microprocessor to affect a performance component. This factor is defined as instruction complexity . The following design alternatives affect this component: 

GLYPH<SM590000> Cycle time (GHz) 

GLYPH<SM590000> Instruction architecture 

GLYPH<SM590000> Pipeline 

GLYPH<SM590000> Superscalar 

GLYPH<SM590000> Out-of-order execution 

GLYPH<SM590000> Branch prediction 

GLYPH<SM590000> Transaction Lookaside Buffer (TLB) 

GLYPH<SM590000> Transactional Execution (TX) 

GLYPH<SM590000> Single instruction multiple data instruction set (SIMD) 5 

GLYPH<SM590000> Simultaneous multithreading (SMT) 

Performance varies as workloads are moved between microprocessors with various designs. However, when on a processor, this component tends to be similar across all models of that processor. 

## 12.3.3 Memory hierarchy and memory nest 

The memory hierarchy  of a processor generally refers to the caches, data buses, and memory arrays that stage the instructions and data that must be run on the microprocessor to complete a transaction or job. 

The following design choices affect this component: 

GLYPH<SM590000> Cache size. 

GLYPH<SM590000> Latencies (sensitive to distance from the microprocessor). 

GLYPH<SM590000> Number of levels, the Modified, Exclusive, Shared, Invalid (MESI) protocol, controllers, switches, the number and bandwidth of data buses, and so on. 

Certain caches are private  to the microprocessor core, which means that only that microprocessor core can access them. Other caches are shared by multiple microprocessor cores. The term memory nest  for an IBM Z processor refers to the shared caches and memory along with the data buses that interconnect them. 

