with increasing layer thickness. Ultimately, this stress leads to the formation of cracks when the thickness is larger than about 400 nm [17]. Recently, improved methods for manufacturing low-loss thick Si$_{3}$N$_{4}$ waveguides have been introduced [17, 18], however, they still suffer from cracks in the Si$_{3}$N$_{4}$ layer [17], limiting the yield and reproducibility of device fabrication. 

In this paper we report on the fabrication of the first silicon nitride waveguides with thicknesses greater than 800 nm in a reproducibly crack-free manner. Instead of depositing a thick layer of Si$_{3}$N$_{4}$, followed by etching the waveguide cores from this layer, we first etch trenches in the silicon dioxide cladding that is formed by thermally oxidizing the top surface of the silicon substrate. The trenches are then filled with Si$_{3}$N$_{4}$ using LPCVD and the resulting waveguide cores are crack-free for depths of up to d = 1.2$_{m}$m. Note, that this method, in general, provides waveguides with an aspect ratio, w / d > 1 , unlike commonly used Si$_{3}$N$_{4}$ waveguides. As a result, the width of the waveguide core is the critical parameter that controls stress-induced cracks, which is related to the thickness of the Si$_{3}$N$_{4}$ layers. Waveguides fabricated in this way are referred to as TriPleX $^{TM}$[19, 20]. Details of this process are given in section 2. We then discuss in section 3 the characterization of several thick waveguides that are manufactured according to this novel procedure and end with a discussion and conclusion in section 4. 

## 2. Fabrication 

In this method, the waveguide devices are manufactured by filling predefined trenches with Si$_{3}$N$_{4}$ using LPCVD. The individual fabrication steps are shown in Fig. 2. In the first step, as shown in Fig. 2(a), reactive ion etching (RIE) is used to etch trenches with a width w and a depth d into the thermally oxidized top surface (oxide depth 8 $_{m}$m) of a silicon wafer. 

In the next step, a 250 nm thick layer of stoichiometric Si$_{3}$N$_{4}$ is deposited. During this deposition process, the Si$_{3}$N$_{4}$ layer grows equally thick from the sidewalls and bot- tom of the trenches, as illustrated in Fig. 2(b). To release stress from the material, the deposition is performed in steps and wafers are allowed to cool down to room tempera- ture between depositions [18]. As the deposition continues, the trench fills with Si$_{3}$N$_{4}$ 

