content_image/1005639.jpg
SMT use is functionally transparent to middleware and applications. No changes are required to run them in an SMT-enabled partition. 

## 3.4.2 Single-instruction multiple-data (enhanced for z14 ZR1) 

The z14 ZR1 superscalar processor has 32 vector registers and an instruction set architecture that includes a subset of 139 new instructions (known as SIMD) that were added to improve the efficiency of complex mathematical models and vector processing. These new instructions allow many operands to be processed with a single instruction. The SIMD instructions use the superscalar core to process operands in parallel. 

SIMD provides the next phase of enhancements of IBM Z analytics capability. The set of SIMD instructions is a type of data parallel computing and vector processing that can decrease the amount of code and accelerate code that handles integer, string, character, and floating point data types. The SIMD instructions improve performance of complex mathematical models and allow integration of business transactions and analytic workloads on IBM Z servers. 

The 32 vector registers feature 128 bits. The 139 new instructions include string operations, vector integer, and vector floating point operations. Each register contains multiple data elements of a fixed size. The following instructions code specifies which data formats to use and the size of the elements: 

GLYPH<SM590000> Byte (16 8-bit operands) 

GLYPH<SM590000> Halfword (eight 16-bit operands) 

GLYPH<SM590000> Word (four 32-bit operands) 

GLYPH<SM590000> Doubleword (two 64-bit operands) 

GLYPH<SM590000> Quadword (one 128-bit operand) 

The collection of elements in a register is called a vector . A single instruction operates on all of the elements in the register. Instructions include a non-destructive operand encoding that allows the addition of the register vector A and register vector B and stores the result in the register vector A (A = A + B). 

A schematic representation of a SIMD instruction with 16-byte size elements in each vector operand is shown in Figure 3-4. 

<img src='content_image/1005639.jpg'>

