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The RAIM design requires the addition of one memory channel that is dedicated for reliability, availability, and serviceability (RAS), as shown in Figure 2-17. 

<img src='content_image/985482.jpg'>

The fifth channel in each MCU enables memory to be implemented as a Redundant Array of Independent Memory (RAIM). RAIM features significant error detection and correction capabilities: bit, lane, DRAM, DIMM, socket, and complete memory channel failures can be detected and corrected, including many types of multiple failures. 

The RAIM design provides the following layers of memory recovery: 

GLYPH<SM590000> ECC with 90B/64B Reed Solomon code. 

GLYPH<SM590000> DRAM failure, with marking technology in which two DRAMs can be marked and no half sparing is needed. A call for replacement occurs on the third DRAM failure. 

GLYPH<SM590000> Lane failure with CRC retry, data-lane sparing, and clock-RAIM with lane sparing. 

GLYPH<SM590000> DIMM failure with CRC retry, data-lane sparing, and clock-RAIM with lane sparing. 

## 2.5.3 Memory configurations 

GLYPH<SM590000> DIMM controller ASIC failure. 

GLYPH<SM590000> Channel failure. 

Consider the following general plugging rules for memory: 

GLYPH<SM590000> 5, 10, 15, or 20 DIMMs are plugged, depending on the configuration (minimum 5 DIMMs: one bank must be installed) 

GLYPH<SM590000> No mixing of DRAM technology within a Memory Controller (that is, all DDR4) 

GLYPH<SM590000> Each five slot DIMM bank must have the same DIMM size 

GLYPH<SM590000> A mix of DIMM sizes can be used between different DIMM banks 

