## NEGATIVE TONE DEVELOPER FOR EXTREME ULTRAVIOLET LITHOGRAPHY 

This application is a non-provisional application of and claims benefit of U.S. Provisional Patent Application Ser. No. 62/511,758, filed May 26, 2017, the entire disclosure of which is incorporated herein by reference. 

Lithography processes are extensively utilized in inte› grated circuit (IC) manufacturing, where various IC patterns are transferred to a workpiece to form an IC device. A lithography process typically involves forming a resist layer over the workpiece, exposing the resist layer to patterned radiation, and developing the exposed resist layer, thereby forming a patterned resist layer. The patterned resist layer is used as a masking element during subsequent IC processing, such as an etching process, where a resist pattern of the patterned resist layer is transferred to the workpiece. A quality of the resist pattern directly impacts a quality of the IC device. As IC technologies continually progress towards smaller technology nodes (for example, down to 14 nano› meters, 10 nanometers, and below), resolution, roughness (for example, line edge roughness (LER) and/or line width roughness (LWR)), and/or contrast of the resist pattern has become critical. Multiple factors affect resolution, rough› ness, and/or contrast of the resist pattern, among which is a developer used for developing the exposed resist layer. Positive tone development (PTD) processes, which remove exposed portions of the resist layer, often use aqueous base developers, and negative tone development (NTD) pro› cesses, which remove unexposed portions of the resist layer, often use organic-based developers. Currently, though PTD processes provide sufficient resist contrast, PTD processes cause resist swelling issues that degrade LER and/or LWR. In contrast, though NTD processes typically minimize ( or even eliminate) resist swelling issues, NTD processes pro› vide insufficient resist contrast, degrading resolution. Accordingly, although existing lithography techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. 

## BRIEF DESCRIPTION OF THE DRAWINGS 

The present disclosure is best understood from the fol› lowing detailed description when read with the accompany› ing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbi› trarily increased or reduced for clarity of discussion. 

FIG. 1 is a flow chart of a lithography method for processing a workpiece according to various aspects of the present disclosure. 

FIGS. 2A-2E are fragmentary cross-sectional views of a workpiece, in portion or entirety, at various fabrication stages (such as those associated with the lithography method of FIG. 1) according to various aspects of the present disclosure. 

FIG. 3 includes a graph having EUV contrast curves for resist layers developed using different developers according to various aspects of the present disclosure. 

FIG. 4 is a simplified block diagram of a lithography system that can be implemented for exposing processes, such as those associated with the lithography method of FIG. 1, according to various aspects of the present disclosure. 

## BACKGROUND 

FIG. 5 is a simplified block diagram of a development system that can be implemented for developing processes, such as those associated with the lithography method of FIG. 1, according to various aspects of the present disclosure. 

The present disclosure relates generally to methods for manufacturing integrated circuit (IC) devices, and more particularly, to lithography techniques and/or lithography materials implemented during manufacturing ofIC devices. 

The following disclosure provides many different embodiments, or examples, for implementing different fea› tures. Reference numerals and/or letters may be repeated in the various examples described herein. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various disclosed embodi› ments and/or configurations. Further, specific examples of components and arrangements are described below to sim- plify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which addi› tional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. 

Further, spatially relative terms, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "up," "down," "top," "bottom," etc. as well as derivatives thereof ( e.g., "horizontally," "downwardly," "upwardly," etc.) are used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s). The spatially relative terms are intended to encompass different orientations than as depicted of a device (or system or apparatus) including the element(s) or feature(s), including orientations associated with the device’s use or operation. The apparatus may be otherwise oriented (rotated 90 degrees or at other orienta› tions) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 

A lithography process involves forming a resist layer over a workpiece and exposing the resist layer to patterned radiation. After exposed to the patterned radiation, the resist layer is developed in a developer (in other words, a chemical solution). The developer removes portions of the resist layer (for example, exposed portions of positive tone resist layers or unexposed portions of negative tone resist layers), thereby forming a patterned resist layer. The patterned resist layer is then often used as a masking element during a subsequent process, such as an etching process or an implan› tation process, to transfer a pattern in the patterned resist layer (referred to herein as a resist pattern) to the workpiece. Advanced lithography materials, such as chemically ampli› fied resist (CAR) materials, have been introduced to improve sensitivity of the resist layer to the radiation, thereby maximizing utilization of the radiation. Sensitivity (S) generally corresponds with an amount of incident radia› tion (amount of energy per unit area) required to produce sufficient chemical reactions to define a pattern in a resist 

## DETAILED DESCRIPTION 

