## PATTERN FORMING METHOD, METHOD FOR FORMING PATTERNED MASK, METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE 

## CROSS-REFERENCE TO RELATED APPLICATIONS 

[0001] This application is a Continuation Application of PCT Application No. PCT/JP2014/075681, filed Sep. 26, 2014, and based upon and claiming the benefit of priority from Japanese Patent Application No. 2013-205808, filed Sep. 30, 2013, the entire contents of all of which are incor› porated herein by reference. 

## BACKGROUND OF THE INVENTION 

[0002] 1. Field of the Invention 

[0003] The present invention relates to a pattern forming method, a method for forming a patterned mask including the pattern forming method, a method for manufacturing an elec› tronic device, and an electronic device, used in a step of manufacturing a semiconductor such as an IC, manufacture of a circuit board of liquid crystal or a thermal head, or a lithography step of other photofabrications. 

[0004] 2. Description of the Related Art 

[0005] In general, in the process of manufacturing a semi› conductor device, a step in which a film to be processed (for example, an insulating film or a conductive film) is formed on a substrate, then, an etching mask is formed on the upper layer thereof, and by etching, a pattern having a predetermined size and shape is formed in the film to be processed is performed multiple times. 

[0006] In the process of forming a pattern in a film to be processed, in general, a lithography technique in which a so-called exposure step or developing treatment step is per› formed using a photosensitive material called a photoresist (hereinafter, referred to as a "resist" in some cases) is used. 

[0007] On the other hand, in the field of semiconductor devices in recent years, demand for high density or high integration has increased, and in order to cope with that, a resist pattern has been also required to be refined. To refine a resist pattern, improvement of the lithography technique is needed, and thus, studies on an exposure light source, a resist material, or an exposure method have been in progress. As such a technique, use of anArF excimer laser as a light source, liquid immersion exposure, or the like is exemplified. How› ever, the line width of a resist pattern which can be manufac› tured by the above method is about 40 nm, and it is difficult to achieve a narrower line width than that. From such a back› ground, to achieve a pattern having higher resolution, various proposals have been made. 

[0008] For example, JP2010-66597 A discloses a method in which a spacer formed of a silicon oxide film is formed by a chemical vapor deposition method (hereinafter also referred to as a "CVD method") on the side wall of a photoresist pattern formed on a film to be processed, and using this as a mask, etching is performed, and as a result, a finer pattern is obtained. This method is performed in the following order. That is, a resist pattern is formed on a substrate including a film to be processed by a photoresist process. A silicon oxide film is formed on the resist pattern by a CVD method, and then, by removing the silicon oxide film of the space portion of the resist pattern and the silicon oxide film of the upper 

portion of the photoresist pattern, a spacer of the silicon oxide film is formed on the side wall of the photoresist pattern. Thereafter, by removing the resist pattern by etching, the spacer remains as a pattern. By processing a film to be pro› cessed using the spacer as an etching mask, a fine pattern is formed. 

[0009] However, since the CVD method used in this method is required to be performed under high temperature conditions, there is a problem in which the shape of the resist pattern is deformed when forming the silicon oxide film or the line width roughness (LWR) is increased. JP2010-66597A discloses a technique in which, to suppress deformation of the resist pattern at the time of forming the silicon oxide film or the increase in L WR, silane gas having at least one or more silazane bonds in one molecule is made to acted upon the resist pattern by a CVD method to oxidize silicon, and as a result, a silicon oxide film is formed. 

[001 OJ As a result of intensive studies, the present inventors found that, even when a silicon oxide film is formed on a resist pattern by the technique disclosed in JP2010-66597 A, adverse effects due to exposure of the resist pattern to a high temperature by the CVD method can not be sufficiently sup› pressed. That is, as a result of exposure of the resist pattern to a high temperature in forming the silicon oxide film by the CVD method, the resist pattern is reduced to become a skirt shape, and the side wall is inclined. It was found that a pattern formed of a silicon oxide film obtained by removing the resist pattern is inclined with respect to the substrate interface, and due to this, there is a problem in which pattern collapse is likely to occur. This problem has not yet been solved, by the related art including the above technique. 

[0011] An object of the present invention is to provide a pattern forming method which can be suitably used in forma› tion of a fine patterned mask in which the verticality at the substrate interface is excellent and the problem of pattern collapse is solved, a method for forming a patterned mask including the pattern forming method, a method for manu› facturing an electronic device, and an electronic device. 

[0012] An embodiment of the present invention is as fol› lows. 

[0013] [ 1] A pattern forming method including (I) a step of forming a first film by applying an active light-sensitive or radiation-sensitive resin composition which contains (A) a resin having a repeating unit having a group that is decom› posed by the action of an acid and generates a polar group and (B) a compound that generates an acid by irradiation with active light or radiation to a substrate, (II) a step of exposing the first film, (III) a step of forming a line-and-space pattern by developing the exposed first film, and (IV) a step of coating the line-and-space pattern with a second film, in which the top width of a line pattern of the line-and-space pattern formed in Step (III) is larger than the bottom width thereof. 

[0014] [2] The pattern forming method according to [1], in which a top width/bottom width which is a ratio of the top width to the bottom width of the line pattern formed in Step (III) is 1.01 to 1.50. 

[0015] [3] The pattern forming method according to [1], in which a top width/bottom width which is a ratio of the top width to the bottom width of the line pattern formed in Step (III) is 1.05 to 1.30. 

## SUMMARY OF THE INVENTION 

