content_image/973233.jpg
Two threads (A and B) running on the same processor core on different pipeline stages and sharing the core resources is shown in Figure 3-6. 

<img src='content_image/973233.jpg'>

The use of SMT provides more efficient use of the processors’ resources and helps address memory latency, which results in overall throughput gains. The active thread shares core resources in space, such as data and instruction caches, TLBs, branch history tables, and, in time, pipeline slots, execution units, and address translators. 

Although SMT increases the processing capacity, the performance in some cases might be superior if a single thread is used. Enhanced hardware monitoring supports measurement through CPUMF for thread usage and capacity. 

For workloads that need maximum thread speed, the partition’s SMT mode can be turned off. For workloads that need more throughput to decrease the dispatch queue size, the partition’s SMT mode can be turned on. 

SMT use is functionally transparent to middleware and applications, and no changes are required to run them in an SMT-enabled partition. 

## 3.4.2 Single-instruction multiple-data 

The z15 superscalar processor has 32 vector registers and an instruction set architecture that includes a subset of instructions (known as SIMD) that were added to improve the efficiency of complex mathematical models and vector processing. These new instructions allow a larger number of operands to be processed with a single instruction. The SIMD instructions use the superscalar core to process operands in parallel. 

