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the large SRAM cell size, even if a large access device is used for the PCM cell, SRAM performance is hard to match. The performance limiter for PCM is the SET speed, which in turn depends on the crystallization speed of the phase change material. As will be described in de- tail in Section II B, while some researchers have demon- strated the use of SET pulses shorter than 10ns[33–36], most of the realistically large array demonstrations tend to use SET pulses that range from roughly 50 to 500ns in length[53]. 

In any case, the most stringent requirement for any emerging memory technology that seeks to replace SRAM is endurance. For all practical purposes, the read/write endurance of SRAM is infinite. While read endurance is not a likely problem for PCM, the required write endurance for SRAM replacement is probably 10 18 — out of reach for nearly all NVM technologies. Stor- ing data semi-permanently with PCM and most other NVM technologies involves some form of “brute force” that alters an easily observable material characteristic of the memory device. For PCM, this “brute force” is the melt-quench RESET operation, and at such elevated temperatures, it has been shown that the constituent atoms of a phase change material will tend to migrate over time[40, 54], as discussed in Sections IV D and IV C. 

Since non-volatility is not a requirement for SRAM ap- plications, one might be able to trade some data reten- tion for improved endurance. Some remote evidence of this trade-off has been demonstrated by showing a strong correlation between the total energy in the RESET pulse and the resulting PCM endurance[40]. The best-case en- durance, achieved for the lowest-energy RESET pulses, was 10 12 SET–RESET cycles[40]. Yet this is still 6 or- ders of magnitude away from the target specification for SRAM. 

DRAM is used in a more diversified set of applications than SRAM. Most of the characteristics discussed above for the replacement of SRAM also apply to the replace- ment of DRAM, although in most cases the specifications are slightly relaxed. Access times of tens of nanoseconds would be acceptable for most computer and consumer electronics applications of DRAM. For embedded DRAM used as video RAM and L3 cache[55], however, an access time of 10 nanoseconds or less is required. As for write endurance, the requirement can be estimated using the following equation[52]: 

where E is endurance, T$_{life}$ is the life expectancy of the system, B is memory bandwidth, α is wear-leveling ef- ficiency, and C is the system memory capacity. As- suming a typical server with a ten year life expectancy, 1 GB/sec bandwidth, 10% wear-leveling efficiency and 

## 2. PCM as DRAM 

<img src='content_image/428738.jpg'>

16 GB capacity, the endurance requirement is approxi- mately 2 × 10 8 — well within the reach of PCM[44, 56]. 

There is also a power argument to be made when dis- cussing PCM as a potential DRAM replacement. This might seem to be a difficult case to make for a tech- nology for which every write cycle involves heating to temperatures ranging from 400 to 700 degrees Celsius. However, DRAM turns out to be a fairly power-hungry technology. This is not due to its periodic refresh, how- ever, which takes place only infrequently, and is not too strongly related to the underlying physical storage mech- anism of charging up a local capacitor. Instead, power inefficiency in DRAM is due to the simultaneous address- ing of multiple banks within the chip. For every bit that passes into or out of a DRAM chip, 8 or even 16 devices are being internally accessed (read and then re- written), somewhat as if your librarian knocked an entire row of books onto the floor each time you asked for a book. Low-power DRAM intended for mobile, battery- powered applications tends to have lower performance, although some developments have been made that can combine high performance with low power[57]. However, the inherent need to re-write after each read access is un- avoidable for a volatile memory like DRAM. Thus sim- ply by being non-volatile, PCM could potentially offer a lower-power alternative to DRAM, despite the inherently power-hungry nature of PCM write operations. 

For stand-alone memories, cost is directly proportional to memory cell size. State of the art DRAM cells oc- cupy 6F 2 in chip area. Thus for PCM to compete in the DRAM arena, PCM cell size would need to be this size or smaller with comparable “area efficiency (the frac- tion of the chip area dedicated to memory devices rather than to peripheral circuitry). Fortunately, such small cell sizes have already been demonstrated using a diode select device[56]. PCM also competes favorably with DRAM in terms of forward scaling into future generations, as DRAM developers are quickly hitting various scaling lim- its associated with storage interference, device leakage, and challenges in integrating high aspect-ratio capaci- tors in tight spaces. Currently, DRAM has fallen behind NAND Flash and standard CMOS logic technologies in terms of scaling to the 45nm technology node and prepa- ration for the 32nm node. However, DRAM is a proven, reliable technology that has been employed in modern computers since the early 1970s. It would be a long jour- ney to displace such a stable technology. 

There are two kinds of Flash memories, NOR and NAND. In (common-source) NOR memory architectures, each cell in a two-dimensional (2D) array is directly con- nected to its word-line and bit-line input lines (with the source electrode of each cell sharing a common ground), whereas in NAND memory architectures, small blocks of cells are connected in series between a high input sig- 

## 3. PCM as Flash 

