GLYPH<SM590000> Global Pause function frame (as described in the IEEE 802.3x standard) should be enabled 

GLYPH<SM590000> Priority Flow Control (PFC) disabled 

GLYPH<SM590000> No firewalls, no routing 

IBM provides the SMC Applicability Tool (SMCAT) that helps determine the potential gains of using SMC-R in an environment (see 2.6.5, “Shared Memory Communi cations Applicability Tool” on page 13). 

With z14 ZR1, the new 10GbE RoCE Express2 feature is available. This feature provides increased virtualization (sharing) capabilities. For more information, see IBM z14 Model ZR1Technical Guide , SG24-8651. 

RoCE Express features port configuration:  Consider the following points: 

GLYPH<SM590000> For 10GbE RoCE Express2 feature (FC 0412), the port number is now configured with the FID number in HCD (or IOCDS) and Port number must  be configured ( no default exists ). 

GLYPH<SM590000> Port number for 10GbE RoCE Express (FC 0411) is configured in z/OS TCP/IP profile and does not change. 

When defining a FID in the TCP/IP profile for 10GbE RoCE Express2 (FC 0412), the port number is no longer applicable. 

When preparing to deploy the RoCE Express features, consider the following items: 

GLYPH<SM590000> The RoCE Express features are “Native” PCIe features; therefore, the following configuration items must be provided: 

– Function ID 

– Type 

–P C H I D 

– Virtual Function ID (VF) 

– Port number 

GLYPH<SM590000> Determine which LPARs are to be shared by one 10GbE RoCE Express port. 

GLYPH<SM590000> Assign the VFs between the sharing LPARs. 

For more configuration information, see 15.2.3, “Defining a RoCE-2  PCIe function” on page 375. 

For 10GbE RoCE Express2 feature management information, see 10.4.4, “SMC-R Management” on page 259. 

## Consider Native PCIe feature Plugging and Resource Groups 

The native PCIe feature support is provided by Resource Group (RG) code running on the integrated firmware processor (IFP). For resilience, four independent RGs are always on the system that share the IFP. For high availability purposes, always use at least two PCIe features located in different RGs, as shown in Figure 2-4. 

