SiO$_{2}$ hard mask and e-beam lithography (HSQ resist), Yoon et al[186] reported that using the Cl$_{2}$/Ar chem- istry to etch the GST resulted in undercut and col- lapse of small GST features due to the isotropic com- ponent of the etching. By switching to a TiN hard mask process and using a CF$_{4}$/Ar chemistry, they were able to successfully pattern sub-100nm features in the GST. Joseph and colleagues[155] developed etch processes to pattern small features in N-doped GST films deposited on and capped with TiN. After using trimming pro- cesses to shrink the critical dimension (CD) of 248nm photolithography-patterned resist down to 100nm, ICP RIE in a Ar/Cl$_{2}$/CHF$_{3}$ gas mixture was used to first etch the TiN and then the N-GST. The authors pointed to the importance of carefully choosing the amount of Cl$_{2}$ so as to minimize undercut and obtain anisotropic profiles. 

In the same work [155], the authors also reported the presence of a uniform 10nm thick damaged layer on all plasma-exposed surfaces of the N-GST, suggesting that the material modification was chemically driven and not enhanced by ion bombardment. TEM-EELS and EDS analysis were used to show that the damaged layer had depletion of Sb and/or Te along with potential oxidation. Depth profile XPS analysis on blanket films subjected to etch (and etch followed by a strip process in an oxygen plasma) revealed selective loss of N and metallic Sb, and increased amount of Ge oxide. Finally, they also showed that the damaged layer could be removed selectively to the undamaged N-GST. 

Chemical mechanical polishing (CMP) is now a ubiqui- tous process in CMOS technology, especially in the Back- End-Of-the-Line (BEOL) flow. It enables the formation of inlaid, or ‘damascene,’ structures that are used in cop- per interconnect fabrication[191]. Such structures are created by first forming a hole (or trench) in a dielectric, then filling the hole, usually with a metal, followed by CMP to planarize the metal with the surrounding dielec- tric. Thus CMP allows patterning of the metal without needing an explicit metal etching step. There have been a number of publications on the CMP of phase change materials such as GST. 

Liu and coworkers[192] made arrays of damascene PCM cells using CMP process. SEM and EDS were used to verify that the GST was properly filled in the contact holes and that the material composition of the GST was not changed by the CMP process. DC current sweeps on fabricated cells showed successful switching from the high to low resistance state. 

Zhong et al[193] used CMP to fabricate damascene- type PCM cells. An alkaline slurry was used to polish GST deposited into 300nm wide vias. AFM measure- ments confirmed that a very smooth (0.8nm rms rough- ness) surface was obtained as a result of the CMP. A thin 

## 3. Chemical-mechanical polishing 

TiN layer was placed between the top surface of the GST and the top electrode. The programming endurance of such devices was an order of magnitude better than de- vices built without CMP. In addition, SET and RESET state resistance fluctuations along the cycling sequence were greatly reduced in the CMP-processed devices. The authors attributed this to the smooth surface and good quality TiN/GST interface leading to lower and more uniform contact resistance. They also suggested that bet- ter confinement of Joule heating and enhanced heat flux in the damascene structure was responsible for more uni- form temperature distribution across the GST and thus more homogeneous material composition distribution as the cycling progressed. 

The effect of adding oxidants such as H$_{2}$O$_{2}$ to the GST CMP slurry was studied by Zhong et al[194]. This study showed that while CMP of GST in a pure acidic silica slurry resulted in a rough surface with microscratches, the addition of 2 wt % H$_{2}$O$_{2}$ allowed them to obtain a smooth surface that was free of damage. XPS analysis on an unpolished GST sample dipped into the oxidant for 10 min showed that the surface was oxidized. Though the component elements were oxidized by different amounts, i.e. Ge > Sb > Te, the CMP process was believed to be able to remove all of these oxides. The authors suggest that the GST CMP mechanism is similar to that of met- als, i.e. oxidation followed by removal of this oxide due to friction with the abrasives in the slurry. The same group also compared ‘RIE’ cleaning in an Ar plasma post-CMP of GST with conventional ultrasonic cleaning[195]. An alkaline silica slurry was used to polish GST into sub- micron contact holes. AFM measurements showed that low surface roughness (0.64nm rms) was obtained after the CMP and RIE cleaning. DC I-V sweep measurements on fabricated devices also showed a significant reduction in the threshold switching voltage as a result of the RIE cleaning method. 

Lee et al[156] used CMP of GST in their demonstra- tion of a scalable confined PCM cell concept. CVD GST deposited into high aspect-ratio 50 nm diameter contact holes was planarized by CMP, thus fully con- fining the phase change material in the contact. SEM images showed that the GST CMP was successful with no scratches, excessive dishing, or void formation in the GST. Electrical tests on these devices showed low RE- SET currents and good cycling endurance. 

A number of cell failures observed in fully integrated PCM chips have been attributed to process-related dam- age. Both the phase change material itself as well as its interfaces with the top and bottom electrodes are suscep- tible to degradation as a result of steps in the integration flow. 

Lee et al[196] introduced suitable interface cleaning processes in order to obtain good contact resistance in 

## 4. Process-induced damage 

