COP400
The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum. Program memory consists of a 512, 1024, or 2048 x 8 ROM. ROM bytes may be program instructions, program data, or jump address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into pages of 64 bytes each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must sometimes be thought of as organized into blocks of 256 bytes. Data memory consists of a 32, 64, or 128 x 4 RAM, organized as several data registers of 16 4-bit digits. RAM addressing is implemented by the 6 or 7-bit B register used as a pointer. The B register's upper 2 or 3 bits (Br) select one of 4 or 8 data registers and lower 4 bits (Bd) select one of 16 4-bit digits in the selected data register. The 4-bit contents of the RAM digit pointed to by the B register are usually loaded into, exchanged with, or operate on the A register. The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 x 8) and RAM (128 x 4). Family members with only 512 or 1024 bytes of ROM will have only a 9 or 10 bit PC. Those with 64 or 32 locations of RAM will have only a 2 bit Br register. Some low end family members omit the SC stack register. The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register. A 4-bit ALU performs the arithmetic and logic functions, storing results in A. ASC and CASC operations output a carry to the 1-bit C register, most often employed to indicate arithmetic overflow. All ROM addressing is accomplished via the 9, 10, or 11-bit PC register. Its binary value selects one of the bytes contained in ROM, usually the next program instruction. The value of PC is automatically incremented by 1 prior to the execution of the current instruction to point to the next sequential ROM location, unless the current instruction is a transfer of control instruction. In the latter case, PC is loaded with the appropriate non-sequential value to implement the transfer of control operation. The PC automatically rolls over to point to the next 64 byte page or 256 byte block of program memory. The upper 1, 2, or 3 bits of PC are also used in the JID and LQID instructions. Three levels of subroutine are implemented by the subroutine save registers, SA, SB, and SC, providing a last-in, first-out (LIFO) hardware subroutine stack. Some implementations do not have a SC. There are no port numbers or memory addresses associated with the COP400 I/O devices. All the physical I/O registers and ports are referenced by the COP400 assembly language directly by name. Nearly all COP400 family devices implement the following: There are a few high end members of the COP400 family such as the COP440 and COP2440 that have 40-pins. These have additional registers and ports: The COP400 family is designed to have very compact code. The most frequently used instructions are one byte. In some cases there are special one-byte forms of two byte instructions. Some features that can be used to make object code more compact are: This example code demonstrates several of the space saving features on the instruction set: All COP400 devices that have 28 pins or more support a single interrupt. The IN 1 line is used as the interrupt input. Interrupt is enabled by setting bit 1 of the EN register to 1 with a LEI instruction. In response to low-going pulse at least two instruction cycles long on IN 1, all transfer of control instructions such as JP are completed and all sequential LBI instructions are executed. The PC is then pushed on the subroutine stack and control is transferred to the interrupt handler at address 0xFF. No subroutines may be called in the interrupt service routine. Although the majority of COP400 devices were targeted at low-end applications, several extensions to the architecture were created to address more demanding applications. Dual CPU, a deeper stack in RAM, and larger address spaces were added to some devices by 1985. “Dual CPU” versions of the COP400 were announced by National Semiconductor in 1981. These single-chip devices contain two ostensibly independent CPUs that share instructions, memory, and most IO devices. In reality, the CPUs are not fully independent and share hardware resources similar to Intel processors with Hyper-Threading Technology (HTT). Like HTT, the dual CPU version works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources such as ALU, buses, and memory. Separate architectural states for each of the two virtual processors is established with duplicated A (accumulators), B (pointer) registers, C (carry flags), N (stack pointers), and PC (program counters). When the reset is deasserted, both processors start at location 0 which contains a CLRA instruction, then one processor jumps to location 401 (hex) followed an instruction cycle later by the second processor executing location 1. The processors will then alternately execute one byte of code each. At maximum clock frequency, the instruction execution time (single byte instruction) for each processor is 4 microseconds, hence, the instruction cycle time for either processor is twice that amount, 8 microseconds. Some dual CPU versions include the 40 pin COP2440N, the 28 pin COP2441N, and the 24 pin COP2442N. Earlier COP400 devices included a two or three level dedicated hardware return stack. Later devices such as the COP440 feature a 4-level return stack implemented with a 2-bit stack pointer and RAM. Dual CPU versions have two separate 4-level return stacks implemented with a two 2-bit stack pointers and two different RAM areas. The basic COP400 instruction set supports ROM addresses of up to 11-bits (2,048 bytes), while data addresses are 7-bits maximum (128 locations). The so-called group 4 devices extended the memory limit by adding three-byte JMP, JSR, and LBI instructions with more address bits. These support ROM addresses of 15-bits maximum (32,768 bytes), while data addresses are 9-bit maximum (512 locations). Devices that support these instructions include COP408, COP484, COP485, C0P409. It is unclear whether any of these group 4 devices were produced. There is an open-source MAME emulator for the COP400 family and several hand held games and specialty calculators.
CPU registers
COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. The COP400 family offered several memory and pinout configurations.