 In an absolutely unprecedented move, Intel has given me access to the engineers in their SOC validation lab. Wow, that is so cool. I absolutely love it. Okay, gotta go, bye. This is an opportunity to talk to some of the smartest people in the world. So I immediately did what anyone would do. I asked them, what came first, the chicken or the egg? That's simple. You must build both a chicken and an egg in parallel to make sure they're compatible with each other. An unconventional answer, but one that makes sense when you consider the cutting edge work that they do inside these walls. Take PCI express gen five, for example. How can you build a compatible CPU and motherboard when there are no devices to test them with? Well, you create one from scratch. So cool. Just like I created the segue to our sponsor. I fix it. For repairs on the go, I fix it has you covered. Find out more about the ultra portable Minnow and Moray sets and how they can make your repairs easier at the end of the video. I was so blown away by the insane gear that they have in the validation lab. When I was shooting my general tour of the Israel development center, that I immediately canceled my return flight so that I could come back another day and get you guys a closer look at it. This lab's goal is twofold. First, they need to test every possible function of the SOC from logic to memory to integrated GPU to connectivity. And second, they need to test at scale to ensure that their results are gonna be applicable across thousands, hundreds of thousands, or even millions of units of processors. Because it's the nature of the silicon business that there's gonna be a spectrum of behavior from the silicon parts. And you've got to test it scale to ensure that this whole spectrum is validated. That's why this place is absolutely packed to the gills with test benches. Most of the ones we're looking at in here have the same core components. A 12th gen Alder Lake processor on top of one of Intel's RVP or reference validation platform motherboards, which man, these things include some really cool functionality for like remote control and testing and all kinds of stuff. I'm actually planning another followup video focusing just on this bad boy, including a look at the liquid nitrogen cool board that they've got in the overclocking lab. So get subscribed to make sure you don't miss it. Beyond the base platform though, there is a broad spectrum of different functions that the lab might want to look at that require different specialized equipment. So let's start over here. PCI express gen five is one of the key selling points of 12th gen. And Intel knew going into it that they were gonna be well ahead of any consumer need for this kind of bandwidth. It's twice as fast as gen four lane for lane and even ahead of market availability of any compatible devices. But they did it anyway, because there are advantages to being the market leader on new technologies. Not only does this kind of future compatibility give Intel a valuable marketing bullet point for their platform, but it's also very likely that as Nvidia or even AMD are developing their next gen PCI express gen five GPUs that they're gonna end up using Intel's Alder Lake platform for their own internal validation, making it much more likely that any early quirks are gonna be accounted for before those products shipped to consumers. Of course, living on the bleeding edge like that means that you've got to get creative sometimes. Okay, this is a bit of an aside, but this is my first hands on with a PCI express gen five device. And not just me, this is almost anyone's first hand on with a PCI express gen five device. This is so cool. And immediately there are some noticeable physical changes compared to PCI express gen four. For example, in gen four, here at the front of the connector, only the presence pins were shorter. So these tell the motherboard that there's a device installed. But in gen five, the presence pins and the power pins are shorter as well. And this seems to be a result of what we've learned about hot plugging from years of Thunderbolt and NVMe storage devices. So this change ensures that all the data connections are complete before the board powers up. But there are also some obvious changes to the data pin layout, presumably to improve signal integrity, because when we double our speed, it means that we are far more sensitive to signaling issues. You can actually see more detail about this in our HDMI cable tester video showing how the eye works and what happens if the eye gets too small. You must be thinking though, okay, cool card, but what does it do? The answer is nothing, but also everything. There's no GPU or storage or network controller on here. Nothing like that. The card is non-functioning in that sense. But what it does do is generate and monitor traffic or errors, and it can do so at every layer, link, physical, transactional, giving Intel's engineers almost full control of what they wanna do with it. Most of these functions can be programmed in band. So that is to say over the PCI Express bus, and then the test can be executed. But some of them are actually handled with dip switches that can do things like limit the speed the PCI Express generation the card runs at, limit the number of lanes that are available. I mean, obviously you don't wanna go build a whole bunch of different physical cards for 1X, 4X, 8X, and 16X, right? Another thing you don't wanna build is custom silicon every time you find a hardware bug. That's why this card uses a field programmable gate array or an FPGA. FPGAs are prohibitively expensive compared to ASICs or normal computer chips. So you'll only rarely see them in consumer products. Apple's afterburner accelerator card is an example. But when you're developing a product that is meant to follow a specification that ain't finalized yet, FPGAs are a must. Because like it says in the name, rather than being locked into a particular configuration, they're actually hardware reprogrammable in the field, allowing the engineers to make changes to the chip to address any shortcomings without wasting months designing and manufacturing a new ASIC every single time. Now, I asked about the eight pin power connector here, and it turns out that it's not actually a requirement for the onboard FPGA, but rather it's there to validate external power functionality. And as for the RAM slot, they were extremely cagey about the RAM slot. Something, something, another mode we don't use. I had kind of hoped it was for something like testing throughput to a known high bandwidth device or something like that. But Intel has super high performance FPGAs. So obviously they're using their own. So they wouldn't really need that. I don't know. This is really cool. One of the big validation challenges today is USB type C, with all the different power envelopes and protocols, DisplayPort, native USB, Thunderbolt, not to mention daisy chaining with the latter. We've reached a point of exponential possible configuration growth to the point where it is practically speaking, impossible to test every single combination. But if you've got one of these, you can do an awful lot. It doesn't really have a name, but this USB-C test rig is super cool. Each one of these wings hanging off of the test bench here has a variety of devices hanging off of it. And they're both internally designed ones and commercially available ones. I see some storage cards. I see what looks like. Well, I see more storage cards. Actually, I don't recognize most of them. Then up here is the brains. This thing is really cool. Typically what the engineer would do is they would plug this port here into the motherboard. And then they connect anything they want to all of these ports up here. And everything else is remotely configurable through software. So you wanna change from USB to Thunderbolt mode, done. Wanna connect this guy right here specifically, easy. How about this one and this one? No problem. What if you want to simulate the effects of someone plugging in and unplugging a device a thousand times? Well, you could make your new hires do it or if you're Intel, you could create a robot for that. But the lab folks are all about working smarter, not harder. Right guys? Yeah, that's what I thought. Now, of course, the main point of this kind of automation is to allow the techs to run a much broader array of configurations and much more quickly, which you need because the real world is full of scenarios that are far more challenging than plugging in and unplugging a device from a powered system. Like let's say a machine goes to sleep with one device and then wakes up with another. Like you're at work plugged into your USB dock, you shut the lid on your laptop, unplug, throw it in your bag, go home. Then you plug in an external display and fire up your machine. Well, the system has to be able to figure out what the heck just happened and who it just woke up with. I call this one the hangover scenario. What do you think? Is that nickname gonna stick? Of course, you guys might've noticed, I talked about displays, but we're not actually plugged into any type C displays. That is where this little guy comes in. Welcome to Times Square. Get it? Cause there's displays everywhere. So clearly they do have parts of the lab that are dedicated to display testing full of all kinds of different monitors so they can ensure that you don't get flicker on a high resolution monitor when you plug in the onboard GPU, for example. But for what I think are fairly obvious reasons, it's not practical to fill the whole lab with 65 inch TVs just so you can make sure that HDMI 2.1 works over on your USB test bench, right? So what they do is they use this little dongle called the dock, D-O-K. And what it does is it rips the EDID information off of any display. The EDID is kind of like the identifier of that particular model that reports its capabilities back to the connected device. Then what it does is it emulates it, making your device think that that monitor is connected. Definitely a space saver. There are some areas where you just can't take shortcuts though. Part of silicon behavior is influenced by its thermal environment. So part of their testing methodology is of course, to alter that environment. I call this guy the thermal doodad. And honestly, I don't know much about it because the expert on this didn't happen to be here. But what I do know is that it's a hydro pneumatic cooling system, which means, other than that those words mean water and air, I'm not sure. And you can actually see that it's hooked up to the building supply of both water and air. I mean, it's no lttstore.com water bottle, but I guess it's pretty cool. And the control panel over here can either be adjusted manually or remotely. And it'll actually change the parameters of the Intel control mechanism, which is over here behind the test bench. So this guy can raise and lower coolant temperatures on command, allowing the techs to simulate a wide variety of different real world use cases. Let's say you turn on your machine outside on a freezing cold day. So they've got to have the CPU be able to start cold and then get hot. Or maybe you take your machine out of the sweltering heat into an air-conditioned room. Well, they've got to build a profile for the silicon's behavior under those conditions too. And the thermal head, that is such a boring engineer name by the way, guys, I'm gonna stick with the doodad, allows them to do just that, which surely makes you wonder, what do they do when they find these kinds of problems that must exist in the hardware? I mean, most of the chips in the validation lab here are gonna be ES1 or ES2, not final specs. So bugs and undesirable behavior are part of the territory. I am so glad you asked because I saved one of the coolest parts of the full tour for this follow-up video. And we're gonna run down right now to the debug lab. Wait, expert showed up. Okay, so the red tubes are carrying water that could be as cold as like below zero, okay? Way below the ambient temperature in this room. So the air in the blue tubes here is actually to blow around the CPU socket and prevent any ice from forming or condensation or anything like that when they're going well below ambient temperature. Super cool. Okay, now we're leaving. When you need to dig as deep as possible into the silicon, the debug lab is the place to go. Why? Because it's the home of the Lada, the laser assisted device alteration. I don't remember. The name is not what's important. What matters is how fricking cool this thing is. It fires high powered lasers into the silicon, like into the PNP junction so you can actually change the properties of the chip. Say for example, you wanna change the timing of an individual transistor or the voltage required to open it. If the engineers wanna see how the chip will behave in a way that's different from how they originally designed and fabbed it, this can do it. What? Like this bears repeating because it's basically science fiction. You take a chip that's already fabbed, you fire a fricking laser beam into it and it acts differently, allowing you to test the outcome of a potential design change before you fab a whole new design. Absolutely unreal. This next one's almost as fun. Unfortunately, I'm not quite allowed to show it to you so we've got a wall of Intel employees in front of it, but I'll describe it. The IRM is kinda like a FLIR thermal camera, but for electrical activity. So you wanna see a gate open or close. You wanna monitor the activity of that gate. When I say gate, I'm talking about a single individual transistor, one of billions on a chip like Alder Lake. This is where you do it. So the engineers can get these images of how the gates behave, allowing them to say, take an issue that comes up in the validation lab, isolate it, sometimes to the transitory that's problematic, then fix it and move on with the debug and get closer to delivery. And after everything we've seen, I think the thing that blows my mind the most is that Intel has spent so many years talking about anything other than how cool this stuff is. In my humble opinion, their biggest PR problem is that they've let business people do too much of the talking while the gear heads have been quite literally locked away in the basement. But I'm hoping that after these videos go up, those days will be firmly behind us. I mean, honestly, I don't see it going down any other way because literally every single person I met here was so enthusiastic and passionate about what they do that it's infectious. I mean, take Dennis, my camera operator. He doesn't give too hot about CPUs and he still managed to have a blast in this place. The pride that these folks take in their work is inspiring and it's absolutely justified. I mean, in spite of the challenges of COVID-19, they managed to hit their delivery estimate on Alder Lake to the week that they predicted. I mean, it's mind blowing, especially now that you've seen all the steps involved. Am I right? Just like my sponsor Segways, blow your mind. I fix it. You break it, I fix it. Not me, of course, but I fix it's Moray and Minnow kits are the tool kits for the tinkerer on the go. The pocket-sized Minnow driver kit is only $14.99 with an easy to open magnetized case, a built-in sorting tray, 16 different bits, and a handle with a built-in eSIM eject tool. Pretty fancy. For something slightly bigger and longer, the Moray driver kit is only $19.99 and comes with 32 different bits with extended reach necks for digging into those hard to reach nooks and crannies. And all I fix it kits come with a lifetime warranty as well, so you're sure to end up in a landfill somewhere before your iFixit kit does. So check out our links in the description to get yours today. If you guys enjoyed this video, all I gotta do is point you to some of the other videos we've done, maybe the Fab Tour, go check it out. It's gonna blow your mind.