Simple-As-Possible computer
The Simple-As-Possible (SAP) computer is a simplified computer architecture designed for educational purposes and described in the book Digital Computer Electronics by Albert Paul Malvino and Jerald A. Brown. The SAP architecture serves as an example in Digital Computer Electronics for building and analyzing complex logical systems with digital electronics.

Digital Computer Electronics successively develops three versions of this computer, designated as SAP-1, SAP-2, and SAP-3.  Each of the last two build upon the immediate previous version by adding additional computational, flow of control, and input/output capabilities.  SAP-2 and SAP-3 are fully Turing-complete.

The instruction set architecture (ISA) that the computer final version (SAP-3) is designed to implement is patterned after and upward compatible with the ISA of the Intel 8080/8085 microprocessor family. Therefore, the instructions implemented in the three SAP computer variations are, in each case, a subset of the 8080/8085 instructions.

Variant

Ben Eater's Design 

YouTuber and former Khan Academy employee Ben Eater created a tutorial building an 8-bit Turing-complete SAP computer on breadboards from logical chips (7400-series) capable of running simple programs such as computing the Fibonacci sequence. Eater's design consists of the following modules:

 An adjustable-speed (upper limitation of a few hundred Hertz) clock module that can be put into a "manual mode" to step through the clock cycles.
 Three register modules (Register A, Register B, and the Instruction Register) that "store small amounts of data that the CPU is processing."
 An arithmetic logic unit (ALU) capable of adding and subtracting 8-bit 2's complement integers from registers A and B. This module also has a flags register with two possible flags (Z and C). Z stands for "zero," and is activated if the ALU outputs zero. C stands for "carry," and is activated if the ALU produces a carry-out bit.
 A RAM module capable of storing 16 bytes. This means that the RAM is 4-bit addressable. As Eater's website puts it, "this is by far its [the computer's] biggest limitation". 
 A 4-bit program counter that keeps track of the current processor instruction, corresponding to a 4-bit addressable RAM.
 An output register that displays its content on four 7-segment displays, capable of displaying both unsigned and 2's complement signed integers. The 7-segment display outputs are controlled by EEPROMs, which are programmed using an Arduino microcontroller.
 A bus that connects these components together. The components connect to the bus using tri-state buffers.
 A "control logic" module that defines "the opcodes the processor recognizes and what happens when it executes each instruction," as well as enabling the computer to be Turing-complete. The CPU microcodes are programmed into EEPROMs using an Arduino microcontroller.
Ben Eater's design has inspired multiple other variants and improvements, primarily on Eater's Reddit forum. Some examples of improvements are:

 An expanded RAM module capable of storing 256 bytes, utilizing the entire 8-bit address space. With the help of segmentation registers, the RAM module can be further expanded to a 16-bit address space, matching the standard for 8-bit computers.
 A stack register that allows incrementing and decrementing the stack pointer.

References

External links 

 SAP-1 online simulator (in English, Spanish and Catalan)
 Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL
 An implementation of Simple As Possible computer - SAP1, written in VHDL (in English and Portuguese)

Computer architecture