Advanced eXtensible Interface
The Advanced eXtensible Interface (AXI), part of the ARM Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4) specifications, is a parallel high-performance, synchronous, high-frequency, multi-master, multi-slave communication interface, mainly designed for on-chip communication.

AXI has been introduced in 2003 with the AMBA3 specification. In 2010, a new revision of AMBA, AMBA4, defined the AXI4, AXI4-Lite and AXI4-Stream protocol. AXI is royalty-free and its specification is freely available from ARM.

AXI offers a wide spectrum of features, including:
 separate address/control and data phases
 support for unaligned data accesses
 burst-based transfers, with a single transmission of the starting address
 separate and independent read and write channels
 support for outstanding transactions
 support for out-of-order transaction completion for transactions having different thread IDs on the same master port. (Transactions on the same master port that have the same thread ID must be completed in order. Additionally, different master ports  may be completed out of order with respect to each other.) 
 support for atomic operations.

AMBA AXI specifies many optional signals, which can be optionally included depending on the specific requirements of the design, making AXI a versatile bus for numerous applications.

While the communication over an AXI bus is between a single master and a single slave, the specification includes detailed description and signals to include N:M interconnects, able to extend the bus to topologies with more masters and slaves.

AMBA AXI4, AXI4-Lite and AXI4-Stream have been adopted by Xilinx and many of its partners as main communication buses in their products.

Thread IDs

Thread IDs allow a single master port to support multiple threads, where each thread has in-order access to the AXI address space, however each thread ID initiated from a single master port may complete out of order with respect to each other.  For instance in the case where one thread ID is blocked by a slow peripheral, another thread ID may continue Independent of the order of the first thread ID.  Another example, one thread on a cpu may be assigned a thread ID for a particular master port memory access such as read addr1, write addr1, read addr1, and this sequence will complete in order because each transaction has the same master port thread ID. Another thread running on the cpu may have another master port thread ID assigned to it, and it's memory access will be in order as well but maybe intermixed with the first thread IDs transactions.

Thread IDs on a master port are not globally defined, thus an AXI switch with multiple master ports will internally prefix the master port index to the thread ID, and provide this concatenated thread ID to the slave device, then on return of the transaction to its master port of origin, this thread ID prefix will be used to locate the master port and the prefix will be truncated.  This is why the slave port thread ID is wider in bits than the master port thread ID.

Axi-lite bus is an AXI bus that only supports a single ID thread per master.  This bus is typically used for an end point that only needs to communicate with a single master device at a time, example, a simple peripheral such as a UART.  In contrast, a CPU is capable of mastering to multiple peripherals and address spaces at a time, and will support more than one thread ID on its axi master ports and axi slave ports.  This is why a CPU will typically support a full spec axi bus.  A typical example of an front side axi switch would include a full spec axi master connected to a cpu master, and several axi-lite slaves connected to the axi switch from different peripheral devices.

(Additional, axi-lite bus is restricted to only support transaction lengths of 1 data word per transaction.)

Handshake 

AXI defines a basic handshake mechanism, composed by an xVALID and xREADY signal. The xVALID signal is driven by the source to inform the destination entity that the payload on the channel is valid and can be read from that clock cycle onwards. Similarly, the xREADY signal is driven by the receiving entity to notify that it is prepared to receive data.

When both the xVALID and xREADY signals are high in the same clock cycle, the data payload is considered "transferred" and the source can either provide a new data payload, by keeping high xVALID, or terminate the transmission, by de-asserting xVALID. An individual data transfer, so a clock cycle when both xVALID and xREADY are high, is called "beat".

Two main rules are defined for the control of these signals:

 A source must not wait for a high xREADY to assert xVALID.
 Once asserted, a source must keep a high xVALID until a handshake occurs.

Thanks to this handshake mechanism, both the source and the destination can control the flow of data, throttling the speed if needed.

Channels 
In the AXI specification, five channels are described:

 Read Address channel (AR)
 Read Data channel (R)
 Write Address channel (AW)
 Write Data channel (W)
 Write Response channel (B)

Other than some basic ordering rules, each channel is independent from each other and has its own couple of xVALID/xREADY handshake signals.

AXI

Signals

Bursts 

AXI is a burst-based protocol, meaning that there may be multiple data transfers (or beats) for a single request. This makes it useful in the cases where it is necessary to transfer large amount of data from or to a specific pattern of addresses.
In AXI, bursts can be of three types, selected by the signals ARBURST (for reads) or AWBURST (for writes):

 FIXED
 INCR
 WRAP

In FIXED bursts, each beat within the transfer has the same address. This is useful for repeated access at the same memory location, such as when reading or writing a FIFO.

In INCR bursts, on the other hand, each beat has an address equal to the previous one plus the transfer size. This burst type is commonly used to read or write sequential memory areas.

WRAP bursts are similar to the INCR ones, as each transfer has an address equal to the previous one plus the transfer size. However, with WRAP bursts, if the address of the current beat reaches the "Higher Address boundary", it is reset to the "Wrap boundary":

with

Transactions

Reads 

To start a read transaction, the master has to provide on the Read address channel:
 the start address on ARADDR
 the burst type, either FIXED, INCR or WRAP, on ARBURST (if present)
 the burst length on ARLEN (if present).
Additionally, the other auxiliary signals, if present, are used to define more specific transfers.

After the usual ARVALID/ARREADY handshake, the slave has to provide on the Read data channel:
 the data corresponding to the specified address(es) on RDATA
 the status of each beat on RRESP
plus any other optional signals.
Each beat of the slave response is done with a RVALID/RREADY handshake and, on the last transfer, the slave has to assert RLAST to inform that no more beats will follow without a new read request.

Writes 

To start a write operation, the master has to provide both the address information and the data ones.

The address information are provided over the Write address channel, in a similar manner as a read operation:
 the start address has to be provided on AWADDR
 the burst type, either FIXED, INCR or WRAP, on AWBURST (if present)
 the burst length on AWLEN (if present)
and, if present, all the optional signals.

A master has also to provide the data related to the specified address(es) on the Write data channel:
 the data on WDATA
 the "strobe" bits on WSTRB (if present), which conditionally mark the individual WDATA bytes as "valid" or "invalid"

Like in the read path, on the last data word, WLAST has to be asserted by the master.

After the completion of both the transactions, the slave has to send back to the master the status of the write over the Write response channel, by returning the result over the BRESP signal.

AXI4-Lite 
AXI4-Lite is a subset of the AXI4 protocol, providing a register-like structure with reduced features and complexity. Notable differences are:
 all bursts are composed by 1 beat only
 all data accesses use the full data bus width, which can be either 32 or 64 bits

AXI4-Lite removes part of the AXI4 signals but follows the AXI4 specification for the remaining ones. Being a subset of AXI4, AXI4-Lite transactions are fully compatible with AXI4 devices, permitting the interoperability between AXI4-Lite masters and AXI4 slaves without additional conversion logic.

Signals

AXI-Stream

See also 
 Advanced Microcontroller Bus Architecture
 Wishbone (computer bus)
 Master/slave (technology)

References

External links 
 AMBA webpage
 AXI4 specification
 ARM AXI introduction
 Xilinx AXI introduction

Computer buses
System on a chip