Write combining
Write combining (WC) is a computer bus technique for allowing data to be combined and temporarily stored in a buffer the write combine buffer (WCB) to be released together later in burst mode instead of writing (immediately) as single bits or small chunks.

Technique
Write combining cannot be used for general memory access (data or code regions) due to the weak ordering. Write-combining does not guarantee that the combination of writes and reads is done in the expected order. For example, a write/read/write combination to a specific address would lead to the write combining order of read/write/write which can lead to obtaining wrong values with the first read (which potentially relies on the write before).

In order to avoid the problem of read/write order described above, the write buffer can be treated as a fully associative cache and added into the memory hierarchy of the device in which it is implemented.
Adding complexity slows down the memory hierarchy so this technique is often only used for memory which does not need strong ordering (always correct) like the frame buffers of video cards.

See also
Framebuffer (FB), and when linear: LFB
Memory type range registers (MTRR) – the older x86 cache control mechanism
Page attribute table (PAT) – x86 page table extension that allows fine-grained cache control, including write combining
Page table
Uncacheable speculative write combining (USWC)
Video Graphics Array (VGA), and Banked (BVGA) Frame Buffer

References

External links
6x86opt, ctppro, CTU, DirectNT, FastVid, fstorion, K6Speed, MTRRLFBE, S3 Speed Up & Write Allocate Monitor enable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 and AMD K6 CPUs in Windows 9x, Windows NTx, DOS, OS/2 and Linux
MTRRLFBE enable LFB and BVGA Write Combining on Intel Pentium Pro/2/3/4 CPUs in Windows 9x and DOS
CTU (Internet Archive cached copy) enable LFB and Banked VGA Write Combining on AMD K6 CPUs in Windows 9x and DOS

Computer buses
Computer memory