ILLIAC II
The ILLIAC II was a revolutionary super-computer built by the University of Illinois that became operational in 1962.

Description 
The concept, proposed in 1958, pioneered Emitter-coupled logic (ECL) circuitry, pipelining, and transistor memory with a design goal of 100x speedup compared to ILLIAC I.

ILLIAC II had 8192 words of core memory, backed up by 65,536 words of storage on magnetic drums. The core memory access time was 1.8 to 2 µs. The magnetic drum access time was 8.5ms.  A "fast buffer" was also provided for storage of short loops and intermediate results (similar in concept to what is now called cache). The "fast buffer" access time was 0.25 µs.

The word size was 52 bits.

Floating point numbers used a format with 7 bits of exponent (power of 4) and 45 bits of mantissa.

Instructions were either 26 bits or 13 bits long, allowing packing of up to 4 instructions per memory word.

Rather than naming the pipeline stages, "Fetch, Decode, and Execute" (as on Stretch), the pipelined stages were named, "Advanced Control, Delayed Control, and Interplay".

Innovation 
 The ILLIAC II was one of the first transistorized computers. Like the IBM Stretch computer, ILLIAC II was designed using "future transistors" that had not yet been invented.
 The ILLIAC II project was proposed before, and competed with IBM's Stretch project, and several ILLIAC designers felt that Stretch borrowed many of its ideas from ILLIAC II, whose design and documentation were published openly as University of Illinois Tech Reports.  Members of the ILLIAC II team jokingly referred to the competing IBM Project as "St. Retch".
 The ILLIAC II had a division unit designed by faculty member James E. Robertson, a co-inventor of the SRT Division algorithm.
 The ILLIAC II was one of the first pipelined computers, along with IBM's Stretch Computer.  The pipelined control was designed by faculty member Donald B. Gillies.  The pipeline stages were named Advanced Control, Delayed Control, and Interplay.
 The ILLIAC II was the first computer to incorporate Speed-Independent Circuitry, invented by faculty member David E. Muller.  Speed-Independent Circuitry is a class of asynchronous digital logic based on the Muller C-element.  This digital logic, being asynchronous, runs at full speed of transistor propagation and requires no clocks.

Discoveries 
During check-out of the ILLIAC II, before it became fully operational, faculty member Donald B. Gillies programmed ILLIAC II to search for Mersenne prime numbers.  The check-out period took roughly 3 weeks, during which the computer verified all the previous Mersenne primes and found three new prime numbers. The results were immortalized for more than a decade on a UIUC Postal Annex cancellation stamp, and were discussed in the New York Times, recorded in the Guinness Book of World Records, and described in a journal paper in Mathematics of Computation.

End of life 
The ILLIAC II computer was disassembled roughly a decade after its construction. By this time the hundreds of modules were obsolete scrap; many faculty members took components home to keep. Donald B. Gillies kept 12 (mostly control) modules.  His family donated 10 of these modules and the front panel to the University of Illinois CS department in 2006.  The photos in this article were taken during the time of donation.

Donald W. Gillies, the son of Donald B. Gillies, has a complete set of documentation (instruction set, design reports, research reports, and grant progress reports, roughly 2000 pages) from the ILLIAC II project. He can be contacted for further details about this computer. Most of this documentation should also be available as DCL technical reports in the UIUC Engineering library, although it would not be packaged as a single report.

See also 
 ORDVAC
 ILLIAC I
 ILLIAC III
 ILLIAC IV

References

External links 
 Gillies, Donald B. Three New Mersenne Primes and a Statistical Theory, Mathematics of Comput., Vol. 18:85 (Jan. 1964), pp. 93–97.
 ILLIAC II documentation at bitsavers.org

One-of-a-kind computers
Transistorized computers