Golden Cove
Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November, 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's 7 nm class process node called Intel 7, previously referred to as 10 nm Enhanced SuperFin (10ESF).

The microarchitecture is used in the high-performance cores (P-core) of the 12th-generation Intel Core processors (codenamed "Alder Lake") and will power 4th-generation Xeon Scalable server processors (codenamed "Sapphire Rapids").

Features 
Intel first unveiled Golden Cove during their Architecture Day 2020. Further details were released by Intel in August 2021, during their next Architecture Day.

Similar to Skylake, Golden Cove is a major update to the core microarchitecture, with Intel stating that will "allow performance for the next decade of compute". Intel considers Golden Cove to be the largest microarchitectural upgrade to the Core family in a decade. Intel touts a 19% IPC increase over Cypress Cove.

Improvements 
 New 6-wide instruction decoder (up from 4-wide in previous microarchitectures) with the ability to fetch up to 32 bytes of instructions per cycle (up from 16)
 Wider 6-wide microarchitecture
 µOP cache size increased to 4K entries (up from 2.25K)
 12 execution ports (up from 10)
 Larger out-of-order instruction window compared to Sunny Cove, with the re-order buffer (ROB) size increased from 352 to 512 entries
 Larger Vector/FP Register File, which was increased from 224 to 332 entries
 Larger Load and Store queues (192 and 114 respectively, from 128 and 72 in Sunny Cove)
 Larger L2 cache for server variants (2 MB per core from 1.25 MB per core)
 Dedicated floating-point adders
 New instruction set extensions:
 CLDEMOTE
 PTWRITE
 User Wait: TPAUSE, UMONITOR, UMWAIT
 Architectural LBRs
 Hypervisor-managed Linear Address Translation (HLAT)
 SERIALIZE
 Enhanced Hardware Feedback Interface (EHFI) and HRESET
 AVX-VNNI
 AVX-512 with AVX512-FP16
 In server Sapphire Rapids CPUs:
 TSX with TSXLDTRK

Products 

The microarchitecture is used in the high-performance cores of the twelfth generation of Intel Core hybrid processors (codenamed "Alder Lake") and will be implemented in the fourth generation of Xeon scalable processors (codenamed "Sapphire Rapids").

See also 
 List of Intel CPU microarchitectures

References 

Intel
Intel microarchitectures
X86 microarchitectures