Honeywell 6000 series
The Honeywell 6000 series computers were rebadged versions of General Electric's 600-series mainframes manufactured by Honeywell International, Inc. from 1970 to 1989.  Honeywell acquired the line when it purchased GE's computer division in 1970 and continued to develop them under a variety of names for many years.

The high-end model was the 6080, with performance approximately 1 MIPS.  Smaller models were the 6070,  6060, 6050, 6040, and 6030. In 1973 a low-end 6025 was introduced. The even-numbered models included an Enhanced Instruction Set feature (EIS), which added decimal arithmetic and storage-to-storage operations to the original word-oriented architecture. 

In 1973 Honeywell introduced the 6180, a 6000-series machine with addressing modifications to support the Multics operating system. In 1974 Honeywell released the 68/80 which added cache memory in each processor and support for a large (2-8 million word) directly addressable memory. In 1975 the 6000-series systems were renamed as Level 66, which were slightly faster (to 1.2 MIPS) and offered larger memories. In 1977 the line was again renamed 66/DPS, and in 1979 to DPS-8, again with a small performance improvement to 1.7 MIPS.  The Multics model was the DPS-8/M.

In 1989, Honeywell sold its computer division to the French company Groupe Bull who continued to market compatible machines.

Hardware

6000-series systems were said to be "memory oriented" — a system controller in each memory module arbitrated requests from other system components (processors, etc.). Memory modules contained 128 K words of 1.2 μs 36-bit words; a system could support one or two memory modules for a maximum of 256 K words (1 MB of 9-bit bytes). Each module provided two-way interleaved memory.

Devices called Input/Output Multiplexers (IOMs) served as intelligent I/O controllers for communication with most peripherals. The IOM supported two different types of peripheral channels: Common Peripheral Channels could handle data transfer rates up to 650,000 cps; Peripheral Subsystem Interface Channels allowed transfers up to 1.3 million cps.

The 6000 supported multiple processors and IOMs. Each processor and IOM had four ports for connection to memory; each memory module had eight ports for communication with other system components, with an interrupt cell for each port. 

Memory protection and relocation was accomplished using a base and bounds register in the processor, the Base Address Register (BAR). The IOM was passed the contents of the BAR for each I/O request, allowing it to use virtual rather than physical addresses.

A variety of communications controllers could also be used with the system.  The older DATANET-30 and the DATANET 305— intended for smaller systems with up to twelve terminals attached to an IOM.  The DATANET 355 processor attached directly to the system controller in a memory module and was capable of supporting up to 200 terminals.

CPU
The CPU operated on 36-bit words, and addresses were 18 bits.  The Accumulator Register (AQ) was 72 bits, or could be accessed separately as two 36-bit registers (A and Q) or four 18-bit registers (AU,AL,QU,QL). An eight-bit Exponent Register contained the exponent for floating point operations (the mantissa was in AQ). There were eight eighteen-bit index registers X0 through X7. 

The 18-bit Base Address Register (BAR) contained the base address and number of 1024-word blocks assigned to the program (the 6180 used segmentation rather than the BAR).  The system also included several special-purpose registers: an 18-bit Instruction Counter (IC) and a 27-bit Timer Register (TR) with a resolution of 2 μs. Sets of special registers were used for fault detection and debugging.

The EIS instruction set added eight additional 24-bit registers AR0 through AR7. These registers contained an 18-bit word address, a 2-bit address of a character within the word, and a 4-bit address of a bit within the character.
  Address register format:
                     1 11 2  2
   0                 7 89 0  3
  +-------------------+--+----+
  |      Word         | C| Bit|
  +-------------------+--+----+

Instruction formats
The 6000-series machine's basic instruction set had more than 185 single-address one-word instructions.  The basic instructions were one word. The addresses pointed to  operand descriptors which contained the actual operand address and additional information.
  Basic instruction format:
                          1 1       2 2 2 2    3
        0                 7 8       6 7 8 9    5
       +-------------------+-----------+-+------+
       |          Y        |  OP       |I| Tag  |
       +-------------------+-----------+-+------+
 Y is the address field (18 bits).
 OP is the opcode (9 bits), the additional bit 27 is the opcode extension bit.
 I is the interrupt inhibit bit.
 Tag indicates the type of address modification to be performed.

The EIS instructions were two-word to four-word instructions depending on the specific instruction.
  EIS instruction format:
                          1 1       2 2 2 2    3
 word   0                 7 8       6 7 8 9    5
       +-------------------+-----------+-+------+
   0   |  Variable field   |  OP       |I| MF1  |
       +-------------------+-----------+-+------+
   1   |  Operand descriptor 1 or indirect word |
       +----------------------------------------+
   2   .  Operand descriptor 2 or indirect word . (optional)
       +- - - - - - - - - - - - - - - - - - - - +
   3   .  Operand descriptor 3 or indirect word . (optional)
       +- - - - - - - - - - - - - - - - - - - - +
 Variable field contains information relating to the specific instruction.
 OP is the EIS opcode..
 I is the interrupt inhibit bit.
 MF1 describes the address modification to be performed for descriptor 1.  If operands 2 and 3 are present the variable field contains MF2 and MF3.

Addressing modes
Multiple levels of indirect addressing were supported.  Indirect addresses had the same format as instructions, and the address modification indicated by the tag field of the indirect address was performed at each level.

The tag field of the instruction consisted of a 3-bit tag modifier (tm) and a 4-bit tag designator (td).

 The tag modifier indicates the type of modification to be performed on the instruction address:
 Register (R): Add the address field (Y) to the contents of the register indicated by the tag designator. 
 Register then indirect (RI): Perform the address modification as in Register modification, use the word at the effective address as an indirect address of the operand.
 Indirect then register (IR): Obtain the indirect word from the address specified by Y, and perform the modification requested by the tag field of the indirect word. This may result in multiple levels of indirection.  Perform the address modification specified by the instruction on the last indirect word encountered.
 Indirect then tally (IT): Obtain the indirect word from the address specified by Y, then use the address in the indirect word as the effective address. Bits 30-35 of the indirect word contained a tally field which could be used for addressing characters within a word.

For modification types R, RI, and IR the tag designator contains a register to be used for indexing (X0-X7,AU,AL,QU,QL,IC). Other TD values indicated that Y should be used as an immediate operand.  Direct addressing was a special case where Y was used as the operand address with no modification.

Data formats
Data was stored in big-endian format.  Bits were numbered starting from 0 (most-significant) to 35 or 71 (least-significant).

Binary fixed-point data was stored in twos-complement.  Half-word (18-bits), word (36-bits) and double-word (72-bits) operands were supported. Multiply and divide instructions were provided which would treat the operand as a binary fraction rather than an integer.
Binary floating-point data could be single precision (36 bits) or double precision (72 bits).  In either case the exponent was eight bits, twos-complement binary.  The mantissa was either 28 or 64 bits, twos-complement binary.
Character data was either 6-bit BCD or 9-bit ASCII.

Peripherals
The following peripherals were available for the 6000-Series machines in 1971.

 Control console, attached to the IOM, was a printer-keyboard that operated at 15 characters per second (cps).
 DSS180 removable disk storage subsystem provided up to 18 drives using disks physically compatible with IBM 2316 disks used in the 2314. The disks were formatted to provide 384 six-bit characters per sector and 27,648,000 characters per pack.  The average seek time was 34 milliseconds (ms) and data transfer rate was 416,000 cps.
 DSS190 removable disk storage subsystem provided up to 16 drives using disks compatible with IBM 3336-11 drives used in the 3330.  The disks were formatted with variable-length sectors in multiples of 384 characters.  One pack could hold up to 133,320,000 characters. The average access time was 30 ms and data transfer rate was 1,074,000 cps.
 DSS270 disk storage subsystem provided up to 20 modules of head-per-track disk. Capacity per module was 15.3 million characters.  Average access time was 26 ms, and maximum transfer rate was 333,000 cps.
 DSS167 disk storage subsystem allowed up to eight online disk drives plus an offline spare.  Per disk capacity was 15 million characters; average access time was 87.5 ms and data transfer rate was 208,000 cps.
 DSS170 removable disk storage subsystem allowed up to eight online disk drives plus an offline spare. Per disk capacity was 27.5 million characters; average access time was 72.5 ms and data transfer rate was 416,000 cps.
 Magnetic tape was available in a variety of models, all using open-reel ½ inch magnetic tape.  Various models could read and write seven-track or nine-track tape with densities from 200 bits per inch (bpi) to 1600 bpi at rates of 37.5 inches per second (ips) to 150 ips.  The maximum transfer rate was 266 characters per second (cps). All models connected to the system through the IOM.
 Line printers were the PRT300 train printer capable of printing at 1150 lines per minute (lpm) and the PRT201 at 1200 lpm.
 Punched card equipment consisted of the CRZ201 card reader capable of reading up to 900 80-column cards per minute (cpm) and the CPZ201 card punch which could punch up to 300 80-column cards per minute.

Software
The primary operating system for the line was the General Comprehensive Operating System (GCOS), which Honeywell originally inherited from General Electric's GECOS. In 1978 Honeywell introduced a rewritten version GCOS 8, which supported virtual memory.  The Multics OS also ran on selected CPU models.

In 1974, Honeywell purchased Xerox Data Systems (XDS), and developed a work-alike of the Xerox operating system CP-V as CP-6 to run on DPS-8 systems in order to retain Xerox' loyal customer base.

References

External links 
 Open source emulator for the Multics processor
 Honeywell DPS8 manuals at Bitsavers
 Computer History Wiki - Honeywell 6000 series
 Multics and Related 6000 Series Front Panels

Honeywell mainframe computers
Computer-related introductions in 1970
History of computing hardware
36-bit computers