Ne-XVP
Ne-XVP was a research project executed between 2006-2008 at NXP Semiconductors. The project undertook a holistic approach to define a next generation multimedia processing architecture for embedded MPSoCs that targets programmability, performance scalability, and silicon efficiency in an evolutionary way. The evolutionary way implies using existing processor cores such as NXP TriMedia as building blocks and supporting industry programming standards such as POSIX threads. Based on the technology-aware design space exploration, the project concluded that hardware accelerators facilitating task management and coherency coupled with right dimensioning of compute cores deliver good programmability, scalable performance and competitive silicon efficiency.

Research

Ne-XVP's research subjects and corresponding publications:
 Asymmetric multicore architecture with generic accelerators 
 Hardware multithreading in VLIWs 
 Low-complexity cache coherence
 Hardware accelerators for task scheduling and synchronization:
 A Hardware Task Scheduler 
 Hardware Synchronization Unit to sync threads 
 Task Management Unit 
 Instruction cache sharing 
 Design Space Exploration with Performance Density as the optimization function 
 Technology modeling for embedded processors 
 Parallelization of complex multimedia algorithms (H.264, Frame Rate Conversion) 
 Auto-parallelizing compilers
 Time-aware programming languages in cooperation with the ACOTES project 
 Visual programming
 Task-level speculation
 Porting GCC to Exposed Pipeline VLIW Processors 
 Multiprogram workload for embedded processing
 A 1-GHz embedded VLIW processor

Project members

 Ghiath Al-Kadi
 Zbigniew Chamski
 Dmitry Cheresiz
 Marc Duranton (project leader)
 Surendra Guntur
 Jan Hoogerbrugge
 Anirban Lahiri
 Ondrej Popp
 Andrei Terechko
 Alex Turjan
 Clemens Wust
 ...

References 

NXP Semiconductors
Very long instruction word computing