Fairchild F8
The Fairchild F8 is an 8-bit microprocessor system from Fairchild Semiconductor, announced in 1974 and shipped in 1975. The original processor family included four main 40-pin integrated circuits (ICs); the 3850 CPU which was the arithmetic logic unit, the 3851 Program Storage Unit (PSU) which contained 1 KB of program ROM and handled instruction decoding, and the 3852 Dynamic Memory Interface (DMI) or 3853 Static Memory Interface (SMI) to control additional RAM or ROM holding the user programs or data. The 3854 DMA was an optional system that added direct memory access into the RAM controlled by the 3852.

A minimal system containing a 3850 and 3851 also included four 8-bit data ports, 64 bytes of RAM, and a user program on ROM. This allowed microcontroller applications to be built using just two chips. It also meant that any application that did not fit the simple requirements generally required at least three 40-pin ICs, the CPU, PSU and either the 3852 or 3853 along with additional memory chips. As a result of these tradeoffs, the F8 series found widespread use in the microcontroller market but saw less use as a CPU in general-purpose computers. It is relatively obscure today, as its embedded uses rarely revealed the F8 inside.

In 1977, Mostek released a greatly improved single-chip implementation, the Mostek 3870. It merged the 3850 and 3851 and reduced the number of power supply voltages. More important, Mostek re-arranged the assembly line so user code in ROM was added at the last step, greatly reducing the cost of customizing the design for controller use. The 3870 replaced the original Fairchild versions and was produced by several companies in the US and Europe. In Europe, STMicroelectronics continued producing variations of the design into the mid-1990s.

History

Development
The F8 story begins with a microprocessor development project at Olympia-Werke, a subsidiary of AEG. Best known as a manufacturer of typewriters, Olympia also had a long history in mechanical calculators, which were rapidly being converted to electronic format. They were developing a processor system known as the CP3-F, which General Instrument (GI) had licensed from them. As part of the license agreement, GI sent David Chung, head of GI's processor division, to Olympia to liaise with their design team. Shortly after returning to the US, Chung quit GI and moved to Fairchild where he became lead designer of the F8, and is named as the primary inventor on the patent.

Fairchild announced the F8 in September 1974, which led almost immediately to a lawsuit from GI for the misappropriation of trade secrets. As the case dragged on, in February 1976 Fairchild announced a cross-licensing deal with Olympia for the F8, meaning they now had legal access to the original CP3F design and GI's lawsuit was neutered, at least in technical details. Very little information on the CP3F is available, but it is widely believed by industry observers that the CP3F is the basis for the F8 design. The court case dragged on into the 1980s, but with no technical issues of note, it had no effect on the sales of the F8.

Production
The first engineering samples of the F8 were sent out in April 1975, with volume shipments beginning that fall. At the time, the electronics industry demanded second source arrangements as insurance that the design would not disappear if the designing company went bankrupt or simply lost interest in the design. Fairchild announced such an agreement with Mostek in June 1975. The agreement allowed both companies to continue independent development of the design.

The F8 was introduced at a single-unit price of $130 (), making it less expensive than contemporary designs like the Intel 8080 or Motorola 6800 which were at least twice that price. Additionally, the minimal system included four 8-bit input/output ports, a small amount of RAM, and 1 KB of ROM. Together, they allowed simple applications to be built with only two ICs. In contrast, designs like the 8080 supported this sort of functionality using separate dedicated-purpose ICs, often dozens, so an F8 system could be implemented for far less total cost. Offsetting this to some degree was that the program ROM in the PSU was masked onto the chips early in the production process, which required separate production lines for each customer. As a result, setup fees were on the order of $10,000 to $15,000.

Although the F8 was marketed as a general-purpose microprocessor, historically it represents the first purpose-designed 8-bit microcontroller, a design that implements a complete computer system on a small number of ICs. Its release had a profound influence on the market, and led to the introduction of dedicated microcontrollers from most other vendors, among them the Intel MCS-48, Motorola MC6801 and MOS 6510, all of which combined various systems formerly left to the circuit board designer to implement. These examples, however, took the process one step further and implemented an entire system on a single IC.

Through the relentless effects of Moore's law, it was not long before the 3850 and 3851 could also be implemented in a single IC, which was released as the 3859. The line was also updated with the addition of the 3856, a 3851 with 2 KB of ROM, and the 3857, a 3856 with additional address lines to access external ROM in addition to the 2 KB internal, eliminating the need for a separate 3853 in many roles.

3870
Around the same time that the 3859 was released, Mostek introduced their own version of a single-chip F8, the Mostek 3870. Whereas the 3859 was essentially just a single-chip 3850/3851, the 3870 was a significant advance; it ran up to 4 MHz, double that of the 3859, and required only a single +5V power supply instead of +5 and +12. A much more important change was that custom ROM code was now masked onto the IC as the very last step in the process, so all of the CPUs were identical until the end of the production line. As a result, the mask fees were on the order of $1000, which made it far less expensive to implement. The 3870 was such an advance over the original that Fairchild stopped production of the 3859 and licensed the 3870 for their own sales.

The 3870 was modified with many sub-versions over time. Among the most important of these was the addition of a socket on top of the chip that allowed an EPROM to be plugged in with no other support circuitry required. This eliminated the need for the on-board ROM and allowed customers to produce their own ROM and eliminate the masking fees. Variations also included examples with more ROM or RAM or other more minor changes.

Meanwhile, the cross-license deal with Olympia led to production in Germany by Telefunken, another of AEG's many brands. Mostek merged with United Technologies in 1979, who drove the company into the ground and in turn sold it to Thomson Semiconducteurs in 1985. Thomson merged with SGS in 1987 to form the modern STMicroelectronics, who continued to produce the 3870 into the 1990s. Fairchild also continued producing versions of the 3870 into the 1980s, when they were purchased by National Semiconductor.

Although little-known today, "in 1977 the F8 was the world's leading microprocessor in terms of CPU sales." The design remains somewhat obscure because most of those uses were as embedded microcontrollers where the chip inside the device is rarely identified, as opposed to products like home computers where the CPU inside is better known. Among its few better-known uses were the Fairchild Channel F in 1976, and in the VideoBrain Computer system in 1977. Both were wiped out of the market by the introduction of the Atari 2600 in 1977.

Fairchild also produced a number of engineering and hobby boards using the F8. Kit 1 was a single circuit board with the 3850 CPU, 3851 PSU, and 3853 SMI. The PSU contained a program known as "Fairbug" that could be accessed using a terminal connected to the CPU over its 8-bit I/O port.

The F8 was discontinued in the mid-1980s, with the final last-time purchase by Innovative Data Technology, San Diego, CA for use in their flagship 1/2" 9-track tape drive the TD1050 series used for billing data interchange by telecom operators.

Description

Chip family
A typical computer system generally requires a CPU, some form of input/output to communicate with the outside world, and memory holding the program code and user data. Typically, I/O would be handled by dedicated chips, and memory would be accessed through an address bus selecting locations in external memory and then returning that data to the CPU over a data bus. Depending on the design, the I/O would communicate with the processor over a dedicated bus, or alternately by placing data in memory and then having the CPU read it. Moving data between all of these different units required additional "glue" circuitry.

The F8 was designed to split these duties up in order to make minimalistic implementations possible. In theory, one could place all of these functions on a single chip, but in the era of 40-pin chips there were simply not enough pins to connect all of these functions up. In particular, implementing a 8-bit data bus, 16-bit address bus and another 8-bit I/O bus would leave only 8 more pins for every other function, from power supply and ground to the various clock signals and control lines. Other designs sometimes multiplexed the address and data lines so the same pins could be used for multiple functions, at the cost of requiring more cycles to complete an operation.

The F8 addressed this problem by internalizing some of the functions, like adding a small amount of RAM to the CPU core, while moving others out of the CPU. The best example of this is the minimal system consisting of the 3850 CPU and 3851 PSU. In this case, there is no need for an address bus at all, the RAM is contained in the 3850 and the program ROM in the 3851. It is the PSU that is responsible for keeping track of the program counter, fetching instructions from the internal ROM and feeding them to the 3850 for processing over a dedicated 5-pin instruction bus along with any associated data over the separate 8-bit data bus. This freed up 11 pins that would otherwise be used for additional address lines, which, along with other simplifications and splitting of duty, allowed the CPU to have two complete I/O busses. The 3851 added another two I/O ports, so that a minimal system had four ports in total.

With only 1 KB of ROM and 64 bytes of RAM, only small programs can be managed, but for many systems, like cash registers, gasoline pumps and similar roles, this is more than enough. When a system does have larger requirements, the 3852 or 3853 can be used. These interface with the PSU and contain additional logic for handling their associated memory; for instance, the 3852 had a complete address bus able to access 64 KB of RAM and the circuitry needed to refresh the data. The PSU is still required in these systems, and the program counter and other pointers are maintained separately in all of these chips by reading the same control lines. The main difference between the 3852 and 3853 was that the former included the dynamic RAM refresh circuitry and a 3-pin link to the 3854 DMA controller, while the 3853 removed these and added a new interrupt handler and timer.

The 3854 DMA controller was linked directly to the 3852 RAM controller and did not use the 5-pin control bus found on the other members of the family. It maintained its own address register and a separate byte count, which together indicated the block of memory to be read or written.

Instruction set architecture
Internally, the CPU contained an 8-bit accumulator, a 5-bit processor status register, a 6-bit "Indirect Scratchpad Address Register", or ISAR, and 64 bytes of "scratchpad" RAM. The first twelve locations within the RAM can be directly accessed and used as secondary accumulators, labeled A through J. The rest of the scratchpad is accessed through the ISAR, a form of indirect addressing.

The 3851/3852/3853 contain the program counter, PC0, along with a secondary program counter, PC1. PC1 was referred to as a stack pointer but was not actually used for this, it was used only to store the return addresses from subroutines and lacked any push or pop instructions. If a larger stack is required, this has to be implemented in software. These chips also had a 16-bit Data Counter, DC0, and its associated Data Counter Buffer, DC1. These were used as indexing registers for indirect addressing, although only DC0 could be accessed directly and the value in DC1 had to be swapped with DC0 using a separate instruction.

The instruction set included 70 opcodes encoded in 8-bits. As was typical of the era, many instructions had a variety of addressing modes with some of the modes encoded in the instruction opcode. For instance, the Load Register (LR) instruction came in 14 different versions depending on the origin and destination of the data. The version starting with $00 was followed by two zero bits and then another two bits indicating locations in the scratchpad in locations 12 through 15, so this used opcodes $00 through $04. $0A was another version of LR, loading the value pointed to by the ISAR. The F8 had a total of eight addressing modes.

The machine instructions can be grouped into six categories: accumulator instructions, branch instructions, memory reference instructions, address register instructions, scratchpad register instruction, miscellaneous instructions (interrupt, input, output, indirect scratchpad register, load, and store).

The F8 ran at 1–2 MHz, yielding a 0.5 μs cycle time. In the F8 the control bus regulates the use of the data bus through the use of timing signals and state controls. The phi clock divides the machine cycle into discrete phases depending on the instruction being executed. The five state control lines are a function of the instruction being executed. The control bus states regulate the control of information in the computer.

FAIR-BUG

Fairchild provided development and evaluation kits for the F8, these kits included a 3851A PSU (Program Storage Unit) which contained a monitor in mask ROM, vectored to start at address 0x8080. At power-on, the ROM was entered. The ROM monitor was referred to in Fairchild literature as FAIR-BUG. The FAIR-BUG monitor is a constellation of routines for assisting product development engineers who interacted with FAIR-BUG from a Teletype. Fairchild extended FAIR-BUG as KD-BUG, for use with a keyboard and display.

FAIR-BUG main commands are single ASCII characters drawn from the set {A, B, C, D, E, F, G, I, L, M, N, P, R, S, W}. Register and memory locations were keyed in as parameters immediately after the command identifier. For example, the command M02F0-02FF results in the content of 16 bytes of memory being typed out by the Teletype. FAIR-BUG commands address all memory locations and all registers. These locations can be examined or modified by the programmer.

FAIR-BUG contains five subroutines which are used in processing commands: Input 2 ASCII Bytes; Output 1 ASCII byte; Output the string CR, LF, Null; Output 1 ASCII byte; Input 1 ASCII Byte from a Parallel Input Device. FAIR-BUG is essentially a random access management routine for all memory, both RAM and ROM, and all registers including program counter, data counter, and scratchpad. The programmer is given the ability to plant any of the 70+ machine code instructions or operands into memory locations. The programmer can then use the G command to load a specific address into the program counter and execute the routine at that address.

The objective in providing the FAIR-BUG routines in 1975 was to assist engineers in speeding up the creation of applications for the F8 ICs.

Notes

References

Citations

Bibliography
 
 
 Datasheet: http://datasheets.chipdb.org/Fairchild/F8/fairchild-3850.pdf
 Patent: http://www.google.com/patents/US4086626

External links
 Free On-Line Dictionary of Computing
 The Great CPU List

8-bit microprocessors