       (= (name op) "+") "010"
       (= (name op) "-") "110")
     "000"))
-
-(def static-states {
-  :fetch {:control-signals '(:rd_pc, :wr_MA), :next :store_instruction}
-  :store_instruction {:control-signals '(:rd_MD, :wr_IR, :inc_pc), :next :decode}
-  :decode {:control-signals '()}
-})
 
 (defn flatten-1 [things]
   (if (empty? things)

                     ; states
                     (map #(list (first %) (:next (second %))) (dissoc states :decode))
                     ; decode
                     (map #(list :decode `(= :opcode ~(second %)) (keyword (str (first %) "_0"))) opcodes))
                   )) (assoc inputs :clock std-logic) outputs)))

(defn build* [cpuname options instructions]
  (.mkdir (java.io.File. cpuname))
  (let [states (merge static-states (make-states instructions))
        [control-unit control-in control-out] (control-unit instructions)]
    (with-open [main-vhdl (java.io.FileWriter. (str cpuname "/main.vhdl"))
                control-vhdl (java.io.FileWriter. (str cpuname "/control.vhdl"))]
      (binding [*out* control-vhdl]

      (let [highs (:control-signals state)
            assertions (map #(list 'high %) highs)
            clears (map #(list 'low %) (difference control-signals highs))]
        (vec (concat (:code state) assertions clears
                     `((<= :alu_operation ~(alu-op-to-opcode (:alu_op state))))))))

    (list (state-machine "control_unit"
                   ; inputs
                   inputs
                   ; outputs
                   outputs 
                   ; signals
                   { :opcode (std-logic-vector (- opcode-width 1) 0) }
                   ; reset
                   (list* '(<= :alu_operation "000") '(goto :fetch) (map #(list 'low %) control-signals))
                   ; states
