 (defmethod to-vhdl :entity [[type name ports defs & architecture]]
   (apply str (interpose "\n" (indent-lines
   (list
-    (spaces "entity" name "is")
-    "port("
+    (spaces "ENTITY" name "is")
+    "PORT("
     (commaify (map to-vhdl (map (partial cons :port) ports)))
     ");"
-    (str "end " name ";")
+    (str "END " name ";")
 
-    (str "architecture arch_" name " of " name " is")
+    (str "ARCHITECTURE arch_" name " OF " name " IS")
     (map to-vhdl defs)
-    "begin"
+    "BEGIN"
     (with-meta (map to-vhdl architecture) {:noindent true})
-    (str "end arch_" name ";"))))))
+    (str "END arch_" name ";"))))))
 
 ; does not generate lines like block-level methods do
 (defmethod to-vhdl :port [[type id direction type]]


(defn generate-vhdl [& entities]
  (do
    (println "library ieee;")
    (println "use ieee.std_logic_1164.all;")
    (println (to-vhdl (first entities)))))

  (:use clojure.contrib.str-utils))


(def std-logic "STD_LOGIC")

(defn std-logic-vector [start end]
  (str "STD_LOGIC_VECTOR(" start " downto " end ")"))


(defn indented-lines [strings] (map (partial str "  ") strings))
