-;; Time-stamp: <2015-03-11 14:13:53 kmodi>
+;; Time-stamp: <2015-03-11 17:03:24 kmodi>
 
 ;; Verilog
 

                    (concat "^\\s*" ; pcre regex
                            verilog-module-name
                            "\\s+"
                            ;; "(#\\s*\\((\\n|.)*?\\)(\\n|.)*?)*" ; optional hardware parameters
                            "(#\\s*\\((\\n|.)*?\\))*" ; optional hardware parameters
                                        ; '(\n|.)*?' does non-greedy multi-line grep
                            "(\\n|.)*?" ; optional newline/space before instance name
                            "\\K" ; don't highlight anything till this point
                            verilog-identifier-regexp ; instance name
                            "(?=[^a-zA-Z0-9_]*\\()")) ; optional space/newline after instance name
                                        ; and before opening parenthesis `('
                                        ; don't highlight anything in (?=..)

          (let ((verilog-instance-regexp
                 (concat "^\\s-*" ; elisp regexp
                         "\\("
                         verilog-mode-identifier-regexp
                         "\\)"
                         "\\s-+"
                         "\\(#\\s-*([[:ascii:][:nonascii:]]*)\\)*" ; optional hardware parameters
                         "\\([^a-zA-Z0-9_\\.,()]*?\\)" ; optional space/newline before instance name
                         "\\(" verilog-mode-identifier-regexp "\\)" ; instance name
                         "\\([^a-zA-Z0-9_]*(\\)" ; optional space/newline after instance name
                                        ; and before opening parenthesis `('
                         ;; "\\([^a-zA-Z0-9_]\\|\\.\\)" ; optional space/newline after `('
