           python-shell-interpreter-args "-i")
 
     (add-hook 'python-mode-hook
-        ; verilog-sk-*
               (lambda ()
                         (evil-leader/set-key
                                 "pp" 'elpy-shell-send-region-or-buffer

        ; verilog-sk-*
              (lambda ()
                        (evil-leader/set-key
                                "th" 'verilog-sk-header
                                "tm" 'verilog-sk-module
                                "ti" 'verilog-sk-input
                                "to" 'verilog-sk-output
                        ; C-c C-a - expand AUTOARG, AUTOWIRE, AUTOREG, AUTOSENSE, ...
                        ; C-c C-k - undo expand of AUTOARG, AUTOWIRE, AUTOREG, AUTOSENSE, ...
                                "ts" 'verilog-sk-state-machine
                                "ta" 'verilog-sk-always
               )))

;; vhdl-mode

        ; vhdl-template-*
              (lambda ()
                        (evil-leader/set-key
                                "-h" 'vhdl-template-header
                                "-n" 'vhdl-compose-new-component
                                "-p" 'vhdl-template-port
                                "-f" 'vhdl-template-for-generate
                                "-e" 'vhdl-template-entity
                                "-a" 'vhdl-template-architecture
                                "-i" 'vhdl-template-component-inst
               )))

    (evil-leader/set-key
