 	      (not (or (looking-at "\\<") (forward-word -1)))
 	      ;; stop if we see an assertion (perhaps labeled)
 	      (and
-	       (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
+	       (looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
 	       (progn
 		 (setq h (point))
 		 (save-excursion

expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against \"input\" (single bit),
\"output logic\" (direction and type) or \"output
[1:0]\" (direction and implicit type).  You also probably want to
skip spaces in your regexp.

For example, the below will result in matching the output \"o\"
against the previous example's module:

	   /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
  (save-excursion
    (let* ((params (verilog-read-auto-params 1 3))
	   (submod (nth 0 params))
	   (regexp (nth 1 params))
	   (direction-re (nth 2 params))
	   submodi)
      ;; Lookup position, etc of co-module
      ;; Note this may raise an error

	(not (or
	      ;; stop if beginning of buffer
	      (bobp)
	      ;; stop if looking at a pre-processor directive
	      (looking-at "`\\w+")
	      ;; stop if we find a ;
	      (= (preceding-char) ?\;)
	      ;; stop if we see a named coverpoint
