 		  (backward-sexp)
 		  (cond
 		   ((match-end 5) ;; of verilog-end-block-ordered-re
-		    (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
+		    (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
+		    (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
 		   ((match-end 6) ;; of verilog-end-block-ordered-re
-		    (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
+		    (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
+		    (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
 		   ((match-end 7) ;; of verilog-end-block-ordered-re
 		    (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
 		   ((match-end 8) ;; of verilog-end-block-ordered-re

;; the following in code (please un comment it first!) in your
;; .emacs, or in your site's site-load.el

; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))

;; Be sure to examine at the help for verilog-auto, and the other
;; verilog-auto-* functions for some major coding time savers.


	   /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against \"input\" (single bit),
\"output logic\" (direction and type) or \"output
[1:0]\" (direction and implicit type).  You also probably want to
skip spaces in your regexp.

For example, the below will result in matching the output \"o\"
against the previous example's module:
