       "Regexp for a valid verilog identifier.")
 
     (defconst modi/verilog-module-instance-re
-      ;; (concat "^\\s-*"
-      ;;         "\\("
-      ;;         modi/verilog-identifier-re
-      ;;         "\\)"
-      ;;         "\\s-+"
-      ;;         ;; optional hardware parameters followed by optional comments
-      ;;         "\\(#\\s-*([[:ascii:][:nonascii:]]*?)\\s-*/*.*\\)*"
-      ;;         "\\([^a-zA-Z0-9_\\.,()$=`]*?\\)" ; optional space/newline before instance name
-      ;;         "\\(" modi/verilog-identifier-re "\\)" ; instance name
-      ;;         "\\([^a-zA-Z0-9_]*(\\)" ; optional space/newline after instance name
-      ;;                             ; and before opening parenthesis `('
-      ;;         ;; "\\([^a-zA-Z0-9_]\\|\\.\\)" ; optional space/newline after `('
-      ;;                             ; or name-based port connections: .input_a(input_a),
-      ;;         )
       (concat "^\\s-*"
               "\\(?1:" ; force group number to 1
               modi/verilog-identifier-re ; module name

              "\\(#([^;]+?)\\(\\s-*//.*?\\)*[^;\\./]+?\\)*"
              "\\(?2:" modi/verilog-identifier-re "\\)" ; instance name
                                        ; force group number to 2
              "[^;a-zA-Z0-9_]+?(" ; optional space/newline after instance name
                                        ; and before opening parenthesis `('
              )
      "Regexp for a valid verilog module instance declaration.")

;; Time-stamp: <2015-05-04 17:13:24 kmodi>

;;; Verilog

