 		       "\\(\\<endcase\\>\\)\\>")
 	       nil 'move)
 	      (cond
-                ((match-end 3)
-                 (setq nest (1+ nest)))
-                ((match-end 2)
-                 (if (= nest 1)
-                     (throw 'found 1))
-                 (setq nest (1- nest)))
-                (t
-                 (throw 'found (= nest 0)))))))
+               ((match-end 3)
+                (setq nest (1+ nest)))
+               ((match-end 2)
+                (if (= nest 1)
+                    (throw 'found 1))
+                (setq nest (1- nest)))
+               (t
+                (throw 'found (= nest 0)))))))
       nil)))
 
 (defun verilog-backward-up-list (arg)

		    (save-excursion
		      (beginning-of-line)
		      (cond
                        ((and verilog-highlight-translate-off
                              (verilog-within-translate-off))
                         (verilog-back-to-start-translate-off (point-min)))
                        ((looking-at verilog-directive-re-1)
                         (point))
                        (t
                         nil))))
	      (if p (goto-char p))))))))

(defun verilog-forward-ws&directives (&optional bound)

	(nesting 'yes)
	(nest 1))
    (cond
     ((looking-at "\\<end\\>")
      ;; 1: Search back for matching begin
      (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
                        "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
     ((looking-at "\\<endtask\\>")
      ;; 2: Search back for matching task
      (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
      (setq nesting 'no))
     ((looking-at "\\<endcase\\>")
      (catch 'nesting
        (verilog-leap-to-case-head) )
      (setq reg nil) ; to force skip
      )

     ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
      ;; 4: Search back for matching fork
      (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
     ((looking-at "\\<endclass\\>")
      ;; 5: Search back for matching class
      (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
     ((looking-at "\\<endtable\\>")
      ;; 6: Search back for matching table
      (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
     ((looking-at "\\<endspecify\\>")
      ;; 7: Search back for matching specify
      (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
     ((looking-at "\\<endfunction\\>")
      ;; 8: Search back for matching function
      (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
      (setq nesting 'no))
     ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
     ((looking-at "\\<endgenerate\\>")
      ;; 8: Search back for matching generate
      (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
     ((looking-at "\\<endgroup\\>")
      ;; 10: Search back for matching covergroup
      (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
     ((looking-at "\\<endproperty\\>")
      ;; 11: Search back for matching property
      (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
     ((looking-at verilog-uvm-end-re)
      ;; 12: Search back for matching sequence
      (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
     ((looking-at verilog-ovm-end-re)
      ;; 12: Search back for matching sequence
      (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
     ((looking-at verilog-vmm-end-re)
      ;; 12: Search back for matching sequence
      (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
     ((looking-at "\\<endinterface\\>")
      ;; 12: Search back for matching interface
      (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
     ((looking-at "\\<endsequence\\>")
      ;; 12: Search back for matching sequence
      (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
     ((looking-at "\\<endclocking\\>")
      ;; 12: Search back for matching clocking
      (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
    (if reg
	(catch 'skip
	  (if (eq nesting 'yes)
	      (let (sreg)
		(while (verilog-re-search-backward reg nil 'move)
		  (cond
                   ((match-end 1) ; begin
                    (if (looking-at "fork")
                        (let ((here (point)))
                          (verilog-beg-of-statement)
                          (unless (looking-at verilog-disable-fork-re)
                            (goto-char here)
                            (setq nest (1- nest))))
                      (setq nest (1- nest)))
                    (if (= 0 nest)
                        ;; Now previous line describes syntax
                        (throw 'skip 1))
                    (if (and snest
                             (= snest nest))
                        (setq reg sreg)))
                   ((match-end 2) ; end
                    (setq nest (1+ nest)))
                   ((match-end 3)
                    ;; endcase, jump to case
                    (setq snest nest)
                    (setq nest (1+ nest))
                    (setq sreg reg)
                    (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
                   ((match-end 4)
                    ;; join, jump to fork
                    (setq snest nest)
                    (setq nest (1+ nest))
                    (setq sreg reg)
                    (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
                   )))
	    ;; no nesting
	    (if (and
		 (verilog-re-search-backward reg nil 'move)
