               "(" ; opening parenthesis `(' before port list
               )
       "Regexp for a valid verilog module instance declaration.")
+    (defvar modi/verilog-block-end-keywords '("end"
+                                              "join" "join_any" "join_none"
+                                              "endchecker"
+                                              "endclass"
+                                              "endclocking"
+                                              "endconfig"
+                                              "endfunction"
+                                              "endgroup"
+                                              "endinterface"
+                                              "endmodule"
+                                              "endpackage"
+                                              "endprimitive"
+                                              "endprogram"
+                                              "endproperty"
+                                              "endsequence"
+                                              "endtask")
+      "Verilog/SystemVerilog block end keywords.
+IEEE 1800-2012 SystemVerilog Section 9.3.4 Block names.")
+
+    (defvar modi/verilog-block-end-keywords-re
+      (regexp-opt modi/verilog-block-end-keywords 'symbols)
+      "Regexp to match the Verilog/SystemVerilog block end keywords.
+See `modi/verilog-block-end-keywords' for more.")
 
     (defconst modi/verilog-header-re
       (concat "^\\s-*"

      (interactive)
      (modi/verilog-compile '(4)))

;;;; convert end-block comments to block names
    (defun modi/verilog-end-block-comments-to-block-names ()
      "Convert valid end-block comments to ': BLOCK_NAME'.
Reference: IEEE 1800-2012 SystemVerilog Section 9.3.4 Block Names.

Examples: endmodule // module_name             → endmodule : module_name
          endfunction // some comment          → endfunction // some comment

;;    modi/verilog-find-parent-module (interactive)
;;    modi/verilog-selective-indent
;;    modi/verilog-compile
;;    convert block-end comments to block names
;;    Do not open all `included files
;;  hideshow
;;  hydra-verilog-template
