                ,.OUT_t(upper_t))
             instName
              (/*AUTOINST*/
-              .i        (i[9:0]),
-              .o        (o));
+              .o        (o),
+              .i        (i[9:0]));
 
 Note that the instantiation now has \"i[9:0]\" as the WIDTH
 was expanded.  Likewise the data type of \"o\" in the AUTOOUTPUT

One work around for this problem is to manually create // Inputs and //
Outputs comments above subcell signals, for example:

	module ModuleName (
	    // Outputs
	    .out (out),
	    // Inputs
	    .in  (in));"
  (save-excursion
    (let ((end-mod-point (verilog-get-end-of-defun))
          st-point end-inst-point par-values

        ;; Local state
        (verilog-read-auto-template-init)
        ;; If we're not in verilog-mode, change syntax table so parsing works right
        (unless (eq major-mode 'verilog-mode) (verilog-mode))
        ;; Allow user to customize
        (verilog-run-hooks 'verilog-before-auto-hook)
        ;; Try to save the user from needing to revert-file to reread file local-variables
