 					    (not (or (looking-at "[ \t]*`[ou]vm_")
 						     (looking-at "[ \t]*`vmm_")))))
 		       (throw 'nesting 'directive))
-           ;; indent structs as if there were module level
-           (setq structres (verilog-in-struct-nested-p))
-           (cond ((not structres) nil)
-                 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
-                 ((> structres 0) (throw 'nesting 'nested-struct))
-                 ((= structres 0) (throw 'nesting 'block))
-                 (t nil))
-
-	   ;; if we are in a parenthesized list, and the user likes to indent these, return.
-	   ;; unless we are in the newfangled coverpoint or constraint blocks
-	   (if (and
-                verilog-indent-lists
-                (verilog-in-paren)
-                (not (verilog-in-coverage-p))
-                )
-	       (progn (setq par 1)
-                      (throw 'nesting 'block)))
-
-	   ;; See if we are continuing a previous line
-	   (while t
-	     ;; trap out if we crawl off the top of the buffer
-	     (if (bobp) (throw 'nesting 'cpp))
-
-	     (if (and (verilog-continued-line-1 lim)
-                      (or (not (verilog-in-coverage-p))
-                          (looking-at verilog-in-constraint-re) ))  ;; may still get hosed if concat in constraint
-		 (let ((sp (point)))
-		   (if (and
-			(not (looking-at verilog-complete-reg))
-			(verilog-continued-line-1 lim))
-		       (progn (goto-char sp)
-			      (throw 'nesting 'cexp))
-
-		     (goto-char sp))
-                   (if (and (verilog-in-coverage-p)
-                            (looking-at verilog-in-constraint-re))
-                       (progn
-			 (beginning-of-line)
-			 (skip-chars-forward " \t")
-			 (throw 'nesting 'constraint)))
-		   (if (and begin
-                            (not verilog-indent-begin-after-if)
-                            (looking-at verilog-no-indent-begin-re))
-		       (progn
-			 (beginning-of-line)
-			 (skip-chars-forward " \t")
-			 (throw 'nesting 'statement))
-		     (progn
-		       (throw 'nesting 'cexp))))
-	       ;; not a continued line
-	       (goto-char starting_position))
-
-	     (if (looking-at "\\<else\\>")
-		 ;; search back for governing if, striding across begin..end pairs
-		 ;; appropriately
-		 (let ((elsec 1))
-		   (while (verilog-re-search-backward verilog-ends-re nil 'move)
-		     (cond
-		      ((match-end 1) ; else, we're in deep
-		       (setq elsec (1+ elsec)))
-		      ((match-end 2) ; if
-		       (setq elsec (1- elsec))
-		       (if (= 0 elsec)
-			   (if verilog-align-ifelse
-			       (throw 'nesting 'statement)
-			     (progn ;; back up to first word on this line
-			       (beginning-of-line)
-			       (verilog-forward-syntactic-ws)
-			       (throw 'nesting 'statement)))))
-		      ((match-end 3) ; assert block
-		       (setq elsec (1- elsec))
-		       (verilog-beg-of-statement) ;; doesn't get to beginning
-		       (if (looking-at verilog-property-re)
-			   (throw 'nesting 'statement) ; We don't need an endproperty for these
-			 (throw 'nesting 'block)	;We still need an endproperty
-			 ))
-		      (t ; endblock
+                   ;; indent structs as if there were module level
+                   (setq structres (verilog-in-struct-nested-p))
+                   (cond ((not structres) nil)
+                         ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
+                         ((> structres 0) (throw 'nesting 'nested-struct))
+                         ((= structres 0) (throw 'nesting 'block))
+                         (t nil))
+
+                   ;; if we are in a parenthesized list, and the user likes to indent these, return.
+                   ;; unless we are in the newfangled coverpoint or constraint blocks
+                   (if (and
+                        verilog-indent-lists
+                        (verilog-in-paren)
+                        (not (verilog-in-coverage-p))
+                        )
+                       (progn (setq par 1)
+                              (throw 'nesting 'block)))
+
+                   ;; See if we are continuing a previous line
+                   (while t
+                     ;; trap out if we crawl off the top of the buffer
+                     (if (bobp) (throw 'nesting 'cpp))
+
+                     (if (and (verilog-continued-line-1 lim)
+                              (or (not (verilog-in-coverage-p))
+                                  (looking-at verilog-in-constraint-re) ))  ;; may still get hosed if concat in constraint
+                         (let ((sp (point)))
+                           (if (and
+                                (not (looking-at verilog-complete-reg))
+                                (verilog-continued-line-1 lim))
+                               (progn (goto-char sp)
+                                      (throw 'nesting 'cexp))
+
+                             (goto-char sp))
+                           (if (and (verilog-in-coverage-p)
+                                    (looking-at verilog-in-constraint-re))
+                               (progn
+                                 (beginning-of-line)
+                                 (skip-chars-forward " \t")
+                                 (throw 'nesting 'constraint)))
+                           (if (and begin
+                                    (not verilog-indent-begin-after-if)
+                                    (looking-at verilog-no-indent-begin-re))
+                               (progn
+                                 (beginning-of-line)
+                                 (skip-chars-forward " \t")
+                                 (throw 'nesting 'statement))
+                             (progn
+                               (throw 'nesting 'cexp))))
+                       ;; not a continued line
+                       (goto-char starting_position))
+
+                     (if (looking-at "\\<else\\>")
+                         ;; search back for governing if, striding across begin..end pairs
+                         ;; appropriately
+                         (let ((elsec 1))
+                           (while (verilog-re-search-backward verilog-ends-re nil 'move)
+                             (cond
+                               ((match-end 1) ; else, we're in deep
+                                (setq elsec (1+ elsec)))
+                               ((match-end 2) ; if
+                                (setq elsec (1- elsec))
+                                (if (= 0 elsec)
+                                    (if verilog-align-ifelse
+                                        (throw 'nesting 'statement)
+                                      (progn ;; back up to first word on this line
+                                        (beginning-of-line)
+                                        (verilog-forward-syntactic-ws)
+                                        (throw 'nesting 'statement)))))
+                               ((match-end 3) ; assert block
+                                (setq elsec (1- elsec))
+                                (verilog-beg-of-statement) ;; doesn't get to beginning
+                                (if (looking-at verilog-property-re)
+                                    (throw 'nesting 'statement) ; We don't need an endproperty for these
+                                  (throw 'nesting 'block)	;We still need an endproperty
+                                  ))
+                               (t ; endblock
 					; try to leap back to matching outward block by striding across
 					; indent level changing tokens then immediately
 					; previous line governs indentation.
-		       (let (( reg) (nest 1))
-			 ;;	 verilog-ends =>  else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
-			 (cond
-			  ((match-end 4) ; end
-			   ;; Search back for matching begin
-			   (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
-			  ((match-end 5) ; endcase
-			   ;; Search back for matching case
-			   (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
-			  ((match-end 6) ; endfunction
-			   ;; Search back for matching function
-			   (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
-			  ((match-end 7) ; endtask
-			   ;; Search back for matching task
-			   (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
-			  ((match-end 8) ; endspecify
-			   ;; Search back for matching specify
-			   (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
-			  ((match-end 9) ; endtable
-			   ;; Search back for matching table
-			   (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
-			  ((match-end 10) ; endgenerate
-			   ;; Search back for matching generate
-			   (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
-			  ((match-end 11) ; joins
-			   ;; Search back for matching fork
-			   (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
-			  ((match-end 12) ; class
-			   ;; Search back for matching class
-			   (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
-			  ((match-end 13) ; covergroup
-			   ;; Search back for matching covergroup
-			   (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
-			 (catch 'skip
-			   (while (verilog-re-search-backward reg nil 'move)
-			     (cond
-			      ((match-end 1) ; begin
-			       (setq nest (1- nest))
-			       (if (= 0 nest)
-				   (throw 'skip 1)))
-			      ((match-end 2) ; end
-			       (setq nest (1+ nest)))))
-			   )))))))
-	     (throw 'nesting (verilog-calc-1)))
-	   );; catch nesting
-		 );; type
+                                (let (( reg) (nest 1))
+                                  ;;	 verilog-ends =>  else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
+                                  (cond
+                                    ((match-end 4) ; end
+                                     ;; Search back for matching begin
+                                     (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
+                                    ((match-end 5) ; endcase
+                                     ;; Search back for matching case
+                                     (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
+                                    ((match-end 6) ; endfunction
+                                     ;; Search back for matching function
+                                     (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
+                                    ((match-end 7) ; endtask
+                                     ;; Search back for matching task
+                                     (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
+                                    ((match-end 8) ; endspecify
+                                     ;; Search back for matching specify
+                                     (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
+                                    ((match-end 9) ; endtable
+                                     ;; Search back for matching table
+                                     (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
+                                    ((match-end 10) ; endgenerate
+                                     ;; Search back for matching generate
+                                     (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
+                                    ((match-end 11) ; joins
+                                     ;; Search back for matching fork
+                                     (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
+                                    ((match-end 12) ; class
+                                     ;; Search back for matching class
+                                     (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
+                                    ((match-end 13) ; covergroup
+                                     ;; Search back for matching covergroup
+                                     (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
+                                  (catch 'skip
+                                    (while (verilog-re-search-backward reg nil 'move)
+                                      (cond
+                                        ((match-end 1) ; begin
+                                         (setq nest (1- nest))
+                                         (if (= 0 nest)
+                                             (throw 'skip 1)))
+                                        ((match-end 2) ; end
+                                         (setq nest (1+ nest)))))
+                                    )))))))
+                     (throw 'nesting (verilog-calc-1)))
+                   );; catch nesting
+             );; type
 	   )
       ;; Return type of block and indent level.
       (if (not type)

	(goto-char p)
	(verilog-backward-case-item lim)
	(verilog-indent-line)))
;;    (let ((verilog-tab-always-indent nil))
;;      (verilog-indent-line))
    ))

;;(defun electric-verilog-equal ()

     ;; parentheses and then continue to the end of the first
     ;; non-escaped EOL
     (concat "\\<`\\w+\\>\\s-*("
             "\\(?:.*?\\(?:\n.*\\)*?\\)" ;; definition: to end of line, then maybe more lines (excludes any trailing \n)
	     "\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
     "\\)"
     )))

(defconst verilog-keywords
  '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
    "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
    "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
    "`time_scale" "`undef" "`while"

    "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
    "assert" "assign" "assume" "automatic" "before" "begin" "bind"
    "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
    "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
    "config" "const" "constraint" "context" "continue" "cover"
    "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
    "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
    "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
    "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
    "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
    "endtask" "enum" "event" "expect" "export" "extends" "extern"
    "final" "first_match" "for" "force" "foreach" "forever" "fork"
    "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
    "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
    "include" "initial" "inout" "input" "inside" "instance" "int"
    "integer" "interface" "intersect" "join" "join_any" "join_none"
    "large" "liblist" "library" "local" "localparam" "logic"
    "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
    "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
    "notif0" "notif1" "null" "or" "output" "package" "packed"
    "parameter" "pmos" "posedge" "primitive" "priority" "program"
    "property" "protected" "pull0" "pull1" "pulldown" "pullup"
    "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
    "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
    "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
    "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
    "showcancelled" "signed" "small" "solve" "specify" "specparam"
    "static" "string" "strong0" "strong1" "struct" "super" "supply0"
    "supply1" "table" "tagged" "task" "this" "throughout" "time"
    "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
    "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
    "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
    "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
    "wire" "with" "within" "wor" "xnor" "xor"
    ;; 1800-2009
    "accept_on" "checker" "endchecker" "eventually" "global" "implies"
    "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
    "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
    "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
    ;; 1800-2012
    "implements" "interconnect" "nettype" "soft"
    )
  "List of Verilog keywords.")

(defconst verilog-comment-start-regexp "//\\|/\\*"
