   \\a*(b+c)
 
 IEEE 1800-2012 SystemVerilog Section 5.6 Identifiers, keywords,and system names.")
+
+    (defconst modi/verilog-identifier-pcre
+      (concat "\\b"
+              "([a-zA-Z_][a-zA-Z0-9$_]*)" ;simple identifier
+              "|(\\\\[!-~]+\\s+)"            ;escaped identifier
+              "\\b")
+      "Perl regex to match a valid Verilog/SystemVerilog identifier.
+This is a Perl regex equivalent of the Elips regexp in
+`modi/verilog-identifier-re'.")
 
     (defconst modi/verilog-module-instance-re
       (let* ((newline-or-space-optional "\\(?:\n\\|\\s-\\)*")

                (user-error "Ctags TAGS file `%s' was not found" tags-file)))
          (user-error "Executable `ctags' is required for this command to work")))

      (with-eval-after-load 'ag

;;;; modi/verilog-find-parent-module (interactive)
        (defun modi/verilog-find-parent-module ()
          "Find the places where the current verilog module is instantiated in
the project."
          (interactive)
          (let ((verilog-module-re (concat "^\\s-*" ; elisp regexp
                                           "\\(?:module\\)\\s-+" ; shy group
                                           "\\("
                                           modi/verilog-identifier-re
                                           "\\)\\b"))
                module-name
                module-instance-re)
            (save-excursion
              (re-search-backward verilog-module-re)
              (setq module-name (match-string 1))
              (setq module-instance-pcre ; pcre regex
                    (concat "^\\s*"
                            module-name
                            "\\s+"
                            "(#\\s*\\((\\n|.)*?\\))*" ; optional hardware parameters
                                        ; '(\n|.)*?' does non-greedy multi-line grep
                            "(\\n|.)*?" ; optional newline/space before instance name
                            "[^.]" ; do not match ".PARAM (PARAM_VAL),"
                            "\\K" ; don't highlight anything till this point
                            modi/verilog-identifier-re ; instance name
                            "(?=[^a-zA-Z0-9_]*\\()")) ; optional space/newline after instance name
                                        ; and before opening parenthesis `('
                                        ; don't highlight anything in (?=..)
              ;; (message module-instance-pcre)
              (ag-regexp module-instance-pcre (projectile-project-root)))))))


;; Time-stamp: <2017-03-31 10:35:44 kmodi>

;; Verilog

