 ;;
 
 ;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2017-09-14-ecdaea3-vpo"
+(defconst verilog-mode-version "2017-11-26-c039b16-vpo"
   "Version of this Verilog mode.")
 (defconst verilog-mode-release-emacs nil
   "If non-nil, this version of Verilog mode was released with Emacs itself.")

;;(verilog-simplify-range-expression "[FOO-1+1-1+1]")  ; FOO-0
;;(verilog-simplify-range-expression "[$clog2(2)]")  ; 1
;;(verilog-simplify-range-expression "[$clog2(7)]")  ; 3

(defun verilog-clog2 (value)
  "Compute $clog2 - ceiling log2 of VALUE."

  `verilog-auto-wire-type' may be used to change the datatype of
  the declarations.

  \"synopsys enum\" may be used in place of \"auto enum\".

An example:

	//== State enumeration
	parameter [2:0] // auto enum state_info
			   SM_IDLE =  3\\='b000,
			   SM_SEND =  3\\='b001,
			   SM_WAIT1 = 3\\='b010;
	//== State variables
	reg [2:0]  /* auto enum state_info */
		   state_r;  /* auto state_vector state_r */
	reg [2:0]  /* auto enum state_info */
		   state_e1;

	/*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
