     (advice-add 'verilog-indent-line-relative :before-until #'my/verilog-selective-indent)
     ;; Advise the indentation done by hitting `TAB'
     (advice-add 'verilog-indent-line          :before-until #'my/verilog-selective-indent)
+
+;;;; modi/verilog-compile
+    (defun modi/verilog-compile (option)
+      "Compile verilog/SystemVerilog.
+If OPTION is \\='(4) (using `\\[universal-argument]' prefix), run simulation.
+If OPTION is \\='(16) (using `\\[universal-argument] \\[universal-argument]' prefix), run linter."
+      (interactive "P")
+      (cl-case (car option)
+        (4  (setq verilog-tool 'verilog-simulator))
+        (16 (setq verilog-tool 'verilog-linter))
+        (t  (setq verilog-tool 'verilog-compiler)))
+      (verilog-set-compile-command)
+      (call-interactively #'compile))
+
+    (defun modi/verilog-simulate ()
+      "Run verilog/SystemVerilog simulation."
+      (interactive)
+      (modi/verilog-compile '(4)))
 
 ;;; hideshow
     (with-eval-after-load 'hideshow

;; Time-stamp: <2016-03-22 18:49:02 kmodi>

;; Verilog


      ;;
      ("C-c C-t"   . hydra-verilog-template/body)
      ("C-^"       . modi/verilog-jump-to-header-dwim)
      ("C-&"       . modi/verilog-jump-to-header-dwim-fwd)
      ("<f9>"      . modi/verilog-compile)
      ("<S-f9>"    . modi/verilog-simulate))
    (bind-chord "\\\\" #'modi/verilog-jump-to-module-at-point verilog-mode-map) ; "\\"
    (when (executable-find "ag")
      (bind-chord "^^" #'modi/verilog-find-parent-module verilog-mode-map))))
