 
 ;; menus
 (easy-menu-define
-  verilog-menu verilog-mode-map "Menu for Verilog mode"
-  (verilog-easy-menu-filter
-   '("Verilog"
-     ("Choose Compilation Action"
-      ["None"
-       (progn
-	 (setq verilog-tool nil)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool nil)
-       :help "When invoking compilation, use compile-command"]
-      ["Lint"
-       (progn
-	 (setq verilog-tool 'verilog-linter)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool `verilog-linter)
-       :help "When invoking compilation, use lint checker"]
-      ["Coverage"
-       (progn
-	 (setq verilog-tool 'verilog-coverage)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool `verilog-coverage)
-       :help "When invoking compilation, annotate for coverage"]
-      ["Simulator"
-       (progn
-	 (setq verilog-tool 'verilog-simulator)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool `verilog-simulator)
-       :help "When invoking compilation, interpret Verilog source"]
-      ["Compiler"
-       (progn
-	 (setq verilog-tool 'verilog-compiler)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool `verilog-compiler)
-       :help "When invoking compilation, compile Verilog source"]
-      ["Preprocessor"
-       (progn
-	 (setq verilog-tool 'verilog-preprocessor)
-	 (verilog-set-compile-command))
-       :style radio
-       :selected (equal verilog-tool `verilog-preprocessor)
-       :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
-      )
-     ("Move"
-      ["Beginning of function"		verilog-beg-of-defun
-       :keys "C-M-a"
-       :help		"Move backward to the beginning of the current function or procedure"]
-      ["End of function"		verilog-end-of-defun
-       :keys "C-M-e"
-       :help		"Move forward to the end of the current function or procedure"]
-      ["Mark function"			verilog-mark-defun
-       :keys "C-M-h"
-       :help		"Mark the current Verilog function or procedure"]
-      ["Goto function/module"		verilog-goto-defun
-       :help		"Move to specified Verilog module/task/function"]
-      ["Move to beginning of block"	electric-verilog-backward-sexp
-       :help		"Move backward over one balanced expression"]
-      ["Move to end of block"		electric-verilog-forward-sexp
-       :help		"Move forward over one balanced expression"]
-      )
-     ("Comments"
-      ["Comment Region"			verilog-comment-region
-       :help		"Put marked area into a comment"]
-      ["UnComment Region"		verilog-uncomment-region
-       :help		"Uncomment an area commented with Comment Region"]
-      ["Multi-line comment insert"	verilog-star-comment
-       :help		"Insert Verilog /* */ comment at point"]
-      ["Lint error to comment"		verilog-lint-off
-       :help		"Convert a Verilog linter warning line into a disable statement"]
-      )
-     "----"
-     ["Compile"				compile
-      :help		"Perform compilation-action (above) on the current buffer"]
-     ["AUTO, Save, Compile"		verilog-auto-save-compile
-      :help		"Recompute AUTOs, save buffer, and compile"]
-     ["Next Compile Error"		next-error
-      :help		"Visit next compilation error message and corresponding source code"]
-     ["Ignore Lint Warning at point"	verilog-lint-off
-      :help		"Convert a Verilog linter warning line into a disable statement"]
-     "----"
-     ["Line up declarations around point"	verilog-pretty-declarations
-      :help		"Line up declarations around point"]
-     ["Line up equations around point"		verilog-pretty-expr
-      :help		"Line up expressions around point"]
-     ["Redo/insert comments on every end"	verilog-label-be
-      :help		"Label matching begin ... end statements"]
-     ["Expand [x:y] vector line"	verilog-expand-vector
-      :help		"Take a signal vector on the current line and expand it to multiple lines"]
-     ["Insert begin-end block"		verilog-insert-block
-      :help		"Insert begin ... end"]
-     ["Complete word"			verilog-complete-word
-      :help		"Complete word at point"]
-     "----"
-     ["Recompute AUTOs"			verilog-auto
-      :help		"Expand AUTO meta-comment statements"]
-     ["Kill AUTOs"			verilog-delete-auto
-      :help		"Remove AUTO expansions"]
-     ["Diff AUTOs"			verilog-diff-auto
-      :help		"Show differences in AUTO expansions"]
-     ["Inject AUTOs"			verilog-inject-auto
-      :help		"Inject AUTOs into legacy non-AUTO buffer"]
-     ("AUTO Help..."
-      ["AUTO General"			(describe-function 'verilog-auto)
-       :help		"Help introduction on AUTOs"]
-      ["AUTO Library Flags"		(describe-variable 'verilog-library-flags)
-       :help		"Help on verilog-library-flags"]
-      ["AUTO Library Path"		(describe-variable 'verilog-library-directories)
-       :help		"Help on verilog-library-directories"]
-      ["AUTO Library Files"		(describe-variable 'verilog-library-files)
-       :help		"Help on verilog-library-files"]
-      ["AUTO Library Extensions"	(describe-variable 'verilog-library-extensions)
-       :help		"Help on verilog-library-extensions"]
-      ["AUTO `define Reading"		(describe-function 'verilog-read-defines)
-       :help		"Help on reading `defines"]
-      ["AUTO `include Reading"		(describe-function 'verilog-read-includes)
-       :help		"Help on parsing `includes"]
-      ["AUTOARG"			(describe-function 'verilog-auto-arg)
-       :help		"Help on AUTOARG - declaring module port list"]
-      ["AUTOASCIIENUM"			(describe-function 'verilog-auto-ascii-enum)
-       :help		"Help on AUTOASCIIENUM - creating ASCII for enumerations"]
-      ["AUTOASSIGNMODPORT"		(describe-function 'verilog-auto-assign-modport)
-       :help		"Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
-      ["AUTOINOUT"			(describe-function 'verilog-auto-inout)
-       :help		"Help on AUTOINOUT - adding inouts from cells"]
-      ["AUTOINOUTCOMP"			(describe-function 'verilog-auto-inout-comp)
-       :help		"Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
-      ["AUTOINOUTIN"			(describe-function 'verilog-auto-inout-in)
-       :help		"Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
-      ["AUTOINOUTMODPORT"		(describe-function 'verilog-auto-inout-modport)
-       :help		"Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
-      ["AUTOINOUTMODULE"		(describe-function 'verilog-auto-inout-module)
-       :help		"Help on AUTOINOUTMODULE - copying i/o from another file"]
-      ["AUTOINOUTPARAM"			(describe-function 'verilog-auto-inout-param)
-       :help		"Help on AUTOINOUTPARAM - copying parameters from another file"]
-      ["AUTOINPUT"			(describe-function 'verilog-auto-input)
-       :help		"Help on AUTOINPUT - adding inputs from cells"]
-      ["AUTOINSERTLISP"			(describe-function 'verilog-auto-insert-lisp)
-       :help		"Help on AUTOINSERTLISP - insert text from a lisp function"]
-      ["AUTOINSERTLAST"			(describe-function 'verilog-auto-insert-last)
-       :help		"Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
-      ["AUTOINST"			(describe-function 'verilog-auto-inst)
-       :help		"Help on AUTOINST - adding pins for cells"]
-      ["AUTOINST (.*)"			(describe-function 'verilog-auto-star)
-       :help		"Help on expanding Verilog-2001 .* pins"]
-      ["AUTOINSTPARAM"			(describe-function 'verilog-auto-inst-param)
-       :help		"Help on AUTOINSTPARAM - adding parameter pins to cells"]
-      ["AUTOLOGIC"			(describe-function 'verilog-auto-logic)
-       :help		"Help on AUTOLOGIC - declaring logic signals"]
-      ["AUTOOUTPUT"			(describe-function 'verilog-auto-output)
-       :help		"Help on AUTOOUTPUT - adding outputs from cells"]
-      ["AUTOOUTPUTEVERY"		(describe-function 'verilog-auto-output-every)
-       :help		"Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
-      ["AUTOREG"			(describe-function 'verilog-auto-reg)
-       :help		"Help on AUTOREG - declaring registers for non-wires"]
-      ["AUTOREGINPUT"			(describe-function 'verilog-auto-reg-input)
-       :help		"Help on AUTOREGINPUT - declaring inputs for non-wires"]
-      ["AUTORESET"			(describe-function 'verilog-auto-reset)
-       :help		"Help on AUTORESET - resetting always blocks"]
-      ["AUTOSENSE or AS"		(describe-function 'verilog-auto-sense)
-       :help		"Help on AUTOSENSE - sensitivity lists for always blocks"]
-      ["AUTOTIEOFF"			(describe-function 'verilog-auto-tieoff)
-       :help		"Help on AUTOTIEOFF - tying off unused outputs"]
-      ["AUTOUNDEF"			(describe-function 'verilog-auto-undef)
-       :help		"Help on AUTOUNDEF - undefine all local defines"]
-      ["AUTOUNUSED"			(describe-function 'verilog-auto-unused)
-       :help		"Help on AUTOUNUSED - terminating unused inputs"]
-      ["AUTOWIRE"			(describe-function 'verilog-auto-wire)
-       :help		"Help on AUTOWIRE - declaring wires for cells"]
-      )
-     "----"
-     ["Submit bug report"		verilog-submit-bug-report
-      :help		"Submit via mail a bug report on verilog-mode.el"]
-     ["Version and FAQ"			verilog-faq
-      :help		"Show the current version, and where to get the FAQ etc"]
-     ["Customize Verilog Mode..."	verilog-customize
-      :help		"Customize variables and other settings used by Verilog-Mode"]
-     ["Customize Verilog Fonts & Colors"	verilog-font-customize
-      :help		"Customize fonts used by Verilog-Mode."])))
+    verilog-menu verilog-mode-map "Menu for Verilog mode"
+    (verilog-easy-menu-filter
+     '("Verilog"
+       ("Choose Compilation Action"
+        ["None"
+         (progn
+           (setq verilog-tool nil)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool nil)
+         :help "When invoking compilation, use compile-command"]
+        ["Lint"
+         (progn
+           (setq verilog-tool 'verilog-linter)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool `verilog-linter)
+         :help "When invoking compilation, use lint checker"]
+        ["Coverage"
+         (progn
+           (setq verilog-tool 'verilog-coverage)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool `verilog-coverage)
+         :help "When invoking compilation, annotate for coverage"]
+        ["Simulator"
+         (progn
+           (setq verilog-tool 'verilog-simulator)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool `verilog-simulator)
+         :help "When invoking compilation, interpret Verilog source"]
+        ["Compiler"
+         (progn
+           (setq verilog-tool 'verilog-compiler)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool `verilog-compiler)
+         :help "When invoking compilation, compile Verilog source"]
+        ["Preprocessor"
+         (progn
+           (setq verilog-tool 'verilog-preprocessor)
+           (verilog-set-compile-command))
+         :style radio
+         :selected (equal verilog-tool `verilog-preprocessor)
+         :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
+        )
+       ("Move"
+        ["Beginning of function"		verilog-beg-of-defun
+         :keys "C-M-a"
+         :help		"Move backward to the beginning of the current function or procedure"]
+        ["End of function"		verilog-end-of-defun
+         :keys "C-M-e"
+         :help		"Move forward to the end of the current function or procedure"]
+        ["Mark function"			verilog-mark-defun
+         :keys "C-M-h"
+         :help		"Mark the current Verilog function or procedure"]
+        ["Goto function/module"		verilog-goto-defun
+         :help		"Move to specified Verilog module/task/function"]
+        ["Move to beginning of block"	electric-verilog-backward-sexp
+         :help		"Move backward over one balanced expression"]
+        ["Move to end of block"		electric-verilog-forward-sexp
+         :help		"Move forward over one balanced expression"]
+        )
+       ("Comments"
+        ["Comment Region"			verilog-comment-region
+         :help		"Put marked area into a comment"]
+        ["UnComment Region"		verilog-uncomment-region
+         :help		"Uncomment an area commented with Comment Region"]
+        ["Multi-line comment insert"	verilog-star-comment
+         :help		"Insert Verilog /* */ comment at point"]
+        ["Lint error to comment"		verilog-lint-off
+         :help		"Convert a Verilog linter warning line into a disable statement"]
+        )
+       "----"
+       ["Compile"				compile
+        :help		"Perform compilation-action (above) on the current buffer"]
+       ["AUTO, Save, Compile"		verilog-auto-save-compile
+        :help		"Recompute AUTOs, save buffer, and compile"]
+       ["Next Compile Error"		next-error
+        :help		"Visit next compilation error message and corresponding source code"]
+       ["Ignore Lint Warning at point"	verilog-lint-off
+        :help		"Convert a Verilog linter warning line into a disable statement"]
+       "----"
+       ["Line up declarations around point"	verilog-pretty-declarations
+        :help		"Line up declarations around point"]
+       ["Line up equations around point"		verilog-pretty-expr
+        :help		"Line up expressions around point"]
+       ["Redo/insert comments on every end"	verilog-label-be
+        :help		"Label matching begin ... end statements"]
+       ["Expand [x:y] vector line"	verilog-expand-vector
+        :help		"Take a signal vector on the current line and expand it to multiple lines"]
+       ["Insert begin-end block"		verilog-insert-block
+        :help		"Insert begin ... end"]
+       ["Complete word"			verilog-complete-word
+        :help		"Complete word at point"]
+       "----"
+       ["Recompute AUTOs"			verilog-auto
+        :help		"Expand AUTO meta-comment statements"]
+       ["Kill AUTOs"			verilog-delete-auto
+        :help		"Remove AUTO expansions"]
+       ["Diff AUTOs"			verilog-diff-auto
+        :help		"Show differences in AUTO expansions"]
+       ["Inject AUTOs"			verilog-inject-auto
+        :help		"Inject AUTOs into legacy non-AUTO buffer"]
+       ("AUTO Help..."
+        ["AUTO General"			(describe-function 'verilog-auto)
+         :help		"Help introduction on AUTOs"]
+        ["AUTO Library Flags"		(describe-variable 'verilog-library-flags)
+         :help		"Help on verilog-library-flags"]
+        ["AUTO Library Path"		(describe-variable 'verilog-library-directories)
+         :help		"Help on verilog-library-directories"]
+        ["AUTO Library Files"		(describe-variable 'verilog-library-files)
+         :help		"Help on verilog-library-files"]
+        ["AUTO Library Extensions"	(describe-variable 'verilog-library-extensions)
+         :help		"Help on verilog-library-extensions"]
+        ["AUTO `define Reading"		(describe-function 'verilog-read-defines)
+         :help		"Help on reading `defines"]
+        ["AUTO `include Reading"		(describe-function 'verilog-read-includes)
+         :help		"Help on parsing `includes"]
+        ["AUTOARG"			(describe-function 'verilog-auto-arg)
+         :help		"Help on AUTOARG - declaring module port list"]
+        ["AUTOASCIIENUM"			(describe-function 'verilog-auto-ascii-enum)
+         :help		"Help on AUTOASCIIENUM - creating ASCII for enumerations"]
+        ["AUTOASSIGNMODPORT"		(describe-function 'verilog-auto-assign-modport)
+         :help		"Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
+        ["AUTOINOUT"			(describe-function 'verilog-auto-inout)
+         :help		"Help on AUTOINOUT - adding inouts from cells"]
+        ["AUTOINOUTCOMP"			(describe-function 'verilog-auto-inout-comp)
+         :help		"Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
+        ["AUTOINOUTIN"			(describe-function 'verilog-auto-inout-in)
+         :help		"Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
+        ["AUTOINOUTMODPORT"		(describe-function 'verilog-auto-inout-modport)
+         :help		"Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
+        ["AUTOINOUTMODULE"		(describe-function 'verilog-auto-inout-module)
+         :help		"Help on AUTOINOUTMODULE - copying i/o from another file"]
+        ["AUTOINOUTPARAM"			(describe-function 'verilog-auto-inout-param)
+         :help		"Help on AUTOINOUTPARAM - copying parameters from another file"]
+        ["AUTOINPUT"			(describe-function 'verilog-auto-input)
+         :help		"Help on AUTOINPUT - adding inputs from cells"]
+        ["AUTOINSERTLISP"			(describe-function 'verilog-auto-insert-lisp)
+         :help		"Help on AUTOINSERTLISP - insert text from a lisp function"]
+        ["AUTOINSERTLAST"			(describe-function 'verilog-auto-insert-last)
+         :help		"Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
+        ["AUTOINST"			(describe-function 'verilog-auto-inst)
+         :help		"Help on AUTOINST - adding pins for cells"]
+        ["AUTOINST (.*)"			(describe-function 'verilog-auto-star)
+         :help		"Help on expanding Verilog-2001 .* pins"]
+        ["AUTOINSTPARAM"			(describe-function 'verilog-auto-inst-param)
+         :help		"Help on AUTOINSTPARAM - adding parameter pins to cells"]
+        ["AUTOLOGIC"			(describe-function 'verilog-auto-logic)
+         :help		"Help on AUTOLOGIC - declaring logic signals"]
+        ["AUTOOUTPUT"			(describe-function 'verilog-auto-output)
+         :help		"Help on AUTOOUTPUT - adding outputs from cells"]
+        ["AUTOOUTPUTEVERY"		(describe-function 'verilog-auto-output-every)
+         :help		"Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
+        ["AUTOREG"			(describe-function 'verilog-auto-reg)
+         :help		"Help on AUTOREG - declaring registers for non-wires"]
+        ["AUTOREGINPUT"			(describe-function 'verilog-auto-reg-input)
+         :help		"Help on AUTOREGINPUT - declaring inputs for non-wires"]
+        ["AUTORESET"			(describe-function 'verilog-auto-reset)
+         :help		"Help on AUTORESET - resetting always blocks"]
+        ["AUTOSENSE or AS"		(describe-function 'verilog-auto-sense)
+         :help		"Help on AUTOSENSE - sensitivity lists for always blocks"]
+        ["AUTOTIEOFF"			(describe-function 'verilog-auto-tieoff)
+         :help		"Help on AUTOTIEOFF - tying off unused outputs"]
+        ["AUTOUNDEF"			(describe-function 'verilog-auto-undef)
+         :help		"Help on AUTOUNDEF - undefine all local defines"]
+        ["AUTOUNUSED"			(describe-function 'verilog-auto-unused)
+         :help		"Help on AUTOUNUSED - terminating unused inputs"]
+        ["AUTOWIRE"			(describe-function 'verilog-auto-wire)
+         :help		"Help on AUTOWIRE - declaring wires for cells"]
+        )
+       "----"
+       ["Submit bug report"		verilog-submit-bug-report
+        :help		"Submit via mail a bug report on verilog-mode.el"]
+       ["Version and FAQ"			verilog-faq
+        :help		"Show the current version, and where to get the FAQ etc"]
+       ["Customize Verilog Mode..."	verilog-customize
+        :help		"Customize variables and other settings used by Verilog-Mode"]
+       ["Customize Verilog Fonts & Colors"	verilog-font-customize
+        :help		"Customize fonts used by Verilog-Mode."])))
 
 (easy-menu-define
-  verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
-  (verilog-easy-menu-filter
-   '("Statements"
-     ["Header"		verilog-sk-header
-      :help		"Insert a header block at the top of file"]
-     ["Comment"		verilog-sk-comment
-      :help		"Insert a comment block"]
-     "----"
-     ["Module"		verilog-sk-module
-      :help		"Insert a module .. (/*AUTOARG*/);.. endmodule block"]
-     ["OVM Class"	verilog-sk-ovm-class
-      :help		"Insert an OVM class block"]
-     ["UVM Object"	verilog-sk-uvm-object
-      :help		"Insert an UVM object block"]
-     ["UVM Component"	verilog-sk-uvm-component
-      :help		"Insert an UVM component block"]
-     ["Primitive"	verilog-sk-primitive
-      :help		"Insert a primitive .. (.. );.. endprimitive block"]
-     "----"
-     ["Input"		verilog-sk-input
-      :help		"Insert an input declaration"]
-     ["Output"		verilog-sk-output
-      :help		"Insert an output declaration"]
-     ["Inout"		verilog-sk-inout
-      :help		"Insert an inout declaration"]
-     ["Wire"		verilog-sk-wire
-      :help		"Insert a wire declaration"]
-     ["Reg"		verilog-sk-reg
-      :help		"Insert a register declaration"]
-     ["Define thing under point as a register" verilog-sk-define-signal
-      :help		"Define signal under point as a register at the top of the module"]
-     "----"
-     ["Initial"		verilog-sk-initial
-      :help		"Insert an initial begin .. end block"]
-     ["Always"		verilog-sk-always
-      :help		"Insert an always @(AS) begin .. end block"]
-     ["Function"	verilog-sk-function
-      :help		"Insert a function .. begin .. end endfunction block"]
-     ["Task"		verilog-sk-task
-      :help		"Insert a task .. begin .. end endtask block"]
-     ["Specify"		verilog-sk-specify
-      :help		"Insert a specify .. endspecify block"]
-     ["Generate"	verilog-sk-generate
-      :help		"Insert a generate .. endgenerate block"]
-     "----"
-     ["Begin"		verilog-sk-begin
-      :help		"Insert a begin .. end block"]
-     ["If"		verilog-sk-if
-      :help		"Insert an if (..) begin .. end block"]
-     ["(if) else"	verilog-sk-else-if
-      :help		"Insert an else if (..) begin .. end block"]
-     ["For"		verilog-sk-for
-      :help		"Insert a for (...) begin .. end block"]
-     ["While"		verilog-sk-while
-      :help		"Insert a while (...) begin .. end block"]
-     ["Fork"		verilog-sk-fork
-      :help		"Insert a fork begin .. end .. join block"]
-     ["Repeat"		verilog-sk-repeat
-      :help		"Insert a repeat (..) begin .. end block"]
-     ["Case"		verilog-sk-case
-      :help		"Insert a case block, prompting for details"]
-     ["Casex"		verilog-sk-casex
-      :help		"Insert a casex (...) item: begin.. end endcase block"]
-     ["Casez"		verilog-sk-casez
-      :help		"Insert a casez (...) item: begin.. end endcase block"])))
+    verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
+    (verilog-easy-menu-filter
+     '("Statements"
+       ["Header"		verilog-sk-header
+        :help		"Insert a header block at the top of file"]
+       ["Comment"		verilog-sk-comment
+        :help		"Insert a comment block"]
+       "----"
+       ["Module"		verilog-sk-module
+        :help		"Insert a module .. (/*AUTOARG*/);.. endmodule block"]
+       ["OVM Class"	verilog-sk-ovm-class
+        :help		"Insert an OVM class block"]
+       ["UVM Object"	verilog-sk-uvm-object
+        :help		"Insert an UVM object block"]
+       ["UVM Component"	verilog-sk-uvm-component
+        :help		"Insert an UVM component block"]
+       ["Primitive"	verilog-sk-primitive
+        :help		"Insert a primitive .. (.. );.. endprimitive block"]
+       "----"
+       ["Input"		verilog-sk-input
+        :help		"Insert an input declaration"]
+       ["Output"		verilog-sk-output
+        :help		"Insert an output declaration"]
+       ["Inout"		verilog-sk-inout
+        :help		"Insert an inout declaration"]
+       ["Wire"		verilog-sk-wire
+        :help		"Insert a wire declaration"]
+       ["Reg"		verilog-sk-reg
+        :help		"Insert a register declaration"]
+       ["Define thing under point as a register" verilog-sk-define-signal
+        :help		"Define signal under point as a register at the top of the module"]
+       "----"
+       ["Initial"		verilog-sk-initial
+        :help		"Insert an initial begin .. end block"]
+       ["Always"		verilog-sk-always
+        :help		"Insert an always @(AS) begin .. end block"]
+       ["Function"	verilog-sk-function
+        :help		"Insert a function .. begin .. end endfunction block"]
+       ["Task"		verilog-sk-task
+        :help		"Insert a task .. begin .. end endtask block"]
+       ["Specify"		verilog-sk-specify
+        :help		"Insert a specify .. endspecify block"]
+       ["Generate"	verilog-sk-generate
+        :help		"Insert a generate .. endgenerate block"]
+       "----"
+       ["Begin"		verilog-sk-begin
+        :help		"Insert a begin .. end block"]
+       ["If"		verilog-sk-if
+        :help		"Insert an if (..) begin .. end block"]
+       ["(if) else"	verilog-sk-else-if
+        :help		"Insert an else if (..) begin .. end block"]
+       ["For"		verilog-sk-for
+        :help		"Insert a for (...) begin .. end block"]
+       ["While"		verilog-sk-while
+        :help		"Insert a while (...) begin .. end block"]
+       ["Fork"		verilog-sk-fork
+        :help		"Insert a fork begin .. end .. join block"]
+       ["Repeat"		verilog-sk-repeat
+        :help		"Insert a repeat (..) begin .. end block"]
+       ["Case"		verilog-sk-case
+        :help		"Insert a case block, prompting for details"]
+       ["Casex"		verilog-sk-casex
+        :help		"Insert a casex (...) item: begin.. end endcase block"]
+       ["Casez"		verilog-sk-casez
+        :help		"Insert a casez (...) item: begin.. end endcase block"])))
 
 (defvar verilog-mode-abbrev-table nil
   "Abbrev table in use in Verilog-mode buffers.")

	      (/= nest 0)
	      (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
	      (cond
	       ((match-end 1) ; fork
		(setq nest (1- nest)))
	       ((match-end 2) ; join
		(setq nest (1+ nest)))))))
    (= nest 0) )) ; return nest

(defun verilog-backward-case-item (lim)

         )
    (save-excursion
      (if (progn
            ;; (verilog-beg-of-statement-1)
            (beginning-of-line)
            (verilog-forward-syntactic-ws)
            (and (not (verilog-in-directive-p))    ;; could have `define input foo
                 (looking-at verilog-declaration-re)))
	  (progn
	    (if (verilog-parenthesis-depth)
		;; in an argument list or parameter block
