  In this paper, we demonstrate the design of efficient and high-performance
AI/Deep Learning accelerators with customized STT-MRAM and a reconfigurable
core. Based on model-driven detailed design space exploration, we present the
design methodology of an innovative scratchpad-assisted on-chip STT-MRAM based
buffer system for high-performance accelerators. Using analytically derived
expression of memory occupancy time of AI model weights and activation maps,
the volatility of STT-MRAM is adjusted with process and temperature variation
aware scaling of thermal stability factor to optimize the retention time,
energy, read/write latency, and area of STT-MRAM. From the analysis of modern
AI workloads and accelerator implementation in 14nm technology, we verify the
efficacy of our designed AI accelerator with STT-MRAM STT-AI. Compared to an
SRAM-based implementation, the STT-AI accelerator achieves 75% area and 3%
power savings at iso-accuracy. Furthermore, with a relaxed bit error rate and
negligible AI accuracy trade-off, the designed STT-AI Ultra accelerator
achieves 75.4%, and 3.5% savings in area and power, respectively over regular
SRAM-based accelerators.

Hardware Architecture;Artificial Intelligence