  The paper presents a methodology for temporal logic verification of
continuous-time switched stochastic systems. Our goal is to find the lower
bound on the probability that a complex temporal property is satisfied over a
finite time horizon. The required temporal properties of the system are
expressed using a fragment of linear temporal logic, called safe-LTL with
respect to finite traces. Our approach combines automata-based verification and
the use of barrier certificates. It relies on decomposing the automaton
associated with the negation of specification into a sequence of simpler
reachability tasks and compute upper bounds for these reachability
probabilities by means of common or multiple barrier certificates. Theoretical
results are illustrated by applying a counter-example guided inductive
synthesis framework to find barrier certificates.

Logic in Computer Science;Systems and Control;Systems and Control