  This paper comments on "Asynchronous Logic Implementation Based on Factorized
DIMS" [Journal of Circuits, Systems, and Computers, vol. 26, no. 5, 1750087:
1-9, May 2017] with respect to two main problematic issues: i) the gate orphan
problem implicit in the factorized DIMS approach discussed in the referenced
article which affects its strong-indication, and ii) how the enumeration of
product terms to represent the synthesis cost is skewed in the referenced
article because the logic expression contains sum of products and also product
of sums. It is observed that the referenced article has not provided a general
logic synthesis algorithm excepting only an example illustration involving a
3-input AND logic function. The absence of a general logic synthesis algorithm
would make it difficult to reproduce the research described in the referenced
article. Moreover, the example illustration in the referenced article describes
an unsafe logic decomposition which is not suitable for the multi-level
synthesis of strong-indication asynchronous circuits. Further, a logic
synthesis method which safely decomposes the DIMS solution to synthesize
multi-level strong-indication asynchronous circuits is available in the
existing literature, which was neither cited nor taken up for comparison in the
referenced article, which is another drawback. Subsequently, it is concluded
that the referenced article has not advanced existing knowledge in the field
but on the contrary, has caused confusions. Hence, in the interest of readers,
this paper additionally highlights some important and relevant literature which
provide valuable information about robust asynchronous circuit synthesis
techniques which employ delay-insensitive codes for data representation and
processing and the 4-phase return-to-zero handshake protocol for data
communication.

Hardware Architecture