  Bias Temperature Instability (BTI) is a major reliability concern in CMOS
technology, especially with High dielectric constant (High-\k{appa}/HK) metal
gate (MG) transistors. In addition, the time independent process induced
variation has also increased because of the aggressive scaling down of devices.
As a result, the faster devices at the lower threshold voltage distribution
tail experience higher stress, leading to additional skewness in the BTI
degradation. Since time dependent dielectric breakdown (TDDB) and
stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it
is necessary to investigate the effect of time zero variability on all these
effects simultaneously. To that effect, we propose a simulation framework to
model and analyze the impact of time-zero variability (in particular, random
dopant fluctuations) on different aging effects. For small area devices (~1000
nm2) in 30nm technology, we observe significant effect of Random Dopant
Fluctuation (RDF) on BTI induced variability ({\sigma}{\Delta}Vth). In
addition, the circuit analysis reveals similar trend on the performance
degradation. However, both TDDB and SILC show weak dependence on RDF. We
conclude that the effect of RDF on Vth degradation cannot be disregarded in
scaled technology and needs to be considered for variation tolerant circuit
design.

Mesoscale and Nanoscale Physics;Data Analysis, Statistics and Probability