  Multiple patterning lithography (MPL) is regarded as one of the most
promising ways of overcoming the resolution limitations of conventional optical
lithography due to the delay of next-generation lithography technology. As the
feature size continues to decrease, layout decomposition for multiple
patterning lithography (MPLD) technology is becoming increasingly crucial for
improving the manufacturability in advanced nodes. The decomposition process
refers to assigning the layout features to different mask layers according to
the design rules and density requirements. When the number of masks $k \geq 3$,
the MPLD problems are NP-hard and thus may suffer from runtime overhead for
practical designs. However, the number of layout patterns is increasing
exponentially in industrial layouts, which hinders the runtime performance of
MPLD models. In this research, we substitute the CPU's dance link data
structure with parallel GPU matrix operations to accelerate the solution for
exact cover-based MPLD algorithms. Experimental results demonstrate that our
system is capable of full-scale, lightning-fast layout decomposition, which can
achieve more than 10$\times$ speed-up without quality degradation compared to
state-of-the-art layout decomposition methods.

Artificial Intelligence;Hardware Architecture