  Covert channels enable information leakage across security boundaries of the
operating system. Microarchitectural covert channels exploit changes in
execution timing resulting from competing access to limited hardware resources.
We use the recent experimental support for time protection, aimed at preventing
covert channels, in the seL4 microkernel and evaluate the efficacy of the
mechanisms against five known channels on Ariane, an open-source 64-bit
application-class RISC-V core. We confirm that without hardware support, these
defences are expensive and incomplete. We show that the addition of a
single-instruction extension to the RISC-V ISA, that flushes microarchitectural
state, can enable the OS to close all five evaluated covert channels with low
increase in context switch costs and negligible hardware overhead. We conclude
that such a mechanism is essential for security.

Cryptography and Security;Hardware Architecture