  In most digital-to-time converter (DTC) based applications, apart from
maintaining low integral non-linearity (INL), it is also required of the system
to achieve a wide frequency translation range. To achieve this performance, we
present a dual-phase direct digital synthesizer (DDS) based DTC with
phase-lookahead mechanism. The proposed technique of variable phase-advancement
enhances the frequency translation range, without excessive power consumption.
A 5-GHz digital phase locked loop (DPLL) with switched loop, incorporating this
DDS based DTC, is implemented in CMOS65nm-LL technology. The proposed DDS based
DTC is able to perform fractional shift upto 80MHz with 100MHz reference clock,
using 3mW of power from 1.2V supply. A simple look-up table based
foreground-calibration of phase-to-amplitude converter (PAC) in DDS improves
the peak INL of the DTC to 0.25ps. Hence, with the proposed DTC and a
proportional-integral-derivative (PID) controller based loop, we are able to
achieve a low-jitter fractional-N DPLL with fastest settling time of 1us
reported until now for fractional-N PLLs.

Instrumentation and Detectors