  Our ISCA 2013 paper provides a fundamental empirical understanding of two
major factors that make it very difficult to determine the minimum data
retention time of a DRAM cell, based on the first comprehensive experimental
characterization of retention time behavior of a large number of modern
commodity DRAM chips from 5 major vendors. We study the prevalence, effects,
and technology scaling characteristics of two significant phenomena: 1) data
pattern dependence (DPD), where the minimum retention time of a DRAM cell is
affected by data stored in other DRAM cells, and 2) variable retention time
(VRT), where the minimum retention time of a DRAM cell changes unpredictably
over time. To this end, we built a flexible FPGA-based testing infrastructure
to test DRAM chips, which has enabled a large amount of further experimental
research in DRAM. Our ISCA 2013 paper's results using this infrastructure
clearly demonstrate that DPD and VRT phenomena are significant issues that must
be addressed for correct operation in DRAM-based systems and their effects are
getting worse as DRAM scales to smaller technology node sizes. Our work also
provides ideas on how to accurately identify data retention times in the
presence of DPD and VRT, e.g., online profiling with error correcting codes,
which later works examined and enabled. Most modern DRAM chips now incorporate
ECC, especially to account for VRT effects.
  This short retrospective provides a brief analysis of our ISCA 2013 paper and
its impact. We describe why we did the work, what we found and its
implications, what the findings as well as the infrastructure we built to
discover them have enabled in later works, and our thoughts on what the future
may bring.

Hardware Architecture