  Modular reduction is a crucial operation in many post-quantum cryptographic
schemes, including the Kyber key exchange method or Dilithium signature scheme.
However, it can be computationally expensive and pose a performance bottleneck
in hardware implementations. To address this issue, we propose a novel approach
for computing modular reduction efficiently in hardware for arbitrary static
moduli. Unlike other commonly used methods such as Barrett or Montgomery
reduction, the method does not require any multiplications. It is not dependent
on properties of any particular choice of modulus for good performance and low
area consumption. Its major strength lies in its low area consumption, which
was reduced by 60% for optimized and up to 90% for generic Barrett
implementations for Kyber and Dilithium. Additionally, it is well suited for
parallelization and pipelining and scales linearly in hardware resource
consumption with increasing operation width. All operations can be performed in
the bit-width of the modulus, rather than the size of the number being reduced.
This shortens carry chains and allows for faster clocking. Moreover, our method
can be executed in constant time, which is essential for cryptography
applications where timing attacks can be used to obtain information about the
secret key.

Cryptography and Security;Hardware Architecture;Performance