  Directed acyclic graphs or Bayesian networks that are popular in many AI
related sectors for probabilistic inference and causal reasoning can be mapped
to probabilistic circuits built out of probabilistic bits (p-bits), analogous
to binary stochastic neurons of stochastic artificial neural networks. In order
to satisfy standard statistical results, individual p-bits not only need to be
updated sequentially, but also in order from the parent to the child nodes,
necessitating the use of sequencers in software implementations. In this
article, we first use SPICE simulations to show that an autonomous hardware
Bayesian network can operate correctly without any clocks or sequencers, but
only if the individual p-bits are appropriately designed. We then present a
simple behavioral model of the autonomous hardware illustrating the essential
characteristics needed for correct sequencer-free operation. This model is also
benchmarked against SPICE simulations and can be used to simulate large scale
networks. Our results could be useful in the design of hardware accelerators
that use energy efficient building blocks suited for low-level implementations
of Bayesian networks. The autonomous massively parallel operation of our
proposed stochastic hardware has biological relevance since neural dynamics in
brain is also stochastic and autonomous by nature.

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