  Fast and accurate depth estimation, or stereo matching, is essential in
embedded stereo vision systems, requiring substantial design effort to achieve
an appropriate balance among accuracy, speed and hardware cost. To reduce the
design effort and achieve the right balance, we propose FP-Stereo for building
high-performance stereo matching pipelines on FPGAs automatically. FP-Stereo
consists of an open-source hardware-efficient library, allowing designers to
obtain the desired implementation instantly. Diverse methods are supported in
our library for each stage of the stereo matching pipeline and a series of
techniques are developed to exploit the parallelism and reduce the resource
overhead. To improve the usability, FP-Stereo can generate synthesizable C code
of the FPGA accelerator with our optimized HLS templates automatically. To
guide users for the right design choice meeting specific application
requirements, detailed comparisons are performed on various configurations of
our library to investigate the accuracy/speed/cost trade-off. Experimental
results also show that FP-Stereo outperforms the state-of-the-art FPGA design
from all aspects, including 6.08% lower error, 2x faster speed, 30% less
resource usage and 40% less energy consumption. Compared to GPU designs,
FP-Stereo achieves the same accuracy at a competitive speed while consuming
much less energy.

Computer Vision and Pattern Recognition;Hardware Architecture;Robotics