  Cardiac Pacemakers are used to regulate the hearts rhythm and prevent
abnormal heart beats. Patients undergo a minimal surgery to get the pacemaker
implanted in the body, whereas these devices do have their limitations such as
battery life, power consumption and integrated circuit area which makes it
difficult for elderly and children to undergo this surgery. This paper focuses
on developing an optimised low pass filter ASIC design for implantable QRS
complex detector for cardiac pacemaker circuits using filter optimisation
techniques such as Pipelining and Folding of filters. The folded low pass
filter design consumes an overall power of 0.7575 mW and comprises a total of
1361 standard cells. The number of adder block units in our work reduces area
consumption by a factor of 48.37%.

Signal Processing