  Spike sorting algorithms are used to separate extracellular recordings of
neuronal populations into single-unit spike activities. The development of
customized hardware implementing spike sorting algorithms is burgeoning.
However, there is a lack of a systematic approach and a set of standardized
evaluation criteria to facilitate direct comparison of both software and
hardware implementations. In this paper, we formalize a set of standardized
criteria and a publicly available synthetic dataset entitled Synthetic
Simulations Of Extracellular Recordings (SSOER), which was constructed by
aggregating existing synthetic datasets with varying Signal-To-Noise Ratios
(SNRs). Furthermore, we present a benchmark for future comparison, and use our
criteria to evaluate a simulated Resistive Random-Access Memory (RRAM)
In-Memory Computing (IMC) system using the Discrete Wavelet Transform (DWT) for
feature extraction. Our system consumes approximately (per channel) 10.72mW and
occupies an area of 0.66mm$^2$ in a 22nm FDSOI Complementary
Metal-Oxide-Semiconductor (CMOS) process.

Machine Learning;Hardware Architecture;Performance