  Memory system is often the main bottleneck in chipmultiprocessor (CMP)
systems in terms of latency, bandwidth and efficiency, and recently
additionally facing capacity and power problems in an era of big data. A lot of
research works have been done to address part of these problems, such as
photonics technology for bandwidth, 3D stacking for capacity, and NVM for power
as well as many micro-architecture level innovations. Many of them need a
modification of current memory architecture, since the decades-old synchronous
memory architecture (SDRAM) has become an obstacle to adopt those advances.
However, to the best of our knowledge, none of them is able to provide a
universal memory interface that is scalable enough to cover all these problems.
  In this paper, we argue that a message-based interface should be adopted to
replace the traditional bus-based interface in memory system. A novel message
interface based memory system (MIMS) is proposed. The key innovation of MIMS is
that processor and memory system communicate through a universal and flexible
message interface. Each message packet could contain multiple memory requests
or commands along with various semantic information. The memory system is more
intelligent and active by equipping with a local buffer scheduler, which is
responsible to process packet, schedule memory requests, and execute specific
commands with the help of semantic information. The experimental results by
simulator show that, with accurate granularity message, the MIMS would improve
performance by 53.21%, while reducing energy delay product (EDP) by 55.90%, the
effective bandwidth utilization is improving by 62.42%. Furthermore, combining
multiple requests in a packet would reduce link overhead and provide
opportunity for address compression.

Hardware Architecture