  We propose a novel constrained Bayesian Optimization (BO) algorithm
optimizing the design process of Laterally-Diffused Metal-Oxide-Semiconductor
(LDMOS) transistors while realizing a target Breakdown Voltage (BV). We convert
the constrained BO problem into a conventional BO problem using a Lagrange
multiplier. Instead of directly optimizing the traditional Figure-of-Merit
(FOM), we set the Lagrangian as the objective function of BO. This adaptive
objective function with a changeable Lagrange multiplier can address
constrained BO problems which have constraints that require costly evaluations,
without the need for additional surrogate models to approximate constraints.
Our algorithm enables a device designer to set the target BV in the design
space, and obtain a device that satisfies the optimized FOM and the target BV
constraint automatically. Utilizing this algorithm, we have also explored the
physical limits of the FOM for our devices in 30 - 50 V range within the
defined design space.

Machine Learning;Systems and Control;Systems and Control