  A threshold logic gate (TLG) performs weighted sum of multiple inputs and
compares the sum with a threshold. We propose Spin-Memeristor Threshold Logic
(SMTL) gates, which employ memristive cross-bar array (MCA) to perform
current-mode summation of binary inputs, whereas, the low-voltage
fast-switching spintronic threshold devices (STD) carry out the threshold
operation in an energy efficient manner. Field programmable SMTL gate arrays
can operate at a small terminal voltage of ~50mV, resulting in ultra-low power
consumption in gates as well as programmable interconnect networks. We evaluate
the performance of SMTL using threshold logic synthesis. Results for common
benchmarks show that SMTL based programmable logic hardware can be more than
100x energy efficient than state of the art CMOS FPGA.

Emerging Technologies;Mesoscale and Nanoscale Physics