  This paper presents an analysis of the fundamental limits on energy
efficiency in both digital and analog in-memory computing architectures, and
compares their performance to single instruction, single data (scalar) machines
specifically in the context of machine inference. The focus of the analysis is
on how efficiency scales with the size, arithmetic intensity, and bit precision
of the computation to be performed. It is shown that analog, in-memory
computing architectures can approach arbitrarily high energy efficiency as both
the problem size and processor size scales.

Hardware Architecture;Neural and Evolutionary Computing;Optics