  Emerging chips with hundreds and thousands of cores require networks with
unprecedented energy/area efficiency and scalability. To address this, we
propose Slim NoC (SN): a new on-chip network design that delivers significant
improvements in efficiency and scalability compared to the state-of-the-art.
The key idea is to use two concepts from graph and number theory,
degree-diameter graphs combined with non-prime finite fields, to enable the
smallest number of ports for a given core count. SN is inspired by
state-of-the-art off-chip topologies; it identifies and distills their
advantages for NoC settings while solving several key issues that lead to
significant overheads on-chip. SN provides NoC-specific layouts, which further
enhance area/energy efficiency. We show how to augment SN with state-of-the-art
router microarchitecture schemes such as Elastic Links, to make the network
even more scalable and efficient. Our extensive experimental evaluations show
that SN outperforms both traditional low-radix topologies (e.g., meshes and
tori) and modern high-radix networks (e.g., various Flattened Butterflies) in
area, latency, throughput, and static/dynamic power consumption for both
synthetic and real workloads. SN provides a promising direction in scalable and
energy-efficient NoC topologies.

Hardware Architecture;Distributed, Parallel, and Cluster Computing;Networking and Internet Architecture