  The scalability of the quantum processor technology is elemental factor in
reaching fault-tolerant quantum computing. Owing to the maturity of
microelectronics, quantum bits (qubits) realized with spins in silicon quantum
dots are considered among the most promising technologies for building scalable
quantum computers. However, several challenges need to be solved to realize
quantum-dot-based quantum processors. In this respect, ultra-low-power on-chip
cryogenic classical complementary metal oxide semiconductor (CMOS) electronics
for control, read-out, and interfacing of the qubits is an important milestone.
We report scalable interfacing of tunable electron and hole quantum dots
embedded in a 64-channel cryogenic multiplexer, which has less-than-detectable
static power dissipation. Our integrated hybrid quantum-dot CMOS technology
provides a plausible route to scalable interfacing of a large number of quantum
dot devices, enabling variability analysis and quantum dot qubit geometry
optimization, which are prerequisites for building large-scale silicon-based
quantum computers. We analyze charge noise and obtain state-of-the-art addition
energies and gate lever arms in electron and hole quantum dots. The
demonstrated electrostatically-defined quantum dots and cryogenic transistors
with sharp turning-on transfer characteristics, made by harnessing a CMOS
process that utilizes a conventional doped-Poly-Si/SiO2/Si MOS stack,
constitute a promising platform for spin qubits monolithically integrated with
cryo-CMOS electronics.

Mesoscale and Nanoscale Physics