  Improving the efficiency of edge detection in embedded applications, such as
UAV control, is critical for reducing system cost and power dissipation. Field
programmable gate arrays (FPGA) are a good platform for making improvements
because of their specialised internal structure. However, current FPGA edge
detectors do not exploit this structure well. A new edge detection architecture
is proposed that is better optimised for FPGAs. The basis of the architecture
is the Sobel edge kernels that are shown to be the most suitable because of
their separability and absence of multiplications. Edge intensities are
calculated with a new 4:2 compressor that consists of two custom-designed 3:2
compressors. Addition speed is increased by breaking carry propagation chains
with look-ahead logic. Testing of the design showed it gives a 28% increase in
speed and 4.4% reduction in area over previous equivalent designs, which
demonstrated that it will lower the cost of edge detection systems, dissipate
less power and still maintain high-speed control.

Hardware Architecture;Computer Vision and Pattern Recognition