  With 3D-stacked DRAM architectures becoming more prevalent, it has become
important to find ways to characterize and mitigate the adverse effects that
can hinder their inherent access parallelism and throughput. One example of
such adversities is the electromigration (EM) effects in the through-silicon
vias (TSVs) of the power delivery network (PDN) of 3D-stacked DRAM
architectures. Several prior works have addressed the effects of EM in TSVs of
3D integrated circuits. However, no prior work has addressed the effects of EM
in the PDN TSVs on the performance and lifetime of 3D-stacked DRAMs. In this
paper, we characterize the effects of EM in PDN TSVs on a Hybrid Memory Cube
(HMC) architecture employing the conventional PDN design with clustered layout
of power and ground TSVs. We then present a new PDN design with a distributed
layout of power and ground TSVs and show that it can mitigate the adverse
effects of EM on the HMC architecture performance without requiring additional
power and ground pins. Our benchmark-driven simulation-based analysis shows
that compared to the clustered PDN layout, our proposed distributed PDN layout
improves the EM-affected lifetime of the HMC architecture by up to 10 years.
During this useful lifetime, the HMC architecture yields up to 1.51 times less
energy-delay product (EDP).

Hardware Architecture