  Safety-critical domains, such as automotive, space, and robotics, are
adopting increasingly powerful multicores with abundant hardware shared
resources for higher performance and efficiency. However, mutual interference
due to parallel operation within the SoC must be properly validated. Recently,
the SafeTI traffic injector has been released and integrated in a homogeneous
RISC-V multicore for testing, otherwise untestable casuistic for software-only
solutions. This paper introduces some enhancements performed on the SafeTI,
which include internal pipelining for higher-rate traffic injection, and its
tailoring to multiple interfaces, as well as its integration in a more powerful
heterogeneous RISC-V multicore based on Gaisler's technology for the space
domain.

Hardware Architecture;Software Engineering