A First Look at the JIT
> Data may only be kept (passed) in BEAM registers between instructions.> This may seem silly, aren’t machine registers faster?> Yes, but in practice not by much and it would make things more complicated.My understanding is that the latency of an L1 cache load is 5 cycles on recent Intel processors.In tight code that is a really substantial overhead. I get that register allocation is complicated, and I totally see the benefit of simplicity, but it's hard not to think that this will significantly limit performance.