The Belt CPU Architecture
First off, I love the post!  Super meaty goodness.I read-ish the whole set of slides and it sounds pretty good (the devil is always in the details), but I got a little worried about VLIW-ish issues when [in the slides] he said on slide #57:    The compiler controls when ops issue

One of the big issues with VLIW was that the compiler had to be intimately aware of processor architecture.  So when you upgraded your '886 to a '986 you needed new binaries because the '986 had more registers or executions units.  [I assume Itanium fixed some of this, but it also sunk my interest in VLIW.]Is this architecture going to face the same issue?Edit: I watching the video and heard that "nearly all of what the super scalar is doing is [not calculating]".  One of the other VLIW issues was that chip area was dominated by cache-area, so all the stuff about [not calculating] shrank and shrank relatively as cache area grew (see: http://techreport.com/review/15818/intel-core-i7-processors).  This claim concerns me.Edit V2: but damn...  Exciting stuff.