An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]
I am glad they are using System Verilog. It is hard for me to understand why SiFive chose Chisel as RTL language. I think that quietly slows down the RISC-V adoption. I honestly tried to understand the advantages of Chisel, but I can not see any. There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1].[1] https://stackoverflow.com/questions/53007782/what-benefits-d...