Open source RISC-V implemented from scratch in one night
Sorry to burst any bubbles here, but this is s very incomplete implementation.You couldn’t run anything but small toy programs on this machine.  This is more like what a student would build in an undergraduate course in computer architecture.For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc.Of course, one wouldn’t implement all of these in a few hours.The fact that this is RISCV is somewhat of a red herring as you could do a similar thing with a restricted subset of MIPS or ARM or even x86 as they do in UT Austin’s comp arch class.