I tested four NVMe SSDs from four vendors – half lose FLUSH’d data on power loss
I always liked the embedded system model where you get flash hardware that has two operations -- erase block and write block.  GC, RAID, error correction, etc. are then handled at the application level.  It was never clear to me that the current tradeoff with consumer-grade SSDs was right.  On the one hand, things like the error correction, redundancy, and garbage collection don't require the attention from CPU (and more importantly, doesn't tie up any bus).  On the other hand, the user has no control over what the software on the SSD's chip does.  Clearly vendors and users are at odds with each other here; vendors want the best benchmarks (so you can sort by speed descending and pick the first one), but users want their files to exist after their power goes out.It would be nice if we could just buy dumb flash and let the application do whatever it wants (I guess that application would be your filesystem; but it could also be direct access for specialized use cases like databases).   If you want maximum speed, adjust your settings for that.  If you want maximum write durability, adjust your settings for that.  People are always looking for that one size fits all use case, but it's hard here.  Some people may be running cloud providers and already have software to store that block on 3 different continents.  Some people may be an embedded system with a fixed disk image that changes once a year, with some temporary storage for logs.  There probably isn't a single setting that gets optimal use out of the flash memory for both use cases.  The cloud provider doesn't care if a block, flash chip, drive, server rack, availability zone, or continent goes away.  The embedded system may be happy to lose logs in exchange for having enough writes left to install the next security update.It's all a mess, but the constraints have changed since we made the mess.  You used to be happy to get 1/6th of a PCI Express lane for all your storage.  Now processors directly expose 128 PCIe lanes and have a multitude of underused efficiency cores waiting to be used.  Maybe we could do all the "smart" stuff in the OS and application code, and just attach commodity dumb flash chips to our computer.