FPGA Interchange format to enable interoperable FPGA tooling
I'm really interested in this subject. What with it being my job. I've thought about this a lot, and the fundamental problem for me is that you have RTLs, but these don't mean anything, they're a cruel joke on engineering students "Oh sure, you can do that in this language but does it map."The problem is that really it's only a tiny subset of RTL languages that are supported by FPGAs, and an even tinier subset that's optimial. God alone can write 10 lines of RTL that'll map to DSP blocks utilizing the carry chain. The problem isn't that the languages don't support multiple targets, it's that the targets are so idiosyncratic that you have to know exactly how it maps.Now, what this format promises to do encompasses describing the resources on a device, but there's a few problems with this. Firstly, they're incredibly complex in terms of trade-offs (you can do X Y Z but X only in A mode Y in all modes but B, Z but the timing of N is off). The likely result of this are a set of simplified rules that make it tractable, but not performant. Secondly, since the only way of getting optimal hardware is to design it for one target - an interchange format seems like nonsense. It's exactly like RTL - it describes everything but doesn't functionally help you translate between targets at all.Fundamentally this just doesn't seem like it solves anything, it's seems to suggest "Hey guys, adopt our standard for all your stuff!", but why? They don't seem to be offering anything of value.If I were being particularly glib, I'd wish a swift promotion to the guys at Google who authored this.