The Reduceron, a CPU designed for functional programs
The x86 architecture is a modified Harvard architecture where close to the CPU (L1 cache) memory is divided into 'instructions' and 'data', further from the CPU the memory is joined.  L2, L3 and RAM are generally 'unified' or can contain either 'instructions' or 'data'.This thesis proposes that separating memory to 'instructions', 'stack', and 'heap' results in a performance increase for functional languages.Additionally this is targeted at software that makes a large number of function calls such that the time expense of function calls with current architectures is higher than the actually computational time expense of the code.Personal opinion: Maybe this is faster at the inner most levels of memory if the code makes lots of function calls.  At the outer most levels of memory many things rely on the ability of 'memory' to be treated as either 'data' or 'instructions'.  JIT compilation for instance.  This would imply that to run general code there needs to be a separation process similar to what occurs between the L2 and L1 caches in current processors.  I'm not sure this ultimately would result in a performance increase for general purpose processors.