\clearpage
\phantomsection
\addcontentsline{toc}{subsection}{OR}
\label{insn:or}
\subsection*{OR: Bitwise Or}

\subsubsection*{Format}

\textrm{OR \%rd, \%r1, \%r2}

\begin{center}
\begin{bytefield}[endianness=big,bitformatting=\scriptsize]{32}
\bitheader{0,7,8,15,16,23,24,31} \\
\bitbox{8}{0x01}
\bitbox{8}{r1}
\bitbox{8}{r2}
\bitbox{8}{rd}
\end{bytefield}
\end{center}

\subsubsection*{Description}

This instruction calculates the bitwise \emph{or} of the values found
in registers \register{r1} and \register{r2}, placing the results in
register \register{rd}.

\subsubsection*{Pseudocode}

\begin{verbatim}
%rd = %r1 | %r2
\end{verbatim}

\subsubsection*{Load-time constraints}
The registers \registerop{r1}, \registerop{r2} and \registerop{rd} must be
valid registers and \registerop{rd} must not be \registerop{r0}.

\subsubsection*{Failure modes}

This instruction has no run-time failure modes beyond its constraints.
