In this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit, choice of an algorithm from a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the Genetic Algorithm is used in order to construct an accurate model for some existing test generation algorithms that are being used everywhere in the world. Some objective quantitative measures are used as an effective tool in making such choice. Such measures are so important to the analysis of algorithms that they become one of the subjects of this work. This is a preview of subscription content, log in to check access. Buy single articleInstant access to the full article PDF. Price includes VAT for USASubscribe to journalImmediate online access to all issues from 2019. Subscription will auto renew annually. This is the net price. Taxes to be calculated in checkout. Johnson B W. Design and Analysis of Fault-Tolerant Digital Systems. Reading, Mass.: Addison-Wesley Pub. Co., 1989. Roth J P. Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and Development, July 1966, 10(4): 278–291. Roth J P, Bouricius W G, Schneider P R. Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits. IEEE Trans. Electronic Computers, October 1967, EC-16(10): 567–579. Abramovici M, Breuer M A, Friedman A D. Digital Systems Testing and Testable Design. Computer Science Press, 1990. Schneider P R. On the necessity to examine D-chains in diagnostic test generation. IBM Journal of Research and Development, January 1967, 11(1): 14. Goel P. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans. Computers, March 1981, C-30(3): 215–222. Fujiwara H, Shimono T. On the acceleration of test generation algorithms. IEEE Trans. Computers, December 1983, C-32(12): 1137–1144. Cha C W, Donath W E, Ozguner F. 9-V algorithm for test pattern generation of combinational digital circuits. IEEE Trans. Computers, March 1978, C-27(3): 193–200. Muth P. A nine-valued circuit model for test generation. IEEE Trans. Computers, June 1976, C-25(6): 630–636. Kirkland T, Mercer M R. A topological search algorithm for ATPG. InProc. 24th Design Automation Conf., June 1987, pp.502–508. Abramovici M, Kulikowski J J, Menon P R, Miller D T. SMART and FAST: Test generation for VLSI scan-design circuits. IEEE Design & Test of Computers, Aug. 1986, 3(4): 43–54. Xu Shiyi, Frank T J. An evaluation of test generation algorithms for combinational circuits. InProc. IEEE the Eighth Asian Test Symposium, Nov. 1999, pp.63–69. Xi Shiyi, Dias G P. Testability forecasting for sequential circuit. InProc. IEEE the Fourth Asian Test Symposium, Nov. 1995, pp.199–205. Hu Yang. Testability Forecasting for Combinational Circuits Using Neural Networks. Master’s Degree Thesis, Shanghai University, 1997. Xu Shiyi, Peter Waiganjo, Dias G P. Testability prediction for sequential circuits using neural networks. InProc. IEEE the Sixth Asian Test Symposium, Nov. 1997, pp.126–132. Mahfoud S, Mani G. Financial forecasting using genetic algorithms. Applied Artificial Intelligence, 1996, 10(6): 543–565. Michalewicz Z. Genetic Algorithms+Data Structures=Evolution Programs. Berlin: Springer-Verlag, 1994. Russell S J, Norvig P. Artificial Intelligence: A Modern Approach. Englewood Cliffs, N.J.: Prentice Hall Inc., 1995, pp.619–620. Welstead S T. Neural Network and Fuzzy Logic Applications in C/C++. New York: John Wiley & Sons Inc., 1994, pp.283–304. Schwefel H-P. Numerical Optimization for Computer Models. John Wiley, Chichester, UK, 1981. Fogel L J, Owens A J, Walsh M J. Artificial Intelligence Through Simulated Evolution. John Wiley, Chichester, UK, 1966. Glover F. Heuristics for integer programming using surrogate constraints. Decision Sciences, 1977, 8(1): 156–166. Holland J H. Adaptation in Natural and Artificial Systems. University of Michigan Press, Ann Arbor, 1975. Koza J R. Genetic Programming. MIT Press, Cambridge, MA, 1991. Brglez F, Fujiwara H. A Neural Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN. International Test Symposium on Circuits and Systems, June 1985. The Bipolar Digital Integrated circuits Data Book for Design Engineers, pt.i: TTL & Interface Instruments.-Dallas: Texas Instruments Inc., 1982. This work was supported by National Natural Science Foundation of China (NSFC) under grant No.69873030 and AM (Applied Material Co.) Foundation of the United States. About this articleCite this articleXu, S., Frank, T.J. Forecasting the efficiency of test generation algorithms for combinational circuits. J. Comput. Sci. & Technol. 15, 326–337 (2000). https://doi.org/10.1007/BF02948868- genetic algorithm- test generation