s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | ((cmd->msg_len-1) << 4) | 0x08); 
s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | ((cmd->msg_len-1) << 4) | 0x08); 
static int s5h1420_send_master_cmd (struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd){	struct s5h1420_state* state = fe->demodulator_priv;	u8 val;	int i;	unsigned long timeout;	int result = 0;	/* setup for DISEQC */	val = s5h1420_readreg(state, 0x3b);	s5h1420_writereg(state, 0x3b, 0x02);	msleep(15);	/* write the DISEQC command bytes */	for(i=0; i< cmd->msg_len; i++) {		s5h1420_writereg(state, 0x3c + i, cmd->msg[i]);	}	/* kick off transmission */	s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | ((cmd->msg_len-1) << 4) | 0x08);	/* wait for transmission to complete */	timeout = jiffies + ((100*HZ) / 1000);	while(time_before(jiffies, timeout)) {		if (s5h1420_readreg(state, 0x3b) & 0x08)			break;		msleep(5);	}	if (time_after(jiffies, timeout))		result = -ETIMEDOUT;	/* restore original settings */	s5h1420_writereg(state, 0x3b, val);	msleep(15);	return result;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/a9d6a80b41c04e8ff4c7442cc35f5df610863841/s5h1420.c/buggy/drivers/media/dvb/frontends/s5h1420.c