apic_write_around(APIC_LDR, val); 
apic_write(APIC_LDR, val); 
static void cluster_init_apic_ldr(void){	unsigned long val, id;	long i, count;	u8 lid;	u8 my_id = hard_smp_processor_id();	u8 my_cluster = APIC_CLUSTER(my_id);	/* Create logical APIC IDs by counting CPUs already in cluster. */	for (count = 0, i = NR_CPUS; --i >= 0; ) {		lid = x86_cpu_to_log_apicid[i];		if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)			++count;	}	/*	 * We only have a 4 wide bitmap in cluster mode.  There's no way	 * to get above 60 CPUs and still give each one it's own bit.	 * But, we're using physical IRQ delivery, so we don't care.	 * Use bit 3 for the 4th through Nth CPU in each cluster.	 */	if (count >= XAPIC_DEST_CPUS_SHIFT)		count = 3;	id = my_cluster | (1UL << count);	x86_cpu_to_log_apicid[smp_processor_id()] = id;	apic_write_around(APIC_DFR, APIC_DFR_CLUSTER);	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;	val |= SET_APIC_LOGICAL_ID(id);	apic_write_around(APIC_LDR, val);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/eddfb4ed290383abf912630fa8dac5acf65c9e55/genapic_cluster.c/buggy/arch/x86_64/kernel/genapic_cluster.c