* Work around a bug in the Oxford Semiconductor 952 rev B * chip which causes it to seriously miscalculate baud rates * when DLL is 0. 
* Oxford Semi 952 rev B workaround 
serial8250_set_termios(struct uart_port *port, struct termios *termios,		       struct termios *old){	struct uart_8250_port *up = (struct uart_8250_port *)port;	unsigned char cval, fcr = 0;	unsigned long flags;	unsigned int baud, quot;	switch (termios->c_cflag & CSIZE) {	case CS5:		cval = 0x00;		break;	case CS6:		cval = 0x01;		break;	case CS7:		cval = 0x02;		break;	default:	case CS8:		cval = 0x03;		break;	}	if (termios->c_cflag & CSTOPB)		cval |= 0x04;	if (termios->c_cflag & PARENB)		cval |= UART_LCR_PARITY;	if (!(termios->c_cflag & PARODD))		cval |= UART_LCR_EPAR;#ifdef CMSPAR	if (termios->c_cflag & CMSPAR)		cval |= UART_LCR_SPAR;#endif	/*	 * Ask the core to calculate the divisor for us.	 */	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 	quot = serial8250_get_divisor(port, baud);	/*	 * Work around a bug in the Oxford Semiconductor 952 rev B	 * chip which causes it to seriously miscalculate baud rates	 * when DLL is 0.	 */	if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&	    up->rev == 0x5201)		quot ++;	if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {		if (baud < 2400)			fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;		else			fcr = uart_config[up->port.type].fcr;	}	/*	 * MCR-based auto flow control.  When AFE is enabled, RTS will be	 * deasserted when the receive FIFO contains more characters than	 * the trigger, or the MCR RTS bit is cleared.  In the case where	 * the remote UART is not using CTS auto flow control, we must	 * have sufficient FIFO entries for the latency of the remote	 * UART to respond.  IOW, at least 32 bytes of FIFO.	 */	if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {		up->mcr &= ~UART_MCR_AFE;		if (termios->c_cflag & CRTSCTS)			up->mcr |= UART_MCR_AFE;	}	/*	 * Ok, we're now changing the port state.  Do it with	 * interrupts disabled.	 */	spin_lock_irqsave(&up->port.lock, flags);	/*	 * Update the per-port timeout.	 */	uart_update_timeout(port, termios->c_cflag, baud);	up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;	if (termios->c_iflag & INPCK)		up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;	if (termios->c_iflag & (BRKINT | PARMRK))		up->port.read_status_mask |= UART_LSR_BI;	/*	 * Characteres to ignore	 */	up->port.ignore_status_mask = 0;	if (termios->c_iflag & IGNPAR)		up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;	if (termios->c_iflag & IGNBRK) {		up->port.ignore_status_mask |= UART_LSR_BI;		/*		 * If we're ignoring parity and break indicators,		 * ignore overruns too (for real raw support).		 */		if (termios->c_iflag & IGNPAR)			up->port.ignore_status_mask |= UART_LSR_OE;	}	/*	 * ignore all characters if CREAD is not set	 */	if ((termios->c_cflag & CREAD) == 0)		up->port.ignore_status_mask |= UART_LSR_DR;	/*	 * CTS flow control flag and modem status interrupts	 */	up->ier &= ~UART_IER_MSI;	if (UART_ENABLE_MS(&up->port, termios->c_cflag))		up->ier |= UART_IER_MSI;	if (up->capabilities & UART_CAP_UUE)		up->ier |= UART_IER_UUE | UART_IER_RTOIE;	serial_out(up, UART_IER, up->ier);	if (up->capabilities & UART_CAP_EFR) {		unsigned char efr = 0;		/*		 * TI16C752/Startech hardware flow control.  FIXME:		 * - TI16C752 requires control thresholds to be set.		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.		 */		if (termios->c_cflag & CRTSCTS)			efr |= UART_EFR_CTS;		serial_outp(up, UART_LCR, 0xBF);		serial_outp(up, UART_EFR, efr);	}	if (up->capabilities & UART_NATSEMI) {		/* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */		serial_outp(up, UART_LCR, 0xe0);	} else {		serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */	}	serial_outp(up, UART_DLL, quot & 0xff);		/* LS of divisor */	serial_outp(up, UART_DLM, quot >> 8);		/* MS of divisor */	/*	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR	 * is written without DLAB set, this mode will be disabled.	 */	if (up->port.type == PORT_16750)		serial_outp(up, UART_FCR, fcr);	serial_outp(up, UART_LCR, cval);		/* reset DLAB */	up->lcr = cval;					/* Save LCR */	if (up->port.type != PORT_16750) {		if (fcr & UART_FCR_ENABLE_FIFO) {			/* emulated UARTs (Lucent Venus 167x) need two steps */			serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);		}		serial_outp(up, UART_FCR, fcr);		/* set fcr */	}	serial8250_set_mctrl(&up->port, up->port.mctrl);	spin_unlock_irqrestore(&up->port.lock, flags);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/4ba5e35daa90871fcb9b01f5ad1e5723343cc0a9/8250.c/buggy/drivers/serial/8250.c