flags_save = tp->tg3_flags; tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG; 
write_op = tp->write32; if (write_op == tg3_write_flush_reg32) tp->write32 = tg3_write32; 
static int tg3_chip_reset(struct tg3 *tp){	u32 val;	u32 flags_save;	int i;	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))		tg3_nvram_lock(tp);	/*	 * We must avoid the readl() that normally takes place.	 * It locks machines, causes machine checks, and other	 * fun things.  So, temporarily disable the 5701	 * hardware workaround, while we do the reset.	 */	flags_save = tp->tg3_flags;	tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;	/* do the reset */	val = GRC_MISC_CFG_CORECLK_RESET;	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {		if (tr32(0x7e2c) == 0x60) {			tw32(0x7e2c, 0x20);		}		if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {			tw32(GRC_MISC_CFG, (1 << 29));			val |= (1 << 29);		}	}	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)		val |= GRC_MISC_CFG_KEEP_GPHY_POWER;	tw32(GRC_MISC_CFG, val);	/* restore 5701 hardware bug workaround flag */	tp->tg3_flags = flags_save;	/* Unfortunately, we have to delay before the PCI read back.	 * Some 575X chips even will not respond to a PCI cfg access	 * when the reset command is given to the chip.	 *	 * How do these hardware designers expect things to work	 * properly if the PCI write is posted for a long period	 * of time?  It is always necessary to have some method by	 * which a register read back can occur to push the write	 * out which does the reset.	 *	 * For most tg3 variants the trick below was working.	 * Ho hum...	 */	udelay(120);	/* Flush PCI posted writes.  The normal MMIO registers	 * are inaccessible at this time so this is the only	 * way to make this reliably (actually, this is no longer	 * the case, see above).  I tried to use indirect	 * register read/write but this upset some 5701 variants.	 */	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);	udelay(120);	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {		if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {			int i;			u32 cfg_val;			/* Wait for link training to complete.  */			for (i = 0; i < 5000; i++)				udelay(100);			pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);			pci_write_config_dword(tp->pdev, 0xc4,					       cfg_val | (1 << 15));		}		/* Set PCIE max payload size and clear error status.  */		pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);	}	/* Re-enable indirect register accesses. */	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,			       tp->misc_host_ctrl);	/* Set MAX PCI retry to zero. */	val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE))		val |= PCISTATE_RETRY_SAME_DMA;	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);	pci_restore_state(tp->pdev);	/* Make sure PCI-X relaxed ordering bit is clear. */	pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);	val &= ~PCIX_CAPS_RELAXED_ORDERING;	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {		u32 val;		/* Chip reset on 5780 will reset MSI enable bit,		 * so need to restore it.		 */		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {			u16 ctrl;			pci_read_config_word(tp->pdev,					     tp->msi_cap + PCI_MSI_FLAGS,					     &ctrl);			pci_write_config_word(tp->pdev,					      tp->msi_cap + PCI_MSI_FLAGS,					      ctrl | PCI_MSI_FLAGS_ENABLE);			val = tr32(MSGINT_MODE);			tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);		}		val = tr32(MEMARB_MODE);		tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);	} else		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);	if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {		tg3_stop_fw(tp);		tw32(0x5000, 0x400);	}	tw32(GRC_MODE, tp->grc_mode);	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {		u32 val = tr32(0xc4);		tw32(0xc4, val | (1 << 15));	}	if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {		tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;		if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)			tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);	}	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {		tp->mac_mode = MAC_MODE_PORT_MODE_TBI;		tw32_f(MAC_MODE, tp->mac_mode);	} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {		tp->mac_mode = MAC_MODE_PORT_MODE_GMII;		tw32_f(MAC_MODE, tp->mac_mode);	} else		tw32_f(MAC_MODE, 0);	udelay(40);	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {		/* Wait for firmware initialization to complete. */		for (i = 0; i < 100000; i++) {			tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);			if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)				break;			udelay(10);		}		if (i >= 100000) {			printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "			       "firmware will not restart magic=%08x\n",			       tp->dev->name, val);			return -ENODEV;		}	}	if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&	    tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {		u32 val = tr32(0x7c00);		tw32(0x7c00, val | (1 << 25));	}	/* Reprobe ASF enable state.  */	tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;	tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);	if (val == NIC_SRAM_DATA_SIG_MAGIC) {		u32 nic_cfg;		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;		}	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/1ee582d8e49a1c9dd43b2599f1cd26507182a8d4/tg3.c/clean/drivers/net/tg3.c