/* Accept unsolicited responses */ azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);  
static int azx_reset(azx_t *chip){	int count;	/* reset controller */	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);	count = 50;	while (azx_readb(chip, GCTL) && --count)		msleep(1);	/* delay for >= 100us for codec PLL to settle per spec	 * Rev 0.9 section 5.5.1	 */	msleep(1);	/* Bring controller out of reset */	azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);	count = 50;	while (! azx_readb(chip, GCTL) && --count)		msleep(1);	/* Brent Chartrand said to wait >= 540us for codecs to intialize */	msleep(1);	/* check to see if controller is ready */	if (! azx_readb(chip, GCTL)) {		snd_printd("azx_reset: controller not ready!\n");		return -EBUSY;	}	/* detect codecs */	if (! chip->codec_mask) {		chip->codec_mask = azx_readw(chip, STATESTS);		snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/41e2fce431070cb2d91391808077378582d3e6b1/hda_intel.c/clean/sound/pci/hda/hda_intel.c