static void __init schizo_base_address_update(struct pci_dev *pdev, int resource) 
static void schizo_base_address_update(struct pci_dev *pdev, int resource) 
static void __init schizo_base_address_update(struct pci_dev *pdev, int resource){	struct pcidev_cookie *pcp = pdev->sysdata;	struct pci_pbm_info *pbm = pcp->pbm;	struct resource *res, *root;	u32 reg;	int where, size, is_64bit;	res = &pdev->resource[resource];	if (resource < 6) {		where = PCI_BASE_ADDRESS_0 + (resource * 4);	} else if (resource == PCI_ROM_RESOURCE) {		where = pdev->rom_base_reg;	} else {		/* Somebody might have asked allocation of a non-standard resource */		return;	}	is_64bit = 0;	if (res->flags & IORESOURCE_IO)		root = &pbm->io_space;	else {		root = &pbm->mem_space;		if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)		    == PCI_BASE_ADDRESS_MEM_TYPE_64)			is_64bit = 1;	}	size = res->end - res->start;	pci_read_config_dword(pdev, where, &reg);	reg = ((reg & size) |	       (((u32)(res->start - root->start)) & ~size));	if (resource == PCI_ROM_RESOURCE) {		reg |= PCI_ROM_ADDRESS_ENABLE;		res->flags |= IORESOURCE_ROM_ENABLE;	}	pci_write_config_dword(pdev, where, reg);	/* This knows that the upper 32-bits of the address	 * must be zero.  Our PCI common layer enforces this.	 */	if (is_64bit)		pci_write_config_dword(pdev, where + 4, 0);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_schizo.c/clean/arch/sparc64/kernel/pci_schizo.c