if (chip->position_fix == POS_FIX_POSBUF) { /* enable the position buffer */ if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); } 
/* enable the position buffer */ if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 
static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev){	unsigned char val;	int timeout;	/* make sure the run bit is zero for SD */	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);	/* reset stream */	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);	udelay(3);	timeout = 300;	while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&	       --timeout)		;	val &= ~SD_CTL_STREAM_RESET;	azx_sd_writeb(azx_dev, SD_CTL, val);	udelay(3);	timeout = 300;	/* waiting for hardware to report that the stream is out of reset */	while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&	       --timeout)		;	/* program the stream_tag */	azx_sd_writel(azx_dev, SD_CTL,		      (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |		      (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));	/* program the length of samples in cyclic buffer */	azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);	/* program the stream format */	/* this value needs to be the same as the one programmed */	azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);	/* program the stream LVI (last valid index) of the BDL */	azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);	/* program the BDL address */	/* lower BDL address */	azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);	/* upper BDL address */	azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));	if (chip->position_fix == POS_FIX_POSBUF) {		/* enable the position buffer */		if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))			azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);	}	/* set the interrupt enable bits in the descriptor control register */	azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/0be3b5d3fb94c36c517655d18a936681d7108667/hda_intel.c/clean/sound/pci/hda/hda_intel.c