struct ixgb_adapter *adapter = netdev->priv; 
struct ixgb_adapter *adapter = netdev_priv(netdev); 
ixgb_intr(int irq, void *data, struct pt_regs *regs){	struct net_device *netdev = data;	struct ixgb_adapter *adapter = netdev->priv;	struct ixgb_hw *hw = &adapter->hw;	uint32_t icr = IXGB_READ_REG(hw, ICR);#ifndef CONFIG_IXGB_NAPI	unsigned int i;#endif	if(unlikely(!icr))		return IRQ_NONE;  /* Not our interrupt */	if(unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC))) {		mod_timer(&adapter->watchdog_timer, jiffies);	}#ifdef CONFIG_IXGB_NAPI	if(netif_rx_schedule_prep(netdev)) {		/* Disable interrupts and register for poll. The flush 		  of the posted write is intentionally left out.		*/		atomic_inc(&adapter->irq_sem);		IXGB_WRITE_REG(&adapter->hw, IMC, ~0);		__netif_rx_schedule(netdev);	}#else	/* yes, that is actually a & and it is meant to make sure that	 * every pass through this for loop checks both receive and	 * transmit queues for completed descriptors, intended to	 * avoid starvation issues and assist tx/rx fairness. */	for(i = 0; i < IXGB_MAX_INTR; i++)		if(!ixgb_clean_rx_irq(adapter) &		   !ixgb_clean_tx_irq(adapter))			break;#endif 	return IRQ_HANDLED;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/8908c6cd1d6889850148aeb50bb14301959adaa7/ixgb_main.c/buggy/drivers/net/ixgb/ixgb_main.c