VerticalRetraceWait(); vga_out8 (0x3d4, 0x67); cr67 = vga_in8 (0x3d5); vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c); /* no STREAMS yet */  vga_out8 (0x3d4, 0x23); vga_out8 (0x3d5, 0x00); vga_out8 (0x3d4, 0x26); vga_out8 (0x3d5, 0x00); 
VerticalRetraceWait(par); vga_out8 (0x3d4, 0x67, par); cr67 = vga_in8 (0x3d5, par); vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */  vga_out8 (0x3d4, 0x23, par); vga_out8 (0x3d5, 0x00, par); vga_out8 (0x3d4, 0x26, par); vga_out8 (0x3d5, 0x00, par); 
static void savagefb_set_par_int (struct savagefb_par  *par){	unsigned char tmp, cr3a, cr66, cr67;	DBG ("savagefb_set_par_int");	par->SavageWaitIdle (par);	vga_out8 (0x3c2, 0x23);	vga_out16 (0x3d4, 0x4838);	vga_out16 (0x3d4, 0xa539);	vga_out16 (0x3c4, 0x0608);	vgaHWProtect (par, 1);	/*	 * Some Savage/MX and /IX systems go nuts when trying to exit the	 * server after WindowMaker has displayed a gradient background.  I	 * haven't been able to find what causes it, but a non-destructive	 * switch to mode 3 here seems to eliminate the issue.	 */	VerticalRetraceWait();	vga_out8 (0x3d4, 0x67);	cr67 = vga_in8 (0x3d5);	vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c); /* no STREAMS yet */	vga_out8 (0x3d4, 0x23);	vga_out8 (0x3d5, 0x00);	vga_out8 (0x3d4, 0x26);	vga_out8 (0x3d5, 0x00);	/* restore extended regs */	vga_out8 (0x3d4, 0x66);	vga_out8 (0x3d5, par->CR66);	vga_out8 (0x3d4, 0x3a);	vga_out8 (0x3d5, par->CR3A);	vga_out8 (0x3d4, 0x31);	vga_out8 (0x3d5, par->CR31);	vga_out8 (0x3d4, 0x32);	vga_out8 (0x3d5, par->CR32);	vga_out8 (0x3d4, 0x58);	vga_out8 (0x3d5, par->CR58);	vga_out8 (0x3d4, 0x53);	vga_out8 (0x3d5, par->CR53 & 0x7f);	vga_out16 (0x3c4, 0x0608);	/* Restore DCLK registers. */	vga_out8 (0x3c4, 0x0e);	vga_out8 (0x3c5, par->SR0E);	vga_out8 (0x3c4, 0x0f);	vga_out8 (0x3c5, par->SR0F);	vga_out8 (0x3c4, 0x29);	vga_out8 (0x3c5, par->SR29);	vga_out8 (0x3c4, 0x15);	vga_out8 (0x3c5, par->SR15);	/* Restore flat panel expansion regsters. */	if( par->chip == S3_SAVAGE_MX ) {		int i;		for( i = 0; i < 8; i++ ) {			vga_out8 (0x3c4, 0x54+i);			vga_out8 (0x3c5, par->SR54[i]);		}	}	vgaHWRestore (par);	/* extended mode timing registers */	vga_out8 (0x3d4, 0x53);	vga_out8 (0x3d5, par->CR53);	vga_out8 (0x3d4, 0x5d);	vga_out8 (0x3d5, par->CR5D);	vga_out8 (0x3d4, 0x5e);	vga_out8 (0x3d5, par->CR5E);	vga_out8 (0x3d4, 0x3b);	vga_out8 (0x3d5, par->CR3B);	vga_out8 (0x3d4, 0x3c);	vga_out8 (0x3d5, par->CR3C);	vga_out8 (0x3d4, 0x43);	vga_out8 (0x3d5, par->CR43);	vga_out8 (0x3d4, 0x65);	vga_out8 (0x3d5, par->CR65);	/* restore the desired video mode with cr67 */	vga_out8 (0x3d4, 0x67);	/* following part not present in X11 driver */	cr67 = vga_in8 (0x3d5) & 0xf;	vga_out8 (0x3d5, 0x50 | cr67);	udelay (10000);	vga_out8 (0x3d4, 0x67);	/* end of part */	vga_out8 (0x3d5, par->CR67 & ~0x0c);	/* other mode timing and extended regs */	vga_out8 (0x3d4, 0x34);	vga_out8 (0x3d5, par->CR34);	vga_out8 (0x3d4, 0x40);	vga_out8 (0x3d5, par->CR40);	vga_out8 (0x3d4, 0x42);	vga_out8 (0x3d5, par->CR42);	vga_out8 (0x3d4, 0x45);	vga_out8 (0x3d5, par->CR45);	vga_out8 (0x3d4, 0x50);	vga_out8 (0x3d5, par->CR50);	vga_out8 (0x3d4, 0x51);	vga_out8 (0x3d5, par->CR51);	/* memory timings */	vga_out8 (0x3d4, 0x36);	vga_out8 (0x3d5, par->CR36);	vga_out8 (0x3d4, 0x60);	vga_out8 (0x3d5, par->CR60);	vga_out8 (0x3d4, 0x68);	vga_out8 (0x3d5, par->CR68);	vga_out8 (0x3d4, 0x69);	vga_out8 (0x3d5, par->CR69);	vga_out8 (0x3d4, 0x6f);	vga_out8 (0x3d5, par->CR6F);	vga_out8 (0x3d4, 0x33);	vga_out8 (0x3d5, par->CR33);	vga_out8 (0x3d4, 0x86);	vga_out8 (0x3d5, par->CR86);	vga_out8 (0x3d4, 0x88);	vga_out8 (0x3d5, par->CR88);	vga_out8 (0x3d4, 0x90);	vga_out8 (0x3d5, par->CR90);	vga_out8 (0x3d4, 0x91);	vga_out8 (0x3d5, par->CR91);	if (par->chip == S3_SAVAGE4) {		vga_out8 (0x3d4, 0xb0);		vga_out8 (0x3d5, par->CRB0);	}	vga_out8 (0x3d4, 0x32);	vga_out8 (0x3d5, par->CR32);	/* unlock extended seq regs */	vga_out8 (0x3c4, 0x08);	vga_out8 (0x3c5, 0x06);	/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates	 * that we should leave the default SR10 and SR11 values there.	 */	if (par->SR10 != 255) {		vga_out8 (0x3c4, 0x10);		vga_out8 (0x3c5, par->SR10);		vga_out8 (0x3c4, 0x11);		vga_out8 (0x3c5, par->SR11);	}	/* restore extended seq regs for dclk */	vga_out8 (0x3c4, 0x0e);	vga_out8 (0x3c5, par->SR0E);	vga_out8 (0x3c4, 0x0f);	vga_out8 (0x3c5, par->SR0F);	vga_out8 (0x3c4, 0x12);	vga_out8 (0x3c5, par->SR12);	vga_out8 (0x3c4, 0x13);	vga_out8 (0x3c5, par->SR13);	vga_out8 (0x3c4, 0x29);	vga_out8 (0x3c5, par->SR29);	vga_out8 (0x3c4, 0x18);	vga_out8 (0x3c5, par->SR18);	/* load new m, n pll values for dclk & mclk */	vga_out8 (0x3c4, 0x15);	tmp = vga_in8 (0x3c5) & ~0x21;	vga_out8 (0x3c5, tmp | 0x03);	vga_out8 (0x3c5, tmp | 0x23);	vga_out8 (0x3c5, tmp | 0x03);	vga_out8 (0x3c5, par->SR15);	udelay (100);	vga_out8 (0x3c4, 0x30);	vga_out8 (0x3c5, par->SR30);	vga_out8 (0x3c4, 0x08);	vga_out8 (0x3c5, par->SR08);	/* now write out cr67 in full, possibly starting STREAMS */	VerticalRetraceWait();	vga_out8 (0x3d4, 0x67);	vga_out8 (0x3d5, par->CR67);	vga_out8 (0x3d4, 0x66);	cr66 = vga_in8 (0x3d5);	vga_out8 (0x3d5, cr66 | 0x80);	vga_out8 (0x3d4, 0x3a);	cr3a = vga_in8 (0x3d5);	vga_out8 (0x3d5, cr3a | 0x80);	if (par->chip != S3_SAVAGE_MX) {		VerticalRetraceWait();		savage_out32 (FIFO_CONTROL_REG, par->MMPR0);		par->SavageWaitIdle (par);		savage_out32 (MIU_CONTROL_REG, par->MMPR1);		par->SavageWaitIdle (par);		savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2);		par->SavageWaitIdle (par);		savage_out32 (MISC_TIMEOUT_REG, par->MMPR3);	}	vga_out8 (0x3d4, 0x66);	vga_out8 (0x3d5, cr66);	vga_out8 (0x3d4, 0x3a);	vga_out8 (0x3d5, cr3a);	SavageSetup2DEngine (par);	vgaHWProtect (par, 0);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/1cc650c69f3079ce3c616c998a741bcf6ddf4f4d/savagefb_driver.c/buggy/drivers/video/savage/savagefb_driver.c