} while(((long)pci_iommu_read(matchreg)) < 0L); 
udelay(1); } 
static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages){	int limit;	PCI_STC_FLUSHFLAG_INIT(strbuf);	if (strbuf->strbuf_ctxflush &&	    iommu->iommu_ctxflush) {		unsigned long matchreg, flushreg;		flushreg = strbuf->strbuf_ctxflush;		matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);		limit = 10000;		do {			pci_iommu_write(flushreg, ctx);			udelay(10);			limit--;			if (!limit)				break;		} while(((long)pci_iommu_read(matchreg)) < 0L);		if (!limit)			printk(KERN_WARNING "pci_strbuf_flush: ctx flush "			       "timeout vaddr[%08x] ctx[%lx]\n",			       vaddr, ctx);	} else {		unsigned long i;		for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)			pci_iommu_write(strbuf->strbuf_pflush, vaddr);	}	pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);	(void) pci_iommu_read(iommu->write_complete_reg);	limit = 10000;	while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {		limit--;		if (!limit)			break;		udelay(10);		membar("#LoadLoad");	}	if (!limit)		printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "		       "vaddr[%08x] ctx[%lx] npages[%ld]\n",		       vaddr, ctx, npages);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a228dfd5dc4b92288ea22d427b2bfc48ba5bb8b0/pci_iommu.c/clean/arch/sparc64/kernel/pci_iommu.c