DBG("bridge_startup(): irq= 0x%x  pin=%d\n", irq, pin); 
pr_debug("bridge_startup(): irq= 0x%x  pin=%d\n", irq, pin); 
static unsigned int startup_bridge_irq(unsigned int irq){	struct bridge_controller *bc;	bridgereg_t device;	bridge_t *bridge;	int pin, swlevel;	cpuid_t cpu;	pin = SLOT_FROM_PCI_IRQ(irq);	bc = IRQ_TO_BRIDGE(irq);	bridge = bc->base;	DBG("bridge_startup(): irq= 0x%x  pin=%d\n", irq, pin);	/*	 * "map" irq to a swlevel greater than 6 since the first 6 bits	 * of INT_PEND0 are taken	 */	swlevel = find_level(&cpu, irq);	bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));	bridge->b_int_enable |= (1 << pin);	bridge->b_int_enable |= 0x7ffffe00;	/* more stuff in int_enable */	/*	 * Enable sending of an interrupt clear packt to the hub on a high to	 * low transition of the interrupt pin.	 *	 * IRIX sets additional bits in the address which are documented as	 * reserved in the bridge docs.	 */	bridge->b_int_mode |= (1UL << pin);	/*	 * We assume the bridge to have a 1:1 mapping between devices	 * (slots) and intr pins.	 */	device = bridge->b_int_device;	device &= ~(7 << (pin*3));	device |= (pin << (pin*3));	bridge->b_int_device = device;        bridge->b_wid_tflush;        return 0;       /* Never anything pending.  */}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d3ffd085536c1801da74c098e25fd3985671e15d/ip27-irq.c/buggy/arch/mips/sgi-ip27/ip27-irq.c