/* Setup HT1000 SouthBridge Controller - Single Channel Only */ else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) { pci_read_config_byte(dev, 0x5A, &btr); btr &= ~0x40; btr |= 0x3; pci_write_config_byte(dev, 0x5A, btr); } 
static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name){	unsigned int reg;	u8 btr;	/* save revision id to determine DMA capability */	pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);	/* force Master Latency Timer value to 64 PCICLKs */	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);	/* OSB4 : South Bridge and IDE */	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {		isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,			  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);		if (isa_dev) {			pci_read_config_dword(isa_dev, 0x64, &reg);			reg &= ~0x00002000; /* disable 600ns interrupt mask */			if(!(reg & 0x00004000))				printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);			reg |=  0x00004000; /* enable UDMA/33 support */			pci_write_config_dword(isa_dev, 0x64, reg);		}	}	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {		/* Third Channel Test */		if (!(PCI_FUNC(dev->devfn) & 1)) {			struct pci_dev * findev = NULL;			u32 reg4c = 0;			findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);			if (findev) {				pci_read_config_dword(findev, 0x4C, &reg4c);				reg4c &= ~0x000007FF;				reg4c |=  0x00000040;				reg4c |=  0x00000020;				pci_write_config_dword(findev, 0x4C, reg4c);			}			outb_p(0x06, 0x0c00);			dev->irq = inb_p(0x0c01);#if 0			printk("%s: device class (0x%04x)\n",				name, dev->class);			if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {				dev->class &= ~0x000F0F00;		//		dev->class |= ~0x00000400;				dev->class |= ~0x00010100;				/**/			}#endif		} else {			struct pci_dev * findev = NULL;			u8 reg41 = 0;			findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);			if (findev) {				pci_read_config_byte(findev, 0x41, &reg41);				reg41 &= ~0x40;				pci_write_config_byte(findev, 0x41, reg41);			}			/*			 * This is a device pin issue on CSB6.			 * Since there will be a future raid mode,			 * early versions of the chipset require the			 * interrupt pin to be set, and it is a compatibility			 * mode issue.			 */			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)				dev->irq = 0;		}//		pci_read_config_dword(dev, 0x40, &pioreg)//		pci_write_config_dword(dev, 0x40, 0x99999999);//		pci_read_config_dword(dev, 0x44, &dmareg);//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);		/* setup the UDMA Control register		 *		 * 1. clear bit 6 to enable DMA		 * 2. enable DMA modes with bits 0-1		 * 	00 : legacy		 * 	01 : udma2		 * 	10 : udma2/udma4		 * 	11 : udma2/udma4/udma5		 */		pci_read_config_byte(dev, 0x5A, &btr);		btr &= ~0x40;		if (!(PCI_FUNC(dev->devfn) & 1))			btr |= 0x2;		else			btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;		pci_write_config_byte(dev, 0x5A, btr);	}	return (dev->irq) ? dev->irq : 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/84f57fbc724e3b56dc87c37dddac89f82cf75ef6/serverworks.c/buggy/drivers/ide/pci/serverworks.c