asm volatile ("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 
asm volatile ("lci %%r0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 
ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,		   unsigned long hints){	register unsigned long pa;	register unsigned long ci; /* coherent index */	/* We currently only support kernel addresses */	BUG_ON(sid != KERNEL_SPACE);	mtsp(sid,1);	/*	** WORD 1 - low order word	** "hints" parm includes the VALID bit!	** "dep" clobbers the physical address offset bits as well.	*/	pa = virt_to_phys(vba);	asm volatile("depw  %1,31,12,%0" : "+r" (pa) : "r" (hints));	((u32 *)pdir_ptr)[1] = (u32) pa;	/*	** WORD 0 - high order word	*/#ifdef __LP64__	/*	** get bits 12:15 of physical address	** shift bits 16:31 of physical address	** and deposit them	*/	asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));	asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa));	asm volatile ("depd  %1,35,4,%0" : "+r" (pa) : "r" (ci));#else	pa = 0;#endif	/*	** get CPU coherency index bits	** Grab virtual index [0:11]	** Deposit virt_idx bits into I/O PDIR word	*/	asm volatile ("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));	asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));	asm volatile ("depw  %1,15,12,%0" : "+r" (pa) : "r" (ci));	((u32 *)pdir_ptr)[0] = (u32) pa;	/* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)	**        PCX-U/U+ do. (eg C200/C240)	**        PCX-T'? Don't know. (eg C110 or similar K-class)	**	** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".	** Hopefully we can patch (NOP) these out at boot time somehow.	**	** "Since PCX-U employs an offset hash that is incompatible with	** the real mode coherence index generation of U2, the PDIR entry	** must be flushed to memory to retain coherence."	*/	asm volatile("fdc 0(%0)" : : "r" (pdir_ptr));	asm volatile("sync");}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/86a61ee9c9f3d8b632d29e86ac6610c43ebbb4f0/ccio-dma.c/buggy/drivers/parisc/ccio-dma.c