 /* * If ownes no valid ASID yet, cannot possibly have gotten * this page into the cache. */ if (cpu_context(smp_processor_id(), vma->vm_mm) == 0) return; 
static inline void local_r4k_flush_cache_page(void *args){	struct flush_cache_page_args *fcp_args = args;	struct vm_area_struct *vma = fcp_args->vma;	unsigned long page = fcp_args->page;	int exec = vma->vm_flags & VM_EXEC;	struct mm_struct *mm = vma->vm_mm;	pgd_t *pgdp;	pud_t *pudp;	pmd_t *pmdp;	pte_t *ptep;	page &= PAGE_MASK;	pgdp = pgd_offset(mm, page);	pudp = pud_offset(pgdp, page);	pmdp = pmd_offset(pudp, page);	ptep = pte_offset(pmdp, page);	/*	 * If the page isn't marked valid, the page cannot possibly be	 * in the cache.	 */	if (!(pte_val(*ptep) & _PAGE_PRESENT))		return;	/*	 * Doing flushes for another ASID than the current one is	 * too difficult since stupid R4k caches do a TLB translation	 * for every cache flush operation.  So we do indexed flushes	 * in that case, which doesn't overly flush the cache too much.	 */	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {		if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {			r4k_blast_dcache_page(page);			if (exec && !cpu_icache_snoops_remote_store)				r4k_blast_scache_page(page);		}		if (exec)			r4k_blast_icache_page(page);		return;	}	/*	 * Do indexed flush, too much work to get the (possible) TLB refills	 * to work correctly.	 */	page = INDEX_BASE + (page & (dcache_size - 1));	if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {		r4k_blast_dcache_page_indexed(page);		if (exec && !cpu_icache_snoops_remote_store)			r4k_blast_scache_page_indexed(page);	}	if (exec) {		if (cpu_has_vtag_icache) {			int cpu = smp_processor_id();			if (cpu_context(cpu, vma->vm_mm) != 0)				drop_mmu_context(vma->vm_mm, cpu);		} else			r4k_blast_icache_page_indexed(page);	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/79acf83e509dd0ca3db6c747bf58931984abc6e3/c-r4k.c/buggy/arch/mips/mm/c-r4k.c