if (hw->phy_type == SK_PHY_BCOM) { /* * Workaround BCOM Errata (#10523) for all BCom Phys * Enable Power Management after link up */ xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) & ~PHY_B_AC_DIS_PM); xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); } 
/* * Workaround BCOM Errata (#10523) for all BCom Phys * Enable Power Management after link up */ xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) & ~PHY_B_AC_DIS_PM); xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 
static void genesis_link_up(struct skge_port *skge){	struct skge_hw *hw = skge->hw;	int port = skge->port;	u16 cmd;	u32 mode, msk;	pr_debug("genesis_link_up\n");	cmd = xm_read16(hw, port, XM_MMU_CMD);	/*	 * enabling pause frame reception is required for 1000BT	 * because the XMAC is not reset if the link is going down	 */	if (skge->flow_control == FLOW_MODE_NONE ||	    skge->flow_control == FLOW_MODE_LOC_SEND)		cmd |= XM_MMU_IGN_PF;	else		/* Enable Pause Frame Reception */		cmd &= ~XM_MMU_IGN_PF;	xm_write16(hw, port, XM_MMU_CMD, cmd);	mode = xm_read32(hw, port, XM_MODE);	if (skge->flow_control == FLOW_MODE_SYMMETRIC ||	    skge->flow_control == FLOW_MODE_LOC_SEND) {		/*		 * Configure Pause Frame Generation		 * Use internal and external Pause Frame Generation.		 * Sending pause frames is edge triggered.		 * Send a Pause frame with the maximum pause time if		 * internal oder external FIFO full condition occurs.		 * Send a zero pause time frame to re-start transmission.		 */		/* XM_PAUSE_DA = '010000C28001' (default) */		/* XM_MAC_PTIME = 0xffff (maximum) */		/* remember this value is defined in big endian (!) */		xm_write16(hw, port, XM_MAC_PTIME, 0xffff);		mode |= XM_PAUSE_MODE;		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);	} else {		/*		 * disable pause frame generation is required for 1000BT		 * because the XMAC is not reset if the link is going down		 */		/* Disable Pause Mode in Mode Register */		mode &= ~XM_PAUSE_MODE;		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);	}	xm_write32(hw, port, XM_MODE, mode);	msk = XM_DEF_MSK;	if (hw->phy_type != SK_PHY_XMAC)		msk |= XM_IS_INP_ASS;	/* disable GP0 interrupt bit */	xm_write16(hw, port, XM_IMSK, msk);	xm_read16(hw, port, XM_ISRC);	/* get MMU Command Reg. */	cmd = xm_read16(hw, port, XM_MMU_CMD);	if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)		cmd |= XM_MMU_GMII_FD;	if (hw->phy_type == SK_PHY_BCOM) {		/*		 * Workaround BCOM Errata (#10523) for all BCom Phys		 * Enable Power Management after link up		 */		xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,				  xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)				  & ~PHY_B_AC_DIS_PM);		xm_phy_write(hw, port, PHY_BCOM_INT_MASK,				  PHY_B_DEF_MSK);	}	/* enable Rx/Tx */	xm_write16(hw, port, XM_MMU_CMD,			cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);	skge_link_up(skge);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/89bf5f231f776443a9d65da0f774aa3632534749/skge.c/clean/drivers/net/skge.c