for (i=0; i<8; i++) 
for (i=0; i<7; i++) 
static void radeon_write_mode (struct radeonfb_info *rinfo,                               struct radeon_regs *mode){	int i;	int primary_mon = PRIMARY_MONITOR(rinfo);	radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);	if (rinfo->arch == RADEON_M6) {		for (i=0; i<8; i++)			OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);	} else {		for (i=0; i<9; i++)			OUTREG(common_regs[i].reg, common_regs[i].val);	}	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,		CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);	OUTREG(CRTC_OFFSET, 0);	OUTREG(CRTC_OFFSET_CNTL, 0);	OUTREG(CRTC_PITCH, mode->crtc_pitch);#if defined(__BIG_ENDIAN)	OUTREG(SURFACE_CNTL, mode->surface_cntl);#endif	while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=	       PPLL_DIV_SEL_MASK) {		OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);	}	OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);	while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=	       (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {		OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);	}	while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=	       (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {		OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);	}	while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=	       (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {		OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);	}	OUTPLL(HTOTAL_CNTL, 0);	OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);//	OUTREG(DDA_CONFIG, mode->dda_config);//	OUTREG(DDA_ON_OFF, mode->dda_on_off);	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {		OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);		OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);		OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);		OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);		OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);		OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);		OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);		OUTREG(TMDS_CRC, mode->tmds_crc);		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);		if (primary_mon == MT_LCD) {			unsigned int tmp = INREG(LVDS_GEN_CNTL);			mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;			mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);			if ((tmp & (LVDS_ON | LVDS_BLON)) ==			    (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {				OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);			} else {				if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {					udelay(1000);					OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);				} else {					OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |					       LVDS_BLON);					udelay(1000);					OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);				}			}		}	}	radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);		return;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/390725c36d220f5ca0c13b8927ac9c758ae1e4ad/radeonfb.c/buggy/drivers/video/radeonfb.c