XM_SC_CLR_RXC | XM_SC_CLR_TXC); 
XM_SC_CLR_RXC | XM_SC_CLR_TXC); 
static void genesis_mac_init(struct skge_hw *hw, int port){	struct skge_port *skge = netdev_priv(hw->dev[port]);	int i;	u32 r;	u16 id1;	u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;	/* magic workaround patterns for Broadcom */	static const struct {		u16 reg;		u16 val;	} A1hack[] = {		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },		{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },		{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },		{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },	}, C0hack[] = {		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },		{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },	};	/* initialize Rx, Tx and Link LED */	skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);	skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);	skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);	skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);	/* Unreset the XMAC. */	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);	/*	 * Perform additional initialization for external PHYs,	 * namely for the 1000baseTX cards that use the XMAC's	 * GMII mode.	 */	spin_lock_bh(&hw->phy_lock);	if (hw->phy_type != SK_PHY_XMAC) {		/* Take PHY out of reset. */		r = skge_read32(hw, B2_GP_IO);		if (port == 0)			r |= GP_DIR_0|GP_IO_0;		else			r |= GP_DIR_2|GP_IO_2;		skge_write32(hw, B2_GP_IO, r);		skge_read32(hw, B2_GP_IO);		/* Enable GMII mode on the XMAC. */		xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);		id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);		/* Optimize MDIO transfer by suppressing preamble. */		xm_write16(hw, port, XM_MMU_CMD,				xm_read16(hw, port, XM_MMU_CMD)				| XM_MMU_NO_PRE);		if (id1 == PHY_BCOM_ID1_C0) {			/*			 * Workaround BCOM Errata for the C0 type.			 * Write magic patterns to reserved registers.			 */			for (i = 0; i < ARRAY_SIZE(C0hack); i++)				xm_phy_write(hw, port,					  C0hack[i].reg, C0hack[i].val);		} else if (id1 == PHY_BCOM_ID1_A1) {			/*			 * Workaround BCOM Errata for the A1 type.			 * Write magic patterns to reserved registers.			 */			for (i = 0; i < ARRAY_SIZE(A1hack); i++)				xm_phy_write(hw, port,					  A1hack[i].reg, A1hack[i].val);		}		/*		 * Workaround BCOM Errata (#10523) for all BCom PHYs.		 * Disable Power Management after reset.		 */		r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);		xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);	}	/* Dummy read */	xm_read16(hw, port, XM_ISRC);	r = xm_read32(hw, port, XM_MODE);	xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);	/* We don't need the FCS appended to the packet. */	r = xm_read16(hw, port, XM_RX_CMD);	xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);	/* We want short frames padded to 60 bytes. */	r = xm_read16(hw, port, XM_TX_CMD);	xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);	/*	 * Enable the reception of all error frames. This is is	 * a necessary evil due to the design of the XMAC. The	 * XMAC's receive FIFO is only 8K in size, however jumbo	 * frames can be up to 9000 bytes in length. When bad	 * frame filtering is enabled, the XMAC's RX FIFO operates	 * in 'store and forward' mode. For this to work, the	 * entire frame has to fit into the FIFO, but that means	 * that jumbo frames larger than 8192 bytes will be	 * truncated. Disabling all bad frame filtering causes	 * the RX FIFO to operate in streaming mode, in which	 * case the XMAC will start transfering frames out of the	 * RX FIFO as soon as the FIFO threshold is reached.	 */	r = xm_read32(hw, port, XM_MODE);	xm_write32(hw, port, XM_MODE,		     XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|		     XM_MD_RX_ERR|XM_MD_RX_IRLE);	xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);	xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);	/*	 * Bump up the transmit threshold. This helps hold off transmit	 * underruns when we're blasting traffic from both ports at once.	 */	xm_write16(hw, port, XM_TX_THR, 512);	/* Configure MAC arbiter */	skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);	/* configure timeout values */	skge_write8(hw, B3_MA_TOINI_RX1, 72);	skge_write8(hw, B3_MA_TOINI_RX2, 72);	skge_write8(hw, B3_MA_TOINI_TX1, 72);	skge_write8(hw, B3_MA_TOINI_TX2, 72);	skge_write8(hw, B3_MA_RCINI_RX1, 0);	skge_write8(hw, B3_MA_RCINI_RX2, 0);	skge_write8(hw, B3_MA_RCINI_TX1, 0);	skge_write8(hw, B3_MA_RCINI_TX2, 0);	/* Configure Rx MAC FIFO */	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);	skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);	/* Configure Tx MAC FIFO */	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);	if (hw->dev[port]->mtu > ETH_DATA_LEN) {		/* Enable frame flushing if jumbo frames used */		skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);	} else {		/* enable timeout timers if normal frames */		skge_write16(hw, B3_PA_CTRL,			     port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);	}	r = xm_read16(hw, port, XM_RX_CMD);	if (hw->dev[port]->mtu > ETH_DATA_LEN)		xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);	else		xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));	switch (hw->phy_type) {	case SK_PHY_XMAC:		if (skge->autoneg == AUTONEG_ENABLE) {			ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;			switch (skge->flow_control) {			case FLOW_MODE_NONE:				ctrl1 |= PHY_X_P_NO_PAUSE;				break;			case FLOW_MODE_LOC_SEND:				ctrl1 |= PHY_X_P_ASYM_MD;				break;			case FLOW_MODE_SYMMETRIC:				ctrl1 |= PHY_X_P_SYM_MD;				break;			case FLOW_MODE_REM_SEND:				ctrl1 |= PHY_X_P_BOTH_MD;				break;			}			xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);			ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;		} else {			ctrl2 = 0;			if (skge->duplex == DUPLEX_FULL)				ctrl2 |= PHY_CT_DUP_MD;		}		xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);		break;	case SK_PHY_BCOM:		ctrl1 = PHY_CT_SP1000;		ctrl2 = 0;		ctrl3 = PHY_AN_CSMA;		ctrl4 = PHY_B_PEC_EN_LTR;		ctrl5 = PHY_B_AC_TX_TST;		if (skge->autoneg == AUTONEG_ENABLE) {			/*			 * Workaround BCOM Errata #1 for the C5 type.			 * 1000Base-T Link Acquisition Failure in Slave Mode			 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register			 */			ctrl2 |= PHY_B_1000C_RD;			if (skge->advertising & ADVERTISED_1000baseT_Half)				ctrl2 |= PHY_B_1000C_AHD;			if (skge->advertising & ADVERTISED_1000baseT_Full)				ctrl2 |= PHY_B_1000C_AFD;			/* Set Flow-control capabilities */			switch (skge->flow_control) {			case FLOW_MODE_NONE:				ctrl3 |= PHY_B_P_NO_PAUSE;				break;			case FLOW_MODE_LOC_SEND:				ctrl3 |= PHY_B_P_ASYM_MD;				break;			case FLOW_MODE_SYMMETRIC:				ctrl3 |= PHY_B_P_SYM_MD;				break;			case FLOW_MODE_REM_SEND:				ctrl3 |= PHY_B_P_BOTH_MD;				break;			}			/* Restart Auto-negotiation */			ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;		} else {			if (skge->duplex == DUPLEX_FULL)				ctrl1 |= PHY_CT_DUP_MD;			ctrl2 |= PHY_B_1000C_MSE;	/* set it to Slave */		}		xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);		xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);		if (skge->netdev->mtu > ETH_DATA_LEN) {			ctrl4 |= PHY_B_PEC_HIGH_LA;			ctrl5 |= PHY_B_AC_LONG_PACK;			xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);		}		xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);		xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);		break;	}	spin_unlock_bh(&hw->phy_lock);	/* Clear MIB counters */	xm_write16(hw, port, XM_STAT_CMD,			XM_SC_CLR_RXC | XM_SC_CLR_TXC);	/* Clear two times according to Errata #3 */	xm_write16(hw, port, XM_STAT_CMD,			XM_SC_CLR_RXC | XM_SC_CLR_TXC);	/* Start polling for link status */	mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/89bf5f231f776443a9d65da0f774aa3632534749/skge.c/clean/drivers/net/skge.c