printk(KERN_ERR DRV_NAME "(%s): failed to clear port RST\n", pci_name(pdev)); 
dev_printk(KERN_ERR, &pdev->dev, "failed to clear port RST\n"); 
static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent){	static int printed_version = 0;	unsigned int board_id = (unsigned int)ent->driver_data;	struct ata_port_info *pinfo = &sil24_port_info[board_id];	struct ata_probe_ent *probe_ent = NULL;	struct sil24_host_priv *hpriv = NULL;	void __iomem *host_base = NULL;	void __iomem *port_base = NULL;	int i, rc;	if (!printed_version++)		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");	rc = pci_enable_device(pdev);	if (rc)		return rc;	rc = pci_request_regions(pdev, DRV_NAME);	if (rc)		goto out_disable;	rc = -ENOMEM;	/* ioremap mmio registers */	host_base = ioremap(pci_resource_start(pdev, 0),			    pci_resource_len(pdev, 0));	if (!host_base)		goto out_free;	port_base = ioremap(pci_resource_start(pdev, 2),			    pci_resource_len(pdev, 2));	if (!port_base)		goto out_free;	/* allocate & init probe_ent and hpriv */	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);	if (!probe_ent)		goto out_free;	hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);	if (!hpriv)		goto out_free;	memset(probe_ent, 0, sizeof(*probe_ent));	probe_ent->dev = pci_dev_to_dev(pdev);	INIT_LIST_HEAD(&probe_ent->node);	probe_ent->sht		= pinfo->sht;	probe_ent->host_flags	= pinfo->host_flags;	probe_ent->pio_mask	= pinfo->pio_mask;	probe_ent->udma_mask	= pinfo->udma_mask;	probe_ent->port_ops	= pinfo->port_ops;	probe_ent->n_ports	= SIL24_FLAG2NPORTS(pinfo->host_flags);	probe_ent->irq = pdev->irq;	probe_ent->irq_flags = SA_SHIRQ;	probe_ent->mmio_base = port_base;	probe_ent->private_data = hpriv;	memset(hpriv, 0, sizeof(*hpriv));	hpriv->host_base = host_base;	hpriv->port_base = port_base;	/*	 * Configure the device	 */	/*	 * FIXME: This device is certainly 64-bit capable.  We just	 * don't know how to use it.  After fixing 32bit activation in	 * this function, enable 64bit masks here.	 */	rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);	if (rc) {		printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",		       pci_name(pdev));		goto out_free;	}	rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);	if (rc) {		printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",		       pci_name(pdev));		goto out_free;	}	/* GPIO off */	writel(0, host_base + HOST_FLASH_CMD);	/* Mask interrupts during initialization */	writel(0, host_base + HOST_CTRL);	for (i = 0; i < probe_ent->n_ports; i++) {		void __iomem *port = port_base + i * PORT_REGS_SIZE;		unsigned long portu = (unsigned long)port;		u32 tmp;		int cnt;		probe_ent->port[i].cmd_addr = portu + PORT_PRB;		probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;		ata_std_ports(&probe_ent->port[i]);		/* Initial PHY setting */		writel(0x20c, port + PORT_PHY_CFG);		/* Clear port RST */		tmp = readl(port + PORT_CTRL_STAT);		if (tmp & PORT_CS_PORT_RST) {			writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);			readl(port + PORT_CTRL_STAT);	/* sync */			for (cnt = 0; cnt < 10; cnt++) {				msleep(10);				tmp = readl(port + PORT_CTRL_STAT);				if (!(tmp & PORT_CS_PORT_RST))					break;			}			if (tmp & PORT_CS_PORT_RST)				printk(KERN_ERR DRV_NAME				       "(%s): failed to clear port RST\n",				       pci_name(pdev));		}		/* Zero error counters. */		writel(0x8000, port + PORT_DECODE_ERR_THRESH);		writel(0x8000, port + PORT_CRC_ERR_THRESH);		writel(0x8000, port + PORT_HSHK_ERR_THRESH);		writel(0x0000, port + PORT_DECODE_ERR_CNT);		writel(0x0000, port + PORT_CRC_ERR_CNT);		writel(0x0000, port + PORT_HSHK_ERR_CNT);		/* FIXME: 32bit activation? */		writel(0, port + PORT_ACTIVATE_UPPER_ADDR);		writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);		/* Configure interrupts */		writel(0xffff, port + PORT_IRQ_ENABLE_CLR);		writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,		       port + PORT_IRQ_ENABLE_SET);		/* Clear interrupts */		writel(0x0fff0fff, port + PORT_IRQ_STAT);		writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);		/* Clear port multiplier enable and resume bits */		writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);		/* Reset itself */		if (__sil24_reset_controller(port))			printk(KERN_ERR DRV_NAME			       "(%s): failed to reset controller\n",			       pci_name(pdev));	}	/* Turn on interrupts */	writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);	pci_set_master(pdev);	/* FIXME: check ata_device_add return value */	ata_device_add(probe_ent);	kfree(probe_ent);	return 0; out_free:	if (host_base)		iounmap(host_base);	if (port_base)		iounmap(port_base);	kfree(probe_ent);	kfree(hpriv);	pci_release_regions(pdev); out_disable:	pci_disable_device(pdev);	return rc;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/a9524a76f70f3343e4be27f95a7e92a8ba5f9009/sata_sil24.c/clean/drivers/scsi/sata_sil24.c