seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000); seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000); 
seq_printf(m, "FPGA Revision\t: %d\n", in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);  switch(bh.type) { case MV64x60_TYPE_GT64260A: s = "gt64260a"; break; case MV64x60_TYPE_GT64260B: s = "gt64260b"; break; case MV64x60_TYPE_MV64360: s = "mv64360"; break; case MV64x60_TYPE_MV64460: s = "mv64460"; break; default: s = "Unknown"; } seq_printf(m, "bridge type\t: %s\n", s); seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); #if defined(CONFIG_NOT_COHERENT_CACHE) seq_printf(m, "coherency\t: %s\n", "off"); #else seq_printf(m, "coherency\t: %s\n", "on"); #endif 
cpci690_show_cpuinfo(struct seq_file *m){	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");	seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);	seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f54bef9e9c84c8dc656c55dc96c1da7b6d1c53d8/cpci690.c/buggy/arch/ppc/platforms/cpci690.c