} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { 
} else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 
static int tg3_set_power_state(struct tg3 *tp, int state){	u32 misc_host_ctrl;	u16 power_control, power_caps;	int pm = tp->pm_cap;	/* Make sure register accesses (indirect or otherwise)	 * will function correctly.	 */	pci_write_config_dword(tp->pdev,			       TG3PCI_MISC_HOST_CTRL,			       tp->misc_host_ctrl);	pci_read_config_word(tp->pdev,			     pm + PCI_PM_CTRL,			     &power_control);	power_control |= PCI_PM_CTRL_PME_STATUS;	power_control &= ~(PCI_PM_CTRL_STATE_MASK);	switch (state) {	case 0:		power_control |= 0;		pci_write_config_word(tp->pdev,				      pm + PCI_PM_CTRL,				      power_control);		udelay(100);	/* Delay after power state change */		/* Switch out of Vaux if it is not a LOM */		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {			tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);			udelay(100);		}		return 0;	case 1:		power_control |= 1;		break;	case 2:		power_control |= 2;		break;	case 3:		power_control |= 3;		break;	default:		printk(KERN_WARNING PFX "%s: Invalid power state (%d) "		       "requested.\n",		       tp->dev->name, state);		return -EINVAL;	};	power_control |= PCI_PM_CTRL_PME_ENABLE;	misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);	tw32(TG3PCI_MISC_HOST_CTRL,	     misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);	if (tp->link_config.phy_is_low_power == 0) {		tp->link_config.phy_is_low_power = 1;		tp->link_config.orig_speed = tp->link_config.speed;		tp->link_config.orig_duplex = tp->link_config.duplex;		tp->link_config.orig_autoneg = tp->link_config.autoneg;	}	if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {		tp->link_config.speed = SPEED_10;		tp->link_config.duplex = DUPLEX_HALF;		tp->link_config.autoneg = AUTONEG_ENABLE;		tg3_setup_phy(tp, 0);	}	pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);	if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {		u32 mac_mode;		if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {			tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);			udelay(40);			mac_mode = MAC_MODE_PORT_MODE_MII;			if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||			    !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))				mac_mode |= MAC_MODE_LINK_POLARITY;		} else {			mac_mode = MAC_MODE_PORT_MODE_TBI;		}		if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))			tw32(MAC_LED_CTRL, tp->led_ctrl);		if (((power_caps & PCI_PM_CAP_PME_D3cold) &&		     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))			mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;		tw32_f(MAC_MODE, mac_mode);		udelay(100);		tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);		udelay(10);	}	if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {		u32 base_val;		base_val = tp->pci_clock_ctrl;		base_val |= (CLOCK_CTRL_RXCLK_DISABLE |			     CLOCK_CTRL_TXCLK_DISABLE);		tw32_f(TG3PCI_CLOCK_CTRL, base_val |		     CLOCK_CTRL_ALTCLK |		     CLOCK_CTRL_PWRDOWN_PLL133);		udelay(40);	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {		/* do nothing */	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {		u32 newbits1, newbits2;		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {			newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |				    CLOCK_CTRL_TXCLK_DISABLE |				    CLOCK_CTRL_ALTCLK);			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;		} else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {			newbits1 = CLOCK_CTRL_625_CORE;			newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;		} else {			newbits1 = CLOCK_CTRL_ALTCLK;			newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;		}		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);		udelay(40);		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);		udelay(40);		if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {			u32 newbits3;			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {				newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |					    CLOCK_CTRL_TXCLK_DISABLE |					    CLOCK_CTRL_44MHZ_CORE);			} else {				newbits3 = CLOCK_CTRL_44MHZ_CORE;			}			tw32_f(TG3PCI_CLOCK_CTRL,					 tp->pci_clock_ctrl | newbits3);			udelay(40);		}	}	tg3_frob_aux_power(tp);	/* Workaround for unstable PLL clock */	if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||	    (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {		u32 val = tr32(0x7d00);		val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);		tw32(0x7d00, val);		if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))			tg3_halt_cpu(tp, RX_CPU_BASE);	}	/* Finally, set the new power state. */	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);	udelay(100);	/* Delay after power state change */	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a4e2b347848bf626b822599329933887dc90e50f/tg3.c/clean/drivers/net/tg3.c