unsigned int __init init_intel_cacheinfo(struct cpuinfo_x86 *c) 
unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c) 
unsigned int __init init_intel_cacheinfo(struct cpuinfo_x86 *c){	unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */	unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */	unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */	if (c->cpuid_level > 4) {		static int is_initialized;		if (is_initialized == 0) {			/* Init num_cache_leaves from boot CPU */			num_cache_leaves = find_num_cache_leaves();			is_initialized++;		}		/*		 * Whenever possible use cpuid(4), deterministic cache		 * parameters cpuid leaf to find the cache details		 */		for (i = 0; i < num_cache_leaves; i++) {			struct _cpuid4_info this_leaf;			int retval;			retval = cpuid4_cache_lookup(i, &this_leaf);			if (retval >= 0) {				switch(this_leaf.eax.split.level) {				    case 1:					if (this_leaf.eax.split.type ==							CACHE_TYPE_DATA)						new_l1d = this_leaf.size/1024;					else if (this_leaf.eax.split.type ==							CACHE_TYPE_INST)						new_l1i = this_leaf.size/1024;					break;				    case 2:					new_l2 = this_leaf.size/1024;					break;				    case 3:					new_l3 = this_leaf.size/1024;					break;				    default:					break;				}			}		}	}	if (c->cpuid_level > 1) {		/* supports eax=2  call */		int i, j, n;		int regs[4];		unsigned char *dp = (unsigned char *)regs;		/* Number of times to iterate */		n = cpuid_eax(2) & 0xFF;		for ( i = 0 ; i < n ; i++ ) {			cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);			/* If bit 31 is set, this is an unknown format */			for ( j = 0 ; j < 3 ; j++ ) {				if ( regs[j] < 0 ) regs[j] = 0;			}			/* Byte 0 is level count, not a descriptor */			for ( j = 1 ; j < 16 ; j++ ) {				unsigned char des = dp[j];				unsigned char k = 0;				/* look up this descriptor in the table */				while (cache_table[k].descriptor != 0)				{					if (cache_table[k].descriptor == des) {						switch (cache_table[k].cache_type) {						case LVL_1_INST:							l1i += cache_table[k].size;							break;						case LVL_1_DATA:							l1d += cache_table[k].size;							break;						case LVL_2:							l2 += cache_table[k].size;							break;						case LVL_3:							l3 += cache_table[k].size;							break;						case LVL_TRACE:							trace += cache_table[k].size;							break;						}						break;					}					k++;				}			}		}		if (new_l1d)			l1d = new_l1d;		if (new_l1i)			l1i = new_l1i;		if (new_l2)			l2 = new_l2;		if (new_l3)			l3 = new_l3;		if ( trace )			printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);		else if ( l1i )			printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);		if ( l1d )			printk(", L1 D cache: %dK\n", l1d);		else			printk("\n");		if ( l2 )			printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);		if ( l3 )			printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);		/*		 * This assumes the L3 cache is shared; it typically lives in		 * the northbridge.  The L1 caches are included by the L2		 * cache, and so should not be included for the purpose of		 * SMP switching weights.		 */		c->x86_cache_size = l2 ? l2 : (l1i+l1d);	}	return l2;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/0bb3184df537002a742bafddf3f4fb482b7fe610/intel_cacheinfo.c/buggy/arch/i386/kernel/cpu/intel_cacheinfo.c