BYTE s0val, s1val, ir; 
unsigned char s0val, s1val, ir; 
enpci_interrupt(int intno, void *dev_id, struct pt_regs *regs){	struct IsdnCardState *cs = dev_id;	BYTE s0val, s1val, ir;	u_long flags;	spin_lock_irqsave(&cs->lock, flags);	s1val = InByte(cs->hw.njet.base + NETJET_IRQSTAT1);        /* AMD threw an interrupt */	if (!(s1val & TJ_AMD_IRQ)) {                /* read and clear interrupt-register */		ir = ReadByteAmd7930(cs, 0x00);		Amd7930_interrupt(cs, ir);		s1val = 1;	} else		s1val = 0;	s0val = InByte(cs->hw.njet.base + NETJET_IRQSTAT0);	if ((s0val | s1val)==0) { // shared IRQ		spin_unlock_irqrestore(&cs->lock, flags);		return IRQ_NONE;	} 	if (s0val)		OutByte(cs->hw.njet.base + NETJET_IRQSTAT0, s0val);	/* DMA-Interrupt: B-channel-stuff */	/* set bits in sval to indicate which page is free */	if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) <		inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ))		/* the 2nd write page is free */		s0val = 0x08;	else	/* the 1st write page is free */		s0val = 0x04;	if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) <		inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ))		/* the 2nd read page is free */		s0val = s0val | 0x02;	else	/* the 1st read page is free */		s0val = s0val | 0x01;	if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */	{		if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {			spin_unlock_irqrestore(&cs->lock, flags);			return IRQ_HANDLED;		}		cs->hw.njet.irqstat0 = s0val;		if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) !=			(cs->hw.njet.last_is0 & NETJET_IRQM0_READ))			/* we have a read dma int */			read_tiger(cs);		if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) !=			(cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE))			/* we have a write dma int */			write_tiger(cs);		test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);	}	spin_unlock_irqrestore(&cs->lock, flags);	return IRQ_HANDLED;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/672c3fd9069e5a138f9d4afc9aeb5aa34aacce32/enternow_pci.c/buggy/drivers/isdn/hisax/enternow_pci.c