ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7)); 
ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7)); 
void __init ixp2000_init_time(unsigned long tick_rate){	ticks_per_jiffy = (tick_rate + HZ/2) / HZ;	ticks_per_usec = tick_rate / 1000000;	/*	 * We use timer 1 as our timer interrupt.	 */	ixp2000_reg_write(IXP2000_T1_CLR, 0);	ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);	ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));	/*	 * We use a second timer as a monotonic counter for tracking	 * missed jiffies.  The IXP2000 has four timers, but if we're	 * on an A-step IXP2800, timer 2 and 3 don't work, so on those	 * chips we use timer 4.  Timer 4 is the only timer that can	 * be used for the watchdog, so we use timer 2 if we're on a	 * non-buggy chip.	 */	if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {		printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");		ixp2000_reg_write(IXP2000_T4_CLR, 0);		ixp2000_reg_write(IXP2000_T4_CLD, -1);		ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));		missing_jiffy_timer_csr = IXP2000_T4_CSR;	} else {		ixp2000_reg_write(IXP2000_T2_CLR, 0);		ixp2000_reg_write(IXP2000_T2_CLD, -1);		ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));		missing_jiffy_timer_csr = IXP2000_T2_CSR;	} 	next_jiffy_time = 0xffffffff;	/* register for interrupt */	setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/e9b72e43d96a1ea2be0f513c78f16743a835d252/core.c/clean/arch/arm/mach-ixp2000/core.c