pci_set_mwi (pdev); 
retval = pci_set_mwi(pdev); if (retval) ehci_dbg(ehci, "unable to enable MWI - not fatal.\n"); 
static int ehci_start (struct usb_hcd *hcd){	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);	u32			temp;	int			retval;	u32			hcc_params;	u8                      sbrn = 0;	int			first;	/* skip some things on restart paths */	first = (ehci->watchdog.data == 0);	if (first) {		init_timer (&ehci->watchdog);		ehci->watchdog.function = ehci_watchdog;		ehci->watchdog.data = (unsigned long) ehci;	}	/*	 * hw default: 1K periodic list heads, one per frame.	 * periodic_size can shrink by USBCMD update if hcc_params allows.	 */	ehci->periodic_size = DEFAULT_I_TDPS;	if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)		return retval;	/* controllers may cache some of the periodic schedule ... */	hcc_params = readl (&ehci->caps->hcc_params);	if (HCC_ISOC_CACHE (hcc_params)) 	// full frame cache		ehci->i_thresh = 8;	else					// N microframes cached		ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);	ehci->reclaim = NULL;	ehci->reclaim_ready = 0;	ehci->next_uframe = -1;	/* controller state:  unknown --> reset */	/* EHCI spec section 4.1 */	if ((retval = ehci_reset (ehci)) != 0) {		ehci_mem_cleanup (ehci);		return retval;	}	writel (ehci->periodic_dma, &ehci->regs->frame_list);#ifdef	CONFIG_PCI	if (hcd->self.controller->bus == &pci_bus_type) {		struct pci_dev		*pdev;		u16			port_wake;		pdev = to_pci_dev(hcd->self.controller);		/* Serial Bus Release Number is at PCI 0x60 offset */		pci_read_config_byte(pdev, 0x60, &sbrn);		/* port wake capability, reported by boot firmware */		pci_read_config_word(pdev, 0x62, &port_wake);		hcd->can_wakeup = (port_wake & 1) != 0;		/* help hc dma work well with cachelines */		pci_set_mwi (pdev);	}#endif	/*	 * dedicate a qh for the async ring head, since we couldn't unlink	 * a 'real' qh without stopping the async schedule [4.8].  use it	 * as the 'reclamation list head' too.	 * its dummy is used in hw_alt_next of many tds, to prevent the qh	 * from automatically advancing to the next td after short reads.	 */	if (first) {		ehci->async->qh_next.qh = NULL;		ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);		ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);		ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);		ehci->async->hw_qtd_next = EHCI_LIST_END;		ehci->async->qh_state = QH_STATE_LINKED;		ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);	}	writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);	/*	 * hcc_params controls whether ehci->regs->segment must (!!!)	 * be used; it constrains QH/ITD/SITD and QTD locations.	 * pci_pool consistent memory always uses segment zero.	 * streaming mappings for I/O buffers, like pci_map_single(),	 * can return segments above 4GB, if the device allows.	 *	 * NOTE:  the dma mask is visible through dma_supported(), so	 * drivers can pass this info along ... like NETIF_F_HIGHDMA,	 * Scsi_Host.highmem_io, and so forth.  It's readonly to all	 * host side drivers though.	 */	if (HCC_64BIT_ADDR (hcc_params)) {		writel (0, &ehci->regs->segment);#if 0// this is deeply broken on almost all architectures		if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK))			ehci_info (ehci, "enabled 64bit DMA\n");#endif	}	/* clear interrupt enables, set irq latency */	if (log2_irq_thresh < 0 || log2_irq_thresh > 6)		log2_irq_thresh = 0;	temp = 1 << (16 + log2_irq_thresh);	if (HCC_CANPARK(hcc_params)) {		/* HW default park == 3, on hardware that supports it (like		 * NVidia and ALI silicon), maximizes throughput on the async		 * schedule by avoiding QH fetches between transfers.		 *		 * With fast usb storage devices and NForce2, "park" seems to		 * make problems:  throughput reduction (!), data errors...		 */		if (park) {			park = min (park, (unsigned) 3);			temp |= CMD_PARK;			temp |= park << 8;		}		ehci_info (ehci, "park %d\n", park);	}	if (HCC_PGM_FRAMELISTLEN (hcc_params)) {		/* periodic schedule size can be smaller than default */		temp &= ~(3 << 2);		temp |= (EHCI_TUNE_FLS << 2);		switch (EHCI_TUNE_FLS) {		case 0: ehci->periodic_size = 1024; break;		case 1: ehci->periodic_size = 512; break;		case 2: ehci->periodic_size = 256; break;		default:	BUG ();		}	}	// Philips, Intel, and maybe others need CMD_RUN before the	// root hub will detect new devices (why?); NEC doesn't	temp |= CMD_RUN;	writel (temp, &ehci->regs->command);	dbg_cmd (ehci, "init", temp);	/* set async sleep time = 10 us ... ? */	/*	 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices	 * are explicitly handed to companion controller(s), so no TT is	 * involved with the root hub.  (Except where one is integrated,	 * and there's no companion controller unless maybe for USB OTG.)	 */	if (first) {		ehci->reboot_notifier.notifier_call = ehci_reboot;		register_reboot_notifier (&ehci->reboot_notifier);	}	hcd->state = HC_STATE_RUNNING;	writel (FLAG_CF, &ehci->regs->configured_flag);	readl (&ehci->regs->command);	/* unblock posted write */	temp = HC_VERSION(readl (&ehci->caps->hc_capbase));	ehci_info (ehci,		"USB %x.%x %s, EHCI %x.%02x, driver %s\n",		((sbrn & 0xf0)>>4), (sbrn & 0x0f),		first ? "initialized" : "restarted",		temp >> 8, temp & 0xff, DRIVER_VERSION);	writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */	if (first)		create_debug_files (ehci);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/95a629657dbe28e44a312c47815b3dc3f1ce0970/ehci-hcd.c/clean/drivers/usb/host/ehci-hcd.c