static void __init psycho_iommu_init(struct pci_controller_info *p) 
static void psycho_iommu_init(struct pci_controller_info *p) 
static void __init psycho_iommu_init(struct pci_controller_info *p){	struct pci_iommu *iommu = p->pbm_A.iommu;	unsigned long tsbbase, i;	u64 control;	/* Setup initial software IOMMU state. */	spin_lock_init(&iommu->lock);	iommu->ctx_lowest_free = 1;	/* Register addresses. */	iommu->iommu_control  = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;	iommu->iommu_tsbbase  = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;	iommu->iommu_flush    = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;	/* PSYCHO's IOMMU lacks ctx flushing. */	iommu->iommu_ctxflush = 0;	/* We use the main control register of PSYCHO as the write	 * completion register.	 */	iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;	/*	 * Invalidate TLB Entries.	 */	control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);	control |= PSYCHO_IOMMU_CTRL_DENAB;	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);	for(i = 0; i < 16; i++) {		psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);		psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);	}	/* Leave diag mode enabled for full-flushing done	 * in pci_iommu.c	 */	iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);	if (!iommu->dummy_page) {		prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");		prom_halt();	}	memset((void *)iommu->dummy_page, 0, PAGE_SIZE);	iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);	/* Using assumed page size 8K with 128K entries we need 1MB iommu page	 * table (128K ioptes * 8 bytes per iopte).  This is	 * page order 7 on UltraSparc.	 */	tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE));	if (!tsbbase) {		prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");		prom_halt();	}	iommu->page_table = (iopte_t *)tsbbase;	iommu->page_table_sz_bits = 17;	iommu->page_table_map_base = 0xc0000000;	iommu->dma_addr_mask = 0xffffffff;	pci_iommu_table_init(iommu, IO_TSB_SIZE);	/* We start with no consistent mappings. */	iommu->lowest_consistent_map =		1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);	for (i = 0; i < PBM_NCLUSTERS; i++) {		iommu->alloc_info[i].flush = 0;		iommu->alloc_info[i].next = 0;	}	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));	control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);	control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);	control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);	psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);	/* If necessary, hook us up for starfire IRQ translations. */	if(this_is_starfire)		p->starfire_cookie = starfire_hookup(p->pbm_A.portid);	else		p->starfire_cookie = NULL;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_psycho.c/buggy/arch/sparc64/kernel/pci_psycho.c