*mbcs |= KN05_MB_CSR_EE; 
*mbcs |= KN4K_MB_CSR_EE; 
static inline void dec_kn03_be_init(void){	volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR);	volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR);	kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);	kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);	/*	 * Set normal ECC detection and generation, enable ECC correction.	 * For KN05 we also need to make sure EE (?) is enabled in the MB.	 * Otherwise DBE/IBE exceptions would be masked but bus error	 * interrupts would still arrive, resulting in an inevitable crash	 * if get_dbe() triggers one.	 */	*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |	       KN03_MCR_CORRECT;	if (current_cpu_data.cputype == CPU_R4400SC)		*mbcs |= KN05_MB_CSR_EE;	fast_iob();}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/64dac503e8265007ea5c53b4d6bf42488a8a8d7a/ecc-berr.c/buggy/arch/mips/dec/ecc-berr.c