void __devinit amd_mcheck_init(struct cpuinfo_x86 *c) 
void amd_mcheck_init(struct cpuinfo_x86 *c) 
void __devinit amd_mcheck_init(struct cpuinfo_x86 *c){	u32 l, h;	int i;	machine_check_vector = k7_machine_check;	wmb();	printk (KERN_INFO "Intel machine check architecture supported.\n");	rdmsr (MSR_IA32_MCG_CAP, l, h);	if (l & (1<<8))	/* Control register present ? */		wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);	nr_mce_banks = l & 0xff;	/* Clear status for MC index 0 separately, we don't touch CTL,	 * as some Athlons cause spurious MCEs when its enabled. */	wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);	for (i=1; i<nr_mce_banks; i++) {		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);	}	set_in_cr4 (X86_CR4_MCE);	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",		smp_processor_id());}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/31ab269a0307d8725737dfbbdeb5dcde7b41bc36/k7.c/buggy/arch/i386/kernel/cpu/mcheck/k7.c