__hlt(); 
halt(); 
static void do_powersaver(union msr_longhaul *longhaul,			unsigned int clock_ratio_index){	struct pci_dev *dev;	unsigned long flags;	unsigned int tmp_mask;	int version;	int i;	u16 pci_cmd;	u16 cmd_state[64];	switch (cpu_model) {	case CPU_EZRA_T:		version = 3;		break;	case CPU_NEHEMIAH:		version = 0xf;		break;	default:		return;	}	rdmsrl(MSR_VIA_LONGHAUL, longhaul->val);	longhaul->bits.SoftBusRatio = clock_ratio_index & 0xf;	longhaul->bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;	longhaul->bits.EnableSoftBusRatio = 1;	longhaul->bits.RevisionKey = 0;	preempt_disable();	local_irq_save(flags);	/*	 * get current pci bus master state for all devices	 * and clear bus master bit	 */	dev = NULL;	i = 0;	do {		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);		if (dev != NULL) {			pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);			cmd_state[i++] = pci_cmd;			pci_cmd &= ~PCI_COMMAND_MASTER;			pci_write_config_word(dev, PCI_COMMAND, pci_cmd);		}	} while (dev != NULL);	tmp_mask=inb(0x21);	/* works on C3. save mask. */	outb(0xFE,0x21);	/* TMR0 only */	outb(0xFF,0x80);	/* delay */	local_irq_enable();	__hlt();	wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);	__hlt();	local_irq_disable();	outb(tmp_mask,0x21);	/* restore mask */	/* restore pci bus master state for all devices */	dev = NULL;	i = 0;	do {		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);		if (dev != NULL) {			pci_cmd = cmd_state[i++];			pci_write_config_byte(dev, PCI_COMMAND, pci_cmd);		}	} while (dev != NULL);	local_irq_restore(flags);	preempt_enable();	/* disable bus ratio bit */	rdmsrl(MSR_VIA_LONGHAUL, longhaul->val);	longhaul->bits.EnableSoftBusRatio = 0;	longhaul->bits.RevisionKey = version;	wrmsrl(MSR_VIA_LONGHAUL, longhaul->val);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/4bb0d3ec3e5b1e9e2399cdc641b3b6521ac9cdaa/longhaul.c/buggy/arch/i386/kernel/cpu/cpufreq/longhaul.c