 init_timer(&uhci->stall_timer); uhci->stall_timer.function = stall_callback; uhci->stall_timer.data = (unsigned long) uhci; 
static int uhci_start(struct usb_hcd *hcd){	struct uhci_hcd *uhci = hcd_to_uhci(hcd);	int retval = -EBUSY;	int i;	dma_addr_t dma_handle;	struct dentry *dentry;	hcd->uses_new_polling = 1;	if (pci_find_capability(to_pci_dev(uhci_dev(uhci)), PCI_CAP_ID_PM))		hcd->can_wakeup = 1;		/* Assume it supports PME# */	dentry = debugfs_create_file(hcd->self.bus_name,			S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci,			&uhci_debug_operations);	if (!dentry) {		dev_err(uhci_dev(uhci),				"couldn't create uhci debugfs entry\n");		retval = -ENOMEM;		goto err_create_debug_entry;	}	uhci->dentry = dentry;	uhci->fsbr = 0;	uhci->fsbrtimeout = 0;	spin_lock_init(&uhci->lock);	INIT_LIST_HEAD(&uhci->qh_remove_list);	INIT_LIST_HEAD(&uhci->td_remove_list);	INIT_LIST_HEAD(&uhci->urb_remove_list);	INIT_LIST_HEAD(&uhci->urb_list);	INIT_LIST_HEAD(&uhci->complete_list);	init_waitqueue_head(&uhci->waitqh);	init_timer(&uhci->stall_timer);	uhci->stall_timer.function = stall_callback;	uhci->stall_timer.data = (unsigned long) uhci;	uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl),			&dma_handle, 0);	if (!uhci->fl) {		dev_err(uhci_dev(uhci), "unable to allocate "				"consistent memory for frame list\n");		goto err_alloc_fl;	}	memset((void *)uhci->fl, 0, sizeof(*uhci->fl));	uhci->fl->dma_handle = dma_handle;	uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),			sizeof(struct uhci_td), 16, 0);	if (!uhci->td_pool) {		dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");		goto err_create_td_pool;	}	uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),			sizeof(struct uhci_qh), 16, 0);	if (!uhci->qh_pool) {		dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");		goto err_create_qh_pool;	}	uhci->term_td = uhci_alloc_td(uhci);	if (!uhci->term_td) {		dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");		goto err_alloc_term_td;	}	for (i = 0; i < UHCI_NUM_SKELQH; i++) {		uhci->skelqh[i] = uhci_alloc_qh(uhci);		if (!uhci->skelqh[i]) {			dev_err(uhci_dev(uhci), "unable to allocate QH\n");			goto err_alloc_skelqh;		}	}	/*	 * 8 Interrupt queues; link all higher int queues to int1,	 * then link int1 to control and control to bulk	 */	uhci->skel_int128_qh->link =			uhci->skel_int64_qh->link =			uhci->skel_int32_qh->link =			uhci->skel_int16_qh->link =			uhci->skel_int8_qh->link =			uhci->skel_int4_qh->link =			uhci->skel_int2_qh->link =			cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;	uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;	uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;	uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;	uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;	/* This dummy TD is to work around a bug in Intel PIIX controllers */	uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |		(0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);	uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);	uhci->skel_term_qh->link = UHCI_PTR_TERM;	uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);	/*	 * Fill the frame list: make all entries point to the proper	 * interrupt queue.	 *	 * The interrupt queues will be interleaved as evenly as possible.	 * There's not much to be done about period-1 interrupts; they have	 * to occur in every frame.  But we can schedule period-2 interrupts	 * in odd-numbered frames, period-4 interrupts in frames congruent	 * to 2 (mod 4), and so on.  This way each frame only has two	 * interrupt QHs, which will help spread out bandwidth utilization.	 */	for (i = 0; i < UHCI_NUMFRAMES; i++) {		int irq;		/*		 * ffs (Find First bit Set) does exactly what we need:		 * 1,3,5,...  => ffs = 0 => use skel_int2_qh = skelqh[6],		 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.		 * ffs > 6 => not on any high-period queue, so use		 *	skel_int1_qh = skelqh[7].		 * Add UHCI_NUMFRAMES to insure at least one bit is set.		 */		irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES);		if (irq < 0)			irq = 7;		/* Only place we don't use the frame list routines */		uhci->fl->frame[i] = UHCI_PTR_QH |				cpu_to_le32(uhci->skelqh[irq]->dma_handle);	}	/*	 * Some architectures require a full mb() to enforce completion of	 * the memory writes above before the I/O transfers in configure_hc().	 */	mb();	configure_hc(uhci);	start_rh(uhci);	return 0;/* * error exits: */err_alloc_skelqh:	for (i = 0; i < UHCI_NUM_SKELQH; i++)		if (uhci->skelqh[i]) {			uhci_free_qh(uhci, uhci->skelqh[i]);			uhci->skelqh[i] = NULL;		}	uhci_free_td(uhci, uhci->term_td);	uhci->term_td = NULL;err_alloc_term_td:	dma_pool_destroy(uhci->qh_pool);	uhci->qh_pool = NULL;err_create_qh_pool:	dma_pool_destroy(uhci->td_pool);	uhci->td_pool = NULL;err_create_td_pool:	dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl),			uhci->fl, uhci->fl->dma_handle);	uhci->fl = NULL;err_alloc_fl:	debugfs_remove(uhci->dentry);	uhci->dentry = NULL;err_create_debug_entry:	return retval;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/1f09df8bfe358994fcb5f3dc4f890694c4069621/uhci-hcd.c/buggy/drivers/usb/host/uhci-hcd.c