unsigned long flags; 
static void tg3_timer(unsigned long __opaque){	struct tg3 *tp = (struct tg3 *) __opaque;	unsigned long flags;	spin_lock_irqsave(&tp->lock, flags);	spin_lock(&tp->tx_lock);	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {		/* All of this garbage is because when using non-tagged		 * IRQ status the mailbox/status_block protocol the chip		 * uses with the cpu is race prone.		 */		if (tp->hw_status->status & SD_STATUS_UPDATED) {			tw32(GRC_LOCAL_CTRL,			     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);		} else {			tw32(HOSTCC_MODE, tp->coalesce_mode |			     (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));		}		if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {			tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;			spin_unlock(&tp->tx_lock);			spin_unlock_irqrestore(&tp->lock, flags);			schedule_work(&tp->reset_task);			return;		}	}	/* This part only runs once per second. */	if (!--tp->timer_counter) {		if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)			tg3_periodic_fetch_stats(tp);		if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {			u32 mac_stat;			int phy_event;			mac_stat = tr32(MAC_STATUS);			phy_event = 0;			if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {				if (mac_stat & MAC_STATUS_MI_INTERRUPT)					phy_event = 1;			} else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)				phy_event = 1;			if (phy_event)				tg3_setup_phy(tp, 0);		} else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {			u32 mac_stat = tr32(MAC_STATUS);			int need_setup = 0;			if (netif_carrier_ok(tp->dev) &&			    (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {				need_setup = 1;			}			if (! netif_carrier_ok(tp->dev) &&			    (mac_stat & (MAC_STATUS_PCS_SYNCED |					 MAC_STATUS_SIGNAL_DET))) {				need_setup = 1;			}			if (need_setup) {				tw32_f(MAC_MODE,				     (tp->mac_mode &				      ~MAC_MODE_PORT_MODE_MASK));				udelay(40);				tw32_f(MAC_MODE, tp->mac_mode);				udelay(40);				tg3_setup_phy(tp, 0);			}		}		tp->timer_counter = tp->timer_multiplier;	}	/* Heartbeat is only sent once every 120 seconds.  */	if (!--tp->asf_counter) {		if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {			u32 val;			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);			val = tr32(GRC_RX_CPU_EVENT);			val |= (1 << 14);			tw32(GRC_RX_CPU_EVENT, val);		}		tp->asf_counter = tp->asf_multiplier;	}	spin_unlock(&tp->tx_lock);	spin_unlock_irqrestore(&tp->lock, flags);	tp->timer.expires = jiffies + tp->timer_offset;	add_timer(&tp->timer);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f47c11eeccc8820010992eb32dbe7370a08f8bd3/tg3.c/buggy/drivers/net/tg3.c