if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) 
if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 
static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp){	u32 val;	/* Make sure register accesses (indirect or otherwise)	 * will function correctly.	 */	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,			       tp->misc_host_ctrl);	tp->phy_id = PHY_ID_INVALID;	tp->led_ctrl = LED_CTRL_MODE_PHY_1;	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);	if (val == NIC_SRAM_DATA_SIG_MAGIC) {		u32 nic_cfg, led_cfg;		u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;		int eeprom_phy_serdes = 0;		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);		tp->nic_sram_data_cfg = nic_cfg;		tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);		ver >>= NIC_SRAM_DATA_VER_SHIFT;		if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&		    (ver > 0) && (ver < 0x100))			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==		    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)			eeprom_phy_serdes = 1;		tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);		if (nic_phy_id != 0) {			u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;			u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;			eeprom_phy_id  = (id1 >> 16) << 10;			eeprom_phy_id |= (id2 & 0xfc00) << 16;			eeprom_phy_id |= (id2 & 0x03ff) <<  0;		} else			eeprom_phy_id = 0;		tp->phy_id = eeprom_phy_id;		if (eeprom_phy_serdes) {			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)				tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;			else				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;		}		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |				    SHASTA_EXT_LED_MODE_MASK);		else			led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;		switch (led_cfg) {		default:		case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:			tp->led_ctrl = LED_CTRL_MODE_PHY_1;			break;		case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:			tp->led_ctrl = LED_CTRL_MODE_PHY_2;			break;		case NIC_SRAM_DATA_CFG_LED_MODE_MAC:			tp->led_ctrl = LED_CTRL_MODE_MAC;			/* Default to PHY_1_MODE if 0 (MAC_MODE) is			 * read on some older 5700/5701 bootcode.			 */			if (GET_ASIC_REV(tp->pci_chip_rev_id) ==			    ASIC_REV_5700 ||			    GET_ASIC_REV(tp->pci_chip_rev_id) ==			    ASIC_REV_5701)				tp->led_ctrl = LED_CTRL_MODE_PHY_1;			break;		case SHASTA_EXT_LED_SHARED:			tp->led_ctrl = LED_CTRL_MODE_SHARED;			if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&			    tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |						 LED_CTRL_MODE_PHY_2);			break;		case SHASTA_EXT_LED_MAC:			tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;			break;		case SHASTA_EXT_LED_COMBO:			tp->led_ctrl = LED_CTRL_MODE_COMBO;			if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |						 LED_CTRL_MODE_PHY_2);			break;		};		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||		     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&		    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)			tp->led_ctrl = LED_CTRL_MODE_PHY_2;		if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&		    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&		    (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))			tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;		}		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)			tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;		if (cfg2 & (1 << 17))			tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;		/* serdes signal pre-emphasis in register 0x590 set by */		/* bootcode if bit 18 is set */		if (cfg2 & (1 << 18))			tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a4e2b347848bf626b822599329933887dc90e50f/tg3.c/clean/drivers/net/tg3.c