/* CPUID workaround for Intel 0F33/0F34 CPU */ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 0x3 && (boot_cpu_data.x86_mask == 0x3 || boot_cpu_data.x86_mask == 0x4)) phys_addr = 36;  
void __init mtrr_bp_init(void){	init_ifs();	if (cpu_has_mtrr) {		mtrr_if = &generic_mtrr_ops;		size_or_mask = 0xff000000;	/* 36 bits */		size_and_mask = 0x00f00000;		/* This is an AMD specific MSR, but we assume(hope?) that		   Intel will implement it to when they extend the address		   bus of the Xeon. */		if (cpuid_eax(0x80000000) >= 0x80000008) {			u32 phys_addr;			phys_addr = cpuid_eax(0x80000008) & 0xff;			size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);			size_and_mask = ~size_or_mask & 0xfff00000;		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&			   boot_cpu_data.x86 == 6) {			/* VIA C* family have Intel style MTRRs, but			   don't support PAE */			size_or_mask = 0xfff00000;	/* 32 bits */			size_and_mask = 0;		}	} else {		switch (boot_cpu_data.x86_vendor) {		case X86_VENDOR_AMD:			if (cpu_has_k6_mtrr) {				/* Pre-Athlon (K6) AMD CPU MTRRs */				mtrr_if = mtrr_ops[X86_VENDOR_AMD];				size_or_mask = 0xfff00000;	/* 32 bits */				size_and_mask = 0;			}			break;		case X86_VENDOR_CENTAUR:			if (cpu_has_centaur_mcr) {				mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];				size_or_mask = 0xfff00000;	/* 32 bits */				size_and_mask = 0;			}			break;		case X86_VENDOR_CYRIX:			if (cpu_has_cyrix_arr) {				mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];				size_or_mask = 0xfff00000;	/* 32 bits */				size_and_mask = 0;			}			break;		default:			break;		}	}	printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);	if (mtrr_if) {		set_num_var_ranges();		init_table();		if (use_intel())			get_mtrr_state();	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/af9c142de94ecf724a18700273bbba390873e072/main.c/buggy/arch/i386/kernel/cpu/mtrr/main.c