 /* FIXME: because generic set affinity mucks * with the affinity before sending it to us * we can get the situation where the affinity is * wrong for our CPU type interrupts */ if (irq != TIMER_IRQ && irq != IPI_IRQ && !cpu_isset(smp_processor_id(), dest)) { int cpu = first_cpu(dest);  printk("rethrowing irq %d from %d to %d\n", irq, smp_processor_id(), cpu); gsc_writel(irq + CPU_IRQ_BASE, cpu_data[cpu].hpa); continue; } 
void do_cpu_irq_mask(struct pt_regs *regs){	unsigned long eirr_val;	irq_enter();	/*	 * Don't allow TIMER or IPI nested interrupts.	 * Allowing any single interrupt to nest can lead to that CPU	 * handling interrupts with all enabled interrupts unmasked.	 */	set_eiem(0UL);	/* 1) only process IRQs that are enabled/unmasked (cpu_eiem)	 * 2) We loop here on EIRR contents in order to avoid	 *    nested interrupts or having to take another interrupt	 *    when we could have just handled it right away.	 */	for (;;) {		unsigned long bit = (1UL << (BITS_PER_LONG - 1));		unsigned int irq;		eirr_val = mfctl(23) & cpu_eiem;		if (!eirr_val)			break;		mtctl(eirr_val, 23); /* reset bits we are going to process */		/* Work our way from MSb to LSb...same order we alloc EIRs */		for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {			if (!(bit & eirr_val))				continue;			/* clear bit in mask - can exit loop sooner */			eirr_val &= ~bit;			__do_IRQ(irq, regs);		}	}	set_eiem(cpu_eiem);	/* restore original mask */	irq_exit();}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/c2ab64d09815cc4d48347ee3679658f197455a2a/irq.c/clean/arch/parisc/kernel/irq.c