pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 
pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 
static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name){	u32 class_rev = 0;	u8 mrdmode = 0;	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);	class_rev &= 0xff;#ifdef __i386__	if (dev->resource[PCI_ROM_RESOURCE].start) {		pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);		printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);	}#endif	switch(dev->device) {		case PCI_DEVICE_ID_CMD_643:			break;		case PCI_DEVICE_ID_CMD_646:			printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);			switch(class_rev) {				case 0x07:				case 0x05:					printk("UltraDMA Capable");					break;				case 0x03:					printk("MultiWord DMA Force Limited");					break;				case 0x01:				default:					printk("MultiWord DMA Limited, IRQ workaround enabled");					break;				}			printk("\n");                        break;		case PCI_DEVICE_ID_CMD_648:		case PCI_DEVICE_ID_CMD_649:			break;		default:			break;	}	/* Set a good latency timer and cache line size value. */	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);	/* FIXME: pci_set_master() to ensure a good latency timer value */	/* Setup interrupts. */	(void) pci_read_config_byte(dev, MRDMODE, &mrdmode);	mrdmode &= ~(0x30);	(void) pci_write_config_byte(dev, MRDMODE, mrdmode);	/* Use MEMORY READ LINE for reads.	 * NOTE: Although not mentioned in the PCI0646U specs,	 *       these bits are write only and won't be read	 *       back as set or not.  The PCI0646U2 specs clarify	 *       this point.	 */	(void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);	/* Set reasonable active/recovery/address-setup values. */	(void) pci_write_config_byte(dev, ARTTIM0,  0x40);	(void) pci_write_config_byte(dev, DRWTIM0,  0x3f);	(void) pci_write_config_byte(dev, ARTTIM1,  0x40);	(void) pci_write_config_byte(dev, DRWTIM1,  0x3f);#ifdef __i386__	(void) pci_write_config_byte(dev, ARTTIM23, 0x1c);#else	(void) pci_write_config_byte(dev, ARTTIM23, 0x5c);#endif	(void) pci_write_config_byte(dev, DRWTIM23, 0x3f);	(void) pci_write_config_byte(dev, DRWTIM3,  0x3f);#ifdef CONFIG_PPC	(void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);#endif /* CONFIG_PPC */#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)	cmd_devs[n_cmd_devs++] = dev;	if (!cmd64x_proc) {		cmd64x_proc = 1;		ide_pci_create_host_proc("cmd64x", cmd64x_get_info);	}#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/299cc3c166f7a11f6cc3b66aafbaf75c2aa0e0e2/cmd64x.c/buggy/drivers/ide/pci/cmd64x.c