 /* * Do a quick test to see if we receive an * interrupt when we enable the TX irq. */ serial_outp(up, UART_IER, UART_IER_THRI); lsr = serial_in(up, UART_LSR); iir = serial_in(up, UART_IIR); serial_outp(up, UART_IER, 0);  if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { if (!(up->capabilities & UART_BUG_TXEN)) { up->capabilities |= UART_BUG_TXEN; pr_debug("ttyS%d - enabling bad tx status workarounds\n", port->line); } } else { up->capabilities &= ~UART_BUG_TXEN; }  
static int serial8250_startup(struct uart_port *port){	struct uart_8250_port *up = (struct uart_8250_port *)port;	unsigned long flags;	int retval;	up->capabilities = uart_config[up->port.type].flags;	up->mcr = 0;	if (up->port.type == PORT_16C950) {		/* Wake up and initialize UART */		up->acr = 0;		serial_outp(up, UART_LCR, 0xBF);		serial_outp(up, UART_EFR, UART_EFR_ECB);		serial_outp(up, UART_IER, 0);		serial_outp(up, UART_LCR, 0);		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */		serial_outp(up, UART_LCR, 0xBF);		serial_outp(up, UART_EFR, UART_EFR_ECB);		serial_outp(up, UART_LCR, 0);	}#ifdef CONFIG_SERIAL_8250_RSA	/*	 * If this is an RSA port, see if we can kick it up to the	 * higher speed clock.	 */	enable_rsa(up);#endif	/*	 * Clear the FIFO buffers and disable them.	 * (they will be reeanbled in set_termios())	 */	serial8250_clear_fifos(up);	/*	 * Clear the interrupt registers.	 */	(void) serial_inp(up, UART_LSR);	(void) serial_inp(up, UART_RX);	(void) serial_inp(up, UART_IIR);	(void) serial_inp(up, UART_MSR);	/*	 * At this point, there's no way the LSR could still be 0xff;	 * if it is, then bail out, because there's likely no UART	 * here.	 */	if (!(up->port.flags & UPF_BUGGY_UART) &&	    (serial_inp(up, UART_LSR) == 0xff)) {		printk("ttyS%d: LSR safety check engaged!\n", up->port.line);		return -ENODEV;	}	/*	 * For a XR16C850, we need to set the trigger levels	 */	if (up->port.type == PORT_16850) {		unsigned char fctr;		serial_outp(up, UART_LCR, 0xbf);		fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);		serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);		serial_outp(up, UART_TRG, UART_TRG_96);		serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);		serial_outp(up, UART_TRG, UART_TRG_96);		serial_outp(up, UART_LCR, 0);	}	/*	 * If the "interrupt" for this port doesn't correspond with any	 * hardware interrupt, we use a timer-based system.  The original	 * driver used to do this with IRQ0.	 */	if (!is_real_interrupt(up->port.irq)) {		unsigned int timeout = up->port.timeout;		timeout = timeout > 6 ? (timeout / 2 - 2) : 1;		up->timer.data = (unsigned long)up;		mod_timer(&up->timer, jiffies + timeout);	} else {		retval = serial_link_irq_chain(up);		if (retval)			return retval;	}	/*	 * Now, initialize the UART	 */	serial_outp(up, UART_LCR, UART_LCR_WLEN8);	spin_lock_irqsave(&up->port.lock, flags);	if (up->port.flags & UPF_FOURPORT) {		if (!is_real_interrupt(up->port.irq))			up->port.mctrl |= TIOCM_OUT1;	} else		/*		 * Most PC uarts need OUT2 raised to enable interrupts.		 */		if (is_real_interrupt(up->port.irq))			up->port.mctrl |= TIOCM_OUT2;	serial8250_set_mctrl(&up->port, up->port.mctrl);	spin_unlock_irqrestore(&up->port.lock, flags);	/*	 * Finally, enable interrupts.  Note: Modem status interrupts	 * are set via set_termios(), which will be occurring imminently	 * anyway, so we don't enable them here.	 */	up->ier = UART_IER_RLSI | UART_IER_RDI;	serial_outp(up, UART_IER, up->ier);	if (up->port.flags & UPF_FOURPORT) {		unsigned int icp;		/*		 * Enable interrupts on the AST Fourport board		 */		icp = (up->port.iobase & 0xfe0) | 0x01f;		outb_p(0x80, icp);		(void) inb_p(icp);	}	/*	 * And clear the interrupt registers again for luck.	 */	(void) serial_inp(up, UART_LSR);	(void) serial_inp(up, UART_RX);	(void) serial_inp(up, UART_IIR);	(void) serial_inp(up, UART_MSR);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/55d3b282b90620e02e825304a9433732a84c58a5/8250.c/buggy/drivers/serial/8250.c