dprintk(0, "cx8802_start_dma %d\n", buf->vb.width); 
dprintk(0, "cx8802_start_dma w: %d, h: %d, f: %d\n", dev->width, dev->height, buf->vb.field); 
static int cx8802_start_dma(struct cx8802_dev    *dev,			    struct cx88_dmaqueue *q,			    struct cx88_buffer   *buf){	struct cx88_core *core = dev->core;	dprintk(0, "cx8802_start_dma %d\n", buf->vb.width);	/* setup fifo + format */	cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],				dev->ts_packet_size, buf->risc.dma);	/* write TS length to chip */	cx_write(MO_TS_LNGTH, buf->vb.width);	/* FIXME: this needs a review.	 * also: move to cx88-blackbird + cx88-dvb source files? */	if (cx88_boards[core->board].dvb) {		/* negedge driven & software reset */		cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);		udelay(100);		cx_write(MO_PINMUX_IO, 0x00);		cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);		switch (core->board) {		case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:		case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:		case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:			cx_write(TS_SOP_STAT, 1<<13);			break;		default:			cx_write(TS_SOP_STAT, 0x00);			break;		}		cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);		udelay(100);	}	if (cx88_boards[core->board].blackbird) {		cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */		cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */		udelay(100);		cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */		cx_write(TS_VALERR_CNTRL, 0x2000);		cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */		udelay(100);	}	/* reset counter */	cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);	q->count = 1;	/* enable irqs */	dprintk( 0, "setting the interrupt mask\n" );	cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);	cx_set(MO_TS_INTMSK,  0x1f0011);	/* start dma */	cx_set(MO_DEV_CNTRL2, (1<<5));	cx_set(MO_TS_DMACNTRL, 0x11);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/31629424132c87f7c8bd79d7ed4d014354a06427/cx88-mpeg.c/buggy/drivers/media/video/cx88/cx88-mpeg.c