for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) child->resource[i] = child->parent->resource[i]; return; 
for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) child->resource[i] = child->parent->resource[i - 3]; 
void __devinit pci_read_bridge_bases(struct pci_bus *child){	struct pci_dev *dev = child->self;	u8 io_base_lo, io_limit_lo;	u16 mem_base_lo, mem_limit_lo;	unsigned long base, limit;	struct resource *res;	int i;	if (!dev)		/* It's a host bus, nothing to read */		return;	if (dev->transparent) {		printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));		for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)			child->resource[i] = child->parent->resource[i];		return;	}	for(i=0; i<3; i++)		child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];	res = child->resource[0];	pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);	pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);	base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;	limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;	if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {		u16 io_base_hi, io_limit_hi;		pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);		pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);		base |= (io_base_hi << 16);		limit |= (io_limit_hi << 16);	}	if (base <= limit) {		res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;		res->start = base;		res->end = limit + 0xfff;	}	res = child->resource[1];	pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);	pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);	base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;	limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;	if (base <= limit) {		res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;		res->start = base;		res->end = limit + 0xfffff;	}	res = child->resource[2];	pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);	pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);	base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;	limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;	if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {		u32 mem_base_hi, mem_limit_hi;		pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);		pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);		/*		 * Some bridges set the base > limit by default, and some		 * (broken) BIOSes do not initialize them.  If we find		 * this, just assume they are not being used.		 */		if (mem_base_hi <= mem_limit_hi) {#if BITS_PER_LONG == 64			base |= ((long) mem_base_hi) << 32;			limit |= ((long) mem_limit_hi) << 32;#else			if (mem_base_hi || mem_limit_hi) {				printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));				return;			}#endif		}	}	if (base <= limit) {		res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;		res->start = base;		res->end = limit + 0xfffff;	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/90b54929b626c80056262d9d99b3f48522e404d0/probe.c/clean/drivers/pci/probe.c