if ((regs->cs & 3) == 0 && 
if (!user_mode(regs) && 
asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs){	void __user *rip = (void __user *)(regs->rip);	struct task_struct * task;	siginfo_t info;	unsigned short mxcsr;	conditional_sti(regs);	if ((regs->cs & 3) == 0 &&        	kernel_math_error(regs, "kernel simd math error"))		return;	/*	 * Save the info for the exception handler and clear the error.	 */	task = current;	save_init_fpu(task);	task->thread.trap_no = 19;	task->thread.error_code = 0;	info.si_signo = SIGFPE;	info.si_errno = 0;	info.si_code = __SI_FAULT;	info.si_addr = rip;	/*	 * The SIMD FPU exceptions are handled a little differently, as there	 * is only a single status/control register.  Thus, to determine which	 * unmasked exception was caught we must mask the exception mask bits	 * at 0x1f80, and then use these to mask the exception bits at 0x3f.	 */	mxcsr = get_fpu_mxcsr(task);	switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) {		case 0x000:		default:			break;		case 0x001: /* Invalid Op */			info.si_code = FPE_FLTINV;			break;		case 0x002: /* Denormalize */		case 0x010: /* Underflow */			info.si_code = FPE_FLTUND;			break;		case 0x004: /* Zero Divide */			info.si_code = FPE_FLTDIV;			break;		case 0x008: /* Overflow */			info.si_code = FPE_FLTOVF;			break;		case 0x020: /* Precision */			info.si_code = FPE_FLTRES;			break;	}	force_sig_info(SIGFPE, &info, task);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/76381fee7e8feb4c22be636aa5d4765dbe4fbf9e/traps.c/buggy/arch/x86_64/kernel/traps.c