static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs){	struct net_device *dev = (struct net_device *) dev_instance;	struct sbmac_softc *sc = netdev_priv(dev);	uint64_t isr;	int handled = 0;	for (;;) {				/*		 * Read the ISR (this clears the bits in the real		 * register, except for counter addr)		 */				isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;				if (isr == 0)			break;		handled = 1;				/*		 * Transmits on channel 0		 */				if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {			sbdma_tx_process(sc,&(sc->sbm_txdma));		}				/*		 * Receives on channel 0		 */		/*		 * It's important to test all the bits (or at least the		 * EOP_SEEN bit) when deciding to do the RX process		 * particularly when coalescing, to make sure we		 * take care of the following:		 *		 * If you have some packets waiting (have been received		 * but no interrupt) and get a TX interrupt before		 * the RX timer or counter expires, reading the ISR		 * above will clear the timer and counter, and you		 * won't get another interrupt until a packet shows		 * up to start the timer again.  Testing		 * EOP_SEEN here takes care of this case.		 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)		 */		 				if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {			sbdma_rx_process(sc,&(sc->sbm_rxdma));		}	}	return IRQ_RETVAL(handled);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/74b0247fbd4b6ed1693a420d85cf50267d840ef4/sb1250-mac.c/buggy/drivers/net/sb1250-mac.c