- dev->sg->handle + dev_priv->gart_vm_start); 
- (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start); 
static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ){	drm_radeon_private_t *dev_priv = dev->dev_private;;	DRM_DEBUG( "\n" );	dev_priv->is_pci = init->is_pci;	if ( dev_priv->is_pci && !dev->sg ) {		DRM_ERROR( "PCI GART memory not allocated!\n" );		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	dev_priv->usec_timeout = init->usec_timeout;	if ( dev_priv->usec_timeout < 1 ||	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {		DRM_DEBUG( "TIMEOUT problem!\n" );		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	switch(init->func) {	case RADEON_INIT_R200_CP:		dev_priv->microcode_version=UCODE_R200;		break;	case RADEON_INIT_R300_CP:		dev_priv->microcode_version=UCODE_R300;		break;	default:		dev_priv->microcode_version=UCODE_R100;	}		dev_priv->do_boxes = 0;	dev_priv->cp_mode = init->cp_mode;	/* We don't support anything other than bus-mastering ring mode,	 * but the ring can be in either AGP or PCI space for the ring	 * read pointer.	 */	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {		DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	switch ( init->fb_bpp ) {	case 16:		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;		break;	case 32:	default:		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;		break;	}	dev_priv->front_offset	= init->front_offset;	dev_priv->front_pitch	= init->front_pitch;	dev_priv->back_offset	= init->back_offset;	dev_priv->back_pitch	= init->back_pitch;	switch ( init->depth_bpp ) {	case 16:		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;		break;	case 32:	default:		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;		break;	}	dev_priv->depth_offset	= init->depth_offset;	dev_priv->depth_pitch	= init->depth_pitch;	/* Hardware state for depth clears.  Remove this if/when we no	 * longer clear the depth buffer with a 3D rectangle.  Hard-code	 * all values to prevent unwanted 3D state from slipping through	 * and screwing with the clear operation.	 */	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |					   (dev_priv->color_fmt << 10) |					   (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));	dev_priv->depth_clear.rb3d_zstencilcntl = 		(dev_priv->depth_fmt |		 RADEON_Z_TEST_ALWAYS |		 RADEON_STENCIL_TEST_ALWAYS |		 RADEON_STENCIL_S_FAIL_REPLACE |		 RADEON_STENCIL_ZPASS_REPLACE |		 RADEON_STENCIL_ZFAIL_REPLACE |		 RADEON_Z_WRITE_ENABLE);	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |					 RADEON_BFACE_SOLID |					 RADEON_FFACE_SOLID |					 RADEON_FLAT_SHADE_VTX_LAST |					 RADEON_DIFFUSE_SHADE_FLAT |					 RADEON_ALPHA_SHADE_FLAT |					 RADEON_SPECULAR_SHADE_FLAT |					 RADEON_FOG_SHADE_FLAT |					 RADEON_VTX_PIX_CENTER_OGL |					 RADEON_ROUND_MODE_TRUNC |					 RADEON_ROUND_PREC_8TH_PIX);	DRM_GETSAREA();	dev_priv->fb_offset = init->fb_offset;	dev_priv->mmio_offset = init->mmio_offset;	dev_priv->ring_offset = init->ring_offset;	dev_priv->ring_rptr_offset = init->ring_rptr_offset;	dev_priv->buffers_offset = init->buffers_offset;	dev_priv->gart_textures_offset = init->gart_textures_offset;		if(!dev_priv->sarea) {		DRM_ERROR("could not find sarea!\n");		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);	if(!dev_priv->mmio) {		DRM_ERROR("could not find mmio region!\n");		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);	if(!dev_priv->cp_ring) {		DRM_ERROR("could not find cp ring region!\n");		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);	if(!dev_priv->ring_rptr) {		DRM_ERROR("could not find ring read pointer!\n");		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	dev->agp_buffer_token = init->buffers_offset;	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);	if(!dev->agp_buffer_map) {		DRM_ERROR("could not find dma buffer region!\n");		dev->dev_private = (void *)dev_priv;		radeon_do_cleanup_cp(dev);		return DRM_ERR(EINVAL);	}	if ( init->gart_textures_offset ) {		dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);		if ( !dev_priv->gart_textures ) {			DRM_ERROR("could not find GART texture region!\n");			dev->dev_private = (void *)dev_priv;			radeon_do_cleanup_cp(dev);			return DRM_ERR(EINVAL);		}	}	dev_priv->sarea_priv =		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +				       init->sarea_priv_offset);#if __OS_HAS_AGP	if ( !dev_priv->is_pci ) {		drm_core_ioremap( dev_priv->cp_ring, dev );		drm_core_ioremap( dev_priv->ring_rptr, dev );		drm_core_ioremap( dev->agp_buffer_map, dev );		if(!dev_priv->cp_ring->handle ||		   !dev_priv->ring_rptr->handle ||		   !dev->agp_buffer_map->handle) {			DRM_ERROR("could not find ioremap agp regions!\n");			dev->dev_private = (void *)dev_priv;			radeon_do_cleanup_cp(dev);			return DRM_ERR(EINVAL);		}	} else#endif	{		dev_priv->cp_ring->handle =			(void *)dev_priv->cp_ring->offset;		dev_priv->ring_rptr->handle =			(void *)dev_priv->ring_rptr->offset;		dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;		DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",			   dev_priv->cp_ring->handle );		DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",			   dev_priv->ring_rptr->handle );		DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",			   dev->agp_buffer_map->handle );	}	dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )				& 0xffff ) << 16;	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |					( ( dev_priv->front_offset					  + dev_priv->fb_location ) >> 10 ) );	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |				       ( ( dev_priv->back_offset					 + dev_priv->fb_location ) >> 10 ) );	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |					( ( dev_priv->depth_offset					  + dev_priv->fb_location ) >> 10 ) );	dev_priv->gart_size = init->gart_size;	dev_priv->gart_vm_start = dev_priv->fb_location				+ RADEON_READ( RADEON_CONFIG_APER_SIZE );#if __OS_HAS_AGP	if ( !dev_priv->is_pci )		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset						- dev->agp->base						+ dev_priv->gart_vm_start);	else#endif		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset						- dev->sg->handle						+ dev_priv->gart_vm_start);	DRM_DEBUG( "dev_priv->gart_size %d\n",		   dev_priv->gart_size );	DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",		   dev_priv->gart_vm_start );	DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",		   dev_priv->gart_buffers_offset );	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle			      + init->ring_size / sizeof(u32));	dev_priv->ring.size = init->ring_size;	dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );	dev_priv->ring.tail_mask =		(dev_priv->ring.size / sizeof(u32)) - 1;	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;#if __OS_HAS_AGP	if ( !dev_priv->is_pci ) {		/* Turn off PCI GART */		radeon_set_pcigart( dev_priv, 0 );	} else#endif	{		if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,					    &dev_priv->bus_pci_gart)) {			DRM_ERROR( "failed to init PCI GART!\n" );			dev->dev_private = (void *)dev_priv;			radeon_do_cleanup_cp(dev);			return DRM_ERR(ENOMEM);		}		/* Turn on PCI GART */		radeon_set_pcigart( dev_priv, 1 );	}	radeon_cp_load_microcode( dev_priv );	radeon_cp_init_ring_buffer( dev, dev_priv );	dev_priv->last_buf = 0;	dev->dev_private = (void *)dev_priv;	radeon_do_engine_reset( dev );	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/b0917bd912d3708c50e1df1b5e1648d0547108a3/radeon_cp.c/buggy/drivers/char/drm/radeon_cp.c