*      prefetch TLB entries 
* 	DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029 
tioca_gart_init(struct tioca_kernel *tioca_kern){	uint64_t ap_reg;	uint64_t offset;	struct page *tmp;	struct tioca_common *tioca_common;	volatile struct tioca *ca_base;	tioca_common = tioca_kern->ca_common;	ca_base = (struct tioca *)tioca_common->ca_common.bs_base;	if (list_empty(tioca_kern->ca_devices))		return 0;	ap_reg = 0;	/*	 * Validate aperature size	 */	switch (CA_APERATURE_SIZE >> 20) {	case 4:		ap_reg |= (0x3ff << CA_GART_AP_SIZE_SHFT);	/* 4MB */		break;	case 8:		ap_reg |= (0x3fe << CA_GART_AP_SIZE_SHFT);	/* 8MB */		break;	case 16:		ap_reg |= (0x3fc << CA_GART_AP_SIZE_SHFT);	/* 16MB */		break;	case 32:		ap_reg |= (0x3f8 << CA_GART_AP_SIZE_SHFT);	/* 32 MB */		break;	case 64:		ap_reg |= (0x3f0 << CA_GART_AP_SIZE_SHFT);	/* 64 MB */		break;	case 128:		ap_reg |= (0x3e0 << CA_GART_AP_SIZE_SHFT);	/* 128 MB */		break;	case 256:		ap_reg |= (0x3c0 << CA_GART_AP_SIZE_SHFT);	/* 256 MB */		break;	case 512:		ap_reg |= (0x380 << CA_GART_AP_SIZE_SHFT);	/* 512 MB */		break;	case 1024:		ap_reg |= (0x300 << CA_GART_AP_SIZE_SHFT);	/* 1GB */		break;	case 2048:		ap_reg |= (0x200 << CA_GART_AP_SIZE_SHFT);	/* 2GB */		break;	case 4096:		ap_reg |= (0x000 << CA_GART_AP_SIZE_SHFT);	/* 4 GB */		break;	default:		printk(KERN_ERR "%s:  Invalid CA_APERATURE_SIZE "		       "0x%lx\n", __FUNCTION__, (ulong) CA_APERATURE_SIZE);		return -1;	}	/*	 * Set up other aperature parameters	 */	if (PAGE_SIZE >= 16384) {		tioca_kern->ca_ap_pagesize = 16384;		ap_reg |= CA_GART_PAGE_SIZE;	} else {		tioca_kern->ca_ap_pagesize = 4096;	}	tioca_kern->ca_ap_size = CA_APERATURE_SIZE;	tioca_kern->ca_ap_bus_base = CA_APERATURE_BASE;	tioca_kern->ca_gart_entries =	    tioca_kern->ca_ap_size / tioca_kern->ca_ap_pagesize;	ap_reg |= (CA_GART_AP_ENB_AGP | CA_GART_AP_ENB_PCI);	ap_reg |= tioca_kern->ca_ap_bus_base;	/*	 * Allocate and set up the GART	 */	tioca_kern->ca_gart_size = tioca_kern->ca_gart_entries * sizeof(u64);	tmp =	    alloc_pages_node(tioca_kern->ca_closest_node,			     GFP_KERNEL | __GFP_ZERO,			     get_order(tioca_kern->ca_gart_size));	if (!tmp) {		printk(KERN_ERR "%s:  Could not allocate "		       "%lu bytes (order %d) for GART\n",		       __FUNCTION__,		       tioca_kern->ca_gart_size,		       get_order(tioca_kern->ca_gart_size));		return -ENOMEM;	}	tioca_kern->ca_gart = page_address(tmp);	tioca_kern->ca_gart_coretalk_addr =	    PHYS_TO_TIODMA(virt_to_phys(tioca_kern->ca_gart));	/*	 * Compute PCI/AGP convenience fields 	 */	offset = CA_PCI32_MAPPED_BASE - CA_APERATURE_BASE;	tioca_kern->ca_pciap_base = CA_PCI32_MAPPED_BASE;	tioca_kern->ca_pciap_size = CA_PCI32_MAPPED_SIZE;	tioca_kern->ca_pcigart_start = offset / tioca_kern->ca_ap_pagesize;	tioca_kern->ca_pcigart_base =	    tioca_kern->ca_gart_coretalk_addr + offset;	tioca_kern->ca_pcigart =	    &tioca_kern->ca_gart[tioca_kern->ca_pcigart_start];	tioca_kern->ca_pcigart_entries =	    tioca_kern->ca_pciap_size / tioca_kern->ca_ap_pagesize;	tioca_kern->ca_pcigart_pagemap =	    kcalloc(1, tioca_kern->ca_pcigart_entries / 8, GFP_KERNEL);	if (!tioca_kern->ca_pcigart_pagemap) {		free_pages((unsigned long)tioca_kern->ca_gart,			   get_order(tioca_kern->ca_gart_size));		return -1;	}	offset = CA_AGP_MAPPED_BASE - CA_APERATURE_BASE;	tioca_kern->ca_gfxap_base = CA_AGP_MAPPED_BASE;	tioca_kern->ca_gfxap_size = CA_AGP_MAPPED_SIZE;	tioca_kern->ca_gfxgart_start = offset / tioca_kern->ca_ap_pagesize;	tioca_kern->ca_gfxgart_base =	    tioca_kern->ca_gart_coretalk_addr + offset;	tioca_kern->ca_gfxgart =	    &tioca_kern->ca_gart[tioca_kern->ca_gfxgart_start];	tioca_kern->ca_gfxgart_entries =	    tioca_kern->ca_gfxap_size / tioca_kern->ca_ap_pagesize;	/*	 * various control settings:	 *      use agp op-combining	 *      use GET semantics to fetch memory	 *      participate in coherency domain	 *      prefetch TLB entries	 */	ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY;	/* PV895469 ? */	ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);	ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);	tioca_kern->ca_gart_iscoherent = 1;	ca_base->ca_control2 |=	    (CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);	/*	 * Unmask GART fetch error interrupts.  Clear residual errors first.	 */	ca_base->ca_int_status_alias = CA_GART_FETCH_ERR;	ca_base->ca_mult_error_alias = CA_GART_FETCH_ERR;	ca_base->ca_int_mask &= ~CA_GART_FETCH_ERR;	/*	 * Program the aperature and gart registers in TIOCA	 */	ca_base->ca_gart_aperature = ap_reg;	ca_base->ca_gart_ptr_table = tioca_kern->ca_gart_coretalk_addr | 1;	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/4628d7cada7a19166ba8fe57f5ef0f0009694e1e/tioca_provider.c/clean/arch/ia64/sn/pci/tioca_provider.c