#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1) 
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 
asmlinkage void cache_parity_error(void){	const int field = 2 * sizeof(unsigned long);	unsigned int reg_val;	/* For the moment, report the problem and hang. */	printk("Cache error exception:\n");	printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());	reg_val = read_c0_cacheerr();	printk("c0_cacheerr == %08x\n", reg_val);	printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",	       reg_val & (1<<30) ? "secondary" : "primary",	       reg_val & (1<<31) ? "data" : "insn");	printk("Error bits: %s%s%s%s%s%s%s\n",	       reg_val & (1<<29) ? "ED " : "",	       reg_val & (1<<28) ? "ET " : "",	       reg_val & (1<<26) ? "EE " : "",	       reg_val & (1<<25) ? "EB " : "",	       reg_val & (1<<24) ? "EI " : "",	       reg_val & (1<<23) ? "E1 " : "",	       reg_val & (1<<22) ? "E0 " : "");	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)	if (reg_val & (1<<22))		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());	if (reg_val & (1<<23))		printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());#endif	panic("Can't handle the cache error!");}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/ec917c2c1ab4359a1d438e62daeb50cc42e632e1/traps.c/buggy/arch/mips/kernel/traps.c