outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI); outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO); 
outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); 
static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase){#if 0	/* Turn off chip DMA */	register_bank(iobase, 1);	outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,	     iobase+IRCC_SCE_CFGB);#endif	/* Disable Tx */	register_bank(iobase, 0);	outb(0x00, iobase+IRCC_LCR_B);	/* Turn off chip DMA */	register_bank(iobase, 1);	outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,	     iobase+IRCC_SCE_CFGB);	self->io.direction = IO_RECV;	self->rx_buff.data = self->rx_buff.head;	/* Set max Rx frame size */	register_bank(iobase, 4);	outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI);	outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO);	/* Setup DMA controller */	irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,		       DMA_RX_MODE);	/* Enable burst mode chip Rx DMA */	register_bank(iobase, 1);	outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |	     IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);	/* Enable interrupt */	register_bank(iobase, 0);	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);	outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);	/* Enable receiver */	register_bank(iobase, 0);	outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,	     iobase+IRCC_LCR_B);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/98b7777331d4344821e900040da5d1d3016d9e67/smsc-ircc2.c/clean/drivers/net/irda/smsc-ircc2.c