int i; 
mpc85xx_cds_init_IRQ(void){	bd_t *binfo = (bd_t *) __res;	int i;	/* Determine the Physical Address of the OpenPIC regs */	phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);	OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;	OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);	/* Skip reserved space and internal sources */	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);	/* Map PIC IRQs 0-11 */	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);	/* we let openpic interrupts starting from an offset, to	 * leave space for cascading interrupts underneath.	 */	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);#ifdef CONFIG_PCI	openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);	for (i = 0; i < NUM_8259_INTERRUPTS; i++)		irq_desc[i].handler = &i8259_pic;	i8259_init(0);#endif#ifdef CONFIG_CPM2	/* Setup CPM2 PIC */        cpm2_init_IRQ();	setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);#endif	return;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/65145e060b1c933ebc4215c3b493f586e08a1d5c/mpc85xx_cds_common.c/clean/arch/ppc/platforms/85xx/mpc85xx_cds_common.c