nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC); 
nxt6000_writereg(state, VIT_BERTIME_2, 0x00); nxt6000_writereg(state, VIT_BERTIME_1, 0x02); nxt6000_writereg(state, VIT_BERTIME_0, 0x00); nxt6000_writereg(state, VIT_COR_INTEN, 0x98); nxt6000_writereg(state, VIT_COR_CTL, 0x82); nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC | 0x02 ); 
static void nxt6000_setup(struct dvb_frontend* fe){	struct nxt6000_state* state = (struct nxt6000_state*) fe->demodulator_priv;	nxt6000_writereg(state, RS_COR_SYNC_PARAM, SYNC_PARAM);	nxt6000_writereg(state, BER_CTRL, /*(1 << 2) | */ (0x01 << 1) | 0x01);	nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC);	nxt6000_writereg(state, OFDM_COR_CTL, (0x01 << 5) | (nxt6000_readreg(state, OFDM_COR_CTL) & 0x0F));	nxt6000_writereg(state, OFDM_COR_MODEGUARD, FORCEMODE8K | 0x02);	nxt6000_writereg(state, OFDM_AGC_CTL, AGCLAST | INITIAL_AGC_BW);	nxt6000_writereg(state, OFDM_ITB_FREQ_1, 0x06);	nxt6000_writereg(state, OFDM_ITB_FREQ_2, 0x31);	nxt6000_writereg(state, OFDM_CAS_CTL, (0x01 << 7) | (0x02 << 3) | 0x04);	nxt6000_writereg(state, CAS_FREQ, 0xBB);	/* CHECKME */	nxt6000_writereg(state, OFDM_SYR_CTL, 1 << 2);	nxt6000_writereg(state, OFDM_PPM_CTL_1, PPM256);	nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, 0x49);	nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, 0x72);	nxt6000_writereg(state, ANALOG_CONTROL_0, 1 << 5);	nxt6000_writereg(state, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2);	nxt6000_writereg(state, DIAG_CONFIG, TB_SET);	if (state->config->clock_inversion)		nxt6000_writereg(state, SUB_DIAG_MODE_SEL, CLKINVERSION);	else		nxt6000_writereg(state, SUB_DIAG_MODE_SEL, 0);	nxt6000_writereg(state, TS_FORMAT, 0);	if (state->config->pll_init) {		nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x01);	/* open i2c bus switch */		state->config->pll_init(fe);		nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x00);	/* close i2c bus switch */	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3a4a571124cdd04215e0f78bc53fe16bab58f32d/nxt6000.c/clean/drivers/media/dvb/frontends/nxt6000.c