/* ** clear I/O PDIR entry "valid" bit ** Do NOT clear the rest - save it for debugging. ** We should only clear bits that have previously ** been enabled. */ ((u8 *)(ioc->pdir_base))[off] = 0; } else { u32 t = get_order(byte_cnt) + PAGE_SHIFT;  iovp |= t; do { /* clear I/O Pdir entry "valid" bit first */ ((u8 *)(ioc->pdir_base))[off] = 0; off += sizeof(u64); byte_cnt -= IOVP_SIZE; } while (byte_cnt > 0); } 
/* ** clear I/O PDIR entry "valid" bit. ** We have to R/M/W the cacheline regardless how much of the ** pdir entry that we clobber. ** The rest of the entry would be useful for debugging if we ** could dump core on HPMC. */ ((u8 *) pdir_ptr)[7] = 0; if (ioc_needs_fdc) asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 
sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt){	u32 iovp = (u32) SBA_IOVP(ioc,iova);	/* Even though this is a big-endian machine, the entries	** in the iopdir are little endian. That's why we clear the byte	** at +7 instead of at +0.	*/	int off = PDIR_INDEX(iovp)*sizeof(u64)+7;#ifdef ASSERT_PDIR_SANITY	/* Assert first pdir entry is set */	if (0x80 != (((u8 *) ioc->pdir_base)[off])) {		sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));	}#endif	if (byte_cnt <= IOVP_SIZE)	{		iovp |= IOVP_SHIFT;     /* set "size" field for PCOM */		/*		** clear I/O PDIR entry "valid" bit		** Do NOT clear the rest - save it for debugging.		** We should only clear bits that have previously		** been enabled.		*/		((u8 *)(ioc->pdir_base))[off] = 0;	} else {		u32 t = get_order(byte_cnt) + PAGE_SHIFT;		iovp |= t;		do {			/* clear I/O Pdir entry "valid" bit first */			((u8 *)(ioc->pdir_base))[off] = 0;			off += sizeof(u64);			byte_cnt -= IOVP_SIZE;		} while (byte_cnt > 0);	}	WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/64908ad95c34f25849412d6d4735ac10f8fb6575/sba_iommu.c/buggy/drivers/parisc/sba_iommu.c