writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig); 
writel(np->rx_buf_sz, base + NvRegOffloadConfig); 
static int nv_open(struct net_device *dev){	struct fe_priv *np = get_nvpriv(dev);	u8 __iomem *base = get_hwbase(dev);	int ret, oom, i;	dprintk(KERN_DEBUG "nv_open: begin\n");	/* 1) erase previous misconfiguration */	/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);	writel(0, base + NvRegMulticastAddrB);	writel(0, base + NvRegMulticastMaskA);	writel(0, base + NvRegMulticastMaskB);	writel(0, base + NvRegPacketFilterFlags);	writel(0, base + NvRegTransmitterControl);	writel(0, base + NvRegReceiverControl);	writel(0, base + NvRegAdapterControl);	/* 2) initialize descriptor rings */	oom = nv_init_ring(dev);	writel(0, base + NvRegLinkSpeed);	writel(0, base + NvRegUnknownTransmitterReg);	nv_txrx_reset(dev);	writel(0, base + NvRegUnknownSetupReg6);	np->in_shutdown = 0;	/* 3) set mac address */	{		u32 mac[2];		mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +				(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);		mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);		writel(mac[0], base + NvRegMacAddrA);		writel(mac[1], base + NvRegMacAddrB);	}	/* 4) give hw rings */	writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);	writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);	writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),		base + NvRegRingSizes);	/* 5) continue setup */	writel(np->linkspeed, base + NvRegLinkSpeed);	writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);	writel(np->desc_ver, base + NvRegTxRxControl);	pci_push(base);	writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);	reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,			NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,			KERN_INFO "open: SetupReg5, Bit 31 remained off\n");	writel(0, base + NvRegUnknownSetupReg4);	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);	/* 6) continue setup */	writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);	writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);	writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);	get_random_bytes(&i, sizeof(i));	writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);	writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);	writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);	writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,			base + NvRegAdapterControl);	writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);	writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);	writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);	i = readl(base + NvRegPowerState);	if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)		writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);	pci_push(base);	udelay(10);	writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);	writel(0, base + NvRegIrqMask);	pci_push(base);	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);	pci_push(base);	ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);	if (ret)		goto out_drain;	/* ask for interrupts */	writel(np->irqmask, base + NvRegIrqMask);	spin_lock_irq(&np->lock);	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);	writel(0, base + NvRegMulticastAddrB);	writel(0, base + NvRegMulticastMaskA);	writel(0, base + NvRegMulticastMaskB);	writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);	/* One manual link speed update: Interrupts are enabled, future link	 * speed changes cause interrupts and are handled by nv_link_irq().	 */	{		u32 miistat;		miistat = readl(base + NvRegMIIStatus);		writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);		dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);	}	ret = nv_update_linkspeed(dev);	nv_start_rx(dev);	nv_start_tx(dev);	netif_start_queue(dev);	if (ret) {		netif_carrier_on(dev);	} else {		printk("%s: no link during initialization.\n", dev->name);		netif_carrier_off(dev);	}	if (oom)		mod_timer(&np->oom_kick, jiffies + OOM_REFILL);	spin_unlock_irq(&np->lock);	return 0;out_drain:	drain_ring(dev);	return ret;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/d81c0983de80c956cf37835b0d35adb3ab4bb03a/forcedeth.c/buggy/drivers/net/forcedeth.c