memset(rxdp, 0, sizeof(RxD_t)); rxdp->Buffer2_ptr = pci_map_single (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4, PCI_DMA_FROMDEVICE); rxdp->Buffer0_ptr = pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN, PCI_DMA_FROMDEVICE); rxdp->Buffer1_ptr = pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN, PCI_DMA_FROMDEVICE);  rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4); rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN); rxdp->Control_2 |= SET_BUFFER1_SIZE(1);	/* dummy. */ rxdp->Control_2 |= BIT(0);	/* Set Buffer_Empty bit. */ rxdp->Host_Control = (u64) ((unsigned long) (skb)); if (alloc_tab & ((1 << rxsync_frequency) - 1)) rxdp->Control_1 |= RXD_OWN_XENA; off++; mac_control->rings[ring_no].rx_curr_put_info.offset = off; #endif 
int fill_rx_buffers(struct s2io_nic *nic, int ring_no){	struct net_device *dev = nic->dev;	struct sk_buff *skb;	RxD_t *rxdp;	int off, off1, size, block_no, block_no1;	int offset, offset1;	u32 alloc_tab = 0;	u32 alloc_cnt;	mac_info_t *mac_control;	struct config_param *config;#ifdef CONFIG_2BUFF_MODE	RxD_t *rxdpnext;	int nextblk;	u64 tmp;	buffAdd_t *ba;	dma_addr_t rxdpphys;#endif#ifndef CONFIG_S2IO_NAPI	unsigned long flags;#endif	RxD_t *first_rxdp = NULL;	mac_control = &nic->mac_control;	config = &nic->config;	alloc_cnt = mac_control->rings[ring_no].pkt_cnt -	    atomic_read(&nic->rx_bufs_left[ring_no]);	size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +	    HEADER_802_2_SIZE + HEADER_SNAP_SIZE;	while (alloc_tab < alloc_cnt) {		block_no = mac_control->rings[ring_no].rx_curr_put_info.		    block_index;		block_no1 = mac_control->rings[ring_no].rx_curr_get_info.		    block_index;		off = mac_control->rings[ring_no].rx_curr_put_info.offset;		off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;#ifndef CONFIG_2BUFF_MODE		offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;#else		offset = block_no * (MAX_RXDS_PER_BLOCK) + off;		offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;#endif		rxdp = mac_control->rings[ring_no].rx_blocks[block_no].		    block_virt_addr + off;		if ((offset == offset1) && (rxdp->Host_Control)) {			DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);			DBG_PRINT(INTR_DBG, " info equated\n");			goto end;		}#ifndef	CONFIG_2BUFF_MODE		if (rxdp->Control_1 == END_OF_BLOCK) {			mac_control->rings[ring_no].rx_curr_put_info.			    block_index++;			mac_control->rings[ring_no].rx_curr_put_info.			    block_index %= mac_control->rings[ring_no].block_count;			block_no = mac_control->rings[ring_no].rx_curr_put_info.				block_index;			off++;			off %= (MAX_RXDS_PER_BLOCK + 1);			mac_control->rings[ring_no].rx_curr_put_info.offset =			    off;			rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);			DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",				  dev->name, rxdp);		}#ifndef CONFIG_S2IO_NAPI		spin_lock_irqsave(&nic->put_lock, flags);		mac_control->rings[ring_no].put_pos =		    (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;		spin_unlock_irqrestore(&nic->put_lock, flags);#endif#else		if (rxdp->Host_Control == END_OF_BLOCK) {			mac_control->rings[ring_no].rx_curr_put_info.			    block_index++;			mac_control->rings[ring_no].rx_curr_put_info.block_index			    %= mac_control->rings[ring_no].block_count;			block_no = mac_control->rings[ring_no].rx_curr_put_info			    .block_index;			off = 0;			DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",				  dev->name, block_no,				  (unsigned long long) rxdp->Control_1);			mac_control->rings[ring_no].rx_curr_put_info.offset =			    off;			rxdp = mac_control->rings[ring_no].rx_blocks[block_no].			    block_virt_addr;		}#ifndef CONFIG_S2IO_NAPI		spin_lock_irqsave(&nic->put_lock, flags);		mac_control->rings[ring_no].put_pos = (block_no *					 (MAX_RXDS_PER_BLOCK + 1)) + off;		spin_unlock_irqrestore(&nic->put_lock, flags);#endif#endif#ifndef	CONFIG_2BUFF_MODE		if (rxdp->Control_1 & RXD_OWN_XENA)#else		if (rxdp->Control_2 & BIT(0))#endif		{			mac_control->rings[ring_no].rx_curr_put_info.			    offset = off;			goto end;		}#ifdef	CONFIG_2BUFF_MODE		/*		 * RxDs Spanning cache lines will be replenished only		 * if the succeeding RxD is also owned by Host. It		 * will always be the ((8*i)+3) and ((8*i)+6)		 * descriptors for the 48 byte descriptor. The offending		 * decsriptor is of-course the 3rd descriptor.		 */		rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].		    block_dma_addr + (off * sizeof(RxD_t));		if (((u64) (rxdpphys)) % 128 > 80) {			rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].			    block_virt_addr + (off + 1);			if (rxdpnext->Host_Control == END_OF_BLOCK) {				nextblk = (block_no + 1) %				    (mac_control->rings[ring_no].block_count);				rxdpnext = mac_control->rings[ring_no].rx_blocks				    [nextblk].block_virt_addr;			}			if (rxdpnext->Control_2 & BIT(0))				goto end;		}#endif#ifndef	CONFIG_2BUFF_MODE		skb = dev_alloc_skb(size + NET_IP_ALIGN);#else		skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);#endif		if (!skb) {			DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);			DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");			if (first_rxdp) {				wmb();				first_rxdp->Control_1 |= RXD_OWN_XENA;			}			return -ENOMEM;		}#ifndef	CONFIG_2BUFF_MODE		skb_reserve(skb, NET_IP_ALIGN);		memset(rxdp, 0, sizeof(RxD_t));		rxdp->Buffer0_ptr = pci_map_single		    (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);		rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);		rxdp->Control_2 |= SET_BUFFER0_SIZE(size);		rxdp->Host_Control = (unsigned long) (skb);		if (alloc_tab & ((1 << rxsync_frequency) - 1))			rxdp->Control_1 |= RXD_OWN_XENA;		off++;		off %= (MAX_RXDS_PER_BLOCK + 1);		mac_control->rings[ring_no].rx_curr_put_info.offset = off;#else		ba = &mac_control->rings[ring_no].ba[block_no][off];		skb_reserve(skb, BUF0_LEN);		tmp = ((unsigned long) skb->data & ALIGN_SIZE);		if (tmp)			skb_reserve(skb, (ALIGN_SIZE + 1) - tmp);		memset(rxdp, 0, sizeof(RxD_t));		rxdp->Buffer2_ptr = pci_map_single		    (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,		     PCI_DMA_FROMDEVICE);		rxdp->Buffer0_ptr =		    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,				   PCI_DMA_FROMDEVICE);		rxdp->Buffer1_ptr =		    pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,				   PCI_DMA_FROMDEVICE);		rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);		rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);		rxdp->Control_2 |= SET_BUFFER1_SIZE(1);	/* dummy. */		rxdp->Control_2 |= BIT(0);	/* Set Buffer_Empty bit. */		rxdp->Host_Control = (u64) ((unsigned long) (skb));		if (alloc_tab & ((1 << rxsync_frequency) - 1))			rxdp->Control_1 |= RXD_OWN_XENA;		off++;		mac_control->rings[ring_no].rx_curr_put_info.offset = off;#endif		rxdp->Control_2 |= SET_RXD_MARKER;		if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {			if (first_rxdp) {				wmb();				first_rxdp->Control_1 |= RXD_OWN_XENA;			}			first_rxdp = rxdp;		}		atomic_inc(&nic->rx_bufs_left[ring_no]);		alloc_tab++;	}      end:	/* Transfer ownership of first descriptor to adapter just before	 * exiting. Before that, use memory barrier so that ownership	 * and other fields are seen by adapter correctly.	 */	if (first_rxdp) {		wmb();		first_rxdp->Control_1 |= RXD_OWN_XENA;	}	return SUCCESS;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/da6971d8ece2ec9762509e20dda6808335b5a10b/s2io.c/clean/drivers/net/s2io.c