if (radeon_no_wb == 1) { dev_priv->writeback_works = 0; DRM_DEBUG("writeback forced off\n"); } 
static void radeon_cp_init_ring_buffer(drm_device_t * dev,				       drm_radeon_private_t * dev_priv){	u32 ring_start, cur_read_ptr;	u32 tmp;	/* Initialize the memory controller */	RADEON_WRITE(RADEON_MC_FB_LOCATION,		     ((dev_priv->gart_vm_start - 1) & 0xffff0000)		     | (dev_priv->fb_location >> 16));#if __OS_HAS_AGP	if (!dev_priv->is_pci) {		RADEON_WRITE(RADEON_MC_AGP_LOCATION,			     (((dev_priv->gart_vm_start - 1 +				dev_priv->gart_size) & 0xffff0000) |			      (dev_priv->gart_vm_start >> 16)));		ring_start = (dev_priv->cp_ring->offset			      - dev->agp->base + dev_priv->gart_vm_start);	} else#endif		ring_start = (dev_priv->cp_ring->offset			      - dev->sg->handle + dev_priv->gart_vm_start);	RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);	/* Set the write pointer delay */	RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);	/* Initialize the ring buffer's read and write pointers */	cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);	RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);	SET_RING_HEAD(dev_priv, cur_read_ptr);	dev_priv->ring.tail = cur_read_ptr;#if __OS_HAS_AGP	if (!dev_priv->is_pci) {		/* set RADEON_AGP_BASE here instead of relying on X from user space */		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,			     dev_priv->ring_rptr->offset			     - dev->agp->base + dev_priv->gart_vm_start);	} else#endif	{		drm_sg_mem_t *entry = dev->sg;		unsigned long tmp_ofs, page_ofs;		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;		page_ofs = tmp_ofs >> PAGE_SHIFT;		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);		DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",			  (unsigned long)entry->busaddr[page_ofs],			  entry->handle + tmp_ofs);	}	/* Initialize the scratch register pointer.  This will cause	 * the scratch register values to be written out to memory	 * whenever they are updated.	 *	 * We simply put this behind the ring read pointer, this works	 * with PCI GART as well as (whatever kind of) AGP GART	 */	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)		     + RADEON_SCRATCH_REG_OFFSET);	dev_priv->scratch = ((__volatile__ u32 *)			     dev_priv->ring_rptr->handle +			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);	/* Writeback doesn't seem to work everywhere, test it first */	DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);	RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);	for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {		if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==		    0xdeadbeef)			break;		DRM_UDELAY(1);	}	if (tmp < dev_priv->usec_timeout) {		dev_priv->writeback_works = 1;		DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);	} else {		dev_priv->writeback_works = 0;		DRM_DEBUG("writeback test failed\n");	}	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;	RADEON_WRITE(RADEON_LAST_DISPATCH_REG,		     dev_priv->sarea_priv->last_dispatch);	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;	RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);	/* Set ring buffer size */#ifdef __BIG_ENDIAN	RADEON_WRITE(RADEON_CP_RB_CNTL,		     dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);#else	RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);#endif	radeon_do_wait_for_idle(dev_priv);	/* Turn on bus mastering */	tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;	RADEON_WRITE(RADEON_BUS_CNTL, tmp);	/* Sync everything up */	RADEON_WRITE(RADEON_ISYNC_CNTL,		     (RADEON_ISYNC_ANY2D_IDLE3D |		      RADEON_ISYNC_ANY3D_IDLE2D |		      RADEON_ISYNC_WAIT_IDLEGUI |		      RADEON_ISYNC_CPSCRATCH_IDLEGUI));}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/689b9d74b1c00e1316fbb7d1e912fe1227fdb1ab/radeon_cp.c/clean/drivers/char/drm/radeon_cp.c