/* XXX this is broken... */ 
void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,			  unsigned long r6, unsigned long r7){	u8 val8;	u8 rev_num;	/* Map 0xe0000000-0xffffffff early because we need access to SRAM	 * and the ISA memory space (for serial port) here. This mapping	 * is redone properly in ppc7d_map_io() later.	 */	mtspr(SPRN_DBAT3U, 0xe0003fff);	mtspr(SPRN_DBAT3L, 0xe000002a);	/*	 * Zero SRAM. Note that this generates parity errors on	 * internal data path in SRAM if it's first time accessing it	 * after reset.	 *	 * We do this ASAP to avoid parity errors when reading	 * uninitialized SRAM.	 */	memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);	pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",		 r3, r4, r5, r6, r7);	parse_bootinfo(find_bootinfo());	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)	 * are non-zero, then we should use the board info from the bd_t	 * structure and the cmdline pointed to by r6 instead of the	 * information from birecs, if any.  Otherwise, use the information	 * from birecs as discovered by the preceeding call to	 * parse_bootinfo().  This rule should work with both PPCBoot, which	 * uses a bd_t board info structure, and the kernel boot wrapper,	 * which uses birecs.	 */	if (r3 && r6) {		bd_t *bp = (bd_t *) __res;		/* copy board info structure */		memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));		/* copy command line */		*(char *)(r7 + KERNELBASE) = 0;		strcpy(cmd_line, (char *)(r6 + KERNELBASE));		printk(KERN_INFO "Board info data:-\n");		printk(KERN_INFO "  Internal freq: %lu MHz, bus freq: %lu MHz\n",		       bp->bi_intfreq, bp->bi_busfreq);		printk(KERN_INFO "  Memory: %lx, size %lx\n", bp->bi_memstart,		       bp->bi_memsize);		printk(KERN_INFO "  Console baudrate: %lu\n", bp->bi_baudrate);		printk(KERN_INFO "  Ethernet address: "		       "%02x:%02x:%02x:%02x:%02x:%02x\n",		       bp->bi_enetaddr[0], bp->bi_enetaddr[1],		       bp->bi_enetaddr[2], bp->bi_enetaddr[3],		       bp->bi_enetaddr[4], bp->bi_enetaddr[5]);	}#ifdef CONFIG_BLK_DEV_INITRD	/* take care of initrd if we have one */	if (r4) {		initrd_start = r4 + KERNELBASE;		initrd_end = r5 + KERNELBASE;		printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);	}#endif /* CONFIG_BLK_DEV_INITRD */	/* Map in board regs, etc. */	isa_io_base = 0xe8000000;	isa_mem_base = 0xe8000000;	pci_dram_offset = 0x00000000;	ISA_DMA_THRESHOLD = 0x00ffffff;	DMA_MODE_READ = 0x44;	DMA_MODE_WRITE = 0x48;	ppc_md.setup_arch = ppc7d_setup_arch;	ppc_md.init = ppc7d_init2;	ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;	ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;	ppc_md.init_IRQ = ppc7d_init_irq;	ppc_md.get_irq = ppc7d_get_irq;	ppc_md.restart = ppc7d_restart;	ppc_md.power_off = ppc7d_power_off;	ppc_md.halt = ppc7d_halt;	ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;	ppc_md.setup_io_mappings = ppc7d_map_io;	ppc_md.time_init = NULL;	ppc_md.set_rtc_time = NULL;	ppc_md.get_rtc_time = NULL;	ppc_md.calibrate_decr = ppc7d_calibrate_decr;	ppc_md.nvram_read_val = NULL;	ppc_md.nvram_write_val = NULL;	ppc_md.heartbeat = ppc7d_heartbeat;	ppc_md.heartbeat_reset = HZ;	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \    defined(CONFIG_I2C_MV64XXX)	platform_notify = ppc7d_platform_notify;#endif#ifdef CONFIG_SERIAL_MPSC	/* On PPC7D, we must configure MPSC support via CPLD control	 * registers.	 */	outb(PPC7D_CPLD_RTS_COM4_SCLK |	     PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);	outb(PPC7D_CPLD_COMS_COM3_TCLKEN |	     PPC7D_CPLD_COMS_COM3_TXEN |	     PPC7D_CPLD_COMS_COM4_TCLKEN |	     PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);#endif /* CONFIG_SERIAL_MPSC */#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)	ppc7d_early_serial_map();#ifdef  CONFIG_SERIAL_TEXT_DEBUG#if defined(CONFIG_SERIAL_MPSC_CONSOLE)	ppc_md.progress = mv64x60_mpsc_progress;#elif defined(CONFIG_SERIAL_8250)	ppc_md.progress = gen550_progress;#else#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX#endif /* CONFIG_SERIAL_8250 */#endif /* CONFIG_SERIAL_TEXT_DEBUG */#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */	/* Enable write access to user flash.  This is necessary for	 * flash probe.	 */	val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);	writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &		       PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),	       (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);	/* Determine if this board has IBM ALMA VME devices */	val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;	if (rev_num <= 1)		ppc7d_has_alma = 1;#ifdef DEBUG	console_printk[0] = 8;#endif}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/35d81a4bfe28a6ea81c9f67c9ce40543124ded0b/radstone_ppc7d.c/clean/arch/ppc/platforms/radstone_ppc7d.c