MV64360_PCI_ACC_CNTL_SNOOP_WB | MV64360_PCI_ACC_CNTL_SWAP_NONE | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES; 
MV64360_PCI_ACC_CNTL_SNOOP_WB | MV64360_PCI_ACC_CNTL_SWAP_NONE | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); 
katana_setup_bridge(void){	struct pci_controller hose;	struct mv64x60_setup_info si;	void __iomem *vaddr;	int i;	u16 val;	u8 save_exclude;	/*	 * Some versions of the Katana firmware mistakenly change the vendor	 * & device id fields in the bridge's pci device (visible via pci	 * config accesses).  This breaks mv64x60_init() because those values	 * are used to identify the type of bridge that's there.  Artesyn	 * claims that the subsystem vendor/device id's will have the correct	 * Marvell values so this code puts back the correct values from there.	 */	memset(&hose, 0, sizeof(hose));	vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);	setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,		vaddr + MV64x60_PCI0_CONFIG_DATA);	save_exclude = mv64x60_pci_exclude_bridge;	mv64x60_pci_exclude_bridge = 0;	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);	if (val != PCI_VENDOR_ID_MARVELL) {		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),			PCI_SUBSYSTEM_VENDOR_ID, &val);		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),			PCI_VENDOR_ID, val);		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),			PCI_SUBSYSTEM_ID, &val);		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),			PCI_DEVICE_ID, val);	}	mv64x60_pci_exclude_bridge = save_exclude;	iounmap(vaddr);	memset(&si, 0, sizeof(si));	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;	si.pci_1.enable_bus = 1;	si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;	si.pci_1.pci_io.pci_base_hi = 0;	si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;	si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;	si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;	si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;	si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;	si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;	si.pci_1.pci_cmd_bits = 0;	si.pci_1.latency_timer = 0x80;	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {#if defined(CONFIG_NOT_COHERENT_CACHE)		si.cpu_prot_options[i] = 0;		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;		si.pci_1.acc_cntl_options[i] =		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |		    MV64360_PCI_ACC_CNTL_SWAP_NONE |		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;#else		si.cpu_prot_options[i] = 0;		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */		si.pci_1.acc_cntl_options[i] =		    MV64360_PCI_ACC_CNTL_SNOOP_WB |		    MV64360_PCI_ACC_CNTL_SWAP_NONE |		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;#endif	}	/* Lookup PCI host bridges */	if (mv64x60_init(&bh, &si))		printk(KERN_WARNING "Bridge initialization failed.\n");	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */	ppc_md.pci_swizzle = common_swizzle;	ppc_md.pci_map_irq = katana_map_irq;	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;	mv64x60_set_bus(&bh, 1, 0);	bh.hose_b->first_busno = 0;	bh.hose_b->last_busno = 0xff;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f4c6cc8d1e2305796f7fdad52d83b88cea4d2276/katana.c/buggy/arch/ppc/platforms/katana.c