 #ifdef CONFIG_NO_IDLE_HZ if (match_posponed) { match_posponed = 0; OSMR0 = initial_match; } #endif 
pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs){	int next_match;	write_seqlock(&xtime_lock);	/* Loop until we get ahead of the free running timer.	 * This ensures an exact clock tick count and time accuracy.	 * IRQs are disabled inside the loop to ensure coherence between	 * lost_ticks (updated in do_timer()) and the match reg value, so we	 * can use do_gettimeofday() from interrupt handlers.	 *	 * HACK ALERT: it seems that the PXA timer regs aren't updated right	 * away in all cases when a write occurs.  We therefore compare with	 * 8 instead of 0 in the while() condition below to avoid missing a	 * match if OSCR has already reached the next OSMR value.	 * Experience has shown that up to 6 ticks are needed to work around	 * this problem, but let's use 8 to be conservative.  Note that this	 * affect things only when the timer IRQ has been delayed by nearly	 * exactly one tick period which should be a pretty rare event.	 */	do {		timer_tick(regs);		OSSR = OSSR_M0;  /* Clear match on timer 0 */		next_match = (OSMR0 += LATCH);	} while( (signed long)(next_match - OSCR) <= 8 );	write_sequnlock(&xtime_lock);	return IRQ_HANDLED;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/5c53ff088cb76dca52bdf2ef36ea63147763f9ea/time.c/clean/arch/arm/mach-pxa/time.c