Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); 
Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz)); wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz)); 
static int setup_p4_watchdog(void){	unsigned int misc_enable, dummy;	rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);	if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))		return 0;	nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;	nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;#ifdef CONFIG_SMP	if (smp_num_siblings == 2)		nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;#endif	if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))		clear_msr_range(0x3F1, 2);	/* MSR 0x3F0 seems to have a default value of 0xFC00, but current	   docs doesn't fully define it, so leave it alone for now. */	if (boot_cpu_data.x86_model >= 0x3) {		/* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */		clear_msr_range(0x3A0, 26);		clear_msr_range(0x3BC, 3);	} else {		clear_msr_range(0x3A0, 31);	}	clear_msr_range(0x3C0, 6);	clear_msr_range(0x3C8, 6);	clear_msr_range(0x3E0, 2);	clear_msr_range(MSR_P4_CCCR0, 18);	clear_msr_range(MSR_P4_PERFCTR0, 18);	wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);	wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);	Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));	wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);	apic_write(APIC_LVTPC, APIC_DM_NMI);	wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);	return 1;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/42ac8ff2ce58138ba1339296406bde6636792bd8/nmi.c/clean/arch/x86_64/kernel/nmi.c