E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 
e1000_reset_hw(struct e1000_hw *hw){    uint32_t ctrl;    uint32_t ctrl_ext;    uint32_t icr;    uint32_t manc;    uint32_t led_ctrl;    DEBUGFUNC("e1000_reset_hw");    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */    if(hw->mac_type == e1000_82542_rev2_0) {        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");        e1000_pci_clear_mwi(hw);    }    /* Clear interrupt mask to stop board from generating interrupts */    DEBUGOUT("Masking off all interrupts\n");    E1000_WRITE_REG(hw, IMC, 0xffffffff);    /* Disable the Transmit and Receive units.  Then delay to allow     * any pending transactions to complete before we hit the MAC with     * the global reset.     */    E1000_WRITE_REG(hw, RCTL, 0);    E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);    E1000_WRITE_FLUSH(hw);    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */    hw->tbi_compatibility_on = FALSE;    /* Delay to allow any outstanding PCI transactions to complete before     * resetting the device     */    msec_delay(10);    ctrl = E1000_READ_REG(hw, CTRL);    /* Must reset the PHY before resetting the MAC */    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {        E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));        msec_delay(5);    }    /* Issue a global reset to the MAC.  This will reset the chip's     * transmit, receive, DMA, and link units.  It will not effect     * the current PCI configuration.  The global reset bit is self-     * clearing, and should clear within a microsecond.     */    DEBUGOUT("Issuing a global reset to MAC\n");    switch(hw->mac_type) {        case e1000_82544:        case e1000_82540:        case e1000_82545:        case e1000_82546:        case e1000_82541:        case e1000_82541_rev_2:            /* These controllers can't ack the 64-bit write when issuing the             * reset, so use IO-mapping as a workaround to issue the reset */            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));            break;        case e1000_82545_rev_3:        case e1000_82546_rev_3:            /* Reset is performed on a shadow of the control register */            E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));            break;        default:            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));            break;    }    /* After MAC reset, force reload of EEPROM to restore power-on settings to     * device.  Later controllers reload the EEPROM automatically, so just wait     * for reload to complete.     */    switch(hw->mac_type) {        case e1000_82542_rev2_0:        case e1000_82542_rev2_1:        case e1000_82543:        case e1000_82544:            /* Wait for reset to complete */            udelay(10);            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);            ctrl_ext |= E1000_CTRL_EXT_EE_RST;            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);            E1000_WRITE_FLUSH(hw);            /* Wait for EEPROM reload */            msec_delay(2);            break;        case e1000_82541:        case e1000_82541_rev_2:        case e1000_82547:        case e1000_82547_rev_2:            /* Wait for EEPROM reload */            msec_delay(20);            break;        default:            /* Wait for EEPROM reload (it happens automatically) */            msec_delay(5);            break;    }    /* Disable HW ARPs on ASF enabled adapters */    if(hw->mac_type >= e1000_82540) {        manc = E1000_READ_REG(hw, MANC);        manc &= ~(E1000_MANC_ARP_EN);        E1000_WRITE_REG(hw, MANC, manc);    }    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {        e1000_phy_init_script(hw);        /* Configure activity LED after PHY reset */        led_ctrl = E1000_READ_REG(hw, LEDCTL);        led_ctrl &= IGP_ACTIVITY_LED_MASK;        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);    }    /* Clear interrupt mask to stop board from generating interrupts */    DEBUGOUT("Masking off all interrupts\n");    E1000_WRITE_REG(hw, IMC, 0xffffffff);    /* Clear any pending interrupt events. */    icr = E1000_READ_REG(hw, ICR);    /* If MWI was previously enabled, reenable it. */    if(hw->mac_type == e1000_82542_rev2_0) {        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)            e1000_pci_set_mwi(hw);    }    return E1000_SUCCESS;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/2d7edb923a823660b081bd4c660300ee19adca8d/e1000_hw.c/clean/drivers/net/e1000/e1000_hw.c