pte_t *pte; 
m8xx_cpm_reset(uint bootpage){	volatile immap_t	 *imp;	volatile cpm8xx_t	*commproc;	pte_t *pte;	imp = (immap_t *)IMAP_ADDR;	commproc = (cpm8xx_t *)&imp->im_cpm;#ifdef CONFIG_UCODE_PATCH	/* Perform a reset.	*/	commproc->cp_cpcr = (CPM_CR_RST | CPM_CR_FLG);	/* Wait for it.	*/	while (commproc->cp_cpcr & CPM_CR_FLG);	cpm_load_patch(imp);#endif	/* Set SDMA Bus Request priority 5.	 * On 860T, this also enables FEC priority 6.  I am not sure	 * this is what we realy want for some applications, but the	 * manual recommends it.	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).	 */	imp->im_siu_conf.sc_sdcr = 1;	/* Reclaim the DP memory for our use. */	m8xx_cpm_dpinit();	/* get the PTE for the bootpage */	if (!get_pteptr(&init_mm, bootpage, &pte))	       panic("get_pteptr failed\n");																								/* and make it uncachable */	pte_val(*pte) |= _PAGE_NO_CACHE;	_tlbie(bootpage);	host_buffer = bootpage;	host_end = host_buffer + PAGE_SIZE;	/* Tell everyone where the comm processor resides.	*/	cpmp = (cpm8xx_t *)commproc;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/079da354db3473b56eb938ca53a2cb0804ea9c8c/commproc.c/clean/arch/ppc/8xx_io/commproc.c