int bus_status = inl(ioaddr + PktStatus); 
int bus_status = ioread32(ioaddr + PktStatus); 
vortex_error(struct net_device *dev, int status){	struct vortex_private *vp = netdev_priv(dev);	long ioaddr = dev->base_addr;	int do_tx_reset = 0, reset_mask = 0;	unsigned char tx_status = 0;	if (vortex_debug > 2) {		printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);	}	if (status & TxComplete) {			/* Really "TxError" for us. */		tx_status = inb(ioaddr + TxStatus);		/* Presumably a tx-timeout. We must merely re-enable. */		if (vortex_debug > 2			|| (tx_status != 0x88 && vortex_debug > 0)) {			printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",				   dev->name, tx_status);			if (tx_status == 0x82) {				printk(KERN_ERR "Probably a duplex mismatch.  See "						"Documentation/networking/vortex.txt\n");			}			dump_tx_ring(dev);		}		if (tx_status & 0x14)  vp->stats.tx_fifo_errors++;		if (tx_status & 0x38)  vp->stats.tx_aborted_errors++;		outb(0, ioaddr + TxStatus);		if (tx_status & 0x30) {			/* txJabber or txUnderrun */			do_tx_reset = 1;		} else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) {	/* maxCollisions */			do_tx_reset = 1;			reset_mask = 0x0108;		/* Reset interface logic, but not download logic */		} else {						/* Merely re-enable the transmitter. */			outw(TxEnable, ioaddr + EL3_CMD);		}	}	if (status & RxEarly) {				/* Rx early is unused. */		vortex_rx(dev);		outw(AckIntr | RxEarly, ioaddr + EL3_CMD);	}	if (status & StatsFull) {			/* Empty statistics. */		static int DoneDidThat;		if (vortex_debug > 4)			printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);		update_stats(ioaddr, dev);		/* HACK: Disable statistics as an interrupt source. */		/* This occurs when we have the wrong media type! */		if (DoneDidThat == 0  &&			inw(ioaddr + EL3_STATUS) & StatsFull) {			printk(KERN_WARNING "%s: Updating statistics failed, disabling "				   "stats as an interrupt source.\n", dev->name);			EL3WINDOW(5);			outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);			vp->intr_enable &= ~StatsFull;			EL3WINDOW(7);			DoneDidThat++;		}	}	if (status & IntReq) {		/* Restore all interrupt sources.  */		outw(vp->status_enable, ioaddr + EL3_CMD);		outw(vp->intr_enable, ioaddr + EL3_CMD);	}	if (status & HostError) {		u16 fifo_diag;		EL3WINDOW(4);		fifo_diag = inw(ioaddr + Wn4_FIFODiag);		printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",			   dev->name, fifo_diag);		/* Adapter failure requires Tx/Rx reset and reinit. */		if (vp->full_bus_master_tx) {			int bus_status = inl(ioaddr + PktStatus);			/* 0x80000000 PCI master abort. */			/* 0x40000000 PCI target abort. */			if (vortex_debug)				printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);			/* In this case, blow the card away */			/* Must not enter D3 or we can't legally issue the reset! */			vortex_down(dev, 0);			issue_and_wait(dev, TotalReset | 0xff);			vortex_up(dev);		/* AKPM: bug.  vortex_up() assumes that the rx ring is full. It may not be. */		} else if (fifo_diag & 0x0400)			do_tx_reset = 1;		if (fifo_diag & 0x3000) {			/* Reset Rx fifo and upload logic */			issue_and_wait(dev, RxReset|0x07);			/* Set the Rx filter to the current state. */			set_rx_mode(dev);			/* enable 802.1q VLAN tagged frames */			set_8021q_mode(dev, 1);			outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */			outw(AckIntr | HostError, ioaddr + EL3_CMD);		}	}	if (do_tx_reset) {		issue_and_wait(dev, TxReset|reset_mask);		outw(TxEnable, ioaddr + EL3_CMD);		if (!vp->full_bus_master_tx)			netif_wake_queue(dev);	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/62afe595de7aaac6c140103a34dc8c208afa34e7/3c59x.c/buggy/drivers/net/3c59x.c