void __init mpic_init(struct mpic *mpic){	int i;	BUG_ON(mpic->num_sources == 0);	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);	/* Set current processor priority to max */	mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf);	/* Initialize timers: just disable them all */	for (i = 0; i < 4; i++) {		mpic_write(mpic->tmregs,			   i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0);		mpic_write(mpic->tmregs,			   i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI,			   MPIC_VECPRI_MASK |			   (MPIC_VEC_TIMER_0 + i));	}	/* Initialize IPIs to our reserved vectors and mark them disabled for now */	mpic_test_broken_ipi(mpic);	for (i = 0; i < 4; i++) {		mpic_ipi_write(i,			       MPIC_VECPRI_MASK |			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |			       (MPIC_VEC_IPI_0 + i));#ifdef CONFIG_SMP		if (!(mpic->flags & MPIC_PRIMARY))			continue;		irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU;		irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi;		#endif /* CONFIG_SMP */	}	/* Initialize interrupt sources */	if (mpic->irq_count == 0)		mpic->irq_count = mpic->num_sources;#ifdef CONFIG_MPIC_BROKEN_U3	/* Do the ioapic fixups on U3 broken mpic */	DBG("MPIC flags: %x\n", mpic->flags);	if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))		mpic_scan_ioapics(mpic);#endif /* CONFIG_MPIC_BROKEN_U3 */	for (i = 0; i < mpic->num_sources; i++) {		/* start with vector = source number, and masked */		u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT);		int level = 0;				/* if it's an IPI, we skip it */		if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) &&		    (mpic->irq_offset + i) <  (mpic->ipi_offset + i + 4))			continue;		/* do senses munging */		if (mpic->senses && i < mpic->senses_count) {			if (mpic->senses[i] & IRQ_SENSE_LEVEL)				vecpri |= MPIC_VECPRI_SENSE_LEVEL;			if (mpic->senses[i] & IRQ_POLARITY_POSITIVE)				vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;		} else			vecpri |= MPIC_VECPRI_SENSE_LEVEL;		/* remember if it was a level interrupts */		level = (vecpri & MPIC_VECPRI_SENSE_LEVEL);		/* deal with broken U3 */		if (mpic->flags & MPIC_BROKEN_U3) {#ifdef CONFIG_MPIC_BROKEN_U3			if (mpic_is_ht_interrupt(mpic, i)) {				vecpri &= ~(MPIC_VECPRI_SENSE_MASK |					    MPIC_VECPRI_POLARITY_MASK);				vecpri |= MPIC_VECPRI_POLARITY_POSITIVE;			}#else			printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n");#endif		}		DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri,		    (level != 0));		/* init hw */		mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri);		mpic_irq_write(i, MPIC_IRQ_DESTINATION,			       1 << hard_smp_processor_id());		/* init linux descriptors */		if (i < mpic->irq_count) {			irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0;			irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq;		}	}		/* Init spurrious vector */	mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS);	/* Disable 8259 passthrough */	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,		   mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)		   | MPIC_GREG_GCONF_8259_PTHROU_DIS);	/* Set current processor priority to 0 */	mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/bd561c79dce9036c9efb17420b6cf8763c8c9de3/mpic.c/buggy/arch/powerpc/sysdev/mpic.c