printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n", pci_name(pdev)); 
dev_printk(KERN_ERR, &pdev->dev, "32-bit DMA enable failed\n"); 
static int ahci_host_init(struct ata_probe_ent *probe_ent){	struct ahci_host_priv *hpriv = probe_ent->private_data;	struct pci_dev *pdev = to_pci_dev(probe_ent->dev);	void __iomem *mmio = probe_ent->mmio_base;	u32 tmp, cap_save;	u16 tmp16;	unsigned int i, j, using_dac;	int rc;	void __iomem *port_mmio;	cap_save = readl(mmio + HOST_CAP);	cap_save &= ( (1<<28) | (1<<17) );	cap_save |= (1 << 27);	/* global controller reset */	tmp = readl(mmio + HOST_CTL);	if ((tmp & HOST_RESET) == 0) {		writel(tmp | HOST_RESET, mmio + HOST_CTL);		readl(mmio + HOST_CTL); /* flush */	}	/* reset must complete within 1 second, or	 * the hardware should be considered fried.	 */	ssleep(1);	tmp = readl(mmio + HOST_CTL);	if (tmp & HOST_RESET) {		printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",			pci_name(pdev), tmp);		return -EIO;	}	writel(HOST_AHCI_EN, mmio + HOST_CTL);	(void) readl(mmio + HOST_CTL);	/* flush */	writel(cap_save, mmio + HOST_CAP);	writel(0xf, mmio + HOST_PORTS_IMPL);	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */	pci_read_config_word(pdev, 0x92, &tmp16);	tmp16 |= 0xf;	pci_write_config_word(pdev, 0x92, tmp16);	hpriv->cap = readl(mmio + HOST_CAP);	hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);	probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;	VPRINTK("cap 0x%x  port_map 0x%x  n_ports %d\n",		hpriv->cap, hpriv->port_map, probe_ent->n_ports);	using_dac = hpriv->cap & HOST_CAP_64;	if (using_dac &&	    !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {		rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);		if (rc) {			rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);			if (rc) {				printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",					pci_name(pdev));				return rc;			}		}	} else {		rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);		if (rc) {			printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",				pci_name(pdev));			return rc;		}		rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);		if (rc) {			printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",				pci_name(pdev));			return rc;		}	}	for (i = 0; i < probe_ent->n_ports; i++) {#if 0 /* BIOSen initialize this incorrectly */		if (!(hpriv->port_map & (1 << i)))			continue;#endif		port_mmio = ahci_port_base(mmio, i);		VPRINTK("mmio %p  port_mmio %p\n", mmio, port_mmio);		ahci_setup_port(&probe_ent->port[i],				(unsigned long) mmio, i);		/* make sure port is not active */		tmp = readl(port_mmio + PORT_CMD);		VPRINTK("PORT_CMD 0x%x\n", tmp);		if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |			   PORT_CMD_FIS_RX | PORT_CMD_START)) {			tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |				 PORT_CMD_FIS_RX | PORT_CMD_START);			writel(tmp, port_mmio + PORT_CMD);			readl(port_mmio + PORT_CMD); /* flush */			/* spec says 500 msecs for each bit, so			 * this is slightly incorrect.			 */			msleep(500);		}		writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);		j = 0;		while (j < 100) {			msleep(10);			tmp = readl(port_mmio + PORT_SCR_STAT);			if ((tmp & 0xf) == 0x3)				break;			j++;		}		tmp = readl(port_mmio + PORT_SCR_ERR);		VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);		writel(tmp, port_mmio + PORT_SCR_ERR);		/* ack any pending irq events for this port */		tmp = readl(port_mmio + PORT_IRQ_STAT);		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);		if (tmp)			writel(tmp, port_mmio + PORT_IRQ_STAT);		writel(1 << i, mmio + HOST_IRQ_STAT);		/* set irq mask (enables interrupts) */		writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);	}	tmp = readl(mmio + HOST_CTL);	VPRINTK("HOST_CTL 0x%x\n", tmp);	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);	tmp = readl(mmio + HOST_CTL);	VPRINTK("HOST_CTL 0x%x\n", tmp);	pci_set_master(pdev);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/a9524a76f70f3343e4be27f95a7e92a8ba5f9009/ahci.c/clean/drivers/scsi/ahci.c