c->options &= MIPS_CPU_4K_CACHE; 
c->options &= ~MIPS_CPU_4K_CACHE; 
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c){	decode_configs(c);	/*	 * For historical reasons the SB1 comes with it's own variant of	 * cache code which eventually will be folded into c-r4k.c.  Until	 * then we pretend it's got it's own cache architecture.	 */	c->options &= MIPS_CPU_4K_CACHE;	c->options |= MIPS_CPU_SB1_CACHE;	switch (c->processor_id & 0xff00) {	case PRID_IMP_SB1:		c->cputype = CPU_SB1;#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* FPU in pass1 is known to have issues. */		c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);#endif		break;	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/d121ced21d79eab7726bfe6b1e33da4ae86072c0/cpu-probe.c/clean/arch/mips/kernel/cpu-probe.c