void falc_init_e1(pc300_t * card, int ch) 
static void falc_init_e1(pc300_t * card, int ch) 
void falc_init_e1(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	void __iomem *falcbase = card->hw.falcbase;	ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);	/* Switch to E1 mode (PCM 30) */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);	/* Clock mode */	if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);	} else { /* Slave mode */		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);	}	cpc_writeb(falcbase + F_REG(LOOP, ch),		   cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);	cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);	cpc_writeb(falcbase + F_REG(FMR0, ch),		   cpc_readb(falcbase + F_REG(FMR0, ch)) &		   ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));	switch (conf->lcode) {		case PC300_LC_AMI:			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) |				   FMR0_XC1 | FMR0_RC1);			break;		case PC300_LC_HDB3:			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) |				   FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);			break;		case PC300_LC_NRZ:			break;	}	cpc_writeb(falcbase + F_REG(LIM0, ch),		   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));	/* Set interface mode to 2 MBPS */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);	cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);	cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);	cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);	switch (conf->fr_mode) {		case PC300_FR_MF_CRC4:			pfalc->multiframe_mode = 1;			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);			cpc_writeb(falcbase + F_REG(FMR3, ch),				   cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);			/* MultiFrame Resynchronization */			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);			/* Automatic Loss of Multiframe > 914 CRC errors */			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);			/* S1 and SI1/SI2 spare Bits set to 1 */			cpc_writeb(falcbase + F_REG(XSP, ch),				   cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);			cpc_writeb(falcbase + F_REG(XSP, ch),				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);			cpc_writeb(falcbase + F_REG(XSP, ch),				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);			/* Automatic Force Resynchronization */			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);			/* Transmit Automatic Remote Alarm */			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);			/* Transmit Spare Bits for National Use (Y, Sn, Sa) */			cpc_writeb(falcbase + F_REG(XSW, ch),				   cpc_readb(falcbase + F_REG(XSW, ch)) |				   XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);			break;		case PC300_FR_MF_NON_CRC4:		case PC300_FR_D4:			pfalc->multiframe_mode = 0;			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) & 				   ~(FMR2_RFS1 | FMR2_RFS0));			cpc_writeb(falcbase + F_REG(XSW, ch),				   cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);			cpc_writeb(falcbase + F_REG(XSP, ch),				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);			/* Automatic Force Resynchronization */			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);			/* Transmit Automatic Remote Alarm */			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);			/* Transmit Spare Bits for National Use (Y, Sn, Sa) */			cpc_writeb(falcbase + F_REG(XSW, ch),				   cpc_readb(falcbase + F_REG(XSW, ch)) |				   XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);			break;		case PC300_FR_UNFRAMED:			pfalc->multiframe_mode = 0;			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) & 				   ~(FMR2_RFS1 | FMR2_RFS0));			cpc_writeb(falcbase + F_REG(XSP, ch),				   cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);			cpc_writeb(falcbase + F_REG(XSW, ch),				   cpc_readb(falcbase + F_REG(XSW, ch)) & 				   ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));			cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) |				   (FMR2_RTM | FMR2_DAIS));			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);			pfalc->sync = 1;			cpc_writeb(falcbase + card->hw.cpld_reg2,				   cpc_readb(falcbase + card->hw.cpld_reg2) |				   (CPLD_REG2_FALC_LED2 << (2 * ch)));			break;	}	/* No signaling */	cpc_writeb(falcbase + F_REG(XSP, ch),		   cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);	cpc_writeb(falcbase + F_REG(CCR1, ch), 0);	cpc_writeb(falcbase + F_REG(LIM1, ch),		   cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);	cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));	/* Transmit Clock-Slot Offset */	cpc_writeb(falcbase + F_REG(XC0, ch),		   cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);	/* Transmit Time-slot Offset */	cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);	/* Receive  Clock-Slot offset */	cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);	/* Receive  Time-slot offset */	cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);	/* LOS Detection after 176 consecutive 0s */	cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);	/* LOS Recovery after 22 ones in the time window of PCD */	cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);	cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);	falc_close_all_timeslots(card, ch);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7665a08928f241247afe8c76865cdbe4ef5489bf/pc300_drv.c/buggy/drivers/net/wan/pc300_drv.c