ring_start = dev_priv->cce_ring->offset - dev->sg->handle; 
ring_start = dev_priv->cce_ring->offset - (unsigned long)dev->sg->virtual; 
static void r128_cce_init_ring_buffer( drm_device_t *dev,				       drm_r128_private_t *dev_priv ){	u32 ring_start;	u32 tmp;	DRM_DEBUG( "\n" );	/* The manual (p. 2) says this address is in "VM space".  This	 * means it's an offset from the start of AGP space.	 */#if __OS_HAS_AGP	if ( !dev_priv->is_pci )		ring_start = dev_priv->cce_ring->offset - dev->agp->base;	else#endif		ring_start = dev_priv->cce_ring->offset - dev->sg->handle;	R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );	/* Set watermark control */	R128_WRITE( R128_PM4_BUFFER_WM_CNTL,		    ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)		    | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)		    | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)		    | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );	/* Force read.  Why?  Because it's in the examples... */	R128_READ( R128_PM4_BUFFER_ADDR );	/* Turn on bus mastering */	tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;	R128_WRITE( R128_BUS_CNTL, tmp );}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/d1f2b55ad2c11f46e30547a9f7754e99b478348e/r128_cce.c/buggy/drivers/char/drm/r128_cce.c