pci_write_config_byte(dev, PCI_ROM_ADDRESS, 
pci_write_config_dword(dev, PCI_ROM_ADDRESS, 
static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name){	int i = 0;	unsigned long hpt34xIoBase = pci_resource_start(dev, 4);	unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };	unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };	u16 cmd;	unsigned long flags;	local_irq_save(flags);	pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);	pci_read_config_word(dev, PCI_COMMAND, &cmd);	if (cmd & PCI_COMMAND_MEMORY) {		if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {			pci_write_config_byte(dev, PCI_ROM_ADDRESS,				dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);			printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",				dev->resource[PCI_ROM_RESOURCE].start);		}		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);	} else {		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);	}	/*	 * Since 20-23 can be assigned and are R/W, we correct them.	 */	pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);	for(i=0; i<4; i++) {		dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);		dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];		dev->resource[i].flags = IORESOURCE_IO;		pci_write_config_dword(dev,				(PCI_BASE_ADDRESS_0 + (i * 4)),				dev->resource[i].start);	}	pci_write_config_word(dev, PCI_COMMAND, cmd);	local_irq_restore(flags);	return dev->irq;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/299cc3c166f7a11f6cc3b66aafbaf75c2aa0e0e2/hpt34x.c/buggy/drivers/ide/pci/hpt34x.c