if (ieee754_csr.nod) ctx->fcr31 |= 0x1000000; 
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,	mips_instruction ir){	unsigned rcsr = 0;	/* resulting csr */	fpuemuprivate.stats.cp1xops++;	switch (MIPSInst_FMA_FFMT(ir)) {	case s_fmt:{		/* 0 */		ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);		ieee754sp fd, fr, fs, ft;		u32 *va;		u32 val;		switch (MIPSInst_FUNC(ir)) {		case lwxc1_op:			va = (void *) (xcp->regs[MIPSInst_FR(ir)] +				xcp->regs[MIPSInst_FT(ir)]);			fpuemuprivate.stats.loads++;			if (get_user(val, va)) {				fpuemuprivate.stats.errors++;				return SIGBUS;			}#ifdef SINGLE_ONLY_FPU			if (MIPSInst_FD(ir) & 1) {				/* illegal register in single-float				 * mode				 */				return SIGILL;			}#endif			SITOREG(val, MIPSInst_FD(ir));			break;		case swxc1_op:			va = (void *) (xcp->regs[MIPSInst_FR(ir)] +				xcp->regs[MIPSInst_FT(ir)]);			fpuemuprivate.stats.stores++;#ifdef SINGLE_ONLY_FPU			if (MIPSInst_FS(ir) & 1) {				/* illegal register in single-float				 * mode				 */				return SIGILL;			}#endif			SIFROMREG(val, MIPSInst_FS(ir));			if (put_user(val, va)) {				fpuemuprivate.stats.errors++;				return SIGBUS;			}			break;		case madd_s_op:			handler = fpemu_sp_madd;			goto scoptop;		case msub_s_op:			handler = fpemu_sp_msub;			goto scoptop;		case nmadd_s_op:			handler = fpemu_sp_nmadd;			goto scoptop;		case nmsub_s_op:			handler = fpemu_sp_nmsub;			goto scoptop;		      scoptop:			SPFROMREG(fr, MIPSInst_FR(ir));			SPFROMREG(fs, MIPSInst_FS(ir));			SPFROMREG(ft, MIPSInst_FT(ir));			fd = (*handler) (fr, fs, ft);			SPTOREG(fd, MIPSInst_FD(ir));		      copcsr:			if (ieee754_cxtest(IEEE754_INEXACT))				rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;			if (ieee754_cxtest(IEEE754_UNDERFLOW))				rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;			if (ieee754_cxtest(IEEE754_OVERFLOW))				rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;			if (ieee754_cxtest(IEEE754_INVALID_OPERATION))				rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;			ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;			if (ieee754_csr.nod)				ctx->fcr31 |= 0x1000000;			if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {				/*printk ("SIGFPE: fpu csr = %08x\n",				   ctx->fcr31); */				return SIGFPE;			}			break;		default:			return SIGILL;		}		break;	}#ifndef SINGLE_ONLY_FPU	case d_fmt:{		/* 1 */		ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);		ieee754dp fd, fr, fs, ft;		u64 *va;		u64 val;		switch (MIPSInst_FUNC(ir)) {		case ldxc1_op:			va = (void *) (xcp->regs[MIPSInst_FR(ir)] +				xcp->regs[MIPSInst_FT(ir)]);			fpuemuprivate.stats.loads++;			if (get_user(val, va)) {				fpuemuprivate.stats.errors++;				return SIGBUS;			}			DITOREG(val, MIPSInst_FD(ir));			break;		case sdxc1_op:			va = (void *) (xcp->regs[MIPSInst_FR(ir)] +				xcp->regs[MIPSInst_FT(ir)]);			fpuemuprivate.stats.stores++;			DIFROMREG(val, MIPSInst_FS(ir));			if (put_user(val, va)) {				fpuemuprivate.stats.errors++;				return SIGBUS;			}			break;		case madd_d_op:			handler = fpemu_dp_madd;			goto dcoptop;		case msub_d_op:			handler = fpemu_dp_msub;			goto dcoptop;		case nmadd_d_op:			handler = fpemu_dp_nmadd;			goto dcoptop;		case nmsub_d_op:			handler = fpemu_dp_nmsub;			goto dcoptop;		      dcoptop:			DPFROMREG(fr, MIPSInst_FR(ir));			DPFROMREG(fs, MIPSInst_FS(ir));			DPFROMREG(ft, MIPSInst_FT(ir));			fd = (*handler) (fr, fs, ft);			DPTOREG(fd, MIPSInst_FD(ir));			goto copcsr;		default:			return SIGILL;		}		break;	}#endif	case 0x7:		/* 7 */		if (MIPSInst_FUNC(ir) != pfetch_op) {			return SIGILL;		}		/* ignore prefx operation */		break;	default:		return SIGILL;	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/cd21dfcfbb5c43de54f6be795dde07397da2bc2f/cp1emu.c/buggy/arch/mips/math-emu/cp1emu.c