dev_lim->mtt_seg_sz = size; 
int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,			struct mthca_dev_lim *dev_lim, u8 *status){	u32 *outbox;	dma_addr_t outdma;	u8 field;	u16 size;	int err;#define QUERY_DEV_LIM_OUT_SIZE             0x100#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET     0x10#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET      0x11#define QUERY_DEV_LIM_RSVD_QP_OFFSET        0x12#define QUERY_DEV_LIM_MAX_QP_OFFSET         0x13#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET       0x14#define QUERY_DEV_LIM_MAX_SRQ_OFFSET        0x15#define QUERY_DEV_LIM_RSVD_EEC_OFFSET       0x16#define QUERY_DEV_LIM_MAX_EEC_OFFSET        0x17#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET      0x19#define QUERY_DEV_LIM_RSVD_CQ_OFFSET        0x1a#define QUERY_DEV_LIM_MAX_CQ_OFFSET         0x1b#define QUERY_DEV_LIM_MAX_MPT_OFFSET        0x1d#define QUERY_DEV_LIM_RSVD_EQ_OFFSET        0x1e#define QUERY_DEV_LIM_MAX_EQ_OFFSET         0x1f#define QUERY_DEV_LIM_RSVD_MTT_OFFSET       0x20#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET     0x21#define QUERY_DEV_LIM_RSVD_MRW_OFFSET       0x22#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET    0x23#define QUERY_DEV_LIM_MAX_AV_OFFSET         0x27#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET     0x29#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET     0x2b#define QUERY_DEV_LIM_MAX_RDMA_OFFSET       0x2f#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET        0x33#define QUERY_DEV_LIM_ACK_DELAY_OFFSET      0x35#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET      0x36#define QUERY_DEV_LIM_VL_PORT_OFFSET        0x37#define QUERY_DEV_LIM_MAX_GID_OFFSET        0x3b#define QUERY_DEV_LIM_MAX_PKEY_OFFSET       0x3f#define QUERY_DEV_LIM_FLAGS_OFFSET          0x44#define QUERY_DEV_LIM_RSVD_UAR_OFFSET       0x48#define QUERY_DEV_LIM_UAR_SZ_OFFSET         0x49#define QUERY_DEV_LIM_PAGE_SZ_OFFSET        0x4b#define QUERY_DEV_LIM_MAX_SG_OFFSET         0x51#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET    0x52#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET      0x55#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET     0x61#define QUERY_DEV_LIM_RSVD_MCG_OFFSET       0x62#define QUERY_DEV_LIM_MAX_MCG_OFFSET        0x63#define QUERY_DEV_LIM_RSVD_PD_OFFSET        0x64#define QUERY_DEV_LIM_MAX_PD_OFFSET         0x65#define QUERY_DEV_LIM_RSVD_RDD_OFFSET       0x66#define QUERY_DEV_LIM_MAX_RDD_OFFSET        0x67#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET   0x80#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET   0x82#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET  0x84#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET  0x86#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET   0x88#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET   0x8a#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET   0x8c#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET   0x8e#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET   0x90#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET   0x92#define QUERY_DEV_LIM_PBL_SZ_OFFSET         0x96#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET     0x97#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET      0x98#define QUERY_DEV_LIM_LAMR_OFFSET           0x9f#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET     0xa0	outbox = pci_alloc_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, &outdma);	if (!outbox)		return -ENOMEM;	err = mthca_cmd_box(dev, 0, outdma, 0, 0, CMD_QUERY_DEV_LIM,			    CMD_TIME_CLASS_A, status);	if (err)		goto out;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);	dev_lim->max_srq_sz = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);	dev_lim->max_qp_sz = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);	dev_lim->reserved_qps = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);	dev_lim->max_qps = 1 << (field & 0x1f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);	dev_lim->reserved_srqs = 1 << (field >> 4);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);	dev_lim->max_srqs = 1 << (field & 0x1f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);	dev_lim->reserved_eecs = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);	dev_lim->max_eecs = 1 << (field & 0x1f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);	dev_lim->max_cq_sz = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);	dev_lim->reserved_cqs = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);	dev_lim->max_cqs = 1 << (field & 0x1f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);	dev_lim->max_mpts = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);	dev_lim->reserved_eqs = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);	dev_lim->max_eqs = 1 << (field & 0x7);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);	dev_lim->reserved_mtts = 1 << (field >> 4);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);	dev_lim->max_mrw_sz = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);	dev_lim->reserved_mrws = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);	dev_lim->max_mtt_seg = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);	dev_lim->max_requester_per_qp = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);	dev_lim->max_responder_per_qp = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);	dev_lim->max_rdma_global = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);	dev_lim->local_ca_ack_delay = field & 0x1f;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);	dev_lim->max_mtu        = field >> 4;	dev_lim->max_port_width = field & 0xf;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);	dev_lim->max_vl    = field >> 4;	dev_lim->num_ports = field & 0xf;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);	dev_lim->max_gids = 1 << (field & 0xf);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);	dev_lim->max_pkeys = 1 << (field & 0xf);	MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);	dev_lim->reserved_uars = field >> 4;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);	dev_lim->uar_size = 1 << ((field & 0x3f) + 20);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);	dev_lim->min_page_sz = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);	dev_lim->max_sg = field;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);	dev_lim->max_desc_sz = size;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);	dev_lim->max_qp_per_mcg = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);	dev_lim->reserved_mgms = field & 0xf;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);	dev_lim->max_mcgs = 1 << field;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);	dev_lim->reserved_pds = field >> 4;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);	dev_lim->max_pds = 1 << (field & 0x3f);	MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);	dev_lim->reserved_rdds = field >> 4;	MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);	dev_lim->max_rdds = 1 << (field & 0x3f);	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);	dev_lim->eec_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);	dev_lim->qpc_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);	dev_lim->eeec_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);	dev_lim->eqpc_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);	dev_lim->eqc_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);	dev_lim->cqc_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);	dev_lim->srq_entry_sz = size;	MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);	dev_lim->uar_scratch_entry_sz = size;	mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",		  dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);	mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",		  dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);	mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",		  dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);	mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",		  dev_lim->reserved_mrws, dev_lim->reserved_mtts);	mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",		  dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);	mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",		  dev_lim->max_pds, dev_lim->reserved_mgms);	mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);	if (dev->hca_type == ARBEL_NATIVE) {		MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);		dev_lim->hca.arbel.resize_srq = field & 1;		MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);		dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);		MTHCA_GET(size, outbox, QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET);		dev_lim->mtt_seg_sz = size;		MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);		dev_lim->mpt_entry_sz = size;		MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);		dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);		MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,			  QUERY_DEV_LIM_BMME_FLAGS_OFFSET);		MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,			  QUERY_DEV_LIM_RSVD_LKEY_OFFSET);		MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);		dev_lim->hca.arbel.lam_required = field & 1;		MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,			  QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);		if (dev_lim->hca.arbel.bmme_flags & 1)			mthca_dbg(dev, "Base MM extensions: yes "				  "(flags %d, max PBL %d, rsvd L_Key %08x)\n",				  dev_lim->hca.arbel.bmme_flags,				  dev_lim->hca.arbel.max_pbl_sz,				  dev_lim->hca.arbel.reserved_lkey);		else			mthca_dbg(dev, "Base MM extensions: no\n");		mthca_dbg(dev, "Max ICM size %lld MB\n",			  (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);	} else {		MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);		dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);		dev_lim->mtt_seg_sz   = MTHCA_MTT_SEG_SIZE;		dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;	}out:	pci_free_consistent(dev->pdev, QUERY_DEV_LIM_OUT_SIZE, outbox, outdma);	return err;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/44ea66879d5638cfed5b5ecf628badfd8ec26f36/mthca_cmd.c/buggy/drivers/infiniband/hw/mthca/mthca_cmd.c