if (np->queue_mem == 0) 
if (np->queue_mem == NULL) { free_irq(dev->irq, dev); 
static int netdev_open(struct net_device *dev){	struct netdev_private *np = netdev_priv(dev);	void __iomem *ioaddr = np->base;	int i, retval;	size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;	/* Do we ever need to reset the chip??? */	retval = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);	if (retval)		return retval;	/* Disable the Rx and Tx, and reset the chip. */	writel(0, ioaddr + GenCtrl);	writel(1, ioaddr + PCIDeviceConfig);	if (debug > 1)		printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",		       dev->name, dev->irq);	/* Allocate the various queues. */	if (np->queue_mem == 0) {		tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;		rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;		tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;		rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;		np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;		np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);		if (np->queue_mem == 0)			return -ENOMEM;		np->tx_done_q     = np->queue_mem;		np->tx_done_q_dma = np->queue_mem_dma;		np->rx_done_q     = (void *) np->tx_done_q + tx_done_q_size;		np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;		np->tx_ring       = (void *) np->rx_done_q + rx_done_q_size;		np->tx_ring_dma   = np->rx_done_q_dma + rx_done_q_size;		np->rx_ring       = (void *) np->tx_ring + tx_ring_size;		np->rx_ring_dma   = np->tx_ring_dma + tx_ring_size;	}	/* Start with no carrier, it gets adjusted later */	netif_carrier_off(dev);	init_ring(dev);	/* Set the size of the Rx buffers. */	writel((np->rx_buf_sz << RxBufferLenShift) |	       (0 << RxMinDescrThreshShift) |	       RxPrefetchMode | RxVariableQ |	       RX_Q_ENTRIES |	       RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |	       RxDescSpace4,	       ioaddr + RxDescQCtrl);	/* Set up the Rx DMA controller. */	writel(RxChecksumIgnore |	       (0 << RxEarlyIntThreshShift) |	       (6 << RxHighPrioThreshShift) |	       ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),	       ioaddr + RxDMACtrl);	/* Set Tx descriptor */	writel((2 << TxHiPriFIFOThreshShift) |	       (0 << TxPadLenShift) |	       ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |	       TX_DESC_Q_ADDR_SIZE |	       TX_DESC_SPACING | TX_DESC_TYPE,	       ioaddr + TxDescCtrl);	writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);	writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);	writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);	writel(np->rx_ring_dma, ioaddr + RxDescQAddr);	writel(np->tx_ring_dma, ioaddr + TxRingPtr);	writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);	writel(np->rx_done_q_dma |	       RxComplType |	       (0 << RxComplThreshShift),	       ioaddr + RxCompletionAddr);	if (debug > 1)		printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);	/* Fill both the Tx SA register and the Rx perfect filter. */	for (i = 0; i < 6; i++)		writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);	/* The first entry is special because it bypasses the VLAN filter.	   Don't use it. */	writew(0, ioaddr + PerfFilterTable);	writew(0, ioaddr + PerfFilterTable + 4);	writew(0, ioaddr + PerfFilterTable + 8);	for (i = 1; i < 16; i++) {		u16 *eaddrs = (u16 *)dev->dev_addr;		void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;		writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4;		writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4;		writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8;	}	/* Initialize other registers. */	/* Configure the PCI bus bursts and FIFO thresholds. */	np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable;	/* modified when link is up. */	writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);	udelay(1000);	writel(np->tx_mode, ioaddr + TxMode);	np->tx_threshold = 4;	writel(np->tx_threshold, ioaddr + TxThreshold);	writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);	netif_start_queue(dev);	if (debug > 1)		printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);	set_rx_mode(dev);	np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);	check_duplex(dev);	/* Enable GPIO interrupts on link change */	writel(0x0f00ff00, ioaddr + GPIOCtrl);	/* Set the interrupt mask */	writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |	       IntrTxDMADone | IntrStatsMax | IntrLinkChange |	       IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,	       ioaddr + IntrEnable);	/* Enable PCI interrupts. */	writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),	       ioaddr + PCIDeviceConfig);#ifdef VLAN_SUPPORT	/* Set VLAN type to 802.1q */	writel(ETH_P_8021Q, ioaddr + VlanType);#endif /* VLAN_SUPPORT */	/* Load Rx/Tx firmware into the frame processors */	for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)		writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);	for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)		writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);	if (enable_hw_cksum)		/* Enable the Rx and Tx units, and the Rx/Tx frame processors. */		writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);	else		/* Enable the Rx and Tx units only. */		writel(TxEnable|RxEnable, ioaddr + GenCtrl);	if (debug > 1)		printk(KERN_DEBUG "%s: Done netdev_open().\n",		       dev->name);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d8840ac907c7943bc7e196b11812adfa95cb28ef/starfire.c/buggy/drivers/net/starfire.c