for (i = 0; i < num_counters; ++i) { 
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { 
static void power4_handle_interrupt(struct pt_regs *regs,				    struct op_counter_config *ctr){	unsigned long pc;	int is_kernel;	int val;	int i;	unsigned int mmcr0;	pc = get_pc(regs);	is_kernel = get_kernel(pc);	/* set the PMM bit (see comment below) */	mtmsrd(mfmsr() | MSR_PMM);	for (i = 0; i < num_counters; ++i) {		val = ctr_read(i);		if (val < 0) {			if (oprofile_running && ctr[i].enabled) {				oprofile_add_pc(pc, is_kernel, i);				ctr_write(i, reset_value[i]);			} else {				ctr_write(i, 0);			}		}	}	mmcr0 = mfspr(SPRN_MMCR0);	/* reset the perfmon trigger */	mmcr0 |= MMCR0_PMXE;	/*	 * We must clear the PMAO bit on some (GQ) chips. Just do it	 * all the time	 */	mmcr0 &= ~MMCR0_PMAO;	/*	 * now clear the freeze bit, counting will not start until we	 * rfid from this exception, because only at that point will	 * the PMM bit be cleared	 */	mmcr0 &= ~MMCR0_FC;	mtspr(SPRN_MMCR0, mmcr0);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a6908cd00036080fbea14ff67335e5f2a1ab5489/op_model_power4.c/clean/arch/ppc64/oprofile/op_model_power4.c