/* * The RX Stop command will not work for Yukon-2 if the BMU does not * reach the end of packet and since we can't make sure that we have * incoming data, we must reset the BMU while it is not doing a DMA * transfer. Since it is possible that the RX path is still active, * the RX RAM buffer will be stopped first, so any possible incoming * data will not trigger a DMA. After the RAM buffer is stopped, the * BMU is polled until any DMA in progress is ended and only then it * will be reset. */  /* disable the RAM Buffer receive queue */ sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_DIS_OP_MD);  for (i = 0; i < 0xffff; i++) if (sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RSL)) == sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RL))) break;  sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_RST_SET | BMU_FIFO_RST); /* reset the Rx prefetch unit */ sky2_write32(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 
sky2_rx_stop(sky2); 
static int sky2_down(struct net_device *dev){	struct sky2_port *sky2 = netdev_priv(dev);	struct sky2_hw *hw = sky2->hw;	unsigned port = sky2->port;	u16 ctrl;	int i;	if (netif_msg_ifdown(sky2))		printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);	netif_stop_queue(dev);	sky2_phy_reset(hw, port);	/* Stop transmitter */	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);	sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),		     RB_RST_SET | RB_DIS_OP_MD);	ctrl = gma_read16(hw, port, GM_GP_CTRL);	ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);	gma_write16(hw, port, GM_GP_CTRL, ctrl);	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);	/* Workaround shared GMAC reset */	if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0	      && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);	/* Disable Force Sync bit and Enable Alloc bit */	sky2_write8(hw, SK_REG(port, TXA_CTRL),		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);	/* Stop Interval Timer and Limit Counter of Tx Arbiter */	sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);	sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);	/* Reset the PCI FIFO of the async Tx queue */	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),		     BMU_RST_SET | BMU_FIFO_RST);	/* Reset the Tx prefetch units */	sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),		     PREF_UNIT_RST_SET);	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);	/*	 * The RX Stop command will not work for Yukon-2 if the BMU does not	 * reach the end of packet and since we can't make sure that we have	 * incoming data, we must reset the BMU while it is not doing a DMA	 * transfer. Since it is possible that the RX path is still active,	 * the RX RAM buffer will be stopped first, so any possible incoming	 * data will not trigger a DMA. After the RAM buffer is stopped, the	 * BMU is polled until any DMA in progress is ended and only then it	 * will be reset.	 */	/* disable the RAM Buffer receive queue */	sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_DIS_OP_MD);	for (i = 0; i < 0xffff; i++)		if (sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RSL))		    == sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RL)))			break;	sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR),		     BMU_RST_SET | BMU_FIFO_RST);	/* reset the Rx prefetch unit */	sky2_write32(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_CTRL),		     PREF_UNIT_RST_SET);	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);	/* turn off led's */	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);	sky2_tx_clean(sky2);	sky2_rx_clean(sky2);	pci_free_consistent(hw->pdev, RX_LE_BYTES,			    sky2->rx_le, sky2->rx_le_map);	kfree(sky2->rx_ring);	pci_free_consistent(hw->pdev,			    TX_RING_SIZE * sizeof(struct sky2_tx_le),			    sky2->tx_le, sky2->tx_le_map);	kfree(sky2->tx_ring);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/6b1a3aefd897fd9be410d192f950656ef2b59694/sky2.c/buggy/drivers/net/sky2.c