/* Mask all interrupts */ gfar_write(&regs->imask, IMASK_INIT_CLEAR);  /* Clear all interrupts */ gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);  /* Stop the DMA, and wait for it to stop */ tempval = gfar_read(&priv->regs->dmactrl); if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != (DMACTRL_GRS | DMACTRL_GTS)) { tempval |= (DMACTRL_GRS | DMACTRL_GTS); gfar_write(&priv->regs->dmactrl, tempval);  while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))) cpu_relax(); }  /* Disable Rx and Tx */ tempval = gfar_read(&regs->maccfg1); tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); gfar_write(&regs->maccfg1, tempval); 
gfar_halt(dev); 
void stop_gfar(struct net_device *dev){	struct gfar_private *priv = netdev_priv(dev);	struct gfar *regs = priv->regs;	unsigned long flags;	u32 tempval;	/* Lock it down */	spin_lock_irqsave(&priv->lock, flags);	/* Tell the kernel the link is down */	priv->mii_info->link = 0;	adjust_link(dev);	/* Mask all interrupts */	gfar_write(&regs->imask, IMASK_INIT_CLEAR);	/* Clear all interrupts */	gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);	/* Stop the DMA, and wait for it to stop */	tempval = gfar_read(&priv->regs->dmactrl);	if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))	    != (DMACTRL_GRS | DMACTRL_GTS)) {		tempval |= (DMACTRL_GRS | DMACTRL_GTS);		gfar_write(&priv->regs->dmactrl, tempval);		while (!(gfar_read(&priv->regs->ievent) &			 (IEVENT_GRSC | IEVENT_GTSC)))			cpu_relax();	}	/* Disable Rx and Tx */	tempval = gfar_read(&regs->maccfg1);	tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);	gfar_write(&regs->maccfg1, tempval);	if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {		/* Clear any pending interrupts */		mii_clear_phy_interrupt(priv->mii_info);		/* Disable PHY Interrupts */		mii_configure_phy_interrupt(priv->mii_info, 				MII_INTERRUPT_DISABLED);	}	spin_unlock_irqrestore(&priv->lock, flags);	/* Free the IRQs */	if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {		free_irq(priv->interruptError, dev);		free_irq(priv->interruptTransmit, dev);		free_irq(priv->interruptReceive, dev);	} else {		free_irq(priv->interruptTransmit, dev);	}	if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {		free_irq(priv->einfo->interruptPHY, dev);	} else {		del_timer_sync(&priv->phy_info_timer);	}	free_skb_resources(priv);	dma_free_coherent(NULL,			sizeof(struct txbd8)*priv->tx_ring_size			+ sizeof(struct rxbd8)*priv->rx_ring_size,			priv->tx_bd_base,			gfar_read(&regs->tbase));}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/0bbaf069f053957e8d733784e18a2992afd1dd3c/gianfar.c/buggy/drivers/net/gianfar.c