/*	if (state->config->pll_init) { dib3000mc_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe)); state->config->pll_init(fe,NULL); dib3000mc_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe)); }*/ 
if (state->config.pll_init) state->config.pll_init(fe);  
static int dib3000mc_fe_init(struct dvb_frontend* fe, int mobile_mode){	struct dib3000_state *state;	deb_info("init start\n");	state = fe->demodulator_priv;	state->timing_offset = 0;	state->timing_offset_comp_done = 0;	wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_CONFIG);	wr(DIB3000MC_REG_RESTART,DIB3000MC_RESTART_OFF);	wr(DIB3000MC_REG_CLK_CFG_1,DIB3000MC_CLK_CFG_1_POWER_UP);	wr(DIB3000MC_REG_CLK_CFG_2,DIB3000MC_CLK_CFG_2_PUP_MOBILE);	wr(DIB3000MC_REG_CLK_CFG_3,DIB3000MC_CLK_CFG_3_POWER_UP);	wr(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_INIT);	wr(DIB3000MC_REG_RST_UNC,DIB3000MC_RST_UNC_OFF);	wr(DIB3000MC_REG_UNK_19,DIB3000MC_UNK_19);	wr(33,5);	wr(36,81);	wr(DIB3000MC_REG_UNK_88,DIB3000MC_UNK_88);	wr(DIB3000MC_REG_UNK_99,DIB3000MC_UNK_99);	wr(DIB3000MC_REG_UNK_111,DIB3000MC_UNK_111_PH_N_MODE_0); /* phase noise algo off */	/* mobile mode - portable reception */	wr_foreach(dib3000mc_reg_mobile_mode,dib3000mc_mobile_mode[1]);/* TUNER_PANASONIC_ENV57H12D5: */	wr_foreach(dib3000mc_reg_agc_bandwidth,dib3000mc_agc_bandwidth);	wr_foreach(dib3000mc_reg_agc_bandwidth_general,dib3000mc_agc_bandwidth_general);	wr_foreach(dib3000mc_reg_agc,dib3000mc_agc_tuner[1]);	wr(DIB3000MC_REG_UNK_110,DIB3000MC_UNK_110);	wr(26,0x6680);	wr(DIB3000MC_REG_UNK_1,DIB3000MC_UNK_1);	wr(DIB3000MC_REG_UNK_2,DIB3000MC_UNK_2);	wr(DIB3000MC_REG_UNK_3,DIB3000MC_UNK_3);	wr(DIB3000MC_REG_SEQ_TPS,DIB3000MC_SEQ_TPS_DEFAULT);	wr_foreach(dib3000mc_reg_bandwidth,dib3000mc_bandwidth_8mhz);	wr_foreach(dib3000mc_reg_bandwidth_general,dib3000mc_bandwidth_general);	wr(DIB3000MC_REG_UNK_4,DIB3000MC_UNK_4);	wr(DIB3000MC_REG_SET_DDS_FREQ_MSB,DIB3000MC_DDS_FREQ_MSB_INV_OFF);	wr(DIB3000MC_REG_SET_DDS_FREQ_LSB,DIB3000MC_DDS_FREQ_LSB);	dib3000mc_set_timing(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);//	wr_foreach(dib3000mc_reg_timing_freq,dib3000mc_timing_freq[3]);	wr(DIB3000MC_REG_UNK_120,DIB3000MC_UNK_120);	wr(DIB3000MC_REG_UNK_134,DIB3000MC_UNK_134);	wr(DIB3000MC_REG_FEC_CFG,DIB3000MC_FEC_CFG);	wr(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);	dib3000mc_set_impulse_noise(state,0,TRANSMISSION_MODE_8K,BANDWIDTH_8_MHZ);/* output mode control, just the MPEG2_SLAVE *///	set_or(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);	wr(DIB3000MC_REG_OUTMODE,DIB3000MC_OM_SLAVE);	wr(DIB3000MC_REG_SMO_MODE,DIB3000MC_SMO_MODE_SLAVE);	wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_SLAVE);	wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_SLAVE);/* MPEG2_PARALLEL_CONTINUOUS_CLOCK	wr(DIB3000MC_REG_OUTMODE,		DIB3000MC_SET_OUTMODE(DIB3000MC_OM_PAR_CONT_CLK,			rd(DIB3000MC_REG_OUTMODE)));	wr(DIB3000MC_REG_SMO_MODE,			DIB3000MC_SMO_MODE_DEFAULT |			DIB3000MC_SMO_MODE_188);	wr(DIB3000MC_REG_FIFO_THRESHOLD,DIB3000MC_FIFO_THRESHOLD_DEFAULT);	wr(DIB3000MC_REG_ELEC_OUT,DIB3000MC_ELEC_OUT_DIV_OUT_ON);*//* diversity */	wr(DIB3000MC_REG_DIVERSITY1,DIB3000MC_DIVERSITY1_DEFAULT);	wr(DIB3000MC_REG_DIVERSITY2,DIB3000MC_DIVERSITY2_DEFAULT);	set_and(DIB3000MC_REG_DIVERSITY3,DIB3000MC_DIVERSITY3_IN_OFF);	set_or(DIB3000MC_REG_CLK_CFG_7,DIB3000MC_CLK_CFG_7_DIV_IN_OFF);/*	if (state->config->pll_init) {		dib3000mc_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));		state->config->pll_init(fe,NULL);		dib3000mc_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));	}*/	deb_info("init end\n");	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/776338e121b9db3156bfb4e21622a0219bbab9d4/dib3000mc.c/clean/drivers/media/dvb/frontends/dib3000mc.c