/* Setup address */ if (busnum == 0) type = 0;	/* Type 0 */ else type = 1;	/* Type 1 */  
static int msc_pcibios_config_access(unsigned char access_type,	struct pci_bus *bus, unsigned int devfn, int where, u32 * data){	unsigned char busnum = bus->number;	unsigned char type;	u32 intr;#ifdef CONFIG_MIPS_BOARDS_GEN	if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {		/* MIPS Core boards have SOCit connected as device 17 */		return -1;	}#endif	/* Clear status register bits. */	MSC_WRITE(MSC01_PCI_INTSTAT,		  (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));	/* Setup address */	if (busnum == 0)		type = 0;	/* Type 0 */	else		type = 1;	/* Type 1 */	MSC_WRITE(MSC01_PCI_CFGADDR,		  ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |		   (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)		   | (PCI_FUNC(devfn) <<		      MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /						      4) <<						     MSC01_PCI_CFGADDR_RNUM_SHF)		   | (type)));	/* Perform access */	if (access_type == PCI_ACCESS_WRITE)		MSC_WRITE(MSC01_PCI_CFGDATA, *data);	else		MSC_READ(MSC01_PCI_CFGDATA, *data);	/* Detect Master/Target abort */	MSC_READ(MSC01_PCI_INTSTAT, intr);	if (intr & (MSC01_PCI_INTCFG_MA_BIT |		    MSC01_PCI_INTCFG_TA_BIT)) {		/* Error occurred */		/* Clear bits */		MSC_READ(MSC01_PCI_INTSTAT, intr);		MSC_WRITE(MSC01_PCI_INTSTAT,			  (MSC01_PCI_INTCFG_MA_BIT |			   MSC01_PCI_INTCFG_TA_BIT));		return -1;	}	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/aa0980b8090878bf42bc73a13d051a203a201d7d/ops-msc.c/clean/arch/mips/pci/ops-msc.c