set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(20 * HZ / 1000); 
msleep(20); 
static int sa1110_target(struct cpufreq_policy *policy,			 unsigned int target_freq,			 unsigned int relation){	struct sdram_params *sdram = &sdram_params;	struct cpufreq_freqs freqs;	struct sdram_info sd;	unsigned long flags;	unsigned int ppcr, unused;	switch(relation){	case CPUFREQ_RELATION_L:		ppcr = sa11x0_freq_to_ppcr(target_freq);		if (sa11x0_ppcr_to_freq(ppcr) > policy->max)			ppcr--;		break;	case CPUFREQ_RELATION_H:		ppcr = sa11x0_freq_to_ppcr(target_freq);		if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&		    (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))			ppcr--;		break;	default:		return -EINVAL;	}	freqs.old = sa11x0_getspeed(0);	freqs.new = sa11x0_ppcr_to_freq(ppcr);	freqs.cpu = 0;	sdram_calculate_timing(&sd, freqs.new, sdram);#if 0	/*	 * These values are wrong according to the SA1110 documentation	 * and errata, but they seem to work.  Need to get a storage	 * scope on to the SDRAM signals to work out why.	 */	if (policy->max < 147500) {		sd.mdrefr |= MDREFR_K1DB2;		sd.mdcas[0] = 0xaaaaaa7f;	} else {		sd.mdrefr &= ~MDREFR_K1DB2;		sd.mdcas[0] = 0xaaaaaa9f;	}	sd.mdcas[1] = 0xaaaaaaaa;	sd.mdcas[2] = 0xaaaaaaaa;#endif	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);	/*	 * The clock could be going away for some time.  Set the SDRAMs	 * to refresh rapidly (every 64 memory clock cycles).  To get	 * through the whole array, we need to wait 262144 mclk cycles.	 * We wait 20ms to be safe.	 */	sdram_set_refresh(2);	if (!irqs_disabled()) {		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout(20 * HZ / 1000);	} else {		mdelay(20);	}	/*	 * Reprogram the DRAM timings with interrupts disabled, and	 * ensure that we are doing this within a complete cache line.	 * This means that we won't access SDRAM for the duration of	 * the programming.	 */	local_irq_save(flags);	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));	udelay(10);	__asm__ __volatile__("					\n\		b	2f					\n\		.align	5					\n\1:		str	%3, [%1, #0]		@ MDCNFG	\n\		str	%4, [%1, #28]		@ MDREFR	\n\		str	%5, [%1, #4]		@ MDCAS0	\n\		str	%6, [%1, #8]		@ MDCAS1	\n\		str	%7, [%1, #12]		@ MDCAS2	\n\		str	%8, [%2, #0]		@ PPCR		\n\		ldr	%0, [%1, #0]				\n\		b	3f					\n\2:		b	1b					\n\3:		nop						\n\		nop"		: "=&r" (unused)		: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),		  "r" (sd.mdrefr), "r" (sd.mdcas[0]),		  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));	local_irq_restore(flags);	/*	 * Now, return the SDRAM refresh back to normal.	 */	sdram_update_refresh(freqs.new, sdram);	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/db5795547694cf68388aaf8f59723e850f7466f6/cpu-sa1110.c/buggy/arch/arm/mach-sa1100/cpu-sa1110.c