d->handle(IRQ_NEPONSET_USAR, d, regs); 
desc_handle_irq(IRQ_NEPONSET_USAR, d, regs); 
neponset_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs){	unsigned int irr;	while (1) {		struct irqdesc *d;		/*		 * Acknowledge the parent IRQ.		 */		desc->chip->ack(irq);		/*		 * Read the interrupt reason register.  Let's have all		 * active IRQ bits high.  Note: there is a typo in the		 * Neponset user's guide for the SA1111 IRR level.		 */		irr = IRR ^ (IRR_ETHERNET | IRR_USAR);		if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)			break;		/*		 * Since there is no individual mask, we have to		 * mask the parent IRQ.  This is safe, since we'll		 * recheck the register for any pending IRQs.		 */		if (irr & (IRR_ETHERNET | IRR_USAR)) {			desc->chip->mask(irq);			if (irr & IRR_ETHERNET) {				d = irq_desc + IRQ_NEPONSET_SMC9196;				d->handle(IRQ_NEPONSET_SMC9196, d, regs);			}			if (irr & IRR_USAR) {				d = irq_desc + IRQ_NEPONSET_USAR;				d->handle(IRQ_NEPONSET_USAR, d, regs);			}			desc->chip->unmask(irq);		}		if (irr & IRR_SA1111) {			d = irq_desc + IRQ_NEPONSET_SA1111;			d->handle(IRQ_NEPONSET_SA1111, d, regs);		}	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/664399e1fbdceb18da9c9c5534dedd62327c63e8/neponset.c/clean/arch/arm/mach-sa1100/neponset.c