iommu_free_ctx(iommu, ctx);  
void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma){	struct pcidev_cookie *pcp;	struct pci_iommu *iommu;	iopte_t *iopte;	unsigned long flags, order, npages, i, ctx;	npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;	pcp = pdev->sysdata;	iommu = pcp->pbm->iommu;	iopte = iommu->page_table +		((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);	spin_lock_irqsave(&iommu->lock, flags);	if ((iopte - iommu->page_table) ==	    iommu->lowest_consistent_map) {		iopte_t *walk = iopte + npages;		iopte_t *limit;		limit = (iommu->page_table +			 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));		while (walk < limit) {			if (!IOPTE_IS_DUMMY(iommu, walk))				break;			walk++;		}		iommu->lowest_consistent_map =			(walk - iommu->page_table);	}	/* Data for consistent mappings cannot enter the streaming	 * buffers, so we only need to update the TSB.  We flush	 * the IOMMU here as well to prevent conflicts with the	 * streaming mapping deferred tlb flush scheme.	 */	ctx = 0;	if (iommu->iommu_ctxflush)		ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;	for (i = 0; i < npages; i++, iopte++)		iopte_make_dummy(iommu, iopte);	if (iommu->iommu_ctxflush) {		pci_iommu_write(iommu->iommu_ctxflush, ctx);	} else {		for (i = 0; i < npages; i++) {			u32 daddr = dvma + (i << IO_PAGE_SHIFT);			pci_iommu_write(iommu->iommu_flush, daddr);		}	}	spin_unlock_irqrestore(&iommu->lock, flags);	order = get_order(size);	if (order < 10)		free_pages((unsigned long)cpu, order);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7c963ad1d113790a8c723a178988b675868f3abe/pci_iommu.c/buggy/arch/sparc64/kernel/pci_iommu.c