 #define	SANDPOINT_87308_CFG_ADDR		0x15c #define	SANDPOINT_87308_CFG_DATA		0x15d  #define	SANDPOINT_87308_CFG_INB(addr, byte) {				\ outb((addr), SANDPOINT_87308_CFG_ADDR);				\ (byte) = inb(SANDPOINT_87308_CFG_DATA);				\ }  #define	SANDPOINT_87308_CFG_OUTB(addr, byte) {				\ outb((addr), SANDPOINT_87308_CFG_ADDR);				\ outb((byte), SANDPOINT_87308_CFG_DATA);				\ }  #define SANDPOINT_87308_SELECT_DEV(dev_num) {				\ SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));			\ }  #define	SANDPOINT_87308_DEV_ENABLE(dev_num) {				\ SANDPOINT_87308_SELECT_DEV(dev_num);				\ SANDPOINT_87308_CFG_OUTB(0x30, 0x01);				\ }  /* * To probe the Sandpoint type, we need to check for a connection between GPIO * pins 6 and 7 on the NS87308 SuperIO. */ static void __init sandpoint_probe_type(void) { u8 x; /* First, ensure that the GPIO pins are enabled. */ SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */ SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */ SANDPOINT_87308_CFG_OUTB(0x61, 0x00); SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */  /* Now, set pin 7 to output and pin 6 to input. */ outb((inb(0x701) | 0x80) & 0xbf, 0x701); /* Set push-pull output */ outb(inb(0x702) | 0x80, 0x702); /* Set pull-up on input */ outb(inb(0x703) | 0x40, 0x703); /* Set output high and check */ x = inb(0x700); outb(x | 0x80, 0x700); x = inb(0x700); sandpoint_is_x2 = ! (x & 0x40); if (ppc_md.progress && sandpoint_is_x2) ppc_md.progress("High output says X2", 0); /* Set output low and check */ outb(x & 0x7f, 0x700); sandpoint_is_x2 |= inb(0x700) & 0x40; if (ppc_md.progress && sandpoint_is_x2) ppc_md.progress("Low output says X2", 0); if (ppc_md.progress && ! sandpoint_is_x2) ppc_md.progress("Sandpoint is X3", 0); }  /* * Fix IDE interrupts. */ static int __init sandpoint_fix_winbond_83553(void) { /* Make some 8259 interrupt level sensitive */ outb(0xe0, 0x4d0); outb(0xde, 0x4d1);  return 0; }  arch_initcall(sandpoint_fix_winbond_83553);  /* * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip. */ static int __init sandpoint_setup_natl_87308(void) { u_char	reg;  /* * Enable all the devices on the Super I/O chip. */ SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */ SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */ SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */ SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */ SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */ SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */ SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */ SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */ SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */ SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */ SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */  /* Set up floppy in PS/2 mode */ outb(0x09, SIO_CONFIG_RA); reg = inb(SIO_CONFIG_RD); reg = (reg & 0x3F) | 0x40; outb(reg, SIO_CONFIG_RD); outb(reg, SIO_CONFIG_RD);	/* Have to write twice to change! */  return 0; }  arch_initcall(sandpoint_setup_natl_87308);  static int __init sandpoint_request_io(void) { request_region(0x00,0x20,"dma1"); request_region(0x20,0x20,"pic1"); request_region(0x40,0x20,"timer"); request_region(0x80,0x10,"dma page reg"); request_region(0xa0,0x20,"pic2"); request_region(0xc0,0x20,"dma2");  return 0; }  arch_initcall(sandpoint_request_io);  /* * Interrupt setup and service.  Interrrupts on the Sandpoint come * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO). * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, * IDE is on EPIC 7 and 8. */ static void __init sandpoint_init_IRQ(void) { int i;  OpenPIC_InitSenses = sandpoint_openpic_initsenses; OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);  mpc10x_set_openpic(); openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade", i8259_irq);  /* * openpic_init() has set up irq_desc[16-31] to be openpic * interrupts.  We need to set irq_desc[0-15] to be i8259 * interrupts. */ for(i=0; i < NUM_8259_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic;  /* * The EPIC allows for a read in the range of 0xFEF00000 -> * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction. */ i8259_init(0xfef00000); }  static u32 sandpoint_irq_canonicalize(u32 irq) { if (irq == 2) return 9; else return irq; }  static unsigned long __init sandpoint_find_end_of_memory(void) { bd_t *bp = (bd_t *)__res;  if (bp->bi_memsize) return bp->bi_memsize;  /* DINK32 13.0 correctly initalizes things, so iff you use * this you _should_ be able to change this instead of a * hardcoded value. */ #if 0 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B); #else return 32*1024*1024; #endif }  static void __init sandpoint_map_io(void) { io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO); }  static void sandpoint_restart(char *cmd) { local_irq_disable();  /* Set exception prefix high - to the firmware */ _nmask_and_or_msr(0, MSR_IP);  /* Reset system via Port 92 */ outb(0x00, 0x92); outb(0x01, 0x92); for(;;);	/* Spin until reset happens */ }  static void sandpoint_power_off(void) { local_irq_disable(); for(;;);	/* No way to shut power off with software */ /* NOTREACHED */ }  static void sandpoint_halt(void) { sandpoint_power_off(); /* NOTREACHED */ }  static int sandpoint_show_cpuinfo(struct seq_file *m) { seq_printf(m, "vendor\t\t: Motorola SPS\n"); seq_printf(m, "machine\t\t: Sandpoint\n");  return 0; }  #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) /* * IDE support. */ static int		sandpoint_ide_ports_known = 0; static unsigned long	sandpoint_ide_regbase[MAX_HWIFS]; static unsigned long	sandpoint_ide_ctl_regbase[MAX_HWIFS]; static unsigned long	sandpoint_idedma_regbase;  static void sandpoint_ide_probe(void) { struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, NULL);  if (pdev) { sandpoint_ide_regbase[0]=pdev->resource[0].start; sandpoint_ide_regbase[1]=pdev->resource[2].start; sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start; sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start; sandpoint_idedma_regbase=pdev->resource[4].start; pci_dev_put(pdev); }  sandpoint_ide_ports_known = 1; }  static int sandpoint_ide_default_irq(unsigned long base) { if (sandpoint_ide_ports_known == 0) sandpoint_ide_probe();  if (base == sandpoint_ide_regbase[0]) return SANDPOINT_IDE_INT0; else if (base == sandpoint_ide_regbase[1]) return SANDPOINT_IDE_INT1; else return 0; }  static unsigned long sandpoint_ide_default_io_base(int index) { if (sandpoint_ide_ports_known == 0) sandpoint_ide_probe();  return sandpoint_ide_regbase[index]; }  static void __init sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq) { unsigned long reg = data_port; uint	alt_status_base; int	i;  for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { hw->io_ports[i] = reg++; }  if (data_port == sandpoint_ide_regbase[0]) { alt_status_base = sandpoint_ide_ctl_regbase[0] + 2; hw->irq = 14; } else if (data_port == sandpoint_ide_regbase[1]) { alt_status_base = sandpoint_ide_ctl_regbase[1] + 2; hw->irq = 15; } else { alt_status_base = 0; hw->irq = 0; }  if (ctrl_port) { hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; } else { hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base; }  if (irq != NULL) { *irq = hw->irq; } } #endif  /* * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1. */ static __inline__ void sandpoint_set_bat(void) { unsigned long bat3u, bat3l;  __asm__ __volatile__( " lis %0,0xf800\n	\ ori %1,%0,0x002a\n	\ ori %0,%0,0x0ffe\n	\ mtspr 0x21e,%0\n	\ mtspr 0x21f,%1\n	\ isync\n			\ sync " : "=r" (bat3u), "=r" (bat3l)); }  TODC_ALLOC();  void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { parse_bootinfo(find_bootinfo());  /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer) * are non-zero, then we should use the board info from the bd_t * structure and the cmdline pointed to by r6 instead of the * information from birecs, if any.  Otherwise, use the information * from birecs as discovered by the preceeding call to * parse_bootinfo().  This rule should work with both PPCBoot, which * uses a bd_t board info structure, and the kernel boot wrapper, * which uses birecs. */ if (r3 && r6) { /* copy board info structure */ memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) ); /* copy command line */ *(char *)(r7+KERNELBASE) = 0; strcpy(cmd_line, (char *)(r6+KERNELBASE)); }  #ifdef CONFIG_BLK_DEV_INITRD /* take care of initrd if we have one */ if (r4) { initrd_start = r4 + KERNELBASE; initrd_end = r5 + KERNELBASE; } #endif /* CONFIG_BLK_DEV_INITRD */  /* Map in board regs, etc. */ sandpoint_set_bat();  isa_io_base = MPC10X_MAPB_ISA_IO_BASE; isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE; pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET; ISA_DMA_THRESHOLD = 0x00ffffff; DMA_MODE_READ = 0x44; DMA_MODE_WRITE = 0x48;  ppc_md.setup_arch = sandpoint_setup_arch; ppc_md.show_cpuinfo = sandpoint_show_cpuinfo; ppc_md.irq_canonicalize = sandpoint_irq_canonicalize; ppc_md.init_IRQ = sandpoint_init_IRQ; ppc_md.get_irq = openpic_get_irq;  ppc_md.restart = sandpoint_restart; ppc_md.power_off = sandpoint_power_off; ppc_md.halt = sandpoint_halt;  ppc_md.find_end_of_memory = sandpoint_find_end_of_memory; ppc_md.setup_io_mappings = sandpoint_map_io;  TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8); ppc_md.time_init = todc_time_init; ppc_md.set_rtc_time = todc_set_rtc_time; ppc_md.get_rtc_time = todc_get_rtc_time; ppc_md.calibrate_decr = todc_calibrate_decr;  ppc_md.nvram_read_val = todc_mc146818_read_val; ppc_md.nvram_write_val = todc_mc146818_write_val;  #ifdef CONFIG_KGDB ppc_md.kgdb_map_scc = gen550_kgdb_map_scc; #endif #ifdef CONFIG_SERIAL_TEXT_DEBUG ppc_md.progress = gen550_progress; #endif  #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) ppc_ide_md.default_irq = sandpoint_ide_default_irq; ppc_ide_md.default_io_base = sandpoint_ide_default_io_base; ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports; #endif } 
sandpoint_setup_arch(void){	/* Probe for Sandpoint model */	sandpoint_probe_type();	if (sandpoint_is_x2)		epic_serial_mode = 0;	loops_per_jiffy = 100000000 / HZ;#ifdef CONFIG_BLK_DEV_INITRD	if (initrd_start)		ROOT_DEV = Root_RAM0;	else#endif#ifdef	CONFIG_ROOT_NFS		ROOT_DEV = Root_NFS;#else		ROOT_DEV = Root_HDA1;#endif	/* Lookup PCI host bridges */	sandpoint_find_bridges();	printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");	printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");	/* DINK32 12.3 and below do not correctly enable any caches.	 * We will do this now with good known values.  Future versions	 * of DINK32 are supposed to get this correct.	 */	if (cpu_has_feature(CPU_FTR_SPEC7450))		/* 745x is different.  We only want to pass along enable. */		_set_L2CR(L2CR_L2E);	else if (cpu_has_feature(CPU_FTR_L2CR))		/* All modules have 1MB of L2.  We also assume that an		 * L2 divisor of 3 will work.		 */		_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3				| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);#if 0	/* Untested right now. */	if (cpu_has_feature(CPU_FTR_L3CR)) {		/* Magic value. */		_set_L3CR(0x8f032000);	}#endif}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/682afbbd1456e9e7b64f482eb05676b933173cdf/sandpoint.c/buggy/arch/ppc/platforms/sandpoint.c