static void __init schizo_register_error_handlers(struct pci_controller_info *p) 
static void schizo_register_error_handlers(struct pci_controller_info *p) 
static void __init schizo_register_error_handlers(struct pci_controller_info *p){	struct pci_pbm_info *pbm;	unsigned int irq;	struct ino_bucket *bucket;	u64 tmp, err_mask, err_no_mask;	/* Build IRQs and register handlers. */	pbm = pbm_for_ino(p, SCHIZO_UE_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);	if (request_irq(irq, schizo_ue_intr,			SA_SHIRQ, "SCHIZO UE", p) < 0) {		prom_printf("%s: Cannot register UE interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_CE_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);	if (request_irq(irq, schizo_ce_intr,			SA_SHIRQ, "SCHIZO CE", p) < 0) {		prom_printf("%s: Cannot register CE interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO);	if (request_irq(irq, schizo_pcierr_intr,			SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) {		prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO);	if (request_irq(irq, schizo_pcierr_intr,			SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) {		prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));	pbm = pbm_for_ino(p, SCHIZO_SERR_INO);	irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);	if (request_irq(irq, schizo_safarierr_intr,			SA_SHIRQ, "SCHIZO SERR", p) < 0) {		prom_printf("%s: Cannot register SafariERR interrupt.\n",			    pbm->name);		prom_halt();	}	bucket = __bucket(irq);	tmp = upa_readl(bucket->imap);	upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));	/* Enable UE and CE interrupts for controller. */	schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,		     (SCHIZO_ECCCTRL_EE |		      SCHIZO_ECCCTRL_UE |		      SCHIZO_ECCCTRL_CE));	err_mask = (SCHIZO_PCICTRL_BUS_UNUS |		    SCHIZO_PCICTRL_ESLCK |		    SCHIZO_PCICTRL_TTO_ERR |		    SCHIZO_PCICTRL_RTRY_ERR |		    SCHIZO_PCICTRL_SBH_ERR |		    SCHIZO_PCICTRL_SERR |		    SCHIZO_PCICTRL_EEN);	err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |		       SCHIZO_PCICTRL_SBH_INT);	/* Enable PCI Error interrupts and clear error	 * bits for each PBM.	 */	tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);	tmp |= err_mask;	tmp &= ~err_no_mask;	schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);	schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,		     (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |		      SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |		      SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |		      SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |		      SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |		      SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));	tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);	tmp |= err_mask;	tmp &= ~err_no_mask;	schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);	schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR,		     (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |		      SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |		      SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |		      SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |		      SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |		      SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));	/* Make all Safari error conditions fatal except unmapped	 * errors which we make generate interrupts.	 */	err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |		    BUS_ERROR_BADMA | BUS_ERROR_BADMB |		    BUS_ERROR_BADMC |		    BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |		    BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |		    BUS_ERROR_CIQTO |		    BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |		    BUS_ERROR_UFPQTO | BUS_ERROR_APERR |		    BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |		    BUS_ERROR_ILL);#if 1	/* XXX Something wrong with some Excalibur systems	 * XXX Sun is shipping.  The behavior on a 2-cpu	 * XXX machine is that both CPU1 parity error bits	 * XXX are set and are immediately set again when	 * XXX their error status bits are cleared.  Just	 * XXX ignore them for now.  -DaveM	 */	err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |		      BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);#endif	schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,		     (SCHIZO_SAFERRCTRL_EN | err_mask));	schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,		     (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_schizo.c/clean/arch/sparc64/kernel/pci_schizo.c