void __devinit intel_p6_mcheck_init(struct cpuinfo_x86 *c) 
void intel_p6_mcheck_init(struct cpuinfo_x86 *c) 
void __devinit intel_p6_mcheck_init(struct cpuinfo_x86 *c){	u32 l, h;	int i;		/* Check for MCE support */	if (!cpu_has(c, X86_FEATURE_MCE))		return;	/* Check for PPro style MCA */ 	if (!cpu_has(c, X86_FEATURE_MCA))		return;	/* Ok machine check is available */	machine_check_vector = intel_machine_check;	wmb();	printk (KERN_INFO "Intel machine check architecture supported.\n");	rdmsr (MSR_IA32_MCG_CAP, l, h);	if (l & (1<<8))	/* Control register present ? */		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);	nr_mce_banks = l & 0xff;	/*	 * Following the example in IA-32 SDM Vol 3:	 * - MC0_CTL should not be written	 * - Status registers on all banks should be cleared on reset	 */	for (i=1; i<nr_mce_banks; i++)		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);	for (i=0; i<nr_mce_banks; i++)		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);	set_in_cr4 (X86_CR4_MCE);	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",		smp_processor_id());}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/31ab269a0307d8725737dfbbdeb5dcde7b41bc36/p6.c/buggy/arch/i386/kernel/cpu/mcheck/p6.c