*PCI_CSR = PCI_CSR_IC; 
*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; 
void __init ixp4xx_pci_preinit(void){  	unsigned long processor_id;	asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);	/*	 * Determine which PCI read method to use.	 * Rev 0 IXP425 requires workaround.	 */	if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {		printk("PCI: IXP42x A0 silicon detected - "			"PCI Non-Prefetch Workaround Enabled\n");		ixp4xx_pci_read = ixp4xx_pci_read_errata;	} else		ixp4xx_pci_read = ixp4xx_pci_read_no_errata;	/* hook in our fault handler for PCI errors */	hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");	pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");	/* 	 * We use identity AHB->PCI address translation	 * in the 0x48000000 to 0x4bffffff address space	 */	*PCI_PCIMEMBASE = 0x48494A4B;	/* 	 * We also use identity PCI->AHB address translation	 * in 4 16MB BARs that begin at the physical memory start	 */	*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + 		((PHYS_OFFSET & 0xFF000000) >> 8) +		((PHYS_OFFSET & 0xFF000000) >> 16) +		((PHYS_OFFSET & 0xFF000000) >> 24) +		0x00010203;	if (*PCI_CSR & PCI_CSR_HOST) {		printk("PCI: IXP4xx is host\n");		pr_debug("setup BARs in controller\n");		/*		 * We configure the PCI inbound memory windows to be 		 * 1:1 mapped to SDRAM		 */		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);		local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);		local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);		local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);		/*		 * Enable CSR window at 0xff000000.		 */		local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);		/*		 * Enable the IO window to be way up high, at 0xfffffc00		 */		local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);	} else {		printk("PCI: IXP4xx is target - No bus scan performed\n");	}	printk("PCI: IXP4xx Using %s access for memory space\n",#ifndef CONFIG_IXP4XX_INDIRECT_PCI			"direct"#else			"indirect"#endif		);	pr_debug("clear error bits in ISR\n");	*PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;	/*	 * Set Initialize Complete in PCI Control Register: allow IXP4XX to	 * respond to PCI configuration cycles. Specify that the AHB bus is	 * operating in big endian mode. Set up byte lane swapping between 	 * little-endian PCI and the big-endian AHB bus 	 */#ifdef __ARMEB__	*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;#else	*PCI_CSR = PCI_CSR_IC;#endif	pr_debug("DONE\n");}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/84613387cb60bc760a4588822cd61fb88e1d7fad/common-pci.c/buggy/arch/arm/mach-ixp4xx/common-pci.c