mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 
static void __init build_mem_type_table(void){	struct cachepolicy *cp;	unsigned int cr = get_cr();	int cpu_arch = cpu_architecture();	int i;#if defined(CONFIG_CPU_DCACHE_DISABLE)	if (cachepolicy > CPOLICY_BUFFERED)		cachepolicy = CPOLICY_BUFFERED;#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)	if (cachepolicy > CPOLICY_WRITETHROUGH)		cachepolicy = CPOLICY_WRITETHROUGH;#endif	if (cpu_arch < CPU_ARCH_ARMv5) {		if (cachepolicy >= CPOLICY_WRITEALLOC)			cachepolicy = CPOLICY_WRITEBACK;		ecc_mask = 0;	}	if (cpu_arch <= CPU_ARCH_ARMv5) {		for (i = 0; i < ARRAY_SIZE(mem_types); i++) {			if (mem_types[i].prot_l1)				mem_types[i].prot_l1 |= PMD_BIT4;			if (mem_types[i].prot_sect)				mem_types[i].prot_sect |= PMD_BIT4;		}	}	/*	 * ARMv6 and above have extended page tables.	 */	if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {		/*		 * bit 4 becomes XN which we must clear for the		 * kernel memory mapping.		 */		mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;		mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;		/*		 * Mark cache clean areas read only from SVC mode		 * and no access from userspace.		 */		mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;	}	cp = &cache_policies[cachepolicy];	if (cpu_arch >= CPU_ARCH_ARMv5) {		mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;		mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;	} else {		mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte;		mem_types[MT_HIGH_VECTORS].prot_pte |= cp->pte;		mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);	}	mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;	mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;	mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;	mem_types[MT_ROM].prot_sect |= cp->pmd;	for (i = 0; i < 16; i++) {		unsigned long v = pgprot_val(protection_map[i]);		v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;		protection_map[i] = __pgprot(v);	}	pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |				 L_PTE_DIRTY | L_PTE_WRITE |				 L_PTE_EXEC | cp->pte);	switch (cp->pmd) {	case PMD_SECT_WT:		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;		break;	case PMD_SECT_WB:	case PMD_SECT_WBWA:		mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;		break;	}	printk("Memory policy: ECC %sabled, Data cache %s\n",		ecc_mask ? "en" : "dis", cp->policy);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/ca315159dfa80a2bfc7d917a717a7ee8d771bdf9/mm-armv.c/clean/arch/arm/mm/mm-armv.c