spin_lock_bh(&hw->phy_lock); 
static void yukon_mac_init(struct skge_hw *hw, int port){	struct skge_port *skge = netdev_priv(hw->dev[port]);	int i;	u32 reg;	const u8 *addr = hw->dev[port]->dev_addr;	/* WA code for COMA mode -- set PHY reset */	if (hw->chip_id == CHIP_ID_YUKON_LITE &&	    hw->chip_rev == CHIP_REV_YU_LITE_A3)		skge_write32(hw, B2_GP_IO,			     (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));	/* hard reset */	skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);	/* WA code for COMA mode -- clear PHY reset */	if (hw->chip_id == CHIP_ID_YUKON_LITE &&	    hw->chip_rev == CHIP_REV_YU_LITE_A3)		skge_write32(hw, B2_GP_IO,			     (skge_read32(hw, B2_GP_IO) | GP_DIR_9)			     & ~GP_IO_9);	/* Set hardware config mode */	reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |		GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;	reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;	/* Clear GMC reset */	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);	if (skge->autoneg == AUTONEG_DISABLE) {		reg = GM_GPCR_AU_ALL_DIS;		gma_write16(hw, port, GM_GP_CTRL,				 gma_read16(hw, port, GM_GP_CTRL) | reg);		switch (skge->speed) {		case SPEED_1000:			reg |= GM_GPCR_SPEED_1000;			/* fallthru */		case SPEED_100:			reg |= GM_GPCR_SPEED_100;		}		if (skge->duplex == DUPLEX_FULL)			reg |= GM_GPCR_DUP_FULL;	} else		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;	switch (skge->flow_control) {	case FLOW_MODE_NONE:		skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);		reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;		break;	case FLOW_MODE_LOC_SEND:		/* disable Rx flow-control */		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;	}	gma_write16(hw, port, GM_GP_CTRL, reg);	skge_read16(hw, GMAC_IRQ_SRC);	spin_lock_bh(&hw->phy_lock);	yukon_init(hw, port);	spin_unlock_bh(&hw->phy_lock);	/* MIB clear */	reg = gma_read16(hw, port, GM_PHY_ADDR);	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);	for (i = 0; i < GM_MIB_CNT_SIZE; i++)		gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);	gma_write16(hw, port, GM_PHY_ADDR, reg);	/* transmit control */	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));	/* receive control reg: unicast + multicast + no FCS  */	gma_write16(hw, port, GM_RX_CTRL,			 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);	/* transmit flow control */	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);	/* transmit parameter */	gma_write16(hw, port, GM_TX_PARAM,			 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |			 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |			 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));	/* serial mode register */	reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);	if (hw->dev[port]->mtu > 1500)		reg |= GM_SMOD_JUMBO_ENA;	gma_write16(hw, port, GM_SERIAL_MODE, reg);	/* physical address: used for pause frames */	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);	/* virtual address for data */	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);	/* enable interrupt mask for counter overflows */	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);	/* Initialize Mac Fifo */	/* Configure Rx MAC FIFO */	skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;	if (hw->chip_id == CHIP_ID_YUKON_LITE &&	    hw->chip_rev == CHIP_REV_YU_LITE_A3)		reg &= ~GMF_RX_F_FL_ON;	skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);	skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);	skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);	/* Configure Tx MAC FIFO */	skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);	skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/4ff6ac052b90ee4dfee92f8e2c5cb7ef8a4d8f13/skge.c/clean/drivers/net/skge.c