outw(0x0040, ioaddr + Wn4_NetDiag); 
iowrite16(0x0040, ioaddr + Wn4_NetDiag); 
vortex_up(struct net_device *dev){	long ioaddr = dev->base_addr;	struct vortex_private *vp = netdev_priv(dev);	unsigned int config;	int i;	if (VORTEX_PCI(vp)) {		pci_set_power_state(VORTEX_PCI(vp), PCI_D0);	/* Go active */		if (vp->pm_state_valid)			pci_restore_state(VORTEX_PCI(vp));		pci_enable_device(VORTEX_PCI(vp));	}	/* Before initializing select the active media port. */	EL3WINDOW(3);	config = inl(ioaddr + Wn3_Config);	if (vp->media_override != 7) {		printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",			   dev->name, vp->media_override,			   media_tbl[vp->media_override].name);		dev->if_port = vp->media_override;	} else if (vp->autoselect) {		if (vp->has_nway) {			if (vortex_debug > 1)				printk(KERN_INFO "%s: using NWAY device table, not %d\n",								dev->name, dev->if_port);			dev->if_port = XCVR_NWAY;		} else {			/* Find first available media type, starting with 100baseTx. */			dev->if_port = XCVR_100baseTx;			while (! (vp->available_media & media_tbl[dev->if_port].mask))				dev->if_port = media_tbl[dev->if_port].next;			if (vortex_debug > 1)				printk(KERN_INFO "%s: first available media type: %s\n",					dev->name, media_tbl[dev->if_port].name);		}	} else {		dev->if_port = vp->default_media;		if (vortex_debug > 1)			printk(KERN_INFO "%s: using default media %s\n",				dev->name, media_tbl[dev->if_port].name);	}	init_timer(&vp->timer);	vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);	vp->timer.data = (unsigned long)dev;	vp->timer.function = vortex_timer;		/* timer handler */	add_timer(&vp->timer);	init_timer(&vp->rx_oom_timer);	vp->rx_oom_timer.data = (unsigned long)dev;	vp->rx_oom_timer.function = rx_oom_timer;	if (vortex_debug > 1)		printk(KERN_DEBUG "%s: Initial media type %s.\n",			   dev->name, media_tbl[dev->if_port].name);	vp->full_duplex = vp->force_fd;	config = BFINS(config, dev->if_port, 20, 4);	if (vortex_debug > 6)		printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);	outl(config, ioaddr + Wn3_Config);	if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {		int mii_reg1, mii_reg5;		EL3WINDOW(4);		/* Read BMSR (reg1) only to clear old status. */		mii_reg1 = mdio_read(dev, vp->phys[0], 1);		mii_reg5 = mdio_read(dev, vp->phys[0], 5);		if (mii_reg5 == 0xffff  ||  mii_reg5 == 0x0000) {			netif_carrier_off(dev); /* No MII device or no link partner report */		} else {			mii_reg5 &= vp->advertising;			if ((mii_reg5 & 0x0100) != 0	/* 100baseTx-FD */				 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */			vp->full_duplex = 1;			netif_carrier_on(dev);		}		vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);		if (vortex_debug > 1)			printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"				   " info1 %04x, setting %s-duplex.\n",					dev->name, vp->phys[0],					mii_reg1, mii_reg5,					vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");		EL3WINDOW(3);	}	/* Set the full-duplex bit. */	outw(	((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |		 	(vp->large_frames ? 0x40 : 0) |			((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),			ioaddr + Wn3_MAC_Ctrl);	if (vortex_debug > 1) {		printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",			dev->name, config);	}	issue_and_wait(dev, TxReset);	/*	 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.	 */	issue_and_wait(dev, RxReset|0x04);	outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);	if (vortex_debug > 1) {		EL3WINDOW(4);		printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",			   dev->name, dev->irq, inw(ioaddr + Wn4_Media));	}	/* Set the station address and mask in window 2 each time opened. */	EL3WINDOW(2);	for (i = 0; i < 6; i++)		outb(dev->dev_addr[i], ioaddr + i);	for (; i < 12; i+=2)		outw(0, ioaddr + i);	if (vp->cb_fn_base) {		unsigned short n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;		if (vp->drv_flags & INVERT_LED_PWR)			n |= 0x10;		if (vp->drv_flags & INVERT_MII_PWR)			n |= 0x4000;		outw(n, ioaddr + Wn2_ResetOptions);	}	if (dev->if_port == XCVR_10base2)		/* Start the thinnet transceiver. We should really wait 50ms...*/		outw(StartCoax, ioaddr + EL3_CMD);	if (dev->if_port != XCVR_NWAY) {		EL3WINDOW(4);		outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |			 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);	}	/* Switch to the stats window, and clear all stats by reading. */	outw(StatsDisable, ioaddr + EL3_CMD);	EL3WINDOW(6);	for (i = 0; i < 10; i++)		inb(ioaddr + i);	inw(ioaddr + 10);	inw(ioaddr + 12);	/* New: On the Vortex we must also clear the BadSSD counter. */	EL3WINDOW(4);	inb(ioaddr + 12);	/* ..and on the Boomerang we enable the extra statistics bits. */	outw(0x0040, ioaddr + Wn4_NetDiag);	/* Switch to register set 7 for normal use. */	EL3WINDOW(7);	if (vp->full_bus_master_rx) { /* Boomerang bus master. */		vp->cur_rx = vp->dirty_rx = 0;		/* Initialize the RxEarly register as recommended. */		outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);		outl(0x0020, ioaddr + PktStatus);		outl(vp->rx_ring_dma, ioaddr + UpListPtr);	}	if (vp->full_bus_master_tx) { 		/* Boomerang bus master Tx. */		vp->cur_tx = vp->dirty_tx = 0;		if (vp->drv_flags & IS_BOOMERANG)			outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */		/* Clear the Rx, Tx rings. */		for (i = 0; i < RX_RING_SIZE; i++)	/* AKPM: this is done in vortex_open, too */			vp->rx_ring[i].status = 0;		for (i = 0; i < TX_RING_SIZE; i++)			vp->tx_skbuff[i] = NULL;		outl(0, ioaddr + DownListPtr);	}	/* Set receiver mode: presumably accept b-case and phys addr only. */	set_rx_mode(dev);	/* enable 802.1q tagged frames */	set_8021q_mode(dev, 1);	outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. *///	issue_and_wait(dev, SetTxStart|0x07ff);	outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */	outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */	/* Allow status bits to be seen. */	vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|		(vp->full_bus_master_tx ? DownComplete : TxAvailable) |		(vp->full_bus_master_rx ? UpComplete : RxComplete) |		(vp->bus_master ? DMADone : 0);	vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |		(vp->full_bus_master_rx ? 0 : RxComplete) |		StatsFull | HostError | TxComplete | IntReq		| (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;	outw(vp->status_enable, ioaddr + EL3_CMD);	/* Ack all pending events, and set active indicator mask. */	outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,		 ioaddr + EL3_CMD);	outw(vp->intr_enable, ioaddr + EL3_CMD);	if (vp->cb_fn_base)			/* The PCMCIA people are idiots.  */		writel(0x8000, vp->cb_fn_base + 4);	netif_start_queue (dev);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/62afe595de7aaac6c140103a34dc8c208afa34e7/3c59x.c/clean/drivers/net/3c59x.c