spin_unlock(&gpio_lock); 
static ssize_t gpio_write(struct file * file, const char * buf, size_t count,                          loff_t *off){	struct gpio_private *priv = (struct gpio_private *)file->private_data;	unsigned char data, clk_mask, data_mask, write_msb;	unsigned long flags;	ssize_t retval = count;	if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {		return -EFAULT;	}    	if (!access_ok(VERIFY_READ, buf, count)) {		return -EFAULT;	}	clk_mask = priv->clk_mask;	data_mask = priv->data_mask;	/* It must have been configured using the IO_CFG_WRITE_MODE */	/* Perhaps a better error code? */	if (clk_mask == 0 || data_mask == 0) {		return -EPERM;	}	write_msb = priv->write_msb;	D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));	while (count--) {		int i;		data = *buf++;		if (priv->write_msb) {			for (i = 7; i >= 0;i--) {				local_irq_save(flags); local_irq_disable();				*priv->port = *priv->shadow &= ~clk_mask;				if (data & 1<<i)					*priv->port = *priv->shadow |= data_mask;				else					*priv->port = *priv->shadow &= ~data_mask;			/* For FPGA: min 5.0ns (DCC) before CCLK high */				*priv->port = *priv->shadow |= clk_mask;				local_irq_restore(flags);			}		} else {			for (i = 0; i <= 7;i++) {				local_irq_save(flags); local_irq_disable();				*priv->port = *priv->shadow &= ~clk_mask;				if (data & 1<<i)					*priv->port = *priv->shadow |= data_mask;				else					*priv->port = *priv->shadow &= ~data_mask;			/* For FPGA: min 5.0ns (DCC) before CCLK high */				*priv->port = *priv->shadow |= clk_mask;				local_irq_restore(flags);			}		}	}	return retval;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7e9204265b4ec6680fad9abc7a78b94087983916/gpio.c/buggy/arch/cris/arch-v10/drivers/gpio.c