 if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0)) return -EFAULT;	/* bad address */  
fix_alignment(struct pt_regs *regs){	int instr, nb, flags;#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)	int opcode, f1, f2, f3;#endif	int i, t;	int reg, areg;	int offset, nb0;	unsigned char __user *addr;	unsigned char *rptr;	union {		long l;		float f;		double d;		unsigned char v[8];	} data;	CHECK_FULL_REGS(regs);#if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)	/* The 4xx-family & Book-E processors have no DSISR register,	 * so we emulate it.	 * The POWER4 has a DSISR register but doesn't set it on	 * an alignment fault.  -- paulus	 */	if (__get_user(instr, (unsigned int __user *) regs->nip))		return 0;	opcode = OPCD(instr);	reg = RS(instr);	areg = RA(instr);	if (!IS_XFORM(opcode)) {		f1 = 0;		f2 = (instr & 0x04000000) >> 26;		f3 = (instr & 0x78000000) >> 27;	} else {		f1 = (instr & 0x00000006) >> 1;		f2 = (instr & 0x00000040) >> 6;		f3 = (instr & 0x00000780) >> 7;	}	instr = ((f1 << 5) | (f2 << 4) | f3);#else	reg = (regs->dsisr >> 5) & 0x1f;	/* source/dest register */	areg = regs->dsisr & 0x1f;		/* register to update */	instr = (regs->dsisr >> 10) & 0x7f;#endif	nb = aligninfo[instr].len;	if (nb == 0) {		long __user *p;		int i;		if (instr != DCBZ)			return 0;	/* too hard or invalid instruction */		/*		 * The dcbz (data cache block zero) instruction		 * gives an alignment fault if used on non-cacheable		 * memory.  We handle the fault mainly for the		 * case when we are running with the cache disabled		 * for debugging.		 */		p = (long __user *) (regs->dar & -L1_CACHE_BYTES);		if (user_mode(regs)		    && !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))			return -EFAULT;		for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)			if (__put_user(0, p+i))				return -EFAULT;		return 1;	}	flags = aligninfo[instr].flags;	if ((flags & (LD|ST)) == 0)		return 0;	/* For the 4xx-family & Book-E processors, the 'dar' field of the	 * pt_regs structure is overloaded and is really from the DEAR.	 */	addr = (unsigned char __user *)regs->dar;	if (flags & M) {		/* lmw, stmw, lswi/x, stswi/x */		nb0 = 0;		if (flags & HARD) {			if (flags & SX) {				nb = regs->xer & 127;				if (nb == 0)					return 1;			} else {				if (__get_user(instr,					    (unsigned int __user *)regs->nip))					return 0;				nb = (instr >> 11) & 0x1f;				if (nb == 0)					nb = 32;			}			if (nb + reg * 4 > 128) {				nb0 = nb + reg * 4 - 128;				nb = 128 - reg * 4;			}		} else {			/* lwm, stmw */			nb = (32 - reg) * 4;		}		rptr = (unsigned char *) &regs->gpr[reg];		if (flags & LD) {			for (i = 0; i < nb; ++i)				if (__get_user(rptr[i], addr+i))					return -EFAULT;			if (nb0 > 0) {				rptr = (unsigned char *) &regs->gpr[0];				addr += nb;				for (i = 0; i < nb0; ++i)					if (__get_user(rptr[i], addr+i))						return -EFAULT;			}			for (; (i & 3) != 0; ++i)				rptr[i] = 0;		} else {			for (i = 0; i < nb; ++i)				if (__put_user(rptr[i], addr+i))					return -EFAULT;			if (nb0 > 0) {				rptr = (unsigned char *) &regs->gpr[0];				addr += nb;				for (i = 0; i < nb0; ++i)					if (__put_user(rptr[i], addr+i))						return -EFAULT;			}		}		return 1;	}	offset = 0;	if (nb < 4) {		/* read/write the least significant bits */		data.l = 0;		offset = 4 - nb;	}	/* Verify the address of the operand */	if (user_mode(regs)) {		if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))			return -EFAULT;	/* bad address */	}	if (flags & F) {		preempt_disable();		if (regs->msr & MSR_FP)			giveup_fpu(current);		preempt_enable();	}	/* If we read the operand, copy it in, else get register values */	if (flags & LD) {		for (i = 0; i < nb; ++i)			if (__get_user(data.v[offset+i], addr+i))				return -EFAULT;	} else if (flags & F) {		data.d = current->thread.fpr[reg];	} else {		data.l = regs->gpr[reg];	}	switch (flags & ~U) {	case LD+SE:	/* sign extend */		if (data.v[2] >= 0x80)			data.v[0] = data.v[1] = -1;		break;	case LD+S:	/* byte-swap */	case ST+S:		if (nb == 2) {			SWAP(data.v[2], data.v[3]);		} else {			SWAP(data.v[0], data.v[3]);			SWAP(data.v[1], data.v[2]);		}		break;	/* Single-precision FP load and store require conversions... */	case LD+F+S:#ifdef CONFIG_PPC_FPU		preempt_disable();		enable_kernel_fp();		cvt_fd(&data.f, &data.d, &current->thread.fpscr);		preempt_enable();#else		return 0;#endif		break;	case ST+F+S:#ifdef CONFIG_PPC_FPU		preempt_disable();		enable_kernel_fp();		cvt_df(&data.d, &data.f, &current->thread.fpscr);		preempt_enable();#else		return 0;#endif		break;	}	if (flags & ST) {		for (i = 0; i < nb; ++i)			if (__put_user(data.v[offset+i], addr+i))				return -EFAULT;	} else if (flags & F) {		current->thread.fpr[reg] = data.d;	} else {		regs->gpr[reg] = data.l;	}	if (flags & U)		regs->gpr[areg] = regs->dar;	return 1;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d5812a77e5803468a5033be91af978be0f7a17d9/align.c/buggy/arch/ppc/kernel/align.c