#if DEBUG_TSC_SYNC 
#ifdef DEBUG_TSC_SYNC 
static __cpuinit void sync_tsc(void){	int i, done = 0;	long delta, adj, adjust_latency = 0;	unsigned long flags, rt, master_time_stamp, bound;#if DEBUG_TSC_SYNC	static struct syncdebug {		long rt;	/* roundtrip time */		long master;	/* master's timestamp */		long diff;	/* difference between midpoint and master's timestamp */		long lat;	/* estimate of tsc adjustment latency */	} t[NUM_ROUNDS] __cpuinitdata;#endif	go[MASTER] = 1;	smp_call_function(sync_master, NULL, 1, 0);	while (go[MASTER])	/* wait for master to be ready */		no_cpu_relax();	spin_lock_irqsave(&tsc_sync_lock, flags);	{		for (i = 0; i < NUM_ROUNDS; ++i) {			delta = get_delta(&rt, &master_time_stamp);			if (delta == 0) {				done = 1;	/* let's lock on to this... */				bound = rt;			}			if (!done) {				unsigned long t;				if (i > 0) {					adjust_latency += -delta;					adj = -delta + adjust_latency/4;				} else					adj = -delta;				rdtscll(t);				wrmsrl(MSR_IA32_TSC, t + adj);			}#if DEBUG_TSC_SYNC			t[i].rt = rt;			t[i].master = master_time_stamp;			t[i].diff = delta;			t[i].lat = adjust_latency/4;#endif		}	}	spin_unlock_irqrestore(&tsc_sync_lock, flags);#if DEBUG_TSC_SYNC	for (i = 0; i < NUM_ROUNDS; ++i)		printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",		       t[i].rt, t[i].master, t[i].diff, t[i].lat);#endif	printk(KERN_INFO	       "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, "	       "maxerr %lu cycles)\n",	       smp_processor_id(), boot_cpu_id, delta, rt);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/44456d37b59d8e541936ed26d8b6e08d27e88ac1/smpboot.c/buggy/arch/x86_64/kernel/smpboot.c