static void __init sabre_iommu_init(struct pci_controller_info *p, int tsbsize, unsigned long dvma_offset, u32 dma_mask) 
static void sabre_iommu_init(struct pci_controller_info *p, int tsbsize, unsigned long dvma_offset, u32 dma_mask) 
static void __init sabre_iommu_init(struct pci_controller_info *p,				    int tsbsize, unsigned long dvma_offset,				    u32 dma_mask){	struct pci_iommu *iommu = p->pbm_A.iommu;	unsigned long tsbbase, i, order;	u64 control;	/* Setup initial software IOMMU state. */	spin_lock_init(&iommu->lock);	iommu->ctx_lowest_free = 1;	/* Register addresses. */	iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;	iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;	iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;	iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;	/* Sabre's IOMMU lacks ctx flushing. */	iommu->iommu_ctxflush = 0;                                        	/* Invalidate TLB Entries. */	control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);	control |= SABRE_IOMMUCTRL_DENAB;	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);	for(i = 0; i < 16; i++) {		sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);		sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);	}	/* Leave diag mode enabled for full-flushing done	 * in pci_iommu.c	 */	iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);	if (!iommu->dummy_page) {		prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");		prom_halt();	}	memset((void *)iommu->dummy_page, 0, PAGE_SIZE);	iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);	tsbbase = __get_free_pages(GFP_KERNEL, order = get_order(tsbsize * 1024 * 8));	if (!tsbbase) {		prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");		prom_halt();	}	iommu->page_table = (iopte_t *)tsbbase;	iommu->page_table_map_base = dvma_offset;	iommu->dma_addr_mask = dma_mask;	pci_iommu_table_init(iommu, PAGE_SIZE << order);	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase));	control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);	control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);	control |= SABRE_IOMMUCTRL_ENAB;	switch(tsbsize) {	case 64:		control |= SABRE_IOMMU_TSBSZ_64K;		iommu->page_table_sz_bits = 16;		break;	case 128:		control |= SABRE_IOMMU_TSBSZ_128K;		iommu->page_table_sz_bits = 17;		break;	default:		prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);		prom_halt();		break;	}	sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);	/* We start with no consistent mappings. */	iommu->lowest_consistent_map =		1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);	for (i = 0; i < PBM_NCLUSTERS; i++) {		iommu->alloc_info[i].flush = 0;		iommu->alloc_info[i].next = 0;	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_sabre.c/buggy/arch/sparc64/kernel/pci_sabre.c