u16 subid; 
u16 subid, pci_cmd; 
void s2io_reset(nic_t * sp){	XENA_dev_config_t __iomem *bar0 = sp->bar0;	u64 val64;	u16 subid;	val64 = SW_RESET_ALL;	writeq(val64, &bar0->sw_reset);	/*	 * At this stage, if the PCI write is indeed completed, the	 * card is reset and so is the PCI Config space of the device.	 * So a read cannot be issued at this stage on any of the	 * registers to ensure the write into "sw_reset" register	 * has gone through.	 * Question: Is there any system call that will explicitly force	 * all the write commands still pending on the bus to be pushed	 * through?	 * As of now I'am just giving a 250ms delay and hoping that the	 * PCI write to sw_reset register is done by this time.	 */	msleep(250);	/* Restore the PCI state saved during initializarion. */	pci_restore_state(sp->pdev);	s2io_init_pci(sp);	msleep(250);	/* Set swapper to enable I/O register access */	s2io_set_swapper(sp);	/* Reset device statistics maintained by OS */	memset(&sp->stats, 0, sizeof (struct net_device_stats));	/* SXE-002: Configure link and activity LED to turn it off */	subid = sp->pdev->subsystem_device;	if ((subid & 0xFF) >= 0x07) {		val64 = readq(&bar0->gpio_control);		val64 |= 0x0000800000000000ULL;		writeq(val64, &bar0->gpio_control);		val64 = 0x0411040400000000ULL;		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));	}	sp->device_enabled_once = FALSE;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/5e25b9ddb6683fe225a2266b53d73c57381a0c18/s2io.c/clean/drivers/net/s2io.c