pbus->shared_type = AC97_SHARED_TYPE_ICH;	/* shared with modem driver */ 
static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override){	ac97_bus_t *pbus;	ac97_template_t ac97;	int err;	unsigned int i, codecs;	unsigned int glob_sta = 0;	ac97_bus_ops_t *ops;	static ac97_bus_ops_t standard_bus_ops = {		.write = snd_intel8x0_codec_write,		.read = snd_intel8x0_codec_read,	};	static ac97_bus_ops_t ali_bus_ops = {		.write = snd_intel8x0_ali_codec_write,		.read = snd_intel8x0_ali_codec_read,	};	chip->spdif_idx = -1; /* use PCMOUT (or disabled) */	switch (chip->device_type) {	case DEVICE_NFORCE:		chip->spdif_idx = NVD_SPBAR;		break;	case DEVICE_ALI:		chip->spdif_idx = ALID_AC97SPDIFOUT;		break;	case DEVICE_INTEL_ICH4:		chip->spdif_idx = ICHD_SPBAR;		break;	};	chip->in_ac97_init = 1;		memset(&ac97, 0, sizeof(ac97));	ac97.private_data = chip;	ac97.private_free = snd_intel8x0_mixer_free_ac97;	ac97.scaps = AC97_SCAP_SKIP_MODEM;	if (chip->xbox)		ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;	if (chip->device_type != DEVICE_ALI) {		glob_sta = igetdword(chip, ICHREG(GLOB_STA));		ops = &standard_bus_ops;		if (chip->device_type == DEVICE_INTEL_ICH4) {			codecs = 0;			if (glob_sta & ICH_PCR)				codecs++;			if (glob_sta & ICH_SCR)				codecs++;			if (glob_sta & ICH_TCR)				codecs++;			chip->in_sdin_init = 1;			for (i = 0; i < codecs; i++) {				snd_intel8x0_codec_read_test(chip, i);				chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;			}			chip->in_sdin_init = 0;		} else {			codecs = glob_sta & ICH_SCR ? 2 : 1;		}	} else {		ops = &ali_bus_ops;		codecs = 1;		/* detect the secondary codec */		for (i = 0; i < 100; i++) {			unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));			if (reg & 0x40) {				codecs = 2;				break;			}			iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);			udelay(1);		}	}	if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)		goto __err;	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;	pbus->shared_type = AC97_SHARED_TYPE_ICH;	/* shared with modem driver */	if (ac97_clock >= 8000 && ac97_clock <= 48000)		pbus->clock = ac97_clock;	/* FIXME: my test board doesn't work well with VRA... */	if (chip->device_type == DEVICE_ALI)		pbus->no_vra = 1;	else		pbus->dra = 1;	chip->ac97_bus = pbus;	ac97.pci = chip->pci;	for (i = 0; i < codecs; i++) {		ac97.num = i;		if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {			if (err != -EACCES)				snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);			if (i == 0)				goto __err;			continue;		}	}	/* tune up the primary codec */	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);	/* enable separate SDINs for ICH4 */	if (chip->device_type == DEVICE_INTEL_ICH4)		pbus->isdin = 1;	/* find the available PCM streams */	i = ARRAY_SIZE(ac97_pcm_defs);	if (chip->device_type != DEVICE_INTEL_ICH4)		i -= 2;		/* do not allocate PCM2IN and MIC2 */	if (chip->spdif_idx < 0)		i--;		/* do not allocate S/PDIF */	err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);	if (err < 0)		goto __err;	chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];	chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];	chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];	if (chip->spdif_idx >= 0)		chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];	if (chip->device_type == DEVICE_INTEL_ICH4) {		chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];		chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];	}	/* enable separate SDINs for ICH4 */	if (chip->device_type == DEVICE_INTEL_ICH4) {		struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;		u8 tmp = igetbyte(chip, ICHREG(SDM));		tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);		if (pcm) {			tmp |= ICH_SE;	/* steer enable for multiple SDINs */			tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;			for (i = 1; i < 4; i++) {				if (pcm->r[0].codec[i]) {					tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;					break;				}			}		} else {			tmp &= ~ICH_SE; /* steer disable */		}		iputbyte(chip, ICHREG(SDM), tmp);	}	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {		chip->multi4 = 1;		if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))			chip->multi6 = 1;	}	if (pbus->pcms[0].r[1].rslots[0]) {		chip->dra = 1;	}	if (chip->device_type == DEVICE_INTEL_ICH4) {		if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)			chip->smp20bit = 1;	}	if (chip->device_type == DEVICE_NFORCE) {		/* 48kHz only */		chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;	}	if (chip->device_type == DEVICE_INTEL_ICH4) {		/* use slot 10/11 for SPDIF */		u32 val;		val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;		val |= ICH_PCM_SPDIF_1011;		iputdword(chip, ICHREG(GLOB_CNT), val);		snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);	}	chip->in_ac97_init = 0;	return 0; __err:	/* clear the cold-reset bit for the next chance */	if (chip->device_type != DEVICE_ALI)		iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);	return err;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/2ba71978c04d4dba983b4fc658f82eae164c2bca/intel8x0.c/clean/sound/pci/intel8x0.c