/* Disable all DMA interrupts for the channel. */ omap_writew(0, OMAP_DMA_CICR(ch)); /* Make sure the DMA transfer is stopped. */ omap_writew(0, OMAP_DMA_CCR(ch)); 
if (cpu_class_is_omap1()) { /* Disable all DMA interrupts for the channel. */ OMAP_DMA_CICR_REG(lch) = 0; /* Make sure the DMA transfer is stopped. */ OMAP_DMA_CCR_REG(lch) = 0; }  if (cpu_is_omap24xx()) { u32 val; /* Disable interrupts */ val = omap_readl(OMAP_DMA4_IRQENABLE_L0); val &= ~(1 << lch); omap_writel(val, OMAP_DMA4_IRQENABLE_L0);  /* Clear the CSR register and IRQ status register */ OMAP_DMA_CSR_REG(lch) = 0x0;  val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); val |= 1 << lch; omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);  /* Disable all DMA interrupts for the channel. */ OMAP_DMA_CICR_REG(lch) = 0;  /* Make sure the DMA transfer is stopped. */ OMAP_DMA_CCR_REG(lch) = 0; omap_clear_dma(lch); } 
void omap_free_dma(int ch){	unsigned long flags;	spin_lock_irqsave(&dma_chan_lock, flags);	if (dma_chan[ch].dev_id == -1) {		printk("omap_dma: trying to free nonallocated DMA channel %d\n", ch);		spin_unlock_irqrestore(&dma_chan_lock, flags);		return;	}	dma_chan[ch].dev_id = -1;	spin_unlock_irqrestore(&dma_chan_lock, flags);	/* Disable all DMA interrupts for the channel. */	omap_writew(0, OMAP_DMA_CICR(ch));	/* Make sure the DMA transfer is stopped. */	omap_writew(0, OMAP_DMA_CCR(ch));}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/1a8bfa1eb998af6e650ad26201f7cae9f2a2fdc8/dma.c/buggy/arch/arm/plat-omap/dma.c