if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { 
 /* If statement applies to 5705 and 5750 PCI devices only */ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { 
static int tg3_reset_hw(struct tg3 *tp){	u32 val, rdmac_mode;	int i, err, limit;	tg3_disable_ints(tp);	tg3_stop_fw(tp);	tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {		err = tg3_abort_hw(tp);		if (err)			return err;	}	err = tg3_chip_reset(tp);	if (err)		return err;	tg3_write_sig_legacy(tp, RESET_KIND_INIT);	/* This works around an issue with Athlon chipsets on	 * B3 tigon3 silicon.  This bit has no effect on any	 * other revision.  But do not set this on PCI Express	 * chips.	 */	if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))		tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;	tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {		val = tr32(TG3PCI_PCISTATE);		val |= PCISTATE_RETRY_SAME_DMA;		tw32(TG3PCI_PCISTATE, val);	}	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {		/* Enable some hw fixes.  */		val = tr32(TG3PCI_MSI_DATA);		val |= (1 << 26) | (1 << 28) | (1 << 29);		tw32(TG3PCI_MSI_DATA, val);	}	/* Descriptor ring init may make accesses to the	 * NIC SRAM area to setup the TX descriptors, so we	 * can only do this after the hardware has been	 * successfully reset.	 */	tg3_init_rings(tp);	/* This value is determined during the probe time DMA	 * engine test, tg3_test_dma.	 */	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);	tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |			  GRC_MODE_4X_NIC_SEND_RINGS |			  GRC_MODE_NO_TX_PHDR_CSUM |			  GRC_MODE_NO_RX_PHDR_CSUM);	tp->grc_mode |= GRC_MODE_HOST_SENDBDS;	if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)		tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;	if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)		tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;	tw32(GRC_MODE,	     tp->grc_mode |	     (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));	/* Setup the timer prescalar register.  Clock is always 66Mhz. */	val = tr32(GRC_MISC_CFG);	val &= ~0xff;	val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);	tw32(GRC_MISC_CFG, val);	/* Initialize MBUF/DESC pool. */	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {		/* Do nothing.  */	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);		else			tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);		tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);		tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);	}#if TG3_TSO_SUPPORT != 0	else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {		int fw_len;		fw_len = (TG3_TSO5_FW_TEXT_LEN +			  TG3_TSO5_FW_RODATA_LEN +			  TG3_TSO5_FW_DATA_LEN +			  TG3_TSO5_FW_SBSS_LEN +			  TG3_TSO5_FW_BSS_LEN);		fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);		tw32(BUFMGR_MB_POOL_ADDR,		     NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);		tw32(BUFMGR_MB_POOL_SIZE,		     NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);	}#endif	if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {		tw32(BUFMGR_MB_RDMA_LOW_WATER,		     tp->bufmgr_config.mbuf_read_dma_low_water);		tw32(BUFMGR_MB_MACRX_LOW_WATER,		     tp->bufmgr_config.mbuf_mac_rx_low_water);		tw32(BUFMGR_MB_HIGH_WATER,		     tp->bufmgr_config.mbuf_high_water);	} else {		tw32(BUFMGR_MB_RDMA_LOW_WATER,		     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);		tw32(BUFMGR_MB_MACRX_LOW_WATER,		     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);		tw32(BUFMGR_MB_HIGH_WATER,		     tp->bufmgr_config.mbuf_high_water_jumbo);	}	tw32(BUFMGR_DMA_LOW_WATER,	     tp->bufmgr_config.dma_low_water);	tw32(BUFMGR_DMA_HIGH_WATER,	     tp->bufmgr_config.dma_high_water);	tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);	for (i = 0; i < 2000; i++) {		if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)			break;		udelay(10);	}	if (i >= 2000) {		printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",		       tp->dev->name);		return -ENODEV;	}	/* Setup replenish threshold. */	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);	/* Initialize TG3_BDINFO's at:	 *  RCVDBDI_STD_BD:	standard eth size rx ring	 *  RCVDBDI_JUMBO_BD:	jumbo frame rx ring	 *  RCVDBDI_MINI_BD:	small frame rx ring (??? does not work)	 *	 * like so:	 *  TG3_BDINFO_HOST_ADDR:	high/low parts of DMA address of ring	 *  TG3_BDINFO_MAXLEN_FLAGS:	(rx max buffer size << 16) |	 *                              ring attribute flags	 *  TG3_BDINFO_NIC_ADDR:	location of descriptors in nic SRAM	 *	 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.	 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.	 *	 * The size of each ring is fixed in the firmware, but the location is	 * configurable.	 */	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,	     ((u64) tp->rx_std_mapping >> 32));	tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,	     ((u64) tp->rx_std_mapping & 0xffffffff));	tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,	     NIC_SRAM_RX_BUFFER_DESC);	/* Don't even try to program the JUMBO/MINI buffer descriptor	 * configs on 5705.	 */	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,		     RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);	} else {		tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,		     RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);		tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,		     BDINFO_FLAGS_DISABLED);		/* Setup replenish threshold. */		tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);		if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,			     ((u64) tp->rx_jumbo_mapping >> 32));			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,			     ((u64) tp->rx_jumbo_mapping & 0xffffffff));			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,			     RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,			     NIC_SRAM_RX_JUMBO_BUFFER_DESC);		} else {			tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,			     BDINFO_FLAGS_DISABLED);		}	}	/* There is only one send ring on 5705/5750, no need to explicitly	 * disable the others.	 */	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {		/* Clear out send RCB ring in SRAM. */		for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,				      BDINFO_FLAGS_DISABLED);	}	tp->tx_prod = 0;	tp->tx_cons = 0;	tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);	tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);	tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,		       tp->tx_desc_mapping,		       (TG3_TX_RING_SIZE <<			BDINFO_FLAGS_MAXLEN_SHIFT),		       NIC_SRAM_TX_BUFFER_DESC);	/* There is only one receive return ring on 5705/5750, no need	 * to explicitly disable the others.	 */	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {		for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;		     i += TG3_BDINFO_SIZE) {			tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,				      BDINFO_FLAGS_DISABLED);		}	}	tp->rx_rcb_ptr = 0;	tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);	tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,		       tp->rx_rcb_mapping,		       (TG3_RX_RCB_RING_SIZE(tp) <<			BDINFO_FLAGS_MAXLEN_SHIFT),		       0);	tp->rx_std_ptr = tp->rx_pending;	tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,		     tp->rx_std_ptr);	tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?						tp->rx_jumbo_pending : 0;	tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,		     tp->rx_jumbo_ptr);	/* Initialize MAC address and backoff seed. */	__tg3_set_mac_addr(tp);	/* MTU + ethernet header + FCS + optional VLAN tag */	tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);	/* The slot time is changed by tg3_setup_phy if we	 * run at gigabit with half duplex.	 */	tw32(MAC_TX_LENGTHS,	     (2 << TX_LENGTHS_IPG_CRS_SHIFT) |	     (6 << TX_LENGTHS_IPG_SHIFT) |	     (32 << TX_LENGTHS_SLOT_TIME_SHIFT));	/* Receive rules. */	tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);	tw32(RCVLPC_CONFIG, 0x0181);	/* Calculate RDMAC_MODE setting early, we need it to determine	 * the RCVLPC_STATE_ENABLE mask.	 */	rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |		      RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |		      RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |		      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |		      RDMAC_MODE_LNGREAD_ENAB);	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {			rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;		} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&			   !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {			rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;		}	}#if TG3_TSO_SUPPORT != 0	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)		rdmac_mode |= (1 << 27);#endif	/* Receive/send statistics. */	if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&	    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {		val = tr32(RCVLPC_STATS_ENABLE);		val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;		tw32(RCVLPC_STATS_ENABLE, val);	} else {		tw32(RCVLPC_STATS_ENABLE, 0xffffff);	}	tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);	tw32(SNDDATAI_STATSENAB, 0xffffff);	tw32(SNDDATAI_STATSCTRL,	     (SNDDATAI_SCTRL_ENABLE |	      SNDDATAI_SCTRL_FASTUPD));	/* Setup host coalescing engine. */	tw32(HOSTCC_MODE, 0);	for (i = 0; i < 2000; i++) {		if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))			break;		udelay(10);	}	tw32(HOSTCC_RXCOL_TICKS, 0);	tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);	tw32(HOSTCC_RXMAX_FRAMES, 1);	tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {		tw32(HOSTCC_RXCOAL_TICK_INT, 0);		tw32(HOSTCC_TXCOAL_TICK_INT, 0);	}	tw32(HOSTCC_RXCOAL_MAXF_INT, 1);	tw32(HOSTCC_TXCOAL_MAXF_INT, 0);	/* set status block DMA address */	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,	     ((u64) tp->status_mapping >> 32));	tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,	     ((u64) tp->status_mapping & 0xffffffff));	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {		/* Status/statistics block address.  See tg3_timer,		 * the tg3_periodic_fetch_stats call there, and		 * tg3_get_stats to see how this works for 5705/5750 chips.		 */		tw32(HOSTCC_STAT_COAL_TICKS,		     DEFAULT_STAT_COAL_TICKS);		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,		     ((u64) tp->stats_mapping >> 32));		tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,		     ((u64) tp->stats_mapping & 0xffffffff));		tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);		tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);	}	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);	tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);	tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))		tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);	/* Clear statistics/status block in chip, and status block in ram. */	for (i = NIC_SRAM_STATS_BLK;	     i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;	     i += sizeof(u32)) {		tg3_write_mem(tp, i, 0);		udelay(40);	}	memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);	tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |		MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);	udelay(40);	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |				       GRC_LCLCTRL_GPIO_OUTPUT1);	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);	udelay(100);	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);	tr32(MAILBOX_INTERRUPT_0);	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {		tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);		udelay(40);	}	val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |	       WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |	       WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |	       WDMAC_MODE_LNGREAD_ENAB);	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {		if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {			/* nothing */		} else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&			   !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&			   !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {			val |= WDMAC_MODE_RX_ACCEL;		}	}	tw32_f(WDMAC_MODE, val);	udelay(40);	if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {		val = tr32(TG3PCI_X_CAPS);		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {			val &= ~PCIX_CAPS_BURST_MASK;			val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {			val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);			val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);			if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)				val |= (tp->split_mode_max_reqs <<					PCIX_CAPS_SPLIT_SHIFT);		}		tw32(TG3PCI_X_CAPS, val);	}	tw32_f(RDMAC_MODE, rdmac_mode);	udelay(40);	tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))		tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);	tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);	tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);	tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);	tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);	tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);#if TG3_TSO_SUPPORT != 0	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)		tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);#endif	tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);	tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);	if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {		err = tg3_load_5701_a0_firmware_fix(tp);		if (err)			return err;	}#if TG3_TSO_SUPPORT != 0	if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {		err = tg3_load_tso_firmware(tp);		if (err)			return err;	}#endif	tp->tx_mode = TX_MODE_ENABLE;	tw32_f(MAC_TX_MODE, tp->tx_mode);	udelay(100);	tp->rx_mode = RX_MODE_ENABLE;	tw32_f(MAC_RX_MODE, tp->rx_mode);	udelay(10);	if (tp->link_config.phy_is_low_power) {		tp->link_config.phy_is_low_power = 0;		tp->link_config.speed = tp->link_config.orig_speed;		tp->link_config.duplex = tp->link_config.orig_duplex;		tp->link_config.autoneg = tp->link_config.orig_autoneg;	}	tp->mi_mode = MAC_MI_MODE_BASE;	tw32_f(MAC_MI_MODE, tp->mi_mode);	udelay(80);	tw32(MAC_LED_CTRL, tp->led_ctrl);	tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {		tw32_f(MAC_RX_MODE, RX_MODE_RESET);		udelay(10);	}	tw32_f(MAC_RX_MODE, tp->rx_mode);	udelay(10);	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&			!(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {			/* Set drive transmission level to 1.2V  */			/* only if the signal pre-emphasis bit is not set  */			val = tr32(MAC_SERDES_CFG);			val &= 0xfffff000;			val |= 0x880;			tw32(MAC_SERDES_CFG, val);		}		if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)			tw32(MAC_SERDES_CFG, 0x616000);	}	/* Prevent chip from dropping frames when flow control	 * is enabled.	 */	tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&	    (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {		/* Use hardware link auto-negotiation */		tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;	}	err = tg3_setup_phy(tp, 1);	if (err)		return err;	if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {		u32 tmp;		/* Clear CRC stats. */		if (!tg3_readphy(tp, 0x1e, &tmp)) {			tg3_writephy(tp, 0x1e, tmp | 0x8000);			tg3_readphy(tp, 0x14, &tmp);		}	}	__tg3_set_rx_mode(tp->dev);	/* Initialize receive rules. */	tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);	tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)		limit = 8;	else		limit = 16;	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)		limit -= 4;	switch (limit) {	case 16:		tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);	case 15:		tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);	case 14:		tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);	case 13:		tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);	case 12:		tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);	case 11:		tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);	case 10:		tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);	case 9:		tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);	case 8:		tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);	case 7:		tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);	case 6:		tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);	case 5:		tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);	case 4:		/* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */	case 3:		/* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */	case 2:	case 1:	default:		break;	};	tg3_write_sig_post_reset(tp, RESET_KIND_INIT);	if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)		tg3_enable_ints(tp);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/85e94cedc44d1c2c1663b5b18f703ca5e7316e59/tg3.c/clean/drivers/net/tg3.c