void __devinit intel_p4_mcheck_init(struct cpuinfo_x86 *c) 
void intel_p4_mcheck_init(struct cpuinfo_x86 *c) 
void __devinit intel_p4_mcheck_init(struct cpuinfo_x86 *c){	u32 l, h;	int i;		machine_check_vector = intel_machine_check;	wmb();	printk (KERN_INFO "Intel machine check architecture supported.\n");	rdmsr (MSR_IA32_MCG_CAP, l, h);	if (l & (1<<8))	/* Control register present ? */		wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);	nr_mce_banks = l & 0xff;	for (i=0; i<nr_mce_banks; i++) {		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);	}	set_in_cr4 (X86_CR4_MCE);	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",		smp_processor_id());	/* Check for P4/Xeon extended MCE MSRs */	rdmsr (MSR_IA32_MCG_CAP, l, h);	if (l & (1<<9))	{/* MCG_EXT_P */		mce_num_extended_msrs = (l >> 16) & 0xff;		printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"				" available\n",			smp_processor_id(), mce_num_extended_msrs);#ifdef CONFIG_X86_MCE_P4THERMAL		/* Check for P4/Xeon Thermal monitor */		intel_init_thermal(c);#endif	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/31ab269a0307d8725737dfbbdeb5dcde7b41bc36/p4.c/clean/arch/i386/kernel/cpu/mcheck/p4.c