#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) write_c0_entrylo0(ptep->pte_high); ptep++; write_c0_entrylo1(ptep->pte_high); 
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) write_c0_entrylo0(ptep->pte_high); ptep++; write_c0_entrylo1(ptep->pte_high); 
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte){	unsigned long flags;	pgd_t *pgdp;	pmd_t *pmdp;	pte_t *ptep;	int idx, pid;	/*	 * Handle debugger faulting in for debugee.	 */	if (current->active_mm != vma->vm_mm)		return;	pid = read_c0_entryhi() & ASID_MASK;	local_irq_save(flags);	address &= (PAGE_MASK << 1);	write_c0_entryhi(address | pid);	pgdp = pgd_offset(vma->vm_mm, address);	mtc0_tlbw_hazard();	tlb_probe();	BARRIER;	pmdp = pmd_offset(pgdp, address);	idx = read_c0_index();	ptep = pte_offset_map(pmdp, address); #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 	write_c0_entrylo0(ptep->pte_high); 	ptep++; 	write_c0_entrylo1(ptep->pte_high);#else  	write_c0_entrylo0(pte_val(*ptep++) >> 6);  	write_c0_entrylo1(pte_val(*ptep) >> 6);#endif	write_c0_entryhi(address | pid);	mtc0_tlbw_hazard();	if (idx < 0)		tlb_write_random();	else		tlb_write_indexed();	tlbw_use_hazard();	write_c0_entryhi(pid);	local_irq_restore(flags);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/304429915dad26ccf212d63ea1f18be36e3188e2/tlb-r4k.c/clean/arch/mips/mm/tlb-r4k.c