if ((tp->nvram_jedecnum == JEDEC_ST) && (nvram_cmd & NVRAM_CMD_FIRST)) { 
if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) && (tp->nvram_jedecnum == JEDEC_ST) && (nvram_cmd & NVRAM_CMD_FIRST)) { 
static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,		u8 *buf){	int i, ret = 0;	for (i = 0; i < len; i += 4, offset += 4) {		u32 data, page_off, phy_addr, nvram_cmd;		memcpy(&data, buf + i, 4);		tw32(NVRAM_WRDATA, cpu_to_be32(data));	        page_off = offset % tp->nvram_pagesize;		if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&			(tp->nvram_jedecnum == JEDEC_ATMEL)) {			phy_addr = ((offset / tp->nvram_pagesize) <<				    ATMEL_AT45DB0X1B_PAGE_POS) + page_off;		}		else {			phy_addr = offset;		}		tw32(NVRAM_ADDR, phy_addr);		nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;	        if ((page_off == 0) || (i == 0))			nvram_cmd |= NVRAM_CMD_FIRST;		else if (page_off == (tp->nvram_pagesize - 4))			nvram_cmd |= NVRAM_CMD_LAST;		if (i == (len - 4))			nvram_cmd |= NVRAM_CMD_LAST;		if ((tp->nvram_jedecnum == JEDEC_ST) &&			(nvram_cmd & NVRAM_CMD_FIRST)) {			if ((ret = tg3_nvram_exec_cmd(tp,				NVRAM_CMD_WREN | NVRAM_CMD_GO |				NVRAM_CMD_DONE)))				break;		}		if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {			/* We always do complete word writes to eeprom. */			nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);		}		if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))			break;	}	return ret;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/4c98748763ce25c5394a7edd686d92c70b4fac38/tg3.c/clean/drivers/net/tg3.c