outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B); 
outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); 
static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs){	u8 ctrl;	IRDA_DEBUG(3, "%s\n", __FUNCTION__);#if 1	/* Disable Rx */	register_bank(iobase, 0);	outb(0x00, iobase+IRCC_LCR_B);#endif	register_bank(iobase, 1);	outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,	     iobase+IRCC_SCE_CFGB);	self->io.direction = IO_XMIT;	/* Set BOF additional count for generating the min turn time */	register_bank(iobase, 4);	outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO);	ctrl = inb(iobase+IRCC_CONTROL) & 0xf0;	outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI);	/* Set max Tx frame size */	outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI);	outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO);	/*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/	/* Enable burst mode chip Tx DMA */	register_bank(iobase, 1);	outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |	     IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);	/* Setup DMA controller (must be done after enabling chip DMA) */	irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,		       DMA_TX_MODE);	/* Enable interrupt */	register_bank(iobase, 0);	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);	outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);	/* Enable transmit */	outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/98b7777331d4344821e900040da5d1d3016d9e67/smsc-ircc2.c/clean/drivers/net/irda/smsc-ircc2.c