XENA_dev_config_t __iomem *bar0 = nic->bar0; 
XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; 
int s2io_enable_msi(nic_t *nic){	XENA_dev_config_t __iomem *bar0 = nic->bar0;	u16 msi_ctrl, msg_val;	struct config_param *config = &nic->config;	struct net_device *dev = nic->dev;	u64 val64, tx_mat, rx_mat;	int i, err;	val64 = readq(&bar0->pic_control);	val64 &= ~BIT(1);	writeq(val64, &bar0->pic_control);	err = pci_enable_msi(nic->pdev);	if (err) {		DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",			  nic->dev->name);		return err;	}	/*	 * Enable MSI and use MSI-1 in stead of the standard MSI-0	 * for interrupt handling.	 */	pci_read_config_word(nic->pdev, 0x4c, &msg_val);	msg_val ^= 0x1;	pci_write_config_word(nic->pdev, 0x4c, msg_val);	pci_read_config_word(nic->pdev, 0x4c, &msg_val);	pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);	msi_ctrl |= 0x10;	pci_write_config_word(nic->pdev, 0x42, msi_ctrl);	/* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */	tx_mat = readq(&bar0->tx_mat0_n[0]);	for (i=0; i<config->tx_fifo_num; i++) {		tx_mat |= TX_MAT_SET(i, 1);	}	writeq(tx_mat, &bar0->tx_mat0_n[0]);	rx_mat = readq(&bar0->rx_mat);	for (i=0; i<config->rx_ring_num; i++) {		rx_mat |= RX_MAT_SET(i, 1);	}	writeq(rx_mat, &bar0->rx_mat);	dev->irq = nic->pdev->irq;	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/da6971d8ece2ec9762509e20dda6808335b5a10b/s2io.c/clean/drivers/net/s2io.c