temp_word = 0x00L; rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word); 
rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00); 
configure_new_function(struct controller *ctrl, struct pci_func *func,		u8 behind_bridge, struct resource_lists *resources,		u8 bridge_bus, u8 bridge_dev){	int cloop;	u8 temp_byte;	u8 class_code;	u16 temp_word;	u32 rc;	u32 temp_register;	u32 base;	unsigned int devfn;	struct pci_resource *mem_node;	struct pci_resource *io_node;	struct pci_bus lpci_bus, *pci_bus;	memcpy(&lpci_bus, ctrl->pci_dev->subordinate, sizeof(lpci_bus));	pci_bus = &lpci_bus;	pci_bus->number = func->bus;	devfn = PCI_DEVFN(func->device, func->function);	/* Check for Bridge */	rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &temp_byte);	if (rc)		return rc;	dbg("%s: bus %x dev %x func %x temp_byte = %x\n", __FUNCTION__,		func->bus, func->device, func->function, temp_byte);	if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { /* PCI-PCI Bridge */		rc = configure_new_bridge(ctrl, func, behind_bridge, resources,						pci_bus);		if (rc)			return rc;	} else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {		/* Standard device */		u64	base64;		rc = pci_bus_read_config_byte(pci_bus, devfn, 0x0B, &class_code);		if (class_code == PCI_BASE_CLASS_DISPLAY)			return DEVICE_TYPE_NOT_SUPPORTED;		/* Figure out IO and memory needs */		for (cloop = PCI_BASE_ADDRESS_0; cloop <= PCI_BASE_ADDRESS_5; cloop += 4) {			temp_register = 0xFFFFFFFF;			rc = pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);			rc = pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp_register);			dbg("Bar[%x]=0x%x on bus:dev:func(0x%x:%x:%x)\n", cloop, temp_register, 				func->bus, func->device, func->function);			if (!temp_register)				continue;			base64 = 0L;			if (temp_register & PCI_BASE_ADDRESS_SPACE_IO) {				/* Map IO */				/* set base = amount of IO space */				base = temp_register & 0xFFFFFFFC;				base = ~base + 1;				dbg("NEED IO length(0x%x)\n", base);				io_node = get_io_resource(&(resources->io_head),(ulong)base);				/* allocate the resource to the board */				if (io_node) {					dbg("Got IO base=0x%x(length=0x%x)\n", io_node->base, io_node->length);					base = (u32)io_node->base;					io_node->next = func->io_head;					func->io_head = io_node;				} else {					err("Got NO IO resource(length=0x%x)\n", base);					return -ENOMEM;				}			} else {	/* map MEM */				int prefetchable = 1;				struct pci_resource **res_node = &func->p_mem_head;				char *res_type_str = "PMEM";				u32	temp_register2;				if (!(temp_register & PCI_BASE_ADDRESS_MEM_PREFETCH)) {					prefetchable = 0;					res_node = &func->mem_head;					res_type_str++;				}				base = temp_register & 0xFFFFFFF0;				base = ~base + 1;				switch (temp_register & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {				case PCI_BASE_ADDRESS_MEM_TYPE_32:					dbg("NEED 32 %s bar=0x%x(length=0x%x)\n", res_type_str, temp_register, base);					if (prefetchable && resources->p_mem_head)						mem_node=get_resource(&(resources->p_mem_head), (ulong)base);					else {						if (prefetchable)							dbg("using MEM for PMEM\n");						mem_node = get_resource(&(resources->mem_head), (ulong)base);					}					/* allocate the resource to the board */					if (mem_node) {						base = (u32)mem_node->base; 						mem_node->next = *res_node;						*res_node = mem_node;						dbg("Got 32 %s base=0x%x(length=0x%x)\n", res_type_str, mem_node->base, 							mem_node->length);					} else {						err("Got NO 32 %s resource(length=0x%x)\n", res_type_str, base);						return -ENOMEM;					}					break;				case PCI_BASE_ADDRESS_MEM_TYPE_64:					rc = pci_bus_read_config_dword(pci_bus, devfn, cloop+4, &temp_register2);					dbg("NEED 64 %s bar=0x%x:%x(length=0x%x)\n", res_type_str, temp_register2, 						temp_register, base);					if (prefetchable && resources->p_mem_head)						mem_node = get_resource(&(resources->p_mem_head), (ulong)base);					else {						if (prefetchable)							dbg("using MEM for PMEM\n");						mem_node = get_resource(&(resources->mem_head), (ulong)base);					}					/* allocate the resource to the board */					if (mem_node) {						base64 = mem_node->base; 						mem_node->next = *res_node;						*res_node = mem_node;						dbg("Got 64 %s base=0x%x:%x(length=%x)\n", res_type_str, (u32)(base64 >> 32), 							(u32)base64, mem_node->length);					} else {						err("Got NO 64 %s resource(length=0x%x)\n", res_type_str, base);						return -ENOMEM;					}					break;				default:					dbg("reserved BAR type=0x%x\n", temp_register);					break;				}			}			if (base64) {				rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);				cloop += 4;				base64 >>= 32;				if (base64) {					dbg("%s: high dword of base64(0x%x) set to 0\n", __FUNCTION__, (u32)base64);					base64 = 0x0L;				}				rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, (u32)base64);			} else {				rc = pci_bus_write_config_dword(pci_bus, devfn, cloop, base);			}		}		/* End of base register loop */		/* disable ROM base Address */		temp_word = 0x00L;		rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word);		/* Set HP parameters (Cache Line Size, Latency Timer) */		rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);		if (rc)			return rc;		pciehprm_enable_card(ctrl, func, PCI_HEADER_TYPE_NORMAL);		dbg("PCI function Hot-Added s:b:d:f(%02x:%02x:%02x:%02x)\n", ctrl->seg, func->bus, func->device, 			func->function);	}  /* End of Not-A-Bridge else */	else {		/* It's some strange type of PCI adapter (Cardbus?) */		return DEVICE_TYPE_NOT_SUPPORTED;	}	func->configured = 1;	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/c2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5/pciehp_ctrl.c/clean/drivers/pci/hotplug/pciehp_ctrl.c