spin_lock_init(&ohci->event_lock);  /* * interrupts are disabled, all right, but... due to SA_SHIRQ we * might get called anyway.  We'll see no event, of course, but * we need to get to that "no event", so enough should be initialized * by that point. */ 
static int __devinit ohci1394_pci_probe(struct pci_dev *dev,					const struct pci_device_id *ent){	static int version_printed = 0;	struct hpsb_host *host;	struct ti_ohci *ohci;	/* shortcut to currently handled device */	unsigned long ohci_base;	if (version_printed++ == 0)		PRINT_G(KERN_INFO, "%s", version);        if (pci_enable_device(dev))		FAIL(-ENXIO, "Failed to enable OHCI hardware");        pci_set_master(dev);	host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev);	if (!host) FAIL(-ENOMEM, "Failed to allocate host structure");	ohci = host->hostdata;	ohci->dev = dev;	ohci->host = host;	ohci->init_state = OHCI_INIT_ALLOC_HOST;	host->pdev = dev;	pci_set_drvdata(dev, ohci);	/* We don't want hardware swapping */	pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);	/* Some oddball Apple controllers do not order the selfid	 * properly, so we make up for it here.  */#ifndef __LITTLE_ENDIAN	/* XXX: Need a better way to check this. I'm wondering if we can	 * read the values of the OHCI1394_PCI_HCI_Control and the	 * noByteSwapData registers to see if they were not cleared to	 * zero. Should this work? Obviously it's not defined what these	 * registers will read when they aren't supported. Bleh! */	if (dev->vendor == PCI_VENDOR_ID_APPLE &&	    dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) {		ohci->no_swap_incoming = 1;		ohci->selfid_swap = 0;	} else		ohci->selfid_swap = 1;#endif#ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW#define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e#endif	/* These chipsets require a bit of extra care when checking after	 * a busreset.  */	if ((dev->vendor == PCI_VENDOR_ID_APPLE &&	     dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) ||	    (dev->vendor ==  PCI_VENDOR_ID_NVIDIA &&	     dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW))		ohci->check_busreset = 1;	/* We hardwire the MMIO length, since some CardBus adaptors	 * fail to report the right length.  Anyway, the ohci spec	 * clearly says it's 2kb, so this shouldn't be a problem. */	ohci_base = pci_resource_start(dev, 0);	if (pci_resource_len(dev, 0) != OHCI1394_REGISTER_SIZE)		PRINT(KERN_WARNING, "Unexpected PCI resource length of %lx!",		      pci_resource_len(dev, 0));	/* Seems PCMCIA handles this internally. Not sure why. Seems	 * pretty bogus to force a driver to special case this.  */#ifndef PCMCIA	if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))		FAIL(-ENOMEM, "MMIO resource (0x%lx - 0x%lx) unavailable",		     ohci_base, ohci_base + OHCI1394_REGISTER_SIZE);#endif	ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;	ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE);	if (ohci->registers == NULL)		FAIL(-ENXIO, "Failed to remap registers - card not accessible");	ohci->init_state = OHCI_INIT_HAVE_IOMAPPING;	DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers);	/* csr_config rom allocation */	ohci->csr_config_rom_cpu =		pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,				     &ohci->csr_config_rom_bus);	OHCI_DMA_ALLOC("consistent csr_config_rom");	if (ohci->csr_config_rom_cpu == NULL)		FAIL(-ENOMEM, "Failed to allocate buffer config rom");	ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER;	/* self-id dma buffer allocation */	ohci->selfid_buf_cpu =		pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,                      &ohci->selfid_buf_bus);	OHCI_DMA_ALLOC("consistent selfid_buf");	if (ohci->selfid_buf_cpu == NULL)		FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets");	ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER;	if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)		PRINT(KERN_INFO, "SelfID buffer %p is not aligned on "		      "8Kb boundary... may cause problems on some CXD3222 chip",		      ohci->selfid_buf_cpu);	/* No self-id errors at startup */	ohci->self_id_errors = 0;	ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE;	/* AR DMA request context allocation */	if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context,			      DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC,			      AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,			      OHCI1394_AsReqRcvContextBase) < 0)		FAIL(-ENOMEM, "Failed to allocate AR Req context");	/* AR DMA response context allocation */	if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context,			      DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC,			      AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,			      OHCI1394_AsRspRcvContextBase) < 0)		FAIL(-ENOMEM, "Failed to allocate AR Resp context");	/* AT DMA request context */	if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context,			      DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC,			      OHCI1394_AsReqTrContextBase) < 0)		FAIL(-ENOMEM, "Failed to allocate AT Req context");	/* AT DMA response context */	if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context,			      DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC,			      OHCI1394_AsRspTrContextBase) < 0)		FAIL(-ENOMEM, "Failed to allocate AT Resp context");	/* Start off with a soft reset, to clear everything to a sane	 * state. */	ohci_soft_reset(ohci);	/* Now enable LPS, which we need in order to start accessing	 * most of the registers.  In fact, on some cards (ALI M5251),	 * accessing registers in the SClk domain without LPS enabled	 * will lock up the machine.  Wait 50msec to make sure we have	 * full link enabled.  */	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);	/* Disable and clear interrupts */	reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);	reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);	mdelay(50);	/* Determine the number of available IR and IT contexts. */	ohci->nb_iso_rcv_ctx =		get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);	DBGMSG("%d iso receive contexts available",	       ohci->nb_iso_rcv_ctx);	ohci->nb_iso_xmit_ctx =		get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);	DBGMSG("%d iso transmit contexts available",	       ohci->nb_iso_xmit_ctx);	/* Set the usage bits for non-existent contexts so they can't	 * be allocated */	ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx;	ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx;	INIT_LIST_HEAD(&ohci->iso_tasklet_list);	spin_lock_init(&ohci->iso_tasklet_list_lock);	ohci->ISO_channel_usage = 0;        spin_lock_init(&ohci->IR_channel_lock);	/* Allocate the IR DMA context right here so we don't have	 * to do it in interrupt path - note that this doesn't	 * waste much memory and avoids the jugglery required to	 * allocate it in IRQ path. */	if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context,			      DMA_CTX_ISO, 0, IR_NUM_DESC,			      IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,			      OHCI1394_IsoRcvContextBase) < 0) {		FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context");	}	/* We hopefully don't have to pre-allocate IT DMA like we did	 * for IR DMA above. Allocate it on-demand and mark inactive. */	ohci->it_legacy_context.ohci = NULL;	if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,			 OHCI1394_DRIVER_NAME, ohci))		FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);	ohci->init_state = OHCI_INIT_HAVE_IRQ;	ohci_initialize(ohci);	/* Set certain csr values */	host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi);	host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo);	host->csr.cyc_clk_acc = 100;  /* how do we determine clk accuracy? */	host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;	host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;	/* Tell the highlevel this host is ready */	if (hpsb_add_host(host))		FAIL(-ENOMEM, "Failed to register host with highlevel");	ohci->init_state = OHCI_INIT_DONE;	return 0;#undef FAIL}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3515d0161d55d2fa1a340932625f94240a68c262/ohci1394.c/clean/drivers/ieee1394/ohci1394.c