if (!bus->self) { /* Root bus */ if (is_python(dn)) { unsigned int *iohole; 
while (pci->phb->dma_window_size * children > 0x80000000ul) pci->phb->dma_window_size >>= 1; DBG("No ISA/IDE, window size is %x\n", pci->phb->dma_window_size); pci->phb->dma_window_base_cur = 0; 
static void iommu_bus_setup_pSeries(struct pci_bus *bus){	struct device_node *dn, *pdn;	struct pci_dn *pci;	struct iommu_table *tbl;	DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self);	/* For each (root) bus, we carve up the available DMA space in 256MB	 * pieces. Since each piece is used by one (sub) bus/device, that would	 * give a maximum of 7 devices per PHB. In most cases, this is plenty.	 *	 * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS	 * bridges below the PHB to allocate the sectioned tables to, so instead	 * we allocate a 1GB table at the PHB level.	 */	dn = pci_bus_to_OF_node(bus);	pci = dn->data;	if (!bus->self) {		/* Root bus */		if (is_python(dn)) {			unsigned int *iohole;			DBG("Python root bus %s\n", bus->name);			iohole = (unsigned int *)get_property(dn, "io-hole", 0);			if (iohole) {				/* On first bus we need to leave room for the				 * ISA address space. Just skip the first 256MB				 * alltogether. This leaves 768MB for the window.				 */				DBG("PHB has io-hole, reserving 256MB\n");				pci->phb->dma_window_size = 3 << 28;				pci->phb->dma_window_base_cur = 1 << 28;			} else {				/* 1GB window by default */				pci->phb->dma_window_size = 1 << 30;				pci->phb->dma_window_base_cur = 0;			}			tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);			iommu_table_setparms(pci->phb, dn, tbl);			pci->iommu_table = iommu_init_table(tbl);		} else {			/* Do a 128MB table at root. This is used for the IDE			 * controller on some SMP-mode POWER4 machines. It			 * doesn't hurt to allocate it on other machines			 * -- it'll just be unused since new tables are			 * allocated on the EADS level.			 *			 * Allocate at offset 128MB to avoid having to deal			 * with ISA holes; 128MB table for IDE is plenty.			 */			pci->phb->dma_window_size = 1 << 27;			pci->phb->dma_window_base_cur = 1 << 27;			tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);			iommu_table_setparms(pci->phb, dn, tbl);			pci->iommu_table = iommu_init_table(tbl);			/* All child buses have 256MB tables */			pci->phb->dma_window_size = 1 << 28;		}	} else {		pdn = pci_bus_to_OF_node(bus->parent);		if (!bus->parent->self && !is_python(pdn)) {			struct iommu_table *tbl;			/* First child and not python means this is the EADS			 * level. Allocate new table for this slot with 256MB			 * window.			 */			tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL);			iommu_table_setparms(pci->phb, dn, tbl);			pci->iommu_table = iommu_init_table(tbl);		} else {			/* Lower than first child or under python, use parent table */			pci->iommu_table = PCI_DN(pdn)->iommu_table;		}	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/3c2822ccb1f8cc96fc006aa82e68e1944290014a/pSeries_iommu.c/clean/arch/ppc64/kernel/pSeries_iommu.c