pgd_t* pgd = (pgd_t*)current_pgd; 
pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id()); 
handle_mmu_bus_fault(struct pt_regs *regs){	int cause;	int select;#ifdef DEBUG	int index;	int page_id;	int acc, inv;#endif	pgd_t* pgd = (pgd_t*)current_pgd;	pmd_t *pmd;	pte_t pte;	int miss, we, writeac;	unsigned long address;	unsigned long flags;	cause = *R_MMU_CAUSE;	address = cause & PAGE_MASK; /* get faulting address */	select = *R_TLB_SELECT;#ifdef DEBUG	page_id = IO_EXTRACT(R_MMU_CAUSE,  page_id,   cause);	acc     = IO_EXTRACT(R_MMU_CAUSE,  acc_excp,  cause);	inv     = IO_EXTRACT(R_MMU_CAUSE,  inv_excp,  cause);  	index   = IO_EXTRACT(R_TLB_SELECT, index,     select);#endif	miss    = IO_EXTRACT(R_MMU_CAUSE,  miss_excp, cause);	we      = IO_EXTRACT(R_MMU_CAUSE,  we_excp,   cause);	writeac = IO_EXTRACT(R_MMU_CAUSE,  wr_rd,     cause);	D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",		 regs->irp, address, miss, inv, we, acc, index, page_id));	/* leave it to the MM system fault handler */	if (miss)		do_page_fault(address, regs, 0, writeac);        else		do_page_fault(address, regs, 1, we);        /* Reload TLB with new entry to avoid an extra miss exception.	 * do_page_fault may have flushed the TLB so we have to restore	 * the MMU registers.	 */	local_save_flags(flags);	local_irq_disable();	pmd = (pmd_t *)(pgd + pgd_index(address));	if (pmd_none(*pmd))		return;	pte = *pte_offset_kernel(pmd, address);	if (!pte_present(pte))		return;	*R_TLB_SELECT = select;	*R_TLB_HI = cause;	*R_TLB_LO = pte_val(pte);	local_irq_restore(flags);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/8d20a541b089ecb67a88a673548161b686ed7b85/fault.c/buggy/arch/cris/arch-v10/mm/fault.c