/* force FDC ops in io_pdir_entry() to be visible to IOMMU */ if (ioc_needs_fdc) asm volatile("sync" : : );  
sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,	   enum dma_data_direction direction){	struct ioc *ioc;	int coalesced, filled = 0;	unsigned long flags;	DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);	ioc = GET_IOC(dev);	/* Fast path single entry scatterlists. */	if (nents == 1) {		sg_dma_address(sglist) = sba_map_single(dev,						(void *)sg_virt_addr(sglist),						sglist->length, direction);		sg_dma_len(sglist)     = sglist->length;		return 1;	}	spin_lock_irqsave(&ioc->res_lock, flags);#ifdef ASSERT_PDIR_SANITY	if (sba_check_pdir(ioc,"Check before sba_map_sg()"))	{		sba_dump_sg(ioc, sglist, nents);		panic("Check before sba_map_sg()");	}#endif#ifdef SBA_COLLECT_STATS	ioc->msg_calls++;#endif	/*	** First coalesce the chunks and allocate I/O pdir space	**	** If this is one DMA stream, we can properly map using the	** correct virtual address associated with each DMA page.	** w/o this association, we wouldn't have coherent DMA!	** Access to the virtual address is what forces a two pass algorithm.	*/	coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);	/*	** Program the I/O Pdir	**	** map the virtual addresses to the I/O Pdir	** o dma_address will contain the pdir index	** o dma_len will contain the number of bytes to map 	** o address contains the virtual address.	*/	filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);#ifdef ASSERT_PDIR_SANITY	if (sba_check_pdir(ioc,"Check after sba_map_sg()"))	{		sba_dump_sg(ioc, sglist, nents);		panic("Check after sba_map_sg()\n");	}#endif	spin_unlock_irqrestore(&ioc->res_lock, flags);	DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);	return filled;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/64908ad95c34f25849412d6d4735ac10f8fb6575/sba_iommu.c/buggy/drivers/parisc/sba_iommu.c