#ifdef CONFIG_ARCH_OMAP1510 
#ifdef CONFIG_ARCH_OMAP15XX 
void __init omap_init_irq(void){	int i, j;#ifdef CONFIG_ARCH_OMAP730	if (cpu_is_omap730()) {		irq_banks = omap730_irq_banks;		irq_bank_count = ARRAY_SIZE(omap730_irq_banks);	}#endif#ifdef CONFIG_ARCH_OMAP1510	if (cpu_is_omap1510()) {		irq_banks = omap1510_irq_banks;		irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);	}#endif#if defined(CONFIG_ARCH_OMAP16XX)	if (cpu_is_omap16xx()) {		irq_banks = omap1610_irq_banks;		irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);	}#endif	printk("Total of %i interrupts in %i interrupt banks\n",	       irq_bank_count * 32, irq_bank_count);	/* Mask and clear all interrupts */	for (i = 0; i < irq_bank_count; i++) {		irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);		irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);	}	/* Clear any pending interrupts */	irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);	irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);	/* Enable interrupts in global mask */	if (cpu_is_omap730()) {		irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);	}	/* Install the interrupt handlers for each bank */	for (i = 0; i < irq_bank_count; i++) {		for (j = i * 32; j < (i + 1) * 32; j++) {			int irq_trigger;			irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);			omap_irq_set_cfg(j, 0, 0, irq_trigger);			set_irq_chip(j, &omap_irq_chip);			set_irq_handler(j, do_level_IRQ);			set_irq_flags(j, IRQF_VALID);		}	}	/* Unmask level 2 handler */	if (cpu_is_omap730()) {		omap_unmask_irq(INT_730_IH2_IRQ);	} else {		omap_unmask_irq(INT_IH2_IRQ);	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/3179a019391f0f8081245fd564a5f1be308ba64f/irq.c/clean/arch/arm/mach-omap1/irq.c