VPRINTK("EXIT\n"); 
 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);  pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;  printk("EXIT\n"); 
static void mv_phy_reset(struct ata_port *ap){	void __iomem *port_mmio = mv_ap_base(ap);	struct ata_taskfile tf;	struct ata_device *dev = &ap->device[0];	unsigned long timeout;	VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);	mv_stop_dma(ap);	writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);	udelay(25);		/* allow reset propagation */	/* Spec never mentions clearing the bit.  Marvell's driver does	 * clear the bit, however.	 */	writelfl(0, port_mmio + EDMA_CMD_OFS);	VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "		"SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),		mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));	/* proceed to init communications via the scr_control reg */	scr_write_flush(ap, SCR_CONTROL, 0x301);	mdelay(1);	scr_write_flush(ap, SCR_CONTROL, 0x300);	timeout = jiffies + (HZ * 1);	do {		mdelay(10);		if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)			break;	} while (time_before(jiffies, timeout));	VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "		"SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),		mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));	if (sata_dev_present(ap)) {		ata_port_probe(ap);	} else {		printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",		       ap->id, scr_read(ap, SCR_STATUS));		ata_port_disable(ap);		return;	}	ap->cbl = ATA_CBL_SATA;	tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);	tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);	tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);	tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);	dev->class = ata_dev_classify(&tf);	if (!ata_dev_present(dev)) {		VPRINTK("Port disabled post-sig: No device present.\n");		ata_port_disable(ap);	}	VPRINTK("EXIT\n");}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/095fec887eaa1c38d17c0c929a6733c744a9fa1f/sata_mv.c/buggy/drivers/scsi/sata_mv.c