pdc20621_put_to_dimm(pe, (void *) &tmp, addr, 
pdc20621_put_to_dimm(pe, (void *) &tmp, addr, 
static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe){	int speed, size, length; 	u32 addr,spd0,pci_status;	u32 tmp=0;	u32 time_period=0;	u32 tcount=0;	u32 ticks=0;	u32 clock=0;	u32 fparam=0;   	void *mmio = pe->mmio_base;	/* hard-code chip #0 */   	mmio += PDC_CHIP0_OFS;	/* Initialize PLL based upon PCI Bus Frequency */	/* Initialize Time Period Register */	writel(0xffffffff, mmio + PDC_TIME_PERIOD);	time_period = readl(mmio + PDC_TIME_PERIOD);	VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);	/* Enable timer */	writel(0x00001a0, mmio + PDC_TIME_CONTROL);	readl(mmio + PDC_TIME_CONTROL);	/* Wait 3 seconds */	msleep(3000);	/* 	   When timer is enabled, counter is decreased every internal	   clock cycle.	*/	tcount = readl(mmio + PDC_TIME_COUNTER);	VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);	/* 	   If SX4 is on PCI-X bus, after 3 seconds, the timer counter	   register should be >= (0xffffffff - 3x10^8).	*/	if(tcount >= PCI_X_TCOUNT) {		ticks = (time_period - tcount);		VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);			clock = (ticks / 300000);		VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);				clock = (clock * 33);		VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);		/* PLL F Param (bit 22:16) */		fparam = (1400000 / clock) - 2;		VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);				/* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */		pci_status = (0x8a001824 | (fparam << 16));	} else		pci_status = PCI_PLL_INIT;	/* Initialize PLL. */	VPRINTK("pci_status: 0x%x\n", pci_status);	writel(pci_status, mmio + PDC_CTL_STATUS);	readl(mmio + PDC_CTL_STATUS);	/* 	   Read SPD of DIMM by I2C interface,	   and program the DIMM Module Controller.	*/ 	if (!(speed = pdc20621_detect_dimm(pe))) {		printk(KERN_ERR "Detect Local DIMM Fail\n");  		return 1;	/* DIMM error */   	}   	VPRINTK("Local DIMM Speed = %d\n", speed);   	/* Programming DIMM0 Module Control Register (index_CID0:80h) */    	size = pdc20621_prog_dimm0(pe);   	VPRINTK("Local DIMM Size = %dMB\n",size);   	/* Programming DIMM Module Global Control Register (index_CID0:88h) */    	if (pdc20621_prog_dimm_global(pe)) {		printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");		return 1;   	}#ifdef ATA_VERBOSE_DEBUG	{		u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',  				'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ', 				 '1','.','1','0',  				'9','8','0','3','1','6','1','2',0,0};		u8 test_parttern2[40] = {0};		pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);		pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);		pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);		pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 		       test_parttern2[1], &(test_parttern2[2]));		pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040, 				       40);		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 		       test_parttern2[1], &(test_parttern2[2]));		pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);		pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);		printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 		       test_parttern2[1], &(test_parttern2[2]));	}#endif	/* ECC initiliazation. */	pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 			  PDC_DIMM_SPD_TYPE, &spd0);	if (spd0 == 0x02) {		VPRINTK("Start ECC initialization\n");		addr = 0;		length = size * 1024 * 1024;		while (addr < length) {			pdc20621_put_to_dimm(pe, (void *) &tmp, addr, 					     sizeof(u32));			addr += sizeof(u32);		}		VPRINTK("Finish ECC initialization\n");	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/8a60a07129fad60bba779a2a4038c7518b167fc7/sata_sx4.c/buggy/drivers/scsi/sata_sx4.c