GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 
GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 
static void sky2_mac_init(struct sky2_hw *hw, unsigned port){	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);	u16 reg;	int i;	const u8 *addr = hw->dev[port]->dev_addr;	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0	    && port == 1) {		/* WA DEV_472 -- looks like crossed wires on port 2 */		/* clear GMAC 1 Control reset */		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);		do {			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);	}	if (sky2->autoneg == AUTONEG_DISABLE) {		reg = gma_read16(hw, port, GM_GP_CTRL);		reg |= GM_GPCR_AU_ALL_DIS;		gma_write16(hw, port, GM_GP_CTRL, reg);		gma_read16(hw, port, GM_GP_CTRL);		switch (sky2->speed) {		case SPEED_1000:			reg |= GM_GPCR_SPEED_1000;			/* fallthru */		case SPEED_100:			reg |= GM_GPCR_SPEED_100;		}		if (sky2->duplex == DUPLEX_FULL)			reg |= GM_GPCR_DUP_FULL;	} else		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;	if (!sky2->tx_pause && !sky2->rx_pause) {		sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);		reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;	} else if (sky2->tx_pause &&!sky2->rx_pause) {		/* disable Rx flow-control */		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;	}	gma_write16(hw, port, GM_GP_CTRL, reg);	sky2_read16(hw, GMAC_IRQ_SRC);	spin_lock_bh(&hw->phy_lock);	sky2_phy_init(hw, port);	spin_unlock_bh(&hw->phy_lock);	/* MIB clear */	reg = gma_read16(hw, port, GM_PHY_ADDR);	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);	for (i = 0; i < GM_MIB_CNT_SIZE; i++)		gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);	gma_write16(hw, port, GM_PHY_ADDR, reg);	/* transmit control */	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));	/* receive control reg: unicast + multicast + no FCS  */	gma_write16(hw, port, GM_RX_CTRL,			 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);	/* transmit flow control */	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);	/* transmit parameter */	gma_write16(hw, port, GM_TX_PARAM,		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));	/* serial mode register */	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);	if (hw->dev[port]->mtu > 1500)		reg |= GM_SMOD_JUMBO_ENA;	gma_write16(hw, port, GM_SERIAL_MODE, reg);	/* physical address: used for pause frames */	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);	/* virtual address for data */	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);	/* enable interrupt mask for counter overflows */	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);	/* Configure Rx MAC FIFO */	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);	sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), 		     GMF_OPER_ON | GMF_RX_F_FL_ON);	reg = RX_FF_FL_DEF_MSK;	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)		reg = 0;	/* WA Dev #4115 */	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);	/* Set threshold to 0xa (64 bytes) 	 *  ASF disabled so no need to do WA dev #4.30 	 */	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);	/* Configure Tx MAC FIFO */	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);	/* Turn off Rx fifo flush (per sk98lin) */	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/793b883ed12a6ae6e2901ddb5e038b77d6f0c0ac/sky2.c/buggy/drivers/net/sky2.c