case 0: { 
case PCI_D0: { 
bnx2_set_power_state(struct bnx2 *bp, int state){	u16 pmcsr;	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);	switch (state) {	case 0: {		u32 val;		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,			(pmcsr & ~PCI_PM_CTRL_STATE_MASK) |			PCI_PM_CTRL_PME_STATUS);		if (pmcsr & PCI_PM_CTRL_STATE_MASK)			/* delay required during transition out of D3hot */			msleep(20);		val = REG_RD(bp, BNX2_EMAC_MODE);		val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;		val &= ~BNX2_EMAC_MODE_MPKT;		REG_WR(bp, BNX2_EMAC_MODE, val);		val = REG_RD(bp, BNX2_RPM_CONFIG);		val &= ~BNX2_RPM_CONFIG_ACPI_ENA;		REG_WR(bp, BNX2_RPM_CONFIG, val);		break;	}	case 3: {		int i;		u32 val, wol_msg;		if (bp->wol) {			u32 advertising;			u8 autoneg;			autoneg = bp->autoneg;			advertising = bp->advertising;			bp->autoneg = AUTONEG_SPEED;			bp->advertising = ADVERTISED_10baseT_Half |				ADVERTISED_10baseT_Full |				ADVERTISED_100baseT_Half |				ADVERTISED_100baseT_Full |				ADVERTISED_Autoneg;			bnx2_setup_copper_phy(bp);			bp->autoneg = autoneg;			bp->advertising = advertising;			bnx2_set_mac_addr(bp);			val = REG_RD(bp, BNX2_EMAC_MODE);			/* Enable port mode. */			val &= ~BNX2_EMAC_MODE_PORT;			val |= BNX2_EMAC_MODE_PORT_MII |			       BNX2_EMAC_MODE_MPKT_RCVD |			       BNX2_EMAC_MODE_ACPI_RCVD |			       BNX2_EMAC_MODE_FORCE_LINK |			       BNX2_EMAC_MODE_MPKT;			REG_WR(bp, BNX2_EMAC_MODE, val);			/* receive all multicast */			for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {				REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),				       0xffffffff);			}			REG_WR(bp, BNX2_EMAC_RX_MODE,			       BNX2_EMAC_RX_MODE_SORT_MODE);			val = 1 | BNX2_RPM_SORT_USER0_BC_EN |			      BNX2_RPM_SORT_USER0_MC_EN;			REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);			REG_WR(bp, BNX2_RPM_SORT_USER0, val);			REG_WR(bp, BNX2_RPM_SORT_USER0, val |			       BNX2_RPM_SORT_USER0_ENA);			/* Need to enable EMAC and RPM for WOL. */			REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,			       BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |			       BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |			       BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);			val = REG_RD(bp, BNX2_RPM_CONFIG);			val &= ~BNX2_RPM_CONFIG_ACPI_ENA;			REG_WR(bp, BNX2_RPM_CONFIG, val);			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;		}		else {			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;		}		bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||		    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {			if (bp->wol)				pmcsr |= 3;		}		else {			pmcsr |= 3;		}		if (bp->wol) {			pmcsr |= PCI_PM_CTRL_PME_ENABLE;		}		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,				      pmcsr);		/* No more memory access after this point until		 * device is brought back to D0.		 */		udelay(50);		break;	}	default:		return -EINVAL;	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/829ca9a30a2ddb727981d80fabdbff2ea86bc9ea/bnx2.c/clean/drivers/net/bnx2.c