 /* Disable port bandwidth limits by clearing MTU register */ mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); 
static void eth_port_start(struct mv643xx_private *mp){	unsigned int port_num = mp->port_num;	int tx_curr_desc, rx_curr_desc;	/* Assignment of Tx CTRP of given queue */	tx_curr_desc = mp->tx_curr_desc_q;	mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),		(u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));	/* Assignment of Rx CRDP of given queue */	rx_curr_desc = mp->rx_curr_desc_q;	mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),		(u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));	/* Add the assigned Ethernet address to the port's address table */	eth_port_uc_addr_set(port_num, mp->port_mac_addr);	/* Assign port configuration and command. */	mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);	mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),						mp->port_config_extend);	/* Increase the Rx side buffer size if supporting GigE */	if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)		mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),			(mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));	else		mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),						mp->port_serial_control);	mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),		mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |						MV643XX_ETH_SERIAL_PORT_ENABLE);	/* Assign port SDMA configuration */	mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),							mp->port_sdma_config);	/* Enable port Rx. */	mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),						mp->port_rx_queue_command);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/8f543718ea1c20795853bf065f1dcb510f210465/mv643xx_eth.c/clean/drivers/net/mv643xx_eth.c