mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2); 
mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x2000); mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 
struct mpic * __init mpic_alloc(unsigned long phys_addr,				unsigned int flags,				unsigned int isu_size,				unsigned int irq_offset,				unsigned int irq_count,				unsigned int ipi_offset,				unsigned char *senses,				unsigned int senses_count,				const char *name){	struct mpic	*mpic;	u32		reg;	const char	*vers;	int		i;	mpic = alloc_bootmem(sizeof(struct mpic));	if (mpic == NULL)		return NULL;		memset(mpic, 0, sizeof(struct mpic));	mpic->name = name;	mpic->hc_irq.typename = name;	mpic->hc_irq.enable = mpic_enable_irq;	mpic->hc_irq.disable = mpic_disable_irq;	mpic->hc_irq.end = mpic_end_irq;	if (flags & MPIC_PRIMARY)		mpic->hc_irq.set_affinity = mpic_set_affinity;#ifdef CONFIG_SMP	mpic->hc_ipi.typename = name;	mpic->hc_ipi.enable = mpic_enable_ipi;	mpic->hc_ipi.disable = mpic_disable_ipi;	mpic->hc_ipi.end = mpic_end_ipi;#endif /* CONFIG_SMP */	mpic->flags = flags;	mpic->isu_size = isu_size;	mpic->irq_offset = irq_offset;	mpic->irq_count = irq_count;	mpic->ipi_offset = ipi_offset;	mpic->num_sources = 0; /* so far */	mpic->senses = senses;	mpic->senses_count = senses_count;	/* Map the global registers */	mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);	mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2);	BUG_ON(mpic->gregs == NULL);	/* Reset */	if (flags & MPIC_WANTS_RESET) {		mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0,			   mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)			   | MPIC_GREG_GCONF_RESET);		while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0)		       & MPIC_GREG_GCONF_RESET)			mb();	}	/* Read feature register, calculate num CPUs and, for non-ISU	 * MPICs, num sources as well. On ISU MPICs, sources are counted	 * as ISUs are added	 */	reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0);	mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;	if (isu_size == 0)		mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)				     >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;	/* Map the per-CPU registers */	for (i = 0; i < mpic->num_cpus; i++) {		mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE +					   i * MPIC_CPU_STRIDE, 0x1000);		BUG_ON(mpic->cpuregs[i] == NULL);	}	/* Initialize main ISU if none provided */	if (mpic->isu_size == 0) {		mpic->isu_size = mpic->num_sources;		mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE,					MPIC_IRQ_STRIDE * mpic->isu_size);		BUG_ON(mpic->isus[0] == NULL);	}	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);	mpic->isu_mask = (1 << mpic->isu_shift) - 1;	/* Display version */	switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {	case 1:		vers = "1.0";		break;	case 2:		vers = "1.2";		break;	case 3:		vers = "1.3";		break;	default:		vers = "<unknown>";		break;	}	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",	       name, vers, phys_addr, mpic->num_cpus);	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,	       mpic->isu_shift, mpic->isu_mask);	mpic->next = mpics;	mpics = mpic;	if (flags & MPIC_PRIMARY)		mpic_primary = mpic;	return mpic;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/958d24df82e021704437da0789c47fcf581e4b85/mpic.c/clean/arch/ppc64/kernel/mpic.c