static void __init apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus) 
static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus) 
static void __init apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus){	struct pci_dev *pdev;	list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {		if (pdev->vendor == PCI_VENDOR_ID_SUN &&		    pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {			u32 word32;			u16 word16;			sabre_read_pci_cfg(pdev->bus, pdev->devfn,					   PCI_COMMAND, 2, &word32);			word16 = (u16) word32;			word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |				PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |				PCI_COMMAND_IO;			word32 = (u32) word16;			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_COMMAND, 2, word32);			/* Status register bits are "write 1 to clear". */			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_STATUS, 2, 0xffff);			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_SEC_STATUS, 2, 0xffff);			/* Use a primary/seconday latency timer value			 * of 64.			 */			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_LATENCY_TIMER, 1, 64);			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_SEC_LATENCY_TIMER, 1, 64);			/* Enable reporting/forwarding of master aborts,			 * parity, and SERR.			 */			sabre_write_pci_cfg(pdev->bus, pdev->devfn,					    PCI_BRIDGE_CONTROL, 1,					    (PCI_BRIDGE_CTL_PARITY |					     PCI_BRIDGE_CTL_SERR |					     PCI_BRIDGE_CTL_MASTER_ABORT));		}	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_sabre.c/buggy/arch/sparc64/kernel/pci_sabre.c