TRIGGER_LEVEL, SIGNAL_THROUGH); vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW); 
IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH); vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW); 
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin){	int irq = -1;	switch (slot) {	case 12:		vr41xx_set_irq_trigger(GD82559_1_PIN,				       TRIGGER_LEVEL,				       SIGNAL_THROUGH);		vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW);		irq = GD82559_1_IRQ;		break;	case 13:		vr41xx_set_irq_trigger(GD82559_2_PIN,				       TRIGGER_LEVEL,				       SIGNAL_THROUGH);		vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW);		irq = GD82559_2_IRQ;		break;	case 14:		switch (pin) {		case 1:			vr41xx_set_irq_trigger(UPD720100_INTA_PIN,					       TRIGGER_LEVEL,					       SIGNAL_THROUGH);			vr41xx_set_irq_level(UPD720100_INTA_PIN,					     LEVEL_LOW);			irq = UPD720100_INTA_IRQ;			break;		case 2:			vr41xx_set_irq_trigger(UPD720100_INTB_PIN,					       TRIGGER_LEVEL,					       SIGNAL_THROUGH);			vr41xx_set_irq_level(UPD720100_INTB_PIN,					     LEVEL_LOW);			irq = UPD720100_INTB_IRQ;			break;		case 3:			vr41xx_set_irq_trigger(UPD720100_INTC_PIN,					       TRIGGER_LEVEL,					       SIGNAL_THROUGH);			vr41xx_set_irq_level(UPD720100_INTC_PIN,					     LEVEL_LOW);			irq = UPD720100_INTC_IRQ;			break;		default:			break;		}		break;	default:		break;	}	return irq;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/43d2c4ca385b02ab7a604aa09a9da36f1668bee6/fixup-tb0226.c/clean/arch/mips/pci/fixup-tb0226.c