set_pp_bit(newpp, hptep); 
DBG_LOW(" -> hit\n"); /* Update the HPTE */ hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) | (newpp & (HPTE_R_PP | HPTE_R_N)); 
static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,				 unsigned long va, int large, int local){	hpte_t *hptep = htab_address + slot;	unsigned long hpte_v;	unsigned long avpn = va >> 23;	int ret = 0;	if (large)		avpn &= ~1;	native_lock_hpte(hptep);	hpte_v = hptep->v;	/* Even if we miss, we need to invalidate the TLB */	if ((HPTE_V_AVPN_VAL(hpte_v) != avpn)	    || !(hpte_v & HPTE_V_VALID)) {		native_unlock_hpte(hptep);		ret = -1;	} else {		set_pp_bit(newpp, hptep);		native_unlock_hpte(hptep);	}	/* Ensure it is out of the tlb too */	if (cpu_has_feature(CPU_FTR_TLBIEL) && !large && local) {		tlbiel(va);	} else {		int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);		if (lock_tlbie)			spin_lock(&native_tlbie_lock);		tlbie(va, large);		if (lock_tlbie)			spin_unlock(&native_tlbie_lock);	}	return ret;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3c726f8dee6f55e96475574e9f645327e461884c/hash_native_64.c/clean/arch/powerpc/mm/hash_native_64.c