void falc_init_t1(pc300_t * card, int ch) 
static void falc_init_t1(pc300_t * card, int ch) 
void falc_init_t1(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	void __iomem *falcbase = card->hw.falcbase;	ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);	/* Switch to T1 mode (PCM 24) */	cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);	/* Wait 20 us for setup */	udelay(20);	/* Transmit Buffer Size (1 frame) */	cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);	/* Clock mode */	if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);	} else { /* Slave mode */		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);		cpc_writeb(falcbase + F_REG(LOOP, ch),			   cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);	}	cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);	cpc_writeb(falcbase + F_REG(FMR0, ch),		   cpc_readb(falcbase + F_REG(FMR0, ch)) &		   ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));	switch (conf->lcode) {		case PC300_LC_AMI:			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) |				   FMR0_XC1 | FMR0_RC1);			/* Clear Channel register to ON for all channels */			cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);			cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);			cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);			break;		case PC300_LC_B8ZS:			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) |				   FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);			break;		case PC300_LC_NRZ:			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);			break;	}	cpc_writeb(falcbase + F_REG(LIM0, ch),		   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);	cpc_writeb(falcbase + F_REG(LIM0, ch),		   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));	/* Set interface mode to 2 MBPS */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);	switch (conf->fr_mode) {		case PC300_FR_ESF:			pfalc->multiframe_mode = 0;			cpc_writeb(falcbase + F_REG(FMR4, ch),				   cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);			cpc_writeb(falcbase + F_REG(FMR1, ch),				   cpc_readb(falcbase + F_REG(FMR1, ch)) | 				   FMR1_CRC | FMR1_EDL);			cpc_writeb(falcbase + F_REG(XDL1, ch), 0);			cpc_writeb(falcbase + F_REG(XDL2, ch), 0);			cpc_writeb(falcbase + F_REG(XDL3, ch), 0);			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);			break;		case PC300_FR_D4:			pfalc->multiframe_mode = 1;			cpc_writeb(falcbase + F_REG(FMR4, ch),				   cpc_readb(falcbase + F_REG(FMR4, ch)) &				   ~(FMR4_FM1 | FMR4_FM0));			cpc_writeb(falcbase + F_REG(FMR0, ch),				   cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);			cpc_writeb(falcbase + F_REG(FMR2, ch),				   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);			break;	}	/* Enable Automatic Resynchronization */	cpc_writeb(falcbase + F_REG(FMR4, ch),		   cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);	/* Transmit Automatic Remote Alarm */	cpc_writeb(falcbase + F_REG(FMR2, ch),		   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);	/* Channel translation mode 1 : one to one */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);	/* No signaling */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);	cpc_writeb(falcbase + F_REG(FMR5, ch),		   cpc_readb(falcbase + F_REG(FMR5, ch)) &		   ~(FMR5_EIBR | FMR5_SRS));	cpc_writeb(falcbase + F_REG(CCR1, ch), 0);	cpc_writeb(falcbase + F_REG(LIM1, ch),		   cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);	switch (conf->lbo) {			/* Provides proper Line Build Out */		case PC300_LBO_0_DB:			cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));			cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);			cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);			cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);			break;		case PC300_LBO_7_5_DB:			cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));			cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);			cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);			cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);			break;		case PC300_LBO_15_DB:			cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));			cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);			cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);			cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);			break;		case PC300_LBO_22_5_DB:			cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));			cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);			cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);			cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);			break;	}	/* Transmit Clock-Slot Offset */	cpc_writeb(falcbase + F_REG(XC0, ch),		   cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);	/* Transmit Time-slot Offset */	cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);	/* Receive  Clock-Slot offset */	cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);	/* Receive  Time-slot offset */	cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);	/* LOS Detection after 176 consecutive 0s */	cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);	/* LOS Recovery after 22 ones in the time window of PCD */	cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);	cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);	if (conf->fr_mode == PC300_FR_ESF_JAPAN) {		cpc_writeb(falcbase + F_REG(RC1, ch),			   cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);	}	falc_close_all_timeslots(card, ch);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7665a08928f241247afe8c76865cdbe4ef5489bf/pc300_drv.c/buggy/drivers/net/wan/pc300_drv.c