spin_lock_init(&ohci->event_lock); 
static void ohci_initialize(struct ti_ohci *ohci){	char irq_buf[16];	quadlet_t buf;	int num_ports, i;	spin_lock_init(&ohci->phy_reg_lock);	spin_lock_init(&ohci->event_lock);	/* Put some defaults to these undefined bus options */	buf = reg_read(ohci, OHCI1394_BusOptions);	buf |=  0x60000000; /* Enable CMC and ISC */	if (hpsb_disable_irm)		buf &= ~0x80000000;	else		buf |=  0x80000000; /* Enable IRMC */	buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */	buf &= ~0x18000000; /* Disable PMC and BMC */	reg_write(ohci, OHCI1394_BusOptions, buf);	/* Set the bus number */	reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);	/* Enable posted writes */	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);	/* Clear link control register */	reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);	/* Enable cycle timer and cycle master and set the IRM	 * contender bit in our self ID packets if appropriate. */	reg_write(ohci, OHCI1394_LinkControlSet,		  OHCI1394_LinkControl_CycleTimerEnable |		  OHCI1394_LinkControl_CycleMaster);	i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;	if (hpsb_disable_irm)		i &= ~PHY_04_CONTENDER;	else		i |= PHY_04_CONTENDER;	set_phy_reg(ohci, 4, i);	/* Set up self-id dma buffer */	reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);	/* enable self-id and phys */	reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID |		  OHCI1394_LinkControl_RcvPhyPkt);	/* Set the Config ROM mapping register */	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);	/* Now get our max packet size */	ohci->max_packet_size =		1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);			/* Don't accept phy packets into AR request context */	reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);	/* Clear the interrupt mask */	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);	reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);	/* Clear the interrupt mask */	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);	reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);	/* Initialize AR dma */	initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);	initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);	/* Initialize AT dma */	initialize_dma_trm_ctx(&ohci->at_req_context);	initialize_dma_trm_ctx(&ohci->at_resp_context);		/* Initialize IR Legacy DMA channel mask */	ohci->ir_legacy_channels = 0;	/*	 * Accept AT requests from all nodes. This probably	 * will have to be controlled from the subsystem	 * on a per node basis.	 */	reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);	/* Specify AT retries */	reg_write(ohci, OHCI1394_ATRetries,		  OHCI1394_MAX_AT_REQ_RETRIES |		  (OHCI1394_MAX_AT_RESP_RETRIES<<4) |		  (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));	/* We don't want hardware swapping */	reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);	/* Enable interrupts */	reg_write(ohci, OHCI1394_IntMaskSet,		  OHCI1394_unrecoverableError |		  OHCI1394_masterIntEnable |		  OHCI1394_busReset |		  OHCI1394_selfIDComplete |		  OHCI1394_RSPkt |		  OHCI1394_RQPkt |		  OHCI1394_respTxComplete |		  OHCI1394_reqTxComplete |		  OHCI1394_isochRx |		  OHCI1394_isochTx |		  OHCI1394_cycleInconsistent);	/* Enable link */	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);	buf = reg_read(ohci, OHCI1394_Version);#ifndef __sparc__	sprintf (irq_buf, "%d", ohci->dev->irq);#else	sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));#endif	PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s]  "	      "MMIO=[%lx-%lx]  Max Packet=[%d]",	      ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),	      ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf,	      pci_resource_start(ohci->dev, 0),	      pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,	      ohci->max_packet_size);	/* Check all of our ports to make sure that if anything is	 * connected, we enable that port. */	num_ports = get_phy_reg(ohci, 2) & 0xf;	for (i = 0; i < num_ports; i++) {		unsigned int status;		set_phy_reg(ohci, 7, i);		status = get_phy_reg(ohci, 8);		if (status & 0x20)			set_phy_reg(ohci, 8, status & ~1);	}        /* Serial EEPROM Sanity check. */        if ((ohci->max_packet_size < 512) ||	    (ohci->max_packet_size > 4096)) {		/* Serial EEPROM contents are suspect, set a sane max packet		 * size and print the raw contents for bug reports if verbose		 * debug is enabled. */#ifdef CONFIG_IEEE1394_VERBOSEDEBUG		int i;#endif		PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "                      "attempting to setting max_packet_size to 512 bytes");		reg_write(ohci, OHCI1394_BusOptions,			  (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);		ohci->max_packet_size = 512;#ifdef CONFIG_IEEE1394_VERBOSEDEBUG		PRINT(KERN_DEBUG, "    EEPROM Present: %d",		      (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);		reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);		for (i = 0;		     ((i < 1000) &&		      (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)			udelay(10);		for (i = 0; i < 0x20; i++) {			reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);			PRINT(KERN_DEBUG, "    EEPROM %02x: %02x", i,			      (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);		}#endif	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3515d0161d55d2fa1a340932625f94240a68c262/ohci1394.c/clean/drivers/ieee1394/ohci1394.c