val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) & 
val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) & 
bnx2_init_5708s_phy(struct bnx2 *bp){	u32 val;	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);	val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);	val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);	if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {		bnx2_read_phy(bp, BCM5708S_UP1, &val);		val |= BCM5708S_UP1_2G5;		bnx2_write_phy(bp, BCM5708S_UP1, val);	}	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||	    (CHIP_ID(bp) == CHIP_ID_5708_B0)) {		/* increase tx signal amplitude */		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,			       BCM5708S_BLK_ADDR_TX_MISC);		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);		val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);	}	val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &	      BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;	if (val) {		u32 is_backplane;		is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +					  BNX2_SHARED_HW_CFG_CONFIG);		if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,				       BCM5708S_BLK_ADDR_TX_MISC);			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,				       BCM5708S_BLK_ADDR_DIG);		}	}	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/e3648b3d8de3b37fae7acbb57db1e001a19cd3b7/bnx2.c/buggy/drivers/net/bnx2.c