return 0; 
 if (tmp & PORT_CS_RDY) return 0;  return __sil24_restart_controller(port); 
static int __sil24_reset_controller(void __iomem *port){	int cnt;	u32 tmp;	/* Reset controller state.  Is this correct? */	writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);	readl(port + PORT_CTRL_STAT);	/* sync */	/* Max ~100ms */	for (cnt = 0; cnt < 1000; cnt++) {		udelay(100);		tmp = readl(port + PORT_CTRL_STAT);		if (!(tmp & PORT_CS_DEV_RST))			break;	}	if (tmp & PORT_CS_DEV_RST)		return -1;	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/7d1ce682d08625258524d23ef5eb9e7ae261c1d0/sata_sil24.c/buggy/drivers/scsi/sata_sil24.c