#ifdef CONFIG_440EP if (uart2 & 0x00800000) p->uart2 = ser_clk; else p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);  if (uart3 & 0x00800000) p->uart3 = ser_clk; else p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256); #endif 
void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,	unsigned int ser_clk){	u32 pllc  = CPR_READ(DCRN_CPR_PLLC);	u32 plld  = CPR_READ(DCRN_CPR_PLLD);	u32 uart0 = SDR_READ(DCRN_SDR_UART0);	u32 uart1 = SDR_READ(DCRN_SDR_UART1);	/* Dividers */	u32 fbdv   = __fix_zero((plld >> 24) & 0x1f, 32);	u32 fwdva  = __fix_zero((plld >> 16) & 0xf, 16);	u32 fwdvb  = __fix_zero((plld >> 8) & 7, 8);	u32 lfbdv  = __fix_zero(plld & 0x3f, 64);	u32 pradv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMAD) >> 24) & 7, 8);	u32 prbdv0 = __fix_zero((CPR_READ(DCRN_CPR_PRIMBD) >> 24) & 7, 8);	u32 opbdv0 = __fix_zero((CPR_READ(DCRN_CPR_OPBD) >> 24) & 3, 4);	u32 perdv0 = __fix_zero((CPR_READ(DCRN_CPR_PERD) >> 24) & 3, 4);	/* Input clocks for primary dividers */	u32 clk_a, clk_b;	if (pllc & 0x40000000){		u32 m;		/* Feedback path */		switch ((pllc >> 24) & 7){		case 0:			/* PLLOUTx */			m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;			break;		case 1:			/* CPU */			m = fwdva * pradv0;			break;		case 5:			/* PERClk */			m = fwdvb * prbdv0 * opbdv0 * perdv0;			break;		default:			printk(KERN_EMERG "invalid PLL feedback source\n");			goto bypass;		}		m *= fbdv;		p->vco = sys_clk * m;		clk_a = p->vco / fwdva;		clk_b = p->vco / fwdvb;	}	else {bypass:		/* Bypass system PLL */		p->vco = 0;		clk_a = clk_b = sys_clk;	}	p->cpu = clk_a / pradv0;	p->plb = clk_b / prbdv0;	p->opb = p->plb / opbdv0;	p->ebc = p->opb / perdv0;	/* UARTs clock */	if (uart0 & 0x00800000)		p->uart0 = ser_clk;	else		p->uart0 = p->plb / __fix_zero(uart0 & 0xff, 256);	if (uart1 & 0x00800000)		p->uart1 = ser_clk;	else		p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/c9cf73aee140baa425429902aaed2c758401343f/ibm440gx_common.c/clean/arch/ppc/syslib/ibm440gx_common.c