u32 tempval; 
int startup_gfar(struct net_device *dev){	struct txbd8 *txbdp;	struct rxbd8 *rxbdp;	dma_addr_t addr;	unsigned long vaddr;	int i;	struct gfar_private *priv = netdev_priv(dev);	struct gfar *regs = priv->regs;	u32 tempval;	int err = 0;	gfar_write(&regs->imask, IMASK_INIT_CLEAR);	/* Allocate memory for the buffer descriptors */	vaddr = (unsigned long) dma_alloc_coherent(NULL, 			sizeof (struct txbd8) * priv->tx_ring_size +			sizeof (struct rxbd8) * priv->rx_ring_size,			&addr, GFP_KERNEL);	if (vaddr == 0) {		printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",		       dev->name);		return -ENOMEM;	}	priv->tx_bd_base = (struct txbd8 *) vaddr;	/* enet DMA only understands physical addresses */	gfar_write(&regs->tbase, addr);	/* Start the rx descriptor ring where the tx ring leaves off */	addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;	vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;	priv->rx_bd_base = (struct rxbd8 *) vaddr;	gfar_write(&regs->rbase, addr);	/* Setup the skbuff rings */	priv->tx_skbuff =	    (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *					priv->tx_ring_size, GFP_KERNEL);	if (priv->tx_skbuff == NULL) {		printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",		       dev->name);		err = -ENOMEM;		goto tx_skb_fail;	}	for (i = 0; i < priv->tx_ring_size; i++)		priv->tx_skbuff[i] = NULL;	priv->rx_skbuff =	    (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *					priv->rx_ring_size, GFP_KERNEL);	if (priv->rx_skbuff == NULL) {		printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",		       dev->name);		err = -ENOMEM;		goto rx_skb_fail;	}	for (i = 0; i < priv->rx_ring_size; i++)		priv->rx_skbuff[i] = NULL;	/* Initialize some variables in our dev structure */	priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;	priv->cur_rx = priv->rx_bd_base;	priv->skb_curtx = priv->skb_dirtytx = 0;	priv->skb_currx = 0;	/* Initialize Transmit Descriptor Ring */	txbdp = priv->tx_bd_base;	for (i = 0; i < priv->tx_ring_size; i++) {		txbdp->status = 0;		txbdp->length = 0;		txbdp->bufPtr = 0;		txbdp++;	}	/* Set the last descriptor in the ring to indicate wrap */	txbdp--;	txbdp->status |= TXBD_WRAP;	rxbdp = priv->rx_bd_base;	for (i = 0; i < priv->rx_ring_size; i++) {		struct sk_buff *skb = NULL;		rxbdp->status = 0;		skb = gfar_new_skb(dev, rxbdp);		priv->rx_skbuff[i] = skb;		rxbdp++;	}	/* Set the last descriptor in the ring to wrap */	rxbdp--;	rxbdp->status |= RXBD_WRAP;	/* If the device has multiple interrupts, register for	 * them.  Otherwise, only register for the one */	if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {		/* Install our interrupt handlers for Error, 		 * Transmit, and Receive */		if (request_irq(priv->interruptError, gfar_error,				0, "enet_error", dev) < 0) {			printk(KERN_ERR "%s: Can't get IRQ %d\n",			       dev->name, priv->interruptError);			err = -1;			goto err_irq_fail;		}		if (request_irq(priv->interruptTransmit, gfar_transmit,				0, "enet_tx", dev) < 0) {			printk(KERN_ERR "%s: Can't get IRQ %d\n",			       dev->name, priv->interruptTransmit);			err = -1;			goto tx_irq_fail;		}		if (request_irq(priv->interruptReceive, gfar_receive,				0, "enet_rx", dev) < 0) {			printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",			       dev->name, priv->interruptReceive);			err = -1;			goto rx_irq_fail;		}	} else {		if (request_irq(priv->interruptTransmit, gfar_interrupt,				0, "gfar_interrupt", dev) < 0) {			printk(KERN_ERR "%s: Can't get IRQ %d\n",			       dev->name, priv->interruptError);			err = -1;			goto err_irq_fail;		}	}	/* Set up the PHY change work queue */	INIT_WORK(&priv->tq, gfar_phy_change, dev);	init_timer(&priv->phy_info_timer);	priv->phy_info_timer.function = &gfar_phy_startup_timer;	priv->phy_info_timer.data = (unsigned long) priv->mii_info;	mod_timer(&priv->phy_info_timer, jiffies + HZ);	/* Configure the coalescing support */	if (priv->txcoalescing)		gfar_write(&regs->txic,			   mk_ic_value(priv->txcount, priv->txtime));	else		gfar_write(&regs->txic, 0);	if (priv->rxcoalescing)		gfar_write(&regs->rxic,			   mk_ic_value(priv->rxcount, priv->rxtime));	else		gfar_write(&regs->rxic, 0);	init_waitqueue_head(&priv->rxcleanupq);	/* Enable Rx and Tx in MACCFG1 */	tempval = gfar_read(&regs->maccfg1);	tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);	gfar_write(&regs->maccfg1, tempval);	/* Initialize DMACTRL to have WWR and WOP */	tempval = gfar_read(&priv->regs->dmactrl);	tempval |= DMACTRL_INIT_SETTINGS;	gfar_write(&priv->regs->dmactrl, tempval);	/* Clear THLT, so that the DMA starts polling now */	gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);	/* Make sure we aren't stopped */	tempval = gfar_read(&priv->regs->dmactrl);	tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);	gfar_write(&priv->regs->dmactrl, tempval);	/* Unmask the interrupts we look for */	gfar_write(&regs->imask, IMASK_DEFAULT);	return 0;rx_irq_fail:	free_irq(priv->interruptTransmit, dev);tx_irq_fail:	free_irq(priv->interruptError, dev);err_irq_fail:rx_skb_fail:	free_skb_resources(priv);tx_skb_fail:	dma_free_coherent(NULL,			sizeof(struct txbd8)*priv->tx_ring_size			+ sizeof(struct rxbd8)*priv->rx_ring_size,			priv->tx_bd_base,			gfar_read(&regs->tbase));	if (priv->mii_info->phyinfo->close)		priv->mii_info->phyinfo->close(priv->mii_info);	kfree(priv->mii_info);	return err;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/0bbaf069f053957e8d733784e18a2992afd1dd3c/gianfar.c/buggy/drivers/net/gianfar.c