"ld	r4, @%2			\n\t" "blez	r4, 2b			\n\t" "bra	1b			\n\t" LOCK_SECTION_END ";; CHECK IPICRi == 0		\n\t" 
"st	%2, @%1			\n\t" 
unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,	int try){	spinlock_t *ipilock;	unsigned long flags = 0;	volatile unsigned long *ipicr_addr;	unsigned long ipicr_val;	unsigned long my_physid_mask;	unsigned long mask = cpus_addr(physid_mask)[0];	if (mask & ~physids_coerce(phys_cpu_present_map))		BUG();	if (ipi_num >= NR_IPIS)		BUG();	mask <<= IPI_SHIFT;	ipilock = &ipi_lock[ipi_num];	ipicr_addr = (volatile unsigned long *)(M32R_ICU_IPICR_ADDR		+ (ipi_num << 2));	my_physid_mask = ~(1 << smp_processor_id());	/*	 * lock ipi_lock[i]	 * check IPICRi == 0	 * write IPICRi (send IPIi)	 * unlock ipi_lock[i]	 */	__asm__ __volatile__ (		";; LOCK ipi_lock[i]		\n\t"		".fillinsn			\n"		"1:				\n\t"		"mvfc	%1, psw 		\n\t"		"clrpsw	#0x40 -> nop		\n\t"		DCACHE_CLEAR("r4", "r5", "%2")		"lock	r4, @%2			\n\t"		"addi	r4, #-1			\n\t"		"unlock	r4, @%2			\n\t"		"mvtc	%1, psw			\n\t"		"bnez	r4, 2f			\n\t"		LOCK_SECTION_START(".balign 4 \n\t")		".fillinsn			\n"		"2:				\n\t"		"ld	r4, @%2			\n\t"		"blez	r4, 2b			\n\t"		"bra	1b			\n\t"		LOCK_SECTION_END		";; CHECK IPICRi == 0		\n\t"		".fillinsn			\n"		"3:				\n\t"		"ld	%0, @%3			\n\t"		"and	%0, %6			\n\t"		"beqz	%0, 4f			\n\t"		"bnez	%5, 5f			\n\t"		"bra	3b			\n\t"		";; WRITE IPICRi (send IPIi)	\n\t"		".fillinsn			\n"		"4:				\n\t"		"st	%4, @%3			\n\t"		";; UNLOCK ipi_lock[i]		\n\t"		".fillinsn			\n"		"5:				\n\t"		"ldi	r4, #1			\n\t"		"st	r4, @%2			\n\t"		: "=&r"(ipicr_val)		: "r"(flags), "r"(&ipilock->slock), "r"(ipicr_addr),		  "r"(mask), "r"(try), "r"(my_physid_mask)		: "memory", "r4"#ifdef CONFIG_CHIP_M32700_TS1		, "r5"#endif	/* CONFIG_CHIP_M32700_TS1 */	);	return ipicr_val;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/fb1c8f93d869b34cacb8b8932e2b83d96a19d720/smp.c/clean/arch/m32r/kernel/smp.c