ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR; 
ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR); 
ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data){	struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;	/* Prepare the EEPROM for writing */	ixgb_setup_eeprom(hw);	/*  Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode	 *  plus 4-bit dummy).  This puts the EEPROM into write/erase mode.	 */	ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);	ixgb_shift_out_bits(hw, 0, 4);	/*  Prepare the EEPROM  */	ixgb_standby_eeprom(hw);	/*  Send the Write command (3-bit opcode + 6-bit addr)  */	ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);	ixgb_shift_out_bits(hw, offset, 6);	/*  Send the data  */	ixgb_shift_out_bits(hw, data, 16);	ixgb_wait_eeprom_command(hw);	/*  Recover from write  */	ixgb_standby_eeprom(hw);	/* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit	 * opcode plus 4-bit dummy).  This takes the EEPROM out of write/erase	 * mode.	 */	ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);	ixgb_shift_out_bits(hw, 0, 4);	/*  Done with writing  */	ixgb_cleanup_eeprom(hw);	/* clear the init_ctrl_reg_1 to signify that the cache is invalidated */	ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR;	return;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/abf481d6af8670c89f33f354c6fbd9977b23cebc/ixgb_ee.c/buggy/drivers/net/ixgb/ixgb_ee.c