void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS]) 
void __init omap_serial_init(void) 
void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS]){	int i;	if (cpu_is_omap730()) {		serial_platform_data[0].regshift = 0;		serial_platform_data[1].regshift = 0;		serial_platform_data[0].irq = INT_730_UART_MODEM_1;		serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;	}	if (cpu_is_omap1510()) {		serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;		serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;		serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;	}	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {		unsigned char reg;		if (ports[i] == 0) {			serial_platform_data[i].membase = NULL;			serial_platform_data[i].mapbase = 0;			continue;		}		switch (i) {		case 0:			uart1_ck = clk_get(NULL, "uart1_ck");			if (IS_ERR(uart1_ck))				printk("Could not get uart1_ck\n");			else {				clk_use(uart1_ck);				if (cpu_is_omap1510())					clk_set_rate(uart1_ck, 12000000);			}			if (cpu_is_omap1510()) {				omap_cfg_reg(UART1_TX);				omap_cfg_reg(UART1_RTS);				if (machine_is_omap_innovator()) {					reg = fpga_read(OMAP1510_FPGA_POWER);					reg |= OMAP1510_FPGA_PCR_COM1_EN;					fpga_write(reg, OMAP1510_FPGA_POWER);					udelay(10);				}			}			break;		case 1:			uart2_ck = clk_get(NULL, "uart2_ck");			if (IS_ERR(uart2_ck))				printk("Could not get uart2_ck\n");			else {				clk_use(uart2_ck);				if (cpu_is_omap1510())					clk_set_rate(uart2_ck, 12000000);				else					clk_set_rate(uart2_ck, 48000000);			}			if (cpu_is_omap1510()) {				omap_cfg_reg(UART2_TX);				omap_cfg_reg(UART2_RTS);				if (machine_is_omap_innovator()) {					reg = fpga_read(OMAP1510_FPGA_POWER);					reg |= OMAP1510_FPGA_PCR_COM2_EN;					fpga_write(reg, OMAP1510_FPGA_POWER);					udelay(10);				}			}			break;		case 2:			uart3_ck = clk_get(NULL, "uart3_ck");			if (IS_ERR(uart3_ck))				printk("Could not get uart3_ck\n");			else {				clk_use(uart3_ck);				if (cpu_is_omap1510())					clk_set_rate(uart3_ck, 12000000);			}			if (cpu_is_omap1510()) {				omap_cfg_reg(UART3_TX);				omap_cfg_reg(UART3_RX);			}			break;		}		omap_serial_reset(&serial_platform_data[i]);	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/3179a019391f0f8081245fd564a5f1be308ba64f/serial.c/buggy/arch/arm/mach-omap1/serial.c