pmd = pmd_offset(dir, address); if (pmd_none(*pmd)) 
pmd = pmd_offset(pgd, address); if (pmd_none_or_clear_bad(pmd)) 
asmlinkage int __do_page_fault(struct pt_regs *regs, unsigned long writeaccess,			       unsigned long address){	unsigned long addrmax = P4SEG;	pgd_t *dir;	pmd_t *pmd;	pte_t *pte;	pte_t entry;#ifdef CONFIG_SH_KGDB	if (kgdb_nofault && kgdb_bus_err_hook)		kgdb_bus_err_hook();#endif#ifdef CONFIG_SH_STORE_QUEUES	addrmax = P4SEG_STORE_QUE + 0x04000000;#endif	if (address >= P3SEG && address < addrmax)		dir = pgd_offset_k(address);	else if (address >= TASK_SIZE)		return 1;	else if (!current->mm)		return 1;	else		dir = pgd_offset(current->mm, address);	pmd = pmd_offset(dir, address);	if (pmd_none(*pmd))		return 1;	if (pmd_bad(*pmd)) {		pmd_ERROR(*pmd);		pmd_clear(pmd);		return 1;	}	pte = pte_offset_kernel(pmd, address);	entry = *pte;	if (pte_none(entry) || pte_not_present(entry)	    || (writeaccess && !pte_write(entry)))		return 1;	if (writeaccess)		entry = pte_mkdirty(entry);	entry = pte_mkyoung(entry);#ifdef CONFIG_CPU_SH4	/*	 * ITLB is not affected by "ldtlb" instruction.	 * So, we need to flush the entry by ourselves.	 */	{		unsigned long flags;		local_irq_save(flags);		__flush_tlb_page(get_asid(), address&PAGE_MASK);		local_irq_restore(flags);	}#endif	set_pte(pte, entry);	update_mmu_cache(NULL, address, entry);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/60ec5585496871345c1a8113d7b60ed9d9474866/fault.c/clean/arch/sh/mm/fault.c