printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n", pci_name(pdev)); 
dev_printk(KERN_WARNING, &pdev->dev, "cache line size not set.  Driver may not function\n"); 
static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent){	static int printed_version;	struct ata_probe_ent *probe_ent = NULL;	unsigned long base;	void __iomem *mmio_base;	int rc;	unsigned int i;	int pci_dev_busy = 0;	u32 tmp, irq_mask;	u8 cls;	if (!printed_version++)		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");	/*	 * If this driver happens to only be useful on Apple's K2, then	 * we should check that here as it has a normal Serverworks ID	 */	rc = pci_enable_device(pdev);	if (rc)		return rc;	rc = pci_request_regions(pdev, DRV_NAME);	if (rc) {		pci_dev_busy = 1;		goto err_out;	}	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);	if (rc)		goto err_out_regions;	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);	if (rc)		goto err_out_regions;	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);	if (probe_ent == NULL) {		rc = -ENOMEM;		goto err_out_regions;	}	memset(probe_ent, 0, sizeof(*probe_ent));	INIT_LIST_HEAD(&probe_ent->node);	probe_ent->dev = pci_dev_to_dev(pdev);	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;	probe_ent->sht = sil_port_info[ent->driver_data].sht;	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;       	probe_ent->irq = pdev->irq;       	probe_ent->irq_flags = SA_SHIRQ;	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;	mmio_base = pci_iomap(pdev, 5, 0);	if (mmio_base == NULL) {		rc = -ENOMEM;		goto err_out_free_ent;	}	probe_ent->mmio_base = mmio_base;	base = (unsigned long) mmio_base;	for (i = 0; i < probe_ent->n_ports; i++) {		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;		probe_ent->port[i].altstatus_addr =		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;		probe_ent->port[i].scr_addr = base + sil_port[i].scr;		ata_std_ports(&probe_ent->port[i]);	}	/* Initialize FIFO PCI bus arbitration */	cls = sil_get_device_cache_line(pdev);	if (cls) {		cls >>= 3;		cls++;  /* cls = (line_size/8)+1 */		writeb(cls, mmio_base + SIL_FIFO_R0);		writeb(cls, mmio_base + SIL_FIFO_W0);		writeb(cls, mmio_base + SIL_FIFO_R1);		writeb(cls, mmio_base + SIL_FIFO_W1);		if (ent->driver_data == sil_3114) {			writeb(cls, mmio_base + SIL_FIFO_R2);			writeb(cls, mmio_base + SIL_FIFO_W2);			writeb(cls, mmio_base + SIL_FIFO_R3);			writeb(cls, mmio_base + SIL_FIFO_W3);		}	} else		printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n",			pci_name(pdev));	if (ent->driver_data == sil_3114) {		irq_mask = SIL_MASK_4PORT;		/* flip the magic "make 4 ports work" bit */		tmp = readl(mmio_base + SIL_IDE2_BMDMA);		if ((tmp & SIL_INTR_STEERING) == 0)			writel(tmp | SIL_INTR_STEERING,			       mmio_base + SIL_IDE2_BMDMA);	} else {		irq_mask = SIL_MASK_2PORT;	}	/* make sure IDE0/1/2/3 interrupts are not masked */	tmp = readl(mmio_base + SIL_SYSCFG);	if (tmp & irq_mask) {		tmp &= ~irq_mask;		writel(tmp, mmio_base + SIL_SYSCFG);		readl(mmio_base + SIL_SYSCFG);	/* flush */	}	/* mask all SATA phy-related interrupts */	/* TODO: unmask bit 6 (SError N bit) for hotplug */	for (i = 0; i < probe_ent->n_ports; i++)		writel(0, mmio_base + sil_port[i].sien);	pci_set_master(pdev);	/* FIXME: check ata_device_add return value */	ata_device_add(probe_ent);	kfree(probe_ent);	return 0;err_out_free_ent:	kfree(probe_ent);err_out_regions:	pci_release_regions(pdev);err_out:	if (!pci_dev_busy)		pci_disable_device(pdev);	return rc;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/a9524a76f70f3343e4be27f95a7e92a8ba5f9009/sata_sil.c/clean/drivers/scsi/sata_sil.c