 spin_unlock_irqrestore(&tp->lock, flags);  
out: 
static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs){	struct net_device *dev = dev_id;	struct tg3 *tp = netdev_priv(dev);	struct tg3_hw_status *sblk = tp->hw_status;	unsigned long flags;	unsigned int handled = 1;	spin_lock_irqsave(&tp->lock, flags);	/* In INTx mode, it is possible for the interrupt to arrive at	 * the CPU before the status block posted prior to the interrupt.	 * Reading the PCI State register will confirm whether the	 * interrupt is ours and will flush the status block.	 */	if ((sblk->status & SD_STATUS_UPDATED) ||	    !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {		/*		 * writing any value to intr-mbox-0 clears PCI INTA# and		 * chip-internal interrupt pending events.		 * writing non-zero to intr-mbox-0 additional tells the		 * NIC to stop sending us irqs, engaging "in-intr-handler"		 * event coalescing.		 */		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,			     0x00000001);		tp->last_tag = sblk->status_tag;		rmb();		sblk->status &= ~SD_STATUS_UPDATED;		if (likely(tg3_has_work(tp)))			netif_rx_schedule(dev);		/* schedule NAPI poll */		else {			/* no work, shared interrupt perhaps?  re-enable			 * interrupts, and flush that PCI write			 */			tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,				     tp->last_tag << 24);			tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);		}	} else {	/* shared interrupt */		handled = 0;	}	spin_unlock_irqrestore(&tp->lock, flags);	return IRQ_RETVAL(handled);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f47c11eeccc8820010992eb32dbe7370a08f8bd3/tg3.c/buggy/drivers/net/tg3.c