if (tmp == 0) { printk("s5h1420: avoided division by 0\n"); tmp = 1; } 
static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status){	struct s5h1420_state* state = fe->demodulator_priv;	u8 val;	if (status == NULL)		return -EINVAL;	/* determine lock state */	*status = s5h1420_get_status_bits(state);	/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert the inversion,	wait a bit and check again */	if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {		val = s5h1420_readreg(state, 0x32);		if ((val & 0x07) == 0x03) {			if (val & 0x08)				s5h1420_writereg(state, 0x31, 0x13);			else				s5h1420_writereg(state, 0x31, 0x1b);			/* wait a bit then update lock status */			mdelay(200);			*status = s5h1420_get_status_bits(state);		}	}	/* perform post lock setup */	if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {		/* calculate the data rate */		u32 tmp = s5h1420_getsymbolrate(state);		switch(s5h1420_readreg(state, 0x32) & 0x07) {		case 0:			tmp = (tmp * 2 * 1) / 2;			break;		case 1:			tmp = (tmp * 2 * 2) / 3;			break;		case 2:			tmp = (tmp * 2 * 3) / 4;			break;		case 3:			tmp = (tmp * 2 * 5) / 6;			break;		case 4:			tmp = (tmp * 2 * 6) / 7;			break;		case 5:			tmp = (tmp * 2 * 7) / 8;			break;		}		tmp = state->fclk / tmp;		/* set the MPEG_CLK_INTL for the calculated data rate */		if (tmp < 4)			val = 0x00;		else if (tmp < 8)			val = 0x01;		else if (tmp < 12)			val = 0x02;		else if (tmp < 16)			val = 0x03;		else if (tmp < 24)			val = 0x04;		else if (tmp < 32)			val = 0x05;		else			val = 0x06;		s5h1420_writereg(state, 0x22, val);		/* DC freeze */		s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);		/* kicker disable + remove DC offset */		s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);		/* post-lock processing has been done! */		state->postlocked = 1;	}	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/a9d6a80b41c04e8ff4c7442cc35f5df610863841/s5h1420.c/buggy/drivers/media/dvb/frontends/s5h1420.c