struct ia64_sal_retval isrv;  /* * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work * around hw issues at the pci bus level.  SGI proms older than * 4.10 don't implment this. */  SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE, pci_domain_nr(bus), bus->number, 0, /* io */ 1, /* write */ port, size, __pa(&val));  if (isrv.status == 0) return size;  /* * If the above failed, retry using the SAL_PROBE call which should * be present in all proms (but which cannot work round PCI chipset * bugs).  This code is retained for compatability with old * pre-4.10 proms, and should be removed at some point in the future. */ 
int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size){	int ret = size;	unsigned long paddr;	unsigned long *addr;	if (!SN_PCIBUS_BUSSOFT(bus)) {		ret = -ENODEV;		goto out;	}	/* Put the phys addr in uncached space */	paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;	paddr += port;	addr = (unsigned long *)paddr;	switch (size) {	case 1:		*(volatile u8 *)(addr) = (u8)(val);		break;	case 2:		*(volatile u16 *)(addr) = (u16)(val);		break;	case 4:		*(volatile u32 *)(addr) = (u32)(val);		break;	default:		ret = -EINVAL;		break;	} out:	return ret;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/61b9cf7c6cf5077c40ad37480fa56f6574af3db5/pci_dma.c/buggy/arch/ia64/sn/pci/pci_dma.c