void falc_intr_enable(pc300_t * card, int ch) 
static void falc_intr_enable(pc300_t * card, int ch) 
void falc_intr_enable(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	void __iomem *falcbase = card->hw.falcbase;	/* Interrupt pins are open-drain */	cpc_writeb(falcbase + F_REG(IPC, ch),		   cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);	/* Conters updated each second */	cpc_writeb(falcbase + F_REG(FMR1, ch),		   cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);	/* Enable SEC and ES interrupts  */	cpc_writeb(falcbase + F_REG(IMR3, ch),		   cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));	if (conf->fr_mode == PC300_FR_UNFRAMED) {		cpc_writeb(falcbase + F_REG(IMR4, ch),			   cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));	} else {		cpc_writeb(falcbase + F_REG(IMR4, ch),			   cpc_readb(falcbase + F_REG(IMR4, ch)) &			   ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));	}	if (conf->media == IF_IFACE_T1) {		cpc_writeb(falcbase + F_REG(IMR3, ch),			   cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);	} else {		cpc_writeb(falcbase + F_REG(IPC, ch),			   cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);		if (conf->fr_mode == PC300_FR_UNFRAMED) {			cpc_writeb(falcbase + F_REG(IMR2, ch),				   cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));		} else {			cpc_writeb(falcbase + F_REG(IMR2, ch),				   cpc_readb(falcbase + F_REG(IMR2, ch)) &				   ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));			if (pfalc->multiframe_mode) {				cpc_writeb(falcbase + F_REG(IMR2, ch),					   cpc_readb(falcbase + F_REG(IMR2, ch)) & 					   ~(IMR2_T400MS | IMR2_MFAR));			} else {				cpc_writeb(falcbase + F_REG(IMR2, ch),					   cpc_readb(falcbase + F_REG(IMR2, ch)) | 					   IMR2_T400MS | IMR2_MFAR);			}		}	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7665a08928f241247afe8c76865cdbe4ef5489bf/pc300_drv.c/buggy/drivers/net/wan/pc300_drv.c