int fill_rx_buffers(struct s2io_nic *nic, int ring_no) 
static int fill_rx_buffers(struct s2io_nic *nic, int ring_no) 
int fill_rx_buffers(struct s2io_nic *nic, int ring_no){	struct net_device *dev = nic->dev;	struct sk_buff *skb;	RxD_t *rxdp;	int off, off1, size, block_no, block_no1;	u32 alloc_tab = 0;	u32 alloc_cnt;	mac_info_t *mac_control;	struct config_param *config;	u64 tmp;	buffAdd_t *ba;#ifndef CONFIG_S2IO_NAPI	unsigned long flags;#endif	RxD_t *first_rxdp = NULL;	mac_control = &nic->mac_control;	config = &nic->config;	alloc_cnt = mac_control->rings[ring_no].pkt_cnt -	    atomic_read(&nic->rx_bufs_left[ring_no]);	while (alloc_tab < alloc_cnt) {		block_no = mac_control->rings[ring_no].rx_curr_put_info.		    block_index;		block_no1 = mac_control->rings[ring_no].rx_curr_get_info.		    block_index;		off = mac_control->rings[ring_no].rx_curr_put_info.offset;		off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;		rxdp = mac_control->rings[ring_no].				rx_blocks[block_no].rxds[off].virt_addr;		if ((block_no == block_no1) && (off == off1) &&					(rxdp->Host_Control)) {			DBG_PRINT(INTR_DBG, "%s: Get and Put",				  dev->name);			DBG_PRINT(INTR_DBG, " info equated\n");			goto end;		}		if (off && (off == rxd_count[nic->rxd_mode])) {			mac_control->rings[ring_no].rx_curr_put_info.			    block_index++;			if (mac_control->rings[ring_no].rx_curr_put_info.			    block_index == mac_control->rings[ring_no].					block_count)				mac_control->rings[ring_no].rx_curr_put_info.					block_index = 0;			block_no = mac_control->rings[ring_no].					rx_curr_put_info.block_index;			if (off == rxd_count[nic->rxd_mode])				off = 0;			mac_control->rings[ring_no].rx_curr_put_info.				offset = off;			rxdp = mac_control->rings[ring_no].				rx_blocks[block_no].block_virt_addr;			DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",				  dev->name, rxdp);		}#ifndef CONFIG_S2IO_NAPI		spin_lock_irqsave(&nic->put_lock, flags);		mac_control->rings[ring_no].put_pos =		    (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;		spin_unlock_irqrestore(&nic->put_lock, flags);#endif		if ((rxdp->Control_1 & RXD_OWN_XENA) &&			((nic->rxd_mode >= RXD_MODE_3A) &&				(rxdp->Control_2 & BIT(0)))) {			mac_control->rings[ring_no].rx_curr_put_info.					offset = off;			goto end;		}		/* calculate size of skb based on ring mode */		size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +				HEADER_802_2_SIZE + HEADER_SNAP_SIZE;		if (nic->rxd_mode == RXD_MODE_1)			size += NET_IP_ALIGN;		else if (nic->rxd_mode == RXD_MODE_3B)			size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;		else			size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;		/* allocate skb */		skb = dev_alloc_skb(size);		if(!skb) {			DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);			DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");			if (first_rxdp) {				wmb();				first_rxdp->Control_1 |= RXD_OWN_XENA;			}			return -ENOMEM ;		}		if (nic->rxd_mode == RXD_MODE_1) {			/* 1 buffer mode - normal operation mode */			memset(rxdp, 0, sizeof(RxD1_t));			skb_reserve(skb, NET_IP_ALIGN);			((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single			    (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);			rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_1);			rxdp->Control_2 |= SET_BUFFER0_SIZE_1(size);		} else if (nic->rxd_mode >= RXD_MODE_3A) {			/*			 * 2 or 3 buffer mode -			 * Both 2 buffer mode and 3 buffer mode provides 128			 * byte aligned receive buffers.			 *			 * 3 buffer mode provides header separation where in			 * skb->data will have L3/L4 headers where as			 * skb_shinfo(skb)->frag_list will have the L4 data			 * payload			 */			memset(rxdp, 0, sizeof(RxD3_t));			ba = &mac_control->rings[ring_no].ba[block_no][off];			skb_reserve(skb, BUF0_LEN);			tmp = (u64)(unsigned long) skb->data;			tmp += ALIGN_SIZE;			tmp &= ~ALIGN_SIZE;			skb->data = (void *) (unsigned long)tmp;			skb->tail = (void *) (unsigned long)tmp;			((RxD3_t*)rxdp)->Buffer0_ptr =			    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,					   PCI_DMA_FROMDEVICE);			rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);			if (nic->rxd_mode == RXD_MODE_3B) {				/* Two buffer mode */				/*				 * Buffer2 will have L3/L4 header plus 				 * L4 payload				 */				((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single				(nic->pdev, skb->data, dev->mtu + 4,						PCI_DMA_FROMDEVICE);				/* Buffer-1 will be dummy buffer not used */				((RxD3_t*)rxdp)->Buffer1_ptr =				pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,					PCI_DMA_FROMDEVICE);				rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);				rxdp->Control_2 |= SET_BUFFER2_SIZE_3								(dev->mtu + 4);			} else {				/* 3 buffer mode */				if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {					dev_kfree_skb_irq(skb);					if (first_rxdp) {						wmb();						first_rxdp->Control_1 |=							RXD_OWN_XENA;					}					return -ENOMEM ;				}			}			rxdp->Control_2 |= BIT(0);		}		rxdp->Host_Control = (unsigned long) (skb);		if (alloc_tab & ((1 << rxsync_frequency) - 1))			rxdp->Control_1 |= RXD_OWN_XENA;		off++;		if (off == (rxd_count[nic->rxd_mode] + 1))			off = 0;		mac_control->rings[ring_no].rx_curr_put_info.offset = off;		rxdp->Control_2 |= SET_RXD_MARKER;		if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {			if (first_rxdp) {				wmb();				first_rxdp->Control_1 |= RXD_OWN_XENA;			}			first_rxdp = rxdp;		}		atomic_inc(&nic->rx_bufs_left[ring_no]);		alloc_tab++;	}      end:	/* Transfer ownership of first descriptor to adapter just before	 * exiting. Before that, use memory barrier so that ownership	 * and other fields are seen by adapter correctly.	 */	if (first_rxdp) {		wmb();		first_rxdp->Control_1 |= RXD_OWN_XENA;	}	return SUCCESS;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/ac1f60db6a62c8605b551497c8002ba267ea1f4a/s2io.c/buggy/drivers/net/s2io.c