/* configure LOW_PWR pin */ omap_cfg_reg(T20_1610_LOW_PWR); 
if (cpu_is_omap16xx()) { /* configure LOW_PWR pin */ omap_cfg_reg(T20_1610_LOW_PWR); } 
static int __init omap_pm_init(void){	printk("Power Management for TI OMAP.\n");	/*	 * We copy the assembler sleep/wakeup routines to SRAM.	 * These routines need to be in SRAM as that's the only	 * memory the MPU can see when it wakes up.	 */	if (cpu_is_omap1510()) {		omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,						omap1510_idle_loop_suspend_sz);		omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,						   omap1510_cpu_suspend_sz);	} else if (cpu_is_omap16xx()) {		omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,						omap1610_idle_loop_suspend_sz);		omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,						   omap1610_cpu_suspend_sz);	}	if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {		printk(KERN_ERR "PM not initialized: Missing SRAM support\n");		return -ENODEV;	}	pm_idle = omap_pm_idle;	setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);#if 0	/* --- BEGIN BOARD-DEPENDENT CODE --- */	/* Sleepx mask direction */	omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);	/* Unmask sleepx signal */	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);	/* --- END BOARD-DEPENDENT CODE --- */#endif	/* Program new power ramp-up time	 * (0 for most boards since we don't lower voltage when in deep sleep)	 */	omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);	/* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */	omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);	/* Configure IDLECT3 */	if (cpu_is_omap16xx())		omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);	pm_set_ops(&omap_pm_ops);#if defined(DEBUG) && defined(CONFIG_PROC_FS)	omap_pm_init_proc();#endif	/* configure LOW_PWR pin */	omap_cfg_reg(T20_1610_LOW_PWR);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/1a8bfa1eb998af6e650ad26201f7cae9f2a2fdc8/pm.c/clean/arch/arm/plat-omap/pm.c