create_pte_mapping(base, dart_tablebase, mode_rw, use_largepages); 
BUG_ON(htab_bolt_mapping(base, dart_tablebase, base, mode_rw, mmu_linear_psize)); 
void __init htab_initialize(void){	unsigned long table, htab_size_bytes;	unsigned long pteg_count;	unsigned long mode_rw;	int i, use_largepages = 0;	unsigned long base = 0, size = 0;	extern unsigned long tce_alloc_start, tce_alloc_end;	DBG(" -> htab_initialize()\n");	/*	 * Calculate the required size of the htab.  We want the number of	 * PTEGs to equal one half the number of real pages.	 */ 	htab_size_bytes = get_hashtable_size();	pteg_count = htab_size_bytes >> 7;	/* For debug, make the HTAB 1/8 as big as it normally would be. */	ifppcdebug(PPCDBG_HTABSIZE) {		pteg_count >>= 3;		htab_size_bytes = pteg_count << 7;	}	htab_hash_mask = pteg_count - 1;	if (systemcfg->platform & PLATFORM_LPAR) {		/* Using a hypervisor which owns the htab */		htab_address = NULL;		_SDR1 = 0; 	} else {		/* Find storage for the HPT.  Must be contiguous in		 * the absolute address space.		 */		table = lmb_alloc(htab_size_bytes, htab_size_bytes);		DBG("Hash table allocated at %lx, size: %lx\n", table,		    htab_size_bytes);		if ( !table ) {			ppc64_terminate_msg(0x20, "hpt space");			loop_forever();		}		htab_address = abs_to_virt(table);		/* htab absolute addr + encoded htabsize */		_SDR1 = table + __ilog2(pteg_count) - 11;		/* Initialize the HPT with no entries */		memset((void *)table, 0, htab_size_bytes);	}	mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;	/* On U3 based machines, we need to reserve the DART area and	 * _NOT_ map it to avoid cache paradoxes as it's remapped non	 * cacheable later on	 */	if (cpu_has_feature(CPU_FTR_16M_PAGE))		use_largepages = 1;	/* create bolted the linear mapping in the hash table */	for (i=0; i < lmb.memory.cnt; i++) {		base = lmb.memory.region[i].base + KERNELBASE;		size = lmb.memory.region[i].size;		DBG("creating mapping for region: %lx : %lx\n", base, size);#ifdef CONFIG_U3_DART		/* Do not map the DART space. Fortunately, it will be aligned		 * in such a way that it will not cross two lmb regions and will		 * fit within a single 16Mb page.		 * The DART space is assumed to be a full 16Mb region even if we		 * only use 2Mb of that space. We will use more of it later for		 * AGP GART. We have to use a full 16Mb large page.		 */		DBG("DART base: %lx\n", dart_tablebase);		if (dart_tablebase != 0 && dart_tablebase >= base		    && dart_tablebase < (base + size)) {			if (base != dart_tablebase)				create_pte_mapping(base, dart_tablebase, mode_rw,						   use_largepages);			if ((base + size) > (dart_tablebase + 16*MB))				create_pte_mapping(dart_tablebase + 16*MB, base + size,						   mode_rw, use_largepages);			continue;		}#endif /* CONFIG_U3_DART */		create_pte_mapping(base, base + size, mode_rw, use_largepages);	}	/*	 * If we have a memory_limit and we've allocated TCEs then we need to	 * explicitly map the TCE area at the top of RAM. We also cope with the	 * case that the TCEs start below memory_limit.	 * tce_alloc_start/end are 16MB aligned so the mapping should work	 * for either 4K or 16MB pages.	 */	if (tce_alloc_start) {		tce_alloc_start += KERNELBASE;		tce_alloc_end += KERNELBASE;		if (base + size >= tce_alloc_start)			tce_alloc_start = base + size + 1;		create_pte_mapping(tce_alloc_start, tce_alloc_end,			mode_rw, use_largepages);	}	DBG(" <- htab_initialize()\n");}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3c726f8dee6f55e96475574e9f645327e461884c/hash_utils_64.c/clean/arch/powerpc/mm/hash_utils_64.c