writel(0, PCIEXACCREG); 
pciu_write(PCIEXACCREG, 0); 
static int __init vr41xx_pciu_init(void){	struct pci_controller_unit_setup *setup;	struct pci_master_address_conversion *master;	struct pci_target_address_conversion *target;	struct pci_mailbox_address *mailbox;	struct pci_target_address_window *window;	unsigned long vtclock, pci_clock_max;	uint32_t val;	setup = &vr41xx_pci_controller_unit_setup;	/* Disable PCI interrupt */	vr41xx_disable_pciint();	/* Supply VTClock to PCIU */	vr41xx_supply_clock(PCIU_CLOCK);	/* Dummy write, waiting for supply of VTClock. */	vr41xx_disable_pciint();	/* Select PCI clock */	if (setup->pci_clock_max != 0)		pci_clock_max = setup->pci_clock_max;	else		pci_clock_max = PCI_CLOCK_MAX;	vtclock = vr41xx_get_vtclock_frequency();	if (vtclock < pci_clock_max)		writel(EQUAL_VTCLOCK, PCICLKSELREG);	else if ((vtclock / 2) < pci_clock_max)		writel(HALF_VTCLOCK, PCICLKSELREG);	else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&	         (vtclock / 3) < pci_clock_max)		writel(ONE_THIRD_VTCLOCK, PCICLKSELREG);	else if ((vtclock / 4) < pci_clock_max)		writel(QUARTER_VTCLOCK, PCICLKSELREG);	else {		printk(KERN_ERR "PCI Clock is over 33MHz.\n");		return -EINVAL;	}	/* Supply PCI clock by PCI bus */	vr41xx_supply_clock(PCI_CLOCK);	if (setup->master_memory1 != NULL) {		master = setup->master_memory1;		val = IBA(master->bus_base_address) |		      MASTER_MSK(master->address_mask) |		      WINEN |		      PCIA(master->pci_base_address);		writel(val, PCIMMAW1REG);	} else {		val = readl(PCIMMAW1REG);		val &= ~WINEN;		writel(val, PCIMMAW1REG);	}	if (setup->master_memory2 != NULL) {		master = setup->master_memory2;		val = IBA(master->bus_base_address) |		      MASTER_MSK(master->address_mask) |		      WINEN |		      PCIA(master->pci_base_address);		writel(val, PCIMMAW2REG);	} else {		val = readl(PCIMMAW2REG);		val &= ~WINEN;		writel(val, PCIMMAW2REG);	}	if (setup->target_memory1 != NULL) {		target = setup->target_memory1;		val = TARGET_MSK(target->address_mask) |		      WINEN |		      ITA(target->bus_base_address);		writel(val, PCITAW1REG);	} else {		val = readl(PCITAW1REG);		val &= ~WINEN;		writel(val, PCITAW1REG);	}	if (setup->target_memory2 != NULL) {		target = setup->target_memory2;		val = TARGET_MSK(target->address_mask) |		      WINEN |		      ITA(target->bus_base_address);		writel(val, PCITAW2REG);	} else {		val = readl(PCITAW2REG);		val &= ~WINEN;		writel(val, PCITAW2REG);	}	if (setup->master_io != NULL) {		master = setup->master_io;		val = IBA(master->bus_base_address) |		      MASTER_MSK(master->address_mask) |		      WINEN |		      PCIIA(master->pci_base_address);		writel(val, PCIMIOAWREG);	} else {		val = readl(PCIMIOAWREG);		val &= ~WINEN;		writel(val, PCIMIOAWREG);	}	if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)		writel(UNLOCK, PCIEXACCREG);	else		writel(0, PCIEXACCREG);	if (current_cpu_data.cputype == CPU_VR4122)		writel(TRDYV(setup->wait_time_limit_from_irdy_to_trdy), PCITRDYVREG);	writel(MLTIM(setup->master_latency_timer), LATTIMEREG);	if (setup->mailbox != NULL) {		mailbox = setup->mailbox;		val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |		      MSI_MEMORY | PREF_APPROVAL;		writel(val, MAILBAREG);	}	if (setup->target_window1) {		window = setup->target_window1;		val = PMBA(window->base_address) | TYPE_32BITSPACE |		      MSI_MEMORY | PREF_APPROVAL;		writel(val, PCIMBA1REG);	}	if (setup->target_window2) {		window = setup->target_window2;		val = PMBA(window->base_address) | TYPE_32BITSPACE |		      MSI_MEMORY | PREF_APPROVAL;		writel(val, PCIMBA2REG);	}	val = readl(RETVALREG);	val &= ~RTYVAL_MASK;	val |= RTYVAL(setup->retry_limit);	writel(val, RETVALREG);	val = readl(PCIAPCNTREG);	val &= ~(TKYGNT | PAPC);	switch (setup->arbiter_priority_control) {	case PCI_ARBITRATION_MODE_ALTERNATE_0:		val |= PAPC_ALTERNATE_0;		break;	case PCI_ARBITRATION_MODE_ALTERNATE_B:		val |= PAPC_ALTERNATE_B;		break;	default:		val |= PAPC_FAIR;		break;	}	if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)		val |= TKYGNT_ENABLE;	writel(val, PCIAPCNTREG);	writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |	       PCI_COMMAND_PARITY | PCI_COMMAND_SERR, COMMANDREG);	/* Clear bus error */	readl(BUSERRADREG);	writel(BLOODY_CONFIG_DONE, PCIENREG);	if (setup->mem_resource != NULL)		vr41xx_pci_controller.mem_resource = setup->mem_resource;	if (setup->io_resource != NULL) {		vr41xx_pci_controller.io_resource = setup->io_resource;	} else {		set_io_port_base(IO_PORT_BASE);		ioport_resource.start = IO_PORT_RESOURCE_START;		ioport_resource.end = IO_PORT_RESOURCE_END;	}	register_pci_controller(&vr41xx_pci_controller);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/5dfa9c1b4f5d399a2800d8486ca188988900db87/pci-vr41xx.c/buggy/arch/mips/pci/pci-vr41xx.c