u32 *tbprop; 
u32 *tbprop = NULL; 
static int __init smp_core99_probe(void){#ifdef CONFIG_6xx	extern int powersave_nap;#endif	struct device_node *cpus, *firstcpu;	int i, ncpus = 0, boot_cpu = -1;	u32 *tbprop;	if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);	cpus = firstcpu = find_type_devices("cpu");	while(cpus != NULL) {		u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);		char *stateprop = (char *)get_property(cpus, "state", NULL);		if (regprop != NULL && stateprop != NULL &&		    !strncmp(stateprop, "running", 7))			boot_cpu = *regprop;		++ncpus;		cpus = cpus->next;	}	if (boot_cpu == -1)		printk(KERN_WARNING "Couldn't detect boot CPU !\n");	if (boot_cpu != 0)		printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);	if (machine_is_compatible("MacRISC4")) {		extern struct smp_ops_t core99_smp_ops;		core99_smp_ops.take_timebase = smp_generic_take_timebase;		core99_smp_ops.give_timebase = smp_generic_give_timebase;	} else {		if (firstcpu != NULL)			tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);		if (tbprop)			core99_tb_gpio = *tbprop;		else			core99_tb_gpio = KL_GPIO_TB_ENABLE;	}	if (ncpus > 1) {		openpic_request_IPIs();		for (i = 1; i < ncpus; ++i)			smp_hw_index[i] = i;#ifdef CONFIG_6xx		powersave_nap = 0;#endif		core99_init_caches(0);	}	return ncpus;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/6460b4cceba0181308042c8d8794eb679bfa22e5/pmac_smp.c/buggy/arch/ppc/platforms/pmac_smp.c