ddlprintk((MYIOC_s_INFO_FMT "Write Ext Image: 0x%x bytes @ %p load_addr=%x\n", ioc->name, fwSize*4, ptrFw, load_addr)); 
ddlprintk((MYIOC_s_INFO_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); 
mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag){	MpiFwHeader_t		*pFwHeader;	MpiExtImageHeader_t	*pExtImage;	u32			 fwSize;	u32			 diag0val;	int			 count;	u32			*ptrFw;	u32			 diagRwData;	u32			 nextImage;	u32			 load_addr;	u32 			 ioc_state=0;	ddlprintk((MYIOC_s_INFO_FMT "downloadboot: fw size 0x%x, ioc FW Ptr %p\n",				ioc->name, ioc->facts.FWImageSize, ioc->cached_fw));	if ( ioc->facts.FWImageSize == 0 )		return -1;	if (ioc->cached_fw == NULL)		return -2;	/* prevent a second downloadboot and memory free with alt_ioc */	if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)		ioc->alt_ioc->cached_fw = NULL;	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));	/* wait 1 msec */	if (sleepFlag == CAN_SLEEP) {		msleep_interruptible(1);	} else {		mdelay (1);	}	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);	for (count = 0; count < 30; count ++) {		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);		if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {			ddlprintk((MYIOC_s_INFO_FMT "RESET_ADAPTER cleared, count=%d\n",				ioc->name, count));			break;		}		/* wait 1 sec */		if (sleepFlag == CAN_SLEEP) {			msleep_interruptible (1000);		} else {			mdelay (1000);		}	}	if ( count == 30 ) {		ddlprintk((MYIOC_s_INFO_FMT "downloadboot failed! Unable to RESET_ADAPTER diag0val=%x\n",		ioc->name, diag0val));		return -3;	}	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);	/* Set the DiagRwEn and Disable ARM bits */	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));	pFwHeader = (MpiFwHeader_t *) ioc->cached_fw;	fwSize = (pFwHeader->ImageSize + 3)/4;	ptrFw = (u32 *) pFwHeader;	/* Write the LoadStartAddress to the DiagRw Address Register	 * using Programmed IO	 */	if (ioc->errata_flag_1064)		pci_enable_io_access(ioc->pcidev);	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);	ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n",		ioc->name, pFwHeader->LoadStartAddress));	ddlprintk((MYIOC_s_INFO_FMT "Write FW Image: 0x%x bytes @ %p\n",				ioc->name, fwSize*4, ptrFw));	while (fwSize--) {		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);	}	nextImage = pFwHeader->NextImageHeaderOffset;	while (nextImage) {		pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);		load_addr = pExtImage->LoadStartAddress;		fwSize = (pExtImage->ImageSize + 3) >> 2;		ptrFw = (u32 *)pExtImage;		ddlprintk((MYIOC_s_INFO_FMT "Write Ext Image: 0x%x bytes @ %p load_addr=%x\n",						ioc->name, fwSize*4, ptrFw, load_addr));		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);		while (fwSize--) {			CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);		}		nextImage = pExtImage->NextImageHeaderOffset;	}	/* Write the IopResetVectorRegAddr */	ddlprintk((MYIOC_s_INFO_FMT "Write IopResetVector Addr=%x! \n", ioc->name, 	pFwHeader->IopResetRegAddr));	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);	/* Write the IopResetVectorValue */	ddlprintk((MYIOC_s_INFO_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);	/* Clear the internal flash bad bit - autoincrementing register,	 * so must do two writes.	 */	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);	diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);	diagRwData |= 0x4000000;	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);	if (ioc->errata_flag_1064)		pci_disable_io_access(ioc->pcidev);	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);	ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n",		ioc->name, diag0val));	diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM);	ddlprintk((MYIOC_s_INFO_FMT "downloadboot now diag0val=%x\n",		ioc->name, diag0val));	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);	/* Write 0xFF to reset the sequencer */	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);	for (count=0; count<HZ*20; count++) {		if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {			ddlprintk((MYIOC_s_INFO_FMT "downloadboot successful! (count=%d) IocState=%x\n",					ioc->name, count, ioc_state));			if ((SendIocInit(ioc, sleepFlag)) != 0) {				ddlprintk((MYIOC_s_INFO_FMT "downloadboot: SendIocInit failed\n",					ioc->name));				return -EFAULT;			}			ddlprintk((MYIOC_s_INFO_FMT "downloadboot: SendIocInit successful\n",					ioc->name));			return 0;		}		if (sleepFlag == CAN_SLEEP) {			msleep_interruptible (10);		} else {			mdelay (10);		}	}	ddlprintk((MYIOC_s_INFO_FMT "downloadboot failed! IocState=%x\n",		ioc->name, ioc_state));	return -EFAULT;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/c6678e0cfb41b029c3600c54b5bb65954de1230a/mptbase.c/clean/drivers/message/fusion/mptbase.c