* just restore the calculated DMA boundary 
* now look for chipsets that are known to expose the * DMA bug without failing the test. 
static int __devinit tg3_test_dma(struct tg3 *tp){	dma_addr_t buf_dma;	u32 *buf, saved_dma_rwctrl;	int ret;	buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);	if (!buf) {		ret = -ENOMEM;		goto out_nofree;	}	tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |			  (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));	tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {		/* DMA read watermark not used on PCIE */		tp->dma_rwctrl |= 0x00180000;	} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)			tp->dma_rwctrl |= 0x003f0000;		else			tp->dma_rwctrl |= 0x003f000f;	} else {		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {			u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);			if (ccval == 0x6 || ccval == 0x7)				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;			/* Set bit 23 to enable PCIX hw bug fix */			tp->dma_rwctrl |= 0x009f0000;		} else {			tp->dma_rwctrl |= 0x001b000f;		}	}	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)		tp->dma_rwctrl &= 0xfffffff0;	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {		/* Remove this if it causes problems for some boards. */		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;		/* On 5700/5701 chips, we need to set this bit.		 * Otherwise the chip will issue cacheline transactions		 * to streamable DMA memory with not all the byte		 * enables turned on.  This is an error on several		 * RISC PCI controllers, in particular sparc64.		 *		 * On 5703/5704 chips, this bit has been reassigned		 * a different meaning.  In particular, it is used		 * on those chips to enable a PCI-X workaround.		 */		tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;	}	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);#if 0	/* Unneeded, already done by tg3_get_invariants.  */	tg3_switch_clocks(tp);#endif	ret = 0;	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)		goto out;	/* It is best to perform DMA test with maximum write burst size	 * to expose the 5700/5701 write DMA bug.	 */	saved_dma_rwctrl = tp->dma_rwctrl;	tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);	while (1) {		u32 *p = buf, i;		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)			p[i] = i;		/* Send the buffer to the chip. */		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);		if (ret) {			printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);			break;		}#if 0		/* validate data reached card RAM correctly. */		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {			u32 val;			tg3_read_mem(tp, 0x2100 + (i*4), &val);			if (le32_to_cpu(val) != p[i]) {				printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);				/* ret = -ENODEV here? */			}			p[i] = 0;		}#endif		/* Now read it back. */		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);		if (ret) {			printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);			break;		}		/* Verify it. */		for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {			if (p[i] == i)				continue;			if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=			    DMA_RWCTRL_WRITE_BNDRY_16) {				tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;				tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;				tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);				break;			} else {				printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);				ret = -ENODEV;				goto out;			}		}		if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {			/* Success. */			ret = 0;			break;		}	}	if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=	    DMA_RWCTRL_WRITE_BNDRY_16) {		/* DMA test passed without adjusting DMA boundary,		 * just restore the calculated DMA boundary		 */		tp->dma_rwctrl = saved_dma_rwctrl;		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);	}out:	pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);out_nofree:	return ret;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/6d1cfbab4de64f2d0c5b0f81177ade0d75b69288/tg3.c/clean/drivers/net/tg3.c