/* looks like this xl is back asswards .. */ 
/* looks like this XL is back asswards .. */ 
static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state){	u16 power_control;	u32 reg1;	int vaux;	int ret = 0;	pr_debug("sky2_set_power_state %d\n", state);	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);	pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);	vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&		(power_control & PCI_PM_CAP_PME_D3cold);	pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);	power_control |= PCI_PM_CTRL_PME_STATUS;	power_control &= ~(PCI_PM_CTRL_STATE_MASK);	switch (state) {	case PCI_D0:		/* switch power to VCC (WA for VAUX problem) */		sky2_write8(hw, B0_POWER_CTRL,			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);		/* disable Core Clock Division, */		sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)			/* enable bits are inverted */			sky2_write8(hw, B2_Y2_CLK_GATE,				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);		else			sky2_write8(hw, B2_Y2_CLK_GATE, 0);		/* Turn off phy power saving */		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);		/* looks like this xl is back asswards .. */		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {			reg1 |= PCI_Y2_PHY1_COMA;			if (hw->ports > 1)				reg1 |= PCI_Y2_PHY2_COMA;		}		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);		break;	case PCI_D3hot:	case PCI_D3cold:		/* Turn on phy power saving */		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);		else			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)			sky2_write8(hw, B2_Y2_CLK_GATE, 0);		else			/* enable bits are inverted */			sky2_write8(hw, B2_Y2_CLK_GATE,				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);		/* switch power to VAUX */		if (vaux && state != PCI_D3cold)			sky2_write8(hw, B0_POWER_CTRL,				    (PC_VAUX_ENA | PC_VCC_ENA |				     PC_VAUX_ON | PC_VCC_OFF));		break;	default:		printk(KERN_ERR PFX "Unknown power state %d\n", state);		ret = -1;	}	pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);	return ret;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d571b694df3ebc66f7a4c507f5a32579e43c2294/sky2.c/buggy/drivers/net/sky2.c