"	.set	noreorder	# test_and_clear_bit	\n" "1:	" __LL	"%0, %1					\n" 
"	.set	push					\n" "	.set	noreorder				\n" "	" __SET_MIPS "					\n" "1:	" __LL	"%0, %1		# test_and_clear_bit	\n" 
static inline int test_and_clear_bit(unsigned long nr,	volatile unsigned long *addr){	if (cpu_has_llsc && R10000_LLSC_WAR) {		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);		unsigned long temp, res;		__asm__ __volatile__(		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"		"	or	%2, %0, %3				\n"		"	xor	%2, %3					\n"			__SC 	"%2, %1					\n"		"	beqzl	%2, 1b					\n"		"	and	%2, %0, %3				\n"#ifdef CONFIG_SMP		"	sync						\n"#endif		: "=&r" (temp), "=m" (*m), "=&r" (res)		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)		: "memory");		return res != 0;	} else if (cpu_has_llsc) {		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);		unsigned long temp, res;		__asm__ __volatile__(		"	.set	noreorder	# test_and_clear_bit	\n"		"1:	" __LL	"%0, %1					\n"		"	or	%2, %0, %3				\n"		"	xor	%2, %3					\n"			__SC 	"%2, %1					\n"		"	beqz	%2, 1b					\n"		"	 and	%2, %0, %3				\n"#ifdef CONFIG_SMP		"	sync						\n"#endif		"	.set	reorder					\n"		: "=&r" (temp), "=m" (*m), "=&r" (res)		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)		: "memory");		return res != 0;	} else {		volatile unsigned long *a = addr;		unsigned long mask;		int retval;		__bi_flags;		a += nr >> SZLONG_LOG;		mask = 1UL << (nr & SZLONG_MASK);		__bi_local_irq_save(flags);		retval = (mask & *a) != 0;		*a &= ~mask;		__bi_local_irq_restore(flags);		return retval;	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/aac8aa7717a23a9bf8740dbfb59755b1d62f04bf/bitops.h/buggy/include/asm-mips/bitops.h