} if (pci_set_dma_mask(pdev, CCISS_DMA_MASK ) != 0) { printk(KERN_ERR "cciss:  Unable to set DMA mask\n"); return(-1); 
static int cciss_pci_init(ctlr_info_t *c, struct pci_dev *pdev){	ushort subsystem_vendor_id, subsystem_device_id, command;	__u32 board_id, scratchpad = 0;	__u64 cfg_offset;	__u32 cfg_base_addr;	__u64 cfg_base_addr_index;	int i;	/* check to see if controller has been disabled */	/* BEFORE trying to enable it */	(void) pci_read_config_word(pdev, PCI_COMMAND,&command);	if(!(command & 0x02))	{		printk(KERN_WARNING "cciss: controller appears to be disabled\n");		return(-1);	}	if (pci_enable_device(pdev))	{		printk(KERN_ERR "cciss: Unable to Enable PCI device\n");		return( -1);	}	if (pci_set_dma_mask(pdev, CCISS_DMA_MASK ) != 0)	{		printk(KERN_ERR "cciss:  Unable to set DMA mask\n");		return(-1);	}	subsystem_vendor_id = pdev->subsystem_vendor;	subsystem_device_id = pdev->subsystem_device;	board_id = (((__u32) (subsystem_device_id << 16) & 0xffff0000) |					subsystem_vendor_id);	/* search for our IO range so we can protect it */	for(i=0; i<DEVICE_COUNT_RESOURCE; i++)	{		/* is this an IO range */ 		if( pci_resource_flags(pdev, i) & 0x01 ) {			c->io_mem_addr = pci_resource_start(pdev, i);			c->io_mem_length = pci_resource_end(pdev, i) -				pci_resource_start(pdev, i) +1;#ifdef CCISS_DEBUG			printk("IO value found base_addr[%d] %lx %lx\n", i,				c->io_mem_addr, c->io_mem_length);#endif /* CCISS_DEBUG */			/* register the IO range */ 			if(!request_region( c->io_mem_addr,                                        c->io_mem_length, "cciss"))			{				printk(KERN_WARNING "cciss I/O memory range already in use addr=%lx length=%ld\n",				c->io_mem_addr, c->io_mem_length);				c->io_mem_addr= 0;				c->io_mem_length = 0;			} 			break;		}	}#ifdef CCISS_DEBUG	printk("command = %x\n", command);	printk("irq = %x\n", pdev->irq);	printk("board_id = %x\n", board_id);#endif /* CCISS_DEBUG */ 	c->intr = pdev->irq;	/*	 * Memory base addr is first addr , the second points to the config         *   table	 */	c->paddr = pci_resource_start(pdev, 0); /* addressing mode bits already removed */#ifdef CCISS_DEBUG	printk("address 0 = %x\n", c->paddr);#endif /* CCISS_DEBUG */ 	c->vaddr = remap_pci_mem(c->paddr, 200);	/* Wait for the board to become ready.  (PCI hotplug needs this.)	 * We poll for up to 120 secs, once per 100ms. */	for (i=0; i < 1200; i++) {		scratchpad = readl(c->vaddr + SA5_SCRATCHPAD_OFFSET);		if (scratchpad == CCISS_FIRMWARE_READY)			break;		set_current_state(TASK_INTERRUPTIBLE);		schedule_timeout(HZ / 10); /* wait 100ms */	}	if (scratchpad != CCISS_FIRMWARE_READY) {		printk(KERN_WARNING "cciss: Board not ready.  Timed out.\n");		return -1;	}	/* get the address index number */	cfg_base_addr = readl(c->vaddr + SA5_CTCFG_OFFSET);	cfg_base_addr &= (__u32) 0x0000ffff;#ifdef CCISS_DEBUG	printk("cfg base address = %x\n", cfg_base_addr);#endif /* CCISS_DEBUG */	cfg_base_addr_index =		find_PCI_BAR_index(pdev, cfg_base_addr);#ifdef CCISS_DEBUG	printk("cfg base address index = %x\n", cfg_base_addr_index);#endif /* CCISS_DEBUG */	if (cfg_base_addr_index == -1) {		printk(KERN_WARNING "cciss: Cannot find cfg_base_addr_index\n");		release_io_mem(c);		return -1;	}	cfg_offset = readl(c->vaddr + SA5_CTMEM_OFFSET);#ifdef CCISS_DEBUG	printk("cfg offset = %x\n", cfg_offset);#endif /* CCISS_DEBUG */	c->cfgtable =  remap_pci_mem(pci_resource_start(pdev,				cfg_base_addr_index) + cfg_offset,				sizeof(CfgTable_struct));	c->board_id = board_id;#ifdef CCISS_DEBUG	print_cfg_table(c->cfgtable); #endif /* CCISS_DEBUG */	for(i=0; i<NR_PRODUCTS; i++) {		if (board_id == products[i].board_id) {			c->product_name = products[i].product_name;			c->access = *(products[i].access);			break;		}	}	if (i == NR_PRODUCTS) {		printk(KERN_WARNING "cciss: Sorry, I don't know how"			" to access the Smart Array controller %08lx\n", 				(unsigned long)board_id);		return -1;	}	if (  (readb(&c->cfgtable->Signature[0]) != 'C') ||	      (readb(&c->cfgtable->Signature[1]) != 'I') ||	      (readb(&c->cfgtable->Signature[2]) != 'S') ||	      (readb(&c->cfgtable->Signature[3]) != 'S') )	{		printk("Does not appear to be a valid CISS config table\n");		return -1;	}#ifdef CONFIG_X86{	/* Need to enable prefetch in the SCSI core for 6400 in x86 */	__u32 prefetch;	prefetch = readl(&(c->cfgtable->SCSI_Prefetch));	prefetch |= 0x100;	writel(prefetch, &(c->cfgtable->SCSI_Prefetch));}#endif#ifdef CCISS_DEBUG	printk("Trying to put board into Simple mode\n");#endif /* CCISS_DEBUG */ 	c->max_commands = readl(&(c->cfgtable->CmdsOutMax));	/* Update the field, and then ring the doorbell */ 	writel( CFGTBL_Trans_Simple, 		&(c->cfgtable->HostWrite.TransportRequest));	writel( CFGTBL_ChangeReq, c->vaddr + SA5_DOORBELL);	/* under certain very rare conditions, this can take awhile.	 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right	 * as we enter this code.) */	for(i=0;i<MAX_CONFIG_WAIT;i++) {		if (!(readl(c->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))			break;		/* delay and try again */		set_current_state(TASK_INTERRUPTIBLE);		schedule_timeout(10);	}	#ifdef CCISS_DEBUG	printk(KERN_DEBUG "I counter got to %d %x\n", i, readl(c->vaddr + SA5_DOORBELL));#endif /* CCISS_DEBUG */#ifdef CCISS_DEBUG	print_cfg_table(c->cfgtable);	#endif /* CCISS_DEBUG */ 	if (!(readl(&(c->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))	{		printk(KERN_WARNING "cciss: unable to get board into"					" simple mode\n");		return -1;	}	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/eb0df9962d97f7156a0870aced9018bf5c8f54c1/cciss.c/clean/drivers/block/cciss.c