void te_config(pc300_t * card, int ch) 
static void te_config(pc300_t * card, int ch) 
void te_config(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	void __iomem *falcbase = card->hw.falcbase;	ucchar dummy;	unsigned long flags;	memset(pfalc, 0, sizeof(falc_t));	switch (conf->media) {		case IF_IFACE_T1:			pfalc->num_channels = NUM_OF_T1_CHANNELS;			pfalc->offset = 1;			break;		case IF_IFACE_E1:			pfalc->num_channels = NUM_OF_E1_CHANNELS;			pfalc->offset = 0;			break;	}	if (conf->tslot_bitmap == 0xffffffffUL)		pfalc->full_bandwidth = 1;	else		pfalc->full_bandwidth = 0;	CPC_LOCK(card, flags);	/* Reset the FALC chip */	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |		   (CPLD_REG1_FALC_RESET << (2 * ch)));	udelay(10000);	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &		   ~(CPLD_REG1_FALC_RESET << (2 * ch)));	if (conf->media == IF_IFACE_T1) {		falc_init_t1(card, ch);	} else {		falc_init_e1(card, ch);	}	falc_init_hdlc(card, ch);	if (conf->rx_sens == PC300_RX_SENS_SH) {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);	} else {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);	}	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |		   ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));	/* Clear all interrupt registers */	dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +		cpc_readb(falcbase + F_REG(FISR1, ch)) +		cpc_readb(falcbase + F_REG(FISR2, ch)) +		cpc_readb(falcbase + F_REG(FISR3, ch));	CPC_UNLOCK(card, flags);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7665a08928f241247afe8c76865cdbe4ef5489bf/pc300_drv.c/buggy/drivers/net/wan/pc300_drv.c