set_rx_timeout(port, port->ip_rx_timeout); 
set_rx_timeout(port, 2); 
config_port(struct ioc4_port *port,	    int baud, int byte_size, int stop_bits, int parenb, int parodd){	char lcr, sizebits;	int spiniter = 0;	DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",		__FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));	if (set_baud(port, baud))		return 1;	switch (byte_size) {	case 5:		sizebits = UART_LCR_WLEN5;		break;	case 6:		sizebits = UART_LCR_WLEN6;		break;	case 7:		sizebits = UART_LCR_WLEN7;		break;	case 8:		sizebits = UART_LCR_WLEN8;		break;	default:		return 1;	}	/* Pause the DMA interface if necessary */	if (port->ip_sscr & IOC4_SSCR_DMA_EN) {		writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,			&port->ip_serial_regs->sscr);		while((readl(&port->ip_serial_regs->sscr)						& IOC4_SSCR_PAUSE_STATE) == 0) {			spiniter++;			if (spiniter > MAXITER)				return -1;		}	}	/* Clear relevant fields in lcr */	lcr = readb(&port->ip_uart_regs->i4u_lcr);	lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |		 UART_LCR_PARITY | LCR_MASK_STOP_BITS);	/* Set byte size in lcr */	lcr |= sizebits;	/* Set parity */	if (parenb) {		lcr |= UART_LCR_PARITY;		if (!parodd)			lcr |= UART_LCR_EPAR;	}	/* Set stop bits */	if (stop_bits)		lcr |= UART_LCR_STOP /* 2 stop bits */ ;	writeb(lcr, &port->ip_uart_regs->i4u_lcr);	/* Re-enable the DMA interface if necessary */	if (port->ip_sscr & IOC4_SSCR_DMA_EN) {		writel(port->ip_sscr, &port->ip_serial_regs->sscr);	}	port->ip_baud = baud;	/* When we get within this number of ring entries of filling the	 * entire ring on tx, place an EXPLICIT intr to generate a lowat	 * notification when output has drained.	 */	port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;	if (port->ip_tx_lowat == 0)		port->ip_tx_lowat = 1;	set_rx_timeout(port, port->ip_rx_timeout);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/6cb2875f8d7e392982229094ad3b6d2f213f48da/ioc4_serial.c/clean/drivers/serial/ioc4_serial.c