XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0; 
XENA_dev_config_t __iomem *bar0 = sp->bar0; 
static void s2io_txpic_intr_handle(nic_t *sp){	XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;	u64 val64;	val64 = readq(&bar0->pic_int_status);	if (val64 & PIC_INT_GPIO) {		val64 = readq(&bar0->gpio_int_reg);		if ((val64 & GPIO_INT_REG_LINK_DOWN) &&		    (val64 & GPIO_INT_REG_LINK_UP)) {			val64 |=  GPIO_INT_REG_LINK_DOWN;			val64 |= GPIO_INT_REG_LINK_UP;			writeq(val64, &bar0->gpio_int_reg);			goto masking;		}		if (((sp->last_link_state == LINK_UP) &&			(val64 & GPIO_INT_REG_LINK_DOWN)) ||		((sp->last_link_state == LINK_DOWN) &&		(val64 & GPIO_INT_REG_LINK_UP))) {			val64 = readq(&bar0->gpio_int_mask);			val64 |=  GPIO_INT_MASK_LINK_DOWN;			val64 |= GPIO_INT_MASK_LINK_UP;			writeq(val64, &bar0->gpio_int_mask);			s2io_set_link((unsigned long)sp);		}masking:		if (sp->last_link_state == LINK_UP) {			/*enable down interrupt */			val64 = readq(&bar0->gpio_int_mask);			/* unmasks link down intr */			val64 &=  ~GPIO_INT_MASK_LINK_DOWN;			/* masks link up intr */			val64 |= GPIO_INT_MASK_LINK_UP;			writeq(val64, &bar0->gpio_int_mask);		} else {			/*enable UP Interrupt */			val64 = readq(&bar0->gpio_int_mask);			/* unmasks link up interrupt */			val64 &= ~GPIO_INT_MASK_LINK_UP;			/* masks link down interrupt */			val64 |=  GPIO_INT_MASK_LINK_DOWN;			writeq(val64, &bar0->gpio_int_mask);		}	}}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/509a2671a445345d917d8828b2cb3f5743af6093/s2io.c/buggy/drivers/net/s2io.c