{ set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(1); } 
schedule_timeout_uninterruptible(1); 
static int __init NCR5380_probe_irq(struct Scsi_Host *instance, int possible){	NCR5380_local_declare();	struct NCR5380_hostdata *hostdata = (struct NCR5380_hostdata *) instance->hostdata;	unsigned long timeout;	int trying_irqs, i, mask;	NCR5380_setup(instance);	for (trying_irqs = i = 0, mask = 1; i < 16; ++i, mask <<= 1)		if ((mask & possible) && (request_irq(i, &probe_intr, SA_INTERRUPT, "NCR-probe", NULL) == 0))			trying_irqs |= mask;	timeout = jiffies + (250 * HZ / 1000);	probe_irq = SCSI_IRQ_NONE;	/*	 * A interrupt is triggered whenever BSY = false, SEL = true	 * and a bit set in the SELECT_ENABLE_REG is asserted on the 	 * SCSI bus.	 *	 * Note that the bus is only driven when the phase control signals	 * (I/O, C/D, and MSG) match those in the TCR, so we must reset that	 * to zero.	 */	NCR5380_write(TARGET_COMMAND_REG, 0);	NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);	NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL);	while (probe_irq == SCSI_IRQ_NONE && time_before(jiffies, timeout))	{		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout(1);	}		NCR5380_write(SELECT_ENABLE_REG, 0);	NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);	for (i = 0, mask = 1; i < 16; ++i, mask <<= 1)		if (trying_irqs & mask)			free_irq(i, NULL);	return probe_irq;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a9a3047dd8ae43ff24caae5ec733a93df129568e/NCR5380.c/clean/drivers/scsi/NCR5380.c