 current->thread.fpscr.val = 0;	/* turn off all fp exceptions */ 
static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,		int sigret){#ifdef CONFIG_PPC32	CHECK_FULL_REGS(regs);#endif	/* Make sure floating point registers are stored in regs */	flush_fp_to_thread(current);	/* save general and floating-point registers */	if (save_general_regs(regs, frame) ||	    __copy_to_user(&frame->mc_fregs, current->thread.fpr,		    ELF_NFPREG * sizeof(double)))		return 1;	current->thread.fpscr.val = 0;	/* turn off all fp exceptions */#ifdef CONFIG_ALTIVEC	/* save altivec registers */	if (current->thread.used_vr) {		flush_altivec_to_thread(current);		if (__copy_to_user(&frame->mc_vregs, current->thread.vr,				   ELF_NVRREG * sizeof(vector128)))			return 1;		/* set MSR_VEC in the saved MSR value to indicate that		   frame->mc_vregs contains valid data */		if (__put_user(regs->msr | MSR_VEC, &frame->mc_gregs[PT_MSR]))			return 1;	}	/* else assert((regs->msr & MSR_VEC) == 0) */	/* We always copy to/from vrsave, it's 0 if we don't have or don't	 * use altivec. Since VSCR only contains 32 bits saved in the least	 * significant bits of a vector, we "cheat" and stuff VRSAVE in the	 * most significant bits of that same vector. --BenH	 */	if (__put_user(current->thread.vrsave, (u32 __user *)&frame->mc_vregs[32]))		return 1;#endif /* CONFIG_ALTIVEC */#ifdef CONFIG_SPE	/* save spe registers */	if (current->thread.used_spe) {		flush_spe_to_thread(current);		if (__copy_to_user(&frame->mc_vregs, current->thread.evr,				   ELF_NEVRREG * sizeof(u32)))			return 1;		/* set MSR_SPE in the saved MSR value to indicate that		   frame->mc_vregs contains valid data */		if (__put_user(regs->msr | MSR_SPE, &frame->mc_gregs[PT_MSR]))			return 1;	}	/* else assert((regs->msr & MSR_SPE) == 0) */	/* We always copy to/from spefscr */	if (__put_user(current->thread.spefscr, (u32 __user *)&frame->mc_vregs + ELF_NEVRREG))		return 1;#endif /* CONFIG_SPE */	if (sigret) {		/* Set up the sigreturn trampoline: li r0,sigret; sc */		if (__put_user(0x38000000UL + sigret, &frame->tramp[0])		    || __put_user(0x44000002UL, &frame->tramp[1]))			return 1;		flush_icache_range((unsigned long) &frame->tramp[0],				   (unsigned long) &frame->tramp[2]);	}	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/cc657f53928997c65bf2409c45166c6ceee8d306/signal_32.c/buggy/arch/powerpc/kernel/signal_32.c