cached_kn02_csr = *csr | KN03_CSR_LEDS; 
cached_kn02_csr = *csr | KN02_CSR_LEDS; 
static inline void dec_kn02_be_init(void){	volatile u32 *csr = (void *)KN02_CSR_BASE;	unsigned long flags;	kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR);	kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN);	spin_lock_irqsave(&kn02_lock, flags);	/* Preset write-only bits of the Control Register cache. */	cached_kn02_csr = *csr | KN03_CSR_LEDS;	/* Set normal ECC detection and generation. */	cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);	/* Enable ECC correction. */	cached_kn02_csr |= KN02_CSR_CORRECT;	*csr = cached_kn02_csr;	iob();	spin_unlock_irqrestore(&kn02_lock, flags);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/64dac503e8265007ea5c53b4d6bf42488a8a8d7a/ecc-berr.c/buggy/arch/mips/dec/ecc-berr.c