case TDA10046_FREQ_045: tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); break; case TDA10046_FREQ_052: tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06); break; 
static void tda10046_init_plls(struct dvb_frontend* fe){	struct tda1004x_state* state = fe->demodulator_priv;	tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);	tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10	if (state->config->xtal_freq == TDA10046_XTAL_4M ) {		dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);		tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0	} else {		dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);		tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3	}	tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);	switch (state->config->if_freq) {	case TDA10046_FREQ_3617:		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);		break;	case TDA10046_FREQ_3613:		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);		break;	}	tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f03cbea36ab9412dcea58e953be4933b36c9b7be/tda1004x.c/clean/drivers/media/dvb/frontends/tda1004x.c