if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */ apic_write(APIC_ESR, 0); 
void __cpuinit setup_local_APIC (void){	unsigned int value, ver, maxlvt;	value = apic_read(APIC_LVR);	ver = GET_APIC_VERSION(value);	if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)		__error_in_apic_c();	/*	 * Double-check whether this APIC is really registered.	 * This is meaningless in clustered apic mode, so we skip it.	 */	if (!apic_id_registered())		BUG();	/*	 * Intel recommends to set DFR, LDR and TPR before enabling	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel	 * document number 292116).  So here it goes...	 */	init_apic_ldr();	/*	 * Set Task Priority to 'accept all'. We never change this	 * later on.	 */	value = apic_read(APIC_TASKPRI);	value &= ~APIC_TPRI_MASK;	apic_write_around(APIC_TASKPRI, value);	/*	 * Now that we are all set up, enable the APIC	 */	value = apic_read(APIC_SPIV);	value &= ~APIC_VECTOR_MASK;	/*	 * Enable APIC	 */	value |= APIC_SPIV_APIC_ENABLED;	/*	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with	 * certain networking cards. If high frequency interrupts are	 * happening on a particular IOAPIC pin, plus the IOAPIC routing	 * entry is masked/unmasked at a high rate as well then sooner or	 * later IOAPIC line gets 'stuck', no more interrupts are received	 * from the device. If focus CPU is disabled then the hang goes	 * away, oh well :-(	 *	 * [ This bug can be reproduced easily with a level-triggered	 *   PCI Ne2000 networking cards and PII/PIII processors, dual	 *   BX chipset. ]	 */	/*	 * Actually disabling the focus CPU check just makes the hang less	 * frequent as it makes the interrupt distributon model be more	 * like LRU than MRU (the short-term load is more even across CPUs).	 * See also the comment in end_level_ioapic_irq().  --macro	 */#if 1	/* Enable focus processor (bit==0) */	value &= ~APIC_SPIV_FOCUS_DISABLED;#else	/* Disable focus processor (bit==1) */	value |= APIC_SPIV_FOCUS_DISABLED;#endif	/*	 * Set spurious IRQ vector	 */	value |= SPURIOUS_APIC_VECTOR;	apic_write_around(APIC_SPIV, value);	/*	 * Set up LVT0, LVT1:	 *	 * set up through-local-APIC on the BP's LINT0. This is not	 * strictly necessary in pure symmetric-IO mode, but sometimes	 * we delegate interrupts to the 8259A.	 */	/*	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro	 */	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;	if (!smp_processor_id() && (pic_mode || !value)) {		value = APIC_DM_EXTINT;		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());	} else {		value = APIC_DM_EXTINT | APIC_LVT_MASKED;		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());	}	apic_write_around(APIC_LVT0, value);	/*	 * only the BP should see the LINT1 NMI signal, obviously.	 */	if (!smp_processor_id())		value = APIC_DM_NMI;	else		value = APIC_DM_NMI | APIC_LVT_MASKED;	if (!APIC_INTEGRATED(ver))		/* 82489DX */		value |= APIC_LVT_LEVEL_TRIGGER;	apic_write_around(APIC_LVT1, value);	{		unsigned oldvalue;		maxlvt = get_maxlvt();		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */			apic_write(APIC_ESR, 0);		oldvalue = apic_read(APIC_ESR);		value = ERROR_APIC_VECTOR;      // enables sending errors		apic_write_around(APIC_LVTERR, value);		/*		 * spec says clear errors after enabling vector.		 */		if (maxlvt > 3)			apic_write(APIC_ESR, 0);		value = apic_read(APIC_ESR);		if (value != oldvalue)			apic_printk(APIC_VERBOSE,			"ESR value after enabling vector: %08x, after %08x\n",			oldvalue, value);	}	nmi_watchdog_default();	if (nmi_watchdog == NMI_LOCAL_APIC)		setup_apic_nmi_watchdog();	apic_pm_activate();}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/5a40b7c2abdedcf53c9a6ee790991acfcef5b6c7/apic.c/buggy/arch/x86_64/kernel/apic.c