immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) | SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10; 
immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr & ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) | SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10); 
pq2ads_setup_pci(struct pci_controller *hose){	__u32 val;	volatile cpm2_map_t *immap = cpm2_immr;	bd_t* binfo = (bd_t*) __res;	u32 sccr = immap->im_clkrst.car_sccr;	uint pci_div,freq,time;		/* PCI int lowest prio */	/* Each 4 bits is a device bus request	and the MS 4bits	 is highest priority */	/* Bus                4bit value	   ---                ----------	   CPM high      	0b0000	   CPM middle           0b0001	   CPM low       	0b0010	   PCI reguest          0b0011	   Reserved      	0b0100	   Reserved      	0b0101	   Internal Core     	0b0110	   External Master 1 	0b0111	   External Master 2 	0b1000	   External Master 3 	0b1001	   The rest are reserved	 */	immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;	/* park bus on core */	immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;	/*	 * Set up master windows that allow the CPU to access PCI space. These	 * windows are set up using the two SIU PCIBR registers.	 */	immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;	immap->im_memctl.memc_pcibr0  = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;#ifdef M82xx_PCI_SEC_WND_SIZE	immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;	immap->im_memctl.memc_pcibr1  = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;#endif#if defined CONFIG_ADS8272	immap->im_siu_conf.siu_82xx.sc_siumcr =		(immap->im_siu_conf.siu_82xx.sc_siumcr &		~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |		SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |		SIUMCR_LBPC11 | SIUMCR_APPC11 |		SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |		SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |		SIUMCR_APPC10 | SIUMCR_CS10PC00 |		SIUMCR_BCTLC00 | SIUMCR_MMR11 ;#elif defined CONFIG_PQ2FADS	/*	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),	 * and local bus for PCI (SIUMCR [LBPC]).	 */	immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &				~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |				SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;#endif	/* Enable PCI  */	immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);	pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *			( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);	freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));	time = (int)666666/freq;	/* due to PCI Local Bus spec, some devices needs to wait such a long	time after RST 	deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */	printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,	(time==1) ? "0.5 seconds":"1 second" );	{		int i;		for(i=0;i<(500*time);i++)			udelay(1000);	}	/* setup ATU registers */	immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |				((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));	immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);	immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);	/* Set-up non-prefetchable window */	immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));	immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);	immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);	/* Set-up prefetchable window */	immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |		(~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));	immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);	immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT); 	/* Inbound transactions from PCI memory space */	immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |					((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));	immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS  >> PITA_ADDR_SHIFT);	immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);#if defined CONFIG_ADS8272	/* PCI int highest prio */	immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;#elif defined CONFIG_PQ2FADS	immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;#endif	/* park bus on PCI */	immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;	/* Enable bus mastering and inbound memory transactions */	early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);	val &= 0xffff0000;	val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;	early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/c41b72d5bd590e6ff781d6bdfc71595f3996bacf/m82xx_pci.c/clean/arch/ppc/syslib/m82xx_pci.c