tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; 
tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 
static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,				     long npages, unsigned long uaddr,				     enum dma_data_direction direction){	u64 rc;	union tce_entry tce, *tcep;	long l, limit;	if (npages == 1)		return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,					   direction);	tcep = __get_cpu_var(tce_page);	/* This is safe to do since interrupts are off when we're called	 * from iommu_alloc{,_sg}()	 */	if (!tcep) {		tcep = (void *)__get_free_page(GFP_ATOMIC);		/* If allocation fails, fall back to the loop implementation */		if (!tcep)			return tce_build_pSeriesLP(tbl, tcenum, npages,						   uaddr, direction);		__get_cpu_var(tce_page) = tcep;	}	tce.te_word = 0;	tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT;	tce.te_rdwr = 1;	if (direction != DMA_TO_DEVICE)		tce.te_pciwr = 1;	/* We can map max one pageful of TCEs at a time */	do {		/*		 * Set up the page with TCE data, looping through and setting		 * the values.		 */		limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry));		for (l = 0; l < limit; l++) {			tcep[l] = tce;			tce.te_rpn++;		}		rc = plpar_tce_put_indirect((u64)tbl->it_index,					    (u64)tcenum << 12,					    (u64)virt_to_abs(tcep),					    limit);		npages -= limit;		tcenum += limit;	} while (npages > 0 && !rc);	if (rc && printk_ratelimit()) {		printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);		printk("\tindex   = 0x%lx\n", (u64)tbl->it_index);		printk("\tnpages  = 0x%lx\n", (u64)npages);		printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);		show_stack(current, (unsigned long *)__get_SP());	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d0035c62d9145a2ce3057c8182a7ff0b4921a41c/pSeries_iommu.c/clean/arch/ppc64/kernel/pSeries_iommu.c