ROT_IN_PIECES 
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val){	__u32 retval;	if (cpu_has_llsc && R10000_LLSC_WAR) {		unsigned long dummy;		__asm__ __volatile__(		"	.set	mips3					\n"		"1:	ll	%0, %3			# xchg_u32	\n"		"	.set	mips0					\n"		"	move	%2, %z4					\n"		"	.set	mips3					\n"		"	sc	%2, %1					\n"		"	beqzl	%2, 1b					\n"		ROT_IN_PIECES#ifdef CONFIG_SMP		"	sync						\n"#endif		"	.set	mips0					\n"		: "=&r" (retval), "=m" (*m), "=&r" (dummy)		: "R" (*m), "Jr" (val)		: "memory");	} else if (cpu_has_llsc) {		unsigned long dummy;		__asm__ __volatile__(		"	.set	mips3					\n"		"1:	ll	%0, %3			# xchg_u32	\n"		"	.set	mips0					\n"		"	move	%2, %z4					\n"		"	.set	mips3					\n"		"	sc	%2, %1					\n"		"	beqz	%2, 1b					\n"#ifdef CONFIG_SMP		"	sync						\n"#endif		"	.set	mips0					\n"		: "=&r" (retval), "=m" (*m), "=&r" (dummy)		: "R" (*m), "Jr" (val)		: "memory");	} else {		unsigned long flags;		local_irq_save(flags);		retval = *m;		*m = val;		local_irq_restore(flags);	/* implies memory barrier  */	}	return retval;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/fabffc13ed720eea986f80f432cedb4550f464ed/system.h/clean/include/asm-mips/system.h