struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv; 
struct stv0297_state *state = fe->demodulator_priv; 
static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p){	struct stv0297_state *state = (struct stv0297_state *) fe->demodulator_priv;	int u_threshold;	int initial_u;	int blind_u;	int delay;	int sweeprate;	int carrieroffset;	unsigned long starttime;	unsigned long timeout;	fe_spectral_inversion_t inversion;	switch (p->u.qam.modulation) {	case QAM_16:	case QAM_32:	case QAM_64:		delay = 100;		sweeprate = 1500;		break;	case QAM_128:		delay = 150;		sweeprate = 1000;		break;	case QAM_256:		delay = 200;		sweeprate = 500;		break;	default:		return -EINVAL;	}	// determine inversion dependant parameters	inversion = p->inversion;	if (state->config->invert)		inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;	carrieroffset = -330;	switch (inversion) {	case INVERSION_OFF:		break;	case INVERSION_ON:		sweeprate = -sweeprate;		carrieroffset = -carrieroffset;		break;	default:		return -EINVAL;	}	stv0297_init(fe);	state->config->pll_set(fe, p);	/* clear software interrupts */	stv0297_writereg(state, 0x82, 0x0);	/* set initial demodulation frequency */	stv0297_set_initialdemodfreq(state, 7250);	/* setup AGC */	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);	stv0297_writereg(state, 0x41, 0x00);	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);	stv0297_writereg(state, 0x72, 0x00);	stv0297_writereg(state, 0x73, 0x00);	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);	/* setup STL */	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);	/* disable frequency sweep */	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);	/* reset deinterleaver */	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);	/* ??? */	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);	/* reset equaliser */	u_threshold = stv0297_readreg(state, 0x00) & 0xf;	initial_u = stv0297_readreg(state, 0x01) >> 4;	blind_u = stv0297_readreg(state, 0x01) & 0xf;	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);	/* data comes from internal A/D */	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);	/* clear phase registers */	stv0297_writereg(state, 0x63, 0x00);	stv0297_writereg(state, 0x64, 0x00);	stv0297_writereg(state, 0x65, 0x00);	stv0297_writereg(state, 0x66, 0x00);	stv0297_writereg(state, 0x67, 0x00);	stv0297_writereg(state, 0x68, 0x00);	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);	/* set parameters */	stv0297_set_qam(state, p->u.qam.modulation);	stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);	stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);	stv0297_set_carrieroffset(state, carrieroffset);	stv0297_set_inversion(state, inversion);	/* kick off lock */	stv0297_writereg_mask(state, 0x88, 0x08, 0x08);	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);	/* wait for WGAGC lock */	starttime = jiffies;	timeout = jiffies + (200 * HZ) / 1000;	while (time_before(jiffies, timeout)) {		msleep(10);		if (stv0297_readreg(state, 0x43) & 0x08)			break;	}	if (time_after(jiffies, timeout)) {		goto timeout;	}	msleep(20);	/* wait for equaliser partial convergence */	timeout = jiffies + (50 * HZ) / 1000;	while (time_before(jiffies, timeout)) {		msleep(10);		if (stv0297_readreg(state, 0x82) & 0x04) {			break;		}	}	if (time_after(jiffies, timeout)) {		goto timeout;	}	/* wait for equaliser full convergence */	timeout = jiffies + (delay * HZ) / 1000;	while (time_before(jiffies, timeout)) {		msleep(10);		if (stv0297_readreg(state, 0x82) & 0x08) {			break;		}	}	if (time_after(jiffies, timeout)) {		goto timeout;	}	/* disable sweep */	stv0297_writereg_mask(state, 0x6a, 1, 0);	stv0297_writereg_mask(state, 0x88, 8, 0);	/* wait for main lock */	timeout = jiffies + (20 * HZ) / 1000;	while (time_before(jiffies, timeout)) {		msleep(10);		if (stv0297_readreg(state, 0xDF) & 0x80) {			break;		}	}	if (time_after(jiffies, timeout)) {		goto timeout;	}	msleep(100);	/* is it still locked after that delay? */	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {		goto timeout;	}	/* success!! */	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);	state->base_freq = p->frequency;	return 0;timeout:	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/b8742700f13163ffa00cddce2a3c940b9ab2ab5a/stv0297.c/clean/drivers/media/dvb/frontends/stv0297.c