bp->regview = NULL; 
bnx2_init_board(struct pci_dev *pdev, struct net_device *dev){	struct bnx2 *bp;	unsigned long mem_len;	int rc;	u32 reg;	SET_MODULE_OWNER(dev);	SET_NETDEV_DEV(dev, &pdev->dev);	bp = dev->priv;	bp->flags = 0;	bp->phy_flags = 0;	/* enable device (incl. PCI PM wakeup), and bus-mastering */	rc = pci_enable_device(pdev);	if (rc) {		printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");		goto err_out;	}	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {		printk(KERN_ERR PFX "Cannot find PCI device base address, "		       "aborting.\n");		rc = -ENODEV;		goto err_out_disable;	}	rc = pci_request_regions(pdev, DRV_MODULE_NAME);	if (rc) {		printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");		goto err_out_disable;	}	pci_set_master(pdev);	bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);	if (bp->pm_cap == 0) {		printk(KERN_ERR PFX "Cannot find power management capability, "			       "aborting.\n");		rc = -EIO;		goto err_out_release;	}	bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);	if (bp->pcix_cap == 0) {		printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");		rc = -EIO;		goto err_out_release;	}	if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {		bp->flags |= USING_DAC_FLAG;		if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {			printk(KERN_ERR PFX "pci_set_consistent_dma_mask "			       "failed, aborting.\n");			rc = -EIO;			goto err_out_release;		}	}	else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {		printk(KERN_ERR PFX "System does not support DMA, aborting.\n");		rc = -EIO;		goto err_out_release;	}	bp->dev = dev;	bp->pdev = pdev;	spin_lock_init(&bp->phy_lock);	spin_lock_init(&bp->tx_lock);	INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);	dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);	mem_len = MB_GET_CID_ADDR(17);	dev->mem_end = dev->mem_start + mem_len;	dev->irq = pdev->irq;	bp->regview = ioremap_nocache(dev->base_addr, mem_len);	if (!bp->regview) {		printk(KERN_ERR PFX "Cannot map register space, aborting.\n");		rc = -ENOMEM;		goto err_out_release;	}	/* Configure byte swap and enable write to the reg_window registers.	 * Rely on CPU to do target byte swapping on big endian systems	 * The chip's target access swapping will not swap all accesses	 */	pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,			       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |			       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);	bnx2_set_power_state(bp, 0);	bp->chip_id = REG_RD(bp, BNX2_MISC_ID);	bp->phy_addr = 1;	/* Get bus information. */	reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);	if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {		u32 clkreg;		bp->flags |= PCIX_FLAG;		clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);				clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;		switch (clkreg) {		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:			bp->bus_speed_mhz = 133;			break;		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:			bp->bus_speed_mhz = 100;			break;		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:			bp->bus_speed_mhz = 66;			break;		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:			bp->bus_speed_mhz = 50;			break;		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:			bp->bus_speed_mhz = 33;			break;		}	}	else {		if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)			bp->bus_speed_mhz = 66;		else			bp->bus_speed_mhz = 33;	}	if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)		bp->flags |= PCI_32BIT_FLAG;	/* 5706A0 may falsely detect SERR and PERR. */	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {		reg = REG_RD(bp, PCI_COMMAND);		reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);		REG_WR(bp, PCI_COMMAND, reg);	}	else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&		!(bp->flags & PCIX_FLAG)) {		printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "		       "aborting.\n");		goto err_out_unmap;	}	bnx2_init_nvram(bp);	/* Get the permanent MAC address.  First we need to make sure the	 * firmware is actually running.	 */	reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);	if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=	    BNX2_DEV_INFO_SIGNATURE_MAGIC) {		printk(KERN_ERR PFX "Firmware not running, aborting.\n");		rc = -ENODEV;		goto err_out_unmap;	}	bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +				BNX2_DEV_INFO_BC_REV);	reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);	bp->mac_addr[0] = (u8) (reg >> 8);	bp->mac_addr[1] = (u8) reg;	reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);	bp->mac_addr[2] = (u8) (reg >> 24);	bp->mac_addr[3] = (u8) (reg >> 16);	bp->mac_addr[4] = (u8) (reg >> 8);	bp->mac_addr[5] = (u8) reg;	bp->tx_ring_size = MAX_TX_DESC_CNT;	bp->rx_ring_size = 100;	bp->rx_csum = 1;	bp->rx_offset = sizeof(struct l2_fhdr) + 2;	bp->tx_quick_cons_trip_int = 20;	bp->tx_quick_cons_trip = 20;	bp->tx_ticks_int = 80;	bp->tx_ticks = 80;			bp->rx_quick_cons_trip_int = 6;	bp->rx_quick_cons_trip = 6;	bp->rx_ticks_int = 18;	bp->rx_ticks = 18;	bp->stats_ticks = 1000000 & 0xffff00;	bp->timer_interval =  HZ;	bp->current_interval =  HZ;	/* Disable WOL support if we are running on a SERDES chip. */	if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {		bp->phy_flags |= PHY_SERDES_FLAG;		bp->flags |= NO_WOL_FLAG;	}	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {		bp->tx_quick_cons_trip_int =			bp->tx_quick_cons_trip;		bp->tx_ticks_int = bp->tx_ticks;		bp->rx_quick_cons_trip_int =			bp->rx_quick_cons_trip;		bp->rx_ticks_int = bp->rx_ticks;		bp->comp_prod_trip_int = bp->comp_prod_trip;		bp->com_ticks_int = bp->com_ticks;		bp->cmd_ticks_int = bp->cmd_ticks;	}	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;	bp->req_line_speed = 0;	if (bp->phy_flags & PHY_SERDES_FLAG) {		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;		reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +				 BNX2_PORT_HW_CFG_CONFIG);		reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;		if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {			bp->autoneg = 0;			bp->req_line_speed = bp->line_speed = SPEED_1000;			bp->req_duplex = DUPLEX_FULL;		}	}	else {		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;	}	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;	init_timer(&bp->timer);	bp->timer.expires = RUN_AT(bp->timer_interval);	bp->timer.data = (unsigned long) bp;	bp->timer.function = bnx2_timer;	return 0;err_out_unmap:	if (bp->regview) {		iounmap(bp->regview);	}err_out_release:	pci_release_regions(pdev);err_out_disable:	pci_disable_device(pdev);	pci_set_drvdata(pdev, NULL);err_out:	return rc;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/73eef4cddb2738c4e8c5ef157ebb1b19d6c9272f/bnx2.c/clean/drivers/net/bnx2.c