return IRQ_RETVAL(1); 
return IRQ_HANDLED; 
bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs){	struct net_device *dev = dev_instance;	struct bnx2 *bp = dev->priv;	/* When using INTx, it is possible for the interrupt to arrive	 * at the CPU before the status block posted prior to the	 * interrupt. Reading a register will flush the status block.	 * When using MSI, the MSI message will always complete after	 * the status block write.	 */	if ((bp->status_blk->status_idx == bp->last_status_idx) ||	    (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &	     BNX2_PCICFG_MISC_STATUS_INTA_VALUE))		return IRQ_RETVAL(0);	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);	/* Return here if interrupt is shared and is disabled. */	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {		return IRQ_RETVAL(1);	}	if (netif_rx_schedule_prep(dev)) {		__netif_rx_schedule(dev);	}	return IRQ_RETVAL(1);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/73eef4cddb2738c4e8c5ef157ebb1b19d6c9272f/bnx2.c/clean/drivers/net/bnx2.c