 num_counters = num_ctrs; 
static void power4_reg_setup(struct op_counter_config *ctr,			     struct op_system_config *sys,			     int num_ctrs){	int i;	num_counters = num_ctrs;	/*	 * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.	 * However we disable it on all POWER4 until we verify it works	 * (I was seeing some strange behaviour last time I tried).	 *	 * It has been verified to work on POWER5 so we enable it there.	 */	if (cpu_has_feature(CPU_FTR_MMCRA_SIHV))		mmcra_has_sihv = 1;	/*	 * The performance counter event settings are given in the mmcr0,	 * mmcr1 and mmcra values passed from the user in the	 * op_system_config structure (sys variable).	 */	mmcr0_val = sys->mmcr0;	mmcr1_val = sys->mmcr1;	mmcra_val = sys->mmcra;	backtrace_spinlocks = sys->backtrace_spinlocks;	for (i = 0; i < num_counters; ++i)		reset_value[i] = 0x80000000UL - ctr[i].count;	/* setup user and kernel profiling */	if (sys->enable_kernel)		mmcr0_val &= ~MMCR0_KERNEL_DISABLE;	else		mmcr0_val |= MMCR0_KERNEL_DISABLE;	if (sys->enable_user)		mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;	else		mmcr0_val |= MMCR0_PROBLEM_DISABLE;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a6908cd00036080fbea14ff67335e5f2a1ab5489/op_model_power4.c/clean/arch/ppc64/oprofile/op_model_power4.c