__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); 
/* see notes above for revision 1.07.  Apparent chip bug */ serialize_cpu(); 
static void collect_cpu_info (void *unused){	int cpu_num = smp_processor_id();	struct cpuinfo_x86 *c = cpu_data + cpu_num;	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;	unsigned int val[2];	uci->sig = uci->pf = uci->rev = uci->cksum = 0;	uci->err = MC_NOTFOUND; 	uci->mc = NULL;	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||	    	cpu_has(c, X86_FEATURE_IA64)) {		printk(KERN_ERR "microcode: CPU%d not a capable Intel processor\n", cpu_num);		return;	} else {		uci->sig = cpuid_eax(0x00000001);		if ((c->x86_model >= 5) || (c->x86 > 6)) {			/* get processor flags from MSR 0x17 */			rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);			uci->pf = 1 << ((val[1] >> 18) & 7);		}	}	wrmsr(MSR_IA32_UCODE_REV, 0, 0);	__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");	/* get the current revision from MSR 0x8B */	rdmsr(MSR_IA32_UCODE_REV, val[0], uci->rev);	pr_debug("microcode: collect_cpu_info : sig=0x%x, pf=0x%x, rev=0x%x\n",			uci->sig, uci->pf, uci->rev);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/245067d1674d451855692fcd4647daf9fd47f82d/microcode.c/clean/arch/i386/kernel/microcode.c