#endif  #ifdef CONFIG_MPC885ADS  /* Deassert PHY reset and enable the PHY. */ { volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE); uint tmp;  tmp = in_be32(bcsr + 1 /* BCSR1 */); tmp |= BCSR1_ETHEN; out_be32(bcsr + 1, tmp); tmp = in_be32(bcsr + 4 /* BCSR4 */); tmp |= BCSR4_ETH10_RST; out_be32(bcsr + 4, tmp); iounmap(bcsr); }  /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode * upon reset. SCC is set to half duplex by default. So this * inconsistency should be better fixed by the software. */ 
static int __init scc_enet_init(void){	struct net_device *dev;	struct scc_enet_private *cep;	int i, j, k, err;	uint dp_offset;	unsigned char	*eap, *ba;	dma_addr_t	mem_addr;	bd_t		*bd;	volatile	cbd_t		*bdp;	volatile	cpm8xx_t	*cp;	volatile	scc_t		*sccp;	volatile	scc_enet_t	*ep;	volatile	immap_t		*immap;	cp = cpmp;	/* Get pointer to Communication Processor */	immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000);	/* and to internal registers */	bd = (bd_t *)__res;	dev = alloc_etherdev(sizeof(*cep));	if (!dev)		return -ENOMEM;	cep = dev->priv;	spin_lock_init(&cep->lock);	/* Get pointer to SCC area in parameter RAM.	*/	ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]);	/* And another to the SCC register area.	*/	sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]);	cep->sccp = (scc_t *)sccp;		/* Keep the pointer handy */	/* Disable receive and transmit in case EPPC-Bug started it.	*/	sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);	/* Cookbook style from the MPC860 manual.....	 * Not all of this is necessary if EPPC-Bug has initialized	 * the network.	 * So far we are lucky, all board configurations use the same	 * pins, or at least the same I/O Port for these functions.....	 * It can't last though......	 */#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))	/* Configure port A pins for Txd and Rxd.	*/	immap->im_ioport.iop_papar |=  (PA_ENET_RXD | PA_ENET_TXD);	immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);	immap->im_ioport.iop_paodr &=                ~PA_ENET_TXD;#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))	/* Configure port B pins for Txd and Rxd.	*/	immap->im_cpm.cp_pbpar |=  (PB_ENET_RXD | PB_ENET_TXD);	immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);	immap->im_cpm.cp_pbodr &=		 ~PB_ENET_TXD;#else#error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined#endif#if defined(PC_ENET_LBK)	/* Configure port C pins to disable External Loopback	 */	immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK;	immap->im_ioport.iop_pcdir |=  PC_ENET_LBK;	immap->im_ioport.iop_pcso  &= ~PC_ENET_LBK;	immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK;	/* Disable Loopback */#endif	/* PC_ENET_LBK */	/* Configure port C pins to enable CLSN and RENA.	*/	immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);	immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);	immap->im_ioport.iop_pcso  |=  (PC_ENET_CLSN | PC_ENET_RENA);	/* Configure port A for TCLK and RCLK.	*/	immap->im_ioport.iop_papar |=  (PA_ENET_TCLK | PA_ENET_RCLK);	immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);	/* Configure Serial Interface clock routing.	 * First, clear all SCC bits to zero, then set the ones we want.	 */	cp->cp_sicr &= ~SICR_ENET_MASK;	cp->cp_sicr |=  SICR_ENET_CLKRT;	/* Manual says set SDDR, but I can't find anything with that	 * name.  I think it is a misprint, and should be SDCR.  This	 * has already been set by the communication processor initialization.	 */	/* Allocate space for the buffer descriptors in the DP ram.	 * These are relative offsets in the DP ram address space.	 * Initialize base addresses for the buffer descriptors.	 */	dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);	ep->sen_genscc.scc_rbase = dp_offset;	cep->rx_bd_base = cpm_dpram_addr(dp_offset);	dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);	ep->sen_genscc.scc_tbase = dp_offset;	cep->tx_bd_base = cpm_dpram_addr(dp_offset);	cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;	cep->cur_rx = cep->rx_bd_base;	/* Issue init Rx BD command for SCC.	 * Manual says to perform an Init Rx parameters here.  We have	 * to perform both Rx and Tx because the SCC may have been	 * already running.	 * In addition, we have to do it later because we don't yet have	 * all of the BD control/status set properly.	cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG;	while (cp->cp_cpcr & CPM_CR_FLG);	 */	/* Initialize function code registers for big-endian.	*/	ep->sen_genscc.scc_rfcr = SCC_EB;	ep->sen_genscc.scc_tfcr = SCC_EB;	/* Set maximum bytes per receive buffer.	 * This appears to be an Ethernet frame size, not the buffer	 * fragment size.  It must be a multiple of four.	 */	ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE;	/* Set CRC preset and mask.	*/	ep->sen_cpres = 0xffffffff;	ep->sen_cmask = 0xdebb20e3;	ep->sen_crcec = 0;	/* CRC Error counter */	ep->sen_alec = 0;	/* alignment error counter */	ep->sen_disfc = 0;	/* discard frame counter */	ep->sen_pads = 0x8888;	/* Tx short frame pad character */	ep->sen_retlim = 15;	/* Retry limit threshold */	ep->sen_maxflr = PKT_MAXBUF_SIZE;   /* maximum frame length register */	ep->sen_minflr = PKT_MINBUF_SIZE;  /* minimum frame length register */	ep->sen_maxd1 = PKT_MAXBLR_SIZE;	/* maximum DMA1 length */	ep->sen_maxd2 = PKT_MAXBLR_SIZE;	/* maximum DMA2 length */	/* Clear hash tables.	*/	ep->sen_gaddr1 = 0;	ep->sen_gaddr2 = 0;	ep->sen_gaddr3 = 0;	ep->sen_gaddr4 = 0;	ep->sen_iaddr1 = 0;	ep->sen_iaddr2 = 0;	ep->sen_iaddr3 = 0;	ep->sen_iaddr4 = 0;	/* Set Ethernet station address.	 */	eap = (unsigned char *)&(ep->sen_paddrh);	for (i=5; i>=0; i--)		*eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];	ep->sen_pper = 0;	/* 'cause the book says so */	ep->sen_taddrl = 0;	/* temp address (LSB) */	ep->sen_taddrm = 0;	ep->sen_taddrh = 0;	/* temp address (MSB) */	/* Now allocate the host memory pages and initialize the	 * buffer descriptors.	 */	bdp = cep->tx_bd_base;	for (i=0; i<TX_RING_SIZE; i++) {		/* Initialize the BD for every fragment in the page.		*/		bdp->cbd_sc = 0;		bdp->cbd_bufaddr = 0;		bdp++;	}	/* Set the last buffer to wrap.	*/	bdp--;	bdp->cbd_sc |= BD_SC_WRAP;	bdp = cep->rx_bd_base;	k = 0;	for (i=0; i<CPM_ENET_RX_PAGES; i++) {		/* Allocate a page.		*/		ba = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE,				&mem_addr, GFP_KERNEL);		/* BUG: no check for failure */		/* Initialize the BD for every fragment in the page.		*/		for (j=0; j<CPM_ENET_RX_FRPPG; j++) {			bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;			bdp->cbd_bufaddr = mem_addr;			cep->rx_vaddr[k++] = ba;			mem_addr += CPM_ENET_RX_FRSIZE;			ba += CPM_ENET_RX_FRSIZE;			bdp++;		}	}	/* Set the last buffer to wrap.	*/	bdp--;	bdp->cbd_sc |= BD_SC_WRAP;	/* Let's re-initialize the channel now.  We have to do it later	 * than the manual describes because we have just now finished	 * the BD initialization.	 */	cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG;	while (cp->cp_cpcr & CPM_CR_FLG);	cep->skb_cur = cep->skb_dirty = 0;	sccp->scc_scce = 0xffff;	/* Clear any pending events */	/* Enable interrupts for transmit error, complete frame	 * received, and any transmit buffer we have also set the	 * interrupt flag.	 */	sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);	/* Install our interrupt handler.	*/	cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev);	/* Set GSMR_H to enable all normal operating modes.	 * Set GSMR_L to enable Ethernet to MC68160.	 */	sccp->scc_gsmrh = 0;	sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);	/* Set sync/delimiters.	*/	sccp->scc_dsr = 0xd555;	/* Set processing mode.  Use Ethernet CRC, catch broadcast, and	 * start frame search 22 bit times after RENA.	 */	sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);	/* It is now OK to enable the Ethernet transmitter.	 * Unfortunately, there are board implementation differences here.	 */#if   (!defined (PB_ENET_TENA) &&  defined (PC_ENET_TENA))	immap->im_ioport.iop_pcpar |=  PC_ENET_TENA;	immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA;#elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA))	cp->cp_pbpar |= PB_ENET_TENA;	cp->cp_pbdir |= PB_ENET_TENA;#else#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA#endif#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)	/* And while we are here, set the configuration to enable ethernet.	*/	*((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK;	*((volatile uint *)RPX_CSR_ADDR) |=			(BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS);#endif#ifdef CONFIG_BSEIP	/* BSE uses port B and C for PHY control.	*/	cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS);	cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);	cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);	immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK;	immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK;	immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK;	immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK;#endif#ifdef CONFIG_FADS	cp->cp_pbpar |= PB_ENET_TENA;	cp->cp_pbdir |= PB_ENET_TENA;	/* Enable the EEST PHY.	*/	*((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;#endif	dev->base_addr = (unsigned long)ep;#if 0	dev->name = "CPM_ENET";#endif	/* The CPM Ethernet specific entries in the device structure. */	dev->open = scc_enet_open;	dev->hard_start_xmit = scc_enet_start_xmit;	dev->tx_timeout = scc_enet_timeout;	dev->watchdog_timeo = TX_TIMEOUT;	dev->stop = scc_enet_close;	dev->get_stats = scc_enet_get_stats;	dev->set_multicast_list = set_multicast_list;	err = register_netdev(dev);	if (err) {		free_netdev(dev);		return err;	}	/* And last, enable the transmit and receive processing.	*/	sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);	printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1);	for (i=0; i<5; i++)		printk("%02x:", dev->dev_addr[i]);	printk("%02x\n", dev->dev_addr[5]);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/e6b6239f8e8e5bd9ba0192a854652abf14e28ce4/enet.c/clean/arch/ppc/8xx_io/enet.c