tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); 
tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); 
static int tda10046_init(struct dvb_frontend* fe){	struct tda1004x_state* state = fe->demodulator_priv;	dprintk("%s\n", __FUNCTION__);	if (state->initialised)		return 0;	if (tda10046_fwupload(fe)) {		printk("tda1004x: firmware upload failed\n");		return -EIO;	}	tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip	// Init the PLL	if (state->config->pll_init) {		tda1004x_enable_tuner_i2c(state);		state->config->pll_init(fe);		tda1004x_disable_tuner_i2c(state);	}	// tda setup	tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer	tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);	tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream	tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer	tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10	tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0	tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99	tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221	tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }	tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup	tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities	tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);	  // }	tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values	tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);	  // }	tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }	tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits	tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1	tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm	tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config	tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config	tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN	tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup	tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config	tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select	tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz	tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);	state->initialised = 1;	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/1dfb800f9d0391dee86d692142745415f5f65f81/tda1004x.c/clean/drivers/media/dvb/frontends/tda1004x.c