pci_assign_all_busses = 1; 
pci_assign_all_buses = 1; 
void __init pq2_find_bridges(void){	extern int pci_assign_all_buses;	struct pci_controller * hose;	int host_bridge;	pci_assign_all_busses = 1;	hose = pcibios_alloc_controller();	if (!hose)		return;	ppc_md.pci_swizzle = common_swizzle;	hose->first_busno = 0;	hose->bus_offset = 0;	hose->last_busno = 0xff;#ifdef CONFIG_ADS8272	hose->set_cfg_type = 1;#endif	setup_m8260_indirect_pci(hose,				 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,				 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);	/* Make sure it is a supported bridge */	early_read_config_dword(hose,				0,				PCI_DEVFN(0,0),				PCI_VENDOR_ID,				&host_bridge);	switch (host_bridge) {		case PCI_DEVICE_ID_MPC8265:			break;		case PCI_DEVICE_ID_MPC8272:			break;		default:			printk("Attempting to use unrecognized host bridge ID"				" 0x%08x.\n", host_bridge);			break;	}	pq2ads_setup_pci(hose);	hose->io_space.start =	M82xx_PCI_LOWER_IO;	hose->io_space.end = M82xx_PCI_UPPER_IO;	hose->mem_space.start = M82xx_PCI_LOWER_MEM;	hose->mem_space.end = M82xx_PCI_UPPER_MMIO;	hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;	isa_io_base =	(unsigned long) ioremap(M82xx_PCI_IO_BASE,					M82xx_PCI_IO_SIZE);	hose->io_base_virt = (void *) isa_io_base;	/* setup resources */	pci_init_resource(&hose->mem_resources[0],			M82xx_PCI_LOWER_MEM,			M82xx_PCI_UPPER_MEM,			IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");	pci_init_resource(&hose->mem_resources[1],			M82xx_PCI_LOWER_MMIO,			M82xx_PCI_UPPER_MMIO,			IORESOURCE_MEM, "PCI memory");	pci_init_resource(&hose->io_resource,			M82xx_PCI_LOWER_IO,			M82xx_PCI_UPPER_IO,			IORESOURCE_IO | 1, "PCI I/O");	ppc_md.pci_exclude_device = pq2pci_exclude_device;	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);	ppc_md.pci_map_irq = pq2pci_map_irq;	ppc_md.pcibios_fixup = NULL;	ppc_md.pcibios_fixup_bus = NULL;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/ab590ccb428f874bb8f9cec1265cc1f9cb38b601/m82xx_pci.c/clean/arch/ppc/syslib/m82xx_pci.c