c->base.virt = ioremap(c->base.phys, c->base.len); 
c->base.virt = ioremap_nocache(c->base.phys, c->base.len); 
static int __devinit i2o_pci_alloc(struct i2o_controller *c){	struct pci_dev *pdev = c->pdev;	struct device *dev = &pdev->dev;	int i;	for (i = 0; i < 6; i++) {		/* Skip I/O spaces */		if (!(pci_resource_flags(pdev, i) & IORESOURCE_IO)) {			if (!c->base.phys) {				c->base.phys = pci_resource_start(pdev, i);				c->base.len = pci_resource_len(pdev, i);				/*				 * If we know what card it is, set the size				 * correctly. Code is taken from dpt_i2o.c				 */				if (pdev->device == 0xa501) {					if (pdev->subsystem_device >= 0xc032 &&					    pdev->subsystem_device <= 0xc03b) {						if (c->base.len > 0x400000)							c->base.len = 0x400000;					} else {						if (c->base.len > 0x100000)							c->base.len = 0x100000;					}				}				if (!c->raptor)					break;			} else {				c->in_queue.phys = pci_resource_start(pdev, i);				c->in_queue.len = pci_resource_len(pdev, i);				break;			}		}	}	if (i == 6) {		printk(KERN_ERR "%s: I2O controller has no memory regions"		       " defined.\n", c->name);		i2o_pci_free(c);		return -EINVAL;	}	/* Map the I2O controller */	if (c->raptor) {		printk(KERN_INFO "%s: PCI I2O controller\n", c->name);		printk(KERN_INFO "     BAR0 at 0x%08lX size=%ld\n",		       (unsigned long)c->base.phys, (unsigned long)c->base.len);		printk(KERN_INFO "     BAR1 at 0x%08lX size=%ld\n",		       (unsigned long)c->in_queue.phys,		       (unsigned long)c->in_queue.len);	} else		printk(KERN_INFO "%s: PCI I2O controller at %08lX size=%ld\n",		       c->name, (unsigned long)c->base.phys,		       (unsigned long)c->base.len);	c->base.virt = ioremap(c->base.phys, c->base.len);	if (!c->base.virt) {		printk(KERN_ERR "%s: Unable to map controller.\n", c->name);		return -ENOMEM;	}	if (c->raptor) {		c->in_queue.virt = ioremap(c->in_queue.phys, c->in_queue.len);		if (!c->in_queue.virt) {			printk(KERN_ERR "%s: Unable to map controller.\n",			       c->name);			i2o_pci_free(c);			return -ENOMEM;		}	} else		c->in_queue = c->base;	c->irq_mask = c->base.virt + 0x34;	c->post_port = c->base.virt + 0x40;	c->reply_port = c->base.virt + 0x44;#ifdef CONFIG_MTRR	/* Enable Write Combining MTRR for IOP's memory region */	c->mtrr_reg0 = mtrr_add(c->in_queue.phys, c->in_queue.len,				MTRR_TYPE_WRCOMB, 1);	c->mtrr_reg1 = -1;	if (c->mtrr_reg0 < 0)		printk(KERN_WARNING "%s: could not enable write combining "		       "MTRR\n", c->name);	else		printk(KERN_INFO "%s: using write combining MTRR\n", c->name);	/*	 * If it is an INTEL i960 I/O processor then set the first 64K to	 * Uncacheable since the region contains the messaging unit which	 * shouldn't be cached.	 */	if ((pdev->vendor == PCI_VENDOR_ID_INTEL ||	     pdev->vendor == PCI_VENDOR_ID_DPT) && !c->raptor) {		printk(KERN_INFO "%s: MTRR workaround for Intel i960 processor"		       "\n", c->name);		c->mtrr_reg1 = mtrr_add(c->base.phys, 0x10000,					MTRR_TYPE_UNCACHABLE, 1);		if (c->mtrr_reg1 < 0) {			printk(KERN_WARNING "%s: Error in setting "			       "MTRR_TYPE_UNCACHABLE\n", c->name);			mtrr_del(c->mtrr_reg0, c->in_queue.phys,				 c->in_queue.len);			c->mtrr_reg0 = -1;		}	}#endif	if (i2o_dma_alloc(dev, &c->status, 8, GFP_KERNEL)) {		i2o_pci_free(c);		return -ENOMEM;	}	if (i2o_dma_alloc(dev, &c->hrt, sizeof(i2o_hrt), GFP_KERNEL)) {		i2o_pci_free(c);		return -ENOMEM;	}	if (i2o_dma_alloc(dev, &c->dlct, 8192, GFP_KERNEL)) {		i2o_pci_free(c);		return -ENOMEM;	}	if (i2o_dma_alloc(dev, &c->status_block, sizeof(i2o_status_block),			  GFP_KERNEL)) {		i2o_pci_free(c);		return -ENOMEM;	}	if (i2o_dma_alloc(dev, &c->out_queue, MSG_POOL_SIZE, GFP_KERNEL)) {		i2o_pci_free(c);		return -ENOMEM;	}	pci_set_drvdata(pdev, c);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/61fbfa8129c1771061a0e9f47747854293081c5b/pci.c/buggy/drivers/message/i2o/pci.c