cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); 
cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE); 
cpci690_setup_peripherals(void){	/* Set up windows to CPLD, RTC/TODC, IPMI. */	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,		CPCI690_BR_SIZE, 0);	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);	cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,		CPCI690_TODC_SIZE, 0);	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);	TODC_INIT(TODC_TYPE_MK48T35, 0, 0,			ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,		CPCI690_IPMI_SIZE, 0);	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);	mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));	mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */	/*	 * Turn off timer/counters.  Not turning off watchdog timer because	 * can't read its reg on the 64260A so don't know if we'll be enabling	 * or disabling.	 */	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,			((1<<0) | (1<<8) | (1<<16) | (1<<24)));	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,			((1<<0) | (1<<8) | (1<<16) | (1<<24)));	/*	 * Set MPSC Multiplex RMII	 * NOTE: ethernet driver modifies bit 0 and 1	 */	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);#define GPP_EXTERNAL_INTERRUPTS \		((1<<24) | (1<<25) | (1<<26) | (1<<27) | \		 (1<<28) | (1<<29) | (1<<30) | (1<<31))	/* PCI interrupts are inputs */	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);	/* PCI interrupts are active low */	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);	/* Clear any pending interrupts for these inputs and enable them. */	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);	/* Route MPP interrupt inputs to GPP */	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f54bef9e9c84c8dc656c55dc96c1da7b6d1c53d8/cpci690.c/buggy/arch/ppc/platforms/cpci690.c