int ch_config(pc300dev_t * d) 
static int ch_config(pc300dev_t * d) 
int ch_config(pc300dev_t * d){	pc300ch_t *chan = (pc300ch_t *) d->chan;	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	pc300_t *card = (pc300_t *) chan->card;	void __iomem *scabase = card->hw.scabase;	void __iomem *plxbase = card->hw.plxbase;	int ch = chan->channel;	uclong clkrate = chan->conf.phys_settings.clock_rate;	uclong clktype = chan->conf.phys_settings.clock_type;	ucshort encoding = chan->conf.proto_settings.encoding;	ucshort parity = chan->conf.proto_settings.parity;   	int tmc, br;	ucchar md0, md2;    	/* Reset the channel */	cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);	/* Configure the SCA registers */	switch (parity) {		case PARITY_NONE:			md0 = MD0_BIT_SYNC;			break;		case PARITY_CRC16_PR0:			md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;			break;		case PARITY_CRC16_PR1:			md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;			break;		case PARITY_CRC32_PR1_CCITT:			md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;			break;		case PARITY_CRC16_PR1_CCITT:		default:			md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;			break;	}	switch (encoding) {		case ENCODING_NRZI:			md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;			break;		case ENCODING_FM_MARK:	/* FM1 */			md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;			break;		case ENCODING_FM_SPACE:	/* FM0 */			md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;			break;		case ENCODING_MANCHESTER: /* It's not working... */			md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;			break;		case ENCODING_NRZ:		default:			md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;			break;	}	cpc_writeb(scabase + M_REG(MD0, ch), md0);	cpc_writeb(scabase + M_REG(MD1, ch), 0);	cpc_writeb(scabase + M_REG(MD2, ch), md2); 	cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);	cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);	/* Configure HW media */	switch (card->hw.type) {		case PC300_RSV:			if (conf->media == IF_IFACE_V35) {				cpc_writel((plxbase + card->hw.gpioc_reg),					   cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));			} else {				cpc_writel((plxbase + card->hw.gpioc_reg),					   cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));			}			break;		case PC300_X21:			break;		case PC300_TE:			te_config(card, ch);			break;	}	switch (card->hw.type) {		case PC300_RSV:		case PC300_X21:			if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {				/* Calculate the clkrate parameters */				tmc = clock_rate_calc(clkrate, card->hw.clock, &br);				cpc_writeb(scabase + M_REG(TMCT, ch), tmc);				cpc_writeb(scabase + M_REG(TXS, ch),					   (TXS_DTRXC | TXS_IBRG | br));				if (clktype == CLOCK_INT) {					cpc_writeb(scabase + M_REG(TMCR, ch), tmc);					cpc_writeb(scabase + M_REG(RXS, ch), 						   (RXS_IBRG | br));				} else {					cpc_writeb(scabase + M_REG(TMCR, ch), 1);					cpc_writeb(scabase + M_REG(RXS, ch), 0);				}	    			if (card->hw.type == PC300_X21) {					cpc_writeb(scabase + M_REG(GPO, ch), 1);					cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);				} else {					cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);				}			} else {				cpc_writeb(scabase + M_REG(TMCT, ch), 1);				if (clktype == CLOCK_EXT) {					cpc_writeb(scabase + M_REG(TXS, ch), 						   TXS_DTRXC);				} else {					cpc_writeb(scabase + M_REG(TXS, ch), 						   TXS_DTRXC|TXS_RCLK);				}	    			cpc_writeb(scabase + M_REG(TMCR, ch), 1);				cpc_writeb(scabase + M_REG(RXS, ch), 0);				if (card->hw.type == PC300_X21) {					cpc_writeb(scabase + M_REG(GPO, ch), 0);					cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);				} else {					cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);				}			}			break;		case PC300_TE:			/* SCA always receives clock from the FALC chip */			cpc_writeb(scabase + M_REG(TMCT, ch), 1);			cpc_writeb(scabase + M_REG(TXS, ch), 0);			cpc_writeb(scabase + M_REG(TMCR, ch), 1);			cpc_writeb(scabase + M_REG(RXS, ch), 0);			cpc_writeb(scabase + M_REG(EXS, ch), 0);			break;	}	/* Enable Interrupts */	cpc_writel(scabase + IER0,		   cpc_readl(scabase + IER0) |		   IR0_M(IR0_RXINTA, ch) |		   IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |		   IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));	cpc_writeb(scabase + M_REG(IE0, ch),		   cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);	cpc_writeb(scabase + M_REG(IE1, ch),		   cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7665a08928f241247afe8c76865cdbe4ef5489bf/pc300_drv.c/buggy/drivers/net/wan/pc300_drv.c