static void __init sabre_register_error_handlers(struct pci_controller_info *p) 
static void sabre_register_error_handlers(struct pci_controller_info *p) 
static void __init sabre_register_error_handlers(struct pci_controller_info *p){	struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */	unsigned long base = pbm->controller_regs;	unsigned long irq, portid = pbm->portid;	u64 tmp;	/* We clear the error bits in the appropriate AFSR before	 * registering the handler so that we don't get spurious	 * interrupts.	 */	sabre_write(base + SABRE_UE_AFSR,		    (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |		     SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |		     SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));	irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO);	if (request_irq(irq, sabre_ue_intr,			SA_SHIRQ, "SABRE UE", p) < 0) {		prom_printf("SABRE%d: Cannot register UE interrupt.\n",			    p->index);		prom_halt();	}	sabre_write(base + SABRE_CE_AFSR,		    (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |		     SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));	irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);	if (request_irq(irq, sabre_ce_intr,			SA_SHIRQ, "SABRE CE", p) < 0) {		prom_printf("SABRE%d: Cannot register CE interrupt.\n",			    p->index);		prom_halt();	}	irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO);	if (request_irq(irq, sabre_pcierr_intr,			SA_SHIRQ, "SABRE PCIERR", p) < 0) {		prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",			    p->index);		prom_halt();	}	tmp = sabre_read(base + SABRE_PCICTRL);	tmp |= SABRE_PCICTRL_ERREN;	sabre_write(base + SABRE_PCICTRL, tmp);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/085ae41f66657a9655ce832b0a61832a06f0e1dc/pci_sabre.c/buggy/arch/sparc64/kernel/pci_sabre.c