/* Inherit non-locked OBP mappings. */ inherit_prom_mappings();  
void __init paging_init(void){	extern pmd_t swapper_pmd_dir[1024];	unsigned long alias_base = kern_base + PAGE_OFFSET;	unsigned long second_alias_page = 0;	unsigned long pt, flags, end_pfn, pages_avail;	unsigned long shift = alias_base - ((unsigned long)KERNBASE);	unsigned long real_end;	set_bit(0, mmu_context_bmap);	real_end = (unsigned long)_end;	if ((real_end > ((unsigned long)KERNBASE + 0x400000)))		bigkernel = 1;#ifdef CONFIG_BLK_DEV_INITRD	if (sparc_ramdisk_image || sparc_ramdisk_image64)		real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));#endif	/* We assume physical memory starts at some 4mb multiple,	 * if this were not true we wouldn't boot up to this point	 * anyways.	 */	pt  = kern_base | _PAGE_VALID | _PAGE_SZ4MB;	pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;	local_irq_save(flags);	if (tlb_type == spitfire) {		__asm__ __volatile__(	"	stxa	%1, [%0] %3\n"	"	stxa	%2, [%5] %4\n"	"	membar	#Sync\n"	"	flush	%%g6\n"	"	nop\n"	"	nop\n"	"	nop\n"		: /* No outputs */		: "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),		  "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)		: "memory");		if (real_end >= KERNBASE + 0x340000) {			second_alias_page = alias_base + 0x400000;			__asm__ __volatile__(		"	stxa	%1, [%0] %3\n"		"	stxa	%2, [%5] %4\n"		"	membar	#Sync\n"		"	flush	%%g6\n"		"	nop\n"		"	nop\n"		"	nop\n"			: /* No outputs */			: "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),			  "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)			: "memory");		}	} else if (tlb_type == cheetah || tlb_type == cheetah_plus) {		__asm__ __volatile__(	"	stxa	%1, [%0] %3\n"	"	stxa	%2, [%5] %4\n"	"	membar	#Sync\n"	"	flush	%%g6\n"	"	nop\n"	"	nop\n"	"	nop\n"		: /* No outputs */		: "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),		  "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))		: "memory");		if (real_end >= KERNBASE + 0x340000) {			second_alias_page = alias_base + 0x400000;			__asm__ __volatile__(		"	stxa	%1, [%0] %3\n"		"	stxa	%2, [%5] %4\n"		"	membar	#Sync\n"		"	flush	%%g6\n"		"	nop\n"		"	nop\n"		"	nop\n"			: /* No outputs */			: "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),			  "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))			: "memory");		}	}	local_irq_restore(flags);		/* Now set kernel pgd to upper alias so physical page computations	 * work.	 */	init_mm.pgd += ((shift) / (sizeof(pgd_t)));		memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));	/* Now can init the kernel/bad page tables. */	pud_set(pud_offset(&swapper_pg_dir[0], 0),		swapper_pmd_dir + (shift / sizeof(pgd_t)));		swapper_pgd_zero = pgd_val(init_mm.pgd[0]);		/* Setup bootmem... */	pages_avail = 0;	last_valid_pfn = end_pfn = bootmem_init(&pages_avail);	/* Inherit non-locked OBP mappings. */	inherit_prom_mappings();		/* Ok, we can use our TLB miss and window trap handlers safely.	 * We need to do a quick peek here to see if we are on StarFire	 * or not, so setup_tba can setup the IRQ globals correctly (it	 * needs to get the hard smp processor id correctly).	 */	{		extern void setup_tba(int);		setup_tba(this_is_starfire);	}	inherit_locked_prom_mappings(1);	/* We only created DTLB mapping of this stuff. */	spitfire_flush_dtlb_nucleus_page(alias_base);	if (second_alias_page)		spitfire_flush_dtlb_nucleus_page(second_alias_page);	__flush_tlb_all();	{		unsigned long zones_size[MAX_NR_ZONES];		unsigned long zholes_size[MAX_NR_ZONES];		unsigned long npages;		int znum;		for (znum = 0; znum < MAX_NR_ZONES; znum++)			zones_size[znum] = zholes_size[znum] = 0;		npages = end_pfn - pfn_base;		zones_size[ZONE_DMA] = npages;		zholes_size[ZONE_DMA] = npages - pages_avail;		free_area_init_node(0, &contig_page_data, zones_size,				    phys_base >> PAGE_SHIFT, zholes_size);	}	device_scan();}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/5085b4a5492f4f8bd32d0cc5b1cad4bf522c2e1a/init.c/clean/arch/sparc64/mm/init.c