if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) && 
if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && 
static void tg3_init_rings(struct tg3 *tp){	u32 i;	/* Free up all the SKBs. */	tg3_free_rings(tp);	/* Zero out all descriptors. */	memset(tp->rx_std, 0, TG3_RX_RING_BYTES);	memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);	memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));	memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);	tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&	    (tp->dev->mtu > ETH_DATA_LEN))		tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;	/* Initialize invariants of the rings, we only set this	 * stuff once.  This works because the card does not	 * write into the rx buffer posting rings.	 */	for (i = 0; i < TG3_RX_RING_SIZE; i++) {		struct tg3_rx_buffer_desc *rxd;		rxd = &tp->rx_std[i];		rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)			<< RXD_LEN_SHIFT;		rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);		rxd->opaque = (RXD_OPAQUE_RING_STD |			       (i << RXD_OPAQUE_INDEX_SHIFT));	}	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {		for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {			struct tg3_rx_buffer_desc *rxd;			rxd = &tp->rx_jumbo[i];			rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)				<< RXD_LEN_SHIFT;			rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |				RXD_FLAG_JUMBO;			rxd->opaque = (RXD_OPAQUE_RING_JUMBO |			       (i << RXD_OPAQUE_INDEX_SHIFT));		}	}	/* Now allocate fresh SKBs for each rx ring. */	for (i = 0; i < tp->rx_pending; i++) {		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,				     -1, i) < 0)			break;	}	if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {		for (i = 0; i < tp->rx_jumbo_pending; i++) {			if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,					     -1, i) < 0)				break;		}	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a4e2b347848bf626b822599329933887dc90e50f/tg3.c/clean/drivers/net/tg3.c