mtrr_wrmsr(MTRRphysBase_MSR(reg), base << PAGE_SHIFT | type, (base & size_and_mask) >> (32 - PAGE_SHIFT)); mtrr_wrmsr(MTRRphysMask_MSR(reg), -size << PAGE_SHIFT | 0x800, (-size & size_and_mask) >> (32 - PAGE_SHIFT)); 
vr->base_lo = base << PAGE_SHIFT | type; vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); vr->mask_lo = -size << PAGE_SHIFT | 0x800; vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);  mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 
static void generic_set_mtrr(unsigned int reg, unsigned long base,			     unsigned long size, mtrr_type type)/*  [SUMMARY] Set variable MTRR register on the local CPU.    <reg> The register to set.    <base> The base address of the region.    <size> The size of the region. If this is 0 the region is disabled.    <type> The type of the region.    <do_safe> If TRUE, do the change safely. If FALSE, safety measures should    be done externally.    [RETURNS] Nothing.*/{	unsigned long flags;	local_irq_save(flags);	prepare_set();	if (size == 0) {		/* The invalid bit is kept in the mask, so we simply clear the		   relevant mask register to disable a range. */		mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);	} else {		mtrr_wrmsr(MTRRphysBase_MSR(reg), base << PAGE_SHIFT | type,		      (base & size_and_mask) >> (32 - PAGE_SHIFT));		mtrr_wrmsr(MTRRphysMask_MSR(reg), -size << PAGE_SHIFT | 0x800,		      (-size & size_and_mask) >> (32 - PAGE_SHIFT));	}	post_set();	local_irq_restore(flags);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3b520b238e018ef0e9d11c9115d5e7d9419c4ef9/generic.c/buggy/arch/i386/kernel/cpu/mtrr/generic.c