rxcsum |= E1000_RXCSUM_TUOFL; 
if(adapter->rx_csum == TRUE) { rxcsum |= E1000_RXCSUM_TUOFL;  /* Enable 82573 IPv4 payload checksum for UDP fragments * Must be used in conjunction with packet-split. */ if((adapter->hw.mac_type > e1000_82547_rev_2) && (adapter->rx_ps)) { rxcsum |= E1000_RXCSUM_IPPCSE; } } else { rxcsum &= ~E1000_RXCSUM_TUOFL; /* don't need to clear IPPCSE as it defaults to 0 */ } 
e1000_configure_rx(struct e1000_adapter *adapter){	uint64_t rdba = adapter->rx_ring.dma;	uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);	uint32_t rctl;	uint32_t rxcsum;	/* disable receives while setting up the descriptors */	rctl = E1000_READ_REG(&adapter->hw, RCTL);	E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);	/* set the Receive Delay Timer Register */	E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay);	if(adapter->hw.mac_type >= e1000_82540) {		E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay);		if(adapter->itr > 1)			E1000_WRITE_REG(&adapter->hw, ITR,				1000000000 / (adapter->itr * 256));	}	/* Setup the Base and Length of the Rx Descriptor Ring */	E1000_WRITE_REG(&adapter->hw, RDBAL, (rdba & 0x00000000ffffffffULL));	E1000_WRITE_REG(&adapter->hw, RDBAH, (rdba >> 32));	E1000_WRITE_REG(&adapter->hw, RDLEN, rdlen);	/* Setup the HW Rx Head and Tail Descriptor Pointers */	E1000_WRITE_REG(&adapter->hw, RDH, 0);	E1000_WRITE_REG(&adapter->hw, RDT, 0);	/* Enable 82543 Receive Checksum Offload for TCP and UDP */	if((adapter->hw.mac_type >= e1000_82543) &&	   (adapter->rx_csum == TRUE)) {		rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);		rxcsum |= E1000_RXCSUM_TUOFL;		E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);	}	/* Enable Receives */	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/2d7edb923a823660b081bd4c660300ee19adca8d/e1000_main.c/clean/drivers/net/e1000/e1000_main.c