int	host_bridge, picr1, picr1_bit; 
int	host_bridge, picr1, picr1_bit, i; 
mpc10x_bridge_init(struct pci_controller *hose,		   uint current_map,		   uint new_map,		   uint phys_eumb_base){	int	host_bridge, picr1, picr1_bit;	ulong	pci_config_addr, pci_config_data;	u_char	pir, byte;	if (ppc_md.progress) ppc_md.progress("mpc10x:enter", 0x100);	/* Set up for current map so we can get at config regs */	switch (current_map) {		case MPC10X_MEM_MAP_A:			setup_indirect_pci(hose,					   MPC10X_MAPA_CNFG_ADDR,					   MPC10X_MAPA_CNFG_DATA);			break;		case MPC10X_MEM_MAP_B:			setup_indirect_pci(hose,					   MPC10X_MAPB_CNFG_ADDR,					   MPC10X_MAPB_CNFG_DATA);			break;		default:			printk("mpc10x_bridge_init: %s\n",				"Invalid current map specified");			if (ppc_md.progress)				ppc_md.progress("mpc10x:exit1", 0x100);			return -1;	}	/* Make sure it's a supported bridge */	early_read_config_dword(hose,			        0,			        PCI_DEVFN(0,0),			        PCI_VENDOR_ID,			        &host_bridge);	switch (host_bridge) {		case MPC10X_BRIDGE_106:		case MPC10X_BRIDGE_8240:		case MPC10X_BRIDGE_107:		case MPC10X_BRIDGE_8245:			break;		default:			if (ppc_md.progress)				ppc_md.progress("mpc10x:exit2", 0x100);			return -1;	}	switch (new_map) {		case MPC10X_MEM_MAP_A:			MPC10X_SETUP_HOSE(hose, A);			pci_config_addr = MPC10X_MAPA_CNFG_ADDR;			pci_config_data = MPC10X_MAPA_CNFG_DATA;			picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_A;			break;		case MPC10X_MEM_MAP_B:			MPC10X_SETUP_HOSE(hose, B);			pci_config_addr = MPC10X_MAPB_CNFG_ADDR;			pci_config_data = MPC10X_MAPB_CNFG_DATA;			picr1_bit = MPC10X_CFG_PICR1_ADDR_MAP_B;			break;		default:			printk("mpc10x_bridge_init: %s\n",				"Invalid new map specified");			if (ppc_md.progress)				ppc_md.progress("mpc10x:exit3", 0x100);			return -1;	}	/* Make bridge use the 'new_map', if not already usng it */	if (current_map != new_map) {		early_read_config_dword(hose,					0,					PCI_DEVFN(0,0),					MPC10X_CFG_PICR1_REG,					&picr1);		picr1 = (picr1 & ~MPC10X_CFG_PICR1_ADDR_MAP_MASK) |			 picr1_bit;		early_write_config_dword(hose,					 0,					 PCI_DEVFN(0,0),					 MPC10X_CFG_PICR1_REG,					 picr1);		asm volatile("sync");		/* Undo old mappings & map in new cfg data/addr regs */		iounmap((void *)hose->cfg_addr);		iounmap((void *)hose->cfg_data);		setup_indirect_pci(hose,				   pci_config_addr,				   pci_config_data);	}	/* Setup resources to match map */	mpc10x_bridge_set_resources(new_map, hose);	/*	 * Want processor accesses of 0xFDxxxxxx to be mapped	 * to PCI memory space at 0x00000000.  Do not want	 * host bridge to respond to PCI memory accesses of	 * 0xFDxxxxxx.  Do not want host bridge to respond	 * to PCI memory addresses 0xFD000000-0xFDFFFFFF;	 * want processor accesses from 0x000A0000-0x000BFFFF	 * to be forwarded to system memory.	 *	 * Only valid if not in agent mode and using MAP B.	 */	if (new_map == MPC10X_MEM_MAP_B) {		early_read_config_byte(hose,				       0,				       PCI_DEVFN(0,0),				       MPC10X_CFG_MAPB_OPTIONS_REG,				       &byte);		byte &= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE  |			  MPC10X_CFG_MAPB_OPTIONS_PCICH |			  MPC10X_CFG_MAPB_OPTIONS_PROCCH);		if (host_bridge != MPC10X_BRIDGE_106) {			byte |= MPC10X_CFG_MAPB_OPTIONS_CFAE;		}		early_write_config_byte(hose,					0,					PCI_DEVFN(0,0),					MPC10X_CFG_MAPB_OPTIONS_REG,					byte);	}	if (host_bridge != MPC10X_BRIDGE_106) {		early_read_config_byte(hose,				       0,				       PCI_DEVFN(0,0),				       MPC10X_CFG_PIR_REG,				       &pir);		if (pir != MPC10X_CFG_PIR_HOST_BRIDGE) {			printk("Host bridge in Agent mode\n");			/* Read or Set LMBAR & PCSRBAR? */		}				/* Set base addr of the 8240/107 EUMB.  */		early_write_config_dword(hose,					 0,					 PCI_DEVFN(0,0),					 MPC10X_CFG_EUMBBAR,					 phys_eumb_base);#ifdef CONFIG_MPC10X_OPENPIC		/* Map EPIC register part of EUMB into vitual memory  - PCORE		   uses an i8259 instead of EPIC. */		OpenPIC_Addr =			ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,				MPC10X_EUMB_EPIC_SIZE);#endif		mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET;		mpc10x_i2c_ocp.irq = MPC10X_I2C_IRQ;		ocp_add_one_device(&mpc10x_i2c_ocp);		mpc10x_dma_ocp[0].paddr = phys_eumb_base +					MPC10X_EUMB_DMA_OFFSET + 0x100;		mpc10x_dma_ocp[0].irq = MPC10X_DMA0_IRQ;		ocp_add_one_device(&mpc10x_dma_ocp[0]);		mpc10x_dma_ocp[1].paddr = phys_eumb_base +					MPC10X_EUMB_DMA_OFFSET + 0x200;		mpc10x_dma_ocp[1].irq = MPC10X_DMA1_IRQ;		ocp_add_one_device(&mpc10x_dma_ocp[1]);	}#ifdef CONFIG_MPC10X_STORE_GATHERING	mpc10x_enable_store_gathering(hose);#else	mpc10x_disable_store_gathering(hose);#endif	/*	 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative	 * PCI reads may return stale data so turn off.	 */	if ((host_bridge == MPC10X_BRIDGE_8240)		|| (host_bridge == MPC10X_BRIDGE_8245)		|| (host_bridge == MPC10X_BRIDGE_107)) {		early_read_config_dword(hose, 0, PCI_DEVFN(0,0),			MPC10X_CFG_PICR1_REG, &picr1);		picr1 &= ~MPC10X_CFG_PICR1_SPEC_PCI_RD;		early_write_config_dword(hose, 0, PCI_DEVFN(0,0),			MPC10X_CFG_PICR1_REG, picr1);	}	/*	 * 8241/8245 erratum 28: PCI reads from local memory may return	 * stale data.  Workaround by setting PICR2[0] to disable copyback	 * optimization.  Oddly, the latest available user manual for the	 * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd.	 */	if (host_bridge == MPC10X_BRIDGE_8245) {		ulong	picr2;		early_read_config_dword(hose, 0, PCI_DEVFN(0,0),			MPC10X_CFG_PICR2_REG, &picr2);		picr2 |= MPC10X_CFG_PICR2_COPYBACK_OPT;		early_write_config_dword(hose, 0, PCI_DEVFN(0,0),			 MPC10X_CFG_PICR2_REG, picr2);	}	if (ppc_md.progress) ppc_md.progress("mpc10x:exit", 0x100);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/b264c3527930ca4812fefc505fde9ad99d8a0117/mpc10x_common.c/buggy/arch/ppc/syslib/mpc10x_common.c