* Disabled all PCIX, Flash, MDIO, IIC and GPIO 
* If Hercules adapter enable GPIO otherwise * disabled all PCIX, Flash, MDIO, IIC and GPIO 
static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag){	XENA_dev_config_t __iomem *bar0 = nic->bar0;	register u64 val64 = 0, temp64 = 0;	/*  Top level interrupt classification */	/*  PIC Interrupts */	if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {		/*  Enable PIC Intrs in the general intr mask register */		val64 = TXPIC_INT_M | PIC_RX_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * Disabled all PCIX, Flash, MDIO, IIC and GPIO			 * interrupts for now.			 * TODO			 */			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);			/*			 * No MSI Support is available presently, so TTI and			 * RTI interrupts are also disabled.			 */		} else if (flag == DISABLE_INTRS) {			/*			 * Disable PIC Intrs in the general			 * intr mask register			 */			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  DMA Interrupts */	/*  Enabling/Disabling Tx DMA interrupts */	if (mask & TX_DMA_INTR) {		/* Enable TxDMA Intrs in the general intr mask register */		val64 = TXDMA_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * Keep all interrupts other than PFC interrupt			 * and PCC interrupt disabled in DMA level.			 */			val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |						      TXDMA_PCC_INT_M);			writeq(val64, &bar0->txdma_int_mask);			/*			 * Enable only the MISC error 1 interrupt in PFC block			 */			val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);			writeq(val64, &bar0->pfc_err_mask);			/*			 * Enable only the FB_ECC error interrupt in PCC block			 */			val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);			writeq(val64, &bar0->pcc_err_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable TxDMA Intrs in the general intr mask			 * register			 */			writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);			writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  Enabling/Disabling Rx DMA interrupts */	if (mask & RX_DMA_INTR) {		/*  Enable RxDMA Intrs in the general intr mask register */		val64 = RXDMA_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * All RxDMA block interrupts are disabled for now			 * TODO			 */			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable RxDMA Intrs in the general intr mask			 * register			 */			writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  MAC Interrupts */	/*  Enabling/Disabling MAC interrupts */	if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {		val64 = TXMAC_INT_M | RXMAC_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * All MAC block error interrupts are disabled for now			 * except the link status change interrupt.			 * TODO			 */			val64 = MAC_INT_STATUS_RMAC_INT;			temp64 = readq(&bar0->mac_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->mac_int_mask);			val64 = readq(&bar0->mac_rmac_err_mask);			val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);			writeq(val64, &bar0->mac_rmac_err_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable MAC Intrs in the general intr mask register			 */			writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);			writeq(DISABLE_ALL_INTRS,			       &bar0->mac_rmac_err_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  XGXS Interrupts */	if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {		val64 = TXXGXS_INT_M | RXXGXS_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * All XGXS block error interrupts are disabled for now			 * TODO			 */			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable MC Intrs in the general intr mask register			 */			writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  Memory Controller(MC) interrupts */	if (mask & MC_INTR) {		val64 = MC_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * Enable all MC Intrs.			 */			writeq(0x0, &bar0->mc_int_mask);			writeq(0x0, &bar0->mc_err_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable MC Intrs in the general intr mask register			 */			writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  Tx traffic interrupts */	if (mask & TX_TRAFFIC_INTR) {		val64 = TXTRAFFIC_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/*			 * Enable all the Tx side interrupts			 * writing 0 Enables all 64 TX interrupt levels			 */			writeq(0x0, &bar0->tx_traffic_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable Tx Traffic Intrs in the general intr mask			 * register.			 */			writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}	/*  Rx traffic interrupts */	if (mask & RX_TRAFFIC_INTR) {		val64 = RXTRAFFIC_INT_M;		if (flag == ENABLE_INTRS) {			temp64 = readq(&bar0->general_int_mask);			temp64 &= ~((u64) val64);			writeq(temp64, &bar0->general_int_mask);			/* writing 0 Enables all 8 RX interrupt levels */			writeq(0x0, &bar0->rx_traffic_mask);		} else if (flag == DISABLE_INTRS) {			/*			 * Disable Rx Traffic Intrs in the general intr mask			 * register.			 */			writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);			temp64 = readq(&bar0->general_int_mask);			val64 |= temp64;			writeq(val64, &bar0->general_int_mask);		}	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/a371a07de9bce837ea4e84569a2b390a42e360ef/s2io.c/clean/drivers/net/s2io.c