(u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)), (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)), 
(u32) (lp->tx_ring_dma_addr), (u32) (lp->rx_ring_dma_addr), 
pcnet32_open(struct net_device *dev){    struct pcnet32_private *lp = dev->priv;    unsigned long ioaddr = dev->base_addr;    u16 val;    int i;    int rc;    unsigned long flags;    if (request_irq(dev->irq, &pcnet32_interrupt,		    lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {	return -EAGAIN;    }    spin_lock_irqsave(&lp->lock, flags);    /* Check for a valid station address */    if (!is_valid_ether_addr(dev->dev_addr)) {	rc = -EINVAL;	goto err_free_irq;    }    /* Reset the PCNET32 */    lp->a.reset (ioaddr);    /* switch pcnet32 to 32bit mode */    lp->a.write_bcr (ioaddr, 20, 2);    if (netif_msg_ifup(lp))	printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",	       dev->name, dev->irq,	       (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),	       (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),	       (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));    /* set/reset autoselect bit */    val = lp->a.read_bcr (ioaddr, 2) & ~2;    if (lp->options & PCNET32_PORT_ASEL)	val |= 2;    lp->a.write_bcr (ioaddr, 2, val);    /* handle full duplex setting */    if (lp->mii_if.full_duplex) {	val = lp->a.read_bcr (ioaddr, 9) & ~3;	if (lp->options & PCNET32_PORT_FD) {	    val |= 1;	    if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))		val |= 2;	} else if (lp->options & PCNET32_PORT_ASEL) {	/* workaround of xSeries250, turn on for 79C975 only */	    i = ((lp->a.read_csr(ioaddr, 88) |			(lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;	    if (i == 0x2627)		val |= 3;	}	lp->a.write_bcr (ioaddr, 9, val);    }    /* set/reset GPSI bit in test register */    val = lp->a.read_csr (ioaddr, 124) & ~0x10;    if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)	val |= 0x10;    lp->a.write_csr (ioaddr, 124, val);    /* Allied Telesyn AT 2700/2701 FX looses the link, so skip that */    if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&        (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||	 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {	printk(KERN_DEBUG "%s: Skipping PHY selection.\n", dev->name);    } else {	/*	 * 24 Jun 2004 according AMD, in order to change the PHY,	 * DANAS (or DISPM for 79C976) must be set; then select the speed,	 * duplex, and/or enable auto negotiation, and clear DANAS	 */	if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {	    lp->a.write_bcr(ioaddr, 32,				lp->a.read_bcr(ioaddr, 32) | 0x0080);	    /* disable Auto Negotiation, set 10Mpbs, HD */	    val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;	    if (lp->options & PCNET32_PORT_FD)		val |= 0x10;	    if (lp->options & PCNET32_PORT_100)		val |= 0x08;	    lp->a.write_bcr (ioaddr, 32, val);	} else {	    if (lp->options & PCNET32_PORT_ASEL) {		lp->a.write_bcr(ioaddr, 32,			lp->a.read_bcr(ioaddr, 32) | 0x0080);		/* enable auto negotiate, setup, disable fd */		val = lp->a.read_bcr(ioaddr, 32) & ~0x98;		val |= 0x20;		lp->a.write_bcr(ioaddr, 32, val);	    }	}    }#ifdef DO_DXSUFLO    if (lp->dxsuflo) { /* Disable transmit stop on underflow */	val = lp->a.read_csr (ioaddr, 3);	val |= 0x40;	lp->a.write_csr (ioaddr, 3, val);    }#endif    lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);    pcnet32_load_multicast(dev);    if (pcnet32_init_ring(dev)) {	rc = -ENOMEM;	goto err_free_ring;    }    /* Re-initialize the PCNET32, and start it when done. */    lp->a.write_csr (ioaddr, 1, (lp->dma_addr +		offsetof(struct pcnet32_private, init_block)) & 0xffff);    lp->a.write_csr (ioaddr, 2, (lp->dma_addr +		offsetof(struct pcnet32_private, init_block)) >> 16);    lp->a.write_csr (ioaddr, 4, 0x0915);    lp->a.write_csr (ioaddr, 0, 0x0001);    netif_start_queue(dev);    /* If we have mii, print the link status and start the watchdog */    if (lp->mii) {	mii_check_media (&lp->mii_if, netif_msg_link(lp), 1);	mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);    }    i = 0;    while (i++ < 100)	if (lp->a.read_csr (ioaddr, 0) & 0x0100)	    break;    /*     * We used to clear the InitDone bit, 0x0100, here but Mark Stockton     * reports that doing so triggers a bug in the '974.     */    lp->a.write_csr (ioaddr, 0, 0x0042);    if (netif_msg_ifup(lp))	printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",		dev->name, i, (u32) (lp->dma_addr +		    offsetof(struct pcnet32_private, init_block)),		lp->a.read_csr(ioaddr, 0));    spin_unlock_irqrestore(&lp->lock, flags);    return 0;	/* Always succeed */err_free_ring:    /* free any allocated skbuffs */    for (i = 0; i < RX_RING_SIZE; i++) {	lp->rx_ring[i].status = 0;	if (lp->rx_skbuff[i]) {	    pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,		    PCI_DMA_FROMDEVICE);	    dev_kfree_skb(lp->rx_skbuff[i]);	}	lp->rx_skbuff[i] = NULL;	lp->rx_dma_addr[i] = 0;    }    /*     * Switch back to 16bit mode to avoid problems with dumb     * DOS packet driver after a warm reboot     */    lp->a.write_bcr (ioaddr, 20, 4);err_free_irq:    spin_unlock_irqrestore(&lp->lock, flags);    free_irq(dev->irq, dev);    return rc;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/eabf04151682bc7b57c84fea58cf9e4e5a3cf2a9/pcnet32.c/buggy/drivers/net/pcnet32.c