/* handle i-cache coherency */ 
#ifdef CONFIG_PPC_STD_MMU unsigned long access = 0, trap; #endif 
void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,		      pte_t pte){	/* handle i-cache coherency */	unsigned long pfn = pte_pfn(pte);#ifdef CONFIG_PPC32	pmd_t *pmd;#else	unsigned long vsid;	void *pgdir;	pte_t *ptep;	int local = 0;	cpumask_t tmp;	unsigned long flags;#endif	/* handle i-cache coherency */	if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE) &&	    !cpu_has_feature(CPU_FTR_NOEXECUTE) &&	    pfn_valid(pfn)) {		struct page *page = pfn_to_page(pfn);		if (!PageReserved(page)		    && !test_bit(PG_arch_1, &page->flags)) {			if (vma->vm_mm == current->active_mm) {#ifdef CONFIG_8xx			/* On 8xx, cache control instructions (particularly 		 	 * "dcbst" from flush_dcache_icache) fault as write 			 * operation if there is an unpopulated TLB entry 			 * for the address in question. To workaround that, 			 * we invalidate the TLB here, thus avoiding dcbst 			 * misbehaviour.			 */				_tlbie(address);#endif				__flush_dcache_icache((void *) address);			} else				flush_dcache_icache_page(page);			set_bit(PG_arch_1, &page->flags);		}	}#ifdef CONFIG_PPC_STD_MMU	/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */	if (!pte_young(pte) || address >= TASK_SIZE)		return;#ifdef CONFIG_PPC32	if (Hash == 0)		return;	pmd = pmd_offset(pgd_offset(vma->vm_mm, address), address);	if (!pmd_none(*pmd))		add_hash_page(vma->vm_mm->context, address, pmd_val(*pmd));#else	pgdir = vma->vm_mm->pgd;	if (pgdir == NULL)		return;	ptep = find_linux_pte(pgdir, address);	if (!ptep)		return;	vsid = get_vsid(vma->vm_mm->context.id, address);	local_irq_save(flags);	tmp = cpumask_of_cpu(smp_processor_id());	if (cpus_equal(vma->vm_mm->cpu_vm_mask, tmp))		local = 1;	__hash_page(address, 0, vsid, ptep, 0x300, local);	local_irq_restore(flags);#endif#endif}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/3c726f8dee6f55e96475574e9f645327e461884c/mem.c/clean/arch/powerpc/mm/mem.c