c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; if (c->x86_num_cores & (c->x86_num_cores - 1)) c->x86_num_cores = 1; 
c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; if (c->x86_max_cores & (c->x86_max_cores - 1)) c->x86_max_cores = 1; 
static int __init init_amd(struct cpuinfo_x86 *c){	int r;	int level;#ifdef CONFIG_SMP	unsigned long value;	/*	 * Disable TLB flush filter by setting HWCR.FFDIS on K8	 * bit 6 of msr C001_0015 	 *	 * Errata 63 for SH-B3 steppings	 * Errata 122 for all steppings (F+ have it disabled by default)	 */	if (c->x86 == 15) {		rdmsrl(MSR_K8_HWCR, value);		value |= 1 << 6;		wrmsrl(MSR_K8_HWCR, value);	}#endif	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */	clear_bit(0*32+31, &c->x86_capability);		/* C-stepping K8? */	level = cpuid_eax(1);	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)		set_bit(X86_FEATURE_K8_C, &c->x86_capability);	r = get_model_name(c);	if (!r) { 		switch (c->x86) { 		case 15:			/* Should distinguish Models here, but this is only			   a fallback anyways. */			strcpy(c->x86_model_id, "Hammer");			break; 		} 	} 	display_cacheinfo(c);	if (c->extended_cpuid_level >= 0x80000008) {		c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;		if (c->x86_num_cores & (c->x86_num_cores - 1))			c->x86_num_cores = 1;		amd_detect_cmp(c);	}	return r;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/94605eff572b727aaad9b4b29bc358b919096503/setup.c/clean/arch/x86_64/kernel/setup.c