set_current_state(TASK_INTERRUPTIBLE); schedule_timeout(1); 
schedule_timeout_interruptible(1); 
static int snd_via82xx_chip_init(via82xx_t *chip){	unsigned int val;	unsigned long end_time;	unsigned char pval;	pci_read_config_byte(chip->pci, VIA_MC97_CTRL, &pval);	if((pval & VIA_MC97_CTRL_INIT) != VIA_MC97_CTRL_INIT) {		pci_write_config_byte(chip->pci, 0x44, pval|VIA_MC97_CTRL_INIT);		udelay(100);	}	pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);	if (! (pval & VIA_ACLINK_C00_READY)) { /* codec not ready? */		/* deassert ACLink reset, force SYNC */		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,				      VIA_ACLINK_CTRL_ENABLE |				      VIA_ACLINK_CTRL_RESET |				      VIA_ACLINK_CTRL_SYNC);		udelay(100);#if 1 /* FIXME: should we do full reset here for all chip models? */		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, 0x00);		udelay(100);#else		/* deassert ACLink reset, force SYNC (warm AC'97 reset) */		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL,				      VIA_ACLINK_CTRL_RESET|VIA_ACLINK_CTRL_SYNC);		udelay(2);#endif		/* ACLink on, deassert ACLink reset, VSR, SGD data out */		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);		udelay(100);	}		pci_read_config_byte(chip->pci, VIA_ACLINK_CTRL, &pval);	if ((pval & VIA_ACLINK_CTRL_INIT) != VIA_ACLINK_CTRL_INIT) {		/* ACLink on, deassert ACLink reset, VSR, SGD data out */		pci_write_config_byte(chip->pci, VIA_ACLINK_CTRL, VIA_ACLINK_CTRL_INIT);		udelay(100);	}	/* wait until codec ready */	end_time = jiffies + msecs_to_jiffies(750);	do {		pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);		if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */			break;		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout(1);	} while (time_before(jiffies, end_time));	if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)		snd_printk(KERN_ERR "AC'97 codec is not ready [0x%x]\n", val);	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |				 VIA_REG_AC97_SECONDARY_VALID |				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));	end_time = jiffies + msecs_to_jiffies(750);	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |				 VIA_REG_AC97_SECONDARY_VALID |				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));	do {		if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_SECONDARY_VALID) {			chip->ac97_secondary = 1;			goto __ac97_ok2;		}		set_current_state(TASK_INTERRUPTIBLE);		schedule_timeout(1);	} while (time_before(jiffies, end_time));	/* This is ok, the most of motherboards have only one codec */      __ac97_ok2:	/* route FM trap to IRQ, disable FM trap */	// pci_write_config_byte(chip->pci, VIA_FM_NMI_CTRL, 0);	/* disable all GPI interrupts */	outl(0, VIAREG(chip, GPI_INTR));	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/8433a509c0eb6bb1f33ce39c82c580b8901619ee/via82xx_modem.c/buggy/sound/pci/via82xx_modem.c