tmp = lmb_alloc(PAGE_SIZE, PAGE_SIZE); 
tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); 
static int dart_init(struct device_node *dart_node){	unsigned int regword;	unsigned int i;	unsigned long tmp;	if (dart_tablebase == 0 || dart_tablesize == 0) {		printk(KERN_INFO "U3-DART: table not allocated, using direct DMA\n");		return -ENODEV;	}	/* Make sure nothing from the DART range remains in the CPU cache	 * from a previous mapping that existed before the kernel took	 * over	 */	flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize);	/* Allocate a spare page to map all invalid DART pages. We need to do	 * that to work around what looks like a problem with the HT bridge	 * prefetching into invalid pages and corrupting data	 */	tmp = lmb_alloc(PAGE_SIZE, PAGE_SIZE);	if (!tmp)		panic("U3-DART: Cannot allocate spare page!");	dart_emptyval = DARTMAP_VALID | ((tmp >> PAGE_SHIFT) & DARTMAP_RPNMASK);	/* Map in DART registers. FIXME: Use device node to get base address */	dart = ioremap(DART_BASE, 0x7000);	if (dart == NULL)		panic("U3-DART: Cannot map registers!");	/* Set initial control register contents: table base, 	 * table size and enable bit	 */	regword = DARTCNTL_ENABLE | 		((dart_tablebase >> PAGE_SHIFT) << DARTCNTL_BASE_SHIFT) |		(((dart_tablesize >> PAGE_SHIFT) & DARTCNTL_SIZE_MASK)				 << DARTCNTL_SIZE_SHIFT);	dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize);	/* Fill initial table */	for (i = 0; i < dart_tablesize/4; i++)		dart_vbase[i] = dart_emptyval;	/* Initialize DART with table base and enable it. */	out_be32((unsigned int *)dart, regword);	/* Invalidate DART to get rid of possible stale TLBs */	dart_tlb_invalidate_all();	printk(KERN_INFO "U3/CPC925 DART IOMMU initialized\n");	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/d0035c62d9145a2ce3057c8182a7ff0b4921a41c/u3_iommu.c/buggy/arch/ppc64/kernel/u3_iommu.c