* by calling gpio_line_set(); 
* by calling set_irq_type(). 
void __init ixp2000_init_irq(void){	int irq;	/*	 * Mask all sources	 */	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);	ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);	/* clear all GPIO edge/level detects */	ixp2000_reg_write(IXP2000_GPIO_REDR, 0);	ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);	ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);	ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);	ixp2000_reg_write(IXP2000_GPIO_INCR, -1);	/* clear PCI interrupt sources */	ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);	/*	 * Certain bits in the IRQ status register of the 	 * IXP2000 are reserved. Instead of trying to map	 * things non 1:1 from bit position to IRQ number,	 * we mark the reserved IRQs as invalid. This makes	 * our mask/unmask code much simpler.	 */	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {		if((1 << irq) & IXP2000_VALID_IRQ_MASK) {			set_irq_chip(irq, &ixp2000_irq_chip);			set_irq_handler(irq, do_level_IRQ);			set_irq_flags(irq, IRQF_VALID);		} else set_irq_flags(irq, 0);	}		/*	 * GPIO IRQs are invalid until someone sets the interrupt mode	 * by calling gpio_line_set();	 */	for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {		set_irq_chip(irq, &ixp2000_GPIO_irq_chip);		set_irq_handler(irq, do_level_IRQ);		set_irq_flags(irq, 0);	}	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);	/*	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in	 * entry-macro.S, so we don't need a chained handler for the	 * PCI interrupt source.	 */	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {		set_irq_chip(irq, &ixp2000_pci_irq_chip);		set_irq_handler(irq, do_level_IRQ);		set_irq_flags(irq, IRQF_VALID);	}}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/c4982887cacf2122bc256e901598b58caf4a34be/core.c/buggy/arch/arm/mach-ixp2000/core.c