think_time = tt ? tt->think_time : 0; qh->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (urb->dev->speed, is_input, 0, max_packet (maxp))); 
qh_make (	struct ehci_hcd		*ehci,	struct urb		*urb,	int			flags) {	struct ehci_qh		*qh = ehci_qh_alloc (ehci, flags);	u32			info1 = 0, info2 = 0;	int			is_input, type;	int			maxp = 0;	if (!qh)		return qh;	/*	 * init endpoint/device data for this QH	 */	info1 |= usb_pipeendpoint (urb->pipe) << 8;	info1 |= usb_pipedevice (urb->pipe) << 0;	is_input = usb_pipein (urb->pipe);	type = usb_pipetype (urb->pipe);	maxp = usb_maxpacket (urb->dev, urb->pipe, !is_input);	/* Compute interrupt scheduling parameters just once, and save.	 * - allowing for high bandwidth, how many nsec/uframe are used?	 * - split transactions need a second CSPLIT uframe; same question	 * - splits also need a schedule gap (for full/low speed I/O)	 * - qh has a polling interval	 *	 * For control/bulk requests, the HC or TT handles these.	 */	if (type == PIPE_INTERRUPT) {		qh->usecs = NS_TO_US (usb_calc_bus_time (USB_SPEED_HIGH, is_input, 0,				hb_mult (maxp) * max_packet (maxp)));		qh->start = NO_FRAME;		if (urb->dev->speed == USB_SPEED_HIGH) {			qh->c_usecs = 0;			qh->gap_uf = 0;			qh->period = urb->interval >> 3;			if (qh->period == 0 && urb->interval != 1) {				/* NOTE interval 2 or 4 uframes could work.				 * But interval 1 scheduling is simpler, and				 * includes high bandwidth.				 */				dbg ("intr period %d uframes, NYET!",						urb->interval);				goto done;			}		} else {			/* gap is f(FS/LS transfer times) */			qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed,					is_input, 0, maxp) / (125 * 1000);			/* FIXME this just approximates SPLIT/CSPLIT times */			if (is_input) {		// SPLIT, gap, CSPLIT+DATA				qh->c_usecs = qh->usecs + HS_USECS (0);				qh->usecs = HS_USECS (1);			} else {		// SPLIT+DATA, gap, CSPLIT				qh->usecs += HS_USECS (1);				qh->c_usecs = HS_USECS (0);			}			qh->period = urb->interval;		}	}	/* support for tt scheduling, and access to toggles */	qh->dev = usb_get_dev (urb->dev);	/* using TT? */	switch (urb->dev->speed) {	case USB_SPEED_LOW:		info1 |= (1 << 12);	/* EPS "low" */		/* FALL THROUGH */	case USB_SPEED_FULL:		/* EPS 0 means "full" */		if (type != PIPE_INTERRUPT)			info1 |= (EHCI_TUNE_RL_TT << 28);		if (type == PIPE_CONTROL) {			info1 |= (1 << 27);	/* for TT */			info1 |= 1 << 14;	/* toggle from qtd */		}		info1 |= maxp << 16;		info2 |= (EHCI_TUNE_MULT_TT << 30);		info2 |= urb->dev->ttport << 23;		/* set the address of the TT; for TDI's integrated		 * root hub tt, leave it zeroed.		 */		if (!ehci_is_TDI(ehci)				|| urb->dev->tt->hub !=					ehci_to_hcd(ehci)->self.root_hub)			info2 |= urb->dev->tt->hub->devnum << 16;		/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */		break;	case USB_SPEED_HIGH:		/* no TT involved */		info1 |= (2 << 12);	/* EPS "high" */		if (type == PIPE_CONTROL) {			info1 |= (EHCI_TUNE_RL_HS << 28);			info1 |= 64 << 16;	/* usb2 fixed maxpacket */			info1 |= 1 << 14;	/* toggle from qtd */			info2 |= (EHCI_TUNE_MULT_HS << 30);		} else if (type == PIPE_BULK) {			info1 |= (EHCI_TUNE_RL_HS << 28);			info1 |= 512 << 16;	/* usb2 fixed maxpacket */			info2 |= (EHCI_TUNE_MULT_HS << 30);		} else {		/* PIPE_INTERRUPT */			info1 |= max_packet (maxp) << 16;			info2 |= hb_mult (maxp) << 30;		}		break;	default: 		dbg ("bogus dev %p speed %d", urb->dev, urb->dev->speed);done:		qh_put (qh);		return NULL;	}	/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */	/* init as live, toggle clear, advance to dummy */	qh->qh_state = QH_STATE_IDLE;	qh->hw_info1 = cpu_to_le32 (info1);	qh->hw_info2 = cpu_to_le32 (info2);	usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1);	qh_refresh (ehci, qh);	return qh;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/d0384200f6b608e77fb5ddf7dfae1bf0e42c1c6e/ehci-q.c/buggy/drivers/usb/host/ehci-q.c