if (controller->io_resource->start < 0x00001000UL)	/* FIXME */ controller->io_resource->start = 0x00001000UL;  iomem_resource.end &= 0xfffffffffULL;			/* 64 GB */ 
void __init mips_pcibios_init(void){	struct pci_controller *controller;	switch (mips_revision_corid) {	case MIPS_REVISION_CORID_QED_RM5261:	case MIPS_REVISION_CORID_CORE_LV:	case MIPS_REVISION_CORID_CORE_FPGA:	case MIPS_REVISION_CORID_CORE_FPGAR2:		/*		 * Due to a bug in the Galileo system controller, we need		 * to setup the PCI BAR for the Galileo internal registers.		 * This should be done in the bios/bootprom and will be		 * fixed in a later revision of YAMON (the MIPS boards		 * boot prom).		 */		GT_WRITE(GT_PCI0_CFGADDR_OFS,			 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */			 (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */			 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/			 ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/			 GT_PCI0_CFGADDR_CONFIGEN_BIT );		/* Perform the write */		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));		controller = &gt64120_controller;		break;	case MIPS_REVISION_CORID_BONITO64:	case MIPS_REVISION_CORID_CORE_20K:	case MIPS_REVISION_CORID_CORE_EMUL_BON:		controller = &bonito64_controller;		break;	case MIPS_REVISION_CORID_CORE_MSC:	case MIPS_REVISION_CORID_CORE_FPGA2:	case MIPS_REVISION_CORID_CORE_EMUL_MSC:		controller = &msc_controller;		break;	default:		return;	}	ioport_resource.end = controller->io_resource->end;	register_pci_controller (controller);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/aa0980b8090878bf42bc73a13d051a203a201d7d/pci.c/buggy/arch/mips/mips-boards/generic/pci.c