gpio_ck = clk_get(NULL, "arm_gpio_ck"); if (IS_ERR(gpio_ck)) 
gpio_ick = clk_get(NULL, "arm_gpio_ck"); if (IS_ERR(gpio_ick)) 
static int __init _omap_gpio_init(void){	int i;	struct gpio_bank *bank;	initialized = 1;	if (cpu_is_omap1510()) {		gpio_ck = clk_get(NULL, "arm_gpio_ck");		if (IS_ERR(gpio_ck))			printk("Could not get arm_gpio_ck\n");		else			clk_use(gpio_ck);	}#ifdef CONFIG_ARCH_OMAP1510	if (cpu_is_omap1510()) {		printk(KERN_INFO "OMAP1510 GPIO hardware\n");		gpio_bank_count = 2;		gpio_bank = gpio_bank_1510;	}#endif#if defined(CONFIG_ARCH_OMAP16XX)	if (cpu_is_omap16xx()) {		u32 rev;		gpio_bank_count = 5;		gpio_bank = gpio_bank_1610;		rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);		printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",		       (rev >> 4) & 0x0f, rev & 0x0f);	}#endif#ifdef CONFIG_ARCH_OMAP730	if (cpu_is_omap730()) {		printk(KERN_INFO "OMAP730 GPIO hardware\n");		gpio_bank_count = 7;		gpio_bank = gpio_bank_730;	}#endif#ifdef CONFIG_ARCH_OMAP24XX	if (cpu_is_omap24xx()) {		int rev;		gpio_bank_count = 4;		gpio_bank = gpio_bank_24xx;		rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);		printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",			(rev >> 4) & 0x0f, rev & 0x0f);	}#endif	for (i = 0; i < gpio_bank_count; i++) {		int j, gpio_count = 16;		bank = &gpio_bank[i];		bank->reserved_map = 0;		bank->base = IO_ADDRESS(bank->base);		spin_lock_init(&bank->lock);		if (bank->method == METHOD_MPUIO) {			omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);		}#ifdef CONFIG_ARCH_OMAP1510		if (bank->method == METHOD_GPIO_1510) {			__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);			__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);		}#endif#if defined(CONFIG_ARCH_OMAP16XX)		if (bank->method == METHOD_GPIO_1610) {			__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);			__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);			__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);		}#endif#ifdef CONFIG_ARCH_OMAP730		if (bank->method == METHOD_GPIO_730) {			__raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);			__raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);			gpio_count = 32; /* 730 has 32-bit GPIOs */		}#endif#ifdef CONFIG_ARCH_OMAP24XX		if (bank->method == METHOD_GPIO_24XX) {			__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);			__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);			gpio_count = 32;		}#endif		for (j = bank->virtual_irq_start;		     j < bank->virtual_irq_start + gpio_count; j++) {			if (bank->method == METHOD_MPUIO)				set_irq_chip(j, &mpuio_irq_chip);			else				set_irq_chip(j, &gpio_irq_chip);			set_irq_handler(j, do_simple_IRQ);			set_irq_flags(j, IRQF_VALID);		}		set_irq_chained_handler(bank->irq, gpio_irq_handler);		set_irq_data(bank->irq, bank);	}	/* Enable system clock for GPIO module.	 * The CAM_CLK_CTRL *is* really the right place. */	if (cpu_is_omap16xx())		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/1a8bfa1eb998af6e650ad26201f7cae9f2a2fdc8/gpio.c/buggy/arch/arm/plat-omap/gpio.c