iommu->iommu_cur_ctx = 0; 
iommu->ctx_lowest_free = 1; 
static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm){	struct pci_iommu *iommu = pbm->iommu;	unsigned long tsbbase, i, tagbase, database, order;	u32 vdma[2], dma_mask;	u64 control;	int err, tsbsize;	err = prom_getproperty(pbm->prom_node, "virtual-dma",			       (char *)&vdma[0], sizeof(vdma));	if (err == 0 || err == -1) {		/* No property, use default values. */		vdma[0] = 0xc0000000;		vdma[1] = 0x40000000;	}	dma_mask = vdma[0];	switch (vdma[1]) {		case 0x20000000:			dma_mask |= 0x1fffffff;			tsbsize = 64;			break;		case 0x40000000:			dma_mask |= 0x3fffffff;			tsbsize = 128;			break;		case 0x80000000:			dma_mask |= 0x7fffffff;			tsbsize = 128;			break;		default:			prom_printf("SCHIZO: strange virtual-dma size.\n");			prom_halt();	};	/* Setup initial software IOMMU state. */	spin_lock_init(&iommu->lock);	iommu->iommu_cur_ctx = 0;	/* Register addresses, SCHIZO has iommu ctx flushing. */	iommu->iommu_control  = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;	iommu->iommu_tsbbase  = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;	iommu->iommu_flush    = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;	iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;	/* We use the main control/status register of SCHIZO as the write	 * completion register.	 */	iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;	/*	 * Invalidate TLB Entries.	 */	control = schizo_read(iommu->iommu_control);	control |= SCHIZO_IOMMU_CTRL_DENAB;	schizo_write(iommu->iommu_control, control);	tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;	for(i = 0; i < 16; i++) {		schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);		schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);	}	/* Leave diag mode enabled for full-flushing done	 * in pci_iommu.c	 */	iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);	if (!iommu->dummy_page) {		prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");		prom_halt();	}	memset((void *)iommu->dummy_page, 0, PAGE_SIZE);	iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);	/* Using assumed page size 8K with 128K entries we need 1MB iommu page	 * table (128K ioptes * 8 bytes per iopte).  This is	 * page order 7 on UltraSparc.	 */	order = get_order(tsbsize * 8 * 1024);	tsbbase = __get_free_pages(GFP_KERNEL, order);	if (!tsbbase) {		prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name);		prom_halt();	}	iommu->page_table = (iopte_t *)tsbbase;	iommu->page_table_map_base = vdma[0];	iommu->dma_addr_mask = dma_mask;	pci_iommu_table_init(iommu, PAGE_SIZE << order);	switch (tsbsize) {	case 64:		iommu->page_table_sz_bits = 16;		break;	case 128:		iommu->page_table_sz_bits = 17;		break;	default:		prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);		prom_halt();		break;	};	/* We start with no consistent mappings. */	iommu->lowest_consistent_map =		1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);	for (i = 0; i < PBM_NCLUSTERS; i++) {		iommu->alloc_info[i].flush = 0;		iommu->alloc_info[i].next = 0;	}	schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));	control = schizo_read(iommu->iommu_control);	control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);	switch (tsbsize) {	case 64:		control |= SCHIZO_IOMMU_TSBSZ_64K;		break;	case 128:		control |= SCHIZO_IOMMU_TSBSZ_128K;		break;	};	control |= SCHIZO_IOMMU_CTRL_ENAB;	schizo_write(iommu->iommu_control, control);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/7c963ad1d113790a8c723a178988b675868f3abe/pci_schizo.c/clean/arch/sparc64/kernel/pci_schizo.c