/* * prepare target chip field */ cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]); apic_write_around(APIC_ICR2, cfg); 
/* * program the ICR */ cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL); 
static inline void send_IPI_mask_sequence(cpumask_t mask, int vector){	unsigned long cfg, flags;	unsigned long query_cpu;	/*	 * Hack. The clustered APIC addressing mode doesn't allow us to send	 * to an arbitrary mask, so I do a unicast to each CPU instead.	 * - mbligh	 */	local_irq_save(flags);	for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {		if (cpu_isset(query_cpu, mask)) {			/*			 * Wait for idle.			 */			apic_wait_icr_idle();			/*			 * prepare target chip field			 */			cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);			apic_write_around(APIC_ICR2, cfg);			/*			 * program the ICR			 */			cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);			/*			 * Send the IPI. The write to APIC_ICR fires this off.			 */			apic_write_around(APIC_ICR, cfg);		}	}	local_irq_restore(flags);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/74f0629397cb435e144ff47c48f3bc39e879f196/ipi.h/buggy/include/asm-x86_64/ipi.h