static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) 
static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) 
static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector){	struct IO_APIC_route_entry entry;	unsigned long flags;	memset(&entry,0,sizeof(entry));	disable_8259A_irq(0);	/* mask LVT0 */	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);	/*	 * We use logical delivery to get the timer IRQ	 * to the first CPU.	 */	entry.dest_mode = INT_DEST_MODE;	entry.mask = 0;					/* unmask IRQ now */	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);	entry.delivery_mode = INT_DELIVERY_MODE;	entry.polarity = 0;	entry.trigger = 0;	entry.vector = vector;	/*	 * The timer IRQ doesn't have to know that behind the	 * scene we have a 8259A-master in AEOI mode ...	 */	irq_desc[0].handler = &ioapic_edge_type;	/*	 * Add it to the IO-APIC irq-routing table:	 */	spin_lock_irqsave(&ioapic_lock, flags);	io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));	io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));	spin_unlock_irqrestore(&ioapic_lock, flags);	enable_8259A_irq(0);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/fcfd636a728fe2b8fb8c8fd8c557302059580577/io_apic.c/clean/arch/i386/kernel/io_apic.c