write_icu1(intassign2, INTASSIGN2); write_icu1(intassign3, INTASSIGN3); 
icu1_write(INTASSIGN2, intassign2); icu1_write(INTASSIGN3, intassign3); 
static inline int set_sysint2_assign(unsigned int irq, unsigned char assign){	irq_desc_t *desc = irq_desc + irq;	uint16_t intassign2, intassign3;	unsigned int pin;	pin = SYSINT2_IRQ_TO_PIN(irq);	spin_lock_irq(&desc->lock);	intassign2 = read_icu1(INTASSIGN2);	intassign3 = read_icu1(INTASSIGN3);	switch (pin) {	case 0:		intassign2 &= ~INTASSIGN_MASK;		intassign2 |= (uint16_t)assign;		break;	case 1:		intassign2 &= ~(INTASSIGN_MASK << 3);		intassign2 |= (uint16_t)assign << 3;		break;	case 3:		intassign2 &= ~(INTASSIGN_MASK << 6);		intassign2 |= (uint16_t)assign << 6;		break;	case 4:		intassign2 &= ~(INTASSIGN_MASK << 9);		intassign2 |= (uint16_t)assign << 9;		break;	case 5:		intassign2 &= ~(INTASSIGN_MASK << 12);		intassign2 |= (uint16_t)assign << 12;		break;	case 6:		intassign3 &= ~INTASSIGN_MASK;		intassign3 |= (uint16_t)assign;		break;	case 7:		intassign3 &= ~(INTASSIGN_MASK << 3);		intassign3 |= (uint16_t)assign << 3;		break;	case 8:		intassign3 &= ~(INTASSIGN_MASK << 6);		intassign3 |= (uint16_t)assign << 6;		break;	case 9:		intassign3 &= ~(INTASSIGN_MASK << 9);		intassign3 |= (uint16_t)assign << 9;		break;	case 10:		intassign3 &= ~(INTASSIGN_MASK << 12);		intassign3 |= (uint16_t)assign << 12;		break;	default:		return -EINVAL;	}	sysint2_assign[pin] = assign;	write_icu1(intassign2, INTASSIGN2);	write_icu1(intassign3, INTASSIGN3);	spin_unlock_irq(&desc->lock);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/979934da9e7a0005bd9c8b1d7d00febb59ff67f7/icu.c/clean/arch/mips/vr41xx/common/icu.c