if(hw->dma_fairness) { 
if(hw->dma_fairness && hw->mac_type <= e1000_82543) { 
e1000_init_hw(struct e1000_hw *hw){    uint32_t ctrl;    uint32_t i;    int32_t ret_val;    uint16_t pcix_cmd_word;    uint16_t pcix_stat_hi_word;    uint16_t cmd_mmrbc;    uint16_t stat_mmrbc;    DEBUGFUNC("e1000_init_hw");    /* Initialize Identification LED */    ret_val = e1000_id_led_init(hw);    if(ret_val) {        DEBUGOUT("Error Initializing Identification LED\n");        return ret_val;    }    /* Set the media type and TBI compatibility */    e1000_set_media_type(hw);    /* Disabling VLAN filtering. */    DEBUGOUT("Initializing the IEEE VLAN\n");    E1000_WRITE_REG(hw, VET, 0);    e1000_clear_vfta(hw);    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */    if(hw->mac_type == e1000_82542_rev2_0) {        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");        e1000_pci_clear_mwi(hw);        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);        E1000_WRITE_FLUSH(hw);        msec_delay(5);    }    /* Setup the receive address. This involves initializing all of the Receive     * Address Registers (RARs 0 - 15).     */    e1000_init_rx_addrs(hw);    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */    if(hw->mac_type == e1000_82542_rev2_0) {        E1000_WRITE_REG(hw, RCTL, 0);        E1000_WRITE_FLUSH(hw);        msec_delay(1);        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)            e1000_pci_set_mwi(hw);    }    /* Zero out the Multicast HASH table */    DEBUGOUT("Zeroing the MTA\n");    for(i = 0; i < E1000_MC_TBL_SIZE; i++)        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);    /* Set the PCI priority bit correctly in the CTRL register.  This     * determines if the adapter gives priority to receives, or if it     * gives equal priority to transmits and receives.     */    if(hw->dma_fairness) {        ctrl = E1000_READ_REG(hw, CTRL);        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);    }    switch(hw->mac_type) {    case e1000_82545_rev_3:    case e1000_82546_rev_3:        break;    default:        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */        if(hw->bus_type == e1000_bus_type_pcix) {            e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);            e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,                &pcix_stat_hi_word);            cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>                PCIX_COMMAND_MMRBC_SHIFT;            stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>                PCIX_STATUS_HI_MMRBC_SHIFT;            if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)                stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;            if(cmd_mmrbc > stat_mmrbc) {                pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;                pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;                e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,                    &pcix_cmd_word);            }        }        break;    }    /* Call a subroutine to configure the link and setup flow control. */    ret_val = e1000_setup_link(hw);    /* Set the transmit descriptor write-back policy */    if(hw->mac_type > e1000_82544) {        ctrl = E1000_READ_REG(hw, TXDCTL);        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;        E1000_WRITE_REG(hw, TXDCTL, ctrl);    }    /* Clear all of the statistics registers (clear on read).  It is     * important that we do this after we have tried to establish link     * because the symbol error count will increment wildly if there     * is no link.     */    e1000_clear_hw_cntrs(hw);    return ret_val;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/2d7edb923a823660b081bd4c660300ee19adca8d/e1000_hw.c/clean/drivers/net/e1000/e1000_hw.c