drm_vbl_send_signals( dev ); 
drm_vbl_send_signals(dev); handled = 1; }  /* SOFTRAP interrupt */ if (status & MGA_SOFTRAPEN) { const u32 prim_start = MGA_READ(MGA_PRIMADDRESS); const u32 prim_end   = MGA_READ(MGA_PRIMEND);   MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);  /* In addition to clearing the interrupt-pending bit, we * have to write to MGA_PRIMEND to re-start the DMA operation. */ if ( (prim_start & ~0x03) != (prim_end & ~0x03) ) { MGA_WRITE(MGA_PRIMEND, prim_end); }  atomic_inc(&dev_priv->last_fence_retired); DRM_WAKEUP(&dev_priv->fence_queue); handled = 1; }  if ( handled ) { 
irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ){	drm_device_t *dev = (drm_device_t *) arg;	drm_mga_private_t *dev_priv = 	   (drm_mga_private_t *)dev->dev_private;	int status;	status = MGA_READ( MGA_STATUS );		/* VBLANK interrupt */	if ( status & MGA_VLINEPEN ) {		MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR );		atomic_inc(&dev->vbl_received);		DRM_WAKEUP(&dev->vbl_queue);		drm_vbl_send_signals( dev );		return IRQ_HANDLED;	}	return IRQ_NONE;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/6795c985a648d1e90b367cc1387c18205ecca4b8/mga_irq.c/buggy/drivers/char/drm/mga_irq.c