writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700)); 
writeq(val64, (void __iomem *)bar0 + 0x2700); 
static int start_nic(struct s2io_nic *nic){	XENA_dev_config_t __iomem *bar0 = nic->bar0;	struct net_device *dev = nic->dev;	register u64 val64 = 0;	u16 interruptible;	u16 subid, i;	mac_info_t *mac_control;	struct config_param *config;	mac_control = &nic->mac_control;	config = &nic->config;	/*  PRC Initialization and configuration */	for (i = 0; i < config->rx_ring_num; i++) {		writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,		       &bar0->prc_rxd0_n[i]);		val64 = readq(&bar0->prc_ctrl_n[i]);		if (nic->config.bimodal)			val64 |= PRC_CTRL_BIMODAL_INTERRUPT;#ifndef CONFIG_2BUFF_MODE		val64 |= PRC_CTRL_RC_ENABLED;#else		val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;#endif		writeq(val64, &bar0->prc_ctrl_n[i]);	}#ifdef CONFIG_2BUFF_MODE	/* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */	val64 = readq(&bar0->rx_pa_cfg);	val64 |= RX_PA_CFG_IGNORE_L2_ERR;	writeq(val64, &bar0->rx_pa_cfg);#endif	/*	 * Enabling MC-RLDRAM. After enabling the device, we timeout	 * for around 100ms, which is approximately the time required	 * for the device to be ready for operation.	 */	val64 = readq(&bar0->mc_rldram_mrs);	val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);	val64 = readq(&bar0->mc_rldram_mrs);	msleep(100);	/* Delay by around 100 ms. */	/* Enabling ECC Protection. */	val64 = readq(&bar0->adapter_control);	val64 &= ~ADAPTER_ECC_EN;	writeq(val64, &bar0->adapter_control);	/*	 * Clearing any possible Link state change interrupts that	 * could have popped up just before Enabling the card.	 */	val64 = readq(&bar0->mac_rmac_err_reg);	if (val64)		writeq(val64, &bar0->mac_rmac_err_reg);	/*	 * Verify if the device is ready to be enabled, if so enable	 * it.	 */	val64 = readq(&bar0->adapter_status);	if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {		DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);		DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",			  (unsigned long long) val64);		return FAILURE;	}	/*  Enable select interrupts */	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;	interruptible |= TX_PIC_INTR | RX_PIC_INTR;	interruptible |= TX_MAC_INTR | RX_MAC_INTR;	en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);	/*	 * With some switches, link might be already up at this point.	 * Because of this weird behavior, when we enable laser,	 * we may not get link. We need to handle this. We cannot	 * figure out which switch is misbehaving. So we are forced to	 * make a global change.	 */	/* Enabling Laser. */	val64 = readq(&bar0->adapter_control);	val64 |= ADAPTER_EOI_TX_ON;	writeq(val64, &bar0->adapter_control);	/* SXE-002: Initialize link and activity LED */	subid = nic->pdev->subsystem_device;	if (((subid & 0xFF) >= 0x07) &&	    (nic->device_type == XFRAME_I_DEVICE)) {		val64 = readq(&bar0->gpio_control);		val64 |= 0x0000800000000000ULL;		writeq(val64, &bar0->gpio_control);		val64 = 0x0411040400000000ULL;		writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));	}	/*	 * Don't see link state interrupts on certain switches, so	 * directly scheduling a link state task from here.	 */	schedule_work(&nic->set_link_task);	return SUCCESS;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/509a2671a445345d917d8828b2cb3f5743af6093/s2io.c/clean/drivers/net/s2io.c