 err_out_priv: mv_priv_free(pp, dev); err_out_pp: kfree(pp); err_out: return rc; 
static int mv_port_start(struct ata_port *ap){	struct device *dev = ap->host_set->dev;	struct mv_port_priv *pp;	void __iomem *port_mmio = mv_ap_base(ap);	void *mem;	dma_addr_t mem_dma;	pp = kmalloc(sizeof(*pp), GFP_KERNEL);	if (!pp) {		return -ENOMEM;	}	memset(pp, 0, sizeof(*pp));	mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, 				 GFP_KERNEL);	if (!mem) {		kfree(pp);		return -ENOMEM;	}	memset(mem, 0, MV_PORT_PRIV_DMA_SZ);	/* First item in chunk of DMA memory: 	 * 32-slot command request table (CRQB), 32 bytes each in size	 */	pp->crqb = mem;	pp->crqb_dma = mem_dma;	mem += MV_CRQB_Q_SZ;	mem_dma += MV_CRQB_Q_SZ;	/* Second item: 	 * 32-slot command response table (CRPB), 8 bytes each in size	 */	pp->crpb = mem;	pp->crpb_dma = mem_dma;	mem += MV_CRPB_Q_SZ;	mem_dma += MV_CRPB_Q_SZ;	/* Third item:	 * Table of scatter-gather descriptors (ePRD), 16 bytes each	 */	pp->sg_tbl = mem;	pp->sg_tbl_dma = mem_dma;	writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT | 		 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);	writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);	writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, 		 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);	writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);	writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);	writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);	writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, 		 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);	pp->req_producer = pp->rsp_consumer = 0;	/* Don't turn on EDMA here...do it before DMA commands only.  Else	 * we'll be unable to send non-data, PIO, etc due to restricted access	 * to shadow regs.	 */	ap->private_data = pp;	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/6037d6bbdff65eb5a84fe35e140f4da4f7cc103a/sata_mv.c/clean/drivers/scsi/sata_mv.c