dvb_pll_configure(state->config->pll_desc, buf, param->frequency, 0); dprintk("%s: tuner bytes: 0x%02x 0x%02x " "0x%02x 0x%02x\n", __FUNCTION__, buf[0],buf[1],buf[2],buf[3]); i2c_writebytes(state, state->config->pll_address ,buf, 4); 
u8 buf[5]; 
static int lgdt3302_set_parameters(struct dvb_frontend* fe,				   struct dvb_frontend_parameters *param){	u8 buf[4];	struct lgdt3302_state* state =		(struct lgdt3302_state*) fe->demodulator_priv;	/* Use 50MHz parameter values from spec sheet since xtal is 50 */	static u8 top_ctrl_cfg[]   = { TOP_CONTROL, 0x03 };	static u8 vsb_freq_cfg[]   = { VSB_CARRIER_FREQ0, 0x00, 0x87, 0x8e, 0x01 };	static u8 demux_ctrl_cfg[] = { DEMUX_CONTROL, 0xfb };	static u8 agc_rf_cfg[]     = { AGC_RF_BANDWIDTH0, 0x40, 0x93, 0x00 };	static u8 agc_ctrl_cfg[]   = { AGC_FUNC_CTRL2, 0xc6, 0x40 };	static u8 agc_delay_cfg[]  = { AGC_DELAY0, 0x07, 0x00, 0xfe };	static u8 agc_loop_cfg[]   = { AGC_LOOP_BANDWIDTH0, 0x08, 0x9a };	/* Change only if we are actually changing the modulation */	if (state->current_modulation != param->u.vsb.modulation) {		switch(param->u.vsb.modulation) {		case VSB_8:			dprintk("%s: VSB_8 MODE\n", __FUNCTION__);			/* Select VSB mode and serial MPEG interface */			top_ctrl_cfg[1] = 0x07;			break;		case QAM_64:			dprintk("%s: QAM_64 MODE\n", __FUNCTION__);			/* Select QAM_64 mode and serial MPEG interface */			top_ctrl_cfg[1] = 0x04;			break;		case QAM_256:			dprintk("%s: QAM_256 MODE\n", __FUNCTION__);			/* Select QAM_256 mode and serial MPEG interface */			top_ctrl_cfg[1] = 0x05;			break;		default:			printk(KERN_WARNING "lgdt3302: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation);			return -1;		}		/* Initializations common to all modes */		/* Select the requested mode */		i2c_writebytes(state, state->config->demod_address,			       top_ctrl_cfg, sizeof(top_ctrl_cfg));		/* Change the value of IFBW[11:0]		   of AGC IF/RF loop filter bandwidth register */		i2c_writebytes(state, state->config->demod_address,			       agc_rf_cfg, sizeof(agc_rf_cfg));		/* Change the value of bit 6, 'nINAGCBY' and		   'NSSEL[1:0] of ACG function control register 2 */		/* Change the value of bit 6 'RFFIX'		   of AGC function control register 3 */		i2c_writebytes(state, state->config->demod_address,			       agc_ctrl_cfg, sizeof(agc_ctrl_cfg));		/* Change the TPCLK pin polarity		   data is valid on falling clock */		i2c_writebytes(state, state->config->demod_address,			       demux_ctrl_cfg, sizeof(demux_ctrl_cfg));		/* Change the value of NCOCTFV[25:0] of carrier		   recovery center frequency register */		i2c_writebytes(state, state->config->demod_address,				       vsb_freq_cfg, sizeof(vsb_freq_cfg));		/* Set the value of 'INLVTHD' register 0x2a/0x2c to 0x7fe */		i2c_writebytes(state, state->config->demod_address,			       agc_delay_cfg, sizeof(agc_delay_cfg));		/* Change the value of IAGCBW[15:8]		   of inner AGC loop filter bandwith */		i2c_writebytes(state, state->config->demod_address,			       agc_loop_cfg, sizeof(agc_loop_cfg));		state->config->set_ts_params(fe, 0);		state->current_modulation = param->u.vsb.modulation;	}	/* Change only if we are actually changing the channel */	if (state->current_frequency != param->frequency) {		dvb_pll_configure(state->config->pll_desc, buf,				  param->frequency, 0);		dprintk("%s: tuner bytes: 0x%02x 0x%02x "			"0x%02x 0x%02x\n", __FUNCTION__, buf[0],buf[1],buf[2],buf[3]);		i2c_writebytes(state, state->config->pll_address ,buf, 4);		/* Check the status of the tuner pll */		i2c_readbytes(state, state->config->pll_address, buf, 1);		dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[0]);		/* Update current frequency */		state->current_frequency = param->frequency;	}	lgdt3302_SwReset(state);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/b6aef071bdef0cd9f69113bb3575aa45fafdbbbf/lgdt3302.c/buggy/drivers/media/dvb/frontends/lgdt3302.c