if (vma->vm_mm == current->active_mm) { #ifdef CONFIG_8xx /* On 8xx, cache control instructions (particularly * "dcbst" from flush_dcache_icache) fault as write * operation if there is an unpopulated TLB entry * for the address in question. To workaround that, * we invalidate the TLB here, thus avoiding dcbst * misbehaviour. */ _tlbie(address); #endif 
if (vma->vm_mm == current->active_mm) 
void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,		      pte_t pte){	/* handle i-cache coherency */	unsigned long pfn = pte_pfn(pte);	if (pfn_valid(pfn)) {		struct page *page = pfn_to_page(pfn);		if (!PageReserved(page)		    && !test_bit(PG_arch_1, &page->flags)) {			if (vma->vm_mm == current->active_mm) {#ifdef CONFIG_8xx			/* On 8xx, cache control instructions (particularly 		 	 * "dcbst" from flush_dcache_icache) fault as write 			 * operation if there is an unpopulated TLB entry 			 * for the address in question. To workaround that, 			 * we invalidate the TLB here, thus avoiding dcbst 			 * misbehaviour.			 */				_tlbie(address);#endif				__flush_dcache_icache((void *) address);			} else				flush_dcache_icache_page(page);			set_bit(PG_arch_1, &page->flags);		}	}#ifdef CONFIG_PPC_STD_MMU	/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */	if (Hash != 0 && pte_young(pte)) {		struct mm_struct *mm;		pmd_t *pmd;		mm = (address < TASK_SIZE)? vma->vm_mm: &init_mm;		pmd = pmd_offset(pgd_offset(mm, address), address);		if (!pmd_none(*pmd))			add_hash_page(mm->context, address, pmd_val(*pmd));	}#endif}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/eb07d964b4491d1bb5864cd3d7e7633ccdda9a53/init.c/buggy/arch/ppc/mm/init.c