shift = port * 2; 
shift = port << 1;		/* (port * 2) */ 
static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,			 unsigned int hc){	void __iomem *mmio = host_set->mmio_base;	void __iomem *hc_mmio = mv_hc_base(mmio, hc);	struct ata_port *ap;	struct ata_queued_cmd *qc;	u32 hc_irq_cause;	int shift, port, port0, hard_port;	u8 ata_status;	if (hc == 0) {		port0 = 0;	} else {		port0 = MV_PORTS_PER_HC;	}	/* we'll need the HC success int register in most cases */	hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);	if (hc_irq_cause) {		writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);	}	VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",		hc,relevant,hc_irq_cause);	for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {		ap = host_set->ports[port];		hard_port = port & MV_PORT_MASK;	/* range 0-3 */		ata_status = 0xffU;		if (((CRBP_DMA_DONE | DEV_IRQ) << hard_port) & hc_irq_cause) {			BUG_ON(NULL == ap);			/* rcv'd new resp, basic DMA complete, or ATA IRQ */			/* This is needed to clear the ATA INTRQ.			 * FIXME: don't read the status reg in EDMA mode!			 */			ata_status = readb((void __iomem *)					   ap->ioaddr.status_addr);		}		shift = port * 2;		if (port >= MV_PORTS_PER_HC) {			shift++;	/* skip bit 8 in the HC Main IRQ reg */		}		if ((PORT0_ERR << shift) & relevant) {			mv_err_intr(ap);			/* FIXME: smart to OR in ATA_ERR? */			ata_status = readb((void __iomem *)					   ap->ioaddr.status_addr) | ATA_ERR;		}				if (ap) {			qc = ata_qc_from_tag(ap, ap->active_tag);			if (NULL != qc) {				VPRINTK("port %u IRQ found for qc, "					"ata_status 0x%x\n", port,ata_status);				BUG_ON(0xffU == ata_status);				/* mark qc status appropriately */				ata_qc_complete(qc, ata_status);			}		}	}	VPRINTK("EXIT\n");}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/31961943e3110c5a1c36b1e0069c29f7c4380e51/sata_mv.c/buggy/drivers/scsi/sata_mv.c