bp->hw_rx_cons = 0; 
bnx2_init_rx_ring(struct bnx2 *bp){	struct rx_bd *rxbd;	int i;	u16 prod, ring_prod; 	u32 val;	/* 8 for CRC and VLAN */	bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;	/* 8 for alignment */	bp->rx_buf_size = bp->rx_buf_use_size + 8;	ring_prod = prod = bp->rx_prod = 0;	bp->rx_cons = 0;	bp->rx_prod_bseq = 0;			rxbd = &bp->rx_desc_ring[0];	for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {		rxbd->rx_bd_len = bp->rx_buf_use_size;		rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;	}	rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;	rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;	val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;	val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;	val |= 0x02 << 8;	CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);	val = (u64) bp->rx_desc_mapping >> 32;	CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);	val = (u64) bp->rx_desc_mapping & 0xffffffff;	CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);	for ( ;ring_prod < bp->rx_ring_size; ) {		if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {			break;		}		prod = NEXT_RX_BD(prod);		ring_prod = RX_RING_IDX(prod);	}	bp->rx_prod = prod;	REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);	REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/f4e418f7f3286f854883f9f7e3bbf7005340d2de/bnx2.c/clean/drivers/net/bnx2.c