if (nic->intr_type == INTA) 
if (sp->intr_type == INTA) 
int s2io_set_swapper(nic_t * sp){	struct net_device *dev = sp->dev;	XENA_dev_config_t __iomem *bar0 = sp->bar0;	u64 val64, valt, valr;	/*	 * Set proper endian settings and verify the same by reading	 * the PIF Feed-back register.	 */	val64 = readq(&bar0->pif_rd_swapper_fb);	if (val64 != 0x0123456789ABCDEFULL) {		int i = 0;		u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */				0x8100008181000081ULL,  /* FE=1, SE=0 */				0x4200004242000042ULL,  /* FE=0, SE=1 */				0};                     /* FE=0, SE=0 */		while(i<4) {			writeq(value[i], &bar0->swapper_ctrl);			val64 = readq(&bar0->pif_rd_swapper_fb);			if (val64 == 0x0123456789ABCDEFULL)				break;			i++;		}		if (i == 4) {			DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",				dev->name);			DBG_PRINT(ERR_DBG, "feedback read %llx\n",				(unsigned long long) val64);			return FAILURE;		}		valr = value[i];	} else {		valr = readq(&bar0->swapper_ctrl);	}	valt = 0x0123456789ABCDEFULL;	writeq(valt, &bar0->xmsi_address);	val64 = readq(&bar0->xmsi_address);	if(val64 != valt) {		int i = 0;		u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */				0x0081810000818100ULL,  /* FE=1, SE=0 */				0x0042420000424200ULL,  /* FE=0, SE=1 */				0};                     /* FE=0, SE=0 */		while(i<4) {			writeq((value[i] | valr), &bar0->swapper_ctrl);			writeq(valt, &bar0->xmsi_address);			val64 = readq(&bar0->xmsi_address);			if(val64 == valt)				break;			i++;		}		if(i == 4) {			unsigned long long x = val64;			DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");			DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);			return FAILURE;		}	}	val64 = readq(&bar0->swapper_ctrl);	val64 &= 0xFFFF000000000000ULL;#ifdef  __BIG_ENDIAN	/*	 * The device by default set to a big endian format, so a	 * big endian driver need not set anything.	 */	val64 |= (SWAPPER_CTRL_TXP_FE |		 SWAPPER_CTRL_TXP_SE |		 SWAPPER_CTRL_TXD_R_FE |		 SWAPPER_CTRL_TXD_W_FE |		 SWAPPER_CTRL_TXF_R_FE |		 SWAPPER_CTRL_RXD_R_FE |		 SWAPPER_CTRL_RXD_W_FE |		 SWAPPER_CTRL_RXF_W_FE |		 SWAPPER_CTRL_XMSI_FE |		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);	if (nic->intr_type == INTA)		val64 |= SWAPPER_CTRL_XMSI_SE;	writeq(val64, &bar0->swapper_ctrl);#else	/*	 * Initially we enable all bits to make it accessible by the	 * driver, then we selectively enable only those bits that	 * we want to set.	 */	val64 |= (SWAPPER_CTRL_TXP_FE |		 SWAPPER_CTRL_TXP_SE |		 SWAPPER_CTRL_TXD_R_FE |		 SWAPPER_CTRL_TXD_R_SE |		 SWAPPER_CTRL_TXD_W_FE |		 SWAPPER_CTRL_TXD_W_SE |		 SWAPPER_CTRL_TXF_R_FE |		 SWAPPER_CTRL_RXD_R_FE |		 SWAPPER_CTRL_RXD_R_SE |		 SWAPPER_CTRL_RXD_W_FE |		 SWAPPER_CTRL_RXD_W_SE |		 SWAPPER_CTRL_RXF_W_FE |		 SWAPPER_CTRL_XMSI_FE |		 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);	if (sp->intr_type == INTA)		val64 |= SWAPPER_CTRL_XMSI_SE;	writeq(val64, &bar0->swapper_ctrl);#endif	val64 = readq(&bar0->swapper_ctrl);	/*	 * Verifying if endian settings are accurate by reading a	 * feedback register.	 */	val64 = readq(&bar0->pif_rd_swapper_fb);	if (val64 != 0x0123456789ABCDEFULL) {		/* Endian settings are incorrect, calls for another dekko. */		DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",			  dev->name);		DBG_PRINT(ERR_DBG, "feedback read %llx\n",			  (unsigned long long) val64);		return FAILURE;	}	return SUCCESS;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/923833405d8d81b5be036093773d88d87fc7e1bd/s2io.c/clean/drivers/net/s2io.c