power = sky2_read32(hw, PCI_C(PCI_DEV_REG1)); power &= ~(PCI_Y2_PHY1_POWD|PCI_Y2_PHY2_POWD);  /* back asswards .. */ 
pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power); power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);  /* looks like this xl is back asswards .. */ 
static int sky2_reset(struct sky2_hw *hw){	u32 ctst, power;	u16 status;	u8 t8, pmd_type;	int i;	ctst = sky2_read32(hw, B0_CTST);	sky2_write8(hw, B0_CTST, CS_RST_CLR);	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",		       pci_name(hw->pdev), hw->chip_id);		return -EOPNOTSUPP;	}	/* disable ASF */	if (hw->chip_id <= CHIP_ID_YUKON_EC) {		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);		sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);	}	/* do a SW reset */	sky2_write8(hw, B0_CTST, CS_RST_SET);	sky2_write8(hw, B0_CTST, CS_RST_CLR);	/* clear PCI errors, if any */	status = sky2_read16(hw, PCI_C(PCI_STATUS));	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);	sky2_write16(hw, PCI_C(PCI_STATUS),		     status | PCI_STATUS_ERROR_BITS);	sky2_write8(hw, B0_CTST, CS_MRST_CLR);	/* clear any PEX errors */	if (is_pciex(hw)) {		sky2_write32(hw, PCI_C(PEX_UNC_ERR_STAT), 0xffffffffUL);		sky2_read16(hw, PCI_C(PEX_LNK_STAT));	}	pmd_type = sky2_read8(hw, B2_PMD_TYP);	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');	hw->ports = 1;	t8 = sky2_read8(hw, B2_Y2_HW_RES);	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))			++hw->ports;	}	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;	/* switch power to VCC (WA for VAUX problem) */	sky2_write8(hw, B0_POWER_CTRL,		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);	/* disable Core Clock Division, */	sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)		/* enable bits are inverted */		sky2_write8(hw, B2_Y2_CLK_GATE,			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);		else			sky2_write8(hw, B2_Y2_CLK_GATE, 0);	/* Turn off phy power saving */	power = sky2_read32(hw, PCI_C(PCI_DEV_REG1));	power &= ~(PCI_Y2_PHY1_POWD|PCI_Y2_PHY2_POWD);	/* back asswards .. */	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {		power |= PCI_Y2_PHY1_COMA;		if (hw->ports > 1)			power |= PCI_Y2_PHY2_COMA;	}	sky2_write32(hw, PCI_C(PCI_DEV_REG1), power);	for (i = 0; i < hw->ports; i++) {		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);	}	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);	sky2_write32(hw, B2_I2C_IRQ, 1); /* Clear I2C IRQ noise */	/* turn off hardware timer (unused) */	sky2_write8(hw, B2_TI_CTRL, TIM_STOP);	sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);		sky2_write8(hw, B0_Y2LED, LED_STAT_ON);	/* Turn on descriptor polling  -- is this necessary? */	sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));	sky2_write8(hw, B28_DPT_CTRL, DPT_START);	/* Turn off receive timestamp */	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);	/* enable the Tx Arbiters */	for (i = 0; i < hw->ports; i++)		sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);	/* Initialize ram interface */	for (i = 0; i < hw->ports; i++) {		sky2_write16(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);	}	/* Optimize PCI Express access */	if (is_pciex(hw)) {		u16 ctrl = sky2_read32(hw, PCI_C(PEX_DEV_CTRL));		ctrl &= ~PEX_DC_MAX_RRS_MSK;		ctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);		sky2_write16(hw, PCI_C(PEX_DEV_CTRL), ctrl);		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);	}	sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);	hw->intr_mask = Y2_IS_BASE;	sky2_write32(hw, B0_IMSK, hw->intr_mask);	/* disable all GMAC IRQ's */	sky2_write8(hw, GMAC_IRQ_MSK, 0);	spin_lock_bh(&hw->phy_lock);	for (i = 0; i < hw->ports; i++)		sky2_phy_reset(hw, i);	spin_unlock_bh(&hw->phy_lock);	/* Setup ring for status responses */	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,					 &hw->st_dma);	if (!hw->st_le)		return -ENOMEM;	memset(hw->st_le, 0, STATUS_LE_BYTES);	hw->st_idx = 0;	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);	sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);	sky2_write32(hw, STAT_LIST_ADDR_HI, (u64)hw->st_dma >> 32);	/* Set the list last index */	sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE-1);	if (is_ec_a1(hw)) {		/* WA for dev. #4.3 */		sky2_write16(hw, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);		/* set Status-FIFO watermark */		sky2_write8(hw, STAT_FIFO_WM, 0x21);	/* WA for dev. #4.18 */		/* set Status-FIFO ISR watermark */		sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07);/* WA for dev. #4.18 */		/* WA for dev. #4.3 and #4.18 */		/* set Status-FIFO Tx timer init value */		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));	} else {		/*		 * Theses settings should avoid the		 * temporary hanging of the status BMU.		 * May be not all required... still under investigation...		 */		sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);		/* set Status-FIFO watermark */		sky2_write8(hw, STAT_FIFO_WM, 0x10);		/* set Status-FIFO ISR watermark */		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)			sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);		else	 /* WA 4109 */			sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);		sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);	}	/* enable the prefetch unit */	/* operational bit not functional for Yukon-EC, but fixed in Yukon-2? */	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/793b883ed12a6ae6e2901ddb5e038b77d6f0c0ac/sky2.c/buggy/drivers/net/sky2.c