#ifdef CONFIG_MIPS_MALTA 
/* Don't handle target retries indefinitely.  */ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == MSC01_PCI_CFG_MAXRTRY_MSK) data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << MSC01_PCI_CFG_MAXRTRY_SHF)) | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << MSC01_PCI_CFG_MAXRTRY_SHF);  wmb(); MSC_WRITE(MSC01_PCI_CFG, data); mb();  
void __init prom_init(void){	prom_argc = fw_arg0;	_prom_argv = (int *) fw_arg1;	_prom_envp = (int *) fw_arg2;	mips_display_message("LINUX");#ifdef CONFIG_MIPS_SEAD	set_io_port_base(KSEG1);#else	/*	 * early setup of _pcictrl_bonito so that we can determine	 * the system controller on a CORE_EMUL board	 */	_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);	mips_revision_corid = MIPS_REVISION_CORID;	if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {		if (BONITO_PCIDID == 0x0001df53 ||		    BONITO_PCIDID == 0x0003df53)			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;		else			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;	}	switch(mips_revision_corid) {	case MIPS_REVISION_CORID_QED_RM5261:	case MIPS_REVISION_CORID_CORE_LV:	case MIPS_REVISION_CORID_CORE_FPGA:	case MIPS_REVISION_CORID_CORE_FPGAR2:		/*		 * Setup the North bridge to do Master byte-lane swapping		 * when running in bigendian.		 */		_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);#ifdef CONFIG_CPU_LITTLE_ENDIAN		GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |			 GT_PCI0_CMD_SBYTESWAP_BIT);#else		GT_WRITE(GT_PCI0_CMD_OFS, 0);#endif#ifdef CONFIG_MIPS_MALTA		set_io_port_base(MALTA_GT_PORT_BASE);#else		set_io_port_base((unsigned long)ioremap(0, 0x20000000));#endif		break;	case MIPS_REVISION_CORID_CORE_EMUL_BON:	case MIPS_REVISION_CORID_BONITO64:	case MIPS_REVISION_CORID_CORE_20K:		_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);		/*		 * Disable Bonito IOBC.		 */		BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &			~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |			  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);		/*		 * Setup the North bridge to do Master byte-lane swapping		 * when running in bigendian.		 */#ifdef CONFIG_CPU_LITTLE_ENDIAN		BONITO_BONGENCFG = BONITO_BONGENCFG &			~(BONITO_BONGENCFG_MSTRBYTESWAP |			  BONITO_BONGENCFG_BYTESWAP);#else		BONITO_BONGENCFG = BONITO_BONGENCFG |			BONITO_BONGENCFG_MSTRBYTESWAP |			BONITO_BONGENCFG_BYTESWAP;#endif#ifdef CONFIG_MIPS_MALTA		set_io_port_base(MALTA_BONITO_PORT_BASE);#else		set_io_port_base((unsigned long)ioremap(0, 0x20000000));#endif		break;	case MIPS_REVISION_CORID_CORE_MSC:	case MIPS_REVISION_CORID_CORE_FPGA2:	case MIPS_REVISION_CORID_CORE_EMUL_MSC:		_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);#ifdef CONFIG_CPU_LITTLE_ENDIAN		MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);#else		MSC_WRITE(MSC01_PCI_SWAP,			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);#endif#ifdef CONFIG_MIPS_MALTA		set_io_port_base(MALTA_MSC_PORT_BASE);#else		set_io_port_base((unsigned long)ioremap(0, 0x20000000));#endif		break;	default:		/* Unknown Core card */		mips_display_message("CC Error");		while(1);   /* We die here... */	}#endif	prom_printf("\nLINUX started...\n");	prom_init_cmdline();	prom_meminit();#ifdef CONFIG_SERIAL_8250_CONSOLE	console_config();#endif}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/aa0980b8090878bf42bc73a13d051a203a201d7d/init.c/clean/arch/mips/mips-boards/generic/init.c