pci_read_config_dword (to_pci_dev(hcd->self.controller), 
pci_read_config_dword(to_pci_dev(hcd->self.controller), 
static int ehci_pci_reset (struct usb_hcd *hcd){	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);	u32			temp;	unsigned		count = 256/4;	spin_lock_init (&ehci->lock);	ehci->caps = hcd->regs;	ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));	dbg_hcs_params (ehci, "reset");	dbg_hcc_params (ehci, "reset");	/* cache this readonly data; minimize chip reads */	ehci->hcs_params = readl (&ehci->caps->hcs_params);	if (hcd->self.controller->bus == &pci_bus_type) {		struct pci_dev	*pdev = to_pci_dev(hcd->self.controller);		switch (pdev->vendor) {		case PCI_VENDOR_ID_TDI:			if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {				ehci->is_tdi_rh_tt = 1;				tdi_reset (ehci);			}			break;		case PCI_VENDOR_ID_AMD:			/* AMD8111 EHCI doesn't work, according to AMD errata */			if (pdev->device == 0x7463) {				ehci_info (ehci, "ignoring AMD8111 (errata)\n");				return -EIO;			}			break;		case PCI_VENDOR_ID_NVIDIA:			/* NVidia reports that certain chips don't handle			 * QH, ITD, or SITD addresses above 2GB.  (But TD,			 * data buffer, and periodic schedule are normal.)			 */			switch (pdev->device) {			case 0x003c:	/* MCP04 */			case 0x005b:	/* CK804 */			case 0x00d8:	/* CK8 */			case 0x00e8:	/* CK8S */				if (pci_set_consistent_dma_mask(pdev,							DMA_31BIT_MASK) < 0)					ehci_warn (ehci, "can't enable NVidia "						"workaround for >2GB RAM\n");				break;			}			break;		}		/* optional debug port, normally in the first BAR */		temp = pci_find_capability (pdev, 0x0a);		if (temp) {			pci_read_config_dword(pdev, temp, &temp);			temp >>= 16;			if ((temp & (3 << 13)) == (1 << 13)) {				temp &= 0x1fff;				ehci->debug = hcd->regs + temp;				temp = readl (&ehci->debug->control);				ehci_info (ehci, "debug port %d%s\n",					HCS_DEBUG_PORT(ehci->hcs_params),					(temp & DBGP_ENABLED)						? " IN USE"						: "");				if (!(temp & DBGP_ENABLED))					ehci->debug = NULL;			}		}		temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));	} else		temp = 0;	/* EHCI 0.96 and later may have "extended capabilities" */	while (temp && count--) {		u32		cap;		pci_read_config_dword (to_pci_dev(hcd->self.controller),				temp, &cap);		ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);		switch (cap & 0xff) {		case 1:			/* BIOS/SMM/... handoff */			if (bios_handoff (ehci, temp, cap) != 0)				return -EOPNOTSUPP;			break;		case 0:			/* illegal reserved capability */			ehci_warn (ehci, "illegal capability!\n");			cap = 0;			/* FALLTHROUGH */		default:		/* unknown */			break;		}		temp = (cap >> 8) & 0xff;	}	if (!count) {		ehci_err (ehci, "bogus capabilities ... PCI problems!\n");		return -EIO;	}	if (ehci_is_TDI(ehci))		ehci_reset (ehci);	ehci_port_power (ehci, 0);	/* at least the Genesys GL880S needs fixup here */	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);	temp &= 0x0f;	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {		ehci_dbg (ehci, "bogus port configuration: "			"cc=%d x pcc=%d < ports=%d\n",			HCS_N_CC(ehci->hcs_params),			HCS_N_PCC(ehci->hcs_params),			HCS_N_PORTS(ehci->hcs_params));		if (hcd->self.controller->bus == &pci_bus_type) {			struct pci_dev	*pdev;			pdev = to_pci_dev(hcd->self.controller);			switch (pdev->vendor) {			case 0x17a0:		/* GENESYS */				/* GL880S: should be PORTS=2 */				temp |= (ehci->hcs_params & ~0xf);				ehci->hcs_params = temp;				break;			case PCI_VENDOR_ID_NVIDIA:				/* NF4: should be PCC=10 */				break;			}		}	}	/* force HC to halt state */	return ehci_halt (ehci);}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/abcc94480634f6fe9fc29b821261e8162c87ddd2/ehci-pci.c/buggy/drivers/usb/host/ehci-pci.c