{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6) }, 
static int __devinit tg3_get_invariants(struct tg3 *tp){	static struct pci_device_id write_reorder_chipsets[] = {		{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,		             PCI_DEVICE_ID_INTEL_82801AA_8) },		{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,		             PCI_DEVICE_ID_INTEL_82801AB_8) },		{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,		             PCI_DEVICE_ID_INTEL_82801BA_11) },		{ PCI_DEVICE(PCI_VENDOR_ID_INTEL,		             PCI_DEVICE_ID_INTEL_82801BA_6) },		{ PCI_DEVICE(PCI_VENDOR_ID_AMD,		             PCI_DEVICE_ID_AMD_FE_GATE_700C) },		{ },	};	u32 misc_ctrl_reg;	u32 cacheline_sz_reg;	u32 pci_state_reg, grc_misc_cfg;	u32 val;	u16 pci_cmd;	int err;#ifdef CONFIG_SPARC64	if (tg3_is_sun_570X(tp))		tp->tg3_flags2 |= TG3_FLG2_SUN_570X;#endif	/* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write	 * reordering to the mailbox registers done by the host	 * controller can cause major troubles.  We read back from	 * every mailbox register write to force the writes to be	 * posted to the chip in order.	 */	if (pci_dev_present(write_reorder_chipsets))		tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;	/* Force memory write invalidate off.  If we leave it on,	 * then on 5700_BX chips we have to enable a workaround.	 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary	 * to match the cacheline size.  The Broadcom driver have this	 * workaround but turns MWI off all the times so never uses	 * it.  This seems to suggest that the workaround is insufficient.	 */	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);	pci_cmd &= ~PCI_COMMAND_INVALIDATE;	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);	/* It is absolutely critical that TG3PCI_MISC_HOST_CTRL	 * has the register indirect write enable bit set before	 * we try to access any of the MMIO registers.  It is also	 * critical that the PCI-X hw workaround situation is decided	 * before that as well.	 */	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,			      &misc_ctrl_reg);	tp->pci_chip_rev_id = (misc_ctrl_reg >>			       MISC_HOST_CTRL_CHIPREV_SHIFT);	/* Wrong chip ID in 5752 A0. This code can be removed later	 * as A0 is not in production.	 */	if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;	/* Find msi capability. */	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)		tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);	/* Initialize misc host control in PCI block. */	tp->misc_host_ctrl |= (misc_ctrl_reg &			       MISC_HOST_CTRL_CHIPREV);	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,			       tp->misc_host_ctrl);	pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,			      &cacheline_sz_reg);	tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;	tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;	tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||	    (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)		tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&	    tp->pci_lat_timer < 64) {		tp->pci_lat_timer = 64;		cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);		cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);		cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);		cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);		pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,				       cacheline_sz_reg);	}	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,			      &pci_state_reg);	if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {		tp->tg3_flags |= TG3_FLAG_PCIX_MODE;		/* If this is a 5700 BX chipset, and we are in PCI-X		 * mode, enable register write workaround.		 *		 * The workaround is to use indirect register accesses		 * for all chip writes not to mailbox registers.		 */		if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {			u32 pm_reg;			u16 pci_cmd;			tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;			/* The chip can have it's power management PCI config			 * space registers clobbered due to this bug.			 * So explicitly force the chip into D0 here.			 */			pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,					      &pm_reg);			pm_reg &= ~PCI_PM_CTRL_STATE_MASK;			pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;			pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,					       pm_reg);			/* Also, force SERR#/PERR# in PCI command. */			pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);			pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);		}	}	/* Back to back register writes can cause problems on this chip,	 * the workaround is to read back all reg writes except those to	 * mailbox regs.  See tg3_write_indirect_reg32().	 *	 * PCI Express 5750_A0 rev chips need this workaround too.	 */	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||	    ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&	     tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))		tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;	if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)		tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;	if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)		tp->tg3_flags |= TG3_FLAG_PCI_32BIT;	/* Chip-specific fixup from Broadcom driver */	if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&	    (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {		pci_state_reg |= PCISTATE_RETRY_SAME_DMA;		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);	}	/* Default fast path register access methods */	tp->read32 = tg3_read32;	tp->write32 = tg3_write32;	tp->read32_mbox = tg3_read32;	tp->write32_mbox = tg3_write32;	tp->write32_tx_mbox = tg3_write32;	tp->write32_rx_mbox = tg3_write32;	/* Various workaround register access methods */	if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)		tp->write32 = tg3_write_indirect_reg32;	else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)		tp->write32 = tg3_write_flush_reg32;	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {		tp->write32_tx_mbox = tg3_write32_tx_mbox;		if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)			tp->write32_rx_mbox = tg3_write_flush_reg32;	}	/* Get eeprom hw config before calling tg3_set_power_state().	 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be	 * determined before calling tg3_set_power_state() so that	 * we know whether or not to switch out of Vaux power.	 * When the flag is set, it means that GPIO1 is used for eeprom	 * write protect and also implies that it is a LOM where GPIOs	 * are not used to switch power.	 */ 	tg3_get_eeprom_hw_cfg(tp);	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().	 * GPIO1 driven high will bring 5700's external PHY out of reset.	 * It is also used as eeprom write protect on LOMs.	 */	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||	    (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |				       GRC_LCLCTRL_GPIO_OUTPUT1);	/* Unused GPIO3 must be driven as output on 5752 because there	 * are no pull-up resistors on unused GPIO pins.	 */	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;	/* Force the chip into D0. */	err = tg3_set_power_state(tp, 0);	if (err) {		printk(KERN_ERR PFX "(%s) transition to D0 failed\n",		       pci_name(tp->pdev));		return err;	}	/* 5700 B0 chips do not support checksumming correctly due	 * to hardware bugs.	 */	if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)		tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;	/* Pseudo-header checksum is done by hardware logic and not	 * the offload processers, so make the chip do the pseudo-	 * header checksums on receive.  For transmit it is more	 * convenient to do the pseudo-header checksum in software	 * as Linux does that on transmit for us in all cases.	 */	tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;	tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;	/* Derive initial jumbo mode from MTU assigned in	 * ether_setup() via the alloc_etherdev() call	 */	if (tp->dev->mtu > ETH_DATA_LEN &&	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)		tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;	/* Determine WakeOnLan speed to use. */	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||	    tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||	    tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {		tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);	} else {		tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;	}	/* A few boards don't want Ethernet@WireSpeed phy feature */	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||	    ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&	     (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||	    (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))		tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||	    GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)		tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;	tp->coalesce_mode = 0;	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&	    GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)		tp->coalesce_mode |= HOSTCC_MODE_32BYTE;	/* Initialize MAC MI mode, polling disabled. */	tw32_f(MAC_MI_MODE, tp->mi_mode);	udelay(80);	/* Initialize data/descriptor byte/word swapping. */	val = tr32(GRC_MODE);	val &= GRC_MODE_HOST_STACKUP;	tw32(GRC_MODE, val | tp->grc_mode);	tg3_switch_clocks(tp);	/* Clear this out for sanity. */	tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,			      &pci_state_reg);	if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&	    (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {		u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);		if (chiprevid == CHIPREV_ID_5701_A0 ||		    chiprevid == CHIPREV_ID_5701_B0 ||		    chiprevid == CHIPREV_ID_5701_B2 ||		    chiprevid == CHIPREV_ID_5701_B5) {			void __iomem *sram_base;			/* Write some dummy words into the SRAM status block			 * area, see if it reads back correctly.  If the return			 * value is bad, force enable the PCIX workaround.			 */			sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;			writel(0x00000000, sram_base);			writel(0x00000000, sram_base + 4);			writel(0xffffffff, sram_base + 4);			if (readl(sram_base) != 0x00000000)				tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;		}	}	udelay(50);	tg3_nvram_init(tp);	grc_misc_cfg = tr32(GRC_MISC_CFG);	grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;	/* Broadcom's driver says that CIOBE multisplit has a bug */#if 0	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&	    grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {		tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;		tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;	}#endif	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&	    (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||	     grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))		tp->tg3_flags2 |= TG3_FLG2_IS_5788;	if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))		tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;	if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {		tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |				      HOSTCC_MODE_CLRTICK_TXBD);		tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;		pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,				       tp->misc_host_ctrl);	}	/* these are limited to 10/100 only */	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&	     (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&	     tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||	    (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&	     (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||	      tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))		tp->tg3_flags |= TG3_FLAG_10_100_ONLY;	err = tg3_phy_probe(tp);	if (err) {		printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",		       pci_name(tp->pdev), err);		/* ... but do not return immediately ... */	}	tg3_read_partno(tp);	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {		tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;	} else {		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)			tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;		else			tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;	}	/* 5700 {AX,BX} chips have a broken status block link	 * change bit implementation, so we must use the	 * status register in those cases.	 */	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)		tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;	else		tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;	/* The led_ctrl is set during tg3_phy_probe, here we might	 * have to force the link status polling mechanism based	 * upon subsystem IDs.	 */	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&	    !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {		tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |				  TG3_FLAG_USE_LINKCHG_REG);	}	/* For all SERDES we poll the MAC status register. */	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)		tp->tg3_flags |= TG3_FLAG_POLL_SERDES;	else		tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;	/* 5700 BX chips need to have their TX producer index mailboxes	 * written twice to workaround a bug.	 */	if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)		tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;	else		tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;	/* It seems all chips can get confused if TX buffers	 * straddle the 4GB address boundary in some cases.	 */	tp->dev->hard_start_xmit = tg3_start_xmit;	tp->rx_offset = 2;	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&	    (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)		tp->rx_offset = 0;	/* By default, disable wake-on-lan.  User can change this	 * using ETHTOOL_SWOL.	 */	tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;	return err;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/6892914fb7980d844f2bac859f4095df9ebd18da/tg3.c/buggy/drivers/net/tg3.c