INB(np, nc_mbox1); 
void sym_start_up (struct sym_hcb *np, int reason){ 	int	i;	u32	phys; 	/*	 *  Reset chip if asked, otherwise just clear fifos. 	 */	if (reason == 1)		sym_soft_reset(np);	else {		OUTB(np, nc_stest3, TE|CSF);		OUTONB(np, nc_ctest3, CLF);	} 	/*	 *  Clear Start Queue	 */	phys = np->squeue_ba;	for (i = 0; i < MAX_QUEUE*2; i += 2) {		np->squeue[i]   = cpu_to_scr(np->idletask_ba);		np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);	}	np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);	/*	 *  Start at first entry.	 */	np->squeueput = 0;	/*	 *  Clear Done Queue	 */	phys = np->dqueue_ba;	for (i = 0; i < MAX_QUEUE*2; i += 2) {		np->dqueue[i]   = 0;		np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);	}	np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);	/*	 *  Start at first entry.	 */	np->dqueueget = 0;	/*	 *  Install patches in scripts.	 *  This also let point to first position the start 	 *  and done queue pointers used from SCRIPTS.	 */	np->fw_patch(np);	/*	 *  Wakeup all pending jobs.	 */	sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);	/*	 *  Init chip.	 */	OUTB(np, nc_istat,  0x00);			/*  Remove Reset, abort */	udelay(2000); /* The 895 needs time for the bus mode to settle */	OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0);					/*  full arb., ena parity, par->ATN  */	OUTB(np, nc_scntl1, 0x00);		/*  odd parity, and remove CRST!! */	sym_selectclock(np, np->rv_scntl3);	/* Select SCSI clock */	OUTB(np, nc_scid  , RRE|np->myaddr);	/* Adapter SCSI address */	OUTW(np, nc_respid, 1ul<<np->myaddr);	/* Id to respond to */	OUTB(np, nc_istat , SIGP	);		/*  Signal Process */	OUTB(np, nc_dmode , np->rv_dmode);		/* Burst length, dma mode */	OUTB(np, nc_ctest5, np->rv_ctest5);	/* Large fifo + large burst */	OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl);	/* Protect SFBR */	OUTB(np, nc_ctest3, np->rv_ctest3);	/* Write and invalidate */	OUTB(np, nc_ctest4, np->rv_ctest4);	/* Master parity checking */	/* Extended Sreq/Sack filtering not supported on the C10 */	if (np->features & FE_C10)		OUTB(np, nc_stest2, np->rv_stest2);	else		OUTB(np, nc_stest2, EXT|np->rv_stest2);	OUTB(np, nc_stest3, TE);			/* TolerANT enable */	OUTB(np, nc_stime0, 0x0c);			/* HTH disabled  STO 0.25 sec */	/*	 *  For now, disable AIP generation on C1010-66.	 */	if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_66)		OUTB(np, nc_aipcntl1, DISAIP);	/*	 *  C10101 rev. 0 errata.	 *  Errant SGE's when in narrow. Write bits 4 & 5 of	 *  STEST1 register to disable SGE. We probably should do 	 *  that from SCRIPTS for each selection/reselection, but 	 *  I just don't want. :)	 */	if (np->device_id == PCI_DEVICE_ID_LSI_53C1010_33 &&	    np->revision_id < 1)		OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30);	/*	 *  DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.	 *  Disable overlapped arbitration for some dual function devices, 	 *  regardless revision id (kind of post-chip-design feature. ;-))	 */	if (np->device_id == PCI_DEVICE_ID_NCR_53C875)		OUTB(np, nc_ctest0, (1<<5));	else if (np->device_id == PCI_DEVICE_ID_NCR_53C896)		np->rv_ccntl0 |= DPR;	/*	 *  Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 	 *  and/or hardware phase mismatch, since only such chips 	 *  seem to support those IO registers.	 */	if (np->features & (FE_DAC|FE_NOPM)) {		OUTB(np, nc_ccntl0, np->rv_ccntl0);		OUTB(np, nc_ccntl1, np->rv_ccntl1);	}#if	SYM_CONF_DMA_ADDRESSING_MODE == 2	/*	 *  Set up scratch C and DRS IO registers to map the 32 bit 	 *  DMA address range our data structures are located in.	 */	if (np->use_dac) {		np->dmap_bah[0] = 0;	/* ??? */		OUTL(np, nc_scrx[0], np->dmap_bah[0]);		OUTL(np, nc_drs, np->dmap_bah[0]);	}#endif	/*	 *  If phase mismatch handled by scripts (895A/896/1010),	 *  set PM jump addresses.	 */	if (np->features & FE_NOPM) {		OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle));		OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle));	}	/*	 *    Enable GPIO0 pin for writing if LED support from SCRIPTS.	 *    Also set GPIO5 and clear GPIO6 if hardware LED control.	 */	if (np->features & FE_LED0)		OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01);	else if (np->features & FE_LEDC)		OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20);	/*	 *      enable ints	 */	OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);	OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID);	/*	 *  For 895/6 enable SBMC interrupt and save current SCSI bus mode.	 *  Try to eat the spurious SBMC interrupt that may occur when 	 *  we reset the chip but not the SCSI BUS (at initialization).	 */	if (np->features & (FE_ULTRA2|FE_ULTRA3)) {		OUTONW(np, nc_sien, SBMC);		if (reason == 0) {			mdelay(100);			INW(np, nc_sist);		}		np->scsi_mode = INB(np, nc_stest4) & SMODE;	}	/*	 *  Fill in target structure.	 *  Reinitialize usrsync.	 *  Reinitialize usrwide.	 *  Prepare sync negotiation according to actual SCSI bus mode.	 */	for (i=0;i<SYM_CONF_MAX_TARGET;i++) {		struct sym_tcb *tp = &np->target[i];		tp->to_reset  = 0;		tp->head.sval = 0;		tp->head.wval = np->rv_scntl3;		tp->head.uval = 0;	}	/*	 *  Download SCSI SCRIPTS to on-chip RAM if present,	 *  and start script processor.	 *  We do the download preferently from the CPU.	 *  For platforms that may not support PCI memory mapping,	 *  we use simple SCRIPTS that performs MEMORY MOVEs.	 */	phys = SCRIPTA_BA(np, init);	if (np->ram_ba) {		if (sym_verbose >= 2)			printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np));		memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz);		if (np->ram_ws == 8192) {			memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz);			phys = scr_to_cpu(np->scr_ram_seg);			OUTL(np, nc_mmws, phys);			OUTL(np, nc_mmrs, phys);			OUTL(np, nc_sfs,  phys);			phys = SCRIPTB_BA(np, start64);		}	}	np->istat_sem = 0;	OUTL(np, nc_dsa, np->hcb_ba);	OUTL_DSP(np, phys);	/*	 *  Notify the XPT about the RESET condition.	 */	if (reason != 0)		sym_xpt_async_bus_reset(np);}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/53222b906903fd861dc24ebccfa07ee125941313/sym_hipd.c/buggy/drivers/scsi/sym53c8xx_2/sym_hipd.c