SBMAC_WRITECSR(s->sbm_rxfilter,0); SBMAC_WRITECSR(s->sbm_imr,0); SBMAC_WRITECSR(s->sbm_framecfg,framecfg); SBMAC_WRITECSR(s->sbm_fifocfg,fifo); SBMAC_WRITECSR(s->sbm_maccfg,cfg); 
__raw_writeq(0, s->sbm_rxfilter); __raw_writeq(0, s->sbm_imr); __raw_writeq(framecfg, s->sbm_framecfg); __raw_writeq(fifo, s->sbm_fifocfg); __raw_writeq(cfg, s->sbm_maccfg); 
static void sbmac_channel_start(struct sbmac_softc *s){	uint64_t reg;	sbmac_port_t port;	uint64_t cfg,fifo,framecfg;	int idx, th_value;		/*	 * Don't do this if running	 */	if (s->sbm_state == sbmac_state_on)		return;		/*	 * Bring the controller out of reset, but leave it off.	 */		SBMAC_WRITECSR(s->sbm_macenable,0);		/*	 * Ignore all received packets	 */		SBMAC_WRITECSR(s->sbm_rxfilter,0);		/* 	 * Calculate values for various control registers.	 */		cfg = M_MAC_RETRY_EN |		M_MAC_TX_HOLD_SOP_EN | 		V_MAC_TX_PAUSE_CNT_16K |		M_MAC_AP_STAT_EN |		M_MAC_FAST_SYNC |		M_MAC_SS_EN |		0;		/* 	 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars	 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above	 * Use a larger RD_THRSH for gigabit	 */	if (periph_rev >= 2) 		th_value = 64;	else 		th_value = 28;	fifo = V_MAC_TX_WR_THRSH(4) |	/* Must be '4' or '8' */		((s->sbm_speed == sbmac_speed_1000)		 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |		V_MAC_TX_RL_THRSH(4) |		V_MAC_RX_PL_THRSH(4) |		V_MAC_RX_RD_THRSH(4) |	/* Must be '4' */		V_MAC_RX_PL_THRSH(4) |		V_MAC_RX_RL_THRSH(8) |		0;	framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |		V_MAC_MAX_FRAMESZ_DEFAULT |		V_MAC_BACKOFF_SEL(1);	/*	 * Clear out the hash address map 	 */		port = s->sbm_base + R_MAC_HASH_BASE;	for (idx = 0; idx < MAC_HASH_COUNT; idx++) {		SBMAC_WRITECSR(port,0);		port += sizeof(uint64_t);	}		/*	 * Clear out the exact-match table	 */		port = s->sbm_base + R_MAC_ADDR_BASE;	for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {		SBMAC_WRITECSR(port,0);		port += sizeof(uint64_t);	}		/*	 * Clear out the DMA Channel mapping table registers	 */		port = s->sbm_base + R_MAC_CHUP0_BASE;	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {		SBMAC_WRITECSR(port,0);		port += sizeof(uint64_t);	}	port = s->sbm_base + R_MAC_CHLO0_BASE;	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {		SBMAC_WRITECSR(port,0);		port += sizeof(uint64_t);	}		/*	 * Program the hardware address.  It goes into the hardware-address	 * register as well as the first filter register.	 */		reg = sbmac_addr2reg(s->sbm_hwaddr);		port = s->sbm_base + R_MAC_ADDR_BASE;	SBMAC_WRITECSR(port,reg);	port = s->sbm_base + R_MAC_ETHERNET_ADDR;#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS	/*	 * Pass1 SOCs do not receive packets addressed to the	 * destination address in the R_MAC_ETHERNET_ADDR register.	 * Set the value to zero.	 */	SBMAC_WRITECSR(port,0);#else	SBMAC_WRITECSR(port,reg);#endif		/*	 * Set the receive filter for no packets, and write values	 * to the various config registers	 */		SBMAC_WRITECSR(s->sbm_rxfilter,0);	SBMAC_WRITECSR(s->sbm_imr,0);	SBMAC_WRITECSR(s->sbm_framecfg,framecfg);	SBMAC_WRITECSR(s->sbm_fifocfg,fifo);	SBMAC_WRITECSR(s->sbm_maccfg,cfg);		/*	 * Initialize DMA channels (rings should be ok now)	 */		sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);	sbdma_channel_start(&(s->sbm_txdma), DMA_TX);		/*	 * Configure the speed, duplex, and flow control	 */	sbmac_set_speed(s,s->sbm_speed);	sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);		/*	 * Fill the receive ring	 */		sbdma_fillring(&(s->sbm_rxdma));		/* 	 * Turn on the rest of the bits in the enable register	 */      		SBMAC_WRITECSR(s->sbm_macenable,		       M_MAC_RXDMA_EN0 |		       M_MAC_TXDMA_EN0 |		       M_MAC_RX_ENABLE |		       M_MAC_TX_ENABLE);		#ifdef CONFIG_SBMAC_COALESCE	/*	 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0	 */	SBMAC_WRITECSR(s->sbm_imr,		       ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |		       ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));#else	/*	 * Accept any kind of interrupt on TX and RX DMA channel 0	 */	SBMAC_WRITECSR(s->sbm_imr,		       (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |		       (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));#endif		/* 	 * Enable receiving unicasts and broadcasts 	 */		SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);		/*	 * we're running now. 	 */		s->sbm_state = sbmac_state_on;		/* 	 * Program multicast addresses 	 */		sbmac_setmulti(s);		/* 	 * If channel was in promiscuous mode before, turn that on 	 */		if (s->sbm_devflags & IFF_PROMISC) {		sbmac_promiscuous_mode(s,1);	}	}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/2039973af59889fea0d14362eae56792cfe8d25a/sb1250-mac.c/buggy/drivers/net/sb1250-mac.c