printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n", 
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", 
int __init clk_init(void){	struct clk **  clkp;	const struct omap_clock_config *info;	int crystal_type = 0; /* Default 12 MHz */	omap_early_clk_reset();	for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {		if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {			clk_register(*clkp);			continue;		}		if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {			clk_register(*clkp);			continue;		}		if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {			clk_register(*clkp);			continue;		}	}	info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);	if (info != NULL) {		if (!cpu_is_omap1510())			crystal_type = info->system_clock_type;	}#if defined(CONFIG_ARCH_OMAP730)	ck_ref.rate = 13000000;#elif defined(CONFIG_ARCH_OMAP16XX)	if (crystal_type == 2)		ck_ref.rate = 19200000;#endif	printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",	       omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),	       omap_readw(ARM_CKCTL));	/* We want to be in syncronous scalable mode */	omap_writew(0x1000, ARM_SYSST);#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER	/* Use values set by bootloader. Determine PLL rate and recalculate	 * dependent clocks as if kernel had changed PLL or divisors.	 */	{		unsigned pll_ctl_val = omap_readw(DPLL_CTL);		ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */		if (pll_ctl_val & 0x10) {			/* PLL enabled, apply multiplier and divisor */			if (pll_ctl_val & 0xf80)				ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;			ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;		} else {			/* PLL disabled, apply bypass divisor */			switch (pll_ctl_val & 0xc) {			case 0:				break;			case 0x4:				ck_dpll1.rate /= 2;				break;			default:				ck_dpll1.rate /= 4;				break;			}		}	}	propagate_rate(&ck_dpll1);#else	/* Find the highest supported frequency and enable it */	if (select_table_rate(&virtual_ck_mpu, ~0)) {		printk(KERN_ERR "System frequencies not set. Check your config.\n");		/* Guess sane values (60MHz) */		omap_writew(0x2290, DPLL_CTL);		omap_writew(0x1005, ARM_CKCTL);		ck_dpll1.rate = 60000000;		propagate_rate(&ck_dpll1);	}#endif	/* Cache rates for clocks connected to ck_ref (not dpll1) */	propagate_rate(&ck_ref);	printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n",	       ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,	       ck_dpll1.rate, arm_ck.rate);#ifdef CONFIG_MACH_OMAP_PERSEUS2	/* Select slicer output as OMAP input clock */	omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);#endif	/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */	omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);	/* Put DSP/MPUI into reset until needed */	omap_writew(0, ARM_RSTCT1);	omap_writew(1, ARM_RSTCT2);	omap_writew(0x400, ARM_IDLECT1);	/*	 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)	 * of the ARM_IDLECT2 register must be set to zero. The power-on	 * default value of this bit is one.	 */	omap_writew(0x0000, ARM_IDLECT2);	/* Turn LCD clock off also */	/*	 * Only enable those clocks we will need, let the drivers	 * enable other clocks as necessary	 */	clk_use(&armper_ck);	clk_use(&armxor_ck);	clk_use(&armtim_ck);	if (cpu_is_omap1510())		clk_enable(&arm_gpio_ck);	return 0;}
4520	/local/tlutelli/issta_data/temp/c/2005_temp/2005/4520/92105bb70634abacc08bbe12bf6f888fbd7dad38/clock.c/buggy/arch/arm/plat-omap/clock.c