static void __init smp_store_cpu_info(int id) 
static void __devinit smp_store_cpu_info(int id) 
static void __init smp_store_cpu_info(int id){	struct cpuinfo_x86 *c = cpu_data + id;	*c = boot_cpu_data;	if (id!=0)		identify_cpu(c);	/*	 * Mask B, Pentium, but not Pentium MMX	 */	if (c->x86_vendor == X86_VENDOR_INTEL &&	    c->x86 == 5 &&	    c->x86_mask >= 1 && c->x86_mask <= 4 &&	    c->x86_model <= 3)		/*		 * Remember we have B step Pentia with bugs		 */		smp_b_stepping = 1;	/*	 * Certain Athlons might work (for various values of 'work') in SMP	 * but they are not certified as MP capable.	 */	if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {		/* Athlon 660/661 is valid. */			if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))			goto valid_k7;		/* Duron 670 is valid */		if ((c->x86_model==7) && (c->x86_mask==0))			goto valid_k7;		/*		 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.		 * It's worth noting that the A5 stepping (662) of some Athlon XP's		 * have the MP bit set.		 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.		 */		if (((c->x86_model==6) && (c->x86_mask>=2)) ||		    ((c->x86_model==7) && (c->x86_mask>=1)) ||		     (c->x86_model> 7))			if (cpu_has_mp)				goto valid_k7;		/* If we get here, it's not a certified SMP capable AMD system. */		tainted |= TAINT_UNSAFE_SMP;	}valid_k7:	;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/0bb3184df537002a742bafddf3f4fb482b7fe610/smpboot.c/clean/arch/i386/kernel/smpboot.c