 /* Clear PHY COMA */ skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg); reg &= ~PCI_PHY_COMA; pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);  
static int skge_reset(struct skge_hw *hw){	u16 ctst;	u8 t8, mac_cfg, pmd_type, phy_type;	int i;	ctst = skge_read16(hw, B0_CTST);	/* do a SW reset */	skge_write8(hw, B0_CTST, CS_RST_SET);	skge_write8(hw, B0_CTST, CS_RST_CLR);	/* clear PCI errors, if any */	skge_pci_clear(hw);	skge_write8(hw, B0_CTST, CS_MRST_CLR);	/* restore CLK_RUN bits (for Yukon-Lite) */	skge_write16(hw, B0_CTST,		     ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));	hw->chip_id = skge_read8(hw, B2_CHIP_ID);	phy_type = skge_read8(hw, B2_E_1) & 0xf;	pmd_type = skge_read8(hw, B2_PMD_TYP);	hw->copper = (pmd_type == 'T' || pmd_type == '1');	switch (hw->chip_id) {	case CHIP_ID_GENESIS:		switch (phy_type) {		case SK_PHY_BCOM:			hw->phy_addr = PHY_ADDR_BCOM;			break;		default:			printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",			       pci_name(hw->pdev), phy_type);			return -EOPNOTSUPP;		}		break;	case CHIP_ID_YUKON:	case CHIP_ID_YUKON_LITE:	case CHIP_ID_YUKON_LP:		if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')			hw->copper = 1;		hw->phy_addr = PHY_ADDR_MARV;		break;	default:		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",		       pci_name(hw->pdev), hw->chip_id);		return -EOPNOTSUPP;	}	mac_cfg = skge_read8(hw, B2_MAC_CFG);	hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;	hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;	/* read the adapters RAM size */	t8 = skge_read8(hw, B2_E_0);	if (hw->chip_id == CHIP_ID_GENESIS) {		if (t8 == 3) {			/* special case: 4 x 64k x 36, offset = 0x80000 */			hw->ram_size = 0x100000;			hw->ram_offset = 0x80000;		} else			hw->ram_size = t8 * 512;	}	else if (t8 == 0)		hw->ram_size = 0x20000;	else		hw->ram_size = t8 * 4096;	hw->intr_mask = IS_HW_ERR | IS_EXT_REG;	if (hw->chip_id == CHIP_ID_GENESIS)		genesis_init(hw);	else {		/* switch power to VCC (WA for VAUX problem) */		skge_write8(hw, B0_POWER_CTRL,			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);		/* avoid boards with stuck Hardware error bits */		if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&		    (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {			printk(KERN_WARNING PFX "stuck hardware sensor bit\n");			hw->intr_mask &= ~IS_HW_ERR;		}		for (i = 0; i < hw->ports; i++) {			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);		}	}	/* turn off hardware timer (unused) */	skge_write8(hw, B2_TI_CTRL, TIM_STOP);	skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);	skge_write8(hw, B0_LED, LED_STAT_ON);	/* enable the Tx Arbiters */	for (i = 0; i < hw->ports; i++)		skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);	/* Initialize ram interface */	skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);	skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);	skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);	skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);	skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);	skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);	skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);	skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);	skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);	/* Set interrupt moderation for Transmit only	 * Receive interrupts avoided by NAPI	 */	skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);	skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));	skge_write32(hw, B2_IRQM_CTRL, TIM_START);	skge_write32(hw, B0_IMSK, hw->intr_mask);	spin_lock_bh(&hw->phy_lock);	for (i = 0; i < hw->ports; i++) {		if (hw->chip_id == CHIP_ID_GENESIS)			genesis_reset(hw, i);		else			yukon_reset(hw, i);	}	spin_unlock_bh(&hw->phy_lock);	return 0;}
10457	/local/tlutelli/issta_data/temp/c/2005_temp/2005/10457/adba9e23b4066f1d741a2076fc6ad18b6c0cea44/skge.c/buggy/drivers/net/skge.c