Design a finite state machine (FSM) in System Verilog that can detect and count the number of 1s in a stream of binary data. The FSM should have two states: (1) a counting state, in which it counts the number of 1s, and (2) an idle state, in which it waits for the next data input. The FSM should output the count of 1s after receiving a specific end-of-stream signal.
Here's a simple Finite State Machine (FSM) design in SystemVerilog to count the number of 1s in a stream of binary data:

module fsm_counting(input [7:0] data, // Data input from stream
                   output logic [3:0] count); // Output indicating count of 1s

  // States
  state counting {
    // Count up until we reach a certain number of 1s
    if (data[6]) begin
      count 