I'm designing a board for a hobby project where I am using a lattice machxo2 cpld as a system interconnect.

The cpld needs to be clocked at 80-100MHz, and because I sprung for a cheaper cpld, it has no on board PLLs. The easiest way for me to clock it is to use a programmable clock from my main mcu (Atmel SAM4S) to clock the cpld (with a pcb trace of about 3cm).

Because the signal is 100MHz, the slew rate will have to be fairly high, and I'm expecting a lot of ringing. Can I reduce the ringing by adding a small resistor to the output pin of the MCU (10-100 Ohm) and a small cap to ground on the clock line (10-100pF)? According to my back of the envelope math, these values will force the rise/fall time to be around 1ns.

![schematic](https://i.stack.imgur.com/KSTrj.png)

[simulate this circuit](/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fKSTrj.png) – Schematic created using [CircuitLab](https://www.circuitlab.com/)

Will this approach work? Is it common practice? I'm coming from a CS background, so my knowledge is a little shaky.

Thanks.