I have a problem with VHDL ALU code. I have to make simple ALU with 4 operations with 4-bit operands. I implemented these operations correctly and they work well. For executing I use E2LP board. For choosing the operation I selected 4 JOY buttons,one for each operation. Problem is that when I press button to execute operation and depress it I want result to stay on LEDs while I don't select any other operation, but that's not happening. For first 5 LEDs this works fine, but upper 3 not.This only works for one operation. My simulation results are correct. Here is code an schema of project.Thank you in advance.

```
----------------------------------------------------------------------------------  Control logic
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

    Port ( --clk : in STD_LOGIC;
              in_saberi : in  STD_LOGIC;
           in_mnozi : in  STD_LOGIC;
           in_ili : in  STD_LOGIC;
           in_rotiraj : in  STD_LOGIC;
           out_saberi : out  STD_LOGIC;
           out_mnozi : out  STD_LOGIC;
           out_ili : out  STD_LOGIC;
           out_rotiraj : out  STD_LOGIC);
end upravljanje;

architecture Behavioral of upravljanje is
signal tmps : std_logic := '1';
signal tmpm : std_logic := '1';
signal tmpi : std_logic := '1';
signal tmpr : std_logic := '1';

begin
logika : process(in_saberi,in_mnozi,in_ili,in_rotiraj)
begin
    if (in_saberi='0' and in_mnozi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_mnozi='0' and in_saberi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='0' and in_rotiraj='1') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='1' and in_rotiraj='0') then
        tmps <= in_saberi;
        tmpm <= in_mnozi;
        tmpi <= in_ili;
        tmpr <= in_rotiraj;
    elsif (in_saberi='1' and in_mnozi='1' and in_ili='1' and in_rotiraj='1') then
        tmps <=  tmps;
        tmpm <= tmpm;
        tmpi <= tmpi;
        tmpr <= tmpr;
    else
        tmps <= '1';
        tmpm <= '1';
        tmpi <= '1';
        tmpr <= '1';
    end if;

end process logika;
    out_saberi <= tmps;
    out_mnozi <= tmpm;
    out_ili <= tmpi;
    out_rotiraj <= tmpr;

end Behavioral;

--------------------------------------------------------------------------

-- this is for operation add
entity sabirac is
    Port ( clk : in  STD_LOGIC;
              data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           saberi : in  STD_LOGIC;
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end sabirac;

architecture Behavioral of sabirac is
signal c : std_logic_vector (5 downto 0) := "000000";
signal tmp : std_logic_vector (7 downto 0) := "00000000";

begin
sabiranje : process(clk,saberi)
begin
    if (saberi='0') then
        tmp(0) <= data1(0) xor data2(0);
        c(0) <= data1(0) and data2(0);
        tmp(1) <= data1(1) xor data2(1) xor c(0);
        c(1) <= (data1(1) and data2(1)) or (data1(1) and c(0)) or (data2(1) and c(0));
        tmp(2) <= data1(2) xor data2(2) xor c(1);
        c(2) <= (data1(2) and data2(2)) or (data1(2) and c(1)) or (data2(2) and c(1));
        tmp(3) <= data1(3) xor data2(3) xor c(2);
        if(data1(3) = data2(3)) then
            c(3) <= (data1(3) and data2(3)) or (data1(3) and c(2)) or (data2(3) and c(2));
            tmp(4) <= c(3);
            tmp(5) <= c(3);
            tmp(6) <= c(3);
            tmp(7) <= c(3);
        else
           c(3) <= data1(3) xor data2(3) xor c(2);
            tmp(4) <= c(3);
            tmp(5) <= c(3);
            tmp(6) <= c(3);
            tmp(7) <= c(3);
        end if;

    else
        tmp <= "ZZZZZZZZ";
    end if;
end process sabiranje;

    result <= tmp;

end Behavioral;

-----------------------------------------------------------------------------

entity mul is
    Port (
              clk : in STD_LOGIC;
              pomnozi : in STD_LOGIC;
              data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end mul;

architecture Behavioral of mul is

begin
mnozenje : process (clk,pomnozi)
begin
    if (pomnozi='0') then
        result <= std_logic_vector(signed(data1) * signed(data2));
    else
        result <= "ZZZZZZZZ";
    end if;     
end process mnozenje;

end Behavioral;

--------------------------------------------------------------------------

entity rotate is
    Port ( clk : in  STD_LOGIC;
           rotiraj : in  STD_LOGIC;
           data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           result : out  STD_LOGIC_VECTOR (7 downto 0));
end rotate;

architecture Behavioral of rotate is
signal tmp : std_logic_vector (3 downto 0) := "0000";
signal tmp2 : std_logic_vector (7 downto 0) := "00000000";

begin
rotacija : process(clk,rotiraj)
begin
    if (rotiraj='0') then

        tmp <= std_logic_vector(rotate_left(unsigned(data1),to_integer(unsigned(data2))));
        tmp2(0) <= tmp(0);
        tmp2(1) <= tmp(1);
        tmp2(2) <= tmp(2);
        tmp2(3) <= tmp(3);
        tmp2(4) <= '0';
        tmp2(5) <= '0';
        tmp2(6) <= '0';
        tmp2(7) <= '0';
    else
        tmp2 <= "ZZZZZZZZ";
    end if;
end process rotacija;
    result <= tmp2;
end Behavioral;

--------------------------------------------------------------------------
-- Logic OR operation
entity logicko_ILI is
    Port ( clk : in  STD_LOGIC;
           data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
           logili : in  STD_LOGIC;
           result : out STD_LOGIC_VECTOR (7 downto 0));
end logicko_ILI;

architecture Behavioral of logicko_ILI is
signal c : std_logic_vector (5 downto 0) := "000000";
signal tmp : std_logic_vector (7 downto 0) := "00000000";

begin
logicko : process(clk,logili)
begin
    if (logili = '0') then
        tmp(0) <= data1(0) or data2(0);
        tmp(1) <= data1(1) or data2(1);
        tmp(2) <= data1(2) or data2(2);
        tmp(3) <= data1(3) or data2(3);
        tmp(4) <= '0';
        tmp(5) <= '1';
        tmp(6) <= '1';
        tmp(7) <= '1';
    else
        tmp <= "ZZZZZZZZ";
    end if;
end process logicko;

  result <= tmp;    

end Behavioral;

```