I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message...

```
entity test is
 port (
  paddr              : in  std_logic_vector(15 downto 0);
  psel                : in  std_logic;
  penable              : in  std_logic;
  pwrite              : in  std_logic
 );  
end entity test;

signal wrfifo_full       : std_logic; 

process (paddr, psel, penable, pwrite, wrfifo_full) is
begin
  if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then
    dt_fifo_wr_i <= '1';
  else
    dt_fifo_wr_i <= '0';
  end if;

```

end process; 

Unfortuantely, I get then the following error message:

> 
> if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and
>  (pwrite and not(wrfifo\_full))) then
>  | ncvhdl\_p: \*E,OPTYMM (hdl/vhdl/test.vhd,523|43): operator argument type mismatch
>  87[4.3.3.2] 93[4.3.2.2] [7.2]
> 
> 
> 

Anyway sees the problem?

Cheers