Design complexity continues to increase, which is contributing to new challenges in verification and debug. Fortunately, new solutions and methodologies (such as UVM) have emerged to address growing design complexity. Yet, even with the productivity gains that can be achieved with the adoption of UVM, newer debugging challenges specifically related to UVM need to be addressed.
Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.
This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.
In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.
In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.
In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.
In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.
Find bugs faster in the Visualizer™ Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, Visualizer provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.