The Integer to Bit Converter block maps each integer (or fixed-point value) in the input vector to a group of bits in the output vector.
The block maps each integer value (or stored integer when you use a fixed point input) to a group of M bits, using the selection for the Output bit order to determine the most significant bit. The resulting output vector length is M times the input vector length.
When you set the Number of bits per integer parameter to M and Treat input values as to Unsigned, then the input values must be between 0 and 2M-1. When you set Number of bits per integer to M and Treat input values as to Signed, then the input values must be between –2M-1 and 2M-1-1. During simulation, the block performs a run-time check and issues an error if any input value is outside of the appropriate range. When the block generates code, it does not perform this run-time check.
This block is single-rate and single-channel. It accepts a length N column vector or a scalar-valued (N = 1) input signal and outputs a length N·M column vector.
The block can accept the data types int8, uint8, int16, uint16, int32, uint32, single, double, and fixed point.
The number of bits the block uses to represent each integer of the input. This parameter must be an integer between 1 and 32.
Indicate if the integer value input ranges should be treated as signed or unsigned. The default setting is Unsigned.
Define whether the first bit of the output signal is the most significant bit (MSB) or the least significant bit (LSB). The default selection is MSB first.
The default selection for this parameter is Inherit via internal rule.
When the parameter is set to Inherit via internal rule, the block determines the output data type based on the input data type.
If the input signal is floating-point (either single or double), the output data type is the same as the input data type.
If the input data type is not floating-point, the output data type is determined as if the parameter is set to Smallest integer.
When the parameter is set to Smallest integer, the block selects the output data type based on settings used in the Hardware Implementation Pane (Simulink) of the Configuration Parameters dialog box.
If you select ASIC/FPGA, the output data type is the ideal one-bit size; ufix1.
This example illustrates how to use the Bit to Integer and Integer to Bit Converter blocks with fixed-point signals.
This example uses a simplified audio scrambler configuration and a 16-bit, fixed-point digital audio source, which is recorded speech. The left-side of the model represents the audio scrambler subsystem and the right-side represents the descrambler subsystem.
You can open the model by typing doc_audioscrambler at the MATLAB® command line.
In the audio scrambler subsystem, the Integer to Bit Converter block unpacks each 16-bit audio sample into a binary, 1-bit signal. The binary signal passes to a linear feedback shift register (LFSR) scrambler, which randomizes the bits in a controllable way, thereby scrambling the signal. The Communications Toolbox™ Scrambler block is used in the LFSR implementation. From the LFSR, the scrambled audio bits pass to the Bit to Integer Converter block. This block packs the scrambled 1-bit samples into 16-bit audio samples. The audio samples pass to the Data Type Conversion block, which converts the integer-based audio samples back into fixed-point samples.
The fixed-point samples pass from the scrambler subsystem to a channel. The channel sends the samples to the descrambler subsystem. For illustrative purposes, this example uses a noiseless channel. In an actual system, a channel may introduce noise. Removing such noise requires a more sophisticated design.
In the audio descrambler subsystem, the Integer to Bit Converter block unpacks each 16-bit audio sample into a binary, 1-bit signal. The binary signal passes to a linear feedback shift register (LFSR) descrambler, which randomizes the bits in a controllable way, reversing the scrambling process. This LFSR descrambler implementation uses the Communications Toolbox Descrambler block. From the LFSR, the descrambled audio bits pass to the Bit to Integer Converter block. This block packs the descrambled 1-bit samples into 16-bit audio samples. The audio samples pass to the Data Type Conversion block, which converts the integer-based audio samples back into fixed-point samples.
In Simulink, the sfix16_En15 data type represents a signed (s) fixed-point (fix) signal with word length 16 and fraction length 15. Therefore, this model represents audio signals using the sfix16_En15 data type, except when converting to and from 1-bit binary signals. All 1-bit signals are represented by ufix1, as seen at the output of the Integer to Bit Converter block. The audio source has a frame size (or number of samples per frame) of 1024. For more information on fixed-point signals, please refer to Fixed-Point Numbers in the Simulink documentation.
You must run the example before you can listen to any of the audio signals.
You can run the example by clicking Simulation > Run.
You can hear the audio signals by clicking the model’s yellow, audio icons.