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| ifc
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Prob001_zero |
Build a circuit that always outputs a LOW.
module TopModule (
output zero
);
|
module TopModule (
output zero
);
|
module RefModule (
output zero
);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should 0");
repeat(20) @(posedge clk, negedge clk);
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_zero;
int errortime_zero;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic zero_ref;
logic zero_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.zero(zero_ref) );
TopModule top_module1 (
.zero(zero_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_zero) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "zero", stats1.errors_zero, stats1.errortime_zero);
else $display("Hint: Output '%s' has no mismatches.", "zero");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))
begin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;
stats1.errors_zero = stats1.errors_zero+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob002_m2014_q4i |
Build a circuit with no inputs and one output. That output should always
drive 0 (or logic low).
module TopModule (
output out
);
|
module TopModule (
output out
);
|
module RefModule (
output out
);
assign out = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.out(out_ref) );
TopModule top_module1 (
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob003_step_one |
Build a circuit with no inputs and one output. That output should always
drive 1 (or logic high).
module TopModule (
output one
);
|
module TopModule (
output one
);
|
module RefModule (
output one
);
assign one = 1'b1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should be 1");
repeat(20) @(posedge clk, negedge clk);
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_one;
int errortime_one;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic one_ref;
logic one_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,one_ref,one_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
RefModule good1 (
.one(one_ref) );
TopModule top_module1 (
.one(one_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_one) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "one", stats1.errors_one, stats1.errortime_one);
else $display("Hint: Output '%s' has no mismatches.", "one");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { one_ref } === ( { one_ref } ^ { one_dut } ^ { one_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (one_ref !== ( one_ref ^ one_dut ^ one_ref ))
begin if (stats1.errors_one == 0) stats1.errortime_one = $time;
stats1.errors_one = stats1.errors_one+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob004_vector2 |
Build a circuit that reverses the byte order of a 32-bit vector.
module TopModule (
input [31:0] in,
output [31:0] out
);
|
module TopModule (
input [31:0] in,
output [31:0] out
);
|
module RefModule (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk, negedge clk)
in <= $random;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [31:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob005_notgate |
Create a module that implements a NOT gate.
module TopModule (
input in,
output out
);
|
module TopModule (
input in,
output out
);
|
module RefModule (
input in,
output out
);
assign out = ~in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 1'b0;
wavedrom_start("Inversion");
repeat(20) @(posedge clk)
in <= $random;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob006_vectorr |
Given an 8-bit input vector [7:0], reverse its bit ordering.
module TopModule (
input [7:0] in,
output [7:0] out
);
|
module TopModule (
input [7:0] in,
output [7:0] out
);
|
module RefModule (
input [7:0] in,
output [7:0] out
);
assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) in <= 8'h1;
@(posedge clk) in <= 8'h2;
@(posedge clk) in <= 8'h4;
@(posedge clk) in <= 8'h8;
@(posedge clk) in <= 8'h80;
@(posedge clk) in <= 8'hc0;
@(posedge clk) in <= 8'he0;
@(posedge clk) in <= 8'hf0;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob007_wire |
Create a module with one input and one output that behaves like a wire.
module TopModule (
input in,
output out
);
|
module TopModule (
input in,
output out
);
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should follow input");
repeat(20) @(posedge clk, negedge clk)
in <= $random;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob008_m2014_q4h |
The module assigns the output port to the same value as the input port
combinationally.
module TopModule (
input in,
output out
);
|
module TopModule (
input in,
output out
);
|
module RefModule (
input in,
output out
);
assign out = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg in = 0
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob009_popcount3 |
A "population count" circuit counts the number of '1's in an input
vector. Build a population count circuit for a 3-bit input vector.
module TopModule (
input [2:0] in,
output [1:0] out
);
|
module TopModule (
input [2:0] in,
output [1:0] out
);
|
module RefModule (
input [2:0] in,
output [1:0] out
);
assign out = in[0]+in[1]+in[2];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [2:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 7;
@(negedge clk);
wavedrom_start();
repeat(9) @(posedge clk) in <= in + 1'b1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] in;
logic [1:0] out_ref;
logic [1:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob010_mt2015_q4a |
Implement the boolean function z = (x^y) & x.
module TopModule (
input x,
input y,
output z
);
|
module TopModule (
input x,
input y,
output z
);
|
module RefModule (
input x,
input y,
output z
);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic y;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.z(z_ref) );
TopModule top_module1 (
.x,
.y,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob011_norgate |
Create a module that implements a NOR gate.
module TopModule (
input a,
input b,
output out
);
|
module TopModule (
input a,
input b,
output out
);
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("NOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob012_xnorgate |
Create a module that implements an XNOR gate.
module TopModule (
input a,
input b,
output out
);
|
module TopModule (
input a,
input b,
output out
);
|
module RefModule (
input a,
input b,
output out
);
assign out = ~(a^b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("XNOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob013_m2014_q4e |
Implement a 2-input NOR gate.
module TopModule (
input in1,
input in2,
output logic out
);
|
module TopModule (
input in1,
input in2,
output logic out
);
|
module RefModule (
input in1,
input in2,
output logic out
);
assign out = ~(in1 | in2);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2 );
RefModule good1 (
.in1,
.in2,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob014_andgate |
Create a module that implements an AND gate.
module TopModule (
input a,
input b,
output out
);
|
module TopModule (
input a,
input b,
output out
);
|
module RefModule (
input a,
input b,
output out
);
assign out = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("AND gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob015_vector1 |
Build a combinational circuit that splits an input half-word (16 bits,
[15:0] ) into lower [7:0] and upper [15:8] bytes.
module TopModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
|
module TopModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
|
module RefModule (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
in <= $random;
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_hi;
int errortime_out_hi;
int errors_out_lo;
int errortime_out_lo;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] in;
logic [7:0] out_hi_ref;
logic [7:0] out_hi_dut;
logic [7:0] out_lo_ref;
logic [7:0] out_lo_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_hi_ref,out_hi_dut,out_lo_ref,out_lo_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_hi(out_hi_ref),
.out_lo(out_lo_ref) );
TopModule top_module1 (
.in,
.out_hi(out_hi_dut),
.out_lo(out_lo_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_hi) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_hi", stats1.errors_out_hi, stats1.errortime_out_hi);
else $display("Hint: Output '%s' has no mismatches.", "out_hi");
if (stats1.errors_out_lo) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_lo", stats1.errors_out_lo, stats1.errortime_out_lo);
else $display("Hint: Output '%s' has no mismatches.", "out_lo");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_hi_ref, out_lo_ref } === ( { out_hi_ref, out_lo_ref } ^ { out_hi_dut, out_lo_dut } ^ { out_hi_ref, out_lo_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_hi_ref !== ( out_hi_ref ^ out_hi_dut ^ out_hi_ref ))
begin if (stats1.errors_out_hi == 0) stats1.errortime_out_hi = $time;
stats1.errors_out_hi = stats1.errors_out_hi+1'b1; end
if (out_lo_ref !== ( out_lo_ref ^ out_lo_dut ^ out_lo_ref ))
begin if (stats1.errors_out_lo == 0) stats1.errortime_out_lo = $time;
stats1.errors_out_lo = stats1.errors_out_lo+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob016_m2014_q4j |
Implement a 4-bit adder with full adders. The output sum should include
the overflow bit.
module TopModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
|
module TopModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
|
module RefModule (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
assign sum = x+y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] x,y
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{x,y} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_sum;
int errortime_sum;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] x;
logic [3:0] y;
logic [4:0] sum_ref;
logic [4:0] sum_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,sum_ref,sum_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.sum(sum_ref) );
TopModule top_module1 (
.x,
.y,
.sum(sum_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { sum_ref } === ( { sum_ref } ^ { sum_dut } ^ { sum_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob017_mux2to1v |
Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
module TopModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
|
module TopModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
|
module RefModule (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 'hdeadbeef;
b <= 'h5eaf00d;
sel <= 0;
@(negedge clk);
wavedrom_start("Beef or seafood?");
repeat(6) @(posedge clk) sel <= ~sel;
@(negedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= {$random, $random, $random, $random, $random, $random, $random};
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] a;
logic [99:0] b;
logic sel;
logic [99:0] out_ref;
logic [99:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel );
RefModule good1 (
.a,
.b,
.sel,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob018_mux256to1 |
Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed
into a single 256-bit input vector. sel=0 should select in[0], sel=1
selects bits in[1], sel=2 selects bits in[2], etc.
module TopModule (
input [255:0] in,
input [7:0] sel,
output out
);
|
module TopModule (
input [255:0] in,
input [7:0] sel,
output out
);
|
module RefModule (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<8; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [255:0] in;
logic [7:0] sel;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.sel );
RefModule good1 (
.in,
.sel,
.out(out_ref) );
TopModule top_module1 (
.in,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob019_m2014_q4f |
Implement the following circuit in Verilog. Two inputs (in1 and in2) go
to an AND gate, but the in2 input to the AND gate has a bubble. The
output of the AND gate is connected to 'out'.
module TopModule (
input in1,
input in2,
output logic out
);
|
module TopModule (
input in1,
input in2,
output logic out
);
|
module RefModule (
input in1,
input in2,
output logic out
);
assign out = in1 & ~in2;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2 );
RefModule good1 (
.in1,
.in2,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob020_mt2015_eq2 |
Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and
produces an output z. The value of z should be 1 if A = B, otherwise z
should be 0.
module TopModule (
input [1:0] A,
input [1:0] B,
output z
);
|
module TopModule (
input [1:0] A,
input [1:0] B,
output z
);
|
module RefModule (
input [1:0] A,
input [1:0] B,
output z
);
assign z = A[1:0]==B[1:0];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 1k. 2-bit equality comparator.
*/
module stimulus_gen (
input clk,
output logic [1:0] A,
output logic [1:0] B
);
always @(posedge clk, negedge clk)
{A, B} <= $random % 16;
initial begin
repeat(1000) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [1:0] A;
logic [1:0] B;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,A,B,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.A,
.B );
RefModule good1 (
.A,
.B,
.z(z_ref) );
TopModule top_module1 (
.A,
.B,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob021_mux256to1v |
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all
packed into a single 1024-bit input vector. sel=0 should select bits
in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
module TopModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
|
module TopModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
|
module RefModule (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [1023:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<32; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [1023:0] in;
logic [7:0] sel;
logic [3:0] out_ref;
logic [3:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.sel );
RefModule good1 (
.in,
.sel,
.out(out_ref) );
TopModule top_module1 (
.in,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob022_mux2to1 |
Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When
sel=1, choose b.
module TopModule (
input a,
input b,
input sel,
output out
);
|
module TopModule (
input a,
input b,
input sel,
output out
);
|
module RefModule (
input a,
input b,
input sel,
output out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel} <= 3'b000;
@(negedge clk) wavedrom_start("<b>Sel</b> chooses between <b>a</b> and <b>b</b>");
@(posedge clk) {a, b, sel} <= 3'b000;
@(posedge clk) {a, b, sel} <= 3'b100;
@(posedge clk) {a, b, sel} <= 3'b110;
@(posedge clk) {a, b, sel} <= 3'b111;
@(posedge clk) {a, b, sel} <= 3'b011;
@(posedge clk) {a, b, sel} <= 3'b001;
@(posedge clk) {a, b, sel} <= 3'b100;
@(posedge clk) {a, b, sel} <= 3'b101;
@(posedge clk) {a, b, sel} <= 3'b110;
@(posedge clk) {a, b, sel} <= 3'b111;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sel;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel );
RefModule good1 (
.a,
.b,
.sel,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob023_vector100r |
Given a 100-bit input vector [99:0], reverse its bit ordering.
a
module TopModule (
input [99:0] in,
output reg [99:0] out
);
|
module TopModule (
input [99:0] in,
output reg [99:0] out
);
|
module RefModule (
input [99:0] in,
output reg [99:0] out
);
always_comb
for (int i=0;i<$bits(out);i++)
out[i] = in[$bits(out)-i-1];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [99:0] in
);
always @(posedge clk, negedge clk)
in <= {$random, $random, $random, $random};
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] in;
logic [99:0] out_ref;
logic [99:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob024_hadd |
Create a half adder. A half adder adds two bits (with no carry-in) and
produces a sum and carry-out.
module TopModule (
input a,
input b,
output sum,
output cout
);
|
module TopModule (
input a,
input b,
output sum,
output cout
);
|
module RefModule (
input a,
input b,
output sum,
output cout
);
assign {cout, sum} = a+b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b
);
always @(posedge clk, negedge clk)
{a,b} <= $random;
initial begin
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_sum;
int errortime_sum;
int errors_cout;
int errortime_cout;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sum_ref;
logic sum_dut;
logic cout_ref;
logic cout_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sum_ref,sum_dut,cout_ref,cout_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.sum(sum_ref),
.cout(cout_ref) );
TopModule top_module1 (
.a,
.b,
.sum(sum_dut),
.cout(cout_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
if (stats1.errors_cout) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "cout", stats1.errors_cout, stats1.errortime_cout);
else $display("Hint: Output '%s' has no mismatches.", "cout");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { sum_ref, cout_ref } === ( { sum_ref, cout_ref } ^ { sum_dut, cout_dut } ^ { sum_ref, cout_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
if (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))
begin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;
stats1.errors_cout = stats1.errors_cout+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob025_reduction |
Parity checking is often used as a simple method of detecting errors when
transmitting data through an imperfect channel. Create a circuit that
will compute a parity bit for a 8-bit byte (which will add a 9th bit to
the byte). We will use "even" parity, where the parity bit is just the
XOR of all 8 data bits.
module TopModule (
input [7:0] in,
output parity
);
|
module TopModule (
input [7:0] in,
output parity
);
|
module RefModule (
input [7:0] in,
output parity
);
assign parity = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_parity;
int errortime_parity;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic parity_ref;
logic parity_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,parity_ref,parity_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.parity(parity_ref) );
TopModule top_module1 (
.in,
.parity(parity_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_parity) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "parity", stats1.errors_parity, stats1.errortime_parity);
else $display("Hint: Output '%s' has no mismatches.", "parity");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { parity_ref } === ( { parity_ref } ^ { parity_dut } ^ { parity_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (parity_ref !== ( parity_ref ^ parity_dut ^ parity_ref ))
begin if (stats1.errors_parity == 0) stats1.errortime_parity = $time;
stats1.errors_parity = stats1.errors_parity+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob026_alwaysblock1 |
Build an AND gate using both an assign statement and a combinational
always block.
module TopModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
|
module TopModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
|
module RefModule (
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("AND gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_alwaysblock;
int errortime_out_alwaysblock;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_assign_ref;
logic out_assign_dut;
logic out_alwaysblock_ref;
logic out_alwaysblock_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_assign_ref,out_assign_dut,out_alwaysblock_ref,out_alwaysblock_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out_assign(out_assign_ref),
.out_alwaysblock(out_alwaysblock_ref) );
TopModule top_module1 (
.a,
.b,
.out_assign(out_assign_dut),
.out_alwaysblock(out_alwaysblock_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_alwaysblock) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_alwaysblock", stats1.errors_out_alwaysblock, stats1.errortime_out_alwaysblock);
else $display("Hint: Output '%s' has no mismatches.", "out_alwaysblock");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_alwaysblock_ref } === ( { out_assign_ref, out_alwaysblock_ref } ^ { out_assign_dut, out_alwaysblock_dut } ^ { out_assign_ref, out_alwaysblock_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_alwaysblock_ref !== ( out_alwaysblock_ref ^ out_alwaysblock_dut ^ out_alwaysblock_ref ))
begin if (stats1.errors_out_alwaysblock == 0) stats1.errortime_out_alwaysblock = $time;
stats1.errors_out_alwaysblock = stats1.errors_out_alwaysblock+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob027_fadd |
Create a full adder. A full adder adds three bits (including carry-in)
and produces a sum and carry-out.
module TopModule (
input a,
input b,
input cin,
output cout,
output sum
);
|
module TopModule (
input a,
input b,
input cin,
output cout,
output sum
);
|
module RefModule (
input a,
input b,
input cin,
output cout,
output sum
);
assign {cout, sum} = a+b+cin;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,cin,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start();
@(posedge clk) {a,b,cin} <= 3'b000;
@(posedge clk) {a,b,cin} <= 3'b010;
@(posedge clk) {a,b,cin} <= 3'b100;
@(posedge clk) {a,b,cin} <= 3'b110;
@(posedge clk) {a,b,cin} <= 3'b000;
@(posedge clk) {a,b,cin} <= 3'b001;
@(posedge clk) {a,b,cin} <= 3'b011;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{a,b,cin} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_cout;
int errortime_cout;
int errors_sum;
int errortime_sum;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic cin;
logic cout_ref;
logic cout_dut;
logic sum_ref;
logic sum_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,cin,cout_ref,cout_dut,sum_ref,sum_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.cin );
RefModule good1 (
.a,
.b,
.cin,
.cout(cout_ref),
.sum(sum_ref) );
TopModule top_module1 (
.a,
.b,
.cin,
.cout(cout_dut),
.sum(sum_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_cout) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "cout", stats1.errors_cout, stats1.errortime_cout);
else $display("Hint: Output '%s' has no mismatches.", "cout");
if (stats1.errors_sum) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "sum", stats1.errors_sum, stats1.errortime_sum);
else $display("Hint: Output '%s' has no mismatches.", "sum");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { cout_ref, sum_ref } === ( { cout_ref, sum_ref } ^ { cout_dut, sum_dut } ^ { cout_ref, sum_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (cout_ref !== ( cout_ref ^ cout_dut ^ cout_ref ))
begin if (stats1.errors_cout == 0) stats1.errortime_cout = $time;
stats1.errors_cout = stats1.errors_cout+1'b1; end
if (sum_ref !== ( sum_ref ^ sum_dut ^ sum_ref ))
begin if (stats1.errors_sum == 0) stats1.errortime_sum = $time;
stats1.errors_sum = stats1.errors_sum+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob028_m2014_q4a |
Implement a D latch using an always block.
module TopModule (
input d,
input ena,
output logic q
);
|
module TopModule (
input d,
input ena,
output logic q
);
|
module RefModule (
input d,
input ena,
output logic q
);
always@(*) begin
if (ena)
q = d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ena
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ena} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic ena;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,d,ena,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.ena );
RefModule good1 (
.d,
.ena,
.q(q_ref) );
TopModule top_module1 (
.d,
.ena,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob029_m2014_q4g |
Implement in Verilog the following circuit: A two-input XNOR (connected
to 'in1' and 'in2) has an output connected to the input of a two-input
XOR. The second input of the XOR is 'in3.' The output of the XOR is
'out'.
module TopModule (
input in1,
input in2,
input in3,
output logic out
);
|
module TopModule (
input in1,
input in2,
input in3,
output logic out
);
|
module RefModule (
input in1,
input in2,
input in3,
output logic out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in1, in2, in3
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{in1, in2, in3} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in1;
logic in2;
logic in3;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in1,in2,in3,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in1,
.in2,
.in3 );
RefModule good1 (
.in1,
.in2,
.in3,
.out(out_ref) );
TopModule top_module1 (
.in1,
.in2,
.in3,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob030_popcount255 |
A "population count" circuit counts the number of '1's in an input
vector. Build a population count circuit for a 255-bit input vector.
module TopModule (
input [254:0] in,
output reg [7:0] out
);
|
module TopModule (
input [254:0] in,
output reg [7:0] out
);
|
module RefModule (
input [254:0] in,
output reg [7:0] out
);
always_comb begin
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [254:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 255'h0;
wavedrom_start("");
@(posedge clk, negedge clk) in <= 255'h0;
@(posedge clk, negedge clk) in <= 255'h0;
@(posedge clk, negedge clk) in <= 255'h1;
@(posedge clk, negedge clk) in <= 255'h1;
@(posedge clk, negedge clk) in <= 255'h3;
@(posedge clk, negedge clk) in <= 255'h3;
@(posedge clk, negedge clk) in <= 255'h7;
@(posedge clk, negedge clk) in <= 255'haaaa;
@(posedge clk, negedge clk) in <= 255'hf00000;
@(posedge clk, negedge clk) in <= 255'h0;
wavedrom_stop();
repeat (200) @(posedge clk, negedge clk) begin
in <= {$random, $random, $random, $random, $random, $random, $random, $random};
end
@(posedge clk);
in <= '0;
@(posedge clk)
in <= '1;
@(posedge clk)
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [254:0] in;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob031_dff |
Create a single D flip-flop.
module TopModule (
input clk,
input d,
output reg q
);
|
module TopModule (
input clk,
input d,
output reg q
);
|
module RefModule (
input clk,
input d,
output reg q
);
initial
q = 1'hx;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
d <= $urandom;
initial begin
@(posedge clk);
wavedrom_start("Positive-edge triggered DFF");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
RefModule good1 (
.clk,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob032_vector0 |
Build a circuit that has one 3-bit input, then outputs the same vector,
and also splits it into three separate 1-bit outputs. Connect output o0
to the input vector's position 0, o1 to position 1, etc.
module TopModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
|
module TopModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
|
module RefModule (
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
vec <= 3'b0;
@(negedge clk);
wavedrom_start();
repeat(10) @(posedge clk)
vec <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_outv;
int errortime_outv;
int errors_o2;
int errortime_o2;
int errors_o1;
int errortime_o1;
int errors_o0;
int errortime_o0;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] vec;
logic [2:0] outv_ref;
logic [2:0] outv_dut;
logic o2_ref;
logic o2_dut;
logic o1_ref;
logic o1_dut;
logic o0_ref;
logic o0_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,vec,outv_ref,outv_dut,o2_ref,o2_dut,o1_ref,o1_dut,o0_ref,o0_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.vec );
RefModule good1 (
.vec,
.outv(outv_ref),
.o2(o2_ref),
.o1(o1_ref),
.o0(o0_ref) );
TopModule top_module1 (
.vec,
.outv(outv_dut),
.o2(o2_dut),
.o1(o1_dut),
.o0(o0_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_outv) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "outv", stats1.errors_outv, stats1.errortime_outv);
else $display("Hint: Output '%s' has no mismatches.", "outv");
if (stats1.errors_o2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o2", stats1.errors_o2, stats1.errortime_o2);
else $display("Hint: Output '%s' has no mismatches.", "o2");
if (stats1.errors_o1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o1", stats1.errors_o1, stats1.errortime_o1);
else $display("Hint: Output '%s' has no mismatches.", "o1");
if (stats1.errors_o0) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o0", stats1.errors_o0, stats1.errortime_o0);
else $display("Hint: Output '%s' has no mismatches.", "o0");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { outv_ref, o2_ref, o1_ref, o0_ref } === ( { outv_ref, o2_ref, o1_ref, o0_ref } ^ { outv_dut, o2_dut, o1_dut, o0_dut } ^ { outv_ref, o2_ref, o1_ref, o0_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (outv_ref !== ( outv_ref ^ outv_dut ^ outv_ref ))
begin if (stats1.errors_outv == 0) stats1.errortime_outv = $time;
stats1.errors_outv = stats1.errors_outv+1'b1; end
if (o2_ref !== ( o2_ref ^ o2_dut ^ o2_ref ))
begin if (stats1.errors_o2 == 0) stats1.errortime_o2 = $time;
stats1.errors_o2 = stats1.errors_o2+1'b1; end
if (o1_ref !== ( o1_ref ^ o1_dut ^ o1_ref ))
begin if (stats1.errors_o1 == 0) stats1.errortime_o1 = $time;
stats1.errors_o1 = stats1.errors_o1+1'b1; end
if (o0_ref !== ( o0_ref ^ o0_dut ^ o0_ref ))
begin if (stats1.errors_o0 == 0) stats1.errortime_o0 = $time;
stats1.errors_o0 = stats1.errors_o0+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob033_ece241_2014_q1c |
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0].
These numbers are added to produce s[7:0]. Also compute whether a
(signed) overflow has occurred.
module TopModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
|
module TopModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
|
module RefModule (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b} <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) {a, b} <= 16'h0;
@(posedge clk) {a, b} <= 16'h0070;
@(posedge clk) {a, b} <= 16'h7070;
@(posedge clk) {a, b} <= 16'h7090;
@(posedge clk) {a, b} <= 16'h9070;
@(posedge clk) {a, b} <= 16'h9090;
@(posedge clk) {a, b} <= 16'h90ff;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_s;
int errortime_s;
int errors_overflow;
int errortime_overflow;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] a;
logic [7:0] b;
logic [7:0] s_ref;
logic [7:0] s_dut;
logic overflow_ref;
logic overflow_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.s(s_ref),
.overflow(overflow_ref) );
TopModule top_module1 (
.a,
.b,
.s(s_dut),
.overflow(overflow_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_s) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "s", stats1.errors_s, stats1.errortime_s);
else $display("Hint: Output '%s' has no mismatches.", "s");
if (stats1.errors_overflow) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "overflow", stats1.errors_overflow, stats1.errortime_overflow);
else $display("Hint: Output '%s' has no mismatches.", "overflow");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (s_ref !== ( s_ref ^ s_dut ^ s_ref ))
begin if (stats1.errors_s == 0) stats1.errortime_s = $time;
stats1.errors_s = stats1.errors_s+1'b1; end
if (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))
begin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;
stats1.errors_overflow = stats1.errors_overflow+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob034_dff8 |
Create 8 D flip-flops. All DFFs should be triggered by the positive edge
of clk.
module TopModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
|
module TopModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
|
module RefModule (
input clk,
input [7:0] d,
output reg [7:0] q
);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
d <= $random % 256;
initial begin
@(posedge clk);
wavedrom_start("Positive-edge triggered DFF");
repeat(10) @(posedge clk);
wavedrom_stop();
#100;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
RefModule good1 (
.clk,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob035_count1to10 |
Make a decade counter that counts 1 through 10, inclusive. The reset
input is active high synchronous, and should reset the counter to 1.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 10)
q <= 1;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset and counting.");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob036_ringer |
Suppose you are designing a circuit to control a cellphone's ringer and
vibration motor. Whenever the phone needs to ring from an incoming call
(input ring), your circuit must either turn on the ringer (output ringer
= 1) or the motor (output motor = 1), but not both. If the phone is in
vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn
on the ringer.
module TopModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
|
module TopModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
|
module RefModule (
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{vibrate_mode,ring} <= 1'b0;
wavedrom_start();
repeat(10) @(posedge clk)
{vibrate_mode,ring} <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_ringer;
int errortime_ringer;
int errors_motor;
int errortime_motor;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic ring;
logic vibrate_mode;
logic ringer_ref;
logic ringer_dut;
logic motor_ref;
logic motor_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.ring,
.vibrate_mode );
RefModule good1 (
.ring,
.vibrate_mode,
.ringer(ringer_ref),
.motor(motor_ref) );
TopModule top_module1 (
.ring,
.vibrate_mode,
.ringer(ringer_dut),
.motor(motor_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_ringer) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "ringer", stats1.errors_ringer, stats1.errortime_ringer);
else $display("Hint: Output '%s' has no mismatches.", "ringer");
if (stats1.errors_motor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "motor", stats1.errors_motor, stats1.errortime_motor);
else $display("Hint: Output '%s' has no mismatches.", "motor");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))
begin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;
stats1.errors_ringer = stats1.errors_ringer+1'b1; end
if (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))
begin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;
stats1.errors_motor = stats1.errors_motor+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob037_review2015_count1k |
Build a counter that counts from 0 to 999, inclusive, with a period of
1000 cycles. The reset input is active high synchronous, and should reset
the counter to 0.
module TopModule (
input clk,
input reset,
output reg [9:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [9:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [9:0] q
);
always @(posedge clk)
if (reset || q == 999)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset");
reset_test();
repeat(5) @(posedge clk);
wavedrom_stop();
reset <= 0;
repeat(989) @(negedge clk);
wavedrom_start("Wrap around behaviour");
repeat(14)@(posedge clk);
wavedrom_stop();
repeat(2000) @(posedge clk, negedge clk) begin
reset <= !($random & 127);
end
reset <= 0;
repeat(2000) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [9:0] q_ref;
logic [9:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob038_count15 |
Build a 4-bit binary counter that counts from 0 through 15, inclusive,
with a period of 16. The reset input is active high synchronous, and
should reset the counter to 0.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
input tb_match,
output reg wavedrom_enable,
output reg[511:0] wavedrom_title
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
@(negedge clk);
wavedrom_start("Reset and counting");
reset_test();
repeat(3) @(posedge clk);
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob039_always_if |
Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1
and sel_b2 are true. Otherwise, choose a. Do the same twice, once using
assign statements and once using a procedural if statement.
module TopModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
|
module TopModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
|
module RefModule (
input a,
input b,
input sel_b1,
input sel_b2,
output out_assign,
output reg out_always
);
assign out_assign = (sel_b1 & sel_b2) ? b : a;
always @(*) out_always = (sel_b1 & sel_b2) ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,sel_b1, sel_b2,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel_b1, sel_b2} <= 4'b000;
@(negedge clk) wavedrom_start("");
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0100;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1000;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1101;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0001;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0110;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1010;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1011;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b1111;
@(posedge clk, negedge clk) {a,b,sel_b1,sel_b2} <= 4'b0011;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel_b1,sel_b2} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_always;
int errortime_out_always;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic sel_b1;
logic sel_b2;
logic out_assign_ref;
logic out_assign_dut;
logic out_always_ref;
logic out_always_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel_b1,sel_b2,out_assign_ref,out_assign_dut,out_always_ref,out_always_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel_b1,
.sel_b2 );
RefModule good1 (
.a,
.b,
.sel_b1,
.sel_b2,
.out_assign(out_assign_ref),
.out_always(out_always_ref) );
TopModule top_module1 (
.a,
.b,
.sel_b1,
.sel_b2,
.out_assign(out_assign_dut),
.out_always(out_always_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_always) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always", stats1.errors_out_always, stats1.errortime_out_always);
else $display("Hint: Output '%s' has no mismatches.", "out_always");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_always_ref } === ( { out_assign_ref, out_always_ref } ^ { out_assign_dut, out_always_dut } ^ { out_assign_ref, out_always_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_always_ref !== ( out_always_ref ^ out_always_dut ^ out_always_ref ))
begin if (stats1.errors_out_always == 0) stats1.errortime_out_always = $time;
stats1.errors_out_always = stats1.errors_out_always+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob040_count10 |
Build a decade counter that counts from 0 through 9, inclusive, with a
period of 10. The reset input is active high synchronous, and should
reset the counter to 0.
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [3:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset || q == 9)
q <= 0;
else
q <= q+1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
wavedrom_start("Synchronous reset and counting");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob041_dff8r |
Create 8 D flip-flops with active high synchronous reset setting the
output to zero. All DFFs should be triggered by the positive edge of clk.
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
|
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
|
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
wavedrom_start("Synchronous active-high reset");
reset_test();
repeat(10) @(negedge clk)
d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic reset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.reset );
RefModule good1 (
.clk,
.d,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob042_vector4 |
One common place to see a replication operator is when sign-extending a
smaller number to a larger one, while preserving its signed value. This
is done by replicating the sign bit (the most significant bit) of the
smaller number to the left. For example, sign-extending 4'b0101 (5) to 8
bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8
bits results in 8'b11111101 (-3). Build a circuit that sign-extends an
8-bit number to 32 bits. This requires a concatenation of 24 copies of
the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit
number itself.
module TopModule (
input [7:0] in,
output [31:0] out
);
|
module TopModule (
input [7:0] in,
output [31:0] out
);
|
module RefModule (
input [7:0] in,
output [31:0] out
);
assign out = { {24{in[7]}}, in };
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in
);
initial begin
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out(out_ref) );
TopModule top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob043_vector5 |
Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise
one- bit comparisons in the 25-bit output vector. The output should be 1
if the two bits being compared are equal. Example: out[24] = ~a ^ a;
out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^
e.
module TopModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
|
module TopModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
|
module RefModule (
input a,
input b,
input c,
input d,
input e,
output [24:0] out
);
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a, b, c, d, e
);
initial begin
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic e;
logic [24:0] out_ref;
logic [24:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e );
RefModule good1 (
.a,
.b,
.c,
.d,
.e,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.e,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob044_vectorgates |
Build a circuit that has two 3-bit inputs that computes the bitwise-OR of
the two vectors, the logical-OR of the two vectors, and the inverse (NOT)
of both vectors. Place the inverse of b in the upper half of out_not
(i.e., bits [5:3]), and the inverse of a in the lower half.
module TopModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
|
module TopModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
|
module RefModule (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b,~a};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 6'h38;
{b, a} <= 6'b0;
@(negedge clk);
wavedrom_start();
repeat(30) @(posedge clk)
{b, a} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_or_bitwise;
int errortime_out_or_bitwise;
int errors_out_or_logical;
int errortime_out_or_logical;
int errors_out_not;
int errortime_out_not;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] a;
logic [2:0] b;
logic [2:0] out_or_bitwise_ref;
logic [2:0] out_or_bitwise_dut;
logic out_or_logical_ref;
logic out_or_logical_dut;
logic [5:0] out_not_ref;
logic [5:0] out_not_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_or_bitwise_ref,out_or_bitwise_dut,out_or_logical_ref,out_or_logical_dut,out_not_ref,out_not_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out_or_bitwise(out_or_bitwise_ref),
.out_or_logical(out_or_logical_ref),
.out_not(out_not_ref) );
TopModule top_module1 (
.a,
.b,
.out_or_bitwise(out_or_bitwise_dut),
.out_or_logical(out_or_logical_dut),
.out_not(out_not_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_or_bitwise) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or_bitwise", stats1.errors_out_or_bitwise, stats1.errortime_out_or_bitwise);
else $display("Hint: Output '%s' has no mismatches.", "out_or_bitwise");
if (stats1.errors_out_or_logical) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or_logical", stats1.errors_out_or_logical, stats1.errortime_out_or_logical);
else $display("Hint: Output '%s' has no mismatches.", "out_or_logical");
if (stats1.errors_out_not) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_not", stats1.errors_out_not, stats1.errortime_out_not);
else $display("Hint: Output '%s' has no mismatches.", "out_not");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } === ( { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ^ { out_or_bitwise_dut, out_or_logical_dut, out_not_dut } ^ { out_or_bitwise_ref, out_or_logical_ref, out_not_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_or_bitwise_ref !== ( out_or_bitwise_ref ^ out_or_bitwise_dut ^ out_or_bitwise_ref ))
begin if (stats1.errors_out_or_bitwise == 0) stats1.errortime_out_or_bitwise = $time;
stats1.errors_out_or_bitwise = stats1.errors_out_or_bitwise+1'b1; end
if (out_or_logical_ref !== ( out_or_logical_ref ^ out_or_logical_dut ^ out_or_logical_ref ))
begin if (stats1.errors_out_or_logical == 0) stats1.errortime_out_or_logical = $time;
stats1.errors_out_or_logical = stats1.errors_out_or_logical+1'b1; end
if (out_not_ref !== ( out_not_ref ^ out_not_dut ^ out_not_ref ))
begin if (stats1.errors_out_not == 0) stats1.errortime_out_not = $time;
stats1.errors_out_not = stats1.errors_out_not+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob045_edgedetect2 |
For each bit in an 8-bit vector, detect when the input signal changes
from one clock cycle to the next (detect any edge). The output bit should
be set the cycle after a 0 to 1 transition occurs.
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
|
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
|
module RefModule (
input clk,
input [7:0] in,
output reg [7:0] anyedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
anyedge <= in ^ d_last;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output reg [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(posedge clk);
@(negedge clk) wavedrom_start("");
repeat(2) @(posedge clk);
in <= 1;
repeat(4) @(posedge clk);
in <= 0;
repeat(4) @(negedge clk);
in <= 6;
repeat(2) @(negedge clk);
in <= 0;
repeat(2) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_anyedge;
int errortime_anyedge;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [7:0] anyedge_ref;
logic [7:0] anyedge_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,anyedge_ref,anyedge_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.clk,
.in,
.anyedge(anyedge_ref) );
TopModule top_module1 (
.clk,
.in,
.anyedge(anyedge_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_anyedge) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "anyedge", stats1.errors_anyedge, stats1.errortime_anyedge);
else $display("Hint: Output '%s' has no mismatches.", "anyedge");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { anyedge_ref } === ( { anyedge_ref } ^ { anyedge_dut } ^ { anyedge_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (anyedge_ref !== ( anyedge_ref ^ anyedge_dut ^ anyedge_ref ))
begin if (stats1.errors_anyedge == 0) stats1.errortime_anyedge = $time;
stats1.errors_anyedge = stats1.errors_anyedge+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob046_dff8p |
Create 8 D flip-flops with active high synchronous reset. The flip-flops
must be reset to 0x34 rather than zero. All DFFs should be triggered by
the negative edge of clk.
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
|
module TopModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
|
module RefModule (
input clk,
input [7:0] d,
input reset,
output reg [7:0] q
);
always @(negedge clk)
if (reset)
q <= 8'h34;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
@(negedge clk);
@(negedge clk);
wavedrom_start("Synchronous active-high reset");
reset_test();
repeat(10) @(negedge clk)
d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic reset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.reset );
RefModule good1 (
.clk,
.d,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob047_dff8ar |
Create 8 D flip-flops with active high asynchronous reset. The output
should be reset to 0. All DFFs should be triggered by the positive edge
of clk.
module TopModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
|
module TopModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
|
module RefModule (
input clk,
input [7:0] d,
input areset,
output reg [7:0] q
);
always @(posedge clk, posedge areset)
if (areset)
q <= 0;
else
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [7:0] d, output areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
d <= $random;
@(negedge clk);
@(negedge clk);
wavedrom_start("Asynchronous active-high reset");
reset_test(1);
repeat(7) @(negedge clk) d <= $random;
@(posedge clk) reset <= 1;
@(negedge clk) reset <= 0; d <= $random;
repeat(2) @(negedge clk) d <= $random;
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 15);
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic areset;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,areset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.areset );
RefModule good1 (
.clk,
.d,
.areset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.areset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob048_m2014_q4c |
Implement a simple D flip flop with active high synchronous reset (reset
output to 0).
module TopModule (
input clk,
input d,
input r,
output logic q
);
|
module TopModule (
input clk,
input d,
input r,
output logic q
);
|
module RefModule (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,r} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic r;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,r,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.r );
RefModule good1 (
.clk,
.d,
.r,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.r,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob049_m2014_q4b |
Implement a D flip flop, positive edge triggered, with an asynchronous
reset "ar".
module TopModule (
input clk,
input d,
input ar,
output logic q
);
|
module TopModule (
input clk,
input d,
input ar,
output logic q
);
|
module RefModule (
input clk,
input d,
input ar,
output logic q
);
always@(posedge clk or posedge ar) begin
if (ar)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic d, ar
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,ar} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic ar;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,ar,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.ar );
RefModule good1 (
.clk,
.d,
.ar,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.ar,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob050_kmap1 |
Implement the circuit described by the Karnaugh map below.
a
bc 0 1
00 | 0 | 1 |
01 | 1 | 1 |
11 | 1 | 1 |
10 | 1 | 1 |
module TopModule (
input a,
input b,
input c,
output out
);
|
module TopModule (
input a,
input b,
input c,
output out
);
|
module RefModule (
input a,
input b,
input c,
output out
);
assign out = (a | b | c);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c} <= 1'b0;
wavedrom_start();
repeat(10) @(posedge clk)
{a,b,c} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c );
RefModule good1 (
.a,
.b,
.c,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob051_gates4 |
Build a combinational circuit with four inputs, in[3:0]. There are 3
outputs:
(1) out_and: output of a 4-input AND gate.
(2) out_or: output of a 4-input OR gate.
(3) out_xor: output of a 4-input XOR gate.
module TopModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
|
module TopModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
|
module RefModule (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(negedge clk) wavedrom_start("All combinations");
@(posedge clk);
repeat(15) @(posedge clk) in <= in + 1;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_and;
int errortime_out_and;
int errors_out_or;
int errortime_out_or;
int errors_out_xor;
int errortime_out_xor;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] in;
logic out_and_ref;
logic out_and_dut;
logic out_or_ref;
logic out_or_dut;
logic out_xor_ref;
logic out_xor_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_and(out_and_ref),
.out_or(out_or_ref),
.out_xor(out_xor_ref) );
TopModule top_module1 (
.in,
.out_and(out_and_dut),
.out_or(out_or_dut),
.out_xor(out_xor_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_and) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_and", stats1.errors_out_and, stats1.errortime_out_and);
else $display("Hint: Output '%s' has no mismatches.", "out_and");
if (stats1.errors_out_or) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or", stats1.errors_out_or, stats1.errortime_out_or);
else $display("Hint: Output '%s' has no mismatches.", "out_or");
if (stats1.errors_out_xor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_xor", stats1.errors_out_xor, stats1.errortime_out_xor);
else $display("Hint: Output '%s' has no mismatches.", "out_xor");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))
begin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;
stats1.errors_out_and = stats1.errors_out_and+1'b1; end
if (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))
begin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;
stats1.errors_out_or = stats1.errors_out_or+1'b1; end
if (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))
begin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;
stats1.errors_out_xor = stats1.errors_out_xor+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob052_gates100 |
Build a combinational circuit with 100 inputs, in[99:0]. There are 3
outputs:
(1) out_and: output of a 100-input AND gate.
(2) out_or: output of a 100-input OR gate.
(3) out_xor: output of a 100-input XOR gate.
module TopModule (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
|
module TopModule (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
|
module RefModule (
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = ∈
assign out_or = |in;
assign out_xor = ^in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output logic [99:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reg [3:0] count; count = 0;
in <= 100'h0;
// AND gate uses huge numbers and creates a sparse waveform.
@(negedge clk) wavedrom_start("Test AND gate");
@(posedge clk,negedge clk) in <= 100'h0; // Test OR gate
@(posedge clk,negedge clk); in <= ~100'h0; // Test AND gate
@(posedge clk,negedge clk); in <= 100'h3ffff;
@(posedge clk,negedge clk); in <= ~100'h3ffff;
@(posedge clk,negedge clk); in <= 100'h80;
@(posedge clk,negedge clk); in <= ~100'h80;
wavedrom_stop();
@(negedge clk) wavedrom_start("Test OR and XOR gates");
@(posedge clk) in <= 100'h0; // Test OR gate
@(posedge clk); in <= 100'h7; // Test AND gate
repeat(10) @(posedge clk, negedge clk) begin
in <= count;
count <= count + 1;
end
@(posedge clk) in <= 100'h0;
@(negedge clk) wavedrom_stop();
in <= $random;
repeat(100) begin
@(negedge clk) in <= $random;
@(posedge clk) in <= $random;
end
for (int i=0;i<100;i++) begin
@(negedge clk) in <= 100'h1<<i;
@(posedge clk) in <= ~(100'h1<<i);
end
@(posedge clk) in <= 100'h0; // Test OR gate
@(posedge clk); in <= ~100'h0; // Test AND gate
@(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_and;
int errortime_out_and;
int errors_out_or;
int errortime_out_or;
int errors_out_xor;
int errortime_out_xor;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] in;
logic out_and_ref;
logic out_and_dut;
logic out_or_ref;
logic out_or_dut;
logic out_xor_ref;
logic out_xor_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_and(out_and_ref),
.out_or(out_or_ref),
.out_xor(out_xor_ref) );
TopModule top_module1 (
.in,
.out_and(out_and_dut),
.out_or(out_or_dut),
.out_xor(out_xor_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_and) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_and", stats1.errors_out_and, stats1.errortime_out_and);
else $display("Hint: Output '%s' has no mismatches.", "out_and");
if (stats1.errors_out_or) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or", stats1.errors_out_or, stats1.errortime_out_or);
else $display("Hint: Output '%s' has no mismatches.", "out_or");
if (stats1.errors_out_xor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_xor", stats1.errors_out_xor, stats1.errortime_out_xor);
else $display("Hint: Output '%s' has no mismatches.", "out_xor");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref } === ( { out_and_ref, out_or_ref, out_xor_ref } ^ { out_and_dut, out_or_dut, out_xor_dut } ^ { out_and_ref, out_or_ref, out_xor_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))
begin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;
stats1.errors_out_and = stats1.errors_out_and+1'b1; end
if (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))
begin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;
stats1.errors_out_or = stats1.errors_out_or+1'b1; end
if (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))
begin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;
stats1.errors_out_xor = stats1.errors_out_xor+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob053_m2014_q4d |
Implement in Verilog the following circuit: A D flip-flop takes as input
the output of a two-input XOR. The flip-flop is positive edge triggered
by clk, but there is no reset. The XOR takes as input 'in' along with the
output 'out' of the flip-flop.
module TopModule (
input clk,
input in,
output logic out
);
|
module TopModule (
input clk,
input in,
output logic out
);
|
module RefModule (
input clk,
input in,
output logic out
);
initial
out = 0;
always@(posedge clk) begin
out <= in ^ out;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.clk,
.in,
.out(out_ref) );
TopModule top_module1 (
.clk,
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob054_edgedetect |
For each bit in an 8-bit vector, detect when the input signal changes
from 0 in one clock cycle to 1 the next (similar to positive edge
detection). The output bit should be set the cycle after a 0 to 1
transition occurs.
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
|
module TopModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
|
module RefModule (
input clk,
input [7:0] in,
output reg [7:0] pedge
);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in;
pedge <= in & ~d_last;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output reg [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
@(posedge clk);
wavedrom_start("");
repeat(2) @(posedge clk);
in <= 1;
repeat(4) @(posedge clk);
in <= 0;
repeat(4) @(negedge clk);
in <= 6;
repeat(2) @(negedge clk);
in <= 0;
repeat(2) @(posedge clk);
wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_pedge;
int errortime_pedge;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [7:0] pedge_ref;
logic [7:0] pedge_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,pedge_ref,pedge_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.clk,
.in,
.pedge(pedge_ref) );
TopModule top_module1 (
.clk,
.in,
.pedge(pedge_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_pedge) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "pedge", stats1.errors_pedge, stats1.errortime_pedge);
else $display("Hint: Output '%s' has no mismatches.", "pedge");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { pedge_ref } === ( { pedge_ref } ^ { pedge_dut } ^ { pedge_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (pedge_ref !== ( pedge_ref ^ pedge_dut ^ pedge_ref ))
begin if (stats1.errors_pedge == 0) stats1.errortime_pedge = $time;
stats1.errors_pedge = stats1.errors_pedge+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob055_conditional |
Given four unsigned numbers, find the minimum. Unsigned numbers can be
compared with standard comparison operators (a < b).
module TopModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
|
module TopModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
|
module RefModule (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output reg [7:0] min
);
always_comb begin
min = a;
if (min > b) min = b;
if (min > c) min = c;
if (min > d) min = d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} <= {8'h1, 8'h2, 8'h3, 8'h4};
@(negedge clk);
wavedrom_start();
@(posedge clk) {a,b,c,d} <= {8'h1, 8'h2, 8'h3, 8'h4};
@(posedge clk) {a,b,c,d} <= {8'h11, 8'h2, 8'h3, 8'h4};
@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h3, 8'h4};
@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h13, 8'h4};
@(posedge clk) {a,b,c,d} <= {8'h11, 8'h12, 8'h13, 8'h14};
@(negedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_min;
int errortime_min;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] a;
logic [7:0] b;
logic [7:0] c;
logic [7:0] d;
logic [7:0] min_ref;
logic [7:0] min_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,min_ref,min_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.min(min_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.min(min_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_min) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "min", stats1.errors_min, stats1.errortime_min);
else $display("Hint: Output '%s' has no mismatches.", "min");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { min_ref } === ( { min_ref } ^ { min_dut } ^ { min_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (min_ref !== ( min_ref ^ min_dut ^ min_ref ))
begin if (stats1.errors_min == 0) stats1.errortime_min = $time;
stats1.errors_min = stats1.errors_min+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob056_ece241_2013_q7 |
A JK flip-flop has the below truth table. Note: Qold is the output of the
flip-flop before the positive clock edge.
J | K | Q
0 | 0 | Qold
0 | 1 | 0
1 | 0 | 1
1 | 1 | ~Qold
module TopModule (
input clk,
input j,
input k,
output reg Q
);
|
module TopModule (
input clk,
input j,
input k,
output reg Q
);
|
module RefModule (
input clk,
input j,
input k,
output reg Q
);
always @(posedge clk)
Q <= j&~Q | ~k&Q;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic j, k,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{j,k} <= 1;
@(negedge clk) wavedrom_start();
@(posedge clk) {j,k} <= 2'h1;
@(posedge clk) {j,k} <= 2'h2;
@(posedge clk) {j,k} <= 2'h3;
@(posedge clk) {j,k} <= 2'h3;
@(posedge clk) {j,k} <= 2'h3;
@(posedge clk) {j,k} <= 2'h0;
@(posedge clk) {j,k} <= 2'h0;
@(posedge clk) {j,k} <= 2'h0;
@(posedge clk) {j,k} <= 2'h2;
@(posedge clk) {j,k} <= 2'h2;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk)
{j,k} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Q;
int errortime_Q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic j;
logic k;
logic Q_ref;
logic Q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,Q_ref,Q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.j,
.k );
RefModule good1 (
.clk,
.j,
.k,
.Q(Q_ref) );
TopModule top_module1 (
.clk,
.j,
.k,
.Q(Q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Q", stats1.errors_Q, stats1.errortime_Q);
else $display("Hint: Output '%s' has no mismatches.", "Q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))
begin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;
stats1.errors_Q = stats1.errors_Q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob057_kmap2 |
Implement the circuit described by the Karnaugh map below.
ab
cd 00 01 11 10
00 | 1 | 1 | 0 | 1 |
01 | 1 | 0 | 0 | 1 |
11 | 0 | 1 | 1 | 1 |
10 | 1 | 1 | 0 | 0 |
module TopModule (
input a,
input b,
input c,
input d,
output out
);
|
module TopModule (
input a,
input b,
input c,
input d,
output out
);
|
module RefModule (
input a,
input b,
input c,
input d,
output out
);
assign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c,d} <= 4'b0;
wavedrom_start();
repeat(16) @(posedge clk)
{a,b,c,d} <= count++;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{d,c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob058_alwaysblock2 |
Build an XOR gate three ways, using an assign statement (output
out_assign), a combinational always block (output out_always_comb), and a
clocked always block (output out_always_ff). Note that the clocked always
block produces a different circuit from the other two: There is a flip-
flop so the output is delayed.
module TopModule (
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
|
module TopModule (
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
|
module RefModule (
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("XOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_always_comb;
int errortime_out_always_comb;
int errors_out_always_ff;
int errortime_out_always_ff;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_assign_ref;
logic out_assign_dut;
logic out_always_comb_ref;
logic out_always_comb_dut;
logic out_always_ff_ref;
logic out_always_ff_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,out_assign_ref,out_assign_dut,out_always_comb_ref,out_always_comb_dut,out_always_ff_ref,out_always_ff_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.clk,
.a,
.b,
.out_assign(out_assign_ref),
.out_always_comb(out_always_comb_ref),
.out_always_ff(out_always_ff_ref) );
TopModule top_module1 (
.clk,
.a,
.b,
.out_assign(out_assign_dut),
.out_always_comb(out_always_comb_dut),
.out_always_ff(out_always_ff_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_always_comb) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always_comb", stats1.errors_out_always_comb, stats1.errortime_out_always_comb);
else $display("Hint: Output '%s' has no mismatches.", "out_always_comb");
if (stats1.errors_out_always_ff) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always_ff", stats1.errors_out_always_ff, stats1.errortime_out_always_ff);
else $display("Hint: Output '%s' has no mismatches.", "out_always_ff");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } === ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ^ { out_assign_dut, out_always_comb_dut, out_always_ff_dut } ^ { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_always_comb_ref !== ( out_always_comb_ref ^ out_always_comb_dut ^ out_always_comb_ref ))
begin if (stats1.errors_out_always_comb == 0) stats1.errortime_out_always_comb = $time;
stats1.errors_out_always_comb = stats1.errors_out_always_comb+1'b1; end
if (out_always_ff_ref !== ( out_always_ff_ref ^ out_always_ff_dut ^ out_always_ff_ref ))
begin if (stats1.errors_out_always_ff == 0) stats1.errortime_out_always_ff = $time;
stats1.errors_out_always_ff = stats1.errors_out_always_ff+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob059_wire4 |
Create a module with 3 inputs and 4 outputs that behaves like wires that
makes these connections:
a -> w
b -> x
b -> y
c -> z
module TopModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
|
module TopModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
|
module RefModule (
input a,
input b,
input c,
output w,
output x,
output y,
output z
);
assign {w,x,y,z} = {a,b,b,c};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a, b, c,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
{a,b,c} <= $random;
initial begin
@(negedge clk) wavedrom_start();
repeat(8) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_w;
int errortime_w;
int errors_x;
int errortime_x;
int errors_y;
int errortime_y;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic w_ref;
logic w_dut;
logic x_ref;
logic x_dut;
logic y_ref;
logic y_dut;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c );
RefModule good1 (
.a,
.b,
.c,
.w(w_ref),
.x(x_ref),
.y(y_ref),
.z(z_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.w(w_dut),
.x(x_dut),
.y(y_dut),
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_w) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "w", stats1.errors_w, stats1.errortime_w);
else $display("Hint: Output '%s' has no mismatches.", "w");
if (stats1.errors_x) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "x", stats1.errors_x, stats1.errortime_x);
else $display("Hint: Output '%s' has no mismatches.", "x");
if (stats1.errors_y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "y", stats1.errors_y, stats1.errortime_y);
else $display("Hint: Output '%s' has no mismatches.", "y");
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (w_ref !== ( w_ref ^ w_dut ^ w_ref ))
begin if (stats1.errors_w == 0) stats1.errortime_w = $time;
stats1.errors_w = stats1.errors_w+1'b1; end
if (x_ref !== ( x_ref ^ x_dut ^ x_ref ))
begin if (stats1.errors_x == 0) stats1.errortime_x = $time;
stats1.errors_x = stats1.errors_x+1'b1; end
if (y_ref !== ( y_ref ^ y_dut ^ y_ref ))
begin if (stats1.errors_y == 0) stats1.errortime_y = $time;
stats1.errors_y = stats1.errors_y+1'b1; end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob060_m2014_q4k |
Implement a shift register with four D flops. Reset is active-low
synchronous resettable.
module TopModule (
input clk,
input resetn,
input in,
output out
);
|
module TopModule (
input clk,
input resetn,
input in,
output out
);
|
module RefModule (
input clk,
input resetn,
input in,
output out
);
reg [3:0] sr;
always @(posedge clk) begin
if (~resetn)
sr <= '0;
else
sr <= {sr[2:0], in};
end
assign out = sr[3];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in, resetn
);
initial begin
repeat(100) @(posedge clk) begin
in <= $random;
resetn <= ($random & 7) != 0;
end
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
resetn <= ($random & 7) != 0;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic resetn;
logic in;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.resetn,
.in );
RefModule good1 (
.clk,
.resetn,
.in,
.out(out_ref) );
TopModule top_module1 (
.clk,
.resetn,
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob061_2014_q4a |
Consider an n-bit shift register circuit. Inputs E are for enabling
shift, R for value to load, L is asserted when it should load, and w is
the input to the first stage of the shift register. Write a Verilog
module named top_module for one stage of this circuit, including both the
flip-flop and multiplexers.
module TopModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
|
module TopModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
|
module RefModule (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic w, R, E, L
);
initial begin
repeat(200) @(posedge clk, negedge clk) begin
{w,R,E,L} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Q;
int errortime_Q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic w;
logic R;
logic E;
logic L;
logic Q_ref;
logic Q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,w,R,E,L,Q_ref,Q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.w,
.R,
.E,
.L );
RefModule good1 (
.clk,
.w,
.R,
.E,
.L,
.Q(Q_ref) );
TopModule top_module1 (
.clk,
.w,
.R,
.E,
.L,
.Q(Q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Q", stats1.errors_Q, stats1.errortime_Q);
else $display("Hint: Output '%s' has no mismatches.", "Q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))
begin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;
stats1.errors_Q = stats1.errors_Q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob062_bugs_mux2 |
Find the bug and fix this 8-bit wide 2-to-1 mux.
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output out );
assign out = (~sel & a) | (sel & b);
endmodule
module TopModule (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
|
module TopModule (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
|
module RefModule (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic sel,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel} <= '0;
@(negedge clk) wavedrom_start("");
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a, b} <= {8'hff, 8'h00}; sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b1;
@(posedge clk, negedge clk) sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b1;
@(posedge clk, negedge clk) sel <= 1'b1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic sel;
logic [7:0] a;
logic [7:0] b;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,sel,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.sel,
.a,
.b );
RefModule good1 (
.sel,
.a,
.b,
.out(out_ref) );
TopModule top_module1 (
.sel,
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob063_review2015_shiftcount |
Build a four-bit shift register that also acts as a down counter. Data is
shifted in most-significant-bit first when shift_ena is 1. The number
currently in the shift register is decremented when count_ena is 1. Since
the full system doesn't ever use shift_ena and count_ena together, it
does not matter what your circuit does if both control inputs are 1 (This
mainly means that it doesn't matter which case gets higher priority).
module TopModule (
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q
);
|
module TopModule (
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q
);
|
module RefModule (
input clk,
input shift_ena,
input count_ena,
input data,
output reg [3:0] q
);
always @(posedge clk) begin
if (shift_ena)
q <= { q[2:0], data };
else if (count_ena)
q <= q - 1'b1;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg shift_ena, count_ena, data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
data <= 0;
shift_ena <= 1;
count_ena <= 0;
repeat(5) @(posedge clk);
data <= 1;
shift_ena <= 0;
count_ena <= 0;
@(posedge clk);
wavedrom_start("Shift mode");
@(posedge clk) shift_ena <= 1;
repeat(2) @(posedge clk) shift_ena <= 0;
@(posedge clk) shift_ena <= 1;
repeat(4) @(posedge clk);
@(posedge clk) data <= 0;
repeat(4) @(posedge clk);
wavedrom_stop();
data <= 1;
shift_ena <= 1;
repeat(4) @(posedge clk);
shift_ena <= 0;
wavedrom_start("Count mode");
@(posedge clk) count_ena <= 1;
repeat(2) @(posedge clk) count_ena <= 0;
@(posedge clk) count_ena <= 1;
repeat(4) @(posedge clk);
@(posedge clk) data <= 0;
repeat(4) @(posedge clk);
wavedrom_stop();
repeat(2000) @(posedge clk, negedge clk) begin
{shift_ena, count_ena} <= $unsigned($random) % 3;
data <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic shift_ena;
logic count_ena;
logic data;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,shift_ena,count_ena,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.shift_ena,
.count_ena,
.data );
RefModule good1 (
.clk,
.shift_ena,
.count_ena,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.shift_ena,
.count_ena,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob064_vector3 |
Given several input vectors, concatenate them together then split them up
into several output vectors. There are six 5-bit input vectors: a, b, c,
d, e, and f, for a total of 30 bits of input. There are four 8-bit output
vectors: w, x, y, and z, for 32 bits of output. The output should be a
concatenation of the input vectors followed by two 1 bits (the two 1 bits
should be in the LSB positions).
module TopModule (
input [4:0] a,
input [4:0] b,
input [4:0] c,
input [4:0] d,
input [4:0] e,
input [4:0] f,
output [7:0] w,
output [7:0] x,
output [7:0] y,
output [7:0] z
);
|
module TopModule (
input [4:0] a,
input [4:0] b,
input [4:0] c,
input [4:0] d,
input [4:0] e,
input [4:0] f,
output [7:0] w,
output [7:0] x,
output [7:0] y,
output [7:0] z
);
|
module RefModule (
input [4:0] a,
input [4:0] b,
input [4:0] c,
input [4:0] d,
input [4:0] e,
input [4:0] f,
output [7:0] w,
output [7:0] x,
output [7:0] y,
output [7:0] z
);
assign { w,x,y,z} = {a,b,c,d,e,f,2'b11};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [4:0] a,b,c,d,e,f,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("");
@(posedge clk) {a,b,c,d,e,f} <= '0;
@(posedge clk) {a,b,c,d,e,f} <= 1;
@(posedge clk) {a,b,c,d,e,f} <= 2;
@(posedge clk) {a,b,c,d,e,f} <= 4;
@(posedge clk) {a,b,c,d,e,f} <= 8;
@(posedge clk) {a,b,c,d,e,f} <= 'h10;
@(posedge clk) {a,b,c,d,e,f} <= 'h20;
@(posedge clk) {a,b,c,d,e,f} <= 'h40;
@(posedge clk) {a,b,c,d,e,f} <= 'h80;
@(posedge clk) {a,b,c,d,e,f} <= 'h100;
@(posedge clk) {a,b,c,d,e,f} <= 'h200;
@(posedge clk) {a,b,c,d,e,f} <= 'h400;
@(posedge clk) {a,b,c,d,e,f} <= {5'h1f, 5'h0, 5'h1f, 5'h0, 5'h1f, 5'h0};
@(negedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e,f} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_w;
int errortime_w;
int errors_x;
int errortime_x;
int errors_y;
int errortime_y;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [4:0] a;
logic [4:0] b;
logic [4:0] c;
logic [4:0] d;
logic [4:0] e;
logic [4:0] f;
logic [7:0] w_ref;
logic [7:0] w_dut;
logic [7:0] x_ref;
logic [7:0] x_dut;
logic [7:0] y_ref;
logic [7:0] y_dut;
logic [7:0] z_ref;
logic [7:0] z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,w_ref,w_dut,x_ref,x_dut,y_ref,y_dut,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e,
.f );
RefModule good1 (
.a,
.b,
.c,
.d,
.e,
.f,
.w(w_ref),
.x(x_ref),
.y(y_ref),
.z(z_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.e,
.f,
.w(w_dut),
.x(x_dut),
.y(y_dut),
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_w) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "w", stats1.errors_w, stats1.errortime_w);
else $display("Hint: Output '%s' has no mismatches.", "w");
if (stats1.errors_x) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "x", stats1.errors_x, stats1.errortime_x);
else $display("Hint: Output '%s' has no mismatches.", "x");
if (stats1.errors_y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "y", stats1.errors_y, stats1.errortime_y);
else $display("Hint: Output '%s' has no mismatches.", "y");
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { w_ref, x_ref, y_ref, z_ref } === ( { w_ref, x_ref, y_ref, z_ref } ^ { w_dut, x_dut, y_dut, z_dut } ^ { w_ref, x_ref, y_ref, z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (w_ref !== ( w_ref ^ w_dut ^ w_ref ))
begin if (stats1.errors_w == 0) stats1.errortime_w = $time;
stats1.errors_w = stats1.errors_w+1'b1; end
if (x_ref !== ( x_ref ^ x_dut ^ x_ref ))
begin if (stats1.errors_x == 0) stats1.errortime_x = $time;
stats1.errors_x = stats1.errors_x+1'b1; end
if (y_ref !== ( y_ref ^ y_dut ^ y_ref ))
begin if (stats1.errors_y == 0) stats1.errortime_y = $time;
stats1.errors_y = stats1.errors_y+1'b1; end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob065_7420 |
The 7400-series integrated circuits are a series of digital chips with a
few gates each. The 7420 is a chip with two 4-input NAND gates.
Create a module with the same functionality as the 7420 chip. It has 8
inputs and 2 outputs.
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
|
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
|
module RefModule (
input p1a,
input p1b,
input p1c,
input p1d,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = ~&( {p1a, p1b, p1c, p1d} );
assign p2y = ~&( {p2a, p2b, p2c, p2d} );
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg p1a, p1b, p1c, p1d,
output reg p2a, p2b, p2c, p2d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{p1a,p1b,p1c,p1d} <= 4'h0;
{p2a,p2b,p2c,p2d} <= 4'h0;
wavedrom_start("Two NAND gates");
repeat(20) @(posedge clk) begin
{p1a,p1b,p1c,p1d} <= count;
{p2a,p2b,p2c,p2d} <= count+1;
count = count + 1;
end
wavedrom_stop();
repeat(200) @(posedge clk,negedge clk) begin
{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_p1y;
int errortime_p1y;
int errors_p2y;
int errortime_p2y;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic p1a;
logic p1b;
logic p1c;
logic p1d;
logic p2a;
logic p2b;
logic p2c;
logic p2d;
logic p1y_ref;
logic p1y_dut;
logic p2y_ref;
logic p2y_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.p1a,
.p1b,
.p1c,
.p1d,
.p2a,
.p2b,
.p2c,
.p2d );
RefModule good1 (
.p1a,
.p1b,
.p1c,
.p1d,
.p2a,
.p2b,
.p2c,
.p2d,
.p1y(p1y_ref),
.p2y(p2y_ref) );
TopModule top_module1 (
.p1a,
.p1b,
.p1c,
.p1d,
.p2a,
.p2b,
.p2c,
.p2d,
.p1y(p1y_dut),
.p2y(p2y_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_p1y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "p1y", stats1.errors_p1y, stats1.errortime_p1y);
else $display("Hint: Output '%s' has no mismatches.", "p1y");
if (stats1.errors_p2y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "p2y", stats1.errors_p2y, stats1.errortime_p2y);
else $display("Hint: Output '%s' has no mismatches.", "p2y");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))
begin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;
stats1.errors_p1y = stats1.errors_p1y+1'b1; end
if (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))
begin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;
stats1.errors_p2y = stats1.errors_p2y+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob066_edgecapture |
For each bit in a 32-bit vector, capture when the input signal changes
from 1 in one clock cycle to 0 the next. "Capture" means that the output
will remain 1 until the register is reset (active high synchronous
reset).
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
|
module TopModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
|
module RefModule (
input clk,
input reset,
input [31:0] in,
output reg [31:0] out
);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output reg [31:0] in,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
reset <= 1;
@(posedge clk);
reset <= 1;
in = 0;
@(negedge clk) wavedrom_start("Example");
repeat(1) @(posedge clk);
reset = 0;
@(posedge clk) in = 32'h2;
repeat(4) @(posedge clk);
in = 32'he;
repeat(2) @(posedge clk);
in = 0;
@(posedge clk) in = 32'h2;
repeat(2) @(posedge clk);
reset = 1;
@(posedge clk);
reset = 0; in = 0;
repeat(3) @(posedge clk);
@(negedge clk) wavedrom_stop();
@(negedge clk) wavedrom_start("");
repeat(2) @(posedge clk);
in <= 1;
repeat(2) @(posedge clk);
in <= 0;
repeat(2) @(negedge clk);
in <= 6;
repeat(1) @(negedge clk);
in <= 0;
repeat(2) @(posedge clk);
in <= 32'h10;
repeat(2) @(posedge clk);
reset <= 1;
repeat(1) @(posedge clk);
in <= 32'h0;
repeat(1) @(posedge clk);
reset <= 0;
repeat(1) @(posedge clk);
reset <= 1;
in <= 32'h20;
repeat(1) @(posedge clk);
reset <= 0;
in <= 32'h00;
repeat(2) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 15);
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [31:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.in );
RefModule good1 (
.clk,
.reset,
.in,
.out(out_ref) );
TopModule top_module1 (
.clk,
.reset,
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob067_countslow |
Build a decade counter that counts from 0 through 9, inclusive, with a
period of 10. The reset input is active high synchronous, and should
reset the counter to 0. We want to be able to pause the counter rather
than always incrementing every clock cycle, so the "slowena" input if
high indicates when the counter should increment.
module TopModule (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
|
module TopModule (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
|
module RefModule (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
always @(posedge clk)
if (reset)
q <= 0;
else if (slowena) begin
if (q == 9)
q <= 0;
else
q <= q+1;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg slowena,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg hint1;
initial begin
reset <= 1;
slowena <= 1;
wavedrom_start("Synchronous reset and counting.");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk);
//wavedrom_start("Testing.");
reset <= 1;
@(posedge clk);
reset <= 0;
repeat(9) @(posedge clk);
slowena <= 0;
@(negedge clk) hint1 = tb_match;
repeat(3) @(posedge clk);
if (hint1 && !tb_match) begin
$display ("Hint: What is supposed to happen when the counter is 9 and not enabled?");
end
//wavedrom_stop();
slowena <= 1;
reset <= 1;
@(posedge clk);
reset <= 0;
wavedrom_start("Enable/disable");
repeat(15) @(posedge clk) slowena <= !($random & 1);
wavedrom_stop();
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
slowena <= !($random&3);
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic slowena;
logic reset;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,slowena,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.slowena,
.reset );
RefModule good1 (
.clk,
.slowena,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.slowena,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob068_countbcd |
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is
encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit,
etc. For digits [3:1], also output an enable signal indicating when each
of the upper three digits should be incremented. Include a synchronous
active-high reset.
module TopModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
|
module TopModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
|
module RefModule (
input clk,
input reset,
output [3:1] ena,
output reg [15:0] q
);
wire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1};
assign ena = enable[3:1];
always @(posedge clk)
for (int i=0;i<4;i++) begin
if (reset || (q[i*4 +:4] == 9 && enable[i]))
q[i*4 +:4] <= 0;
else if (enable[i])
q[i*4 +:4] <= q[i*4 +:4]+1;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
reset_test();
repeat(2) @(posedge clk);
@(negedge clk);
wavedrom_start("Counting");
repeat(12) @(posedge clk);
@(negedge clk);
wavedrom_stop();
repeat(71) @(posedge clk);
@(negedge clk) wavedrom_start("100 rollover");
repeat(16) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk)
reset <= !($random & 31);
repeat(19590) @(posedge clk);
reset <= 1'b1;
repeat(5) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_ena;
int errortime_ena;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [3:1] ena_ref;
logic [3:1] ena_dut;
logic [15:0] q_ref;
logic [15:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena_ref,ena_dut,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.ena(ena_ref),
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.ena(ena_dut),
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_ena) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "ena", stats1.errors_ena, stats1.errortime_ena);
else $display("Hint: Output '%s' has no mismatches.", "ena");
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { ena_ref, q_ref } === ( { ena_ref, q_ref } ^ { ena_dut, q_dut } ^ { ena_ref, q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (ena_ref !== ( ena_ref ^ ena_dut ^ ena_ref ))
begin if (stats1.errors_ena == 0) stats1.errortime_ena = $time;
stats1.errors_ena = stats1.errors_ena+1'b1; end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob069_truthtable1 |
Create a combinational circuit that implements the truth table.
x3 | x2 | x1 | f
0 | 0 | 0 | 0
0 | 0 | 1 | 0
0 | 1 | 0 | 1
0 | 1 | 1 | 1
1 | 0 | 0 | 0
1 | 0 | 1 | 1
1 | 1 | 0 | 0
1 | 1 | 1 | 1
module TopModule (
input x3,
input x2,
input x1,
output f
);
|
module TopModule (
input x3,
input x2,
input x1,
output f
);
|
module RefModule (
input x3,
input x2,
input x1,
output f
);
assign f = ( ~x3 & x2 & ~x1 ) |
( ~x3 & x2 & x1 ) |
( x3 & ~x2 & x1 ) |
( x3 & x2 & x1 ) ;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg x3, x2, x1,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{x3, x2, x1} <= 3'h7;
@(negedge clk) wavedrom_start("All 8 input combinations");
repeat(8) @(posedge clk) {x3, x2, x1} <= {x3, x2, x1} + 1'b1;
@(negedge clk) wavedrom_stop();
repeat(40) @(posedge clk, negedge clk);
{x3, x2, x1} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_f;
int errortime_f;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x3;
logic x2;
logic x1;
logic f_ref;
logic f_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x3,x2,x1,f_ref,f_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x3,
.x2,
.x1 );
RefModule good1 (
.x3,
.x2,
.x1,
.f(f_ref) );
TopModule top_module1 (
.x3,
.x2,
.x1,
.f(f_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_f) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "f", stats1.errors_f, stats1.errortime_f);
else $display("Hint: Output '%s' has no mismatches.", "f");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (f_ref !== ( f_ref ^ f_dut ^ f_ref ))
begin if (stats1.errors_f == 0) stats1.errortime_f = $time;
stats1.errors_f = stats1.errors_f+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob070_ece241_2013_q2 |
A single-output digital system with four inputs (a,b,c,d) generates a
logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1,
4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers
3, 8, 11, and 12 never occur in this system. For example, 7 corresponds
to a,b,c,d being set to 0,1,1,1, respectively. Determine the output
out_sop in minimum sum-of-products form, and the output out_pos in
minimum product-of-sums form.
module TopModule (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
|
module TopModule (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
|
module RefModule (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
wire pos0, pos1;
assign out_sop = c&d | ~a&~b&c;
assign pos0 = c & (~b|d)&(~a|b);
assign pos1 = c & (~b|d)&(~a|d);
assign out_pos = (pos0 == pos1) ? pos0 : 1'bx;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
bit fail = 0;
bit fail1 = 0;
always @(posedge clk, negedge clk)
if (!tb_match)
fail = 1;
initial begin
@(posedge clk) {a,b,c,d} <= 0;
@(posedge clk) {a,b,c,d} <= 1;
@(posedge clk) {a,b,c,d} <= 2;
@(posedge clk) {a,b,c,d} <= 4;
@(posedge clk) {a,b,c,d} <= 5;
@(posedge clk) {a,b,c,d} <= 6;
@(posedge clk) {a,b,c,d} <= 7;
@(posedge clk) {a,b,c,d} <= 9;
@(posedge clk) {a,b,c,d} <= 10;
@(posedge clk) {a,b,c,d} <= 13;
@(posedge clk) {a,b,c,d} <= 14;
@(posedge clk) {a,b,c,d} <= 15;
@(posedge clk) fail1 = fail;
//@(negedge clk) wavedrom_start();
for (int i=0;i<16;i++)
@(posedge clk)
{a,b,c,d} <= i;
//@(negedge clk) wavedrom_stop();
repeat(50) @(posedge clk, negedge clk)
{a,b,c,d} <= $random;
if (fail && ~fail1)
$display("Hint: Your circuit passes on the 12 required input combinations, but doesn't match the don't-care cases. Are you using minimal SOP and POS?");
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_sop;
int errortime_out_sop;
int errors_out_pos;
int errortime_out_pos;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_sop_ref;
logic out_sop_dut;
logic out_pos_ref;
logic out_pos_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_sop_ref,out_sop_dut,out_pos_ref,out_pos_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.out_sop(out_sop_ref),
.out_pos(out_pos_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.out_sop(out_sop_dut),
.out_pos(out_pos_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_sop) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_sop", stats1.errors_out_sop, stats1.errortime_out_sop);
else $display("Hint: Output '%s' has no mismatches.", "out_sop");
if (stats1.errors_out_pos) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_pos", stats1.errors_out_pos, stats1.errortime_out_pos);
else $display("Hint: Output '%s' has no mismatches.", "out_pos");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_sop_ref, out_pos_ref } === ( { out_sop_ref, out_pos_ref } ^ { out_sop_dut, out_pos_dut } ^ { out_sop_ref, out_pos_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_sop_ref !== ( out_sop_ref ^ out_sop_dut ^ out_sop_ref ))
begin if (stats1.errors_out_sop == 0) stats1.errortime_out_sop = $time;
stats1.errors_out_sop = stats1.errors_out_sop+1'b1; end
if (out_pos_ref !== ( out_pos_ref ^ out_pos_dut ^ out_pos_ref ))
begin if (stats1.errors_out_pos == 0) stats1.errortime_out_pos = $time;
stats1.errors_out_pos = stats1.errors_out_pos+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob071_always_casez |
Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the
output should report the first (least significant) bit in the vector that
is 1. Report zero if the input vector has no bits that are high. For
example, the input 8'b10010000 should output 3'd4, because bit[4] is
first bit that is high.
module TopModule (
input [7:0] in,
output reg [2:0] pos
);
|
module TopModule (
input [7:0] in,
output reg [2:0] pos
);
|
module RefModule (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4;
8'bzz1zzzzz: pos = 3'h5;
8'bz1zzzzzz: pos = 3'h6;
8'b1zzzzzzz: pos = 3'h7;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Priority encoder");
@(posedge clk) in <= 8'h1;
repeat(8) @(posedge clk) in <= in << 1;
in <= 8'h10;
repeat(8) @(posedge clk) in <= in + 1;
@(negedge clk) wavedrom_stop();
repeat(50) @(posedge clk, negedge clk) begin
in <= $urandom;
end
repeat(260) @(posedge clk, negedge clk) begin
in <= in + 1;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_pos;
int errortime_pos;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [2:0] pos_ref;
logic [2:0] pos_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.pos(pos_ref) );
TopModule top_module1 (
.in,
.pos(pos_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_pos) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "pos", stats1.errors_pos, stats1.errortime_pos);
else $display("Hint: Output '%s' has no mismatches.", "pos");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))
begin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;
stats1.errors_pos = stats1.errors_pos+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob072_thermostat |
A heating/cooling thermostat controls both a heater (during winter) and
an air conditioner (during summer). Implement a circuit that will turn on
and off the heater, air conditioning, and blower fan as appropriate. The
thermostat can be in one of two modes: heating (mode = 1) and cooling
(mode = 0). In heating mode, turn the heater on when it is too cold
(too_cold = 1) but do not use the air conditioner. In cooling mode, turn
the air conditioner on when it is too hot (too_hot = 1), but do not turn
on the heater. When the heater or air conditioner are on, also turn on
the fan to circulate the air. In addition, the user can also request the
fan to turn on (fan_on = 1), even if the heater and air conditioner are
off.
module TopModule (
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
|
module TopModule (
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
|
module RefModule (
input mode,
input too_cold,
input too_hot,
input fan_on,
output heater,
output aircon,
output fan
);
assign fan = (mode ? too_cold : too_hot) | fan_on;
assign heater = (mode & too_cold);
assign aircon = (~mode & too_hot);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg too_cold, too_hot, mode, fan_on,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{too_cold, too_hot, mode, fan_on} <= 4'b0010;
@(negedge clk);
wavedrom_start("Winter");
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1010;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1011;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0011;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0010;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0110;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1110;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0111;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1111;
@(negedge clk) wavedrom_stop();
{too_cold, too_hot, mode, fan_on} <= 4'b0000;
@(negedge clk);
wavedrom_start("Summer");
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0100;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0101;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0001;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b0000;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1000;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1100;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1001;
@(posedge clk) {too_cold, too_hot, mode, fan_on} <= 4'b1101;
@(negedge clk) wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) {too_cold, too_hot, mode, fan_on} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_heater;
int errortime_heater;
int errors_aircon;
int errortime_aircon;
int errors_fan;
int errortime_fan;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic mode;
logic too_cold;
logic too_hot;
logic fan_on;
logic heater_ref;
logic heater_dut;
logic aircon_ref;
logic aircon_dut;
logic fan_ref;
logic fan_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,mode,too_cold,too_hot,fan_on,heater_ref,heater_dut,aircon_ref,aircon_dut,fan_ref,fan_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.mode,
.too_cold,
.too_hot,
.fan_on );
RefModule good1 (
.mode,
.too_cold,
.too_hot,
.fan_on,
.heater(heater_ref),
.aircon(aircon_ref),
.fan(fan_ref) );
TopModule top_module1 (
.mode,
.too_cold,
.too_hot,
.fan_on,
.heater(heater_dut),
.aircon(aircon_dut),
.fan(fan_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_heater) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "heater", stats1.errors_heater, stats1.errortime_heater);
else $display("Hint: Output '%s' has no mismatches.", "heater");
if (stats1.errors_aircon) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "aircon", stats1.errors_aircon, stats1.errortime_aircon);
else $display("Hint: Output '%s' has no mismatches.", "aircon");
if (stats1.errors_fan) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "fan", stats1.errors_fan, stats1.errortime_fan);
else $display("Hint: Output '%s' has no mismatches.", "fan");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { heater_ref, aircon_ref, fan_ref } === ( { heater_ref, aircon_ref, fan_ref } ^ { heater_dut, aircon_dut, fan_dut } ^ { heater_ref, aircon_ref, fan_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (heater_ref !== ( heater_ref ^ heater_dut ^ heater_ref ))
begin if (stats1.errors_heater == 0) stats1.errortime_heater = $time;
stats1.errors_heater = stats1.errors_heater+1'b1; end
if (aircon_ref !== ( aircon_ref ^ aircon_dut ^ aircon_ref ))
begin if (stats1.errors_aircon == 0) stats1.errortime_aircon = $time;
stats1.errors_aircon = stats1.errors_aircon+1'b1; end
if (fan_ref !== ( fan_ref ^ fan_dut ^ fan_ref ))
begin if (stats1.errors_fan == 0) stats1.errortime_fan = $time;
stats1.errors_fan = stats1.errors_fan+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob073_dff16e |
Create 16 D flip-flops. It's sometimes useful to only modify parts of a
group of flip-flops. The byte-enable inputs control whether each byte of
the 16 registers should be written to on that cycle. byteena[1] controls
the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset. All DFFs should be triggered
by the positive edge of clk.
module TopModule (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
|
module TopModule (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
|
module RefModule (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
always @(posedge clk) begin
if (!resetn)
q <= 0;
else begin
if (byteena[0])
q[7:0] <= d[7:0];
if (byteena[1])
q[15:8] <= d[15:8];
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [15:0] d, output reg [1:0] byteena,
output reg resetn,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign resetn = ~reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
reset <= 1;
byteena <= 2'b11;
d <= 16'habcd;
@(posedge clk);
wavedrom_start("Synchronous active-low reset");
reset_test(0);
repeat(2) @(posedge clk);
wavedrom_stop();
@(posedge clk);
byteena <= 2'b11;
d <= $random;
@(posedge clk);
@(negedge clk);
wavedrom_start("DFF with byte enables");
repeat(10) @(posedge clk) begin
d <= $random;
byteena <= byteena + 1;
end
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
byteena[0] <= ($random & 3) != 0;
byteena[1] <= ($random & 3) != 0;
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic resetn;
logic [1:0] byteena;
logic [15:0] d;
logic [15:0] q_ref;
logic [15:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,byteena,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.resetn,
.byteena,
.d );
RefModule good1 (
.clk,
.resetn,
.byteena,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.resetn,
.byteena,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob074_ece241_2014_q4 |
Given the finite state machine circuit described below, assume that the D
flip-flops are initially reset to zero before the machine begins.
Build this circuit in Verilog.
Input x goes to three different two-input gates: a XOR, an AND, and a OR
gate. Each of the three gates is connected to the input of a D flip-flop
and then the flip-flop outputs all go to a three-input XNOR, whose output
is Z. The second input of the XOR is its corresponding flip-flop's
output, the second input of the AND is its corresponding flip-flop's
complemented output, and finally the second input of the OR is its
corresponding flip-flop's complementary output.
module TopModule (
input clk,
input x,
output z
);
|
module TopModule (
input clk,
input x,
output z
);
|
module RefModule (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
x <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
x <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x );
RefModule good1 (
.clk,
.x,
.z(z_ref) );
TopModule top_module1 (
.clk,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob075_counter_2bc |
Build a two-bit saturating counter. The counter increments (up to a
maximum of 3) when train_valid = 1 and train_taken = 1. It decrements
(down to a minimum of 0) when train_valid = 1 and train_taken = 0. When
not training (train_valid = 0), the counter keeps its value unchanged.
areset is a positive edge triggered asynchronous reset that resets the
counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit
counter value.
module TopModule (
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
|
module TopModule (
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
|
module RefModule (
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
if(state < 3 && train_taken)
state <= state + 1;
else if(state > 0 && !train_taken)
state <= state - 1;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen(
input clk,
output logic areset,
output logic train_valid,
output train_taken,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
output int wavedrom_hide_after_time
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
assign areset = reset;
logic train_taken_r;
assign train_taken = train_valid ? train_taken_r : 1'bx;
initial begin
@(posedge clk);
@(posedge clk) reset <= 1;
@(posedge clk) reset <= 0;
train_taken_r <= 1;
train_valid <= 1;
wavedrom_start("Asynchronous reset");
reset_test(1); // Test for asynchronous reset
wavedrom_stop();
@(posedge clk) reset <= 1;
train_taken_r <= 1;
train_valid <= 0;
@(posedge clk) reset <= 0;
wavedrom_start("Count up, then down");
train_taken_r <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
train_taken_r <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
wavedrom_stop();
repeat(1000) @(posedge clk,negedge clk)
{train_valid, train_taken_r} <= {$urandom} ;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_state;
int errortime_state;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic train_valid;
logic train_taken;
logic [1:0] state_ref;
logic [1:0] state_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,train_valid,train_taken,state_ref,state_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.train_valid,
.train_taken );
RefModule good1 (
.clk,
.areset,
.train_valid,
.train_taken,
.state(state_ref) );
TopModule top_module1 (
.clk,
.areset,
.train_valid,
.train_taken,
.state(state_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "state", stats1.errors_state, stats1.errortime_state);
else $display("Hint: Output '%s' has no mismatches.", "state");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { state_ref } === ( { state_ref } ^ { state_dut } ^ { state_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (state_ref !== ( state_ref ^ state_dut ^ state_ref ))
begin if (stats1.errors_state == 0) stats1.errortime_state = $time;
stats1.errors_state = stats1.errors_state+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob076_always_case |
Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the
corresponding data input. Otherwise, output 0. The data inputs and
outputs are all 4 bits wide.
module TopModule (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
|
module TopModule (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
|
module RefModule (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
);
always @(*) begin
case (sel)
3'h0: out = data0;
3'h1: out = data1;
3'h2: out = data2;
3'h3: out = data3;
3'h4: out = data4;
3'h5: out = data5;
default: out = 4'b0;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [2:0] sel,
output logic [3:0] data0,
output logic [3:0] data1,
output logic [3:0] data2,
output logic [3:0] data3,
output logic [3:0] data4,
output logic [3:0] data5,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
data0 <= 4'ha;
data1 <= 4'hb;
data2 <= 4'hc;
data3 <= 4'hd;
data4 <= 4'he;
data5 <= 4'hf;
{sel} <= 3'b111;
@(negedge clk) wavedrom_start("<b>Sel</b> chooses one of the data inputs");
repeat(8) @(posedge clk) sel <= sel + 1;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk) begin
{data0, data1, data2, data3} <= $urandom;
{data4, data5, sel} <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] sel;
logic [3:0] data0;
logic [3:0] data1;
logic [3:0] data2;
logic [3:0] data3;
logic [3:0] data4;
logic [3:0] data5;
logic [3:0] out_ref;
logic [3:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,sel,data0,data1,data2,data3,data4,data5,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.sel,
.data0,
.data1,
.data2,
.data3,
.data4,
.data5 );
RefModule good1 (
.sel,
.data0,
.data1,
.data2,
.data3,
.data4,
.data5,
.out(out_ref) );
TopModule top_module1 (
.sel,
.data0,
.data1,
.data2,
.data3,
.data4,
.data5,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob077_wire_decl |
Implement the following circuit. Create two intermediate wires (named
anything you want) to connect the AND and OR gates together. Note that
the wire that feeds the NOT gate is really wire `out`, so you do not
necessarily need to declare a third wire here. Notice how wires are
driven by exactly one source (output of a gate), but can feed multiple
inputs.
The circuit is composed of two layers. The first layer, counting from the
input, is two AND gates: one whose input is connected to a and b, and the
second is connected to c and d. The second layer there is an OR gate to
OR the two AND outputs, connected the output 'out'. Additionally, there
is an inverted output 'out_n'.
module TopModule (
input a,
input b,
input c,
input d,
output out,
output out_n
);
|
module TopModule (
input a,
input b,
input c,
input d,
output out,
output out_n
);
|
module RefModule (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire w1, w2;
assign w1 = a&b;
assign w2 = c&d;
assign out = w1|w2;
assign out_n = ~out;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
// hdlbits_prop {len: 5}
module stimulus_gen (
input clk,
output reg a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} = 4'h0;
@(negedge clk);
wavedrom_start("Exhaustive test");
repeat(20) @(posedge clk, negedge clk)
{d,c,b,a} <= {d,c,b,a} + 1'b1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk) begin
{a,b,c,d} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int errors_out_n;
int errortime_out_n;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_ref;
logic out_dut;
logic out_n_ref;
logic out_n_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut,out_n_ref,out_n_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.out(out_ref),
.out_n(out_n_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.out(out_dut),
.out_n(out_n_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
if (stats1.errors_out_n) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_n", stats1.errors_out_n, stats1.errortime_out_n);
else $display("Hint: Output '%s' has no mismatches.", "out_n");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref, out_n_ref } === ( { out_ref, out_n_ref } ^ { out_dut, out_n_dut } ^ { out_ref, out_n_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
if (out_n_ref !== ( out_n_ref ^ out_n_dut ^ out_n_ref ))
begin if (stats1.errors_out_n == 0) stats1.errortime_out_n = $time;
stats1.errors_out_n = stats1.errors_out_n+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob078_dualedge |
A dual-edge triggered flip-flop is triggered on both edges of the clock.
However, FPGAs don't have dual-edge triggered flip-flops, and always
@(posedge clk or negedge clk) is not accepted as a legal sensitivity
list. Build a circuit that functionally behaves like a dual-edge
triggered flip-flop.
module TopModule (
input clk,
input d,
output reg q
);
|
module TopModule (
input clk,
input d,
output reg q
);
|
module RefModule (
input clk,
input d,
output reg q
);
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
reg qp, qn;
always @(posedge clk)
qp <= d;
always @(negedge clk)
qn <= d;
// This causes q to change too early when clk changes. Need delay by
// delta cycle
// assign q = clk ? qp : qn;
always @(*)
q <= clk ? qp : qn;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
d <= 1'b0;
@(negedge clk) wavedrom_start();
repeat(20) @(posedge clk, negedge clk)
d <= $random>>2;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
d <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
RefModule good1 (
.clk,
.d,
.q(q_ref) );
TopModule top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob079_fsm3onehot |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Use the following one-hot
state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state
transition and output logic equations by inspection assuming a one-hot
encoding. Implement only the state transition logic and output logic (the
combinational logic portion) for this state machine.
State | Next state in=0, Next state in=1 | Output
A | A, B | 0
B | C, B | 0
C | A, D | 0
D | C, B | 1
module TopModule (
input in,
input [3:0] state,
output reg [3:0] next_state,
output out
);
|
module TopModule (
input in,
input [3:0] state,
output reg [3:0] next_state,
output out
);
|
module RefModule (
input in,
input [3:0] state,
output reg [3:0] next_state,
output out
);
parameter A=0, B=1, C=2, D=3;
assign next_state[A] = (state[A] | state[C]) & ~in;
assign next_state[B] = (state[A] | state[B] | state[D]) & in;
assign next_state[C] = (state[B] | state[D]) & ~in;
assign next_state[D] = state[C] & in;
assign out = (state[D]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic [3:0] state,
input tb_match
);
int errored1 = 0;
int onehot_error = 0;
initial begin
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
state <= 1<< ($unsigned($random) % 4);
in <= $random;
if (!tb_match) onehot_error++;
end
// Random.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
state <= $random;
in <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
if (!onehot_error && errored1)
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_next_state;
int errortime_next_state;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic [3:0] state;
logic [3:0] next_state_ref;
logic [3:0] next_state_dut;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.state );
RefModule good1 (
.in,
.state,
.next_state(next_state_ref),
.out(out_ref) );
TopModule top_module1 (
.in,
.state,
.next_state(next_state_dut),
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_next_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "next_state", stats1.errors_next_state, stats1.errortime_next_state);
else $display("Hint: Output '%s' has no mismatches.", "next_state");
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))
begin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;
stats1.errors_next_state = stats1.errors_next_state+1'b1; end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob080_timer |
Implement a timer that counts down for a given number of clock cycles,
then asserts a signal to indicate that the given duration has elapsed. A
good way to implement this is with a down-counter that asserts an output
signal when the count becomes 0. At each clock cycle:
(1) If load = 1, load the internal counter with the 10-bit data, the
number of clock cycles the timer should count before timing out. The
counter can be loaded at any time, including when it is still counting
and has not yet reached 0.
(2) If load = 0, the internal counter should decrement by 1. The output
signal tc ("terminal count") indicates whether the internal counter has
reached 0. Once the internal counter has reached 0, it should stay 0
(stop counting) until the counter is loaded again.
module TopModule (
input clk,
input load,
input [9:0] data,
output tc
);
|
module TopModule (
input clk,
input load,
input [9:0] data,
output tc
);
|
module RefModule (
input clk,
input load,
input [9:0] data,
output tc
);
logic [9:0] count_value;
always @(posedge clk)
if(load) count_value <= data;
else if(count_value != 0) count_value <= count_value - 1;
assign tc = count_value == 0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen(
input clk,
output logic load,
output logic [9:0] data,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
output int wavedrom_hide_after_time
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
load <= 1'b0;
wavedrom_start("Count 3, then 10 cycles");
@(posedge clk) {data, load} <= {10'd3, 1'b1};
@(posedge clk) {data, load} <= {10'hx, 1'b0};
@(posedge clk) load <= 0;
@(posedge clk) load <= 0;
@(posedge clk) load <= 0;
@(posedge clk) {data, load} <= {10'd10, 1'b1};
@(posedge clk) {data, load} <= {10'hx, 1'b0};
repeat(12) @(posedge clk);
wavedrom_stop();
@(posedge clk) {load, data} <= {1'b1, 10'h10};
@(posedge clk) {load, data} <= {1'b0, 10'h10};
@(posedge clk) {load, data} <= {1'b1, 10'h0}; // Load 0
@(posedge clk) {load, data} <= {1'b1, 10'h3ff}; // Load 1023
@(posedge clk) {load, data} <= {1'b0, 10'h0};
repeat(1040) @(posedge clk);
repeat(2500) @(posedge clk) begin
load <= !($urandom & 10'hf);
data <= $urandom_range(0,32);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_tc;
int errortime_tc;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [9:0] data;
logic tc_ref;
logic tc_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,tc_ref,tc_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.data );
RefModule good1 (
.clk,
.load,
.data,
.tc(tc_ref) );
TopModule top_module1 (
.clk,
.load,
.data,
.tc(tc_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_tc) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "tc", stats1.errors_tc, stats1.errortime_tc);
else $display("Hint: Output '%s' has no mismatches.", "tc");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { tc_ref } === ( { tc_ref } ^ { tc_dut } ^ { tc_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (tc_ref !== ( tc_ref ^ tc_dut ^ tc_ref ))
begin if (stats1.errors_tc == 0) stats1.errortime_tc = $time;
stats1.errors_tc = stats1.errors_tc+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob081_7458 |
The 7458 is a chip with four AND gates and two OR gates. Create a module
in Verilog with the same functionality as the 7458 chip. It has 10 inputs
and 2 outputs. You may choose to use an `assign` statement to drive each
of the output wires, or you may choose to declare (four) wires for use as
intermediate signals, where each internal wire is driven by the output of
one of the AND gates.
In this circuit, p1y should be the OR of two 3-input AND gates: one that
ANDs p1a, p1b, and p1c, and the second that ANDs p1d, p1e, and p1f. The
output p2y is the OR of two 2-input AND gates: one that ANDs p2a and p2b,
and the second that ANDs p2c and p2d.
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
|
module TopModule (
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
|
module RefModule (
input p1a,
input p1b,
input p1c,
input p1d,
input p1e,
input p1f,
output p1y,
input p2a,
input p2b,
input p2c,
input p2d,
output p2y
);
assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f};
assign p2y = &{p2a, p2b} | &{p2c, p2d};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg p1a, p1b, p1c, p1d, p1e, p1f,
output reg p2a, p2b, p2c, p2d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{p1a,p1b,p1c,p1d,p1e,p1f} <= 4'h0;
{p2a,p2b,p2c,p2d} <= 4'h0;
wavedrom_start();
repeat(20) @(posedge clk) begin
{p1a,p1b,p1c,p1d,p1e,p1f} <= {count[2:0], count[3:1]};
{p2a,p2b,p2c,p2d} <= count;
count = count + 1;
end
wavedrom_stop();
repeat(400) @(posedge clk,negedge clk) begin
{p1a,p1b,p1c,p1d,p2a,p2b,p2c,p2d} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_p1y;
int errortime_p1y;
int errors_p2y;
int errortime_p2y;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic p1a;
logic p1b;
logic p1c;
logic p1d;
logic p1e;
logic p1f;
logic p2a;
logic p2b;
logic p2c;
logic p2d;
logic p1y_ref;
logic p1y_dut;
logic p2y_ref;
logic p2y_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,p1a,p1b,p1c,p1d,p1e,p1f,p2a,p2b,p2c,p2d,p1y_ref,p1y_dut,p2y_ref,p2y_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.p1a,
.p1b,
.p1c,
.p1d,
.p1e,
.p1f,
.p2a,
.p2b,
.p2c,
.p2d );
RefModule good1 (
.p1a,
.p1b,
.p1c,
.p1d,
.p1e,
.p1f,
.p2a,
.p2b,
.p2c,
.p2d,
.p1y(p1y_ref),
.p2y(p2y_ref) );
TopModule top_module1 (
.p1a,
.p1b,
.p1c,
.p1d,
.p1e,
.p1f,
.p2a,
.p2b,
.p2c,
.p2d,
.p1y(p1y_dut),
.p2y(p2y_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_p1y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "p1y", stats1.errors_p1y, stats1.errortime_p1y);
else $display("Hint: Output '%s' has no mismatches.", "p1y");
if (stats1.errors_p2y) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "p2y", stats1.errors_p2y, stats1.errortime_p2y);
else $display("Hint: Output '%s' has no mismatches.", "p2y");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { p1y_ref, p2y_ref } === ( { p1y_ref, p2y_ref } ^ { p1y_dut, p2y_dut } ^ { p1y_ref, p2y_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (p1y_ref !== ( p1y_ref ^ p1y_dut ^ p1y_ref ))
begin if (stats1.errors_p1y == 0) stats1.errortime_p1y = $time;
stats1.errors_p1y = stats1.errors_p1y+1'b1; end
if (p2y_ref !== ( p2y_ref ^ p2y_dut ^ p2y_ref ))
begin if (stats1.errors_p2y == 0) stats1.errortime_p2y = $time;
stats1.errors_p2y = stats1.errors_p2y+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob082_lfsr32 |
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of the shift register. A Galois LFSR
is one particular arrangement where bit positions with a "tap" are XORed
with the output bit to produce each bit's next value, while bit positions
without a tap shift. Build a 32-bit Galois LFSR with taps at bit
positions 32, 22, 2, and 1. Reset should be active high synchronous, and
should reset the output q to 32'h1.
module TopModule (
input clk,
input reset,
output reg [31:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [31:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [31:0] q
);
logic [31:0] q_next;
always@(q) begin
q_next = q[31:1];
q_next[31] = q[0];
q_next[21] ^= q[0];
q_next[1] ^= q[0];
q_next[0] ^= q[0];
end
always @(posedge clk) begin
if (reset)
q <= 32'h1;
else
q <= q_next;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset
);
initial begin
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
@(posedge clk) reset <= 1'b0;
repeat(200000) @(posedge clk);
reset <= 1'b1;
repeat(5) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [31:0] q_ref;
logic [31:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob083_mt2015_q4b |
The module can be described by the following simulation waveform:
time x y z
0ns 0 0 1
5ns 0 0 1
10ns 0 0 1
15ns 0 0 1
20ns 0 0 1
25ns 1 0 0
30ns 1 0 0
35ns 0 1 0
40ns 0 1 0
45ns 1 1 1
50ns 1 1 1
55ns 0 0 1
60ns 0 1 0
65ns 0 1 0
70ns 1 1 1
75ns 0 1 0
80ns 0 1 0
85ns 0 1 0
90ns 1 0 0
module TopModule (
input x,
input y,
output z
);
|
module TopModule (
input x,
input y,
output z
);
|
module RefModule (
input x,
input y,
output z
);
assign z = ~(x^y);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic y,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{x,y} <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) {y,x} <= 0;
@(posedge clk) {y,x} <= 1;
@(posedge clk) {y,x} <= 2;
@(posedge clk) {y,x} <= 3;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{x, y} <= $random % 4;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic y;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.z(z_ref) );
TopModule top_module1 (
.x,
.y,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob084_ece241_2013_q12 |
In this question, you will design a circuit for an 8x1 memory, where
writing to the memory is accomplished by shifting-in bits, and reading is
"random access", as in a typical RAM. You will then use the circuit to
realize a 3-input logic function. First, create an 8-bit shift register
with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7].
The shift register input should be called S, which feeds the input of
Q[0] (MSB is shifted in first). The enable input is synchronous active
high and controls whether to shift. Extend the circuit to have 3
additional inputs A,B,C and an output Z. The circuit's behaviour should
be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so
on. Your circuit should contain ONLY the 8-bit shift register, and
multiplexers.
module TopModule (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
|
module TopModule (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
|
module RefModule (
input clk,
input enable,
input S,
input A,
input B,
input C,
output reg Z
);
reg [7:0] q;
always @(posedge clk) begin
if (enable)
q <= {q[6:0], S};
end
assign Z = q[ {A, B, C} ];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic S, enable,
output logic A, B, C,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
enable <= 0;
{A,B,C} <= 0;
S <= 1'bx;
@(negedge clk) wavedrom_start("A 3-input AND gate");
@(posedge clk);
@(posedge clk) enable <= 1; S <= 1;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) S <= 0;
@(posedge clk) enable <= 0; S <= 1'bx;
{A,B,C} <= 5;
@(posedge clk) {A,B,C} <= 6;
@(posedge clk) {A,B,C} <= 7;
@(posedge clk) {A,B,C} <= 0;
@(posedge clk) {A,B,C} <= 1;
@(negedge clk) wavedrom_stop();
repeat(500) @(posedge clk, negedge clk) begin
{A,B,C,S} <= $random;
enable <= ($random&3) == 0;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Z;
int errortime_Z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic enable;
logic S;
logic A;
logic B;
logic C;
logic Z_ref;
logic Z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,enable,S,A,B,C,Z_ref,Z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.enable,
.S,
.A,
.B,
.C );
RefModule good1 (
.clk,
.enable,
.S,
.A,
.B,
.C,
.Z(Z_ref) );
TopModule top_module1 (
.clk,
.enable,
.S,
.A,
.B,
.C,
.Z(Z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Z", stats1.errors_Z, stats1.errortime_Z);
else $display("Hint: Output '%s' has no mismatches.", "Z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Z_ref } === ( { Z_ref } ^ { Z_dut } ^ { Z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Z_ref !== ( Z_ref ^ Z_dut ^ Z_ref ))
begin if (stats1.errors_Z == 0) stats1.errortime_Z = $time;
stats1.errors_Z = stats1.errors_Z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob085_shift4 |
Build a 4-bit shift register (right shift), with asynchronous positive
edge triggered areset, synchronous active high signals load, and enable.
(1) areset: Resets shift register to zero.
(2) load: Loads shift register with data[3:0] instead of shifting.
(3) ena: Shift right (q[3] becomes zero, q[0] is shifted out and
disappears).
(4) q: The contents of the shift register. If both the load and ena
inputs are asserted (1), the load input has higher priority.
module TopModule (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
|
module TopModule (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
|
module RefModule (
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk, posedge areset) begin
if (areset)
q <= 0;
else if (load)
q <= data;
else if (ena)
q <= q[3:1];
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output areset,
output reg load,
output reg ena,
output reg[3:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{load, ena, reset, data} <= 7'h40;
@(posedge clk) {load, ena, reset, data} <= 7'h4f;
wavedrom_start("Load and reset");
@(posedge clk) {load, ena, reset, data} <= 7'h0x;
@(posedge clk) {load, ena, reset, data} <= 7'h2x;
@(posedge clk) {load, ena, reset, data} <= 7'h2x;
@(posedge clk) {load, ena, reset, data} <= 7'h0x;
reset_test(1);
@(posedge clk);
@(posedge clk);
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
load <= !($random & 15);
ena <= |($random & 31);
data <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic load;
logic ena;
logic [3:0] data;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,load,ena,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.load,
.ena,
.data );
RefModule good1 (
.clk,
.areset,
.load,
.ena,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.areset,
.load,
.ena,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob086_lfsr5 |
A linear feedback shift register is a shift register usually with a few
XOR gates to produce the next state of the shift register. A Galois LFSR
is one particular arrangement where bit positions with a "tap" are XORed
with the output bit to produce its next value, while bit positions
without a tap shift. If the taps positions are carefully chosen, the LFSR
can be made to be "maximum-length". A maximum-length LFSR of n bits
cycles through 2**n-1 states before repeating (the all-zero state is
never reached). Build a 5-bit maximal-length Galois LFSR with taps at bit
positions 5 and 3. The active-high synchronous reset should reset the
LFSR output to 1.
module TopModule (
input clk,
input reset,
output reg [4:0] q
);
|
module TopModule (
input clk,
input reset,
output reg [4:0] q
);
|
module RefModule (
input clk,
input reset,
output reg [4:0] q
);
logic [4:0] q_next;
always @(q) begin
q_next = q[4:1];
q_next[4] = q[0];
q_next[2] ^= q[0];
end
always @(posedge clk) begin
if (reset)
q <= 5'h1;
else
q <= q_next;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
@(negedge clk);
wavedrom_start();
reset_test();
repeat(8) @(posedge clk);
@(negedge clk);
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
end
@(posedge clk) reset <= 1'b0;
repeat(2000) @(posedge clk);
reset <= 1'b1;
repeat(5) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [4:0] q_ref;
logic [4:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.q(q_ref) );
TopModule top_module1 (
.clk,
.reset,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob087_gates |
Build a combinational circuit with two inputs, a and b. There are 7
outputs, each with a logic gate driving it:
(1) out_and: a and b
(2) out_or: a or b
(3) out_xor: a xor b
(4) out_nand: a nand b
(5) out_nor: a nor b
(6) out_xnor: a xnor b
(7) out_anotb: a and-not b
module TopModule (
input a,
input b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
|
module TopModule (
input a,
input b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
|
module RefModule (
input a,
input b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = a^b;
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xnor = a^~b;
assign out_anotb = a & ~b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) {a,b} <= 0;
wavedrom_start();
@(posedge clk) {a,b} <= 0;
@(posedge clk) {a,b} <= 1;
@(posedge clk) {a,b} <= 2;
@(posedge clk) {a,b} <= 3;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{a,b} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_and;
int errortime_out_and;
int errors_out_or;
int errortime_out_or;
int errors_out_xor;
int errortime_out_xor;
int errors_out_nand;
int errortime_out_nand;
int errors_out_nor;
int errortime_out_nor;
int errors_out_xnor;
int errortime_out_xnor;
int errors_out_anotb;
int errortime_out_anotb;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_and_ref;
logic out_and_dut;
logic out_or_ref;
logic out_or_dut;
logic out_xor_ref;
logic out_xor_dut;
logic out_nand_ref;
logic out_nand_dut;
logic out_nor_ref;
logic out_nor_dut;
logic out_xnor_ref;
logic out_xnor_dut;
logic out_anotb_ref;
logic out_anotb_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_and_ref,out_and_dut,out_or_ref,out_or_dut,out_xor_ref,out_xor_dut,out_nand_ref,out_nand_dut,out_nor_ref,out_nor_dut,out_xnor_ref,out_xnor_dut,out_anotb_ref,out_anotb_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.out_and(out_and_ref),
.out_or(out_or_ref),
.out_xor(out_xor_ref),
.out_nand(out_nand_ref),
.out_nor(out_nor_ref),
.out_xnor(out_xnor_ref),
.out_anotb(out_anotb_ref) );
TopModule top_module1 (
.a,
.b,
.out_and(out_and_dut),
.out_or(out_or_dut),
.out_xor(out_xor_dut),
.out_nand(out_nand_dut),
.out_nor(out_nor_dut),
.out_xnor(out_xnor_dut),
.out_anotb(out_anotb_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_and) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_and", stats1.errors_out_and, stats1.errortime_out_and);
else $display("Hint: Output '%s' has no mismatches.", "out_and");
if (stats1.errors_out_or) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_or", stats1.errors_out_or, stats1.errortime_out_or);
else $display("Hint: Output '%s' has no mismatches.", "out_or");
if (stats1.errors_out_xor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_xor", stats1.errors_out_xor, stats1.errortime_out_xor);
else $display("Hint: Output '%s' has no mismatches.", "out_xor");
if (stats1.errors_out_nand) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_nand", stats1.errors_out_nand, stats1.errortime_out_nand);
else $display("Hint: Output '%s' has no mismatches.", "out_nand");
if (stats1.errors_out_nor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_nor", stats1.errors_out_nor, stats1.errortime_out_nor);
else $display("Hint: Output '%s' has no mismatches.", "out_nor");
if (stats1.errors_out_xnor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_xnor", stats1.errors_out_xnor, stats1.errortime_out_xnor);
else $display("Hint: Output '%s' has no mismatches.", "out_xnor");
if (stats1.errors_out_anotb) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_anotb", stats1.errors_out_anotb, stats1.errortime_out_anotb);
else $display("Hint: Output '%s' has no mismatches.", "out_anotb");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } === ( { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ^ { out_and_dut, out_or_dut, out_xor_dut, out_nand_dut, out_nor_dut, out_xnor_dut, out_anotb_dut } ^ { out_and_ref, out_or_ref, out_xor_ref, out_nand_ref, out_nor_ref, out_xnor_ref, out_anotb_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_and_ref !== ( out_and_ref ^ out_and_dut ^ out_and_ref ))
begin if (stats1.errors_out_and == 0) stats1.errortime_out_and = $time;
stats1.errors_out_and = stats1.errors_out_and+1'b1; end
if (out_or_ref !== ( out_or_ref ^ out_or_dut ^ out_or_ref ))
begin if (stats1.errors_out_or == 0) stats1.errortime_out_or = $time;
stats1.errors_out_or = stats1.errors_out_or+1'b1; end
if (out_xor_ref !== ( out_xor_ref ^ out_xor_dut ^ out_xor_ref ))
begin if (stats1.errors_out_xor == 0) stats1.errortime_out_xor = $time;
stats1.errors_out_xor = stats1.errors_out_xor+1'b1; end
if (out_nand_ref !== ( out_nand_ref ^ out_nand_dut ^ out_nand_ref ))
begin if (stats1.errors_out_nand == 0) stats1.errortime_out_nand = $time;
stats1.errors_out_nand = stats1.errors_out_nand+1'b1; end
if (out_nor_ref !== ( out_nor_ref ^ out_nor_dut ^ out_nor_ref ))
begin if (stats1.errors_out_nor == 0) stats1.errortime_out_nor = $time;
stats1.errors_out_nor = stats1.errors_out_nor+1'b1; end
if (out_xnor_ref !== ( out_xnor_ref ^ out_xnor_dut ^ out_xnor_ref ))
begin if (stats1.errors_out_xnor == 0) stats1.errortime_out_xnor = $time;
stats1.errors_out_xnor = stats1.errors_out_xnor+1'b1; end
if (out_anotb_ref !== ( out_anotb_ref ^ out_anotb_dut ^ out_anotb_ref ))
begin if (stats1.errors_out_anotb == 0) stats1.errortime_out_anotb = $time;
stats1.errors_out_anotb = stats1.errors_out_anotb+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob088_ece241_2014_q5b |
The following diagram is a Mealy machine implementation of the 2's
complementer. Implement in Verilog using one-hot encoding. Resets into
state A and reset is asynchronous active-high.
A --x=0 (z=0)--> A
A --x=1 (z=1)--> B
B --x=0 (z=1)--> B
B --x=1 (z=0)--> B
module TopModule (
input clk,
input areset,
input x,
output z
);
|
module TopModule (
input clk,
input areset,
input x,
output z
);
|
module RefModule (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1;
reg state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? B : A;
B: state <= B;
endcase
end
end
assign z = (state == A && x==1) | (state == B && x==0);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
x <= 0;
reset <= 1;
@(posedge clk) reset <= 0; x <= 1;
@(posedge clk) x <= 0;
reset_test(1);
@(negedge clk) wavedrom_start();
@(posedge clk) {reset,x} <= 2'h2;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk)
{reset,x} <= {($random&31) == 0, ($random&1)==0 };
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.x );
RefModule good1 (
.clk,
.areset,
.x,
.z(z_ref) );
TopModule top_module1 (
.clk,
.areset,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob089_ece241_2014_q5a |
You are to design a one-input one-output serial 2's complementer Moore
state machine. The input (x) is a series of bits (one per clock cycle)
beginning with the least-significant bit of the number, and the output
(Z) is the 2's complement of the input. The machine will accept input
numbers of arbitrary length. The circuit requires a positive edge
triggered asynchronous reset. The conversion begins when Reset is
released and stops when Reset is asserted.
module TopModule (
input clk,
input areset,
input x,
output z
);
|
module TopModule (
input clk,
input areset,
input x,
output z
);
|
module RefModule (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <= x ? B : C;
C: state <= x ? B : C;
endcase
end
end
assign z = (state == C);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
x <= 0;
reset <= 1;
@(posedge clk) reset <= 0; x <= 1;
@(posedge clk) x <= 0;
reset_test(1);
@(negedge clk) wavedrom_start();
@(posedge clk) {reset,x} <= 2'h2;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk)
{reset,x} <= {($random&31) == 0, ($random&1)==0 };
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.x );
RefModule good1 (
.clk,
.areset,
.x,
.z(z_ref) );
TopModule top_module1 (
.clk,
.areset,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob090_circuit1 |
This is a combinational circuit. Read the simulation waveforms to
determine what the circuit does, then implement it.
time a b q
0ns 0 0 0
5ns 0 0 0
10ns 0 0 0
15ns 0 0 0
20ns 0 0 0
25ns 0 1 0
30ns 0 1 0
35ns 1 0 0
40ns 1 0 0
45ns 1 1 1
50ns 1 1 1
55ns 0 0 0
60ns 0 0 0
65ns 0 1 0
70ns 0 1 0
75ns 1 0 0
80ns 1 0 0
85ns 1 1 1
90ns 1 1 1
module TopModule (
input a,
input b,
output q
);
|
module TopModule (
input a,
input b,
output q
);
|
module RefModule (
input a,
input b,
output q
);
assign q = a&b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b} <= 0;
repeat(8) @(posedge clk) {a,b} <= {a,b} + 1;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.a,
.b,
.q(q_ref) );
TopModule top_module1 (
.a,
.b,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob091_2012_q2b |
Consider the state machine shown below:
A (0) --1--> B
A (0) --0--> A
B (0) --1--> C
B (0) --0--> D
C (0) --1--> E
C (0) --0--> D
D (0) --1--> F
D (0) --0--> A
E (1) --1--> E
E (1) --0--> D
F (1) --1--> C
F (1) --0--> D
Assume that a one-hot code is used with the state assignment y[5:0] =
000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)
Write a Verilog for the signal Y1, which is the input of state flip-flop
y[1], for the signal Y3, which is the input of state flip-flop y[3].
Derive the Verilog by inspection assuming a one-hot encoding.
module TopModule (
input [5:0] y,
input w,
output Y1,
output Y3
);
|
module TopModule (
input [5:0] y,
input w,
output Y1,
output Y3
);
|
module RefModule (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic[5:0] y,
output logic w,
input tb_match
);
int errored1 = 0;
int onehot_error = 0;
int temp;
initial begin
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
y <= 1<< ($unsigned($random) % 6);
w <= $random;
if (!tb_match) onehot_error++;
end
// Random.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
do
temp = $random;
while ( !{temp[5:4],temp[2:1]} == !{temp[3],temp[0]} );
// Make y[3,0] and y[5,4,2,1] mutually exclusive, so we can accept Y3=(~y[3] & ~y[0]) &~w as a valid answer too.
y <= temp;
w <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.");
if (!onehot_error && errored1)
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y1;
int errortime_Y1;
int errors_Y3;
int errortime_Y3;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [5:0] y;
logic w;
logic Y1_ref;
logic Y1_dut;
logic Y3_ref;
logic Y3_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut,Y3_ref,Y3_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
RefModule good1 (
.y,
.w,
.Y1(Y1_ref),
.Y3(Y3_ref) );
TopModule top_module1 (
.y,
.w,
.Y1(Y1_dut),
.Y3(Y3_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y1", stats1.errors_Y1, stats1.errortime_Y1);
else $display("Hint: Output '%s' has no mismatches.", "Y1");
if (stats1.errors_Y3) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y3", stats1.errors_Y3, stats1.errortime_Y3);
else $display("Hint: Output '%s' has no mismatches.", "Y3");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y1_ref, Y3_ref } === ( { Y1_ref, Y3_ref } ^ { Y1_dut, Y3_dut } ^ { Y1_ref, Y3_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))
begin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;
stats1.errors_Y1 = stats1.errors_Y1+1'b1; end
if (Y3_ref !== ( Y3_ref ^ Y3_dut ^ Y3_ref ))
begin if (stats1.errors_Y3 == 0) stats1.errortime_Y3 = $time;
stats1.errors_Y3 = stats1.errors_Y3+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob092_gatesv100 |
You are given a 100-bit input vector in[99:0]. We want to know some
relationships between each bit and its neighbour:
(1) out_both: Each bit of this output vector should indicate whether
both the corresponding input bit and its neighbour to the left are '1'.
For example, out_both[98] should indicate if in[98] and in[99] are both
1. Since in[99] has no neighbour to the left, the answer is obvious so
we don't need to know out_both[99].
(2) out_any: Each bit of this output vector should indicate whether any
of the corresponding input bit and its neighbour to the right are '1'.
For example, out_any[2] should indicate if either in[2] or in[1] are 1.
Since in[0] has no neighbour to the right, the answer is obvious so we
don't need to know out_any[0].
(3) out_different: Each bit of this output vector should indicate
whether the corresponding input bit is different from its neighbour to
the left. For example, out_different[98] should indicate if in[98] is
different from in[99]. For this part, treat the vector as wrapping
around, so in[99]'s neighbour to the left is in[0].
module TopModule (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
|
module TopModule (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
|
module RefModule (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_both = in & in[99:1];
assign out_any = in | in[99:1];
assign out_different = in^{in[0], in[99:1]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output logic [99:0] in
);
initial begin
in <= $random;
repeat(100) begin
@(negedge clk) in <= $random;
@(posedge clk) in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_both;
int errortime_out_both;
int errors_out_any;
int errortime_out_any;
int errors_out_different;
int errortime_out_different;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] in;
logic [98:0] out_both_ref;
logic [98:0] out_both_dut;
logic [99:1] out_any_ref;
logic [99:1] out_any_dut;
logic [99:0] out_different_ref;
logic [99:0] out_different_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_both(out_both_ref),
.out_any(out_any_ref),
.out_different(out_different_ref) );
TopModule top_module1 (
.in,
.out_both(out_both_dut),
.out_any(out_any_dut),
.out_different(out_different_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_both) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_both", stats1.errors_out_both, stats1.errortime_out_both);
else $display("Hint: Output '%s' has no mismatches.", "out_both");
if (stats1.errors_out_any) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_any", stats1.errors_out_any, stats1.errortime_out_any);
else $display("Hint: Output '%s' has no mismatches.", "out_any");
if (stats1.errors_out_different) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_different", stats1.errors_out_different, stats1.errortime_out_different);
else $display("Hint: Output '%s' has no mismatches.", "out_different");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))
begin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;
stats1.errors_out_both = stats1.errors_out_both+1'b1; end
if (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))
begin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;
stats1.errors_out_any = stats1.errors_out_any+1'b1; end
if (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))
begin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;
stats1.errors_out_different = stats1.errors_out_different+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob093_ece241_2014_q3 |
For the following Karnaugh map, give the circuit implementation using one
4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using
as few as possible. You are not allowed to use any other logic gate and
you must use _a_ and _b_ as the multiplexer selector inputs, as shown on
the 4-to-1 multiplexer below.
ab
cd 00 01 11 10
00 | 0 | 0 | 0 | 1 |
01 | 1 | 0 | 0 | 0 |
11 | 1 | 0 | 1 | 1 |
10 | 1 | 0 | 0 | 1 |
Consider a block diagram with inputs 'c' and 'd' going into a module
called "top_module". This "top_module" has four outputs, mux_in[3:0],
that connect to a four input mux. The mux takes as input {a,b} and ab =
00 is connected to mux_in[0], ab=01 is connected to mux_in[1], and so in.
You are implementing in Verilog just the portion labelled "top_module",
such that the entire circuit (including the 4-to-1 mux) implements the
K-map.
module TopModule (
input c,
input d,
output [3:0] mux_in
);
|
module TopModule (
input c,
input d,
output [3:0] mux_in
);
|
module RefModule (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[2] = ~d;
assign mux_in[3] = c&d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{c, d} <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) {c, d} <= 2'h0;
@(posedge clk) {c, d} <= 2'h1;
@(posedge clk) {c, d} <= 2'h2;
@(posedge clk) {c, d} <= 2'h3;
@(negedge clk) wavedrom_stop();
repeat(50) @(posedge clk, negedge clk)
{c,d} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_mux_in;
int errortime_mux_in;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic c;
logic d;
logic [3:0] mux_in_ref;
logic [3:0] mux_in_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,c,d,mux_in_ref,mux_in_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.c,
.d );
RefModule good1 (
.c,
.d,
.mux_in(mux_in_ref) );
TopModule top_module1 (
.c,
.d,
.mux_in(mux_in_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_mux_in) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "mux_in", stats1.errors_mux_in, stats1.errortime_mux_in);
else $display("Hint: Output '%s' has no mismatches.", "mux_in");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { mux_in_ref } === ( { mux_in_ref } ^ { mux_in_dut } ^ { mux_in_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (mux_in_ref !== ( mux_in_ref ^ mux_in_dut ^ mux_in_ref ))
begin if (stats1.errors_mux_in == 0) stats1.errortime_mux_in = $time;
stats1.errors_mux_in = stats1.errors_mux_in+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob094_gatesv |
You are given a four-bit input vector in[3:0]. We want to know some
relationships between each bit and its neighbour:
(1) out_both: Each bit of this output vector should indicate whether
both the corresponding input bit and its neighbour to the left (higher
index) are '1'. For example, out_both[2] should indicate if in[2] and
in[3] are both 1. Since in[3] has no neighbour to the left, the answer
is obvious so we don't need to know out_both[3].
(2) out_any: Each bit of this output vector should indicate whether any
of the corresponding input bit and its neighbour to the right are '1'.
For example, out_any[2] should indicate if either in[2] or in[1] are 1.
Since in[0] has no neighbour to the right, the answer is obvious so we
don't need to know out_any[0].
(3) out_different: Each bit of this output vector should indicate
whether the corresponding input bit is different from its neighbour to
the left. For example, out_different[2] should indicate if in[2] is
different from in[3]. For this part, treat the vector as wrapping
around, so in[3]'s neighbour to the left is in[0].
module TopModule (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
|
module TopModule (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
|
module RefModule (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
assign out_both = in[2:0] & in[3:1];
assign out_any = in[2:0] | in[3:1];
assign out_different = in^{in[0], in[3:1]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
output logic [3:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 4'h3;
@(negedge clk);
wavedrom_start();
@(posedge clk) in <= 3;
@(posedge clk) in <= 6;
@(posedge clk) in <= 12;
@(posedge clk) in <= 9;
@(posedge clk) in <= 5;
@(negedge clk);
wavedrom_stop();
in <= $random;
repeat(100) begin
@(negedge clk) in <= $random;
@(posedge clk) in <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_both;
int errortime_out_both;
int errors_out_any;
int errortime_out_any;
int errors_out_different;
int errortime_out_different;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] in;
logic [2:0] out_both_ref;
logic [2:0] out_both_dut;
logic [3:1] out_any_ref;
logic [3:1] out_any_dut;
logic [3:0] out_different_ref;
logic [3:0] out_different_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_both_ref,out_both_dut,out_any_ref,out_any_dut,out_different_ref,out_different_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.out_both(out_both_ref),
.out_any(out_any_ref),
.out_different(out_different_ref) );
TopModule top_module1 (
.in,
.out_both(out_both_dut),
.out_any(out_any_dut),
.out_different(out_different_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_both) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_both", stats1.errors_out_both, stats1.errortime_out_both);
else $display("Hint: Output '%s' has no mismatches.", "out_both");
if (stats1.errors_out_any) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_any", stats1.errors_out_any, stats1.errortime_out_any);
else $display("Hint: Output '%s' has no mismatches.", "out_any");
if (stats1.errors_out_different) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_different", stats1.errors_out_different, stats1.errortime_out_different);
else $display("Hint: Output '%s' has no mismatches.", "out_different");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_both_ref, out_any_ref, out_different_ref } === ( { out_both_ref, out_any_ref, out_different_ref } ^ { out_both_dut, out_any_dut, out_different_dut } ^ { out_both_ref, out_any_ref, out_different_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_both_ref !== ( out_both_ref ^ out_both_dut ^ out_both_ref ))
begin if (stats1.errors_out_both == 0) stats1.errortime_out_both = $time;
stats1.errors_out_both = stats1.errors_out_both+1'b1; end
if (out_any_ref !== ( out_any_ref ^ out_any_dut ^ out_any_ref ))
begin if (stats1.errors_out_any == 0) stats1.errortime_out_any = $time;
stats1.errors_out_any = stats1.errors_out_any+1'b1; end
if (out_different_ref !== ( out_different_ref ^ out_different_dut ^ out_different_ref ))
begin if (stats1.errors_out_different == 0) stats1.errortime_out_different = $time;
stats1.errors_out_different = stats1.errors_out_different+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob095_review2015_fsmshift |
This module is a part of the FSM for controlling the shift register, we
want the ability to enable the shift register for exactly 4 clock cycles
whenever the proper bit pattern is detected. Whenever the FSM is reset,
assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should
be active high synchronous.
module TopModule (
input clk,
input reset,
output shift_ena
);
|
module TopModule (
input clk,
input reset,
output shift_ena
);
|
module RefModule (
input clk,
input reset,
output shift_ena
);
parameter B0=0, B1=1, B2=2, B3=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = Done;
Done: next = Done;
endcase
end
always @(posedge clk)
if (reset) state <= B0;
else state <= next;
assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset
);
initial begin
repeat(100) @(negedge clk) begin
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_shift_ena;
int errortime_shift_ena;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic shift_ena_ref;
logic shift_ena_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,shift_ena_ref,shift_ena_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset );
RefModule good1 (
.clk,
.reset,
.shift_ena(shift_ena_ref) );
TopModule top_module1 (
.clk,
.reset,
.shift_ena(shift_ena_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_shift_ena) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "shift_ena", stats1.errors_shift_ena, stats1.errortime_shift_ena);
else $display("Hint: Output '%s' has no mismatches.", "shift_ena");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { shift_ena_ref } === ( { shift_ena_ref } ^ { shift_ena_dut } ^ { shift_ena_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))
begin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;
stats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob096_review2015_fsmseq |
Build a finite-state machine that searches for the sequence 1101 in an
input bit stream. When the sequence is found, it should set
start_shifting to 1, forever, until reset. Reset is active high
synchronous.
module TopModule (
input clk,
input reset,
input data,
output start_shifting
);
|
module TopModule (
input clk,
input reset,
input data,
output start_shifting
);
|
module RefModule (
input clk,
input reset,
input data,
output start_shifting
);
parameter S=0, S1=1, S11=2, S110=3, Done=4;
reg [2:0] state, next;
always_comb begin
case (state)
S: next = data ? S1: S;
S1: next = data ? S11: S;
S11: next = data ? S11 : S110;
S110: next = data ? Done : S;
Done: next = Done;
endcase
end
always @(posedge clk)
if (reset) state <= S;
else state <= next;
assign start_shifting = state == Done;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset, data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
wire [0:9] d = 10'b1110110011;
initial begin
reset <= 1;
@(posedge clk) reset <= 0;
data <= 1;
repeat(2) @(posedge clk) ;
data <= 0;
@(posedge clk);
data <= 1;
@(posedge clk);
data <= 0;
wavedrom_start("Reset and sequence detect");
reset_test();
for (int i=0;i<10;i++) begin
@(posedge clk) data <= d[i];
end
wavedrom_stop();
repeat(600) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
data <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_start_shifting;
int errortime_start_shifting;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic data;
logic start_shifting_ref;
logic start_shifting_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,start_shifting_ref,start_shifting_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.data );
RefModule good1 (
.clk,
.reset,
.data,
.start_shifting(start_shifting_ref) );
TopModule top_module1 (
.clk,
.reset,
.data,
.start_shifting(start_shifting_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_start_shifting) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "start_shifting", stats1.errors_start_shifting, stats1.errortime_start_shifting);
else $display("Hint: Output '%s' has no mismatches.", "start_shifting");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { start_shifting_ref } === ( { start_shifting_ref } ^ { start_shifting_dut } ^ { start_shifting_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (start_shifting_ref !== ( start_shifting_ref ^ start_shifting_dut ^ start_shifting_ref ))
begin if (stats1.errors_start_shifting == 0) stats1.errortime_start_shifting = $time;
stats1.errors_start_shifting = stats1.errors_start_shifting+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob097_mux9to1v |
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses
b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.
module TopModule (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [15:0] i,
input [3:0] sel,
output logic [15:0] out
);
|
module TopModule (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [15:0] i,
input [3:0] sel,
output logic [15:0] out
);
|
module RefModule (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [15:0] i,
input [3:0] sel,
output logic [15:0] out
);
always @(*) begin
out = '1;
case (sel)
4'h0: out = a;
4'h1: out = b;
4'h2: out = c;
4'h3: out = d;
4'h4: out = e;
4'h5: out = f;
4'h6: out = g;
4'h7: out = h;
4'h8: out = i;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [15:0] a,b,c,d,e,f,g,h,i,
output logic [3:0] sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d,e,f,g,h,i,sel} <= { 16'ha, 16'hb, 16'hc, 16'hd, 16'he, 16'hf, 16'h11, 16'h12, 16'h13, 4'h0 };
@(negedge clk) wavedrom_start();
@(posedge clk) sel <= 4'h1;
@(posedge clk) sel <= 4'h2;
@(posedge clk) sel <= 4'h3;
@(posedge clk) sel <= 4'h4;
@(posedge clk) sel <= 4'h7;
@(posedge clk) sel <= 4'h8;
@(posedge clk) sel <= 4'h9;
@(posedge clk) sel <= 4'ha;
@(posedge clk) sel <= 4'hb;
@(negedge clk) wavedrom_stop();
repeat(200) @(negedge clk, posedge clk) begin
{a,b,c,d,e,f,g,h,i,sel} <= {$random, $random, $random, $random, $random};
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] a;
logic [15:0] b;
logic [15:0] c;
logic [15:0] d;
logic [15:0] e;
logic [15:0] f;
logic [15:0] g;
logic [15:0] h;
logic [15:0] i;
logic [3:0] sel;
logic [15:0] out_ref;
logic [15:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,f,g,h,i,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e,
.f,
.g,
.h,
.i,
.sel );
RefModule good1 (
.a,
.b,
.c,
.d,
.e,
.f,
.g,
.h,
.i,
.sel,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.e,
.f,
.g,
.h,
.i,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob098_circuit7 |
This is a sequential circuit. Read the simulation waveforms to determine
what the circuit does, then implement it.
time clk a q
0ns 0 x x
5ns 1 0 x
10ns 0 0 x
15ns 1 0 1
20ns 0 0 1
25ns 1 0 1
30ns 0 0 1
35ns 1 1 1
40ns 0 1 1
45ns 1 1 0
50ns 0 1 0
55ns 1 1 0
60ns 0 1 0
65ns 1 1 0
70ns 0 1 0
75ns 1 1 0
80ns 0 1 0
85ns 1 1 0
90ns 0 1 0
module TopModule (
input clk,
input a,
output reg q
);
|
module TopModule (
input clk,
input a,
output reg q
);
|
module RefModule (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(posedge clk) {a} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a} <= 0;
repeat(10) @(posedge clk) a <= $urandom;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
a <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a );
RefModule good1 (
.clk,
.a,
.q(q_ref) );
TopModule top_module1 (
.clk,
.a,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob099_m2014_q6c |
Consider the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Resets into state A. For this part, assume that a one-hot code is used
with the state assignment y[6:1] = 000001, 000010, 000100, 001000,
010000, 100000 for states A, B,..., F, respectively.
Write Verilog for the next-state signals Y2 and Y4 corresponding to
signal y[2] and y[4]. Derive the logic equations by inspection assuming a
one-hot encoding.
module TopModule (
input [6:1] y,
input w,
output Y2,
output Y4
);
|
module TopModule (
input [6:1] y,
input w,
output Y2,
output Y4
);
|
module RefModule (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic[6:1] y,
output logic w,
input tb_match
);
int errored1 = 0;
int onehot_error = 0;
int temp;
initial begin
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
y <= 1<< ($unsigned($random) % 6);
w <= $random;
if (!tb_match) onehot_error++;
end
// Random.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
do
temp = $random;
while ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );
// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.
y[6:1] <= temp[6:1];
w <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.");
if (!onehot_error && errored1)
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y2;
int errortime_Y2;
int errors_Y4;
int errortime_Y4;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [6:1] y;
logic w;
logic Y2_ref;
logic Y2_dut;
logic Y4_ref;
logic Y4_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut,Y4_ref,Y4_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
RefModule good1 (
.y,
.w,
.Y2(Y2_ref),
.Y4(Y4_ref) );
TopModule top_module1 (
.y,
.w,
.Y2(Y2_dut),
.Y4(Y4_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y2", stats1.errors_Y2, stats1.errortime_Y2);
else $display("Hint: Output '%s' has no mismatches.", "Y2");
if (stats1.errors_Y4) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y4", stats1.errors_Y4, stats1.errortime_Y4);
else $display("Hint: Output '%s' has no mismatches.", "Y4");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y2_ref, Y4_ref } === ( { Y2_ref, Y4_ref } ^ { Y2_dut, Y4_dut } ^ { Y2_ref, Y4_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))
begin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;
stats1.errors_Y2 = stats1.errors_Y2+1'b1; end
if (Y4_ref !== ( Y4_ref ^ Y4_dut ^ Y4_ref ))
begin if (stats1.errors_Y4 == 0) stats1.errortime_Y4 = $time;
stats1.errors_Y4 = stats1.errors_Y4+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob100_fsm3comb |
The following is the state transition table for a Moore state machine
with one input, one output, and four states. Use the following state
encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state
transition logic and output logic (the combinational logic portion) for
this state machine. Given the current state (state), compute the
next_state and output (out) based on the state transition table.
State | Next state in=0, Next state in=1 | Output
A | A, B | 0
B | C, B | 0
C | A, D | 0
D | C, B | 1
module TopModule (
input in,
input [1:0] state,
output reg [1:0] next_state,
output out
);
|
module TopModule (
input in,
input [1:0] state,
output reg [1:0] next_state,
output out
);
|
module RefModule (
input in,
input [1:0] state,
output reg [1:0] next_state,
output out
);
parameter A=0, B=1, C=2, D=3;
always_comb begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
assign out = (state==D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic [1:0] state
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
in <= $random;
state <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_next_state;
int errortime_next_state;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic [1:0] state;
logic [1:0] next_state_ref;
logic [1:0] next_state_dut;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.state );
RefModule good1 (
.in,
.state,
.next_state(next_state_ref),
.out(out_ref) );
TopModule top_module1 (
.in,
.state,
.next_state(next_state_dut),
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_next_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "next_state", stats1.errors_next_state, stats1.errortime_next_state);
else $display("Hint: Output '%s' has no mismatches.", "next_state");
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { next_state_ref, out_ref } === ( { next_state_ref, out_ref } ^ { next_state_dut, out_dut } ^ { next_state_ref, out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))
begin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;
stats1.errors_next_state = stats1.errors_next_state+1'b1; end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
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