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module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
//inputs
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000), // 1 in fixed3.5
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
//outputs
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule |
module EBABWrapper
(
/*AUTOARG*/
// Outputs
bus_byte_enable, bus_read, bus_write, bus_write_data, bus_addr,
// Inputs
clk, rst, out_sel, delta_mode_left, delta_mode_right, bus_ack,
bus_read_data, delta_left, delta_right, triangle_wave_max_left,
triangle_wave_max_right
);
input clk, rst, out_sel, delta_mode_left, delta_mode_right;
input bus_ack; // Avalon bus raises this when done
input [31:0] bus_read_data; // data from Avalon bus
input [31:0] delta_left, delta_right;
input [9:0] triangle_wave_max_left, triangle_wave_max_right;
output reg [3:0] bus_byte_enable; // four bit byte read/write mask
output reg bus_read; // high when requesting data
output reg bus_write; // high when writing data
output reg [31:0] bus_write_data; // data to send to Avalog bus
output reg [31:0] bus_addr; // Avalon address
wire [31:0] audio_base_address = 32'h00003040; // Avalon address
wire [31:0] audio_fifo_address = 32'h00003044; // Avalon address +4
wire [31:0] audio_data_left_address = 32'h00003048; // Avalon address +8
wire [31:0] audio_data_right_address = 32'h0000304c; // Avalon address +12
reg [3:0] state;
reg [7:0] fifo_space; // current free words in audio interface
// audio input/output from audio module FIFO
reg [31:0] right_audio_input, left_audio_input;
reg audio_input_valid;
wire [31:0] right_audio_output, left_audio_output, pitch_shift_out[0:1], filter_out[0:1];
wire pitch_shift_val[0:1], audio_out_val[0:1];
assign left_audio_output = (audio_out_val[0]) ? filter_out[0] : left_audio_output;
assign right_audio_output = (audio_out_val[1]) ? filter_out[1] : right_audio_output;
buffer #(1024) left_buffer
(
// inputs
.clk(clk),
.rst(rst),
.delta(delta_left),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_left),
.triangle_wave_max(triangle_wave_max_left),
// outputs
.pitch_shift_out(pitch_shift_out[0]),
.pitch_shift_val(pitch_shift_val[0])
);
buffer #(1024) right_buffer
(
// inputs
.clk(clk),
.rst(rst),
.delta(delta_right),
.new_sample_val(audio_input_valid),
.new_sample_data(right_audio_input),
.out_sel(1'b1),
.delta_mode(delta_mode_right),
.triangle_wave_max(triangle_wave_max_right),
// outputs
.pitch_shift_out(pitch_shift_out[1]),
.pitch_shift_val(pitch_shift_val[1])
);
IIR6_32bit_fixed filter_left(
.audio_out (filter_out[0]),
.audio_in (pitch_shift_out[0]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[0]),
.rst(rst),
.audio_out_val(audio_out_val[0])
) ; //end filter
IIR6_32bit_fixed filter_right(
.audio_out (filter_out[1]),
.audio_in (pitch_shift_out[1]),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(clk),
.data_val(pitch_shift_val[1]),
.rst(rst),
.audio_out_val(audio_out_val[1])
) ; //end filter
always @(posedge clk) begin //CLOCK_50
// reset state machine and read/write controls
if (rst) begin
state <= 0;
bus_read <= 0; // set to one if a read opeation from bus
bus_write <= 0; // set to one if a write operation to bus
end
// === writing stereo to the audio FIFO ==========
// set up read FIFO available space
if (state==4'd0) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd1; // wait for read ACK
end
// wait for read ACK and read the fifo available
// bus ACK is high when data is available
if (state==4'd1 && bus_ack==1) begin
state <= 4'd2; //4'd2
// FIFO write space is in high byte
fifo_space <= (bus_read_data>>24);
// end the read
bus_read <= 1'b0;
end
// When there is room in the FIFO
// -- start write to fifo for each channel
// -- first the left channel
if (state==4'd2 && fifo_space>8'd2) begin //
state <= 4'd3;
bus_write_data <= left_audio_output;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_write <= 1'b1;
end
// if no space, try again later
else if (state==4'd2 && fifo_space<=8'd2) begin
state <= 4'b0;
end
// detect bus-transaction-complete ACK
// for left channel write
// You MUST do this check
if (state==4'd3 && bus_ack==1) begin
state <= 4'd4; // include right channel
//state <= 4'd0; // left channel only, write only.
//state <= 4'd6; // read/write left channel only
bus_write <= 0;
end
// -- now the right channel
if (state==4'd4) begin //
state <= 4'd5;
// loop back audio input data
bus_write_data <= right_audio_output;
bus_addr <= audio_data_right_address;
bus_write <= 1'b1;
end
// detect bus-transaction-complete ACK
// for right channel write
// You MUST do this check
if (state==4'd5 && bus_ack==1) begin
// state <= 4'd0; // for write only function
state <= 4'd6; // for read/write function
bus_write <= 0;
end
// === reading stereo from the audio FIFO ==========
// set up read FIFO for available read values
if (state==4'd6 ) begin
bus_addr <= audio_fifo_address;
bus_read <= 1'b1;
bus_byte_enable <= 4'b1111;
state <= 4'd7; // wait for read ACK
end
// wait for read ACK and read the fifo available
// bus ACK is high when data is available
if (state==4'd7 && bus_ack==1) begin
state <= 4'd8; //4'dxx
// FIFO read space is in low byte
// which is zero when empty
fifo_space <= bus_read_data & 8'hff;
// end the read
bus_read <= 1'b0;
end
// When there is data in the read FIFO
// -- read it from both channels
// -- first the left channel
if (state==4'd8 && fifo_space>8'd0) begin //
state <= 4'd9;
bus_addr <= audio_data_left_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
// if no data, try again later
else if (state==4'd8 && fifo_space<=8'd0) begin
state <= 4'b0;
end
// detect bus-transaction-complete ACK
// for left channel read
// You MUST do this check
if (state==4'd9 && bus_ack==1) begin
state <= 4'd10; // include right channel
left_audio_input <= bus_read_data;
bus_read <= 0;
end
// When there is data in the read FIFO
// -- read it from both channels
// -- now right channel
if (state==4'd10) begin //
state <= 4'd11;
bus_addr <= audio_data_right_address;
bus_byte_enable <= 4'b1111;
bus_read <= 1'b1;
end
// detect bus-transaction-complete ACK
// for right channel read
// You MUST do this check
if (state==4'd11 && bus_ack==1) begin
state <= 4'd12; // back to beginning
right_audio_input <= bus_read_data;
// set the data-ready strobe
audio_input_valid <= 1'b1;
bus_read <= 0;
end
// end data-ready strobe
if (state==4'd12) begin
state <= 4'd0; // back to beginning
audio_input_valid <= 1'b0;
end
end // always @(posedge state_clock)
endmodule // EBABWrapper |
module DE1_SoC_Computer
(
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
// SDRAM
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
// I2C Bus for Configuration of the Audio and Video-In Chips
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
// 40-Pin Headers
GPIO_0,
GPIO_1,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// IR
IRDA_RXD,
IRDA_TXD,
// Pushbuttons
KEY,
// LEDs
LEDR,
// PS2 Ports
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
// Slider Switches
SW,
// Video-In
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
// VGA
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
HPS_DDR3_ADDR,
HPS_DDR3_BA,
HPS_DDR3_CAS_N,
HPS_DDR3_CKE,
HPS_DDR3_CK_N,
HPS_DDR3_CK_P,
HPS_DDR3_CS_N,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_N,
HPS_DDR3_DQS_P,
HPS_DDR3_ODT,
HPS_DDR3_RAS_N,
HPS_DDR3_RESET_N,
HPS_DDR3_RZQ,
HPS_DDR3_WE_N,
// Ethernet
HPS_ENET_GTX_CLK,
HPS_ENET_INT_N,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
// Flash
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
// Accelerometer
HPS_GSENSOR_INT,
// General Purpose I/O
HPS_GPIO,
// I2C
HPS_I2C_CONTROL,
HPS_I2C1_SCLK,
HPS_I2C1_SDAT,
HPS_I2C2_SCLK,
HPS_I2C2_SDAT,
// Pushbutton
HPS_KEY,
// LED
HPS_LED,
// SD Card
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
// SPI
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
// UART
HPS_UART_RX,
HPS_UART_TX,
// USB
HPS_CONV_USB_N,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_STP
);
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input CLOCK4_50;
// ADC
inout ADC_CS_N;
output ADC_DIN;
input ADC_DOUT;
output ADC_SCLK;
// Audio
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
// SDRAM
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_RAS_N;
output DRAM_UDQM;
output DRAM_WE_N;
// I2C Bus for Configuration of the Audio and Video-In Chips
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
// 40-pin headers
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
// Seven Segment Displays
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
// IR
input IRDA_RXD;
output IRDA_TXD;
// Pushbuttons
input [3:0] KEY;
// LEDs
output [9:0] LEDR;
// PS2 Ports
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
// Slider Switches
input [9:0] SW;
// Video-In
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
// VGA
output [7:0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
output [14:0] HPS_DDR3_ADDR;
output [2:0] HPS_DDR3_BA;
output HPS_DDR3_CAS_N;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_N;
output HPS_DDR3_CK_P;
output HPS_DDR3_CS_N;
output [3:0] HPS_DDR3_DM;
inout [31:0] HPS_DDR3_DQ;
inout [3:0] HPS_DDR3_DQS_N;
inout [3:0] HPS_DDR3_DQS_P;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_N;
output HPS_DDR3_RESET_N;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_N;
// Ethernet
output HPS_ENET_GTX_CLK;
inout HPS_ENET_INT_N;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
input HPS_ENET_RX_CLK;
input [3:0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [3:0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
// Flash
inout [3:0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
// Accelerometer
inout HPS_GSENSOR_INT;
// General Purpose I/O
inout [1:0] HPS_GPIO;
// I2C
inout HPS_I2C_CONTROL;
inout HPS_I2C1_SCLK;
inout HPS_I2C1_SDAT;
inout HPS_I2C2_SCLK;
inout HPS_I2C2_SDAT;
// Pushbutton
inout HPS_KEY;
// LED
inout HPS_LED;
// SD Card
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [3:0] HPS_SD_DATA;
// SPI
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
inout HPS_SPIM_SS;
// UART
input HPS_UART_RX;
output HPS_UART_TX;
// USB
inout HPS_CONV_USB_N;
input HPS_USB_CLKOUT;
inout [70] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_STP;
//=======================================================
// REG/WIRE declarations
//=======================================================
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX1 = 7'b1111111;
//=======================================================
// Bus controller for AVALON bus-master
//=======================================================
// computes DDS for sine wave and fills audio FIFO
// reads audio FIFO and loops it back
// MUST configure (in Qsys) Audio Config module
// -- Line in to ADC
// -- uncheck both bypass options
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
wire bus_ack; // Avalon bus raises this when done
wire [31:0] bus_read_data; // data from Avalon bus
wire rst, hps_rst;
assign rst = ~KEY[0] || hps_rst;
wire [31:0] delta_left;
wire [31:0] delta_right;
wire delta_mode_left, delta_mode_right;
wire [9:0] triangle_wave_max_left, triangle_wave_max_right;
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(CLOCK_50),
.rst(rst | hps_rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data),
.delta_left(delta_left),
.delta_right(delta_right),
.out_sel(SW[9]),
.delta_mode_left(delta_mode_left),
.delta_mode_right(delta_mode_right),
.triangle_wave_max_right(triangle_wave_max_right),
.triangle_wave_max_left(triangle_wave_max_left)
);
Computer_System The_System
(
////////////////////////////////////
// FPGA Side
////////////////////////////////////
// Global signals
.system_pll_ref_clk_clk (CLOCK_50),
.system_pll_ref_reset_reset (1'b0),
// AV Config
.av_config_SCLK (FPGA_I2C_SCLK),
.av_config_SDAT (FPGA_I2C_SDAT),
// Audio Subsystem
.audio_pll_ref_clk_clk (CLOCK3_50),
.audio_pll_ref_reset_reset (1'b0),
.audio_clk_clk (AUD_XCK),
.audio_ADCDAT (AUD_ADCDAT),
.audio_ADCLRCK (AUD_ADCLRCK),
.audio_BCLK (AUD_BCLK),
.audio_DACDAT (AUD_DACDAT),
.audio_DACLRCK (AUD_DACLRCK),
// HPS slaves
.reset_slave_external_connection_export (hps_rst),
.delta_left_slave_external_connection_export (delta_left),
.delta_right_slave_external_connection_export (delta_right),
.triangle_wave_max_left_slave_external_connection_export (triangle_wave_max_left),
.triangle_wave_max_right_slave_external_connection_export (triangle_wave_max_right),
.delta_mode_right_slave_external_connection_export (delta_mode_right),
.delta_mode_left_slave_external_connection_export (delta_mode_left),
// bus-master state machine interface
.bus_master_audio_external_interface_address (bus_addr),
.bus_master_audio_external_interface_byte_enable (bus_byte_enable),
.bus_master_audio_external_interface_read (bus_read),
.bus_master_audio_external_interface_write (bus_write),
.bus_master_audio_external_interface_write_data (bus_write_data),
.bus_master_audio_external_interface_acknowledge (bus_ack),
.bus_master_audio_external_interface_read_data (bus_read_data),
// VGA Subsystem
.vga_pll_ref_clk_clk (CLOCK2_50),
.vga_pll_ref_reset_reset (1'b0),
.vga_CLK (VGA_CLK),
.vga_BLANK (VGA_BLANK_N),
.vga_SYNC (VGA_SYNC_N),
.vga_HS (VGA_HS),
.vga_VS (VGA_VS),
.vga_R (VGA_R),
.vga_G (VGA_G),
.vga_B (VGA_B),
// SDRAM
.sdram_clk_clk (DRAM_CLK),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm ({DRAM_UDQM,DRAM_LDQM}),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
////////////////////////////////////
// HPS Side
////////////////////////////////////
// DDR3 SDRAM
.memory_mem_a (HPS_DDR3_ADDR),
.memory_mem_ba (HPS_DDR3_BA),
.memory_mem_ck (HPS_DDR3_CK_P),
.memory_mem_ck_n (HPS_DDR3_CK_N),
.memory_mem_cke (HPS_DDR3_CKE),
.memory_mem_cs_n (HPS_DDR3_CS_N),
.memory_mem_ras_n (HPS_DDR3_RAS_N),
.memory_mem_cas_n (HPS_DDR3_CAS_N),
.memory_mem_we_n (HPS_DDR3_WE_N),
.memory_mem_reset_n (HPS_DDR3_RESET_N),
.memory_mem_dq (HPS_DDR3_DQ),
.memory_mem_dqs (HPS_DDR3_DQS_P),
.memory_mem_dqs_n (HPS_DDR3_DQS_N),
.memory_mem_odt (HPS_DDR3_ODT),
.memory_mem_dm (HPS_DDR3_DM),
.memory_oct_rzqin (HPS_DDR3_RZQ),
// Ethernet
.hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),
.hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),
.hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),
.hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),
.hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),
.hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),
.hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
.hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
.hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),
.hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),
.hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),
// Flash
.hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),
.hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),
.hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),
.hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),
.hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),
.hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),
// Accelerometer
.hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
//.adc_sclk (ADC_SCLK),
//.adc_cs_n (ADC_CS_N),
//.adc_dout (ADC_DOUT),
//.adc_din (ADC_DIN),
// General Purpose I/O
.hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
.hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),
// I2C
.hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
.hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT),
.hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK),
// Pushbutton
.hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),
// LED
.hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),
// SD Card
.hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),
.hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
.hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
.hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),
.hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
.hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),
// SPI
.hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK),
.hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI),
.hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO),
.hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS),
// UART
.hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),
.hps_io_hps_io_uart0_inst_TX (HPS_UART_TX),
// USB
.hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),
.hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),
.hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),
.hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),
.hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),
.hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),
.hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),
.hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),
.hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),
.hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),
.hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),
.hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT)
);
endmodule // DE1_SoC_Computer |
module butter_test();
reg rst, CLOCK_50;
reg [31:0] counter;
reg audio_input_ready;
// DDS update signal for testing
reg [31:0] dds_accum;
// DDS LUT
reg [31:0] sine_out;
wire [31:0] my_out;
// make reset
initial begin
counter = 32'b0;
CLOCK_50 = 1'b0;
audio_input_ready = 1'b0;
dds_accum = 32'd0;
sine_out = 32'h7fff_ffff;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#1000000
sine_out = ~sine_out;
end
always begin
#20813
audio_input_ready = 1;
#20
audio_input_ready = 0;
end
// update phase accumulator
// sync to audio data rate (48kHz) using audio_input_ready signal
/*always @(posedge CLOCK_50) begin //CLOCK_50
// Fout = (sample_rate)/(2^32)*(constant)
// then Fout=48000/(2^32)*(44739242) = 500 Hz
if (audio_input_ready) dds_accum <= dds_accum + 32'd44739242;
end*/
// DDS sine wave ROM
//sync_rom sineTable(CLOCK_50, dds_accum[31:24], sine_out);
//Filter: cutoff=0.145833
IIR6_32bit_fixed filter(
.audio_out (my_out),
.audio_in (sine_out),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(CLOCK_50),
.data_val(audio_input_ready),
.rst(rst),
.audio_out_val(audio_out_val)
); //end filter
endmodule |
module sync_rom (clock, address, sine);
input clock;
input [7:0] address;
output [15:0] sine;
reg signed [15:0] sine;
always@(posedge clock)
begin
case(address)
8'h00: sine = 16'h0000;
8'h01: sine = 16'h0192;
8'h02: sine = 16'h0323;
8'h03: sine = 16'h04b5;
8'h04: sine = 16'h0645;
8'h05: sine = 16'h07d5;
8'h06: sine = 16'h0963;
8'h07: sine = 16'h0af0;
8'h08: sine = 16'h0c7c;
8'h09: sine = 16'h0e05;
8'h0a: sine = 16'h0f8c;
8'h0b: sine = 16'h1111;
8'h0c: sine = 16'h1293;
8'h0d: sine = 16'h1413;
8'h0e: sine = 16'h158f;
8'h0f: sine = 16'h1708;
8'h10: sine = 16'h187d;
8'h11: sine = 16'h19ef;
8'h12: sine = 16'h1b5c;
8'h13: sine = 16'h1cc5;
8'h14: sine = 16'h1e2a;
8'h15: sine = 16'h1f8b;
8'h16: sine = 16'h20e6;
8'h17: sine = 16'h223c;
8'h18: sine = 16'h238d;
8'h19: sine = 16'h24d9;
8'h1a: sine = 16'h261f;
8'h1b: sine = 16'h275f;
8'h1c: sine = 16'h2899;
8'h1d: sine = 16'h29cc;
8'h1e: sine = 16'h2afa;
8'h1f: sine = 16'h2c20;
8'h20: sine = 16'h2d40;
8'h21: sine = 16'h2e59;
8'h22: sine = 16'h2f6b;
8'h23: sine = 16'h3075;
8'h24: sine = 16'h3178;
8'h25: sine = 16'h3273;
8'h26: sine = 16'h3366;
8'h27: sine = 16'h3452;
8'h28: sine = 16'h3535;
8'h29: sine = 16'h3611;
8'h2a: sine = 16'h36e4;
8'h2b: sine = 16'h37ae;
8'h2c: sine = 16'h3870;
8'h2d: sine = 16'h3929;
8'h2e: sine = 16'h39da;
8'h2f: sine = 16'h3a81;
8'h30: sine = 16'h3b1f;
8'h31: sine = 16'h3bb5;
8'h32: sine = 16'h3c41;
8'h33: sine = 16'h3cc4;
8'h34: sine = 16'h3d3d;
8'h35: sine = 16'h3dad;
8'h36: sine = 16'h3e14;
8'h37: sine = 16'h3e70;
8'h38: sine = 16'h3ec4;
8'h39: sine = 16'h3f0d;
8'h3a: sine = 16'h3f4d;
8'h3b: sine = 16'h3f83;
8'h3c: sine = 16'h3fb0;
8'h3d: sine = 16'h3fd2;
8'h3e: sine = 16'h3feb;
8'h3f: sine = 16'h3ffa;
8'h40: sine = 16'h3fff;
8'h41: sine = 16'h3ffa;
8'h42: sine = 16'h3feb;
8'h43: sine = 16'h3fd2;
8'h44: sine = 16'h3fb0;
8'h45: sine = 16'h3f83;
8'h46: sine = 16'h3f4d;
8'h47: sine = 16'h3f0d;
8'h48: sine = 16'h3ec4;
8'h49: sine = 16'h3e70;
8'h4a: sine = 16'h3e14;
8'h4b: sine = 16'h3dad;
8'h4c: sine = 16'h3d3d;
8'h4d: sine = 16'h3cc4;
8'h4e: sine = 16'h3c41;
8'h4f: sine = 16'h3bb5;
8'h50: sine = 16'h3b1f;
8'h51: sine = 16'h3a81;
8'h52: sine = 16'h39da;
8'h53: sine = 16'h3929;
8'h54: sine = 16'h3870;
8'h55: sine = 16'h37ae;
8'h56: sine = 16'h36e4;
8'h57: sine = 16'h3611;
8'h58: sine = 16'h3535;
8'h59: sine = 16'h3452;
8'h5a: sine = 16'h3366;
8'h5b: sine = 16'h3273;
8'h5c: sine = 16'h3178;
8'h5d: sine = 16'h3075;
8'h5e: sine = 16'h2f6b;
8'h5f: sine = 16'h2e59;
8'h60: sine = 16'h2d40;
8'h61: sine = 16'h2c20;
8'h62: sine = 16'h2afa;
8'h63: sine = 16'h29cc;
8'h64: sine = 16'h2899;
8'h65: sine = 16'h275f;
8'h66: sine = 16'h261f;
8'h67: sine = 16'h24d9;
8'h68: sine = 16'h238d;
8'h69: sine = 16'h223c;
8'h6a: sine = 16'h20e6;
8'h6b: sine = 16'h1f8b;
8'h6c: sine = 16'h1e2a;
8'h6d: sine = 16'h1cc5;
8'h6e: sine = 16'h1b5c;
8'h6f: sine = 16'h19ef;
8'h70: sine = 16'h187d;
8'h71: sine = 16'h1708;
8'h72: sine = 16'h158f;
8'h73: sine = 16'h1413;
8'h74: sine = 16'h1293;
8'h75: sine = 16'h1111;
8'h76: sine = 16'h0f8c;
8'h77: sine = 16'h0e05;
8'h78: sine = 16'h0c7c;
8'h79: sine = 16'h0af0;
8'h7a: sine = 16'h0963;
8'h7b: sine = 16'h07d5;
8'h7c: sine = 16'h0645;
8'h7d: sine = 16'h04b5;
8'h7e: sine = 16'h0323;
8'h7f: sine = 16'h0192;
8'h80: sine = 16'h0000;
8'h81: sine = 16'hfe6e;
8'h82: sine = 16'hfcdd;
8'h83: sine = 16'hfb4b;
8'h84: sine = 16'hf9bb;
8'h85: sine = 16'hf82b;
8'h86: sine = 16'hf69d;
8'h87: sine = 16'hf510;
8'h88: sine = 16'hf384;
8'h89: sine = 16'hf1fb;
8'h8a: sine = 16'hf074;
8'h8b: sine = 16'heeef;
8'h8c: sine = 16'hed6d;
8'h8d: sine = 16'hebed;
8'h8e: sine = 16'hea71;
8'h8f: sine = 16'he8f8;
8'h90: sine = 16'he783;
8'h91: sine = 16'he611;
8'h92: sine = 16'he4a4;
8'h93: sine = 16'he33b;
8'h94: sine = 16'he1d6;
8'h95: sine = 16'he075;
8'h96: sine = 16'hdf1a;
8'h97: sine = 16'hddc4;
8'h98: sine = 16'hdc73;
8'h99: sine = 16'hdb27;
8'h9a: sine = 16'hd9e1;
8'h9b: sine = 16'hd8a1;
8'h9c: sine = 16'hd767;
8'h9d: sine = 16'hd634;
8'h9e: sine = 16'hd506;
8'h9f: sine = 16'hd3e0;
8'ha0: sine = 16'hd2c0;
8'ha1: sine = 16'hd1a7;
8'ha2: sine = 16'hd095;
8'ha3: sine = 16'hcf8b;
8'ha4: sine = 16'hce88;
8'ha5: sine = 16'hcd8d;
8'ha6: sine = 16'hcc9a;
8'ha7: sine = 16'hcbae;
8'ha8: sine = 16'hcacb;
8'ha9: sine = 16'hc9ef;
8'haa: sine = 16'hc91c;
8'hab: sine = 16'hc852;
8'hac: sine = 16'hc790;
8'had: sine = 16'hc6d7;
8'hae: sine = 16'hc626;
8'haf: sine = 16'hc57f;
8'hb0: sine = 16'hc4e1;
8'hb1: sine = 16'hc44b;
8'hb2: sine = 16'hc3bf;
8'hb3: sine = 16'hc33c;
8'hb4: sine = 16'hc2c3;
8'hb5: sine = 16'hc253;
8'hb6: sine = 16'hc1ec;
8'hb7: sine = 16'hc190;
8'hb8: sine = 16'hc13c;
8'hb9: sine = 16'hc0f3;
8'hba: sine = 16'hc0b3;
8'hbb: sine = 16'hc07d;
8'hbc: sine = 16'hc050;
8'hbd: sine = 16'hc02e;
8'hbe: sine = 16'hc015;
8'hbf: sine = 16'hc006;
8'hc0: sine = 16'hc001;
8'hc1: sine = 16'hc006;
8'hc2: sine = 16'hc015;
8'hc3: sine = 16'hc02e;
8'hc4: sine = 16'hc050;
8'hc5: sine = 16'hc07d;
8'hc6: sine = 16'hc0b3;
8'hc7: sine = 16'hc0f3;
8'hc8: sine = 16'hc13c;
8'hc9: sine = 16'hc190;
8'hca: sine = 16'hc1ec;
8'hcb: sine = 16'hc253;
8'hcc: sine = 16'hc2c3;
8'hcd: sine = 16'hc33c;
8'hce: sine = 16'hc3bf;
8'hcf: sine = 16'hc44b;
8'hd0: sine = 16'hc4e1;
8'hd1: sine = 16'hc57f;
8'hd2: sine = 16'hc626;
8'hd3: sine = 16'hc6d7;
8'hd4: sine = 16'hc790;
8'hd5: sine = 16'hc852;
8'hd6: sine = 16'hc91c;
8'hd7: sine = 16'hc9ef;
8'hd8: sine = 16'hcacb;
8'hd9: sine = 16'hcbae;
8'hda: sine = 16'hcc9a;
8'hdb: sine = 16'hcd8d;
8'hdc: sine = 16'hce88;
8'hdd: sine = 16'hcf8b;
8'hde: sine = 16'hd095;
8'hdf: sine = 16'hd1a7;
8'he0: sine = 16'hd2c0;
8'he1: sine = 16'hd3e0;
8'he2: sine = 16'hd506;
8'he3: sine = 16'hd634;
8'he4: sine = 16'hd767;
8'he5: sine = 16'hd8a1;
8'he6: sine = 16'hd9e1;
8'he7: sine = 16'hdb27;
8'he8: sine = 16'hdc73;
8'he9: sine = 16'hddc4;
8'hea: sine = 16'hdf1a;
8'heb: sine = 16'he075;
8'hec: sine = 16'he1d6;
8'hed: sine = 16'he33b;
8'hee: sine = 16'he4a4;
8'hef: sine = 16'he611;
8'hf0: sine = 16'he783;
8'hf1: sine = 16'he8f8;
8'hf2: sine = 16'hea71;
8'hf3: sine = 16'hebed;
8'hf4: sine = 16'hed6d;
8'hf5: sine = 16'heeef;
8'hf6: sine = 16'hf074;
8'hf7: sine = 16'hf1fb;
8'hf8: sine = 16'hf384;
8'hf9: sine = 16'hf510;
8'hfa: sine = 16'hf69d;
8'hfb: sine = 16'hf82b;
8'hfc: sine = 16'hf9bb;
8'hfd: sine = 16'hfb4b;
8'hfe: sine = 16'hfcdd;
8'hff: sine = 16'hfe6e;
endcase
end
endmodule |
module RAM_512_18
#(parameter B = 1024)
(
output signed [31:0] q,
input signed [31:0] data,
input [($clog2(B)-1):0] wraddress, rdaddress,
input wren, rden, clock
);
reg [8:0] read_address_reg;
reg signed [31:0] mem [(B-1):0] /*synthesis ramstyle = M10K" */;
reg rden_reg;
always @(posedge clock) begin
if (wren)
mem[wraddress] <= data;
end
always @(posedge clock) begin
read_address_reg <= rdaddress;
rden_reg <= rden;
end
assign q = (rden_reg) ? mem[read_address_reg] : 0;
endmodule |
module buffer
#(parameter B=1024)
(
// inputs
clk,
rst,
delta,
new_sample_val,
new_sample_data,
out_sel,
delta_mode, // indicates whether to use fixed or varying delta
triangle_wave_max,
// outputs
pitch_shift_out,
pitch_shift_val
);
input clk, rst, new_sample_val, out_sel, delta_mode;
input [9:0] triangle_wave_max;
//input output_filter_ack;
// pitch-shift amount
input [31:0] delta; // 3.29 format
// audio in
input signed [31:0] new_sample_data;
reg signed [31:0] new_sample_data_reg;
// enables
reg rb1_rden, rb2_rden, rb1_wren, rb2_wren;
// fractional index for pitch shifting (see MATLAB model)
reg [$clog2(B)+28:0] rb1_index; //$clog2(B).29 format
reg [$clog2(B)+28:0] rb2_index;
// actual read address
reg [$clog2(B)-1:0] rb1_read_addr;
reg [$clog2(B)-1:0] rb2_read_addr;
// write address
reg [$clog2(B)-1:0] rb1_write_addr;
reg [$clog2(B)-1:0] rb2_write_addr;
// read data
wire signed [31:0] rb1_read_out;
wire signed [31:0] rb2_read_out;
// state 0 = waiting for new sample
// state 1 =
reg [2:0] state;
// needed for two delta modes
wire [31:0] delta_effective; //or reg?
reg [9:0] delta_rom_addr;
reg [9:0] delta_counter;
wire [31:0] delta_rom_out;
// output interface for next unit
output signed [31:0] pitch_shift_out;
output signed [31:0] pitch_shift_val;
assign pitch_shift_out = (out_sel) ? rb1_read_out
: ((rb1_read_out >>> 1) + (rb2_read_out >>> 1));
assign pitch_shift_val = (state == 3'd2) ? 1'b1 : 1'b0;
// delta_mode = 1 => use input delta
assign delta_effective = (delta_mode) ? delta : delta_rom_out;
RAM_512_18 #(B) rb1
(
.clock(clk),
.q(rb1_read_out),
.rdaddress(rb1_read_addr),
.data(new_sample_data_reg),
.wraddress(rb1_write_addr),
.wren(rb1_wren),
.rden(rb1_rden)
);
RAM_512_18 #(B) rb2
(
.clock(clk),
.q(rb2_read_out),
.rdaddress(rb2_read_addr),
.data(new_sample_data_reg),
.wraddress(rb1_write_addr),
.wren(rb2_wren),
.rden(rb2_rden)
);
// ROM for time varying delta
delta_rom d1 (.clock(clk),
.address(delta_rom_addr),
.delta_out(delta_rom_out));
always @ (posedge clk) begin
if (rst) begin
state <= 3'd0;
rb1_index <= 0;
rb2_index <= 0;
rb1_write_addr <= 0;
rb2_write_addr <= (B/2);
rb1_read_addr <= 0;
rb2_read_addr <= 0;
new_sample_data_reg <= 0;
rb1_rden <= 0;
rb2_rden <= 0;
rb1_wren <= 0;
rb2_wren <= 0;
delta_counter <= 0;
delta_rom_addr <= 0;
end
else if ((state == 3'd0) && new_sample_val) begin
new_sample_data_reg <= new_sample_data;
// increment write addr, modulo rb size
rb1_write_addr <= (rb1_write_addr == (B - 1)) ? 0 : (rb1_write_addr + 1);
rb2_write_addr <= (rb2_write_addr == (B - 1)) ? 0 : (rb2_write_addr + 1);
// update fractional index, modulo rb size
rb1_index <= (rb1_index + delta_effective);
rb2_index <= (rb2_index + delta_effective);
// only take integer part for read address
rb1_read_addr <= rb1_index[$clog2(B)+28 : 29];
rb2_read_addr <= rb2_index[$clog2(B)+28 : 29];
rb1_rden <= 1;
rb2_rden <= 1;
rb1_wren <= 1;
rb2_wren <= 1;
state <= 3'd1;
end
else if ((state == 3'd1)) begin
// done writing
rb1_wren <= 0;
rb2_wren <= 0;
state <= 3'd2;
end
else if ((state == 3'd2)) begin
// done reading
// read_buffer_val is set to one (combinational above)
rb1_rden <= 0;
rb2_rden <= 0;
state <= 3'd0;
// stay on each delta sample for 188 reads (total period of 1sec), then
// go to next address in ROM, restart from address 0 when necessary
delta_counter <= (delta_counter == triangle_wave_max) ? 10'd0
: (delta_counter + 10'd1);
delta_rom_addr <= (delta_counter == triangle_wave_max) ?
((delta_rom_addr == 10'd513 ) ? 10'd0
: (delta_rom_addr + 10'd1)) : delta_rom_addr;
end
else begin
// don't do anything
rb1_rden <= 0;
rb2_rden <= 0;
rb1_wren <= 0;
rb2_wren <= 0;
end
end
endmodule |
module project_top();
reg rst, clk;
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
reg bus_ack; // Avalon bus raises this when done
reg [31:0] bus_read_data; // data from Avalon bus
reg [31:0] counter;
wire [31:0] audio_fifo_address = 32'h00003044; // Avalon address +4
wire [31:0] audio_left_address = 32'h00003048; // Avalon address +8
wire [31:0] audio_right_address = 32'h0000304c; // Avalon address +12
// make reset
initial begin
bus_read_data = 32'b0;
counter = 32'b0;
clk = 1'b0;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
clk = !clk;
end
always @(posedge clk) begin
// fake bus acjs
bus_ack <= bus_write | bus_read;
end
always @(posedge bus_read) begin
// fake bus reads
if (bus_addr == audio_fifo_address) begin
bus_read_data <= (8'd3 << 24) | 8'd2; // allow reads and writes
end
else if ((bus_addr == audio_right_address)) begin
counter <= counter + 1;
bus_read_data <= counter;
end
end
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(clk),
.rst(rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data)
);
endmodule |
module delta_rom (clock, address, delta_out);
input clock;
input [9:0] address;
output [31:0] delta_out;
reg [31:0] delta_out;
always@(posedge clock)
begin
case(address)
10'd0: delta_out = 32'b00010000000000000000000000000000;
10'd1: delta_out = 32'b00010000001000000000000000000000;
10'd2: delta_out = 32'b00010000010000000000000000000000;
10'd3: delta_out = 32'b00010000011000000000000000000000;
10'd4: delta_out = 32'b00010000100000000000000000000000;
10'd5: delta_out = 32'b00010000101000000000000000000000;
10'd6: delta_out = 32'b00010000110000000000000000000000;
10'd7: delta_out = 32'b00010000111000000000000000000000;
10'd8: delta_out = 32'b00010001000000000000000000000000;
10'd9: delta_out = 32'b00010001001000000000000000000000;
10'd10: delta_out = 32'b00010001010000000000000000000000;
10'd11: delta_out = 32'b00010001011000000000000000000000;
10'd12: delta_out = 32'b00010001100000000000000000000000;
10'd13: delta_out = 32'b00010001101000000000000000000000;
10'd14: delta_out = 32'b00010001110000000000000000000000;
10'd15: delta_out = 32'b00010001111000000000000000000000;
10'd16: delta_out = 32'b00010010000000000000000000000000;
10'd17: delta_out = 32'b00010010001000000000000000000000;
10'd18: delta_out = 32'b00010010010000000000000000000000;
10'd19: delta_out = 32'b00010010011000000000000000000000;
10'd20: delta_out = 32'b00010010100000000000000000000000;
10'd21: delta_out = 32'b00010010101000000000000000000000;
10'd22: delta_out = 32'b00010010110000000000000000000000;
10'd23: delta_out = 32'b00010010111000000000000000000000;
10'd24: delta_out = 32'b00010011000000000000000000000000;
10'd25: delta_out = 32'b00010011001000000000000000000000;
10'd26: delta_out = 32'b00010011010000000000000000000000;
10'd27: delta_out = 32'b00010011011000000000000000000000;
10'd28: delta_out = 32'b00010011100000000000000000000000;
10'd29: delta_out = 32'b00010011101000000000000000000000;
10'd30: delta_out = 32'b00010011110000000000000000000000;
10'd31: delta_out = 32'b00010011111000000000000000000000;
10'd32: delta_out = 32'b00010100000000000000000000000000;
10'd33: delta_out = 32'b00010100001000000000000000000000;
10'd34: delta_out = 32'b00010100010000000000000000000000;
10'd35: delta_out = 32'b00010100011000000000000000000000;
10'd36: delta_out = 32'b00010100100000000000000000000000;
10'd37: delta_out = 32'b00010100101000000000000000000000;
10'd38: delta_out = 32'b00010100110000000000000000000000;
10'd39: delta_out = 32'b00010100111000000000000000000000;
10'd40: delta_out = 32'b00010101000000000000000000000000;
10'd41: delta_out = 32'b00010101001000000000000000000000;
10'd42: delta_out = 32'b00010101010000000000000000000000;
10'd43: delta_out = 32'b00010101011000000000000000000000;
10'd44: delta_out = 32'b00010101100000000000000000000000;
10'd45: delta_out = 32'b00010101101000000000000000000000;
10'd46: delta_out = 32'b00010101110000000000000000000000;
10'd47: delta_out = 32'b00010101111000000000000000000000;
10'd48: delta_out = 32'b00010110000000000000000000000000;
10'd49: delta_out = 32'b00010110001000000000000000000000;
10'd50: delta_out = 32'b00010110010000000000000000000000;
10'd51: delta_out = 32'b00010110011000000000000000000000;
10'd52: delta_out = 32'b00010110100000000000000000000000;
10'd53: delta_out = 32'b00010110101000000000000000000000;
10'd54: delta_out = 32'b00010110110000000000000000000000;
10'd55: delta_out = 32'b00010110111000000000000000000000;
10'd56: delta_out = 32'b00010111000000000000000000000000;
10'd57: delta_out = 32'b00010111001000000000000000000000;
10'd58: delta_out = 32'b00010111010000000000000000000000;
10'd59: delta_out = 32'b00010111011000000000000000000000;
10'd60: delta_out = 32'b00010111100000000000000000000000;
10'd61: delta_out = 32'b00010111101000000000000000000000;
10'd62: delta_out = 32'b00010111110000000000000000000000;
10'd63: delta_out = 32'b00010111111000000000000000000000;
10'd64: delta_out = 32'b00011000000000000000000000000000;
10'd65: delta_out = 32'b00011000001000000000000000000000;
10'd66: delta_out = 32'b00011000010000000000000000000000;
10'd67: delta_out = 32'b00011000011000000000000000000000;
10'd68: delta_out = 32'b00011000100000000000000000000000;
10'd69: delta_out = 32'b00011000101000000000000000000000;
10'd70: delta_out = 32'b00011000110000000000000000000000;
10'd71: delta_out = 32'b00011000111000000000000000000000;
10'd72: delta_out = 32'b00011001000000000000000000000000;
10'd73: delta_out = 32'b00011001001000000000000000000000;
10'd74: delta_out = 32'b00011001010000000000000000000000;
10'd75: delta_out = 32'b00011001011000000000000000000000;
10'd76: delta_out = 32'b00011001100000000000000000000000;
10'd77: delta_out = 32'b00011001101000000000000000000000;
10'd78: delta_out = 32'b00011001110000000000000000000000;
10'd79: delta_out = 32'b00011001111000000000000000000000;
10'd80: delta_out = 32'b00011010000000000000000000000000;
10'd81: delta_out = 32'b00011010001000000000000000000000;
10'd82: delta_out = 32'b00011010010000000000000000000000;
10'd83: delta_out = 32'b00011010011000000000000000000000;
10'd84: delta_out = 32'b00011010100000000000000000000000;
10'd85: delta_out = 32'b00011010101000000000000000000000;
10'd86: delta_out = 32'b00011010110000000000000000000000;
10'd87: delta_out = 32'b00011010111000000000000000000000;
10'd88: delta_out = 32'b00011011000000000000000000000000;
10'd89: delta_out = 32'b00011011001000000000000000000000;
10'd90: delta_out = 32'b00011011010000000000000000000000;
10'd91: delta_out = 32'b00011011011000000000000000000000;
10'd92: delta_out = 32'b00011011100000000000000000000000;
10'd93: delta_out = 32'b00011011101000000000000000000000;
10'd94: delta_out = 32'b00011011110000000000000000000000;
10'd95: delta_out = 32'b00011011111000000000000000000000;
10'd96: delta_out = 32'b00011100000000000000000000000000;
10'd97: delta_out = 32'b00011100001000000000000000000000;
10'd98: delta_out = 32'b00011100010000000000000000000000;
10'd99: delta_out = 32'b00011100011000000000000000000000;
10'd100: delta_out = 32'b00011100100000000000000000000000;
10'd101: delta_out = 32'b00011100101000000000000000000000;
10'd102: delta_out = 32'b00011100110000000000000000000000;
10'd103: delta_out = 32'b00011100111000000000000000000000;
10'd104: delta_out = 32'b00011101000000000000000000000000;
10'd105: delta_out = 32'b00011101001000000000000000000000;
10'd106: delta_out = 32'b00011101010000000000000000000000;
10'd107: delta_out = 32'b00011101011000000000000000000000;
10'd108: delta_out = 32'b00011101100000000000000000000000;
10'd109: delta_out = 32'b00011101101000000000000000000000;
10'd110: delta_out = 32'b00011101110000000000000000000000;
10'd111: delta_out = 32'b00011101111000000000000000000000;
10'd112: delta_out = 32'b00011110000000000000000000000000;
10'd113: delta_out = 32'b00011110001000000000000000000000;
10'd114: delta_out = 32'b00011110010000000000000000000000;
10'd115: delta_out = 32'b00011110011000000000000000000000;
10'd116: delta_out = 32'b00011110100000000000000000000000;
10'd117: delta_out = 32'b00011110101000000000000000000000;
10'd118: delta_out = 32'b00011110110000000000000000000000;
10'd119: delta_out = 32'b00011110111000000000000000000000;
10'd120: delta_out = 32'b00011111000000000000000000000000;
10'd121: delta_out = 32'b00011111001000000000000000000000;
10'd122: delta_out = 32'b00011111010000000000000000000000;
10'd123: delta_out = 32'b00011111011000000000000000000000;
10'd124: delta_out = 32'b00011111100000000000000000000000;
10'd125: delta_out = 32'b00011111101000000000000000000000;
10'd126: delta_out = 32'b00011111110000000000000000000000;
10'd127: delta_out = 32'b00011111111000000000000000000000;
10'd128: delta_out = 32'b00100000000000000000000000000000;
10'd129: delta_out = 32'b00100000001000000000000000000000;
10'd130: delta_out = 32'b00100000010000000000000000000000;
10'd131: delta_out = 32'b00100000011000000000000000000000;
10'd132: delta_out = 32'b00100000100000000000000000000000;
10'd133: delta_out = 32'b00100000101000000000000000000000;
10'd134: delta_out = 32'b00100000110000000000000000000000;
10'd135: delta_out = 32'b00100000111000000000000000000000;
10'd136: delta_out = 32'b00100001000000000000000000000000;
10'd137: delta_out = 32'b00100001001000000000000000000000;
10'd138: delta_out = 32'b00100001010000000000000000000000;
10'd139: delta_out = 32'b00100001011000000000000000000000;
10'd140: delta_out = 32'b00100001100000000000000000000000;
10'd141: delta_out = 32'b00100001101000000000000000000000;
10'd142: delta_out = 32'b00100001110000000000000000000000;
10'd143: delta_out = 32'b00100001111000000000000000000000;
10'd144: delta_out = 32'b00100010000000000000000000000000;
10'd145: delta_out = 32'b00100010001000000000000000000000;
10'd146: delta_out = 32'b00100010010000000000000000000000;
10'd147: delta_out = 32'b00100010011000000000000000000000;
10'd148: delta_out = 32'b00100010100000000000000000000000;
10'd149: delta_out = 32'b00100010101000000000000000000000;
10'd150: delta_out = 32'b00100010110000000000000000000000;
10'd151: delta_out = 32'b00100010111000000000000000000000;
10'd152: delta_out = 32'b00100011000000000000000000000000;
10'd153: delta_out = 32'b00100011001000000000000000000000;
10'd154: delta_out = 32'b00100011010000000000000000000000;
10'd155: delta_out = 32'b00100011011000000000000000000000;
10'd156: delta_out = 32'b00100011100000000000000000000000;
10'd157: delta_out = 32'b00100011101000000000000000000000;
10'd158: delta_out = 32'b00100011110000000000000000000000;
10'd159: delta_out = 32'b00100011111000000000000000000000;
10'd160: delta_out = 32'b00100100000000000000000000000000;
10'd161: delta_out = 32'b00100100001000000000000000000000;
10'd162: delta_out = 32'b00100100010000000000000000000000;
10'd163: delta_out = 32'b00100100011000000000000000000000;
10'd164: delta_out = 32'b00100100100000000000000000000000;
10'd165: delta_out = 32'b00100100101000000000000000000000;
10'd166: delta_out = 32'b00100100110000000000000000000000;
10'd167: delta_out = 32'b00100100111000000000000000000000;
10'd168: delta_out = 32'b00100101000000000000000000000000;
10'd169: delta_out = 32'b00100101001000000000000000000000;
10'd170: delta_out = 32'b00100101010000000000000000000000;
10'd171: delta_out = 32'b00100101011000000000000000000000;
10'd172: delta_out = 32'b00100101100000000000000000000000;
10'd173: delta_out = 32'b00100101101000000000000000000000;
10'd174: delta_out = 32'b00100101110000000000000000000000;
10'd175: delta_out = 32'b00100101111000000000000000000000;
10'd176: delta_out = 32'b00100110000000000000000000000000;
10'd177: delta_out = 32'b00100110001000000000000000000000;
10'd178: delta_out = 32'b00100110010000000000000000000000;
10'd179: delta_out = 32'b00100110011000000000000000000000;
10'd180: delta_out = 32'b00100110100000000000000000000000;
10'd181: delta_out = 32'b00100110101000000000000000000000;
10'd182: delta_out = 32'b00100110110000000000000000000000;
10'd183: delta_out = 32'b00100110111000000000000000000000;
10'd184: delta_out = 32'b00100111000000000000000000000000;
10'd185: delta_out = 32'b00100111001000000000000000000000;
10'd186: delta_out = 32'b00100111010000000000000000000000;
10'd187: delta_out = 32'b00100111011000000000000000000000;
10'd188: delta_out = 32'b00100111100000000000000000000000;
10'd189: delta_out = 32'b00100111101000000000000000000000;
10'd190: delta_out = 32'b00100111110000000000000000000000;
10'd191: delta_out = 32'b00100111111000000000000000000000;
10'd192: delta_out = 32'b00101000000000000000000000000000;
10'd193: delta_out = 32'b00101000001000000000000000000000;
10'd194: delta_out = 32'b00101000010000000000000000000000;
10'd195: delta_out = 32'b00101000011000000000000000000000;
10'd196: delta_out = 32'b00101000100000000000000000000000;
10'd197: delta_out = 32'b00101000101000000000000000000000;
10'd198: delta_out = 32'b00101000110000000000000000000000;
10'd199: delta_out = 32'b00101000111000000000000000000000;
10'd200: delta_out = 32'b00101001000000000000000000000000;
10'd201: delta_out = 32'b00101001001000000000000000000000;
10'd202: delta_out = 32'b00101001010000000000000000000000;
10'd203: delta_out = 32'b00101001011000000000000000000000;
10'd204: delta_out = 32'b00101001100000000000000000000000;
10'd205: delta_out = 32'b00101001101000000000000000000000;
10'd206: delta_out = 32'b00101001110000000000000000000000;
10'd207: delta_out = 32'b00101001111000000000000000000000;
10'd208: delta_out = 32'b00101010000000000000000000000000;
10'd209: delta_out = 32'b00101010001000000000000000000000;
10'd210: delta_out = 32'b00101010010000000000000000000000;
10'd211: delta_out = 32'b00101010011000000000000000000000;
10'd212: delta_out = 32'b00101010100000000000000000000000;
10'd213: delta_out = 32'b00101010101000000000000000000000;
10'd214: delta_out = 32'b00101010110000000000000000000000;
10'd215: delta_out = 32'b00101010111000000000000000000000;
10'd216: delta_out = 32'b00101011000000000000000000000000;
10'd217: delta_out = 32'b00101011001000000000000000000000;
10'd218: delta_out = 32'b00101011010000000000000000000000;
10'd219: delta_out = 32'b00101011011000000000000000000000;
10'd220: delta_out = 32'b00101011100000000000000000000000;
10'd221: delta_out = 32'b00101011101000000000000000000000;
10'd222: delta_out = 32'b00101011110000000000000000000000;
10'd223: delta_out = 32'b00101011111000000000000000000000;
10'd224: delta_out = 32'b00101100000000000000000000000000;
10'd225: delta_out = 32'b00101100001000000000000000000000;
10'd226: delta_out = 32'b00101100010000000000000000000000;
10'd227: delta_out = 32'b00101100011000000000000000000000;
10'd228: delta_out = 32'b00101100100000000000000000000000;
10'd229: delta_out = 32'b00101100101000000000000000000000;
10'd230: delta_out = 32'b00101100110000000000000000000000;
10'd231: delta_out = 32'b00101100111000000000000000000000;
10'd232: delta_out = 32'b00101101000000000000000000000000;
10'd233: delta_out = 32'b00101101001000000000000000000000;
10'd234: delta_out = 32'b00101101010000000000000000000000;
10'd235: delta_out = 32'b00101101011000000000000000000000;
10'd236: delta_out = 32'b00101101100000000000000000000000;
10'd237: delta_out = 32'b00101101101000000000000000000000;
10'd238: delta_out = 32'b00101101110000000000000000000000;
10'd239: delta_out = 32'b00101101111000000000000000000000;
10'd240: delta_out = 32'b00101110000000000000000000000000;
10'd241: delta_out = 32'b00101110001000000000000000000000;
10'd242: delta_out = 32'b00101110010000000000000000000000;
10'd243: delta_out = 32'b00101110011000000000000000000000;
10'd244: delta_out = 32'b00101110100000000000000000000000;
10'd245: delta_out = 32'b00101110101000000000000000000000;
10'd246: delta_out = 32'b00101110110000000000000000000000;
10'd247: delta_out = 32'b00101110111000000000000000000000;
10'd248: delta_out = 32'b00101111000000000000000000000000;
10'd249: delta_out = 32'b00101111001000000000000000000000;
10'd250: delta_out = 32'b00101111010000000000000000000000;
10'd251: delta_out = 32'b00101111011000000000000000000000;
10'd252: delta_out = 32'b00101111100000000000000000000000;
10'd253: delta_out = 32'b00101111101000000000000000000000;
10'd254: delta_out = 32'b00101111110000000000000000000000;
10'd255: delta_out = 32'b00101111111000000000000000000000;
10'd256: delta_out = 32'b00110000000000000000000000000000;
10'd257: delta_out = 32'b00101111111000000000000000000000;
10'd258: delta_out = 32'b00101111110000000000000000000000;
10'd259: delta_out = 32'b00101111101000000000000000000000;
10'd260: delta_out = 32'b00101111100000000000000000000000;
10'd261: delta_out = 32'b00101111011000000000000000000000;
10'd262: delta_out = 32'b00101111010000000000000000000000;
10'd263: delta_out = 32'b00101111001000000000000000000000;
10'd264: delta_out = 32'b00101111000000000000000000000000;
10'd265: delta_out = 32'b00101110111000000000000000000000;
10'd266: delta_out = 32'b00101110110000000000000000000000;
10'd267: delta_out = 32'b00101110101000000000000000000000;
10'd268: delta_out = 32'b00101110100000000000000000000000;
10'd269: delta_out = 32'b00101110011000000000000000000000;
10'd270: delta_out = 32'b00101110010000000000000000000000;
10'd271: delta_out = 32'b00101110001000000000000000000000;
10'd272: delta_out = 32'b00101110000000000000000000000000;
10'd273: delta_out = 32'b00101101111000000000000000000000;
10'd274: delta_out = 32'b00101101110000000000000000000000;
10'd275: delta_out = 32'b00101101101000000000000000000000;
10'd276: delta_out = 32'b00101101100000000000000000000000;
10'd277: delta_out = 32'b00101101011000000000000000000000;
10'd278: delta_out = 32'b00101101010000000000000000000000;
10'd279: delta_out = 32'b00101101001000000000000000000000;
10'd280: delta_out = 32'b00101101000000000000000000000000;
10'd281: delta_out = 32'b00101100111000000000000000000000;
10'd282: delta_out = 32'b00101100110000000000000000000000;
10'd283: delta_out = 32'b00101100101000000000000000000000;
10'd284: delta_out = 32'b00101100100000000000000000000000;
10'd285: delta_out = 32'b00101100011000000000000000000000;
10'd286: delta_out = 32'b00101100010000000000000000000000;
10'd287: delta_out = 32'b00101100001000000000000000000000;
10'd288: delta_out = 32'b00101100000000000000000000000000;
10'd289: delta_out = 32'b00101011111000000000000000000000;
10'd290: delta_out = 32'b00101011110000000000000000000000;
10'd291: delta_out = 32'b00101011101000000000000000000000;
10'd292: delta_out = 32'b00101011100000000000000000000000;
10'd293: delta_out = 32'b00101011011000000000000000000000;
10'd294: delta_out = 32'b00101011010000000000000000000000;
10'd295: delta_out = 32'b00101011001000000000000000000000;
10'd296: delta_out = 32'b00101011000000000000000000000000;
10'd297: delta_out = 32'b00101010111000000000000000000000;
10'd298: delta_out = 32'b00101010110000000000000000000000;
10'd299: delta_out = 32'b00101010101000000000000000000000;
10'd300: delta_out = 32'b00101010100000000000000000000000;
10'd301: delta_out = 32'b00101010011000000000000000000000;
10'd302: delta_out = 32'b00101010010000000000000000000000;
10'd303: delta_out = 32'b00101010001000000000000000000000;
10'd304: delta_out = 32'b00101010000000000000000000000000;
10'd305: delta_out = 32'b00101001111000000000000000000000;
10'd306: delta_out = 32'b00101001110000000000000000000000;
10'd307: delta_out = 32'b00101001101000000000000000000000;
10'd308: delta_out = 32'b00101001100000000000000000000000;
10'd309: delta_out = 32'b00101001011000000000000000000000;
10'd310: delta_out = 32'b00101001010000000000000000000000;
10'd311: delta_out = 32'b00101001001000000000000000000000;
10'd312: delta_out = 32'b00101001000000000000000000000000;
10'd313: delta_out = 32'b00101000111000000000000000000000;
10'd314: delta_out = 32'b00101000110000000000000000000000;
10'd315: delta_out = 32'b00101000101000000000000000000000;
10'd316: delta_out = 32'b00101000100000000000000000000000;
10'd317: delta_out = 32'b00101000011000000000000000000000;
10'd318: delta_out = 32'b00101000010000000000000000000000;
10'd319: delta_out = 32'b00101000001000000000000000000000;
10'd320: delta_out = 32'b00101000000000000000000000000000;
10'd321: delta_out = 32'b00100111111000000000000000000000;
10'd322: delta_out = 32'b00100111110000000000000000000000;
10'd323: delta_out = 32'b00100111101000000000000000000000;
10'd324: delta_out = 32'b00100111100000000000000000000000;
10'd325: delta_out = 32'b00100111011000000000000000000000;
10'd326: delta_out = 32'b00100111010000000000000000000000;
10'd327: delta_out = 32'b00100111001000000000000000000000;
10'd328: delta_out = 32'b00100111000000000000000000000000;
10'd329: delta_out = 32'b00100110111000000000000000000000;
10'd330: delta_out = 32'b00100110110000000000000000000000;
10'd331: delta_out = 32'b00100110101000000000000000000000;
10'd332: delta_out = 32'b00100110100000000000000000000000;
10'd333: delta_out = 32'b00100110011000000000000000000000;
10'd334: delta_out = 32'b00100110010000000000000000000000;
10'd335: delta_out = 32'b00100110001000000000000000000000;
10'd336: delta_out = 32'b00100110000000000000000000000000;
10'd337: delta_out = 32'b00100101111000000000000000000000;
10'd338: delta_out = 32'b00100101110000000000000000000000;
10'd339: delta_out = 32'b00100101101000000000000000000000;
10'd340: delta_out = 32'b00100101100000000000000000000000;
10'd341: delta_out = 32'b00100101011000000000000000000000;
10'd342: delta_out = 32'b00100101010000000000000000000000;
10'd343: delta_out = 32'b00100101001000000000000000000000;
10'd344: delta_out = 32'b00100101000000000000000000000000;
10'd345: delta_out = 32'b00100100111000000000000000000000;
10'd346: delta_out = 32'b00100100110000000000000000000000;
10'd347: delta_out = 32'b00100100101000000000000000000000;
10'd348: delta_out = 32'b00100100100000000000000000000000;
10'd349: delta_out = 32'b00100100011000000000000000000000;
10'd350: delta_out = 32'b00100100010000000000000000000000;
10'd351: delta_out = 32'b00100100001000000000000000000000;
10'd352: delta_out = 32'b00100100000000000000000000000000;
10'd353: delta_out = 32'b00100011111000000000000000000000;
10'd354: delta_out = 32'b00100011110000000000000000000000;
10'd355: delta_out = 32'b00100011101000000000000000000000;
10'd356: delta_out = 32'b00100011100000000000000000000000;
10'd357: delta_out = 32'b00100011011000000000000000000000;
10'd358: delta_out = 32'b00100011010000000000000000000000;
10'd359: delta_out = 32'b00100011001000000000000000000000;
10'd360: delta_out = 32'b00100011000000000000000000000000;
10'd361: delta_out = 32'b00100010111000000000000000000000;
10'd362: delta_out = 32'b00100010110000000000000000000000;
10'd363: delta_out = 32'b00100010101000000000000000000000;
10'd364: delta_out = 32'b00100010100000000000000000000000;
10'd365: delta_out = 32'b00100010011000000000000000000000;
10'd366: delta_out = 32'b00100010010000000000000000000000;
10'd367: delta_out = 32'b00100010001000000000000000000000;
10'd368: delta_out = 32'b00100010000000000000000000000000;
10'd369: delta_out = 32'b00100001111000000000000000000000;
10'd370: delta_out = 32'b00100001110000000000000000000000;
10'd371: delta_out = 32'b00100001101000000000000000000000;
10'd372: delta_out = 32'b00100001100000000000000000000000;
10'd373: delta_out = 32'b00100001011000000000000000000000;
10'd374: delta_out = 32'b00100001010000000000000000000000;
10'd375: delta_out = 32'b00100001001000000000000000000000;
10'd376: delta_out = 32'b00100001000000000000000000000000;
10'd377: delta_out = 32'b00100000111000000000000000000000;
10'd378: delta_out = 32'b00100000110000000000000000000000;
10'd379: delta_out = 32'b00100000101000000000000000000000;
10'd380: delta_out = 32'b00100000100000000000000000000000;
10'd381: delta_out = 32'b00100000011000000000000000000000;
10'd382: delta_out = 32'b00100000010000000000000000000000;
10'd383: delta_out = 32'b00100000001000000000000000000000;
10'd384: delta_out = 32'b00100000000000000000000000000000;
10'd385: delta_out = 32'b00011111111000000000000000000000;
10'd386: delta_out = 32'b00011111110000000000000000000000;
10'd387: delta_out = 32'b00011111101000000000000000000000;
10'd388: delta_out = 32'b00011111100000000000000000000000;
10'd389: delta_out = 32'b00011111011000000000000000000000;
10'd390: delta_out = 32'b00011111010000000000000000000000;
10'd391: delta_out = 32'b00011111001000000000000000000000;
10'd392: delta_out = 32'b00011111000000000000000000000000;
10'd393: delta_out = 32'b00011110111000000000000000000000;
10'd394: delta_out = 32'b00011110110000000000000000000000;
10'd395: delta_out = 32'b00011110101000000000000000000000;
10'd396: delta_out = 32'b00011110100000000000000000000000;
10'd397: delta_out = 32'b00011110011000000000000000000000;
10'd398: delta_out = 32'b00011110010000000000000000000000;
10'd399: delta_out = 32'b00011110001000000000000000000000;
10'd400: delta_out = 32'b00011110000000000000000000000000;
10'd401: delta_out = 32'b00011101111000000000000000000000;
10'd402: delta_out = 32'b00011101110000000000000000000000;
10'd403: delta_out = 32'b00011101101000000000000000000000;
10'd404: delta_out = 32'b00011101100000000000000000000000;
10'd405: delta_out = 32'b00011101011000000000000000000000;
10'd406: delta_out = 32'b00011101010000000000000000000000;
10'd407: delta_out = 32'b00011101001000000000000000000000;
10'd408: delta_out = 32'b00011101000000000000000000000000;
10'd409: delta_out = 32'b00011100111000000000000000000000;
10'd410: delta_out = 32'b00011100110000000000000000000000;
10'd411: delta_out = 32'b00011100101000000000000000000000;
10'd412: delta_out = 32'b00011100100000000000000000000000;
10'd413: delta_out = 32'b00011100011000000000000000000000;
10'd414: delta_out = 32'b00011100010000000000000000000000;
10'd415: delta_out = 32'b00011100001000000000000000000000;
10'd416: delta_out = 32'b00011100000000000000000000000000;
10'd417: delta_out = 32'b00011011111000000000000000000000;
10'd418: delta_out = 32'b00011011110000000000000000000000;
10'd419: delta_out = 32'b00011011101000000000000000000000;
10'd420: delta_out = 32'b00011011100000000000000000000000;
10'd421: delta_out = 32'b00011011011000000000000000000000;
10'd422: delta_out = 32'b00011011010000000000000000000000;
10'd423: delta_out = 32'b00011011001000000000000000000000;
10'd424: delta_out = 32'b00011011000000000000000000000000;
10'd425: delta_out = 32'b00011010111000000000000000000000;
10'd426: delta_out = 32'b00011010110000000000000000000000;
10'd427: delta_out = 32'b00011010101000000000000000000000;
10'd428: delta_out = 32'b00011010100000000000000000000000;
10'd429: delta_out = 32'b00011010011000000000000000000000;
10'd430: delta_out = 32'b00011010010000000000000000000000;
10'd431: delta_out = 32'b00011010001000000000000000000000;
10'd432: delta_out = 32'b00011010000000000000000000000000;
10'd433: delta_out = 32'b00011001111000000000000000000000;
10'd434: delta_out = 32'b00011001110000000000000000000000;
10'd435: delta_out = 32'b00011001101000000000000000000000;
10'd436: delta_out = 32'b00011001100000000000000000000000;
10'd437: delta_out = 32'b00011001011000000000000000000000;
10'd438: delta_out = 32'b00011001010000000000000000000000;
10'd439: delta_out = 32'b00011001001000000000000000000000;
10'd440: delta_out = 32'b00011001000000000000000000000000;
10'd441: delta_out = 32'b00011000111000000000000000000000;
10'd442: delta_out = 32'b00011000110000000000000000000000;
10'd443: delta_out = 32'b00011000101000000000000000000000;
10'd444: delta_out = 32'b00011000100000000000000000000000;
10'd445: delta_out = 32'b00011000011000000000000000000000;
10'd446: delta_out = 32'b00011000010000000000000000000000;
10'd447: delta_out = 32'b00011000001000000000000000000000;
10'd448: delta_out = 32'b00011000000000000000000000000000;
10'd449: delta_out = 32'b00010111111000000000000000000000;
10'd450: delta_out = 32'b00010111110000000000000000000000;
10'd451: delta_out = 32'b00010111101000000000000000000000;
10'd452: delta_out = 32'b00010111100000000000000000000000;
10'd453: delta_out = 32'b00010111011000000000000000000000;
10'd454: delta_out = 32'b00010111010000000000000000000000;
10'd455: delta_out = 32'b00010111001000000000000000000000;
10'd456: delta_out = 32'b00010111000000000000000000000000;
10'd457: delta_out = 32'b00010110111000000000000000000000;
10'd458: delta_out = 32'b00010110110000000000000000000000;
10'd459: delta_out = 32'b00010110101000000000000000000000;
10'd460: delta_out = 32'b00010110100000000000000000000000;
10'd461: delta_out = 32'b00010110011000000000000000000000;
10'd462: delta_out = 32'b00010110010000000000000000000000;
10'd463: delta_out = 32'b00010110001000000000000000000000;
10'd464: delta_out = 32'b00010110000000000000000000000000;
10'd465: delta_out = 32'b00010101111000000000000000000000;
10'd466: delta_out = 32'b00010101110000000000000000000000;
10'd467: delta_out = 32'b00010101101000000000000000000000;
10'd468: delta_out = 32'b00010101100000000000000000000000;
10'd469: delta_out = 32'b00010101011000000000000000000000;
10'd470: delta_out = 32'b00010101010000000000000000000000;
10'd471: delta_out = 32'b00010101001000000000000000000000;
10'd472: delta_out = 32'b00010101000000000000000000000000;
10'd473: delta_out = 32'b00010100111000000000000000000000;
10'd474: delta_out = 32'b00010100110000000000000000000000;
10'd475: delta_out = 32'b00010100101000000000000000000000;
10'd476: delta_out = 32'b00010100100000000000000000000000;
10'd477: delta_out = 32'b00010100011000000000000000000000;
10'd478: delta_out = 32'b00010100010000000000000000000000;
10'd479: delta_out = 32'b00010100001000000000000000000000;
10'd480: delta_out = 32'b00010100000000000000000000000000;
10'd481: delta_out = 32'b00010011111000000000000000000000;
10'd482: delta_out = 32'b00010011110000000000000000000000;
10'd483: delta_out = 32'b00010011101000000000000000000000;
10'd484: delta_out = 32'b00010011100000000000000000000000;
10'd485: delta_out = 32'b00010011011000000000000000000000;
10'd486: delta_out = 32'b00010011010000000000000000000000;
10'd487: delta_out = 32'b00010011001000000000000000000000;
10'd488: delta_out = 32'b00010011000000000000000000000000;
10'd489: delta_out = 32'b00010010111000000000000000000000;
10'd490: delta_out = 32'b00010010110000000000000000000000;
10'd491: delta_out = 32'b00010010101000000000000000000000;
10'd492: delta_out = 32'b00010010100000000000000000000000;
10'd493: delta_out = 32'b00010010011000000000000000000000;
10'd494: delta_out = 32'b00010010010000000000000000000000;
10'd495: delta_out = 32'b00010010001000000000000000000000;
10'd496: delta_out = 32'b00010010000000000000000000000000;
10'd497: delta_out = 32'b00010001111000000000000000000000;
10'd498: delta_out = 32'b00010001110000000000000000000000;
10'd499: delta_out = 32'b00010001101000000000000000000000;
10'd500: delta_out = 32'b00010001100000000000000000000000;
10'd501: delta_out = 32'b00010001011000000000000000000000;
10'd502: delta_out = 32'b00010001010000000000000000000000;
10'd503: delta_out = 32'b00010001001000000000000000000000;
10'd504: delta_out = 32'b00010001000000000000000000000000;
10'd505: delta_out = 32'b00010000111000000000000000000000;
10'd506: delta_out = 32'b00010000110000000000000000000000;
10'd507: delta_out = 32'b00010000101000000000000000000000;
10'd508: delta_out = 32'b00010000100000000000000000000000;
10'd509: delta_out = 32'b00010000011000000000000000000000;
10'd510: delta_out = 32'b00010000010000000000000000000000;
10'd511: delta_out = 32'b00010000001000000000000000000000;
10'd512: delta_out = 32'b00010000000000000000000000000000;
10'd513: delta_out = 32'b00001111111000000000000000000000;
endcase
end
endmodule |
module IIR6_32bit_fixed (audio_out, audio_in,
scale,
b1, b2, b3, b4, b5, b6, b7,
a2, a3, a4, a5, a6, a7,
clk, data_val, rst, audio_out_val);
// The filter is a "Direct Form II Transposed"
//
// a(1)*y(n) = b(1)*x(n) + b(2)*x(n-1) + ... + b(nb+1)*x(n-nb)
// - a(2)*y(n-1) - ... - a(na+1)*y(n-na)
//
// If a(1) is not equal to 1, FILTER normalizes the filter
// coefficients by a(1).
//
// one audio sample, 16 bit, 2's complement
output reg signed [31:0] audio_out;
output reg signed audio_out_val;
// one audio sample, 16 bit, 2's complement
input wire signed [31:0] audio_in;
// shift factor for output
input wire [2:0] scale;
// filter coefficients
input wire signed [31:0] b1, b2, b3, b4, b5, b6, b7, a2, a3, a4, a5, a6, a7;
input wire clk, data_val, rst;
/// filter vars
wire signed [31:0] f1_mac_new, f1_coeff_x_value;
reg signed [31:0] f1_coeff, f1_mac_old, f1_value;
// input to filter
reg signed [31:0] x_n;
// input history x(n-1), x(n-2)
reg signed [31:0] x_n1, x_n2, x_n3, x_n4, x_n5, x_n6;
// output history: y_n is the new filter output, BUT it is
// immediately stored in f1_y_n1 for the next loop through
// the filter state machine
reg signed [31:0] f1_y_n1, f1_y_n2, f1_y_n3, f1_y_n4, f1_y_n5, f1_y_n6;
// MAC operation
signed_mult f1_c_x_v (.out(f1_coeff_x_value), .a(f1_coeff), .b(f1_value));
assign f1_mac_new = f1_mac_old + f1_coeff_x_value;
// state variable
reg [3:0] state;
///////////////////////////////////////////////////////////////////
//Run the filter state machine FAST so that it completes in one
//audio cycle
always @ (posedge clk)
begin
if (rst) begin
state <= 4'd15; //turn off the state machine
f1_value <= 0;
f1_coeff <= 0;
f1_mac_old <= 0;
x_n <= 0;
x_n1 <= 0;
x_n2 <= 0;
x_n3 <= 0;
x_n4 <= 0;
x_n5 <= 0;
x_n6 <= 0;
f1_y_n1 <= 0;
f1_y_n2 <= 0;
f1_y_n3 <= 0;
f1_y_n4 <= 0;
f1_y_n5 <= 0;
f1_y_n6 <= 0;
audio_out_val <= 0;
end
else begin
case (state)
1:
begin
// set up b1*x(n)
f1_mac_old <= 32'd0;
f1_coeff <= b1;
f1_value <= (audio_in >>> 1);
//register input
x_n <= (audio_in >>> 1);
// next state
state <= 4'd2;
end
2:
begin
// set up b2*x(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= b2;
f1_value <= x_n1;
// next state
state <= 4'd3;
end
3:
begin
// set up b3*x(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= b3;
f1_value <= x_n2;
// next state
state <= 4'd4;
end
4:
begin
// set up b4*x(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= b4;
f1_value <= x_n3;
// next state
state <= 4'd5;
end
5:
begin
// set up b5*x(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= b5;
f1_value <= x_n4;
// next state
state <= 4'd6;
end
6:
begin
// set up b6*x(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= b6;
f1_value <= x_n5;
// next state
state <= 4'd7;
end
7:
begin
// set up b7*x(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= b7;
f1_value <= x_n6;
// next state
state <= 4'd8;
end
8:
begin
// set up -a2*y(n-1)
f1_mac_old <= f1_mac_new;
f1_coeff <= a2;
f1_value <= f1_y_n1;
//next state
state <= 4'd9;
end
9:
begin
// set up -a3*y(n-2)
f1_mac_old <= f1_mac_new;
f1_coeff <= a3;
f1_value <= f1_y_n2;
//next state
state <= 4'd10;
end
4'd10:
begin
// set up -a4*y(n-3)
f1_mac_old <= f1_mac_new;
f1_coeff <= a4;
f1_value <= f1_y_n3;
//next state
state <= 4'd11;
end
4'd11:
begin
// set up -a5*y(n-4)
f1_mac_old <= f1_mac_new;
f1_coeff <= a5;
f1_value <= f1_y_n4;
//next state
state <= 4'd12;
end
4'd12:
begin
// set up -a6*y(n-5)
f1_mac_old <= f1_mac_new;
f1_coeff <= a6;
f1_value <= f1_y_n5;
//next state
state <= 4'd13;
end
13:
begin
// set up -a7*y(n-6)
f1_mac_old <= f1_mac_new;
f1_coeff <= a7;
f1_value <= f1_y_n6;
//next state
state <= 4'd14;
end
14:
begin
// get the output
// and put it in the LAST output var
// for the next pass thru the state machine
//mult by four because of coeff scaling
// to prevent overflow
f1_y_n1 <= f1_mac_new<<scale;
audio_out <= f1_y_n1;
audio_out_val <= 1'b1;
// update output history
f1_y_n2 <= f1_y_n1;
f1_y_n3 <= f1_y_n2;
f1_y_n4 <= f1_y_n3;
f1_y_n5 <= f1_y_n4;
f1_y_n6 <= f1_y_n5;
// update input history
x_n1 <= x_n;
x_n2 <= x_n1;
x_n3 <= x_n2;
x_n4 <= x_n3;
x_n5 <= x_n4;
x_n6 <= x_n5;
//next state
state <= 4'd15;
end
15:
begin
// wait for data valid signal
audio_out_val <= 1'b0;
if (data_val)
begin
state <= 4'd1;
end
end
default:
begin
// default state is end state
state <= 4'd15;
end
endcase
end
end
endmodule |
module signed_mult (out, a, b);
output [31:0] out;
input signed [31:0] a;
input signed [31:0] b;
wire signed [31:0] out;
wire signed [63:0] mult_out;
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[63], mult_out[59:30]};
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w);
parameter cache_entry = 14;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
wire [3:0] hit;
wire [3:0] modify;
wire [3:0] miss;
wire [3:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [7:0] r_cm_data;
wire [1:0] hit_num;
reg [2:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [3:0] write_set;
reg [3:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write0),
.word_en(word_en), // 4word r/w change
.readdata(readdata0),
.wb_addr(wb_addr0),
.hit(hit[0]),
.modify(modify[0]),
.miss(miss[0]),
.valid(valid[0]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write1),
.word_en(word_en), // 4word r/w change
.readdata(readdata1),
.wb_addr(wb_addr1),
.hit(hit[1]),
.modify(modify[1]),
.miss(miss[1]),
.valid(valid[1]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write2),
.word_en(word_en), // 4word r/w change
.readdata(readdata2),
.wb_addr(wb_addr2),
.hit(hit[2]),
.modify(modify[2]),
.miss(miss[2]),
.valid(valid[2]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write3),
.word_en(word_en), // 4word r/w change
.readdata(readdata3),
.wb_addr(wb_addr3),
.hit(hit[3]),
.modify(modify[3]),
.miss(miss[3]),
.valid(valid[3]),
.read_miss(read_buf));
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign addr = (o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 : (hit[1]) ? 1 : (hit[2]) ? 2 : 3;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if((|hit) && read_buf) begin
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= (hit[0]) ? readdata0[31:0] : (hit[1]) ? readdata1[31:0] : (hit[2]) ? readdata2[31:0] : readdata3[31:0];
2'b01: o_p_readdata <= (hit[0]) ? readdata0[63:32] : (hit[1]) ? readdata1[63:32] : (hit[2]) ? readdata2[63:32] : readdata3[63:32];
2'b10: o_p_readdata <= (hit[0]) ? readdata0[95:64] : (hit[1]) ? readdata1[95:64] : (hit[2]) ? readdata2[95:64] : readdata3[95:64];
2'b11: o_p_readdata <= (hit[0]) ? readdata0[127:96] : (hit[1]) ? readdata1[127:96] : (hit[2]) ? readdata2[127:96] : readdata3[127:96];
endcase
o_p_readdata_valid <= 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
cnt_hit_r <= cnt_hit_r + 1;
state <= IDLE;
end else if(!(&valid) || miss[r_cm_data[1:0]]) begin
state <= FETCH1;
if(!valid[0]) begin
fetch_write <= 4'b0001;
w_cm_data <= 8'b11100100;
w_cm <= 1;
end else if(!valid[1]) begin
fetch_write <= 4'b0010;
w_cm_data <= (r_cm_data[1:0] == 2'b01) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b01) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b01) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[2]) begin
fetch_write <= 4'b0100;
w_cm_data <= (r_cm_data[1:0] == 2'b10) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b10) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b10) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[3]) begin
fetch_write <= 4'b1000;
w_cm_data <= (r_cm_data[1:0] == 2'b11) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b11) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b11) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(miss[r_cm_data[1:0]]) begin
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
end
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
end else begin
state <= WB1;
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end //1/13
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} : {wb_addr3, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 : readdata3;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
endcase // case (state)
end
end
endmodule // cache |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, modify, miss, valid;
wire [22-cache_entry:0] i_tag;
wire dirty;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
//write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, write, write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w);
parameter cache_entry = 9;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
wire [7:0] hit;
wire [7:0] modify;
wire [7:0] miss;
wire [7:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] readdata4, readdata5, readdata6, readdata7;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire write4, write5, write6, write7;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
wire [7:0] r_cm_data;
wire [3:0] hit_num;
wire [3:0] invalid_num;
reg [2:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [7:0] write_set;
reg [7:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
// reg [2:0] replace;
wire [2:0] replace;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write0),
.word_en(word_en), // 4word r/w change
.readdata(readdata0),
.wb_addr(wb_addr0),
.hit(hit[0]),
.modify(modify[0]),
.miss(miss[0]),
.valid(valid[0]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write1),
.word_en(word_en), // 4word r/w change
.readdata(readdata1),
.wb_addr(wb_addr1),
.hit(hit[1]),
.modify(modify[1]),
.miss(miss[1]),
.valid(valid[1]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write2),
.word_en(word_en), // 4word r/w change
.readdata(readdata2),
.wb_addr(wb_addr2),
.hit(hit[2]),
.modify(modify[2]),
.miss(miss[2]),
.valid(valid[2]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write3),
.word_en(word_en), // 4word r/w change
.readdata(readdata3),
.wb_addr(wb_addr3),
.hit(hit[3]),
.modify(modify[3]),
.miss(miss[3]),
.valid(valid[3]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set4(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write4),
.word_en(word_en), // 4word r/w change
.readdata(readdata4),
.wb_addr(wb_addr4),
.hit(hit[4]),
.modify(modify[4]),
.miss(miss[4]),
.valid(valid[4]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set5(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write5),
.word_en(word_en), // 4word r/w change
.readdata(readdata5),
.wb_addr(wb_addr5),
.hit(hit[5]),
.modify(modify[5]),
.miss(miss[5]),
.valid(valid[5]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set6(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write6),
.word_en(word_en), // 4word r/w change
.readdata(readdata6),
.wb_addr(wb_addr6),
.hit(hit[6]),
.modify(modify[6]),
.miss(miss[6]),
.valid(valid[6]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set7(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write7),
.word_en(word_en), // 4word r/w change
.readdata(readdata7),
.wb_addr(wb_addr7),
.hit(hit[7]),
.modify(modify[7]),
.miss(miss[7]),
.valid(valid[7]),
.read_miss(read_buf));
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign write4 = (fetch_write[4]) ? i_m_readdata_valid : write_set[4];
assign write5 = (fetch_write[5]) ? i_m_readdata_valid : write_set[5];
assign write6 = (fetch_write[6]) ? i_m_readdata_valid : write_set[6];
assign write7 = (fetch_write[7]) ? i_m_readdata_valid : write_set[7];
assign addr = (o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 :
(hit[1]) ? 1 :
(hit[2]) ? 2 :
(hit[3]) ? 3 :
(hit[4]) ? 4 :
(hit[5]) ? 5 :
(hit[6]) ? 6 : 7;
assign invalid_num = (!valid[0]) ? 0 :
(!valid[1]) ? 1 :
(!valid[2]) ? 2 :
(!valid[3]) ? 3 :
(!valid[4]) ? 4 :
(!valid[5]) ? 5 :
(!valid[6]) ? 6 : 7;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
assign replace = (r_cm_data[6]) ? ((r_cm_data[4]) ? ((r_cm_data[0]) ? 7 : 6) : ((r_cm_data[1]) ? 5 : 4)) :
((r_cm_data[5]) ? ((r_cm_data[2]) ? 3 : 2) : ((r_cm_data[3]) ? 1 : 0));
always @(posedge clk) begin
if(hit) begin
case(hit_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else if(!(&valid)) begin
case(invalid_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else begin
case(replace)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end
end
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
w_cm <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
w_cm <= 1;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
end else if((|hit) && read_buf) begin
state <= IDLE;
w_cm <= 1;
o_p_readdata_valid <= 1;
cnt_hit_r <= cnt_hit_r + 1;
case(write_addr_buf[1:0])
2'b00: begin
o_p_readdata <= (hit[0]) ? readdata0[31:0] :
(hit[1]) ? readdata1[31:0] :
(hit[2]) ? readdata2[31:0] :
(hit[3]) ? readdata3[31:0] :
(hit[4]) ? readdata4[31:0] :
(hit[5]) ? readdata5[31:0] :
(hit[6]) ? readdata6[31:0] : readdata7[31:0];
end
2'b01: begin
o_p_readdata <= (hit[0]) ? readdata0[63:32] :
(hit[1]) ? readdata1[63:32] :
(hit[2]) ? readdata2[63:32] :
(hit[3]) ? readdata3[63:32] :
(hit[4]) ? readdata4[63:32] :
(hit[5]) ? readdata5[63:32] :
(hit[6]) ? readdata6[63:32] : readdata7[63:32];
end
2'b10: begin
o_p_readdata <= (hit[0]) ? readdata0[95:64] :
(hit[1]) ? readdata1[95:64] :
(hit[2]) ? readdata2[95:64] :
(hit[3]) ? readdata3[95:64] :
(hit[4]) ? readdata4[95:64] :
(hit[5]) ? readdata5[95:64] :
(hit[6]) ? readdata6[95:64] : readdata7[95:64];
end
2'b11: begin
o_p_readdata <= (hit[0]) ? readdata0[127:96] :
(hit[1]) ? readdata1[127:96] :
(hit[2]) ? readdata2[127:96] :
(hit[3]) ? readdata3[127:96] :
(hit[4]) ? readdata4[127:96] :
(hit[5]) ? readdata5[127:96] :
(hit[6]) ? readdata6[127:96] : readdata7[127:96];
end
endcase
end else if(!(&valid)) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(invalid_num)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else if(miss[replace]) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else begin
state <= WB1;
w_cm <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} :
(fetch_write[3]) ? {wb_addr3, 3'b000} :
(fetch_write[4]) ? {wb_addr4, 3'b000} :
(fetch_write[5]) ? {wb_addr5, 3'b000} :
(fetch_write[6]) ? {wb_addr6, 3'b000} : {wb_addr7, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 :
(fetch_write[3]) ? readdata3 :
(fetch_write[4]) ? readdata4 :
(fetch_write[5]) ? readdata5 :
(fetch_write[6]) ? readdata6 : readdata7;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
endcase // case (state)
end
end
endmodule // cache |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, modify, miss, valid;
wire [22-cache_entry:0] i_tag;
wire dirty;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
// write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, write, write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule |
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w,
cache_config,
change);
parameter cache_entry = 9;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
input wire [3:0] cache_config;
input wire change;
wire [7:0] hit;
wire [7:0] modify;
wire [7:0] miss;
wire [7:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] readdata4, readdata5, readdata6, readdata7;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire write4, write5, write6, write7;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
wire [7:0] r_cm_data;
wire [3:0] hit_num;
wire [3:0] invalid_num;
reg [3:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [7:0] write_set;
reg [7:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
wire [2:0] replace;
reg [1:0] flash;
reg [3:0] phase;
reg [cache_entry:0] flash_cnt;
wire [7:0] dirty;
reg [3:0] current_config;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
localparam FLASH = 8;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
config_ctrl #(.cache_entry(cache_entry))
config_ctrl(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en),
.write({write7, write6, write5, write4, write3, write2, write1, write0}),
.readdata0(readdata0),
.readdata1(readdata1),
.readdata2(readdata2),
.readdata3(readdata3),
.readdata4(readdata4),
.readdata5(readdata5),
.readdata6(readdata6),
.readdata7(readdata7),
.wb_addr0(wb_addr0),
.wb_addr1(wb_addr1),
.wb_addr2(wb_addr2),
.wb_addr3(wb_addr3),
.wb_addr4(wb_addr4),
.wb_addr5(wb_addr5),
.wb_addr6(wb_addr6),
.wb_addr7(wb_addr7),
.hit(hit),
.miss(miss),
.dirty(dirty),
.valid(valid),
.read_miss(read_buf),
.flash(flash),
.c_fig(current_config)
);
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign write4 = (fetch_write[4]) ? i_m_readdata_valid : write_set[4];
assign write5 = (fetch_write[5]) ? i_m_readdata_valid : write_set[5];
assign write6 = (fetch_write[6]) ? i_m_readdata_valid : write_set[6];
assign write7 = (fetch_write[7]) ? i_m_readdata_valid : write_set[7];
assign addr = (state == FLASH) ? {write_addr_buf[24:cache_entry+2], flash_cnt[cache_entry-1:0]} :
(o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 :
(hit[1]) ? 1 :
(hit[2]) ? 2 :
(hit[3]) ? 3 :
(hit[4]) ? 4 :
(hit[5]) ? 5 :
(hit[6]) ? 6 : 7;
assign invalid_num = (!valid[0]) ? 0 :
(!valid[1]) ? 1 :
(!valid[2]) ? 2 :
(!valid[3]) ? 3 :
(!valid[4]) ? 4 :
(!valid[5]) ? 5 :
(!valid[6]) ? 6 : 7;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
assign replace = (current_config) ? {1'b0, r_cm_data[1:0]} :
(r_cm_data[6]) ? ((r_cm_data[4]) ? ((r_cm_data[0]) ? 7 : 6) : ((r_cm_data[1]) ? 5 : 4)) :
((r_cm_data[5]) ? ((r_cm_data[2]) ? 3 : 2) : ((r_cm_data[3]) ? 1 : 0));
always @(posedge clk) begin
if(current_config == 4'b0000) begin
if(hit) begin
case(hit_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else if(!(&valid)) begin
case(invalid_num)
// 0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
0: w_cm_data <= 8'b01101000;
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else begin
case(replace)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end
end else if(current_config == 4'b0001) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b00111001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == invalid_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == invalid_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
end
end else if(current_config == 4'b0010) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b11100001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]};
end
end
end
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
flash <= 0;
phase <= 0;
flash_cnt <= 0;
current_config <= 0; // default cache config is 4way
w_cm <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end else if(change) begin
state <= FLASH;
flash <= 2'b10;
phase <= 0;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
w_cm <= 1;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
end else if((|hit) && read_buf) begin
state <= IDLE;
w_cm <= 1;
o_p_readdata_valid <= 1;
cnt_hit_r <= cnt_hit_r + 1;
case(write_addr_buf[1:0])
2'b00: begin
o_p_readdata <= (hit[0]) ? readdata0[31:0] :
(hit[1]) ? readdata1[31:0] :
(hit[2]) ? readdata2[31:0] :
(hit[3]) ? readdata3[31:0] :
(hit[4]) ? readdata4[31:0] :
(hit[5]) ? readdata5[31:0] :
(hit[6]) ? readdata6[31:0] : readdata7[31:0];
end
2'b01: begin
o_p_readdata <= (hit[0]) ? readdata0[63:32] :
(hit[1]) ? readdata1[63:32] :
(hit[2]) ? readdata2[63:32] :
(hit[3]) ? readdata3[63:32] :
(hit[4]) ? readdata4[63:32] :
(hit[5]) ? readdata5[63:32] :
(hit[6]) ? readdata6[63:32] : readdata7[63:32];
end
2'b10: begin
o_p_readdata <= (hit[0]) ? readdata0[95:64] :
(hit[1]) ? readdata1[95:64] :
(hit[2]) ? readdata2[95:64] :
(hit[3]) ? readdata3[95:64] :
(hit[4]) ? readdata4[95:64] :
(hit[5]) ? readdata5[95:64] :
(hit[6]) ? readdata6[95:64] : readdata7[95:64];
end
2'b11: begin
o_p_readdata <= (hit[0]) ? readdata0[127:96] :
(hit[1]) ? readdata1[127:96] :
(hit[2]) ? readdata2[127:96] :
(hit[3]) ? readdata3[127:96] :
(hit[4]) ? readdata4[127:96] :
(hit[5]) ? readdata5[127:96] :
(hit[6]) ? readdata6[127:96] : readdata7[127:96];
end
endcase
end else if(!(&valid)) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(invalid_num)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else if(miss[replace]) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else begin
state <= WB1;
w_cm <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} :
(fetch_write[3]) ? {wb_addr3, 3'b000} :
(fetch_write[4]) ? {wb_addr4, 3'b000} :
(fetch_write[5]) ? {wb_addr5, 3'b000} :
(fetch_write[6]) ? {wb_addr6, 3'b000} : {wb_addr7, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 :
(fetch_write[3]) ? readdata3 :
(fetch_write[4]) ? readdata4 :
(fetch_write[5]) ? readdata5 :
(fetch_write[6]) ? readdata6 : readdata7;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
FLASH: begin
if(!i_m_waitrequest) begin
if(flash_cnt[cache_entry] && !change) begin
state <= IDLE;
flash <= 0;
o_m_write <= 0;
flash_cnt <= 0;
current_config <= cache_config;
end else if(flash_cnt[cache_entry]) begin
flash <= 0;
o_m_write <= 0;
end else begin
phase <= (phase == 10) ? 0 : phase + 1;
case(phase)
0: o_m_write <= 0;
1: begin
if(dirty[0]) begin
o_m_addr <= {wb_addr0, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
2: begin
if(dirty[1]) begin
o_m_addr <= {wb_addr1, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
3: begin
if(dirty[2]) begin
o_m_addr <= {wb_addr2, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
4: begin
if(dirty[3]) begin
o_m_addr <= {wb_addr3, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
5: begin
if(dirty[4]) begin
o_m_addr <= {wb_addr4, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
6: begin
if(dirty[5]) begin
o_m_addr <= {wb_addr5, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
7: begin
if(dirty[6]) begin
o_m_addr <= {wb_addr6, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
8: begin
if(dirty[7]) begin
o_m_addr <= {wb_addr7, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
9: begin
o_m_write <= 0;
flash <= 2'b11;
end
10: begin
flash <= 2'b10;
flash_cnt <= flash_cnt + 1;
end
endcase
end
end
end
endcase // case (state)
end
end
endmodule // cache |
module config_ctrl(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
word_en,
write,
readdata0,
readdata1,
readdata2,
readdata3,
readdata4,
readdata5,
readdata6,
readdata7,
wb_addr0,
wb_addr1,
wb_addr2,
wb_addr3,
wb_addr4,
wb_addr5,
wb_addr6,
wb_addr7,
hit,
miss,
dirty,
valid,
read_miss,
flash,
c_fig);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire [3:0] word_en;
input wire [7:0] write;
input wire read_miss;
input wire [1:0] flash;
input wire [3:0] c_fig;
output wire [127:0] readdata0, readdata1, readdata2, readdata3;
output wire [127:0] readdata4, readdata5, readdata6, readdata7;
output wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
output wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
output wire [7:0] hit, miss, dirty, valid;
wire [7:0] s_hit;
wire [7:0] s_miss;
wire [7:0] s_dirty;
wire [7:0] s_valid;
wire [127:0] s_readdata0, s_readdata1, s_readdata2, s_readdata3;
wire [127:0] s_readdata4, s_readdata5, s_readdata6, s_readdata7;
wire [22:0] s_wb_addr0, s_wb_addr1, s_wb_addr2, s_wb_addr3;
wire [22:0] s_wb_addr4, s_wb_addr5, s_wb_addr6, s_wb_addr7;
assign hit = (c_fig == 0) ? s_hit :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_hit[7], s_hit[5], s_hit[3], s_hit[1]} :
{4'b0000, s_hit[6], s_hit[4], s_hit[2], s_hit[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_hit[4], s_hit[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_hit[5], s_hit[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_hit[6], s_hit[2]} :
{6'b000000, s_hit[7], s_hit[3]}) : 8'b00000000;
assign miss = (c_fig == 0) ? s_miss :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_miss[7], s_miss[5], s_miss[3], s_miss[1]} :
{4'b0000, s_miss[6], s_miss[4], s_miss[2], s_miss[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_miss[4], s_miss[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_miss[5], s_miss[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_miss[6], s_miss[2]} :
{6'b000000, s_miss[7], s_miss[3]}) : 8'b00000000;
assign dirty = s_dirty;
assign valid = (c_fig == 0) ? s_valid :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b1111, s_valid[7], s_valid[5], s_valid[3], s_valid[1]} :
{4'b1111, s_valid[6], s_valid[4], s_valid[2], s_valid[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b111111, s_valid[4], s_valid[0]} :
(o_tag[1:0] == 2'b01) ? {6'b111111, s_valid[5], s_valid[1]} :
(o_tag[1:0] == 2'b10) ? {6'b111111, s_valid[6], s_valid[2]} :
{6'b111111, s_valid[7], s_valid[3]}) : 8'b00000000;
assign readdata0 = ((c_fig == 0) || flash[1]) ? s_readdata0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata1 : s_readdata0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata0 :
(o_tag[1:0] == 2'b01) ? s_readdata1 :
(o_tag[1:0] == 2'b10) ? s_readdata2 : s_readdata3) : s_readdata0;
assign readdata1 = ((c_fig == 0) || flash[1]) ? s_readdata1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata3 : s_readdata2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata4 :
(o_tag[1:0] == 2'b01) ? s_readdata5 :
(o_tag[1:0] == 2'b10) ? s_readdata6 : s_readdata7) : s_readdata1;
assign readdata2 = ((c_fig == 0) || flash[1]) ? s_readdata2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata5 : s_readdata4) : readdata2;
assign readdata3 = ((c_fig == 0) || flash[1]) ? s_readdata3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata7 : s_readdata6) : readdata3;
assign readdata4 = s_readdata4;
assign readdata5 = s_readdata5;
assign readdata6 = s_readdata6;
assign readdata7 = s_readdata7;
assign wb_addr0 = ((c_fig == 0) || flash[1]) ? s_wb_addr0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr1 : s_wb_addr0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr0 :
(o_tag[1:0] == 2'b01) ? s_wb_addr1 :
(o_tag[1:0] == 2'b10) ? s_wb_addr2 : s_wb_addr3) : s_wb_addr0;
assign wb_addr1 = ((c_fig == 0) || flash[1]) ? s_wb_addr1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr3 : s_wb_addr2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr4 :
(o_tag[1:0] == 2'b01) ? s_wb_addr5 :
(o_tag[1:0] == 2'b10) ? s_wb_addr6 : s_wb_addr7) : s_wb_addr1;
assign wb_addr2 = ((c_fig == 0) || flash[1]) ? s_wb_addr2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr5 : s_wb_addr4) : wb_addr2;
assign wb_addr3 = ((c_fig == 0) || flash[1]) ? s_wb_addr3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr7 : s_wb_addr6) : wb_addr3;
assign wb_addr4 = s_wb_addr4;
assign wb_addr5 = s_wb_addr5;
assign wb_addr6 = s_wb_addr6;
assign wb_addr7 = s_wb_addr7;
wire [7:0] s_write;
assign s_write = (c_fig == 0) ? write :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0], 1'b0} :
{1'b0, write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {3'b000, write[1], 3'b000, write[0]} :
(o_tag[1:0] == 2'b01) ? {2'b00, write[1], 3'b000, write[0], 1'b0} :
(o_tag[1:0] == 2'b10) ? {1'b0, write[1], 3'b000, write[0], 2'b00} : {write[1], 3'b000, write[0], 3'b000}) : 8'b00000000;
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[0]),
.readdata(s_readdata0),
.wb_addr(s_wb_addr0),
.hit(s_hit[0]),
.miss(s_miss[0]),
.dirty(s_dirty[0]),
.valid(s_valid[0]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[1]),
.readdata(s_readdata1),
.wb_addr(s_wb_addr1),
.hit(s_hit[1]),
.miss(s_miss[1]),
.dirty(s_dirty[1]),
.valid(s_valid[1]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[2]),
.readdata(s_readdata2),
.wb_addr(s_wb_addr2),
.hit(s_hit[2]),
.miss(s_miss[2]),
.dirty(s_dirty[2]),
.valid(s_valid[2]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[3]),
.readdata(s_readdata3),
.wb_addr(s_wb_addr3),
.hit(s_hit[3]),
.miss(s_miss[3]),
.dirty(s_dirty[3]),
.valid(s_valid[3]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set4(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[4]),
.readdata(s_readdata4),
.wb_addr(s_wb_addr4),
.hit(s_hit[4]),
.miss(s_miss[4]),
.dirty(s_dirty[4]),
.valid(s_valid[4]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set5(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[5]),
.readdata(s_readdata5),
.wb_addr(s_wb_addr5),
.hit(s_hit[5]),
.miss(s_miss[5]),
.dirty(s_dirty[5]),
.valid(s_valid[5]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set6(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[6]),
.readdata(s_readdata6),
.wb_addr(s_wb_addr6),
.hit(s_hit[6]),
.miss(s_miss[6]),
.dirty(s_dirty[6]),
.valid(s_valid[6]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set7(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[7]),
.readdata(s_readdata7),
.wb_addr(s_wb_addr7),
.hit(s_hit[7]),
.miss(s_miss[7]),
.dirty(s_dirty[7]),
.valid(s_valid[7]),
.read_miss(read_miss),
.flash(flash[0]));
endmodule // config_ctrl |
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
miss,
dirty,
valid,
read_miss,
flash);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
input wire flash;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, miss, dirty, valid;
wire [22-cache_entry:0] i_tag;
wire modify;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
//write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (flash) ? {1'b0, 1'b0, i_tag} :
(read_miss) ? {1'b0, 1'b1, o_tag} :
(modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
// assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, (write || flash), write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule |
module simple_ram
#(parameter width = 1,
parameter widthad = 1
)
(
input clk,
input [widthad-1:0] wraddress,
input wren,
input [width-1:0] data,
input [widthad-1:0] rdaddress,
output reg [width-1:0] q
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren) mem[wraddress] <= data;
q <= mem[rdaddress];
end
endmodule |
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4)
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
reg [10:0] tx_clk_divider = CLOCK_DIVIDE;
reg [2:0] recv_state = RX_IDLE;
reg [5:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [5:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
always @(posedge clk) begin
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
// The clk_divider counter counts down from
// the CLOCK_DIVIDE constant. Whenever it
// reaches 0, 1/16 of the bit period has elapsed.
// Countdown timers for the receiving and transmitting
// state machines are decremented.
rx_clk_divider = rx_clk_divider - 1;
if (!rx_clk_divider) begin
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = rx_countdown - 1;
end
tx_clk_divider = tx_clk_divider - 1;
if (!tx_clk_divider) begin
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = tx_countdown - 1;
end
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_clk_divider = CLOCK_DIVIDE;
rx_countdown = 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 4;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 4;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 8;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_clk_divider = CLOCK_DIVIDE;
tx_countdown = 4;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 4;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 8;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (100) @(posedge clk);
resetn <= 1;
repeat (1000) @(posedge clk);
$finish;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
always @(posedge clk) begin
if (mem_valid && mem_ready) begin
if (mem_instr)
$display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata);
else if (mem_wstrb)
$display("write 0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb);
else
$display("read 0x%08x: 0x%08x", mem_addr, mem_rdata);
end
end
picorv32 #(
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg [31:0] memory [0:255];
initial begin
memory[0] = 32'h 3fc00093; // li x1,1020
memory[1] = 32'h 0000a023; // sw x0,0(x1)
memory[2] = 32'h 0000a103; // loop: lw x2,0(x1)
memory[3] = 32'h 00110113; // addi x2,x2,1
memory[4] = 32'h 0020a023; // sw x2,0(x1)
memory[5] = 32'h ff5ff06f; // j <loop>
end
always @(posedge clk) begin
mem_ready <= 0;
if (mem_valid && !mem_ready) begin
if (mem_addr < 1024) begin
mem_ready <= 1;
mem_rdata <= memory[mem_addr >> 2];
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end
/* add memory-mapped IO here */
end
end
endmodule |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.AXI_TEST (AXI_TEST),
.VERBOSE (VERBOSE)
) top (
.clk(clk),
.resetn(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [ 2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [ 3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [ 2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
axi4_memory #(
.AXI_TEST (AXI_TEST),
.VERBOSE (VERBOSE)
) mem (
.clk (clk ),
.mem_axi_awvalid (mem_axi_awvalid ),
.mem_axi_awready (mem_axi_awready ),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid (mem_axi_arvalid ),
.mem_axi_arready (mem_axi_arready ),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.tests_passed (tests_passed )
);
`ifdef RISCV_FORMAL
wire rvfi_valid;
wire [63:0] rvfi_order;
wire [31:0] rvfi_insn;
wire rvfi_trap;
wire rvfi_halt;
wire rvfi_intr;
wire [4:0] rvfi_rs1_addr;
wire [4:0] rvfi_rs2_addr;
wire [31:0] rvfi_rs1_rdata;
wire [31:0] rvfi_rs2_rdata;
wire [4:0] rvfi_rd_addr;
wire [31:0] rvfi_rd_wdata;
wire [31:0] rvfi_pc_rdata;
wire [31:0] rvfi_pc_wdata;
wire [31:0] rvfi_mem_addr;
wire [3:0] rvfi_mem_rmask;
wire [3:0] rvfi_mem_wmask;
wire [31:0] rvfi_mem_rdata;
wire [31:0] rvfi_mem_wdata;
`endif
picorv32_axi #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.irq (irq ),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata (rvfi_rs1_rdata ),
.rvfi_rs2_rdata (rvfi_rs2_rdata ),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask (rvfi_mem_rmask ),
.rvfi_mem_wmask (rvfi_mem_wmask ),
.rvfi_mem_rdata (rvfi_mem_rdata ),
.rvfi_mem_wdata (rvfi_mem_wdata ),
`endif
.trace_valid (trace_valid ),
.trace_data (trace_data )
);
`ifdef RISCV_FORMAL
picorv32_rvfimon rvfi_monitor (
.clock (clk ),
.reset (!resetn ),
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata (rvfi_rs1_rdata),
.rvfi_rs2_rdata (rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask (rvfi_mem_rmask),
.rvfi_mem_wmask (rvfi_mem_wmask),
.rvfi_mem_rdata (rvfi_mem_rdata),
.rvfi_mem_wdata (rvfi_mem_wdata)
);
`endif
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, mem.memory);
end
integer cycle_counter;
always @(posedge clk) begin
cycle_counter <= resetn ? cycle_counter + 1 : 0;
if (resetn && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror"))
$finish;
$stop;
end
end
end
endmodule |
module axi4_memory #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
/* verilator lint_off MULTIDRIVEN */
input clk,
input mem_axi_awvalid,
output reg mem_axi_awready,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
input mem_axi_wvalid,
output reg mem_axi_wready,
input [31:0] mem_axi_wdata,
input [ 3:0] mem_axi_wstrb,
output reg mem_axi_bvalid,
input mem_axi_bready,
input mem_axi_arvalid,
output reg mem_axi_arready,
input [31:0] mem_axi_araddr,
input [ 2:0] mem_axi_arprot,
output reg mem_axi_rvalid,
input mem_axi_rready,
output reg [31:0] mem_axi_rdata,
output reg tests_passed
);
reg [31:0] memory [0:128*1024/4-1] /* verilator public */;
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
reg axi_test;
initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
initial begin
mem_axi_awready = 0;
mem_axi_wready = 0;
mem_axi_bvalid = 0;
mem_axi_arready = 0;
mem_axi_rvalid = 0;
tests_passed = 0;
end
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [2:0] fast_axi_transaction = ~0;
reg [4:0] async_axi_transaction = ~0;
reg [4:0] delay_axi_transaction = 0;
always @(posedge clk) begin
if (axi_test) begin
xorshift64_next;
{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
end
end
reg latched_raddr_en = 0;
reg latched_waddr_en = 0;
reg latched_wdata_en = 0;
reg fast_raddr = 0;
reg fast_waddr = 0;
reg fast_wdata = 0;
reg [31:0] latched_raddr;
reg [31:0] latched_waddr;
reg [31:0] latched_wdata;
reg [ 3:0] latched_wstrb;
reg latched_rinsn;
task handle_axi_arvalid; begin
mem_axi_arready <= 1;
latched_raddr = mem_axi_araddr;
latched_rinsn = mem_axi_arprot[2];
latched_raddr_en = 1;
fast_raddr <= 1;
end endtask
task handle_axi_awvalid; begin
mem_axi_awready <= 1;
latched_waddr = mem_axi_awaddr;
latched_waddr_en = 1;
fast_waddr <= 1;
end endtask
task handle_axi_wvalid; begin
mem_axi_wready <= 1;
latched_wdata = mem_axi_wdata;
latched_wstrb = mem_axi_wstrb;
latched_wdata_en = 1;
fast_wdata <= 1;
end endtask
task handle_axi_rvalid; begin
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
if (latched_raddr < 128*1024) begin
mem_axi_rdata <= memory[latched_raddr >> 2];
mem_axi_rvalid <= 1;
latched_raddr_en = 0;
end else begin
$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
$finish;
end
end endtask
task handle_axi_bvalid; begin
if (verbose)
$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
if (latched_waddr < 128*1024) begin
if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
end else
if (latched_waddr == 32'h1000_0000) begin
if (verbose) begin
if (32 <= latched_wdata && latched_wdata < 128)
$display("OUT: '%c'", latched_wdata[7:0]);
else
$display("OUT: %3d", latched_wdata);
end else begin
$write("%c", latched_wdata[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
end else
if (latched_waddr == 32'h2000_0000) begin
if (latched_wdata == 123456789)
tests_passed = 1;
end else begin
$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
$finish;
end
mem_axi_bvalid <= 1;
latched_waddr_en = 0;
latched_wdata_en = 0;
end endtask
always @(negedge clk) begin
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
end
always @(posedge clk) begin
mem_axi_arready <= 0;
mem_axi_awready <= 0;
mem_axi_wready <= 0;
fast_raddr <= 0;
fast_waddr <= 0;
fast_wdata <= 0;
if (mem_axi_rvalid && mem_axi_rready) begin
mem_axi_rvalid <= 0;
end
if (mem_axi_bvalid && mem_axi_bready) begin
mem_axi_bvalid <= 0;
end
if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
latched_raddr = mem_axi_araddr;
latched_rinsn = mem_axi_arprot[2];
latched_raddr_en = 1;
end
if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
latched_waddr = mem_axi_awaddr;
latched_waddr_en = 1;
end
if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
latched_wdata = mem_axi_wdata;
latched_wstrb = mem_axi_wstrb;
latched_wdata_en = 1;
end
if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
end
endmodule |
module testbench #(
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 1;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 0;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.VERBOSE (VERBOSE)
) top (
.wb_clk(clk),
.wb_rst(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule |
module picorv32_wrapper #(
parameter VERBOSE = 0
) (
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [31:0] wb_s2m_dat;
wire wb_s2m_ack;
wb_ram #(
.depth (128*1024),
.VERBOSE (VERBOSE)
) ram ( // Wishbone interface
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_i(wb_m2s_adr),
.wb_dat_i(wb_m2s_dat),
.wb_stb_i(wb_m2s_stb),
.wb_cyc_i(wb_m2s_cyc),
.wb_dat_o(wb_s2m_dat),
.wb_ack_o(wb_s2m_ack),
.wb_sel_i(wb_m2s_sel),
.wb_we_i(wb_m2s_we),
.mem_instr(mem_instr),
.tests_passed(tests_passed)
);
picorv32_wb #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.trap (trap),
.irq (irq),
.trace_valid (trace_valid),
.trace_data (trace_data),
.mem_instr(mem_instr),
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wbm_adr_o(wb_m2s_adr),
.wbm_dat_i(wb_s2m_dat),
.wbm_stb_o(wb_m2s_stb),
.wbm_ack_i(wb_s2m_ack),
.wbm_cyc_o(wb_m2s_cyc),
.wbm_dat_o(wb_m2s_dat),
.wbm_we_o(wb_m2s_we),
.wbm_sel_o(wb_m2s_sel)
);
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, ram.mem);
end
integer cycle_counter;
always @(posedge wb_clk) begin
cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
if (!wb_rst && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge wb_clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror"))
$finish;
$stop;
end
end
end
endmodule |
module wb_ram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o,
input mem_instr,
output reg tests_passed
);
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
initial tests_passed = 0;
reg [31:0] adr_r;
wire valid = wb_cyc_i & wb_stb_i;
always @(posedge wb_clk_i) begin
adr_r <= wb_adr_i;
// Ack generation
wb_ack_o <= valid & !wb_ack_o;
if (wb_rst_i)
begin
adr_r <= {32{1'b0}};
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
wire [31:0] waddr = adr_r[31:2];
wire [31:0] raddr = wb_adr_i[31:2];
wire [3:0] we = {4{ram_we}} & wb_sel_i;
wire [$clog2(depth/4)-1:0] raddr2 = raddr[$clog2(depth/4)-1:0];
wire [$clog2(depth/4)-1:0] waddr2 = waddr[$clog2(depth/4)-1:0];
reg [31:0] mem [0:depth/4-1] /* verilator public */;
always @(posedge wb_clk_i) begin
if (ram_we) begin
if (verbose)
$display("WR: ADDR=%08x DATA=%08x STRB=%04b",
adr_r, wb_dat_i, we);
if (adr_r[31:0] == 32'h1000_0000)
if (verbose) begin
if (32 <= wb_dat_i[7:0] && wb_dat_i[7:0] < 128)
$display("OUT: '%c'", wb_dat_i[7:0]);
else
$display("OUT: %3d", wb_dat_i[7:0]);
end else begin
$write("%c", wb_dat_i[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
else
if (adr_r[31:0] == 32'h2000_0000)
if (wb_dat_i[31:0] == 123456789)
tests_passed = 1;
end
end
always @(posedge wb_clk_i) begin
if (waddr2 < 128 * 1024 / 4) begin
if (we[0])
mem[waddr2][7:0] <= wb_dat_i[7:0];
if (we[1])
mem[waddr2][15:8] <= wb_dat_i[15:8];
if (we[2])
mem[waddr2][23:16] <= wb_dat_i[23:16];
if (we[3])
mem[waddr2][31:24] <= wb_dat_i[31:24];
end
if (valid & wb_ack_o & !ram_we)
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], mem_instr ? " INSN" : "");
wb_dat_o <= mem[raddr2];
end
initial begin
if (memfile != "")
$readmemh(memfile, mem);
end
endmodule |
module layer_0(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
parameter NUM_NEURONS = 8;
reg [NUM_NEURONS-1:0] spike_layer_0_potential_reg[NUM_NEURONS-1:0];
wire [NUM_NEURONS-1:0] spike_layer_0_potential[NUM_NEURONS-1:0];
// Instantiate the neurons
// Layer 0: 8 neurons
// neuron0_0
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_0 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[0]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[0][7:0]),
.spike_out(output_spike[0])
);
// neuron0_1
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_1 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h1),
.memb_potential_in(spike_layer_0_potential_reg[1]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[1]),
.spike_out(output_spike[1])
);
// neuron0_2
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_2 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[2]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[2]),
.spike_out(output_spike[2])
);
// neuron0_3
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_3 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[3]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[3]),
.spike_out(output_spike[3])
);
// neuron0_4
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_4 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[4]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[4]),
.spike_out(output_spike[4])
);
// neuron0_5
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_5 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[5]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[5]),
.spike_out(output_spike[5])
);
// neuron0_6
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_6 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[6]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[6]),
.spike_out(output_spike[6])
);
// neuron0_7
leaky_integrate_fire uut_leaky_integrate_fire_layer_0_7 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_0_potential_reg[7]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_0_potential[7]),
.spike_out(output_spike[7])
);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
{spike_layer_0_potential_reg[7], spike_layer_0_potential_reg[6], spike_layer_0_potential_reg[5], spike_layer_0_potential_reg[4],
spike_layer_0_potential_reg[3], spike_layer_0_potential_reg[2], spike_layer_0_potential_reg[1], spike_layer_0_potential_reg[0]} <= 64'h0;
end else begin
{spike_layer_0_potential_reg[7], spike_layer_0_potential_reg[6], spike_layer_0_potential_reg[5], spike_layer_0_potential_reg[4],
spike_layer_0_potential_reg[3], spike_layer_0_potential_reg[2], spike_layer_0_potential_reg[1], spike_layer_0_potential_reg[0]} <= {spike_layer_0_potential[7], spike_layer_0_potential[6], spike_layer_0_potential[5], spike_layer_0_potential[4],
spike_layer_0_potential[3], spike_layer_0_potential[2], spike_layer_0_potential[1], spike_layer_0_potential[0]};
end
end
endmodule |
module controller(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
wire [7:0] output_spike_layer_0;
layer_0 uut_layer_0 (
.clk(clk), .reset_n(reset_n),
.input_spike(input_spike),
.output_spike(output_spike_layer_0)
);
layer_1 uut_layer_1 (
.clk(clk), .reset_n(reset_n),
.input_spike(output_spike_layer_0),
.output_spike(output_spike)
);
endmodule |
module layer_1(
input clk,
input reset_n,
input [7:0] input_spike,
output [7:0] output_spike
);
parameter NUM_NEURONS = 8;
reg [NUM_NEURONS-1:0] spike_layer_1_potential_reg[NUM_NEURONS-1:0];
wire [NUM_NEURONS-1:0] spike_layer_1_potential[NUM_NEURONS-1:0];
// Instantiate the neurons
// Layer 1: 8 neurons
// neuron1_0
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_0 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[0]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[0][7:0]),
.spike_out(output_spike[0])
);
// neuron1_1
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_1 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[1]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[1]),
.spike_out(output_spike[1])
);
// neuron1_2
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_2 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[2]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[2]),
.spike_out(output_spike[2])
);
// neuron1_3
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_3 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[3]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[3]),
.spike_out(output_spike[3])
);
// neuron1_4
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_4 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[4]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[4]),
.spike_out(output_spike[4])
);
// neuron1_5
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_5 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[5]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[5]),
.spike_out(output_spike[5])
);
// neuron1_6
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_6 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[6]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[6]),
.spike_out(output_spike[6])
);
// neuron1_7
leaky_integrate_fire uut_leaky_integrate_fire_layer_1_7 (
.clk(clk), .reset_n(reset_n),
.spike_in(input_spike[7:0]),
.weight(64'h77777777),
.memb_potential_in(spike_layer_1_potential_reg[7]),
.threshold(8'h9),
.leak_value(8'h1),
.tref(4'h2),
.memb_potential_out(spike_layer_1_potential[7]),
.spike_out(output_spike[7])
);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
{spike_layer_1_potential_reg[7], spike_layer_1_potential_reg[6], spike_layer_1_potential_reg[5], spike_layer_1_potential_reg[4],
spike_layer_1_potential_reg[3], spike_layer_1_potential_reg[2], spike_layer_1_potential_reg[1], spike_layer_1_potential_reg[0]} <= 64'h0;
end else begin
{spike_layer_1_potential_reg[7], spike_layer_1_potential_reg[6], spike_layer_1_potential_reg[5], spike_layer_1_potential_reg[4],
spike_layer_1_potential_reg[3], spike_layer_1_potential_reg[2], spike_layer_1_potential_reg[1], spike_layer_1_potential_reg[0]} <= {spike_layer_1_potential[7], spike_layer_1_potential[6], spike_layer_1_potential[5], spike_layer_1_potential[4],
spike_layer_1_potential[3], spike_layer_1_potential[2], spike_layer_1_potential[1], spike_layer_1_potential[0]};
end
end
endmodule |
module tb_leaky_integrate_fire;
reg clk;
reg reset_n;
reg spike_in_0, spike_in_1, spike_in_2, spike_in_3, spike_in_4, spike_in_5, spike_in_6, spike_in_7;
reg [7:0] weight_0, weight_1, weight_2, weight_3, weight_4, weight_5, weight_6, weight_7;
reg [7:0] memb_potential_in;
reg [7:0] threshold;
reg [7:0] leak_value;
reg [3:0] tref;
wire [7:0] memb_potential_out;
wire spike_out;
parameter STEP = 10;
leaky_integrate_fire uut (
.clk(clk), .reset_n(reset_n),
.spike_in({spike_in_7, spike_in_6, spike_in_5, spike_in_4, spike_in_3, spike_in_2, spike_in_1, spike_in_0}),
.weight({weight_7, weight_6, weight_5, weight_4, weight_3, weight_2, weight_1, weight_0}),
.memb_potential_in(memb_potential_in), .threshold(threshold), .leak_value(leak_value), .tref(tref),
.memb_potential_out(memb_potential_out), .spike_out(spike_out)
);
always #(STEP/2) clk = ~clk;
initial begin
$dumpfile("tb_leaky_integrate_fire.vcd");
$dumpvars(0, tb_leaky_integrate_fire);
clk = 1'b0; reset_n = 1'b1; #1;
reset_n = 1'b0; #1; reset_n = 1'b1; #1;
memb_potential_in = 8'h00; threshold = 8'h10; leak_value = 8'h1; tref = 4'h2;
weight_0 = 8'h01; weight_1 = 8'h02; weight_2 = 8'h03; weight_3 = 8'h04; weight_4 = 8'h05; weight_5 = 8'h06; weight_6 = 8'h07; weight_7 = 8'h08;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
// Test 1
spike_in_0 = 1'b1; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b1; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b1; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b1; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out;
spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out;
// Test 2
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b1; spike_in_2 = 1'b1; spike_in_3 = 1'b1; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b0; spike_in_6 = 1'b0; spike_in_7 = 1'b0; #STEP
memb_potential_in = memb_potential_out; #STEP
memb_potential_in = memb_potential_out; #STEP
memb_potential_in = memb_potential_out; #STEP
// Test 3
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; spike_in_0 = 1'b0; spike_in_1 = 1'b0; spike_in_2 = 1'b0; spike_in_3 = 1'b0; spike_in_4 = 1'b0; spike_in_5 = 1'b1; spike_in_6 = 1'b1; spike_in_7 = 1'b1; #STEP
memb_potential_in = memb_potential_out; #STEP
$finish;
end
endmodule |
module leaky_integrate_fire(
input clk,
input reset_n,
input [7:0] spike_in,
input [63:0] weight_0,
input [63:0] weight_1,
input [63:0] weight_2,
input [63:0] weight_3,
input [63:0] weight_4,
input [63:0] weight_5,
input [63:0] weight_6,
input [63:0] weight_7,
input [7:0] memb_potential_in,
input [7:0] threshold,
input [7:0] leak_value,
input [3:0] tref,
output [7:0] memb_potential_out,
output reg spike_out
);
reg [3:0] tr = 0;
reg [7:0] voltage;
wire [15:0] memb_potential_integrate; // integrate membrane potential
wire [15:0] synaptic_integration; // integrate synaptic current
wire [15:0] leak_and_int_potential; // leaked current and integrated potential
wire underflow;
wire [7:0] spike_and_weight[0:7];
// AND gate for spike and weight
assign spike_and_weight[0] = spike_in[0] * (weight_0[7:0] + weight_1[7:0] + weight_2[7:0] + weight_3[7:0] + weight_4[7:0] + weight_5[7:0] + weight_6[7:0] + weight_7[7:0]);
assign spike_and_weight[1] = spike_in[1] * (weight_0[15:8] + weight_1[15:8] + weight_2[15:8] + weight_3[15:8] + weight_4[15:8] + weight_5[15:8] + weight_6[15:8] + weight_7[15:8]);
assign spike_and_weight[2] = spike_in[2] * (weight_0[23:16] + weight_1[23:16] + weight_2[23:16] + weight_3[23:16] + weight_4[23:16] + weight_5[23:16] + weight_6[23:16] + weight_7[23:16]);
assign spike_and_weight[3] = spike_in[3] * (weight_0[31:24] + weight_1[31:24] + weight_2[31:24] + weight_3[31:24] + weight_4[31:24] + weight_5[31:24] + weight_6[31:24] + weight_7[31:24]);
assign spike_and_weight[4] = spike_in[4] * (weight_0[39:32] + weight_1[39:32] + weight_2[39:32] + weight_3[39:32] + weight_4[39:32] + weight_5[39:32] + weight_6[39:32] + weight_7[39:32]);
assign spike_and_weight[5] = spike_in[5] * (weight_0[47:40] + weight_1[47:40] + weight_2[47:40] + weight_3[47:40] + weight_4[47:40] + weight_5[47:40] + weight_6[47:40] + weight_7[47:40]);
assign spike_and_weight[6] = spike_in[6] * (weight_0[55:48] + weight_1[55:48] + weight_2[55:48] + weight_3[55:48] + weight_4[55:48] + weight_5[55:48] + weight_6[55:48] + weight_7[55:48]);
assign spike_and_weight[7] = spike_in[7] * (weight_0[63:56] + weight_1[63:56] + weight_2[63:56] + weight_3[63:56] + weight_4[63:56] + weight_5[63:56] + weight_6[63:56] + weight_7[63:56]);
// Integrate current
assign memb_potential_integrate = spike_and_weight[0]
+ spike_and_weight[1]
+ spike_and_weight[2]
+ spike_and_weight[3]
+ spike_and_weight[4]
+ spike_and_weight[5]
+ spike_and_weight[6]
+ spike_and_weight[7];
// integrate membrane potential and current
assign synaptic_integration = memb_potential_in + memb_potential_integrate;
// leak current
assign leak_and_int_potential = synaptic_integration - leak_value;
assign underflow = synaptic_integration < leak_value;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
spike_out <= 1'b0;
voltage <= 8'b0;
tr <= 4'b0;
end
else begin
// check if in refractory period
if (tr > 0) begin
spike_out <= 1'b0;
tr <= tr - 4'b1;
voltage = 8'b0;
end
else if (underflow) begin
spike_out <= 1'b0;
voltage <= 8'b0;
end
else if (leak_and_int_potential >= threshold) begin // leak_and_int_potential >= threshold
spike_out <= 1'b1;
tr <= tref; // refractory period
voltage = 8'b0;
end
else begin
spike_out <= 1'b0;
voltage <= leak_and_int_potential[7:0];
end
end
end
assign memb_potential_out = voltage;
endmodule |
module tb_controller;
reg clk, reset_n;
reg [7:0] input_spike;
wire [7:0] output_spike;
parameter STEP = 10;
controller uut_controller (
.clk(clk), .reset_n(reset_n),
.input_spike(input_spike),
.output_spike(output_spike)
);
always #(STEP/2) clk = ~clk;
initial
begin
$dumpfile("tb_controller.vcd");
$dumpvars(0, tb_controller);
clk = 0; reset_n = 1; input_spike = 8'b00000000;
#1 reset_n = 0;
#2 reset_n = 1;
#STEP input_spike = 8'b11111111;
#STEP input_spike = 8'b00000000;
#STEP input_spike = 8'b11111111;
#STEP input_spike = 8'b00000000;
#STEP
$finish;
end
endmodule |
module cond ( nzcv, condition_code, will_this_be_executed);
input wire[3:0] nzcv;
input wire[3:0] condition_code;
output reg will_this_be_executed;
always @* begin
case(condition_code)
0: begin //EQ
if(nzcv[2] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
1: begin //NE
if(nzcv[2] == 0) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
2: begin //CS
if(nzcv[1] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
3: begin //CC
if(nzcv[1] == 0) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
4: begin //MI
if(nzcv[3] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
5: begin //PL
if(nzcv[3] == 0) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
6: begin //VS
if(nzcv[0] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
7: begin //VC
if(nzcv[0] == 0) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
8: begin //HI
if(nzcv[1] == 1 && nzcv[2] == 0) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
9: begin //LS
if(nzcv[1] == 0 && nzcv[2] == 1) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
10: begin //GE
if(nzcv[3] == nzcv[0]) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
11: begin //LT
if(nzcv[3] != nzcv[0]) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
12: begin //GT
if(nzcv[2] == 0 && nzcv[3] == nzcv[0]) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
13: begin //LE
if(nzcv[2] == 0 || nzcv[3] != nzcv[0]) will_this_be_executed = 1;
else will_this_be_executed = 0;
end
14: begin //AL
will_this_be_executed = 1;
end
15: begin //reserved
will_this_be_executed = 1;
end
endcase
end
endmodule |
module bshift(instr_bit_25,imm_value, Rm, Rs, operand2, cin, c_to_alu, direct_data, use_shifter);
parameter n=32;
input [n-1:0] direct_data;
input use_shifter;
input instr_bit_25; // bit no. 25 in the instr
input [11:0] imm_value; // bits 11-0 in instr
input [n-1:0] Rm;
input [n-1:0] Rs;
output [n-1:0] operand2; // operand 2 for ALU
input cin;
output reg c_to_alu;
wire instr_bit_25;
wire [11:0] imm_value;
reg [n-1:0] in;
reg [n-1:0] out;
reg [7:0] shiftby; // no. bits to be shifted
reg [n-1:0] junk;
assign operand2 =(use_shifter==1)?out:direct_data ;
always @* begin
if (instr_bit_25) begin
// right rotate 32 bit zero extended imm_value[7:0] by 2*(top 4 bits of imm_value)
in[n-1:8] = 0;
in[7:0] = imm_value[7:0];
shiftby[0]=0;
shiftby[7:4]=4'd0;
shiftby[4:1] = imm_value[11:8];
{junk,out} = {in,in} >> shiftby[7:0];
if(shiftby[7:0]==0) c_to_alu = cin;
else c_to_alu = out[31];
end
else begin // 10 cases here.
// logical shift left by Immediate. This one is for 2 cases.
if(imm_value[6:4] == 0) begin
in = Rm;
{c_to_alu,out} = {cin ,in} << imm_value[11:7];
// C flag
end
// logical shift left by register
if(imm_value[6:4] == 3'd1) begin
in = Rm;
shiftby[7:0] = Rs[7:0];
{c_to_alu,out} = {cin,in} << shiftby[7:0];
end
// logical shift right by immediate
if(imm_value[6:4] == 3'd2) begin
in = Rm;
{out, c_to_alu} = {in,cin} >> imm_value[11:7];
end
// logical shift right by register
if(imm_value[6:4] == 3'd3) begin
in = Rm;
shiftby[7:0] = Rs[7:0];
{out, c_to_alu} = {in,cin} >> shiftby[7:0];
end
//Arithmetic shift right by immediate
if(imm_value[6:4] == 3'd4) begin
in = Rm;
//out[7] = in[7]; // preserves sign
if(in[n-1]){junk,out, c_to_alu} = {32'hFFFFFFFF,in,cin} >> imm_value[11:7];
else {out, c_to_alu} = {in,cin} >> imm_value[11:7];
end
//Arithmetic Shift Right by Register
if(imm_value[6:4] == 3'd5) begin
in = Rm;
shiftby[7:0] = Rs[7:0];
if(in[n-1]) {junk,out, c_to_alu} = {32'hFFFFFFFF,in,cin} >> shiftby[7:0];
else {out,c_to_alu} = {in,cin} >> shiftby[7:0];
end
// Rotate Right by immediate
if((imm_value[6:4] == 3'd6)&&(imm_value[11:7]!=5'd0)) begin
in = Rm;
{junk,out,c_to_alu} = {in,in,cin} >> imm_value[11:7];
end
//Rotate Right by Register
if(imm_value[6:4] == 3'd7) begin
in=Rm;
shiftby[7:0] = Rs[7:0];
{junk,out,c_to_alu} = {in,in,cin} >> shiftby[4:0]; // [4:0] because.. if input is given as 100 it is enough to shift with 4 .. i.e 100mod 32
end
// RRX
if((imm_value[6:4] == 3'd6)&&(imm_value[11:7]==5'd0)) begin
in= Rm;
{out, c_to_alu} = {cin, in};
end
end
end
endmodule |
module register_file(in_address1,in_address2,in_address3,in_address4,
out_data1,out_data2,out_data3,out_data4,
write_address,write_data,write_enable,
write_address2, write_data2, write_enable2,
pc, pc_update, pc_write,
cspr, cspr_write, cspr_update, clk );
parameter N = 32; //register data size
reg [N-1:0] R [15:0]; //16, 32 bit registers
//reading
input [3:0]in_address1;
input [3:0]in_address2;
input [3:0]in_address3;
input [3:0]in_address4;
output reg [N-1:0]out_data1;
output reg [N-1:0]out_data2;
output reg [N-1:0]out_data3;
output reg [N-1:0]out_data4;
//writing
input [3:0]write_address;
input[N-1:0] write_data;
input [3:0]write_address2;
input[N-1:0] write_data2;
input clk;
input write_enable;
input write_enable2;
//pc
output reg [N-1:0]pc;
input pc_write;
input[N-1:0] pc_update;
//cspr
output reg [N-1:0]cspr;
input wire cspr_write;
input[N-1:0] cspr_update;
initial begin
cspr = 0;
R[0] = 0;
R[1] = 0;
R[2] = 0;
R[3] = 0;
R[4] = 0;
R[5] = 0;
R[6] = 0;
R[7] = 0;
R[8] = 0;
R[9] = 0;
R[10] = 0;
R[11] = 0;
R[12] = 0;
R[13] = 0;
R[14] = 0;
R[15] = 0; //pc = 0
end
always@(*) begin
pc = R[2^3];
end
always@(negedge clk) begin
out_data1=R[in_address1];
out_data2=R[in_address2];
out_data3=R[in_address3];
out_data4=R[in_address4];
if(pc_write == 1) R[15] = pc_update;
if(cspr_write == 1) cspr = cspr_update;
if (write_enable==1) R[write_address]=write_data;
if (write_enable2==1) R[write_address2]=write_data2;
end
endmodule |
module test;
reg clk;
DeepPipeline arm(clk);
initial
begin
clk = 1;
$dumpfile("test.vcd");
$dumpvars(0,test);
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
#1 clk = ~clk;
end
endmodule |
module instr_cache(PC,instr,read_enable,clk);
parameter instr_size = 32;
parameter N = 32;
parameter addr_size = 8; //pc supplies address to instr_cache, so addr_size is same as addr_width here. We ignore msb bits from r15.
reg [instr_size-1:0] M [256-1:0]; //2^addr_size-1, 32 bit instructions
input read_enable;
input [N-1:0]PC;
input clk;
output reg [instr_size-1:0] instr;
initial begin
//application code here.
M[0]= 32'he3a0000a;
M[1]= 32'he3a00000; //MOV r0, #10 ; Set up parameters
M[2]= 32'he3a01001; //MOV r1, #3
M[3] =32'he0913002; //MOV r4, #4;here
M[4]= 32'he1a01002; //MOV r9, #19
M[5]= 32'he1a02003; //add ro,r1,#43
M[6]= 32'h3afffffb; //MOV r7, #2
M[7]= 32'he3a07001; //
M[8]= 32'he3a07002; //
M[9]= 32'he3a07002; //
M[10]= 32'he3a07003; //
M[11]= 32'he3a07004; //
M[12]= 32'he3a07005; //
M[13]= 32'he3a07006; //
M[14]= 32'he3a07007; //
M[15]= 32'he3a07008; //
M[16]= 32'he3a07009; //
M[17]= 32'he3a07001; //
end
always @ (negedge clk)
begin
if(read_enable==1) begin
instr= M[PC[addr_size+1:2]];
end
end
endmodule |
module data_cache(data_address,in_data,out_data,read_enable,write_enable,clk,isByte);
parameter data_width = 8; //size of each data read, will be of width 16, i.e, half word by default.
parameter N =32;
parameter addr_width = 12; //It determines the number of data (half)words in memory
reg [data_width-1:0] M [2^addr_width-1:0]; //2^addr_width-1, 16 bit data
input [N-1 :0] data_address;
input read_enable;
input write_enable;
input clk;
input isByte;
output reg [N-1:0] out_data;
input [N-1 :0] in_data;
always @ (posedge read_enable, posedge write_enable)
begin
if(read_enable) begin
if(isByte == 1) out_data = {24'hzzzzzz, M[data_address[addr_width-1:0]]};
else out_data = { M[data_address[addr_width-1:0]+3], M[data_address[addr_width-1:0]+2], M[data_address[addr_width-1:0]+1] , M[data_address[addr_width-1:0]]};
end
else if(write_enable)
begin
if(isByte == 1) M[data_address[addr_width-1:0]]=in_data[data_width-1:0];
else { M[data_address[addr_width-1:0]+3], M[data_address[addr_width-1:0]+2], M[data_address[addr_width-1:0]+1] , M[data_address[addr_width-1:0]] } = in_data;
end
end
endmodule |
module register_test;
reg[3:0] read_address;
reg[3:0] write_address;
reg[31:0] write_data;
reg write_enable = 0;
reg[31:0] pc_update;
reg pc_write;
reg clk;
wire[31:0] out_data_1;
wire[31:0] cspr;
wire[31:0] pc;
register_file RegisterFile( //inputs
.in_address1(read_address),
.in_address2(),
.in_address3(),
.in_address4(write_address),
.universal_read_address(),
.in_data(write_data),
.write_enable(write_enable),
.pc_update(pc_update),
.pc_write(pc_write),
.cspr_write(),
.cspr_update(),
.clk(clk),
//outputs
.out_data1(out_data_1),
.out_data2(),
.out_data3(),
.universal_out_data(),
.pc(pc),
.cspr(cspr)
);
initial begin
#1 clk = 1;
#2 clk = 0;
#3 clk = 1;
read_address = 0;
#4 clk = 0;
$display("pc- %h" , pc);
#5 clk = 1;
pc_update = pc+4;
pc_write = 1;
#6 clk = 0;
$display("pc %h", pc);
end
endmodule |
module alu(opcode, operand_1, operand_2, result, nzcv_old, nzcv, c_from_shifter, isWriteback);
parameter N = 32;
input[3:0] opcode; //opcode of operation
input wire [N-1:0] operand_1; //operands:
input wire [N-1:0] operand_2;
input wire[3:0] nzcv_old; //old nzcv
input wire c_from_shifter;//this is carry flag from shifter. so that we can update carry flag for logical instructions
output reg isWriteback; //specifies if result is to be written back
output reg[N-1:0] result; //output
output reg [3:0] nzcv; //update nzcv register
/*condition code register. i.e, both read and write, nzcv[3] = n
nzcv[0] = v
nzcv[1] = c
nzcv[2] = z
nzcv[3] = n */
reg cin;
reg cout;
reg[N-1:0] neg;
always @(*) begin
nzcv= nzcv_old;
case(opcode)
//logical and
`AND: begin
result = operand_1 & operand_2;
nzcv[1] = c_from_shifter;
isWriteback = 1;
end
//xor
`EOR: begin
result = operand_1 ^ operand_2;
isWriteback = 1;
nzcv[1] = c_from_shifter;
end
//result = op1-op2
`SUB: begin
neg = -operand_2;
{cin, result[N-2:0]} = operand_1[N-2:0]+neg[N-2:0];
{cout, result[N-1]} = cin+ operand_1[N-1]+neg[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//result = op2-op1
`RSB: begin
neg = -operand_1;
{cin, result[N-2:0]} = operand_2[N-2:0]+neg[N-2:0];
{cout, result[N-1]} = cin+ operand_2[N-1]+neg[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//result = op1+op2
`ADD: begin
{cin, result[N-2:0]} = operand_1[N-2:0]+operand_2[N-2:0];
{cout, result[N-1]} = cin+ operand_1[N-1]+operand_2[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//result = op1+op2+c
`ADC: begin
{cin, result[N-2:0]} = operand_1[N-2:0]+operand_2[N-2:0]+nzcv_old[1];
{cout, result[N-1]} = cin+ operand_1[N-1]+operand_2[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//result = op1 – Op2 + C-1
`SBC: begin
neg = -operand_2;
{cin, result[N-2:0]} = operand_1[N-2:0]+neg[N-2:0]+nzcv_old[1]-1;
{cout, result[N-1]} = cin+ operand_1[N-1]+neg[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//result = op2-op1+c-1
`RSC: begin
neg = -operand_1;
{cin, result[N-2:0]} = operand_2[N-2:0]+neg[N-2:0]+nzcv_old[1]-1;
{cout, result[N-1]} = cin+ operand_2[N-1]+neg[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 1;
end
//same as AND but you don't write back
`TST: begin
result = operand_1 & operand_2;
isWriteback = 0;
nzcv[1] = c_from_shifter;
end
//same as EOR but you don't write back
`TEQ: begin
result = operand_1 ^ operand_2;
isWriteback = 0;
nzcv[1] = c_from_shifter;
end
//same as SUB but you don't write back
`CMP: begin
neg = -operand_2;
{cin, result[N-2:0]} = operand_1[N-2:0]+neg[N-2:0];
{cout, result[N-1]} = cin+ operand_1[N-1]+neg[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 0;
end
//same as ADD but you don't write back
`CMN: begin
{cin, result[N-2:0]} = operand_1[N-2:0]+operand_2[N-2:0];
{cout, result[N-1]} = cin+ operand_1[N-1]+operand_2[N-1];
nzcv[1] = cout; //carry flag
nzcv[0] = cin^cout; //overflow flag
isWriteback = 0;
end
//bitwise or
`ORR: begin
result = operand_1 | operand_2;
isWriteback = 1;
nzcv[1] = c_from_shifter;
end
//move. op1 ignored
`MOV: begin
result = operand_2;
isWriteback = 1;
nzcv[1] =c_from_shifter;
end
//res = op1 & ~op2
`BIC: begin
result = operand_1 & (~operand_2);
isWriteback = 1;
nzcv[1] =c_from_shifter;
end
//move negated op2
`MVN: begin
result = ~operand_2;
isWriteback = 1;
nzcv[1] = c_from_shifter;
end
endcase
nzcv[3] = result[N-1]; //n flag
nzcv[2] = (result == 0); // z flag
end
endmodule |
module SOC (
input wire CLK, // system clock
input wire RESET,// reset button
output reg [3:0] LEDS, // system LEDs
output wire TXD // UART transmit
);
wire clk;
wire resetn;
wire [31:0] IO_mem_addr;
wire [31:0] IO_mem_rdata;
wire [31:0] IO_mem_wdata;
wire IO_mem_wr;
Processor CPU(
.clk(clk),
.resetn(resetn),
.IO_mem_addr(IO_mem_addr),
.IO_mem_rdata(IO_mem_rdata),
.IO_mem_wdata(IO_mem_wdata),
.IO_mem_wr(IO_mem_wr)
);
wire [13:0] IO_wordaddr = IO_mem_addr[15:2];
// Memory-mapped IO in IO page, 1-hot addressing in word address.
localparam IO_LEDS_bit = 0; // W four leds
localparam IO_UART_DAT_bit = 1; // W data to send (8 bits)
localparam IO_UART_CNTL_bit = 2; // R status. bit 9: busy sending
always @(posedge clk) begin
if(IO_mem_wr & IO_wordaddr[IO_LEDS_bit]) begin
LEDS <= IO_mem_wdata[3:0];
end
end
wire uart_valid = IO_mem_wr & IO_wordaddr[IO_UART_DAT_bit];
wire uart_ready;
corescore_emitter_uart #(
.clk_freq_hz(`CPU_FREQ*1000000),
.baud_rate(1000000)
) UART(
.i_clk(clk),
.i_data(IO_mem_wdata[7:0]),
.i_valid(uart_valid),
.o_ready(uart_ready),
.o_uart_tx(TXD)
);
assign IO_mem_rdata =
IO_wordaddr[IO_UART_CNTL_bit] ? { 22'b0, !uart_ready, 9'b0}
: 32'b0;
`ifdef BENCH
always @(posedge clk) begin
if(uart_valid) begin
`ifdef CONFIG_DEBUG
$display("UART: %c", IO_mem_wdata[7:0]);
`else
$write("%c", IO_mem_wdata[7:0] );
$fflush(32'h8000_0001);
`endif
end
end
`endif
// Gearbox and reset circuitry.
Clockworks CW(
.CLK(CLK),
.RESET(RESET),
.clk(clk),
.resetn(resetn)
);
endmodule |
module Clockworks
(
input wire CLK, // clock pin of the board
input wire RESET, // reset pin of the board
output wire clk, // (optionally divided) clock for the design.
// divided if SLOW is different from zero.
output wire resetn // (optionally timed) negative reset for the design
);
parameter SLOW=0;
generate
/****************************************************
Slow speed mode.
- Create a clock divider to let observe what happens.
- Nothing special to do for reset
****************************************************/
if(SLOW != 0) begin
// Factor is 1 << slow_bit.
// Since simulation is approx. 16 times slower than
// actual device we use different factor for bosh.
`ifdef BENCH
localparam slow_bit=SLOW-4;
`else
localparam slow_bit=SLOW;
`endif
reg [slow_bit:0] slow_CLK = 0;
always @(posedge CLK) begin
slow_CLK <= slow_CLK + 1;
end
assign clk = slow_CLK[slow_bit];
`ifdef NEGATIVE_RESET
assign resetn = RESET;
`else
assign resetn = !RESET;
`endif
/****************************************************
High speed mode.
- Nothing special to do for the clock
- A timer that resets the design during the first
few microseconds, because reading in Ice40 BRAM
during the first few microseconds returns garbage !
(made me bang my head against the wall).
****************************************************/
end else begin
`ifdef CPU_FREQ
femtoPLL #(
.freq(`CPU_FREQ)
) pll(
.pclk(CLK),
.clk(clk)
);
`else
assign clk=CLK;
`endif
// Preserve resources on Ice40HX1K (IceStick) with
// carefully tuned counter (12 bits suffice).
// For other FPGAs, use larger counter.
`ifdef ICE_STICK
reg [11:0] reset_cnt = 0;
`else
reg [15:0] reset_cnt = 0;
`endif
assign resetn = &reset_cnt;
`ifdef NEGATIVE_RESET
always @(posedge clk,negedge RESET) begin
if(!RESET) begin
reset_cnt <= 0;
end else begin
reset_cnt <= reset_cnt + !resetn;
end
end
`else
always @(posedge clk,posedge RESET) begin
if(RESET) begin
reset_cnt <= 0;
end else begin
/* verilator lint_off WIDTH */
reset_cnt <= reset_cnt + !resetn;
/* verilator lint_on WIDTH */
end
end
`endif
end
endgenerate
endmodule |
module Processor (
input wire clk,
input wire resetn,
output wire [31:0] IO_mem_addr, // IO memory address
input wire [31:0] IO_mem_rdata, // data read from IO memory
output wire [31:0] IO_mem_wdata, // data written to IO memory
output wire IO_mem_wr // IO write flag
);
/******************************************************************************/
/* state machine (removed in next step that has a true pipeline) */
localparam F_bit = 0; localparam F_state = 1 << F_bit;
localparam D_bit = 1; localparam D_state = 1 << D_bit;
localparam E_bit = 2; localparam E_state = 1 << E_bit;
localparam M_bit = 3; localparam M_state = 1 << M_bit;
localparam W_bit = 4; localparam W_state = 1 << W_bit;
reg [4:0] state;
wire halt;
always @(posedge clk) begin
if(!resetn) begin
state <= F_state;
end else if(!halt) begin
state <= {state[3:0],state[4]};
end
end
/******************************************************************************/
/*
Reminder for the 10 RISC-V codeops
----------------------------------
ALUreg // rd <- rs1 OP rs2
ALUimm // rd <- rs1 OP Iimm
Branch // if(rs1 OP rs2) PC<-PC+Bimm
JALR // rd <- PC+4; PC<-rs1+Iimm
JAL // rd <- PC+4; PC<-PC+Jimm
AUIPC // rd <- PC + Uimm
LUI // rd <- Uimm
Load // rd <- mem[rs1+Iimm]
Store // mem[rs1+Simm] <- rs2
SYSTEM // special
*/
/******************************************************************************/
reg [63:0] cycle;
reg [63:0] instret;
always @(posedge clk) begin
cycle <= !resetn ? 0 : cycle + 1;
end
/******************************************************************************/
localparam NOP = 32'b0000000_00000_00000_000_00000_0110011;
/*** F: Instruction fetch ***/
reg [31:0] F_PC;
/** These two signals come from the Execute stage **/
wire [31:0] jumpOrBranchAddress;
wire jumpOrBranch;
reg [31:0] PROGROM[0:16383]; // 16384 4-bytes words
// 64 Kb of program ROM
initial begin
$readmemh("PROGROM.hex",PROGROM);
end
always @(posedge clk) begin
if(!resetn) begin
F_PC <= 0;
end else if(state[F_bit]) begin
FD_instr <= PROGROM[F_PC[15:2]];
FD_PC <= F_PC;
F_PC <= F_PC+4;
end else if(state[M_bit] & jumpOrBranch) begin
F_PC <= jumpOrBranchAddress;
end
end
/******************************************************************************/
reg [31:0] FD_PC;
reg [31:0] FD_instr;
/******************************************************************************/
/*** D: Instruction decode ***/
/** These three signals come from the Writeback stage **/
wire wbEnable;
wire [31:0] wbData;
wire [4:0] wbRdId;
reg [31:0] registerFile [0:31];
wire D_isLoad = (FD_instr[6:2] == 5'b00000);
wire D_isJALorJALR = (FD_instr[2] & FD_instr[6]);
wire D_isJAL = FD_instr[3];
wire D_isALUreg = (FD_instr[6:2] == 5'b01100);
wire D_isBranch = (FD_instr[6:2] == 5'b11000);
wire D_isStore = (FD_instr[6:2] == 5'b01000);
wire D_isSYSTEM = (FD_instr[6:2] == 5'b11100);
wire [31:0] D_Iimm = {{21{FD_instr[31]}},FD_instr[30:20]};
wire [31:0] D_Simm = {{21{FD_instr[31]}},FD_instr[30:25],FD_instr[11:7]};
wire [31:0] D_Uimm = {FD_instr[31:12],{12{1'b0}}};
wire [31:0] D_Jimm =
{{12{FD_instr[31]}},FD_instr[19:12],FD_instr[20],FD_instr[30:21],1'b0};
wire [31:0] D_Bimm =
{{20{FD_instr[31]}},FD_instr[7],FD_instr[30:25],FD_instr[11:8],1'b0};
// Load-Store
wire [31:0] D_addr = DE_rs1 + (D_isLoad ? D_Iimm : D_Simm);
wire D_isB = (FD_instr[13:12] == 2'b00);
wire D_isH = (FD_instr[13:12] == 2'b01);
wire [3:0] D_storeMask = D_isB ?
(D_addr[1] ?
(D_addr[0] ? 4'b1000 : 4'b0100) :
(D_addr[0] ? 4'b0010 : 4'b0001)
) :
D_isH ? (D_addr[1] ? 4'b1100 : 4'b0011) :
4'b1111 ;
wire D_isRAM = !D_addr[22];
always @(posedge clk) begin
if(state[D_bit]) begin
DE_isALUreg <= D_isALUreg;
DE_isBranch <= D_isBranch;
DE_isALUregorBranch <= D_isALUreg || D_isBranch;
DE_isJALR <= (FD_instr[6:2] == 5'b11001);
DE_isLoad <= D_isLoad;
DE_isStore <= D_isStore;
DE_isCSRRS <= D_isSYSTEM && (FD_instr[14:12] == 3'b010);
DE_isEBREAK <= D_isSYSTEM && (FD_instr[14:12] == 3'b000);
DE_Iimm <= D_Iimm;
DE_rdId <= FD_instr[11:7];
DE_funct3 <= FD_instr[14:12];
DE_funct3_is <= 8'b00000001 << FD_instr[14:12];
DE_funct7 <= FD_instr[30];
DE_csrId <= {FD_instr[27],FD_instr[21]};
DE_addr <= D_addr;
// Code below is equivalent to:
// DE_PCplus4orUimm =
// ((isLUI ? 0 : FD_PC)) + ((isJAL | isJALR) ? 4 : Uimm)
// (knowing that isLUI | isAUIPC | isJAL | isJALR)
DE_PCplus4orUimm <= ({32{FD_instr[6:5]!=2'b01}} & FD_PC) +
(D_isJALorJALR ? 4 : D_Uimm);
DE_isJALorJALRorLUIorAUIPC <= FD_instr[2];
DE_PCplusBorJimm <= FD_PC + (D_isJAL ? D_Jimm : D_Bimm);
DE_isJALorJALR <= (FD_instr[2] & FD_instr[6]);
DE_storeMask <= D_storeMask & {4{D_isRAM & D_isStore}};
end
end
always @(posedge clk) begin
if(state[W_bit] & wbEnable) begin
registerFile[wbRdId] <= wbData;
end
end
/******************************************************************************/
wire [31:0] DE_rs1 = registerFile[FD_instr[19:15]];
wire [31:0] DE_rs2 = registerFile[FD_instr[24:20]];
reg DE_isALUreg;
reg DE_isBranch;
reg DE_isJALR;
reg DE_isLoad;
reg DE_isStore;
reg DE_isEBREAK;
reg DE_isCSRRS;
reg [31:0] DE_Iimm;
reg [4:0] DE_rdId;
reg [1:0] DE_csrId;
reg [2:0] DE_funct3;
(* onehot *) reg [7:0] DE_funct3_is;
reg [5:5] DE_funct7;
reg [31:0] DE_addr;
reg DE_isJALorJALRorLUIorAUIPC;
reg DE_isJALorJALR;
reg DE_isALUregorBranch;
reg [31:0] DE_PCplus4orUimm;
reg [31:0] DE_PCplusBorJimm;
reg [3:0] DE_storeMask;
/******************************************************************************/
/*** E: Execute ***/
/*********** the ALU *************************************************/
wire [31:0] E_aluIn1 = DE_rs1;
wire [31:0] E_aluIn2 = DE_isALUregorBranch ? DE_rs2 : DE_Iimm;
wire E_minus = DE_funct7[5] & DE_isALUreg;
wire E_arith_shift = DE_funct7[5];
// The adder is used by both arithmetic instructions and JALR.
wire [31:0] E_aluPlus = E_aluIn1 + E_aluIn2;
// Use a single 33 bits subtract to do subtraction and all comparisons
// (trick borrowed from swapforth/J1)
wire [32:0] E_aluMinus = {1'b1, ~E_aluIn2} + {1'b0,E_aluIn1} + 33'b1;
wire E_LT =
(E_aluIn1[31] ^ E_aluIn2[31]) ? E_aluIn1[31] : E_aluMinus[32];
wire E_LTU = E_aluMinus[32];
wire E_EQ = (E_aluMinus[31:0] == 0);
// Flip a 32 bit word. Used by the shifter (a single shifter for
// left and right shifts, saves silicium !)
function [31:0] flip32;
input [31:0] x;
flip32 = {x[ 0], x[ 1], x[ 2], x[ 3], x[ 4], x[ 5], x[ 6], x[ 7],
x[ 8], x[ 9], x[10], x[11], x[12], x[13], x[14], x[15],
x[16], x[17], x[18], x[19], x[20], x[21], x[22], x[23],
x[24], x[25], x[26], x[27], x[28], x[29], x[30], x[31]};
endfunction
wire [31:0] E_shifter_in = DE_funct3_is[1] ? flip32(E_aluIn1) : E_aluIn1;
/* verilator lint_off WIDTH */
wire [31:0] E_rightshift =
$signed({E_arith_shift & E_aluIn1[31], E_shifter_in}) >>> E_aluIn2[4:0];
/* verilator lint_on WIDTH */
wire [31:0] E_leftshift = flip32(E_rightshift);
wire [31:0] E_aluOut =
DE_funct3_is[0] ? (E_minus ? E_aluMinus[31:0] : E_aluPlus) :
DE_funct3_is[1] ? E_leftshift :
DE_funct3_is[2] ? {31'b0, E_LT} :
DE_funct3_is[3] ? {31'b0, E_LTU} :
DE_funct3_is[4] ? E_aluIn1 ^ E_aluIn2 :
DE_funct3_is[5] ? E_rightshift :
DE_funct3_is[6] ? E_aluIn1 | E_aluIn2 :
E_aluIn1 & E_aluIn2 ;
/****************** Branch ******************************/
wire E_takeBranch =
DE_funct3_is[0] ? E_EQ :
DE_funct3_is[1] ? !E_EQ :
DE_funct3_is[4] ? E_LT :
DE_funct3_is[5] ? !E_LT :
DE_funct3_is[6] ? E_LTU :
!E_LTU ;
/****************** Store ******************************/
wire E_isB = (DE_funct3[1:0] == 2'b00);
wire E_isH = (DE_funct3[1:0] == 2'b01);
wire [31:0] E_STORE_data;
assign E_STORE_data[ 7: 0] = DE_rs2[7:0];
assign E_STORE_data[15: 8] = DE_addr[0] ? DE_rs2[7:0] : DE_rs2[15: 8] ;
assign E_STORE_data[23:16] = DE_addr[1] ? DE_rs2[7:0] : DE_rs2[23:16] ;
assign E_STORE_data[31:24] = DE_addr[0] ? DE_rs2[7:0] :
DE_addr[1] ? DE_rs2[15:8] : DE_rs2[31:24] ;
wire E_isIO = DE_addr[22];
wire E_isRAM = !E_isIO;
assign IO_mem_addr = DE_addr;
assign IO_mem_wr = state[E_bit] & DE_isStore & E_isIO;
assign IO_mem_wdata = DE_rs2;
reg [31:0] DATARAM [0:16383]; // 16384 4-bytes words
// 64 Kb of data RAM in total
wire [13:0] E_word_addr = DE_addr[15:2];
always @(posedge clk) begin
if(state[E_bit]) begin
EM_Mdata <= DATARAM[E_word_addr];
if(DE_storeMask[0]) DATARAM[E_word_addr][ 7:0 ] <= E_STORE_data[ 7:0 ];
if(DE_storeMask[1]) DATARAM[E_word_addr][15:8 ] <= E_STORE_data[15:8 ];
if(DE_storeMask[2]) DATARAM[E_word_addr][23:16] <= E_STORE_data[23:16];
if(DE_storeMask[3]) DATARAM[E_word_addr][31:24] <= E_STORE_data[31:24];
end
end
always @(posedge clk) begin
if(state[E_bit]) begin
EM_IOdata <= IO_mem_rdata;
case(DE_csrId)
2'b00: EM_CSRdata <= cycle[31:0];
2'b10: EM_CSRdata <= cycle[63:32];
2'b01: EM_CSRdata <= instret[31:0];
2'b11: EM_CSRdata <= instret[63:32];
endcase
end
end
initial begin
$readmemh("DATARAM.hex",DATARAM);
end
/**************************************************************/
always @(posedge clk) begin
if(state[E_bit]) begin
EM_Eresult <= DE_isJALorJALRorLUIorAUIPC ?
DE_PCplus4orUimm : E_aluOut;
EM_JumpOrBranch <= DE_isJALorJALR ||
(DE_isBranch && E_takeBranch);
EM_JumpOrBranchAddress <= DE_isJALR ? {E_aluPlus[31:1],1'b0}
: DE_PCplusBorJimm;
EM_addr <= DE_addr[1:0];
EM_isIO <= DE_addr[22];
EM_isLoad <= DE_isLoad;
EM_isStore <= DE_isStore;
EM_isBranch <= DE_isBranch;
EM_isCSRRS <= DE_isCSRRS;
EM_rdId <= DE_rdId;
EM_funct3 <= DE_funct3;
end
end
assign halt = resetn & DE_isEBREAK;
/******************************************************************************/
reg [31:0] EM_Eresult;
reg [1:0] EM_addr;
reg EM_isIO;
reg EM_isLoad;
reg EM_isStore;
reg EM_isBranch;
reg EM_isCSRRS;
reg [4:0] EM_rdId;
reg [2:0] EM_funct3;
reg [31:0] EM_CSRdata;
reg [31:0] EM_Mdata;
reg [31:0] EM_IOdata;
reg EM_JumpOrBranch;
reg [31:0] EM_JumpOrBranchAddress;
/******************************************************************************/
/*** M: Memory ***/
wire M_isB = (EM_funct3[1:0] == 2'b00);
wire M_isH = (EM_funct3[1:0] == 2'b01);
wire M_sext = !EM_funct3[2];
/*************** LOAD ****************************/
wire [15:0] M_LOAD_H=EM_addr[1] ? EM_Mdata[31:16]: EM_Mdata[15:0];
wire [7:0] M_LOAD_B=EM_addr[0] ? M_LOAD_H[15:8] : M_LOAD_H[7:0];
wire M_LOAD_sign=M_sext & (M_isB ? M_LOAD_B[7] : M_LOAD_H[15]);
wire [31:0] M_Mresult = M_isB ? {{24{M_LOAD_sign}},M_LOAD_B} :
M_isH ? {{16{M_LOAD_sign}},M_LOAD_H} :
EM_Mdata ;
always @(posedge clk) begin
if(state[M_bit]) begin
MW_rdId <= EM_rdId;
MW_WBdata <= EM_isLoad ? (EM_isIO ? EM_IOdata : M_Mresult) :
EM_isCSRRS ? EM_CSRdata :
EM_Eresult ;
MW_wbEnable <= !EM_isBranch && !EM_isStore && (EM_rdId != 0);
instret <= instret + 1;
end
if(!resetn) begin
instret <= 0;
end
end
/******************************************************************************/
reg [31:0] MW_WBdata;
reg [4:0] MW_rdId;
reg MW_wbEnable;
/******************************************************************************/
assign wbData = MW_WBdata;
assign wbEnable = MW_wbEnable;
assign wbRdId = MW_rdId;
/******************************************************************************/
assign jumpOrBranchAddress = EM_JumpOrBranchAddress;
assign jumpOrBranch = EM_JumpOrBranch;
/******************************************************************************/
`ifdef BENCH
always @(posedge clk) begin
if(halt) $finish();
end
`endif
/******************************************************************************/
endmodule |
module OneShot(
input pulse,
input clk,
input rst,
output reg out
);
initial out = 0;
parameter waiting_l = 2'b00, on = 2'b01, waiting_h = 2'b10;
reg[1:0] next_state, current_state;
always @ (posedge clk or posedge rst) begin
if(rst) begin
current_state <= waiting_l;
end
else begin
current_state <= next_state;
end
end
always @ (current_state or pulse) begin
if(current_state == on) begin
next_state <= waiting_h;
end
else if(current_state == waiting_h) begin
if(pulse) begin
next_state <= waiting_h;
end
else begin
next_state <= waiting_l;
end
end
else if(pulse) begin
next_state<= on;
end
else begin
next_state<= waiting_l;
end
end
always @(current_state or rst) begin
if(rst)
out <= 1'b0;
else if(current_state == on)
out <= 1'b1;
else
out <= 1'b0;
end
endmodule |
module tx_test;
// Inputs
wire rx;
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg rxing;
// Outputs
wire tx;
// Instantiate the Unit Under Test (UUT)
tx_container uut (
.tx(tx),
.txing(txing),
.rx(rx),
.rxing(rxing),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data)
);
assign rx = tx;
initial begin
// Initialize Inputs
address = 11'h28;
rxing = 0;
clk = 1'b0;
baud_clk = 1'b0;
rst = 1'b1;
//data = 64'hAAAAAAAAAAAAAAAA;
data = 64'hA83;
send_data = 1'b0;
// Add stimulus here
#100 rst = 0;
#101 send_data = 1'b1;
#3000 send_data = 1'b0;
#310000 $stop;
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule |
module shift_reg(
input rx,
output reg[(reg_length-1):0] shifted_bus,
output reg finished_rx,
input rst,
input baud_clk
);
parameter reg_length = 150;
initial finished_rx = 0;
parameter idle = 2'b00, reading = 2'b01, finished = 2'b10, finished_and_waiting = 2'b11;
reg[1:0] current_state, next_state;
reg [(reg_length-1):0] bitShiftReg = {reg_length{1'b1}};
always @(posedge baud_clk or posedge rst) begin
if(rst) begin
bitShiftReg <= {reg_length{1'b1}};
current_state <= idle;
end
else begin
current_state <= next_state;
bitShiftReg <= {bitShiftReg[(reg_length-2):0],rx};
end
end
always @(rx or bitShiftReg or current_state) begin
case(current_state)
idle: begin
if(rx == 1)
next_state <= idle;
else
next_state <= reading;
end
reading: begin
if(bitShiftReg[6:0] == {7{1'b1}})
next_state <= finished;
else
next_state <= reading;
end
finished: begin
next_state<= finished_and_waiting;
end
default: begin
next_state<=idle;
end
endcase
end
always @ (current_state) begin
if(current_state == finished)
finished_rx <= 1;
else
finished_rx <= 0;
end
always @ (posedge finished_rx or posedge rst) begin
if(rst)
shifted_bus <= {reg_length{1'b1}};
else
shifted_bus <= bitShiftReg;
end
endmodule |
module can_tx(
output reg tx,
output reg can_bitstuff,
output reg txing,
input rx,
input[10:0] address,
input clk,
input baud_clk,
input rst,
input [63:0] data,
input send_data,
input bitstuffed_output,
input clear_to_tx
);
assign rx_buf = rx;
parameter all_ones = 15'b111111111111111;
parameter idle = 8'h0, start_of_frame = 8'h1, addressing =8'h2 ,rtr = 8'h3 ,ide = 8'h4, reserve_bit = 8'h5, num_of_bytes = 8'h6,
data_out = 8'h7, crc_out = 8'h8, crc_delimiter = 8'h9 , ack = 8'hA, ack_delimiter = 8'hB, end_of_frame = 8'hC, waiting = 8'hD;
parameter bytes = 5'd8;
reg[10:0] address_count = 0, crc_count = 0, eof_count = 0 , data_bit_count = 0, data_byte_count = 0;
reg[7:0] c_state=0, n_state=0;
initial txing = 0;
reg[14:0] crc_output, crc_holder;
wire one_shotted_send;
wire[14:0] crc_buff;
CRC cyclic_red_check(data, one_shotted_send, crc_buff,rst,clk);
OneShot os(send_data, clk, rst, one_shotted_send);
always @(crc_buff or crc_holder) begin
if(crc_buff != all_ones)
crc_output <= crc_buff;
else
crc_output <= crc_holder;
end
always @ (posedge clk or posedge rst) begin
if(rst == 1) begin
crc_holder <= 15'd0;
end
else begin
crc_holder <= crc_output;
end
end
//Update Logic
always @ (posedge baud_clk or posedge rst) begin
if(rst == 1) begin
c_state <= 32'd0;
end
else begin
c_state <= n_state;
end
end
//Counting Logic
always @ (posedge baud_clk) begin
case(c_state)
idle: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
waiting: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
start_of_frame:begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
addressing: begin
address_count <= address_count + 1'b1;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
rtr: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ide: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
reserve_bit: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
num_of_bytes: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= data_byte_count +1'b1;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
data_out: begin
address_count <= 11'd0;
data_bit_count<= data_bit_count +1'b1;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
crc_out: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= crc_count + 1'b1;
eof_count <= 11'd0;
end
crc_delimiter: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ack: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ack_delimiter:begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
end_of_frame: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= eof_count +1'b1;
end
default: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
endcase
end
//Next State Logic
always @ (c_state or rx_buf or data or send_data or address_count or bitstuffed_output or data_byte_count
or data_bit_count or crc_count or eof_count or clear_to_tx or crc_output) begin
case(c_state)
idle: begin
if(send_data && clear_to_tx) begin
n_state <= start_of_frame;
end
else begin
n_state <= idle;
end
end
start_of_frame: begin
if(!rx_buf) begin
n_state <= addressing;
end
else begin
n_state <= waiting;
end
end
waiting: begin
if(send_data && clear_to_tx) begin
n_state <= start_of_frame;
end
else begin
n_state <= waiting;
end
end
addressing: begin
if(rx_buf != bitstuffed_output) begin
n_state <= waiting; //Lost Arbitration
end
else if(address_count == 11'd10) begin
n_state <= rtr;
end
else begin
n_state <= addressing;
end
end
rtr: begin
n_state <= ide;
end
ide: begin
n_state <= reserve_bit;
end
reserve_bit: begin
n_state <= num_of_bytes;
end
num_of_bytes: begin
if(data_byte_count == 11'd3) begin
n_state <= data_out;
end
else begin
n_state <= num_of_bytes;
end
end
data_out: begin
if(data_bit_count == 11'd63) begin
n_state <= crc_out;
end
else begin
n_state <= data_out;
end
end
crc_out: begin
if(crc_count == 11'd14) begin
n_state <= crc_delimiter;
end
else begin
n_state <= crc_out;
end
end
crc_delimiter: begin
n_state <= ack;
end
ack: begin
n_state <= ack_delimiter;
end
ack_delimiter: begin
n_state <= end_of_frame;
end
end_of_frame: begin
if(eof_count == 11'd6) begin
n_state <= idle;
end
else begin
n_state <= end_of_frame;
end
end
default:
begin
n_state <= idle;
end
endcase
end
//Output Logic
always @(c_state or address or data or crc_output or crc_count or data_byte_count or data_bit_count or address_count) begin
case(c_state)
idle: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b0;
end
addressing: begin
tx <= address[11'd10-address_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
start_of_frame: begin
tx<= 0;
can_bitstuff <= 1'b0;
txing <= 1'b1;
end
rtr: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
ide: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
reserve_bit: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
num_of_bytes: begin
tx <= bytes[11'd3-data_byte_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
data_out: begin
tx <= data[11'd63-data_bit_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
crc_out: begin
tx <= crc_output[11'd14-crc_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
crc_delimiter: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
ack: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
ack_delimiter:begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
end_of_frame: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
waiting: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b0;
end
default: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
endcase
end
endmodule |
module CANIPCORETEST;
// Inputs
reg can_clk;
reg can_phy_rx;
reg bus2ip_reset;
reg bus2ip_rnw;
reg bus2ip_cs;
reg sys_clk;
reg [0:5] bus2ip_addr;
reg [0:31] bus2ip_data;
// Outputs
wire ip2bus_intrevent;
wire ip2bus_error;
wire ip2bus_ack;
wire can_phy_tx;
wire [0:31] ip2bus_data;
// Instantiate the Unit Under Test (UUT)
CAN_BUS_Model uut (
.can_phy_rx(can_phy_rx),
.can_clk(can_clk),
.bus2ip_reset(bus2ip_reset),
.ip2bus_intrevent(ip2bus_intrevent),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_cs(bus2ip_cs),
.ip2bus_error(ip2bus_error),
.sys_clk(sys_clk),
.ip2bus_ack(ip2bus_ack),
.can_phy_tx(can_phy_tx),
.ip2bus_data(ip2bus_data),
.bus2ip_addr(bus2ip_addr),
.bus2ip_data(bus2ip_data)
);
initial begin
// Initialize Inputs
can_clk = 0;
bus2ip_reset = 1;
bus2ip_rnw = 1;
bus2ip_cs = 0;
sys_clk = 0;
bus2ip_addr = 6'd3;
bus2ip_data = 32'd42;
can_phy_rx = 1;
// Wait 100 ns for global reset to finish
#100;
bus2ip_reset = 0;
#10;
bus2ip_data = 32'd42;
bus2ip_addr = 6'd3;
#10;
bus2ip_cs = 1;
bus2ip_rnw = 0;
#50
bus2ip_cs = 0;
bus2ip_rnw = 1;
// Add stimulus here
end
always #5 sys_clk=~sys_clk;
always #25 can_clk=~can_clk;
endmodule |
module tx_container(
output reg tx,
output txing,
input rx,
input rxing,
input[10:0] address,
input clk,
input baud_clk,
input rst,
input [63:0] data,
input send_data
);
parameter init = 2'h0, ones = 2'h1, zeros = 2'h2;
assign clear_to_tx =1;
reg bit_stuffing = 0;
reg[1:0] c_state=0, n_state=0, p_state = 0;
reg[31:0] bit_stuffing_count = 0;
wire can_bitstuff;
can_tx tx_block(tx_buf,can_bitstuff,txing,rx,address,clk,baud_clk,rst,data,send_data,tx,clear_to_tx);
always @ (posedge clk or posedge rst) begin
if(rst) begin
bit_stuffing_count<= 0;
bit_stuffing <= 0;
end
else begin
if(n_state != c_state) begin
bit_stuffing_count<= 0;
bit_stuffing <= 0;
end
else if(!can_bitstuff) begin
bit_stuffing_count <= 0;
bit_stuffing <= 0;
end
else if(bit_stuffing_count >= 5000)begin
bit_stuffing_count <= 0;
bit_stuffing <= 0;
end
else if(bit_stuffing_count >= 4000)begin
bit_stuffing_count <= bit_stuffing_count + 1;
bit_stuffing <= 1;
end
else begin
bit_stuffing_count <= bit_stuffing_count +1;
bit_stuffing <= 0;
end
end
end
always @ (posedge clk) begin
c_state <= n_state;
end
always @ (tx_buf) begin
if(tx_buf == 1) begin
n_state<= ones;
end
else begin
n_state <= zeros;
end
end
always @ (bit_stuffing or tx_buf) begin
if(bit_stuffing) begin
tx <= ~tx_buf;
end
else begin
tx <= tx_buf;
end
end
endmodule |
module BaudGen(clk,rst,baud_clk);
input clk,rst;
output reg baud_clk;
//EndCount is equal to clk frequency/baud frequency
// Therefore 400MHz/500kHz = 800
parameter EndCount = 10'd800;
reg[9:0] count = 0;
always@(posedge clk)begin
if(rst == 1) begin
count <=10'd0;
baud_clk <= 10'd0;
end
else if(count == EndCount) begin
count <= 10'd0;
baud_clk <= ~baud_clk;
end
else begin
count <= count + 10'd1;
baud_clk <= baud_clk;
end
end
endmodule |
module Tx_test_internal;
// Inputs
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
// Outputs
wire tx;
wire can_bitstuff;
wire txing;
// Instantiate the Unit Under Test (UUT)
can_tx uut (
.tx(tx),
.can_bitstuff(can_bitstuff),
.txing(txing),
.rx(rx),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data),
.bitstuffed_output(bitstuffed_output),
.clear_to_tx(clear_to_tx)
);
initial begin
// Initialize Inputs
address = 11'h28;
clk = 0;
baud_clk = 0;
rst = 1;
data = 43;
send_data = 0;
clear_to_tx = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
send_data = 1;
clear_to_tx = 1;
#300000 $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule |
module Main(
output CAN_TX,
input CAN_RX,
input RESET,
input CLOCK_SIGNAL_IN,
input send_data,
input[7:0] transmit_data
);
wire[63:0] tx_data;
wire txing;
assign tx_data = {8{transmit_data}};
//Device address, arbitrarily chosen
parameter address = 11'h25, rxing = 1'b1;
//Clock Generator (100MHz in, 400MHz out)
Clock_gen clock_block(CLOCK_SIGNAL_IN,clk);
//Baud Clk Generator(currently set for baud of 500kHz)
BaudGen baud_calc(clk,RESET,baud_clk);
//Tx Block
//can_tx tx_block(CAN_TX,CAN_RX,address,clk,baud_clk,RESET,tx_data,send_data);
tx_container tx_can(CAN_TX,txing,CAN_RX,rxing,address,clk,baud_clk,RESET,tx_data,send_data);
//rx_container rx_can(rx_data,rxing,txing,CAN_RX,clk,baud_clk,RESET);
//Rx goes here
endmodule |
module Main_test;
// Inputs
assign CAN_RX = CAN_TX;
reg RESET;
reg CLOCK_SIGNAL_IN;
reg send_data;
reg [7:0] transmit_data;
// Outputs
wire CAN_TX;
// Instantiate the Unit Under Test (UUT)
Main uut (
.CAN_TX(CAN_TX),
.CAN_RX(CAN_RX),
.RESET(RESET),
.CLOCK_SIGNAL_IN(CLOCK_SIGNAL_IN),
.send_data(send_data),
.transmit_data(transmit_data)
);
initial begin
// Initialize Inputs
RESET = 1;
CLOCK_SIGNAL_IN = 0;
send_data = 0;
transmit_data = 8'b11100011;
// Wait 100 ns for global reset to finish
#100;
#100 RESET = 0;
#1000 send_data = 1;
#100000 $stop;
// Add stimulus here
end
always #10 CLOCK_SIGNAL_IN = ~CLOCK_SIGNAL_IN;
endmodule |
module OneShotTest;
// Inputs
reg pulse;
reg clk;
reg rst;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
// Initialize Inputs
pulse = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
pulse = 1;
#100; $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
endmodule |
module BitshiftTest;
// Inputs
reg rx;
reg rst;
reg baud_clk;
// Outputs
wire [149:0] shifted_bus;
// Instantiate the Unit Under Test (UUT)
shift_reg uut (
.rx(rx),
.shifted_bus(shifted_bus),
.finished_rx(finished_rx),
.rst(rst),
.baud_clk(baud_clk)
);
initial begin
// Initialize Inputs
rx = 1'b1;
rst = 1;
baud_clk = 0;
#10 rst = 1'b0;
#1000 rx = 1'b0;
#12000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#4100 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#6000 rx = 1'b0;
#2000 rx = 1'b1;
#10000 rx = 1'b0;
#6000 rx = 1'b1;
#70000; $stop;
end
always #1000 baud_clk=~baud_clk;
endmodule |
module top (
input clk,
input rst,
inout led,
inout [5:0] lcd
);
parameter EXCEPTION_HANDLING = 0;
// self-reset w/ self-detect logic
// self-reset just start w/ a value and decrement it until zero; at same time, sample the
// default external reset value at startup, supposing that you are not pressing the button
// at the programming moment! supposed to work in *any* board!
reg [3:0] reset_counter = 15; // self-reset
reg reset = 1; // global reset
reg extrst = 1; // external reset default value (sampled at startup)
always@(posedge clk)
begin
reset_counter <= reset_counter ? reset_counter-1 : // while(reset_counter--);
extrst!=rst ? 13 : 0; // rst != extrst -> restart counter
reset <= reset_counter ? 1 : 0; // while not zero, reset = 1, after that use extrst
extrst <= (reset_counter==14) ? rst : extrst; // sample the reset button and store the value when not in reset
end
// BUS
wire [31:0] busAddress;
wire [31:0] busWriteEnable;
wire [31:0] busDataIn;
reg [31:0] busDataOut = 0;
wire busValid; // 1 => Start bus transaction, 0 => Don't use bus
wire busInstr; // 1 => Instruction, 0 => Data
reg busReady = 0; // 1 => Bus is ready with data, 0 => If bus is busy
// CPU
wire [31:0] cpuDataIn;
wire [31:0] cpuDataOut;
wire [31:0] cpuAddress;
wire cpuBusWriteEnable;
wire cpuBusValid;
wire cpuBusInstr;
wire cpuBusReady;
// PORT
wire [31:0] portDataOutA;
wire [31:0] portDataOutB;
wire [31:0] portDataIn;
wire portChipSelectA;
wire portChipSelectB;
wire portWriteIO;
wire portWriteDirection;
wire [31:0] portDirectionA;
wire [31:0] portDirectionB;
wire [31:0] _IOPortA;
wire [31:0] _IOPortB;
// Timer 0
wire [31:0] t0DataIn;
wire [31:0] t0DataOut;
wire t0ChipSelect;
wire t0Write;
wire t0WriteCommand;
// CSR
reg [31:0] csrDataIn;
wire [63:0] instructionsExecuted;
wire [31:0] csrDataOut;
wire [11:0] csrNumber;
wire csrWriteEnable;
reg [63:0] cycleCount;
CPU # (
.EXCEPTION_HANDLING(EXCEPTION_HANDLING)
) cpu (
clk,
reset,
cpuDataIn,
cpuDataOut,
cpuAddress,
cpuBusValid,
cpuBusInstr,
cpuBusReady,
cpuBusWriteEnable,
csrDataIn,
csrDataOut,
csrNumber,
csrWriteEnable,
instructionsExecuted
);
DigitalPort portA (clk, reset, portChipSelectA, portWriteIO, portWriteDirection, portDataIn, portDataOutA, portDirectionA, _IOPortA);
DigitalPort portB (clk, reset, portChipSelectB, portWriteIO, portWriteDirection, portDataIn, portDataOutB, portDirectionB, _IOPortB);
Timer t0 (clk, reset, t0ChipSelect, t0Write, t0WriteCommand, t0DataIn, t0DataOut);
assign led = _IOPortB[0];
assign lcd = _IOPortA[5:0];
// assign IOPortA = {_IOPortA[0], 31'b0};
// assign IOPortB = {_IOPortB[0], 31'b0};
// Memory
reg [31:0] ROM [0:8191]; // 32KB
reg [31:0] RAM [0:8191]; // 32KB
reg [31:0] EXCP [0:15]; // 1KB
reg [31:0] ROMFF;
reg [31:0] RAMFF;
reg [31:0] EXCPF;
wire romChipSelect;
wire ramChipSelect;
wire excpChipSelect;
initial begin
$readmemh("gcc/rom.mem", ROM);
if (EXCEPTION_HANDLING == 1) $readmemh("gcc/excp.mem", EXCP);
end
always @(posedge clk)
begin
if (!reset)
begin
if (!busValid)
begin
busReady <= 0;
end
else
begin
if (busWriteEnable)
begin
if (romChipSelect) ROM[busAddress[15:2]] <= busDataIn;
else if (ramChipSelect) RAM[busAddress[14:2]] <= busDataIn;
else if (excpChipSelect && EXCEPTION_HANDLING == 1) EXCP[busAddress[9:2]-10'h1E0] <= busDataIn;
else if (portChipSelectA || portChipSelectB)
begin
`ifdef SIMULATION
if (portChipSelectA) $info("Wrote %08x on PORTA (IO=%01d, DIR=%01d, PC=%08x)", busDataIn, portWriteIO, portWriteDirection, cpu.PC.programCounter);
if (portChipSelectB) $info("Wrote %08x on PORTB (IO=%01d, DIR=%01d, PC=%08x)", busDataIn, portWriteIO, portWriteDirection, cpu.PC.programCounter);
`endif
end
else if (t0ChipSelect)
begin
// Nothing
end
else
begin
`ifdef SIMULATION
$error("Ummapped Memory Write at 0x%08x", busAddress);
$finish;
`endif
end
end
busReady <= 1;
end
case (csrNumber)
12'hB00: // Machine Cycle counter L
csrDataIn <= cycleCount[31:0];
12'hB02: // Machine Instruction Counter L
csrDataIn <= instructionsExecuted[31:0];
12'hB80: // Machine Cycle counter H
csrDataIn <= cycleCount[63:32];
12'hB82: // Machine Instruction Counter H
csrDataIn <= instructionsExecuted[63:32];
default:
csrDataIn <= 0;
endcase
end
else
begin
busReady <= 0;
cycleCount <= 0;
end
`ifdef SIMULATION
if (busInstr && busValid)
begin
$info("Reading at PC %08x", busAddress);
// ROM[busAddress[15:2]]
end
`endif
ROMFF <= ROM[busAddress[15:2]]; // ROMFF is part of BRAM
RAMFF <= RAM[busAddress[14:2]]; // RAMFF is part of BRAM
if (EXCEPTION_HANDLING == 1) EXCPF <= EXCP[busAddress[9:2]-10'h1E0]; // 0x53F0DE0 offset
end
always @(*)
begin
if (romChipSelect) busDataOut <= ROMFF;
else if (ramChipSelect) busDataOut <= RAMFF;
else if (excpChipSelect && EXCEPTION_HANDLING == 1) busDataOut <= EXCPF;
else if (portChipSelectA) busDataOut <= portDirection ? portDirectionA : portDataOutA;
else if (portChipSelectB) busDataOut <= portDirection ? portDirectionB : portDataOutB;
else if (t0ChipSelect) busDataOut <= t0DataOut;
else
begin
busDataOut <= 0;
`ifdef SIMULATION
$error("Ummapped Memory Access at 0x%08x", busAddress);
$finish;
`endif
end
end
// IO
// IO ADDR = 0xF0000000 // 8 bytes, lower 4 bytes == value, upper 4 bytes = dir
assign portIO = busAddress[2:0] == 3'b000;
assign portDirection = busAddress[2:0] == 3'b100;
assign portWriteIO = portIO && busWriteEnable;
assign portWriteDirection = portDirection && busWriteEnable;
assign portChipSelectA = {busAddress[31:3], 3'b000} == 32'hF0000000;
assign portChipSelectB = {busAddress[31:3], 3'b000} == 32'hF0000008;
assign portDataIn = busDataIn;
// BUS Assign
assign busWriteEnable = cpuBusWriteEnable;
assign busAddress = cpuAddress;
assign cpuDataIn = busDataOut;
assign busDataIn = cpuDataOut;
assign busValid = cpuBusValid;
assign busInstr = cpuBusInstr;
assign cpuBusReady = busReady;
// Memory CS
assign romChipSelect = {busAddress[31:16], 16'b0} == 32'h00000000;
assign ramChipSelect = {busAddress[31:16], 16'b0} == 32'h00010000;
assign excpChipSelect = {busAddress[31:16], 16'b0} == 32'h05E00000 && EXCEPTION_HANDLING == 1;
// Timer 0
// IO ADDR = 0xF1000000
// Data => 0xF1000000
// CMD => 0xF1000001
assign t0ChipSelect = {busAddress[31:3], 3'b000} == 32'hF1000000;
assign t0Write = busAddress[2:0] == 3'h0 && busWriteEnable;
assign t0WriteCommand = busAddress[2:0] == 3'h4 && busWriteEnable;
assign t0DataIn = busDataIn;
endmodule |
module butterflyRadix4First(
input clk,
input en,
input[15:0] re_0,
input[15:0] re_1,
input[15:0] re_2,
input[15:0] re_3,
input[15:0] re_4,
input[15:0] re_5,
input[15:0] re_6,
input[15:0] re_7,
input[15:0] re_8,
input[15:0] re_9,
input[15:0] re_10,
input[15:0] re_11,
input[15:0] re_12,
input[15:0] re_13,
input[15:0] re_14,
input[15:0] re_15,
input[15:0] im_0,
input[15:0] im_1,
input[15:0] im_2,
input[15:0] im_3,
input[15:0] im_4,
input[15:0] im_5,
input[15:0] im_6,
input[15:0] im_7,
input[15:0] im_8,
input[15:0] im_9,
input[15:0] im_10,
input[15:0] im_11,
input[15:0] im_12,
input[15:0] im_13,
input[15:0] im_14,
input[15:0] im_15,
output[15:0] butterfly_re0,
output[15:0] butterfly_re1,
output[15:0] butterfly_re2,
output[15:0] butterfly_re3,
output[15:0] butterfly_re4,
output[15:0] butterfly_re5,
output[15:0] butterfly_re6,
output[15:0] butterfly_re7,
output[15:0] butterfly_re8,
output[15:0] butterfly_re9,
output[15:0] butterfly_re10,
output[15:0] butterfly_re11,
output[15:0] butterfly_re12,
output[15:0] butterfly_re13,
output[15:0] butterfly_re14,
output[15:0] butterfly_re15,
output[15:0] butterfly_im0,
output[15:0] butterfly_im1,
output[15:0] butterfly_im2,
output[15:0] butterfly_im3,
output[15:0] butterfly_im4,
output[15:0] butterfly_im5,
output[15:0] butterfly_im6,
output[15:0] butterfly_im7,
output[15:0] butterfly_im8,
output[15:0] butterfly_im9,
output[15:0] butterfly_im10,
output[15:0] butterfly_im11,
output[15:0] butterfly_im12,
output[15:0] butterfly_im13,
output[15:0] butterfly_im14,
output[15:0] butterfly_im15
);
// n=0
// X(n+1)=W(1,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+5)=W(2,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+9)=W(3,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+13)=W(4,:)*([x(n+1),x(n+5),x(n+9),x(n+13)].');
complexAddRadix_4 complexAdd1(
.clk(clk),
.x1_re(re_0), //1
.x1_im(im_0), //0
.x2_re(re_4), //3
.x2_im(im_4), //0
.x3_re(re_8), //0
.x3_im(im_8), //0
.x4_re(re_12), //1
.x4_im(im_12), //0
.re_0(butterfly_re0),
.im_0(butterfly_im0),
.re_1(butterfly_re4),
.im_1(butterfly_im4),
.re_2(butterfly_re8),
.im_2(butterfly_im8),
.re_3(butterfly_re12),
.im_3(butterfly_im12)
);
// n=1
// X(n+1)=W(1,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+5)=W(2,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+9)=W(3,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+13)=W(4,:)*([x(n+1),x(n+5),x(n+9),x(n+13)].');
complexAddRadix_4 complexAdd2(
.clk(clk),
.x1_re(re_1),
.x1_im(im_1),
.x2_re(re_5),
.x2_im(im_5),
.x3_re(re_9),
.x3_im(im_9),
.x4_re(re_13),
.x4_im(im_13),
.re_0(butterfly_re1),
.im_0(butterfly_im1),
.re_1(butterfly_re5),
.im_1(butterfly_im5),
.re_2(butterfly_re9),
.im_2(butterfly_im9),
.re_3(butterfly_re13),
.im_3(butterfly_im13)
);
// n=2
// X(n+1)=W(1,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+5)=W(2,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+9)=W(3,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+13)=W(4,:)*([x(n+1),x(n+5),x(n+9),x(n+13)].');
complexAddRadix_4 complexAdd3(
.clk(clk),
.x1_re(re_2),
.x1_im(im_2),
.x2_re(re_6),
.x2_im(im_6),
.x3_re(re_10),
.x3_im(im_10),
.x4_re(re_14),
.x4_im(im_14),
.re_0(butterfly_re2),
.im_0(butterfly_im2),
.re_1(butterfly_re6),
.im_1(butterfly_im6),
.re_2(butterfly_re10),
.im_2(butterfly_im10),
.re_3(butterfly_re14),
.im_3(butterfly_im14)
);
// n=3
// X(n+1)=W(1,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+5)=W(2,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+9)=W(3,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+13)=W(4,:)*([x(n+1),x(n+5),x(n+9),x(n+13)].');
complexAddRadix_4 complexAdd4(
.clk(clk),
.x1_re(re_3),
.x1_im(im_3),
.x2_re(re_7),
.x2_im(im_7),
.x3_re(re_11),
.x3_im(im_11),
.x4_re(re_15),
.x4_im(im_15),
.re_0(butterfly_re3),
.im_0(butterfly_im3),
.re_1(butterfly_re7),
.im_1(butterfly_im7),
.re_2(butterfly_re11),
.im_2(butterfly_im11),
.re_3(butterfly_re15),
.im_3(butterfly_im15)
);
endmodule |
module dit
#(
// Length of FFT vector.
parameter N = 16,
// Base two log of N
parameter NLOG2 = 4,
// Number of bits in vector values (double this value for a complex number).
parameter X_WDTH = 8,
// Number of bits in twiddle factor values. (must be equal to X_WDTH at the moment)
parameter TF_WDTH = 8,
// Whether to run in debug mode.
parameter DEBUGMODE = 0
)
(
// The clock signal.
input wire clk,
// Normally set to 1. Set to 0 to reset module.
input wire rst_n,
// Input value.
// Within each complex number the real part is at the low end and the complex
// at the high end.
input wire [2*X_WDTH-1:0] in_x,
// Set to 1 when new data placed in in_x.
input wire in_nd,
// Output value.
output reg [2*X_WDTH-1:0] out_x,
// Set to 1 when new data is placed in out_x.
output reg out_nd,
// Set to 1 when can't keep up with input data.
output reg overflow
);
`define MSG_DEBUG(g) if(DEBUGMODE) $display("DEBUG : %m:", g)
`define MSG_ERROR(g) $display("ERROR : %m:", g)
/******************************/
/* Define global data buffers */
/******************************/
// Input buffer.
reg [X_WDTH*2-1:0] bufferin0[N-1:0];
reg bufferin_full0_A;
reg bufferin_full0_B;
wire bufferin_full0;
assign bufferin_full0 = bufferin_full0_A + bufferin_full0_B;
reg [X_WDTH*2-1:0] bufferin1[N-1:0];
reg bufferin_full1_A;
reg bufferin_full1_B;
wire bufferin_full1;
assign bufferin_full1 = bufferin_full1_A + bufferin_full1_B;
reg bufferin_write_switch;
reg bufferin_read_switch;
wire bufferin_read_full;
wire bufferin_write_full;
assign bufferin_read_full = bufferin_read_switch?bufferin_full1:bufferin_full0;
assign bufferin_write_full = bufferin_write_switch?bufferin_full1:bufferin_full0;
// Working buffers.
reg [X_WDTH*2-1:0] bufferX[N-1:0];
reg [X_WDTH*2-1:0] bufferY[N-1:0];
// Output buffer.
reg [X_WDTH*2-1:0] bufferout[N-1:0];
// Whether the output buffer is full.
// We have two registers since they are drive by different processes.
// 'A' flips back and forth as the buffer is fulled.
// 'B' flips back and forth as the buffer is emptied.
reg bufferout_full_A;
reg bufferout_full_B;
wire bufferout_full;
assign bufferout_full = bufferout_full_A + bufferout_full_B;
// Whether the buffer contains good data. (i.e. not old)
// Data should not be read from a buffer unless the correponding
// updated value is 1.
reg [N-1:0] updatedX;
reg [N-1:0] updatedY;
/*******************************************************/
/* */
/* Define logic for receiving samples and placing in */
/* an input buffer. */
/* */
/*******************************************************/
reg [NLOG2-1:0] bufferin_addr;
initial
begin
bufferin_addr <= {NLOG2{1'b0}};
bufferin_full0_A <= 1'b0;
bufferin_full1_A <= 1'b0;
bufferin_write_switch <= 1'b0;
overflow <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferin_addr <= {NLOG2{1'b0}};
bufferin_full0_A <= 1'b0;
bufferin_full1_A <= 1'b0;
bufferin_write_switch <= 1'b0;
overflow <= 1'b0;
end
else
begin
if (in_nd)
begin
// Check for overflowed data.
if (bufferin_write_full)
overflow <= 1'b1;
if (bufferin_write_switch)
bufferin1[bufferin_addr] <= in_x;
else
bufferin0[bufferin_addr] <= in_x;
bufferin_addr <= bufferin_addr + 1;
if (&bufferin_addr)
begin
bufferin_write_switch <= ~bufferin_write_switch;
if (bufferin_write_switch)
bufferin_full1_A <= ~bufferin_full1_A;
else
bufferin_full0_A <= ~bufferin_full0_A;
end
end
end
end
/*******************************************************/
/* */
/* Define logic for emitting samples from the output */
/* buffer. */
/* */
/*******************************************************/
reg [NLOG2-1:0] bufferout_addr;
initial
begin
bufferout_addr <= {NLOG2{1'b0}};
bufferout_full_B <= 1'b0;
out_nd <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferout_addr <= {NLOG2{1'b0}};
bufferout_full_B <= 1'b0;
out_nd <= 1'b0;
end
else
begin
if (bufferout_full)
begin
out_x <= bufferout[bufferout_addr];
out_nd <= 1'b1;
bufferout_addr <= bufferout_addr + 1;
if (&bufferout_addr)
bufferout_full_B <= ~bufferout_full_B;
end
else
out_nd <= 1'b0;
end
end
/********************************************************/
/* */
/* Define FSM that passes data to the BF module. */
/* */
/********************************************************/
reg [1:0] fsm_state;
/* Define the control FSM states. */
localparam [1:0] FSM_ST_INIT = 0;
localparam [1:0] FSM_ST_IDLE = 1;
localparam [1:0] FSM_ST_CALC = 2;
localparam [1:0] FSM_ST_SEND = 3;
/*
Calculation that determine which positions we should read from and write to
for with the butterfly module.
If we have a series x_n that we want to get the DFT of, X_k we can write X_k in
terms of E_k and O_k where E_k and O_k are the DFTs of the even and odd components
of x_n respectively.
for k<N/2 : X_k = E_k + exp(-2*pi*i*k/N)*O_k
for k>=N/2 : X_k = E_{k-N/2} - exp(-2*pi*{k-N/2}/N)*O_{k-N/2}
We use this relationship to calculate the DFT of x_n in a series of stages. AFter the
final stage the output is X_k. After the second to last stage the output is an
interleaving of E_k and O_k.
At some general stage we have S interleaved series.
So if X_k is the j'th series in a stage and P_n is the n'th output in that stage:
X_k = P_{k*S+j}
E_k is from a stage with 2*S series and it is in the j'th series in the stage
O_k is from a stage with 2*S series and it is in the (S+j)'th series in stage
Let Q_n be the n'th output of the stage before P.
E_k = Q_{k*2*S+j}
O_k = Q_{k*2*S+S+j}
Also let T_n = exp(-2*pi*i*n/M)
M = N*S (total number of items in stage output)
P_{k*S+j} = Q_{2*k*S+j} + T_{k*S} * Q_{k*2*S+S+j}
P_{k*S+j+M/2} = Q_{2*k*S+j} - T_{k*S} * Q_{k*2*S+S+j}
We'll give these addresses names:
out0_addr = k*S+j
out1_addr = k*S+j+M/2
in0_addr = 2*k*S+j
in1_addr = 2*k*S+S+j
Now we assume we know out0_addr and try to get efficient ways to calculate the
other addresses.
out0_addr = k*S+j (j ranges from 0 to S-1, and S is a multiple of two)
If we look at out0_addr in binary the lowest log2(S) bits give the value of j
and the highest log2(N) bits give the value for k.
*/
// Number of series in the stage we are writing to.
reg [NLOG2-1:0] S;
// Contains a 1 for the bits that give j from out0_addr (i.e. which series).
reg [NLOG2-1:0] series_bits;
reg [NLOG2-1:0] out0_addr;
// Functions of the above 3 registers.
wire [NLOG2-1:0] in0_addr;
wire [NLOG2-1:0] in1_addr;
wire [NLOG2-1:0] out1_addr;
wire [NLOG2-2:0] tf_addr;
//To get in0_addr we leave the lowest log2(S) bits alone but we shift the log2(N)
//highest bits to the left (high is to left).
//To get in1_addr we add S to in0_addr.
// out1_addr = out0+addr + M/2
// We simply flip the highest bit from 0 to 1 which adds M/2.
assign out1_addr = {1'b1, out0_addr[NLOG2-2:0]};
// in0_addr = 2*k*S+j
// (out0_addr & series_bits) = j
// (out0_addr & ~series_bits) = k*S
// Since the bits don't overlap we can add them with an OR.
assign in0_addr = (out0_addr & series_bits) | ((out0_addr & ~series_bits)<<1);
assign in1_addr = in0_addr + S;
// (out0_addr & ~series_bits) = k*S
assign tf_addr = out0_addr & ~series_bits;
// Set to 1 when x_nd is set to 1 from the last BF calculation of the FFT.
reg finished;
// Which buffer we are reading from.
// 1 if we are reading from X.
// 0 if we are reading from Y.
reg readbuf_switch;
// We want readbuf_switch delayed by one step to send into the BF module.
// The is because readbuf_switch may have changed since the values being
// sent in were read.
reg readbuf_switch_old;
// Whether it is the first stage.
wire first_stage;
assign first_stage = (S == {1'b1,{NLOG2-1{1'b0}}});
// Whether it is the last stage.
wire last_stage;
assign last_stage = (S == 1);
// Inputs in to the BF module
wire [2*X_WDTH-1:0] in0;
wire [2*X_WDTH-1:0] in1;
assign in0 = first_stage?(bufferin_read_switch?bufferin1[in0_addr]:bufferin0[in0_addr]):(readbuf_switch?bufferX[in0_addr]:bufferY[in0_addr]);
assign in1 = first_stage?(bufferin_read_switch?bufferin1[in1_addr]:bufferin0[in1_addr]):(readbuf_switch?bufferX[in1_addr]:bufferY[in1_addr]);
// Whether the two inputs have been updated.
// Making sure we don't read before we have written.
wire updated0;
wire updated1;
assign updated0 = first_stage?1:(readbuf_switch?updatedX[in0_addr]:updatedY[in0_addr]);
assign updated1 = first_stage?1:(readbuf_switch?updatedX[in1_addr]:updatedY[in1_addr]);
// Set to 1 when we want the twiddle factor module to return some new
// twiddle factors.
reg tf_addr_nd;
// Tells the BF module that we are sending some data.
reg x_nd;
wire [2*TF_WDTH-1:0] tf;
initial
begin
fsm_state <= FSM_ST_INIT;
tf_addr_nd <= 1'b0;
x_nd <= 1'b0;
readbuf_switch <= 1'b0;
bufferin_read_switch <= 1'b0;
bufferin_full0_B <= 1'b0;
bufferin_full1_B <= 1'b0;
end
// Create the FSM machine
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
fsm_state <= FSM_ST_INIT;
tf_addr_nd <= 1'b0;
x_nd <= 1'b0;
readbuf_switch <= 1'b0;
bufferin_read_switch <= 1'b0;
bufferin_full0_B <= 1'b0;
bufferin_full1_B <= 1'b0;
end
else
begin
// Delay for readbuf_switch.
readbuf_switch_old <= readbuf_switch;
// Take note of when new data arrives.
case (fsm_state)
FSM_ST_INIT:
begin
// Starting a new FFT (we may not have received input data
// yet but we can still prepare.
`MSG_DEBUG("FSM_ST_INIT");
out0_addr <= 0;
// For the first stage we write to (the second stage) there
// are N/2 series.
series_bits <= {NLOG2{1'b1}} >> 1;
// There are N/2 series in that stage.
S <= {1'b1,{NLOG2-1{1'b0}}};
// Tell twiddle factor module to calculate the first
// twiddle factor.
tf_addr_nd <= 1'b1;
x_nd <= 1'b0;
finished <= 1'b0;
fsm_state <= FSM_ST_IDLE;
end // case: FSM_ST_INIT
FSM_ST_IDLE:
begin
// Copy the input data into a buffer.
// If no input data is there we wait here until receiving
// input data.
// During the first step in this state the twiddle
// factor module will update the twiddle factor.
// During the last step in this state the BF module is
// sent it's first inputs.
`MSG_DEBUG("FSM_ST_IDLE");
tf_addr_nd <= 1'b0;
if (bufferin_read_full)
begin
fsm_state <= FSM_ST_CALC;
x_nd <= 1'b1;
end
end // case: FSM_ST_IDLE
FSM_ST_CALC:
begin
`MSG_DEBUG("FSM_ST_CALC");
// In this state sections, series_bits, out0_addr and
// readbuf switch are updated so that we know where
// the BF module should read from and write to.
fsm_state <= FSM_ST_SEND;
tf_addr_nd <= 1'b1;
x_nd <= 1'b0;
if (&(out1_addr))
begin
// We finished the last FFT stage. Move onto the next.
`MSG_DEBUG("-------NEXT STAGE---------");
// If we're on the first stage then free up the input buffer
// for more input.
if (first_stage)
begin
`MSG_DEBUG("-Input Buffer No Longer Full-");
if (bufferin_read_switch)
bufferin_full1_B <= ~bufferin_full1_B;
else
bufferin_full0_B <= ~bufferin_full0_B;
bufferin_read_switch <= ~bufferin_read_switch;
end
// One less bit of in0_addr corresponds to which section
// it is in.
series_bits <= series_bits >> 1;
// We have half as many sections as in the last stage.
S <= S >> 1;
out0_addr <= 0;
// We switch which buffers we are reading from and
// writing to.
readbuf_switch <= ~readbuf_switch;
// Mark the buffer we were previously reading from as
// not updated. We will write to it now.
// Moved later so we drive from same process as we set.
/*
if (readbuf_switch)
updatedX <= {N{1'b0}};
else
updatedY <= {N{1'b0}};
*/
end
else
begin
`MSG_DEBUG("-------NEXT POSITION---------");
// Otherwise we still have more sections to do at
// this position.
out0_addr <= out0_addr + 1;
end
end
FSM_ST_SEND:
begin
`MSG_DEBUG("FSM_ST_SEND");
tf_addr_nd <= 1'b0;
// Wait in this state until the data we need to read is ready
// to go.
if (updated0 & updated1)
begin
x_nd <= 1'b1;
// If we have just sent data for the last BF calculation
// of the FFT calculation then go to the INIT state.
if (&(out1_addr) & (S==1))
begin
`MSG_DEBUG("--------FINISHED LAST STAGE---------");
fsm_state <= FSM_ST_INIT;
finished <= 1'b1;
end
else
fsm_state <= FSM_ST_CALC;
end
else
begin
`MSG_DEBUG("Waiting for data to be written.");
end
end
default:
begin
fsm_state <= FSM_ST_INIT;
end
endcase
end
end
/********************************************************/
/* */
/* Define logic that receives data from the BF. */
/* */
/********************************************************/
// Outputs from the BF
// The addresses where the output should be written to.
wire [NLOG2-1:0] out0_addr_z;
wire [NLOG2-1:0] out1_addr_z;
// The real and imag components of the output.
wire [2*X_WDTH-1:0] z;
// Set to 1 when the ZA is output.
// On the step after ZB is output.
wire z_nd;
// Set to 1 for the last ZA of a FFT.
wire finished_z;
// Set to 1 if data is from the last stage.
wire last_stage_z;
// Indicates which buffer the inputs to the BF module were
// read from.
// 1 if read from X.
// 0 if read from Y.
wire readbuf_switch_z;
// Delayed content of readbuf_swith_z;
reg readbuf_switch_z_last;
// Delayed content of out1_addr_z_old since we need to use
// it after it may have changed.
reg [NLOG2-1:0] out1_addr_z_old;
// The address to write the currently received BF output.
wire [NLOG2-1:0] out_addr_z;
assign out_addr_z = (z_nd)?out0_addr_z:out1_addr_z_old;
// A delayed z_nd. Tells us when to expect ZB.
reg z_nd_last;
// For delaying variables. It takes 2 steps to write the output data
// to the buffer at which point we decide whether to write the data
// to bufferout. These registers are needed for that decision.
reg finished_z_old[1:0];
reg last_stage_z_old[0:0];
reg readbuf_switch_z_old[1:0];
initial
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
bufferout_full_A <= 1'b0;
z_nd_last <= 1'b0;
end
else
begin
// Put updated reset here so we drive it from same process.
if ((fsm_state == FSM_ST_CALC) & (&(out1_addr)))
begin
if (readbuf_switch)
updatedX <= {N{1'b0}};
else
updatedY <= {N{1'b0}};
end
// Set all the delays.
readbuf_switch_z_last <= readbuf_switch_z;
finished_z_old[0] <= finished_z;
finished_z_old[1] <= finished_z_old[0];
last_stage_z_old[0] <= last_stage_z;
readbuf_switch_z_old[0] <= readbuf_switch_z;
readbuf_switch_z_old[1] <= readbuf_switch_z_old[0];
out1_addr_z_old <= out1_addr_z;
z_nd_last <= z_nd;
if (finished_z_old[1])
// We have filled the output buffer
bufferout_full_A <= ~bufferout_full_A;
// Write received data to the buffers and set updated flag.
if (z_nd | z_nd_last)
begin
if ((last_stage_z & z_nd)|(last_stage_z_old[0] & ~z_nd))
begin
bufferout[out_addr_z] <= z;
end
else
begin
if ((readbuf_switch_z & z_nd)|(readbuf_switch_z_old[0] & ~z_nd))
begin
bufferY[out_addr_z] <= z;
updatedY[out_addr_z] <= 1'b1;
end
else
begin
bufferX[out_addr_z] <= z;
updatedX[out_addr_z] <= 1'b1;
end
end
end
end
end
/* Instantiate twiddle factor unit. */
twiddlefactors
twiddlefactors_0 (
.clk (clk),
.addr (tf_addr),
.addr_nd (tf_addr_nd),
.tf_out (tf)
);
/* Instantiate the generic butterfly unit. */
butterfly #(
.M_WDTH (3 + 2*NLOG2),
.X_WDTH (X_WDTH)
)
butterfly_0 (
.clk (clk),
.rst_n (rst_n),
.m_in ({readbuf_switch_old, out0_addr, out1_addr, finished, last_stage}),
.w (tf),
.xa (in0),
.xb (in1),
.x_nd (x_nd),
.m_out ({readbuf_switch_z, out0_addr_z, out1_addr_z, finished_z, last_stage_z}),
.y (z),
.y_nd (z_nd)
);
endmodule // dit |
module complexAddRadix_4(
input clk,
input [15:0] x1_re,
input [15:0] x1_im,
input [15:0] x2_re,
input [15:0] x2_im,
input [15:0] x3_re,
input [15:0] x3_im,
input [15:0] x4_re,
input [15:0] x4_im,
output [15:0] re_0,
output [15:0] im_0,
output [15:0] re_1,
output [15:0] im_1,
output [15:0] re_2,
output [15:0] im_2,
output [15:0] re_3,
output [15:0] im_3
);
/** First Add output**/
reg[18:0] add_re_reg_0 = 19'd0;
reg[18:0] add_im_reg_0 = 19'd0;
reg[18:0] add_re_reg_1 = 19'd0;
reg[18:0] add_im_reg_1 = 19'd0;
reg[18:0] add_re_reg_2 = 19'd0;
reg[18:0] add_im_reg_2 = 19'd0;
reg[18:0] add_re_reg_3 = 19'd0;
reg[18:0] add_im_reg_3 = 19'd0;
/**end**/
/** Second Add output**/
reg[18:0] add_re_reg1_0 = 19'd0;
reg[18:0] add_im_reg1_0 = 19'd0;
reg[18:0] add_re_reg1_1 = 19'd0;
reg[18:0] add_im_reg1_1 = 19'd0;
reg[18:0] add_re_reg1_2 = 19'd0;
reg[18:0] add_im_reg1_2 = 19'd0;
reg[18:0] add_re_reg1_3 = 19'd0;
reg[18:0] add_im_reg1_3 = 19'd0;
/**end**/
/** Third Add output **/
reg[18:0] add_re_reg2_0 = 19'd0;
reg[18:0] add_im_reg2_0 = 19'd0;
reg[18:0] add_re_reg2_1 = 19'd0;
reg[18:0] add_im_reg2_1 = 19'd0;
reg[18:0] add_re_reg2_2 = 19'd0;
reg[18:0] add_im_reg2_2 = 19'd0;
reg[18:0] add_re_reg2_3 = 19'd0;
reg[18:0] add_im_reg2_3 = 19'd0;
/**end**/
/** data standardize**/
reg[15:0] x3_re_reg = 19'd0;
reg[15:0] x3_im_reg = 19'd0;
reg[15:0] x4_re_reg = 19'd0;
reg[15:0] x4_im_reg = 19'd0;
reg[15:0] x4_re_reg1 = 19'd0;
reg[15:0] x4_im_reg1 = 19'd0;
/**end**/
always @(posedge clk)// delay
begin
x3_re_reg <= x3_re;
x3_im_reg <= x3_im;
x4_re_reg1 <= x4_re;
x4_im_reg1 <= x4_im;
end
always @(posedge clk)
begin
x4_re_reg <= x4_re_reg1;
x4_im_reg <= x4_im_reg1;
end
always @(posedge clk)// first add
begin
add_re_reg_0 <= {{3{x1_re[15]}},x1_re} + {{3{x2_re[15]}},x2_re};
add_im_reg_0 <= {{3{x1_im[15]}},x1_im} + {{3{x2_im[15]}},x2_im};
add_re_reg_1 <= {{3{x1_re[15]}},x1_re} + {{3{x2_im[15]}},x2_im};
add_im_reg_1 <= {{3{x1_im[15]}},x1_im} - {{3{x2_re[15]}},x2_re};
add_re_reg_2 <= {{3{x1_re[15]}},x1_re} - {{3{x2_re[15]}},x2_re};
add_im_reg_2 <= {{3{x1_im[15]}},x1_im} - {{3{x2_im[15]}},x2_im};
add_re_reg_3 <= {{3{x1_re[15]}},x1_re} - {{3{x2_im[15]}},x2_im};
add_im_reg_3 <= {{3{x1_im[15]}},x1_im} + {{3{x2_re[15]}},x2_re};
end
always @(posedge clk)//second add
begin
add_re_reg1_0 <= add_re_reg_0 + {{3{x3_re_reg[15]}},x3_re_reg};
add_im_reg1_0 <= add_im_reg_0 + {{3{x3_im_reg[15]}},x3_im_reg};
add_re_reg1_1 <= add_re_reg_1 - {{3{x3_re_reg[15]}},x3_re_reg};
add_im_reg1_1 <= add_im_reg_1 - {{3{x3_im_reg[15]}},x3_im_reg};
add_re_reg1_2 <= add_re_reg_2 + {{3{x3_re_reg[15]}},x3_re_reg};
add_im_reg1_2 <= add_im_reg_2 + {{3{x3_im_reg[15]}},x3_im_reg};
add_re_reg1_3 <= add_re_reg_3 - {{3{x3_re_reg[15]}},x3_re_reg};
add_im_reg1_3 <= add_im_reg_3 - {{3{x3_im_reg[15]}},x3_im_reg};
end
always @(posedge clk)//third add
begin
add_re_reg2_0 <= add_re_reg1_0 + {{3{x4_re_reg[15]}},x4_re_reg};
add_im_reg2_0 <= add_im_reg1_0 + {{3{x4_im_reg[15]}},x4_im_reg};
add_re_reg2_1 <= add_re_reg1_1 - {{3{x4_im_reg[15]}},x4_im_reg};
add_im_reg2_1 <= add_im_reg1_1 + {{3{x4_re_reg[15]}},x4_re_reg};
add_re_reg2_2 <= add_re_reg1_2 - {{3{x4_re_reg[15]}},x4_re_reg};
add_im_reg2_2 <= add_im_reg1_2 - {{3{x4_im_reg[15]}},x4_im_reg};
add_re_reg2_3 <= add_re_reg1_3 + {{3{x4_im_reg[15]}},x4_im_reg};
add_im_reg2_3 <= add_im_reg1_3 - {{3{x4_re_reg[15]}},x4_re_reg};
end
assign re_0 = add_re_reg2_0[15:0];
assign im_0 = add_im_reg2_0[15:0];
assign re_1 = add_re_reg2_1[15:0];
assign im_1 = add_im_reg2_1[15:0];
assign re_2 = add_re_reg2_2[15:0];
assign im_2 = add_im_reg2_2[15:0];
assign re_3 = add_re_reg2_3[15:0];
assign im_3 = add_im_reg2_3[15:0];
endmodule |
module butterflyRadix4Second(
input clk,
input[15:0] re_0,
input[15:0] re_1,
input[15:0] re_2,
input[15:0] re_3,
input[15:0] re_4,
input[15:0] re_5,
input[15:0] re_6,
input[15:0] re_7,
input[15:0] re_8,
input[15:0] re_9,
input[15:0] re_10,
input[15:0] re_11,
input[15:0] re_12,
input[15:0] re_13,
input[15:0] re_14,
input[15:0] re_15,
input[15:0] im_0,
input[15:0] im_1,
input[15:0] im_2,
input[15:0] im_3,
input[15:0] im_4,
input[15:0] im_5,
input[15:0] im_6,
input[15:0] im_7,
input[15:0] im_8,
input[15:0] im_9,
input[15:0] im_10,
input[15:0] im_11,
input[15:0] im_12,
input[15:0] im_13,
input[15:0] im_14,
input[15:0] im_15,
output[15:0] butterfly_re0,
output[15:0] butterfly_re1,
output[15:0] butterfly_re2,
output[15:0] butterfly_re3,
output[15:0] butterfly_re4,
output[15:0] butterfly_re5,
output[15:0] butterfly_re6,
output[15:0] butterfly_re7,
output[15:0] butterfly_re8,
output[15:0] butterfly_re9,
output[15:0] butterfly_re10,
output[15:0] butterfly_re11,
output[15:0] butterfly_re12,
output[15:0] butterfly_re13,
output[15:0] butterfly_re14,
output[15:0] butterfly_re15,
output[15:0] butterfly_im0,
output[15:0] butterfly_im1,
output[15:0] butterfly_im2,
output[15:0] butterfly_im3,
output[15:0] butterfly_im4,
output[15:0] butterfly_im5,
output[15:0] butterfly_im6,
output[15:0] butterfly_im7,
output[15:0] butterfly_im8,
output[15:0] butterfly_im9,
output[15:0] butterfly_im10,
output[15:0] butterfly_im11,
output[15:0] butterfly_im12,
output[15:0] butterfly_im13,
output[15:0] butterfly_im14,
output[15:0] butterfly_im15
);
//**************** Second Butterfly *****************
// n=0:3
// X2(n+1) = W(1,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+5) = W(2,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+9) = W(3,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+13) = W(4,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
//******* followwing parameter come from exp(-1i*2*pi/N*n) above********//
//*********** cos *******************//
parameter cos0 = 17'b0_1000_0000_0000_0000; //(1*2^15)-1 origin:1 after:32767
parameter cos1 = 17'b0_1000_0000_0000_0000; //1
parameter cos2 = 17'b0_1000_0000_0000_0000; //1
parameter cos3 = 17'b0_0111_0110_0100_0001; //0.9239 -> 30273
parameter cos4 = 17'b0_0101_1010_1000_0010; //0.7071 -> 23170
parameter cos5 = 17'b0_0011_0000_1111_1100; //0.3827 -> 12540
parameter cos6 = 17'b0_0101_1010_1000_0010; //0.7071
parameter cos7 = 17'b0_0000000000000000; //0
parameter cos8 = 17'b1_1010_0101_0111_1110; //-0.7071-> -23170
parameter cos9 = 17'b0_0011_0000_1111_1100; //0.3827
parameter cos10 = 17'b1_1010_0101_0111_1110; //-0.7071
parameter cos11 = 17'b1_1000_1001_1011_1111; //-0.9239-> -30273
//*********** sin *******************//
parameter sin0 = 17'b00000000000000000; //0
parameter sin1 = 17'b00000000000000000; //0
parameter sin2 = 17'b00000000000000000; //0
parameter sin3 = 17'b1_1100_1111_0000_0100; // -0.3827 complement
parameter sin4 = 17'b1_1010_0101_0111_1110; //-0.29291 -0.7071
parameter sin5 = 17'b1_1000_1001_1011_1111; //-0.07614 -0.9239
parameter sin6 = 17'b1_1010_0101_0111_1110; //-0.7071
parameter sin7 = 17'b1_1111_1111_1111_1111; //-1
parameter sin8 = 17'b1_1010_0101_0111_1110; //-0.7071
parameter sin9 = 17'b1_1000_1001_1011_1111; //-0.9239
parameter sin10 = 17'b1_1010_0101_0111_1110; //-0.7071
parameter sin11 = 17'b0_0011_0000_1111_1100; //0.3827
// n=0:3
// X2(n+1) = W(1,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+5) = W(2,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+9) = W(3,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+13) = W(4,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// n=0
// X2(1) = W(1,:)*[X1(1),X1(2)*exp(-1i*2*pi/N*n),X1(3)*exp(-1i*2*pi/N*2*n),X1(4)*exp(-1i*2*pi/N*3*n)].';
// X2(5) = W(2,:)*[X1(1),X1(2)*exp(-1i*2*pi/N*n),X1(3)*exp(-1i*2*pi/N*2*n),X1(4)*exp(-1i*2*pi/N*3*n)].';
// X2(9) = W(3,:)*[X1(1),X1(2)*exp(-1i*2*pi/N*n),X1(3)*exp(-1i*2*pi/N*2*n),X1(4)*exp(-1i*2*pi/N*3*n)].';
// X2(13) = W(4,:)*[X1(1),X1(2)*exp(-1i*2*pi/N*n),X1(3)*exp(-1i*2*pi/N*2*n),X1(4)*exp(-1i*2*pi/N*3*n)].';
butterflyUnitRadix4 butterflyRadix4Unit1(
.clk(clk),
.cos0(cos0), //ar
.sin0(sin0), //br
.cos1(cos1),
.sin1(sin1),
.cos2(cos2),
.sin2(sin2),
.x1_re(re_0),
.x1_im(im_0),
.x2_re(re_1),
.x2_im(im_1),
.x3_re(re_2),
.x3_im(im_2),
.x4_re(re_3),
.x4_im(im_3),
.p1_re(butterfly_re0),
.p1_im(butterfly_im0),
.p2_re(butterfly_re4),
.p2_im(butterfly_im4),
.p3_re(butterfly_re8),
.p3_im(butterfly_im8),
.p4_re(butterfly_re12),
.p4_im(butterfly_im12)
);
// n=1
// X2(2) = W(1,:)*[X1(5),X1(6)*exp(-1i*2*pi/N*n),X1(7)*exp(-1i*2*pi/N*2*n),X1(8)*exp(-1i*2*pi/N*3*n)].';
// X2(6) = W(2,:)*[X1(5),X1(6)*exp(-1i*2*pi/N*n),X1(7)*exp(-1i*2*pi/N*2*n),X1(8)*exp(-1i*2*pi/N*3*n)].';
// X2(10) = W(3,:)*[X1(5),X1(6)*exp(-1i*2*pi/N*n),X1(7)*exp(-1i*2*pi/N*2*n),X1(8)*exp(-1i*2*pi/N*3*n)].';
// X2(14) = W(4,:)*[X1(5),X1(6)*exp(-1i*2*pi/N*n),X1(7)*exp(-1i*2*pi/N*2*n),X1(8)*exp(-1i*2*pi/N*3*n)].';
butterflyUnitRadix4 butterflyRadix4Unit2(
.clk(clk),
.cos0(cos3),
.sin0(sin3),
.cos1(cos4),
.sin1(sin4),
.cos2(cos5),
.sin2(sin5),
.x1_re(re_4),
.x1_im(im_4),
.x2_re(re_5),
.x2_im(im_5),
.x3_re(re_6),
.x3_im(im_6),
.x4_re(re_7),
.x4_im(im_7),
.p1_re(butterfly_re1),
.p1_im(butterfly_im1),
.p2_re(butterfly_re5),
.p2_im(butterfly_im5),
.p3_re(butterfly_re9),
.p3_im(butterfly_im9),
.p4_re(butterfly_re13),
.p4_im(butterfly_im13)
);
// n=3
// X2(3) = W(1,:)*[X1(9),X1(10)*exp(-1i*2*pi/N*n),X1(11)*exp(-1i*2*pi/N*2*n),X1(12)*exp(-1i*2*pi/N*3*n)].';
// X2(7) = W(2,:)*[X1(9),X1(10)*exp(-1i*2*pi/N*n),X1(11)*exp(-1i*2*pi/N*2*n),X1(12)*exp(-1i*2*pi/N*3*n)].';
// X2(11) = W(3,:)*[X1(9),X1(10)*exp(-1i*2*pi/N*n),X1(11)*exp(-1i*2*pi/N*2*n),X1(12)*exp(-1i*2*pi/N*3*n)].';
// X2(15) = W(4,:)*[X1(9),X1(10)*exp(-1i*2*pi/N*n),X1(11)*exp(-1i*2*pi/N*2*n),X1(12)*exp(-1i*2*pi/N*3*n)].';
butterflyUnitRadix4 butterflyRadix4Unit3(
.clk(clk),
.cos0(cos6),
.sin0(sin6),
.cos1(cos7),
.sin1(sin7),
.cos2(cos8),
.sin2(sin8),
.x1_re(re_8),
.x1_im(im_8),
.x2_re(re_9),
.x2_im(im_9),
.x3_re(re_10),
.x3_im(im_10),
.x4_re(re_11),
.x4_im(im_11),
.p1_re(butterfly_re2),
.p1_im(butterfly_im2),
.p2_re(butterfly_re6),
.p2_im(butterfly_im6),
.p3_re(butterfly_re10),
.p3_im(butterfly_im10),
.p4_re(butterfly_re14),
.p4_im(butterfly_im14)
);
// n=4
// X2(4) = W(1,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(8) = W(2,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(12) = W(3,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(16) = W(4,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(16) = W(4,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(16) = W(4,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
// X2(16) = W(4,:)*[X1(13),X1(14)*exp(-1i*2*pi/N*n),X1(15)*exp(-1i*2*pi/N*2*n),X1(16)*exp(-1i*2*pi/N*3*n)].';
butterflyUnitRadix4 butterflyRadix4Unit4(
.clk(clk),
.cos0(cos9),
.sin0(sin9),
.cos1(cos10),
.sin1(sin10),
.cos2(cos11),
.sin2(sin11),
.x1_re(re_12),
.x1_im(im_12),
.x2_re(re_13),
.x2_im(im_13),
.x3_re(re_14),
.x3_im(im_14),
.x4_re(re_15),
.x4_im(im_15),
.p1_re(butterfly_re3),
.p1_im(butterfly_im3),
.p2_re(butterfly_re7),
.p2_im(butterfly_im7),
.p3_re(butterfly_re11),
.p3_im(butterfly_im11),
.p4_re(butterfly_re15),
.p4_im(butterfly_im15)
);
endmodule |
module butterfly
#(
// The width of m_in.
parameter M_WDTH = 0,
// The width of the input, output and twiddle factors.
parameter X_WDTH = 0
)
(
input wire clk,
input wire rst_n,
// m_in contains data that passes through this block with no change.
// It is delayed for 3 counts like x_nd->y_nd.
input wire [M_WDTH-1:0] m_in,
// The twiddle factor.
input wire signed [2*X_WDTH-1:0] w,
// XA
input wire signed [2*X_WDTH-1:0] xa,
// XB
input wire signed [2*X_WDTH-1:0] xb,
// Set to 1 when new data is present on inputs.
// Cannot be set to 1 for two consecutive steps.
input wire x_nd,
// delayed version of m_in.
output reg [M_WDTH-1:0] m_out,
// YA = XA + W*XB
// YB = XA - W*XB
// When y_nd=1 y_re and y_im are outputing YA.
// The step after they are outputting YB.
output wire signed [2*X_WDTH-1:0] y,
output reg y_nd
);
// Set wire to the real and imag parts for convenience.
wire signed [X_WDTH-1:0] w_re;
wire signed [X_WDTH-1:0] w_im;
assign w_re = w[2*X_WDTH-1:X_WDTH];
assign w_im = w[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xa_re;
wire signed [X_WDTH-1:0] xa_im;
assign xa_re = xa[2*X_WDTH-1:X_WDTH];
assign xa_im = xa[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xb_re;
wire signed [X_WDTH-1:0] xb_im;
assign xb_re = xb[2*X_WDTH-1:X_WDTH];
assign xb_im = xb[X_WDTH-1:0];
reg signed [X_WDTH-1: 0] y_re;
reg signed [X_WDTH-1: 0] y_im;
assign y = {y_re, y_im};
// Delayed m_in.
reg signed [M_WDTH-1:0] m[1:0];
// Delayed XA
reg signed [X_WDTH-1:0] za_re[1:0];
reg signed [X_WDTH-1:0] za_im[1:0];
// Delayed XB
reg signed [X_WDTH-1:0] zb_re;
reg signed [X_WDTH-1:0] zb_im;
// Delayed W
reg signed [X_WDTH-1:0] ww_re;
reg signed [X_WDTH-1:0] ww_im;
// Delayed x_nd
reg signed x_nd_old[2:0];
// Storage for output of multipliers
reg signed [2*X_WDTH-1:0] zbw_m1;
reg signed [2*X_WDTH-1:0] zbw_m2;
// W * XB
reg signed [X_WDTH-1:0] zbw_re;
wire signed [X_WDTH-1:0] zbw_im;
assign zbw_im = (zbw_m1 >>> (X_WDTH-2)) + (zbw_m2 >>> (X_WDTH-2));
reg signed [X_WDTH-1:0] zbw_im_old;
// Wire of longer length for adding or substracting W*XB to XA.
// If we don't create longer wires for them then we can lose the
// high bit. The contents of these wires are downshifted into a
// normal size for use.
wire signed [X_WDTH:0] z1_re_big;
wire signed [X_WDTH:0] z1_im_big;
assign z1_re_big = za_re[0] + zbw_re;
assign z1_im_big = za_im[0] + zbw_im;
wire signed [X_WDTH:0] z2_re_big;
wire signed [X_WDTH:0] z2_im_big;
assign z2_re_big = za_re[1] - zbw_re;
assign z2_im_big = za_im[1] - zbw_im_old;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
y_nd <= 1'b0;
end
else
begin
// Set delay for x_nd_old and m.
x_nd_old[0] <= x_nd;
x_nd_old[1] <= x_nd_old[0];
x_nd_old[2] <= x_nd_old[1];
m[0] <= m_in;
m[1] <= m[0];
m_out <= m[1];
// STAGE 1
if (x_nd)
begin
za_re[0] <= xa_re;
za_im[0] <= xa_im;
ww_re <= w_re;
ww_im <= w_im;
zb_re <= xb_re;
zb_im <= xb_im;
// We perform two multiplications for calculate the real part
// of W*XB.
zbw_m1 <= xb_re*w_re;
zbw_m2 <= xb_im*w_im;
if (x_nd_old[0])
$display("ERROR: BF got new data two steps in a row.");
end
if (x_nd_old[0])
// STAGE 2
begin
// Now start the multiplications for the imag part of W*WB.
zbw_m1 <= zb_re*ww_im;
zbw_m2 <= zb_im*ww_re;
// Downshift the multiplied results into normal width and
// substract them.
// Overflow is not possible upon substraction since we
// know that W and XB both have magnitude less than 1
// so their multiple must also.
zbw_re <= (zbw_m1 >>> (X_WDTH-2)) - (zbw_m2 >>> (X_WDTH-2));
end
// STAGE 3
if (x_nd_old[1])
begin
// We only need to shift the required delayed data
// with XA every two steps since new input cannot
// arrive more frequently than that.
// XA is needed by a wire calculating z2_re_big and ze_im_big
// next step.
za_re[1] <= za_re[0];
za_im[1] <= za_im[0];
// Output YA.
y_nd <= 1'b1;
y_re <= z1_re_big >>> 1;
y_im <= z1_im_big >>> 1;
zbw_im_old <= zbw_im;
end
// STAGE 4
if (x_nd_old[2])
begin
// Output YB.
y_nd <= 1'b0;
y_re <= z2_re_big >>> 1;
y_im <= z2_im_big >>> 1;
end
end
end
endmodule |
module Deserializer(
clk,
reset,
datain,
// first 16 is real last16 is imaginary
dataout0,
dataout1,
dataout2,
dataout3,
dataout4,
dataout5,
dataout6,
dataout7,
dataout8,
dataout9,
dataout10,
dataout11,
dataout12,
dataout13,
dataout14,
dataout15,
dataout16,
dataout17,
dataout18,
dataout19,
dataout20,
dataout21,
dataout22,
dataout23,
dataout24,
dataout25,
dataout26,
dataout27,
dataout28,
dataout29,
dataout30,
dataout31,
finish
);
input clk;
input [15:0] datain;
input reset;
output [15:0] dataout0;
output [15:0] dataout1;
output [15:0] dataout2;
output [15:0] dataout3;
output [15:0] dataout4;
output [15:0] dataout5;
output [15:0] dataout6;
output [15:0] dataout7;
output [15:0] dataout8;
output [15:0] dataout9;
output [15:0] dataout10;
output [15:0] dataout11;
output [15:0] dataout12;
output [15:0] dataout13;
output [15:0] dataout14;
output [15:0] dataout15;
output [15:0] dataout16;
output [15:0] dataout17;
output [15:0] dataout18;
output [15:0] dataout19;
output [15:0] dataout20;
output [15:0] dataout21;
output [15:0] dataout22;
output [15:0] dataout23;
output [15:0] dataout24;
output [15:0] dataout25;
output [15:0] dataout26;
output [15:0] dataout27;
output [15:0] dataout28;
output [15:0] dataout29;
output [15:0] dataout30;
output [15:0] dataout31;
output finish;
reg signed [15:0] dataout0,dataout1,dataout2,dataout3,dataout4,dataout5,dataout6,dataout7,dataout8,dataout9,dataout10,dataout11,dataout12,dataout13,dataout14,dataout15,dataout16,dataout17,dataout18,dataout19,dataout20,dataout21,dataout22,dataout23,dataout24,dataout25,dataout26,dataout27,dataout28,dataout29,dataout30,dataout31;
// reg signed [15:0] finish;
reg signed [3:0] counter;
reg finish;
reg dataValid;
always @ (posedge clk or negedge reset)
if(!reset)
begin
dataout0 <= datain;
dataout1 <= dataout0;
dataout2 <= dataout1;
dataout3 <= dataout2;
dataout4 <= dataout3;
dataout5 <= dataout4;
dataout6 <= dataout5;
dataout7 <= dataout6;
dataout8 <= dataout7;
dataout9 <= dataout8;
dataout10 <= dataout9;
dataout11 <= dataout10;
dataout12 <= dataout11;
dataout13 <= dataout12;
dataout14 <= dataout13;
dataout15 <= dataout14;
dataout16 <= dataout15;
dataout17 <= dataout16;
dataout18 <= dataout17;
dataout19 <= dataout18;
dataout20 <= dataout19;
dataout21 <= dataout20;
dataout22 <= dataout21;
dataout23 <= dataout22;
dataout24 <= dataout23;
dataout25 <= dataout24;
dataout26 <= dataout25;
dataout27 <= dataout26;
dataout28 <= dataout27;
dataout29 <= dataout28;
dataout30 <= dataout29;
dataout31 <= dataout30;
if (datain != 16'd0)
begin
dataValid <= 1'b1;
end
if(dataValid == 1'b1)
begin
if(counter == 4'd15)
begin
counter <= 4'd0;
finish <= 1'b1;
end
else
counter <= counter+4'b1 ;
end
end
else
begin
dataout0 <= 16'd0;
dataout1 <= 16'd0;
dataout2 <= 16'd0;
dataout3 <= 16'd0;
dataout4 <= 16'd0;
dataout5 <= 16'd0;
dataout6 <= 16'd0;
dataout7 <= 16'd0;
dataout8 <= 16'd0;
dataout9 <= 16'd0;
dataout10 <= 16'd0;
dataout11 <= 16'd0;
dataout12 <= 16'd0;
dataout13 <= 16'd0;
dataout14 <= 16'd0;
dataout15 <= 16'd0;
dataout16 <= 16'd0;
dataout17 <= 16'd0;
dataout18 <= 16'd0;
dataout19 <= 16'd0;
dataout20 <= 16'd0;
dataout21 <= 16'd0;
dataout22 <= 16'd0;
dataout23 <= 16'd0;
dataout24 <= 16'd0;
dataout25 <= 16'd0;
dataout26 <= 16'd0;
dataout27 <= 16'd0;
dataout28 <= 16'd0;
dataout29 <= 16'd0;
dataout30 <= 16'd0;
dataout31 <= 16'd0;
counter <= 4'b0 ;
finish <= 1'b0;
dataValid <= 1'b0;
end
endmodule |
module FFT_top(
input clk,
input reset,
input [4:0] address,
output[15:0] out_re0,
output[15:0] out_re1,
output[15:0] out_re2,
output[15:0] out_re3,
output[15:0] out_re4,
output[15:0] out_re5,
output[15:0] out_re6,
output[15:0] out_re7,
output[15:0] out_re8,
output[15:0] out_re9,
output[15:0] out_re10,
output[15:0] out_re11,
output[15:0] out_re12,
output[15:0] out_re13,
output[15:0] out_re14,
output[15:0] out_re15,
output[15:0] out_im0,
output[15:0] out_im1,
output[15:0] out_im2,
output[15:0] out_im3,
output[15:0] out_im4,
output[15:0] out_im5,
output[15:0] out_im6,
output[15:0] out_im7,
output[15:0] out_im8,
output[15:0] out_im9,
output[15:0] out_im10,
output[15:0] out_im11,
output[15:0] out_im12,
output[15:0] out_im13,
output[15:0] out_im14,
output[15:0] out_im15
);
wire [15:0] dataStream;
wire [15:0] inputRe0,inputRe1,inputRe2,inputRe3,inputRe4,inputRe5,inputRe6,inputRe7,inputRe8,inputRe9,inputRe10,inputRe11,inputRe12,inputRe13,inputRe14,inputRe15,inputIm0,inputIm1,inputIm2,inputIm3,inputIm4,inputIm5,inputIm6,inputIm7,inputIm8,inputIm9,inputIm10,inputIm11,inputIm12,inputIm13,inputIm14,inputIm15;
wire[15:0] butterfly_re[15:0];
wire[15:0] butterfly_im[15:0];
//****** read data *****************
inputRom rom1(
.clka(clk),
.addra(address),
.douta(dataStream)
);
//**********************************
//****** Deserializer ***************
Deserializer dese1(
.clk(clk),
.reset(reset),
.datain(dataStream),
.dataout0(inputRe0),
.dataout1(inputRe1),
.dataout2(inputRe2),
.dataout3(inputRe3),
.dataout4(inputRe4),
.dataout5(inputRe5),
.dataout6(inputRe6),
.dataout7(inputRe7),
.dataout8(inputRe8),
.dataout9(inputRe9),
.dataout10(inputRe10),
.dataout11(inputRe11),
.dataout12(inputRe12),
.dataout13(inputRe13),
.dataout14(inputRe14),
.dataout15(inputRe15),
.dataout16(inputIm0),
.dataout17(inputIm1),
.dataout18(inputIm2),
.dataout19(inputIm3),
.dataout20(inputIm4),
.dataout21(inputIm5),
.dataout22(inputIm6),
.dataout23(inputIm7),
.dataout24(inputIm8),
.dataout25(inputIm9),
.dataout26(inputIm10),
.dataout27(inputIm11),
.dataout28(inputIm12),
.dataout29(inputIm13),
.dataout30(inputIm14),
.dataout31(inputIm15),
.finish(out)
);
//*************** butterfuly 1 **********************
// n=0:3
// X(n+1)=W(1,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+5)=W(2,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+9)=W(3,:)* ([x(n+1),x(n+5),x(n+9),x(n+13)].');
// X(n+13)=W(4,:)*([x(n+1),x(n+5),x(n+9),x(n+13)].');
//W = [ 1 1 1 1
// 1 -j -1 j
// 1 -1 1 -1
// 1 j -1 -j ]
butterflyRadix4First butterfly1st(
.clk(clk),
.en(out),
.re_0(inputRe0),
.re_1(inputRe1),
.re_2(inputRe2),
.re_3(inputRe3),
.re_4(inputRe4),
.re_5(inputRe5),
.re_6(inputRe6),
.re_7(inputRe7),
.re_8(inputRe8),
.re_9(inputRe9),
.re_10(inputRe10),
.re_11(inputRe11),
.re_12(inputRe12),
.re_13(inputRe13),
.re_14(inputRe14),
.re_15(inputRe15),
.im_0(inputIm0),
.im_1(inputIm1),
.im_2(inputIm2),
.im_3(inputIm3),
.im_4(inputIm4),
.im_5(inputIm5),
.im_6(inputIm6),
.im_7(inputIm7),
.im_8(inputIm8),
.im_9(inputIm9),
.im_10(inputIm10),
.im_11(inputIm11),
.im_12(inputIm12),
.im_13(inputIm13),
.im_14(inputIm14),
.im_15(inputIm15),
.butterfly_re0(butterfly_re[0]),
.butterfly_re1(butterfly_re[1]),
.butterfly_re2(butterfly_re[2]),
.butterfly_re3(butterfly_re[3]),
.butterfly_re4(butterfly_re[4]),
.butterfly_re5(butterfly_re[5]),
.butterfly_re6(butterfly_re[6]),
.butterfly_re7(butterfly_re[7]),
.butterfly_re8(butterfly_re[8]),
.butterfly_re9(butterfly_re[9]),
.butterfly_re10(butterfly_re[10]),
.butterfly_re11(butterfly_re[11]),
.butterfly_re12(butterfly_re[12]),
.butterfly_re13(butterfly_re[13]),
.butterfly_re14(butterfly_re[14]),
.butterfly_re15(butterfly_re[15]),
.butterfly_im0(butterfly_im[0]),
.butterfly_im1(butterfly_im[1]),
.butterfly_im2(butterfly_im[2]),
.butterfly_im3(butterfly_im[3]),
.butterfly_im4(butterfly_im[4]),
.butterfly_im5(butterfly_im[5]),
.butterfly_im6(butterfly_im[6]),
.butterfly_im7(butterfly_im[7]),
.butterfly_im8(butterfly_im[8]),
.butterfly_im9(butterfly_im[9]),
.butterfly_im10(butterfly_im[10]),
.butterfly_im11(butterfly_im[11]),
.butterfly_im12(butterfly_im[12]),
.butterfly_im13(butterfly_im[13]),
.butterfly_im14(butterfly_im[14]),
.butterfly_im15(butterfly_im[15])
);
//***************************************************
//**************** Second Butterfly *****************
// n=0:3
// X(n+1) = W(1,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+5) = W(2,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+9) = W(3,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+13) = W(4,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
butterflyRadix4Second butterfly2nd(
.clk(clk),
.re_0(butterfly_re[0]),
.re_1(butterfly_re[1]),
.re_2(butterfly_re[2]),
.re_3(butterfly_re[3]),
.re_4(butterfly_re[4]),
.re_5(butterfly_re[5]),
.re_6(butterfly_re[6]),
.re_7(butterfly_re[7]),
.re_8(butterfly_re[8]),
.re_9(butterfly_re[9]),
.re_10(butterfly_re[10]),
.re_11(butterfly_re[11]),
.re_12(butterfly_re[12]),
.re_13(butterfly_re[13]),
.re_14(butterfly_re[14]),
.re_15(butterfly_re[15]),
.im_0(butterfly_im[0]),
.im_1(butterfly_im[1]),
.im_2(butterfly_im[2]),
.im_3(butterfly_im[3]),
.im_4(butterfly_im[4]),
.im_5(butterfly_im[5]),
.im_6(butterfly_im[6]),
.im_7(butterfly_im[7]),
.im_8(butterfly_im[8]),
.im_9(butterfly_im[9]),
.im_10(butterfly_im[10]),
.im_11(butterfly_im[11]),
.im_12(butterfly_im[12]),
.im_13(butterfly_im[13]),
.im_14(butterfly_im[14]),
.im_15(butterfly_im[15]),
.butterfly_re0(out_re0),
.butterfly_re1(out_re1),
.butterfly_re2(out_re2),
.butterfly_re3(out_re3),
.butterfly_re4(out_re4),
.butterfly_re5(out_re5),
.butterfly_re6(out_re6),
.butterfly_re7(out_re7),
.butterfly_re8(out_re8),
.butterfly_re9(out_re9),
.butterfly_re10(out_re10),
.butterfly_re11(out_re11),
.butterfly_re12(out_re12),
.butterfly_re13(out_re13),
.butterfly_re14(out_re14),
.butterfly_re15(out_re15),
.butterfly_im0(out_im0),
.butterfly_im1(out_im1),
.butterfly_im2(out_im2),
.butterfly_im3(out_im3),
.butterfly_im4(out_im4),
.butterfly_im5(out_im5),
.butterfly_im6(out_im6),
.butterfly_im7(out_im7),
.butterfly_im8(out_im8),
.butterfly_im9(out_im9),
.butterfly_im10(out_im10),
.butterfly_im11(out_im11),
.butterfly_im12(out_im12),
.butterfly_im13(out_im13),
.butterfly_im14(out_im14),
.butterfly_im15(out_im15)
);
//***************************************************
//***************************************************
endmodule |
module FFT_top_tb;
// Inputs
reg clk;
reg reset;
reg [4:0] address;
reg [15:0] data_tmp11,data_tmp21,data_tmp31,data_tmp41,data_tmp51,data_tmp61,data_tmp71,data_tmp81,data_tmp91,data_tmp101,data_tmp111,data_tmp121,data_tmp131,data_tmp141,data_tmp151,data_tmp161;
reg [15:0] data_tmp12,data_tmp22,data_tmp32,data_tmp42,data_tmp52,data_tmp62,data_tmp72,data_tmp82,data_tmp92,data_tmp102,data_tmp112,data_tmp122,data_tmp132,data_tmp142,data_tmp152,data_tmp162;
// Outputs
wire [15:0] out_r1,out_r2,out_r3,out_r4,out_r5,out_r6,out_r7,out_r8,out_r9,out_r10,out_r11,out_r12,out_r13,out_r14,out_r15,out_r16;
wire [15:0] out_i1,out_i2,out_i3,out_i4,out_i5,out_i6,out_i7,out_i8,out_i9,out_i10,out_i11,out_i12,out_i13,out_i14,out_i15,out_i16;
// Instantiate the Unit Under Test (UUT)
FFT_top uut (
.clk(clk),
.reset(reset),
.address(address),
.out_re0(out_r1),
.out_re1(out_r2),
.out_re2(out_r3),
.out_re3(out_r4),
.out_re4(out_r5),
.out_re5(out_r6),
.out_re6(out_r7),
.out_re7(out_r8),
.out_re8(out_r9),
.out_re9(out_r10),
.out_re10(out_r11),
.out_re11(out_r12),
.out_re12(out_r13),
.out_re13(out_r14),
.out_re14(out_r15),
.out_re15(out_r16),
.out_im0(out_i1),
.out_im1(out_i2),
.out_im2(out_i3),
.out_im3(out_i4),
.out_im4(out_i5),
.out_im5(out_i6),
.out_im6(out_i7),
.out_im7(out_i8),
.out_im8(out_i9),
.out_im9(out_i10),
.out_im10(out_i11),
.out_im11(out_i12),
.out_im12(out_i13),
.out_im13(out_i14),
.out_im14(out_i15),
.out_im15(out_i16)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1'b1;
address = 5'd0;
// Wait 100 ns for global reset to finish
#25;
reset = 1'b0;
// Add stimulus here
end
always
begin
#10 clk =~clk;
end
always @ (negedge clk or negedge reset)
begin
if(!reset)
begin
if(address==5'd31)
begin
address = 5'd0;
//$finish;
end
else
address = address+5'd1;
end
else
address = 5'd0;
end
//******* display *********************//
always @ (posedge clk)
begin
//*********** 1 **************//
if(out_r1[15] == 1'b1)
begin
data_tmp11=~out_r1+1'b1;
$display("-%d + ",data_tmp11);
end
else
begin
data_tmp11=out_r1;
$display("%d + ",data_tmp11);
end
if(out_i1[15] == 1'b1)
begin
data_tmp12=~out_i1+1'b1;
$display("-%d i \n",data_tmp12);
end
else
begin
data_tmp12=out_i1;
$display("%d i \n",data_tmp12);
end
//*********** 2 **************//
if(out_r2[15] == 1'b1)
begin
data_tmp21=~out_r2+1'b1;
$display("-%d + ",data_tmp21);
end
else
begin
data_tmp21=out_r2;
$display("%d + ",data_tmp21);
end
if(out_i2[15] == 1'b1)
begin
data_tmp22=~out_i2+1'b1;
$display("-%d i \n",data_tmp22);
end
else
begin
data_tmp22=out_i2;
$display("%d i \n",data_tmp22);
end
//*********** 3 **************//
if(out_r3[15] == 1'b1)
begin
data_tmp31=~out_r3+1'b1;
$display("-%d + ",data_tmp31);
end
else
begin
data_tmp31=out_r3;
$display("%d + ",data_tmp31);
end
if(out_i3[15] == 1'b1)
begin
data_tmp32=~out_i3+1'b1;
$display("-%d i \n",data_tmp32);
end
else
begin
data_tmp32=out_i3;
$display("%d i \n",data_tmp32);
end
//*********** 4 **************//
if(out_r4[15] == 1'b1)
begin
data_tmp41=~out_r4+1'b1;
$display("-%d + ",data_tmp41);
end
else
begin
data_tmp41=out_r4;
$display("%d + ",data_tmp41);
end
if(out_i4[15] == 1'b1)
begin
data_tmp42=~out_i4+1'b1;
$display("-%d i \n",data_tmp42);
end
else
begin
data_tmp42=out_i4;
$display("%d i \n",data_tmp42);
end
//*********** 5 **************//
if(out_r5[15] == 1'b1)
begin
data_tmp51=~out_r5+1'b1;
$display("-%d + ",data_tmp51);
end
else
begin
data_tmp51=out_r5;
$display("%d + ",data_tmp51);
end
if(out_i5[15] == 1'b1)
begin
data_tmp52=~out_i5+1'b1;
$display("-%d i \n",data_tmp52);
end
else
begin
data_tmp52=out_i5;
$display("%d i \n",data_tmp52);
end
//*********** 6 **************//
if(out_r6[15] == 1'b1)
begin
data_tmp61=~out_r6+1'b1;
$display("-%d + ",data_tmp11);
end
else
begin
data_tmp61=out_r6;
$display("%d + ",data_tmp61);
end
if(out_i6[15] == 1'b1)
begin
data_tmp62=~out_i6+1'b1;
$display("-%d i \n",data_tmp62);
end
else
begin
data_tmp62=out_i6;
$display("%d i \n",data_tmp62);
end
//*********** 7 **************//
if(out_r7[15] == 1'b1)
begin
data_tmp71=~out_r7+1'b1;
$display("-%d + ",data_tmp71);
end
else
begin
data_tmp71=out_r7;
$display("%d + ",data_tmp71);
end
if(out_i7[15] == 1'b1)
begin
data_tmp72=~out_i7+1'b1;
$display("-%d i \n",data_tmp72);
end
else
begin
data_tmp72=out_i7;
$display("%d i \n",data_tmp72);
end//*********** 8 **************//
if(out_r8[15] == 1'b1)
begin
data_tmp81=~out_r8+1'b1;
$display("-%d + ",data_tmp81);
end
else
begin
data_tmp81=out_r8;
$display("%d + ",data_tmp81);
end
if(out_i8[15] == 1'b1)
begin
data_tmp82=~out_i8+1'b1;
$display("-%d i \n",data_tmp82);
end
else
begin
data_tmp82=out_i8;
$display("%d i \n",data_tmp82);
end//*********** 9 **************//
if(out_r9[15] == 1'b1)
begin
data_tmp91=~out_r9+1'b1;
$display("-%d + ",data_tmp91);
end
else
begin
data_tmp91=out_r9;
$display("%d + ",data_tmp91);
end
if(out_i9[15] == 1'b1)
begin
data_tmp92=~out_i9+1'b1;
$display("-%d i \n",data_tmp92);
end
else
begin
data_tmp92=out_i9;
$display("%d i \n",data_tmp92);
end//*********** 10 **************//
if(out_r10[15] == 1'b1)
begin
data_tmp101=~out_r10+1'b1;
$display("-%d + ",data_tmp101);
end
else
begin
data_tmp101=out_r10;
$display("%d + ",data_tmp101);
end
if(out_i10[15] == 1'b1)
begin
data_tmp102=~out_i10+1'b1;
$display("-%d i \n",data_tmp102);
end
else
begin
data_tmp102=out_i10;
$display("%d i \n",data_tmp102);
end//*********** 11**************//
if(out_r11[15] == 1'b1)
begin
data_tmp111=~out_r11+1'b1;
$display("-%d + ",data_tmp111);
end
else
begin
data_tmp111=out_r11;
$display("%d + ",data_tmp111);
end
if(out_i11[15] == 1'b1)
begin
data_tmp112=~out_i11+1'b1;
$display("-%d i \n",data_tmp112);
end
else
begin
data_tmp112=out_i11;
$display("%d i \n",data_tmp112);
end//*********** 12 **************//
if(out_r12[15] == 1'b1)
begin
data_tmp121=~out_r12+1'b1;
$display("-%d + ",data_tmp121);
end
else
begin
data_tmp121=out_r12;
$display("%d + ",data_tmp121);
end
if(out_i12[15] == 1'b1)
begin
data_tmp122=~out_i12+1'b1;
$display("-%d i \n",data_tmp122);
end
else
begin
data_tmp122=out_i12;
$display("%d i \n",data_tmp122);
end//*********** 13 **************//
if(out_r13[15] == 1'b1)
begin
data_tmp131=~out_r13+1'b1;
$display("-%d + ",data_tmp131);
end
else
begin
data_tmp131=out_r13;
$display("%d + ",data_tmp131);
end
if(out_i13[15] == 1'b1)
begin
data_tmp132=~out_i13+1'b1;
$display("-%d i \n",data_tmp132);
end
else
begin
data_tmp132=out_i13;
$display("%d i \n",data_tmp132);
end//*********** 14 **************//
if(out_r14[15] == 1'b1)
begin
data_tmp141=~out_r14+1'b1;
$display("-%d + ",data_tmp141);
end
else
begin
data_tmp141=out_r14;
$display("%d + ",data_tmp141);
end
if(out_i14[15] == 1'b1)
begin
data_tmp142=~out_i14+1'b1;
$display("-%d i \n",data_tmp142);
end
else
begin
data_tmp142=out_i14;
$display("%d i \n",data_tmp142);
end//*********** 15 **************//
if(out_r15[15] == 1'b1)
begin
data_tmp151=~out_r15+1'b1;
$display("-%d + ",data_tmp151);
end
else
begin
data_tmp151=out_r15;
$display("%d + ",data_tmp151);
end
if(out_i15[15] == 1'b1)
begin
data_tmp152=~out_i15+1'b1;
$display("-%d i \n",data_tmp152);
end
else
begin
data_tmp152=out_i15;
$display("%d i \n",data_tmp152);
end//*********** 16 **************//
if(out_r16[15] == 1'b1)
begin
data_tmp161=~out_r16+1'b1;
$display("-%d + ",data_tmp161);
end
else
begin
data_tmp161=out_r16;
$display("%d + ",data_tmp161);
end
if(out_i16[15] == 1'b1)
begin
data_tmp162=~out_i16+1'b1;
$display("-%d i \n",data_tmp162);
end
else
begin
data_tmp162=out_i16;
$display("%d i \n",data_tmp162);
end
end
endmodule |
module butterflyUnitRadix4(
input clk,
input[16:0] cos0,
input[16:0] sin0,
input[16:0] cos1,
input[16:0] sin1,
input[16:0] cos2,
input[16:0] sin2,
input[15:0] x1_re,
input[15:0] x1_im,
input[15:0] x2_re,
input[15:0] x2_im,
input[15:0] x3_re,
input[15:0] x3_im,
input[15:0] x4_re,
input[15:0] x4_im,
output[15:0] p1_re,
output[15:0] p1_im,
output[15:0] p2_re,
output[15:0] p2_im,
output[15:0] p3_re,
output[15:0] p3_im,
output[15:0] p4_re,
output[15:0] p4_im
);
/** complex multi output **/
wire[15:0] X2_re;
wire[15:0] X2_im;
wire[15:0] X3_re;
wire[15:0] X3_im;
wire[15:0] X4_re;
wire[15:0] X4_im;
/**end**/
reg[15:0] X1_re_reg0 = 16'd0;
reg[15:0] X1_re_reg1 = 16'd0;
reg[15:0] X1_re_reg2 = 16'd0;
reg[15:0] X1_re_reg3 = 16'd0;
reg[15:0] X1_re_reg4 = 16'd0;
reg[15:0] X1_re_reg5 = 16'd0;
reg[15:0] X1_im_reg0 = 16'd0;
reg[15:0] X1_im_reg1 = 16'd0;
reg[15:0] X1_im_reg2 = 16'd0;
reg[15:0] X1_im_reg3 = 16'd0;
reg[15:0] X1_im_reg4 = 16'd0;
reg[15:0] X1_im_reg5 = 16'd0;
always @(posedge clk)
begin
X1_re_reg0 <= x1_re;
X1_im_reg0 <= x1_im;
X1_re_reg1 <= X1_re_reg0;
X1_im_reg1 <= X1_im_reg0;
X1_re_reg2 <= X1_re_reg1;
X1_im_reg2 <= X1_im_reg1;
X1_re_reg3 <= X1_re_reg2;
X1_im_reg3 <= X1_im_reg2;
X1_re_reg4 <= X1_re_reg3;
X1_im_reg4 <= X1_im_reg3;
X1_re_reg5 <= X1_re_reg4;
X1_im_reg5 <= X1_im_reg4;
end
//**************** Second Butterfly *****************
// n=0:3
// X2(n+1) = W(1,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+5) = W(2,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+9) = W(3,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
// X2(n+13) = W(4,:)*[X1(4*n+1),X1(4*n+2)*exp(-1i*2*pi/N*n),X1(4*n+3)*exp(-1i*2*pi/N*2*n),X1(4*n+4)*exp(-1i*2*pi/N*3*n)].';
complex_mul inst0_complex_mul(
.clk(clk),
.ar(cos0),
.ai(sin0),
.br(x2_re),
.bi(x2_im),
.pr(X2_re),
.pi(X2_im)
);
complex_mul inst1_complex_mul(
.clk(clk),
.ar(cos1),
.ai(sin1),
.br(x3_re),
.bi(x3_im),
.pr(X3_re),
.pi(X3_im)
);
complex_mul inst2_complex_mul(
.clk(clk),
.ar(cos2),
.ai(sin2),
.br(x4_re),
.bi(x4_im),
.pr(X4_re),
.pi(X4_im)
);
complexAddRadix_4 complexAdd_2ndButterfly(
.clk(clk),
.x1_re(X1_re_reg5),
.x1_im(X1_im_reg5),
.x2_re(X2_re),
.x2_im(X2_im),
.x3_re(X3_re),
.x3_im(X3_im),
.x4_re(X4_re),
.x4_im(X4_im),
.re_0(p1_re),
.im_0(p1_im),
.re_1(p2_re),
.im_1(p2_im),
.re_2(p3_re),
.im_2(p3_im),
.re_3(p4_re),
.im_3(p4_im)
);
endmodule |
module FFT16Radix4(
);
endmodule |
module layer_1(
input sys_clk ,
input sys_rst_n ,
input start_flag ,
output [32:0] data_out ,
output out_valid
);
wire [15:0] data_pic ;
wire pic_valid ;
pic_input pic_generate(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.pic_start (start_flag ),
.pic_out_valid (pic_valid ),
.data_pic (data_pic )
);
conv conv_1_1(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.data_pic (data_pic ),
.pic_valid (pic_valid ),
.data_out (data_out ),
.out_valid (out_valid )
);
endmodule |
module vga(
input clk ,
input rst_n ,
input [23:0] data ,
output hs ,
output vs ,
output [ 9:0] x_pix ,
output [ 9:0] y_pix ,
output [23:0] color_rgb
);
parameter h_sync = 'd96 ;
parameter h_back = 'd40 ;
parameter h_left = 'd8 ;
parameter h_vali = 'd640 ;
parameter h_righ = 'd8 ;
parameter h_fron = 'd8 ;
parameter h_peri = 'd800 ;
parameter v_sync = 'd2 ;
parameter v_back = 'd25 ;
parameter v_topb = 'd8 ;
parameter v_vali = 'd480 ;
parameter v_unde = 'd8 ;
parameter v_fron = 'd2 ;
parameter v_peri = 'd525 ;
reg [9:0] v_count ;
reg [9:0] h_count ;
wire h_en ;
wire v_en ;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)begin
h_count <= 10'd0;
v_count <= 10'd0;
end
else if(h_count < h_peri)
h_count <= h_count + 1'b1;
else begin
h_count <= 10'd0;
if (v_count < v_peri)
v_count <= v_count + 1'b1;
else
v_count <= 10'd0;
end
end
assign hs = (h_count > 'd0 && h_count < h_sync) ? 1'b0 : 1'b1;
assign vs = (v_count > 'd0 && v_count < v_sync) ? 1'b0 : 1'b1;
assign h_en = (h_count > h_sync + h_back + h_left && h_count < h_sync + h_back + h_left + h_vali) ? 1'b1 : 1'b0;
assign v_en = (v_count > v_sync + v_back + v_topb && v_count < v_sync + v_back + v_topb + v_vali) ? 1'b1 : 1'b0;
assign x_pix = h_en ? h_count - h_sync - h_back - h_left : 10'b0;
assign y_pix = v_en ? v_count - v_sync - v_back - v_topb : 10'b0;
assign color_rgb = h_en && v_en ? data : 24'd0;
endmodule |
module ann (
input clk ,
input rst_n ,
input signed [20:0] ina ,
input signed [20:0] inb ,
input signed [20:0] inc ,
input signed [20:0] ind ,
input valid_in,
output reg valid_out,
output reg signed [20:0] out1 ,
output reg signed [20:0] out2 ,
output reg signed [20:0] out3
);
parameter w1_1 = 21'b1_1111_1111_1010_0001_1011;
parameter w2_1 = 21'b1_1111_1101_1100_0011_1110;
parameter w3_1 = 21'b1_1111_1111_0100_1011_0010;
parameter w4_1 = 21'b1_1111_1111_1011_1000_1000;
parameter w5_1 = 21'b1_1111_1111_1000_0000_0011;
parameter w6_1 = 21'b1_1111_1101_1100_0000_1001;
parameter w7_1 = 21'b1_1111_1111_1000_1110_1000;
parameter w8_1 = 21'b1_1111_1110_1111_1111_1001;
parameter w1_2 = 21'b1_1111_1111_1011_1011_0101;
parameter w2_2 = 21'b1_1111_1101_1010_1100_1001;
parameter w3_2 = 21'b1_1111_1111_0111_1101_1110;
parameter w4_2 = 21'b0_0000_0000_0100_0011_0000;
parameter w5_2 = 21'b1_1111_1111_1001_0101_0001;
parameter w6_2 = 21'b1_1111_1111_1110_1001_0101;
parameter w7_2 = 21'b1_1111_1111_0101_0101_0000;
parameter w8_2 = 21'b1_1111_1111_1111_0101_0010;
parameter w1_3 = 21'b1_1111_1111_1010_1010_1111;
parameter w2_3 = 21'b0_0000_0101_1001_1100_0100;
parameter w3_3 = 21'b1_1111_1111_0110_1001_1110;
parameter w4_3 = 21'b1_1111_1111_1001_0010_1100;
parameter w5_3 = 21'b0_0000_0000_0110_1100_1101;
parameter w6_3 = 21'b1_1111_1110_1111_1101_0111;
parameter w7_3 = 21'b1_1111_1111_1011_1100_1000;
parameter w8_3 = 21'b1_1111_1111_0111_0011_1000;
parameter w1_4 = 21'b0_0000_0000_0001_1011_1001;
parameter w2_4 = 21'b0_0000_1010_0101_1111_1101;
parameter w3_4 = 21'b1_1111_1111_1101_1011_0101;
parameter w4_4 = 21'b1_1111_1111_0101_1001_0011;
parameter w5_4 = 21'b1_1111_1111_1000_1000_1000;
parameter w6_4 = 21'b1_1111_1111_1110_1001_0010;
parameter w7_4 = 21'b1_1111_1111_0110_1110_1011;
parameter w8_4 = 21'b1_1111_1111_1001_0010_1110;
parameter w1_21 = 21'b0_0000_0000_1001_1011_0000;
parameter w2_21 = 21'b0_0000_0000_0100_1101_1100;
parameter w3_21 = 21'b1_1111_1111_1011_1011_0011;
parameter w4_21 = 21'b0_0000_0000_0101_1011_0000;
parameter w5_21 = 21'b1_1111_1111_1000_0011_1011;
parameter w6_21 = 21'b1_1111_1111_1110_1110_1110;
parameter w7_21 = 21'b0_0000_0000_1000_0000_0001;
parameter w8_21 = 21'b1_1111_1111_1011_1111_0101;
parameter w1_22 = 21'b1_1111_1110_0110_1110_0101;
parameter w2_22 = 21'b1_1111_1111_1000_1011_1000;
parameter w3_22 = 21'b1_1111_1111_0110_1001_0110;
parameter w4_22 = 21'b0_0000_1010_0010_0011_1000;
parameter w5_22 = 21'b1_1111_1110_1011_1110_0111;
parameter w6_22 = 21'b1_1111_1100_1101_0001_1011;
parameter w7_22 = 21'b1_1111_1111_1111_1101_0110;
parameter w8_22 = 21'b1_1111_1111_0111_0100_0001;
parameter w1_23 = 21'b0_0000_0000_0001_0111_0100;
parameter w2_23 = 21'b1_1111_1111_1001_0001_0101;
parameter w3_23 = 21'b0_0000_0000_0001_1100_0000;
parameter w4_23 = 21'b0_0000_0000_0011_1110_1010;
parameter w5_23 = 21'b1_1111_1111_1000_0011_0101;
parameter w6_23 = 21'b1_1111_1111_1110_0101_0001;
parameter w7_23 = 21'b0_0000_0000_0011_1100_1111;
parameter w8_23 = 21'b1_1111_1111_1110_0101_0010;
parameter w1_24 = 21'b1_1111_1111_0111_0010_1111;
parameter w2_24 = 21'b0_0000_0000_0000_1011_0100;
parameter w3_24 = 21'b0_0000_0000_0011_0011_0101;
parameter w4_24 = 21'b0_0000_0000_0000_0100_1011;
parameter w5_24 = 21'b0_0000_0000_1000_1011_0101;
parameter w6_24 = 21'b0_0000_0000_0001_1011_0010;
parameter w7_24 = 21'b0_0000_0000_0111_1110_0111;
parameter w8_24 = 21'b1_1111_1111_1000_1110_0110;
parameter w1_25 = 21'b1_1111_1111_1000_1110_1111;
parameter w2_25 = 21'b0_0000_0000_0110_0000_0101;
parameter w3_25 = 21'b1_1111_1111_1101_1111_1111;
parameter w4_25 = 21'b1_1111_1111_1001_0111_0010;
parameter w5_25 = 21'b0_0000_0000_1000_0101_1111;
parameter w6_25 = 21'b1_1111_1111_1101_0000_0101;
parameter w7_25 = 21'b0_0000_0000_0100_1110_1010;
parameter w8_25 = 21'b0_0000_0000_0100_0110_1101;
parameter w1_26 = 21'b1_1111_1111_1000_1001_0001;
parameter w2_26 = 21'b0_0000_0000_0010_0110_1100;
parameter w3_26 = 21'b0_0000_0000_0100_1110_1010;
parameter w4_26 = 21'b0_0000_0000_0000_0101_0010;
parameter w5_26 = 21'b1_1111_1111_1011_0111_1110;
parameter w6_26 = 21'b1_1111_1111_1001_0000_1010;
parameter w7_26 = 21'b1_1111_1111_1110_1001_1000;
parameter w8_26 = 21'b0_0000_0000_1001_0001_1011;
parameter w1_27 = 21'b0_0000_0000_0011_0011_0011;
parameter w2_27 = 21'b0_0000_0000_0010_0110_0010;
parameter w3_27 = 21'b1_1111_1111_1000_0111_0100;
parameter w4_27 = 21'b0_0000_0000_1000_1100_1110;
parameter w5_27 = 21'b1_1111_1111_1111_0000_0101;
parameter w6_27 = 21'b0_0000_0000_0001_1000_1001;
parameter w7_27 = 21'b1_1111_1111_1110_0011_0011;
parameter w8_27 = 21'b1_1111_1111_1010_1101_1010;
parameter w1_28 = 21'b0_0000_0000_0011_1111_0101;
parameter w2_28 = 21'b0_0000_0000_0001_0111_0001;
parameter w3_28 = 21'b1_1111_1111_0110_0100_0100;
parameter w4_28 = 21'b0_0000_0000_0011_0010_0000;
parameter w5_28 = 21'b1_1111_1111_1100_1001_1011;
parameter w6_28 = 21'b1_1111_1111_1100_0100_1010;
parameter w7_28 = 21'b0_0000_0000_0111_1000_1111;
parameter w8_28 = 21'b1_1111_1111_1101_0011_0100;
parameter w1_31 = 21'b0_0000_0010_1011_0110_1000;
parameter w2_31 = 21'b1_1111_1110_1001_1011_0001;
parameter w3_31 = 21'b1_1111_1110_1111_1000_0100;
parameter w4_31 = 21'd0;
parameter w5_31 = 21'd0;
parameter w6_31 = 21'd0;
parameter w7_31 = 21'd0;
parameter w8_31 = 21'd0;
parameter w1_32 = 21'b0_0000_0001_0011_0000_0000;
parameter w2_32 = 21'b1_1111_1111_1100_0100_1110;
parameter w3_32 = 21'b0_0000_0000_0110_1011_1001;
parameter w4_32 = 21'd0;
parameter w5_32 = 21'd0;
parameter w6_32 = 21'd0;
parameter w7_32 = 21'd0;
parameter w8_32 = 21'd0;
parameter w1_33 = 21'b0_0000_0000_0100_1111_1111;
parameter w2_33 = 21'b1_1111_1111_0111_0010_0000;
parameter w3_33 = 21'b1_1111_1111_0100_1010_1001;
parameter w4_33 = 21'd0;
parameter w5_33 = 21'd0;
parameter w6_33 = 21'd0;
parameter w7_33 = 21'd0;
parameter w8_33 = 21'd0;
parameter w1_34 = 21'b1_1110_1000_0111_1110_0100;
parameter w2_34 = 21'b0_0000_1010_1100_1010_0010;
parameter w3_34 = 21'b0_0000_1010_1111_0010_0010;
parameter w4_34 = 21'd0;
parameter w5_34 = 21'd0;
parameter w6_34 = 21'd0;
parameter w7_34 = 21'd0;
parameter w8_34 = 21'd0;
parameter w1_35 = 21'b0_0000_0001_1101_1000_0001;
parameter w2_35 = 21'b1_1111_1111_0001_1100_1011;
parameter w3_35 = 21'b1_1111_1111_1011_0110_0000;
parameter w4_35 = 21'd0;
parameter w5_35 = 21'd0;
parameter w6_35 = 21'd0;
parameter w7_35 = 21'd0;
parameter w8_35 = 21'd0;
parameter w1_36 = 21'b0_0000_0011_0000_1111_0101;
parameter w2_36 = 21'b1_1111_1101_1000_0010_0011;
parameter w3_36 = 21'b1_1111_1111_0000_1110_0100;
parameter w4_36 = 21'd0;
parameter w5_36 = 21'd0;
parameter w6_36 = 21'd0;
parameter w7_36 = 21'd0;
parameter w8_36 = 21'd0;
parameter w1_37 = 21'b0_0000_0000_0010_0000_0111;
parameter w2_37 = 21'b0_0000_0000_1011_0001_1000;
parameter w3_37 = 21'b0_0000_0000_0001_0111_0001;
parameter w4_37 = 21'd0;
parameter w5_37 = 21'd0;
parameter w6_37 = 21'd0;
parameter w7_37 = 21'd0;
parameter w8_37 = 21'd0;
parameter w1_38 = 21'b1_1111_1111_0100_1010_0001;
parameter w2_38 = 21'b0_0000_0000_0111_0001_1010;
parameter w3_38 = 21'b1_1111_1111_1001_1011_0001;
parameter w4_38 = 21'd0;
parameter w5_38 = 21'd0;
parameter w6_38 = 21'd0;
parameter w7_38 = 21'd0;
parameter w8_38 = 21'd0;
parameter b1_1 = 21'b0_0000_0000_1001_1011_0101;
parameter b2_1 = 21'b1_1111_1111_0100_0001_0001;
parameter b3_1 = 21'b0_0000_0000_0100_0101_0111;
parameter b4_1 = 21'b1_1111_1111_1011_1101_0100;
parameter b5_1 = 21'b0_0000_0000_0100_0011_1000;
parameter b6_1 = 21'b0_0000_0000_0011_1100_1010;
parameter b7_1 = 21'b1_1111_1111_0101_0001_1010;
parameter b8_1 = 21'b0_0000_0000_0011_1111_0100;
parameter b1_2 = 21'b0_0000_0010_0101_0011_1010;
parameter b2_2 = 21'b1_1111_1111_1110_0100_0101;
parameter b3_2 = 21'b1_1111_1111_0110_1000_0100;
parameter b4_2 = 21'b1_1111_0101_1110_0001_1111;
parameter b5_2 = 21'b0_0000_0001_1111_1010_1010;
parameter b6_2 = 21'b0_0000_0011_0111_0010_1011;
parameter b7_2 = 21'b1_1111_1111_1001_1001_0101;
parameter b8_2 = 21'b1_1111_1111_1000_1110_0100;
parameter b1_3 = 21'b0_0001_0011_1110_1111_0010;
parameter b2_3 = 21'b0_0000_1000_0011_0000_0101;
parameter b3_3 = 21'b1_1110_0100_1011_0011_1011;
parameter b4_3 = 21'd0;
parameter b5_3 = 21'd0;
parameter b6_3 = 21'd0;
parameter b7_3 = 21'd0;
parameter b8_3 = 21'd0;
reg signed [20:0] w1 ;
reg signed [20:0] w2 ;
reg signed [20:0] w3 ;
reg signed [20:0] w4 ;
reg signed [20:0] w5 ;
reg signed [20:0] w6 ;
reg signed [20:0] w7 ;
reg signed [20:0] w8 ;
reg signed [20:0] b1 ;
reg signed [20:0] b2 ;
reg signed [20:0] b3 ;
reg signed [20:0] b4 ;
reg signed [20:0] b5 ;
reg signed [20:0] b6 ;
reg signed [20:0] b7 ;
reg signed [20:0] b8 ;
reg signed [20:0] in1 ;
reg signed [40:0] sum1_1 ;
reg signed [20:0] sum_1 ;
reg signed [40:0] sum1_2 ;
reg signed [20:0] sum_2 ;
reg signed [40:0] sum1_3 ;
reg signed [20:0] sum_3 ;
reg signed [40:0] sum1_4 ;
reg signed [20:0] sum_4 ;
reg signed [40:0] sum1_5 ;
reg signed [20:0] sum_5 ;
reg signed [40:0] sum1_6 ;
reg signed [20:0] sum_6 ;
reg signed [40:0] sum1_7 ;
reg signed [20:0] sum_7 ;
reg signed [40:0] sum1_8 ;
reg signed [20:0] sum_8 ;
reg signed [20:0] sum2_1 ;
reg signed [20:0] sum2_2 ;
reg signed [20:0] sum2_3 ;
reg signed [20:0] sum2_4 ;
reg signed [20:0] sum2_5 ;
reg signed [20:0] sum2_6 ;
reg signed [20:0] sum2_7 ;
reg signed [20:0] sum2_8 ;
reg [7:0]cnt_1;
reg [7:0] cnt_2;
reg [7:0] cnt_3;
reg signed [20:0] suma ;
reg signed [20:0] sumb ;
reg signed [20:0] sumc ;
reg signed [20:0] sumd ;
reg signed [20:0] sume ;
reg signed [20:0] sumf ;
reg signed [20:0] sumg ;
reg signed [20:0] sumh ;
reg signed [20:0] suma_1 ;
reg signed [20:0] sumb_1 ;
reg signed [20:0] sumc_1 ;
reg signed [20:0] sumd_1 ;
reg signed [20:0] sume_1 ;
reg signed [20:0] sumf_1 ;
reg signed [20:0] sumg_1 ;
reg signed [20:0] sumh_1 ;
wire signed [20:0] suma1 ;
wire signed [20:0] sumb1 ;
wire signed [20:0] sumc1 ;
wire signed [20:0] sumd1 ;
wire signed [20:0] sume1 ;
wire signed [20:0] sumf1 ;
wire signed [20:0] sumg1 ;
wire signed [20:0] sumh1 ;
wire signed [20:0] suma_11 ;
wire signed [20:0] sumb_11 ;
wire signed [20:0] sumc_11 ;
wire signed [20:0] sumd_11 ;
wire signed [20:0] sume_11 ;
wire signed [20:0] sumf_11 ;
wire signed [20:0] sumg_11 ;
wire signed [20:0] sumh_11 ;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_1 = 41'd0;
sum_1 = 21'd0;
sum2_1 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_1 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_1 = 21'd0;
end
else begin
sum1_1 = in1 * w1;
sum2_1 = {sum1_1[40],sum1_1[31:24],sum1_1[23:12]};
sum_1 =sum_1 +sum2_1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_2 = 41'd0;
sum_2 = 21'd0;
sum2_2 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_2 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_2 = 21'd0;
end
else begin
sum1_2 = in1 * w2;
sum2_2 = {sum1_2[40],sum1_2[31:24],sum1_2[23:12]};
sum_2 =sum_2 +sum2_2;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_3 = 41'd0;
sum_3 = 21'd0;
sum2_3 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_3 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_3 = 21'd0;
end
else begin
sum1_3 = in1 * w3;
sum2_3 = {sum1_3[40],sum1_3[31:24],sum1_3[23:12]};
sum_3 =sum_3 +sum2_3;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_4 = 41'd0;
sum_4 = 21'd0;
sum2_4 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_4 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_4 = 21'd0;
end
else begin
sum1_4 = in1 * w4;
sum2_4 = {sum1_4[40],sum1_4[31:24],sum1_4[23:12]};
sum_4 =sum_4 +sum2_4;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_5 = 41'd0;
sum_5 = 21'd0;
sum2_5 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_5 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_5 = 21'd0;
end
else begin
sum1_5 = in1 * w5;
sum2_5 = {sum1_5[40],sum1_5[31:24],sum1_5[23:12]};
sum_5 =sum_5 +sum2_5;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_6 = 41'd0;
sum_6 = 21'd0;
sum2_6 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_6 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_6 = 21'd0;
end
else begin
sum1_6 = in1 * w6;
sum2_6= {sum1_6[40],sum1_6[31:24],sum1_6[23:12]};
sum_6 =sum_6 +sum2_6;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_7 = 41'd0;
sum_7 = 21'd0;
sum2_7 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_7 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_7 = 21'd0;
end
else begin
sum1_7 = in1 * w7;
sum2_7 = {sum1_7[40],sum1_7[31:24],sum1_7[23:12]};
sum_7 =sum_7+sum2_7;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum1_8 = 41'd0;
sum_8 = 21'd0;
sum2_8 = 21'd0;
end
else if (cnt_2 == 8'd1) begin
sum_8 = 21'd0;
end
else if (cnt_3 == 8'd1) begin
sum_8 = 21'd0;
end
else begin
sum1_8 = in1 * w8;
sum2_8 = {sum1_8[40],sum1_8[31:24],sum1_8[23:12]};
sum_8 =sum_8 +sum2_8;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt_1<= 8'd0;
cnt_2<= 8'd0;
cnt_3<= 8'd0;
end
else if(valid_in == 1'd1) begin
cnt_1 <= cnt_1 + 1'd1;
if(cnt_1>=8'd6 && cnt_3 <=8'd20)
cnt_2 <=cnt_2 + 1'd1;
if(cnt_2 >= 8'd10 && cnt_3 <=8'd20)
cnt_3<=cnt_3 + 1'd1;
if(cnt_3 ==8'd20)begin
cnt_1<= cnt_1;
cnt_2<=cnt_2 ;
cnt_3<= cnt_3;
end
end
else begin
cnt_1<= 8'd0;
cnt_2<= 8'd0;
cnt_3<= 8'd0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)begin
valid_out<=1'd0;
suma<= 21'd0;
sumb<= 21'd0;
sumc<= 21'd0;
sumd<= 21'd0;
sume<= 21'd0;
sumf<= 21'd0;
sumg<= 21'd0;
sumh<= 21'd0;
suma_1<= 21'd0;
sumb_1<= 21'd0;
sumc_1<= 21'd0;
sumd_1<= 21'd0;
sume_1<= 21'd0;
sumf_1<= 21'd0;
sumg_1<= 21'd0;
sumh_1<= 21'd0;
out1<= 21'd0;
out2<= 21'd0;
out3<= 21'd0;
end
else if (cnt_1 == 8'd6) begin
suma<= sum_1+b1;
sumb<= sum_2+b2;
sumc<= sum_3+b3;
sumd<= sum_4+b4;
sume<= sum_5+b5;
sumf<= sum_6+b6;
sumg<= sum_7+b7;
sumh<= sum_8+b8;
end
else if (cnt_2 == 8'd10) begin
suma_1<= sum_1+b1;
sumb_1<= sum_2+b2;
sumc_1<= sum_3+b3;
sumd_1<= sum_4+b4;
sume_1<= sum_5+b5;
sumf_1<= sum_6+b6;
sumg_1<= sum_7+b7;
sumh_1<= sum_8+b8;
end
else if (cnt_3 == 8'd10) begin
out1<= sum_1+b1;
out2<= sum_2+b2;
out3<= sum_3+b3;
end
else if(cnt_3 == 8'd15)
valid_out<=1'd1;
end
assign suma1 = (suma[20] == 1'd0 )? suma: 21'b0;
assign sumb1 = (sumb[20] == 1'd0 )? sumb: 21'b0;
assign sumc1 = (sumc[20] == 1'd0 )? sumc: 21'b0;
assign sumd1 = (sumd[20] == 1'd0 )? sumd: 21'b0;
assign sume1 = (sume[20] == 1'd0 )? sume: 21'b0;
assign sumf1 = (sumf[20] == 1'd0 )? sumf: 21'b0;
assign sumg1 = (sumg[20] == 1'd0 )? sumg: 21'b0;
assign sumh1 = (sumh[20] == 1'd0 )? sumh: 21'b0;
assign suma_11 = (suma_1[20] == 1'd0 )? suma_1: 21'b0;
assign sumb_11 = (sumb_1[20] == 1'd0 )? sumb_1: 21'b0;
assign sumc_11 = (sumc_1[20] == 1'd0 )? sumc_1: 21'b0;
assign sumd_11 = (sumd_1[20] == 1'd0 )? sumd_1: 21'b0;
assign sume_11 = (sume_1[20] == 1'd0 )? sume_1: 21'b0;
assign sumf_11 = (sumf_1[20] == 1'd0 )? sumf_1: 21'b0;
assign sumg_11 = (sumg_1[20] == 1'd0 )? sumg_1: 21'b0;
assign sumh_11 = (sumh_1[20] == 1'd0 )? sumh_1: 21'b0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
in1<=21'd0;
b1 <= 0;
b2 <= 0;
b3 <= 0;
b4 <= 0;
b5 <= 0;
b6 <= 0;
b7 <= 0;
b8 <= 0;
w1 <= 0 ;
w2 <= 0 ;
w3 <= 0 ;
w4 <= 0 ;
w5 <= 0 ;
w6 <= 0 ;
w7 <= 0 ;
w8 <= 0 ;
end
else if (cnt_1 > 8'd0&&cnt_1 <= 8'd4)begin
b1 <= b1_1;
b2 <= b2_1;
b3 <= b3_1;
b4 <= b4_1;
b5 <= b5_1;
b6 <= b6_1;
b7 <= b7_1;
b8 <= b8_1;
case(cnt_1)
8'd1: begin
in1 <= ina;
w1 <= w1_1 ;
w2 <= w2_1 ;
w3 <= w3_1 ;
w4 <= w4_1 ;
w5 <= w5_1 ;
w6 <= w6_1 ;
w7 <= w7_1 ;
w8 <= w8_1 ;
end
8'd2: begin
in1 <= inb;
w1 <= w1_2 ;
w2 <= w2_2 ;
w3 <= w3_2 ;
w4 <= w4_2 ;
w5 <= w5_2 ;
w6 <= w6_2 ;
w7 <= w7_2 ;
w8 <= w8_2 ;
end
8'd3: begin
in1 <= inc;
w1 <= w1_3 ;
w2 <= w2_3 ;
w3 <= w3_3 ;
w4 <= w4_3 ;
w5 <= w5_3 ;
w6 <= w6_3 ;
w7 <= w7_3 ;
w8 <= w8_3 ;
end
8'd4: begin
in1 <= ind;
w1 <= w1_4 ;
w2 <= w2_4 ;
w3 <= w3_4 ;
w4 <= w4_4 ;
w5 <= w5_4 ;
w6 <= w6_4 ;
w7 <= w7_4 ;
w8 <= w8_4 ;
end
default: begin
in1<=0;
w1 <= 0 ;
w2 <= 0 ;
w3 <= 0 ;
w4 <= 0 ;
w5 <= 0 ;
w6 <= 0 ;
w7 <= 0 ;
w8 <= 0 ;
end
endcase
end
else if (cnt_2 > 8'd0&&cnt_2 <= 8'd8) begin
b1 <= b1_2;
b2 <= b2_2;
b3 <= b3_2;
b4 <= b4_2;
b5 <= b5_2;
b6 <= b6_2;
b7 <= b7_2;
b8 <= b8_2;
case(cnt_2)
8'd1: begin
in1 <= suma1;
w1 <= w1_21 ;
w2 <= w2_21 ;
w3 <= w3_21 ;
w4 <= w4_21 ;
w5 <= w5_21 ;
w6 <= w6_21 ;
w7 <= w7_21 ;
w8 <= w8_21 ;
end
8'd2: begin
in1 <= sumb1;
w1 <= w1_22 ;
w2 <= w2_22 ;
w3 <= w3_22 ;
w4 <= w4_22 ;
w5 <= w5_22 ;
w6 <= w6_22 ;
w7 <= w7_22 ;
w8 <= w8_22 ;
end
8'd3: begin
in1 <= sumc1;
w1 <= w1_23 ;
w2 <= w2_23 ;
w3 <= w3_23 ;
w4 <= w4_23 ;
w5 <= w5_23 ;
w6 <= w6_23 ;
w7 <= w7_23 ;
w8 <= w8_23 ;
end
8'd4: begin
in1 <= sumd1;
w1 <= w1_24 ;
w2 <= w2_24 ;
w3 <= w3_24 ;
w4 <= w4_24 ;
w5 <= w5_24 ;
w6 <= w6_24 ;
w7 <= w7_24 ;
w8 <= w8_24 ;
end
8'd5: begin
in1 <= sume1;
w1 <= w1_25 ;
w2 <= w2_25 ;
w3 <= w3_25 ;
w4 <= w4_25 ;
w5 <= w5_25 ;
w6 <= w6_25 ;
w7 <= w7_25 ;
w8 <= w8_25 ;
end
8'd6: begin
in1 <= sumf1;
w1 <= w1_26 ;
w2 <= w2_26 ;
w3 <= w3_26 ;
w4 <= w4_26 ;
w5 <= w5_26 ;
w6 <= w6_26 ;
w7 <= w7_26 ;
w8 <= w8_26 ;
end
8'd7: begin
in1 <= sumg1;
w1 <= w1_27 ;
w2 <= w2_27 ;
w3 <= w3_27 ;
w4 <= w4_27 ;
w5 <= w5_27 ;
w6 <= w6_27 ;
w7 <= w7_27 ;
w8 <= w8_27 ;
end
8'd8: begin
in1 <= sumh1;
w1 <= w1_28 ;
w2 <= w2_28 ;
w3 <= w3_28 ;
w4 <= w4_28 ;
w5 <= w5_28 ;
w6 <= w6_28 ;
w7 <= w7_28 ;
w8 <= w8_28 ;
end
default:begin
in1<=0;
w1 <= 0 ;
w2 <= 0 ;
w3 <= 0 ;
w4 <= 0 ;
w5 <= 0 ;
w6 <= 0 ;
w7 <= 0 ;
w8 <= 0 ;
end
endcase
end
else if (cnt_3 > 8'd0 && cnt_3 <= 8'd8) begin
b1 <= b1_3;
b2 <= b2_3;
b3 <= b3_3;
b4 <= b4_3;
b5 <= b5_3;
b6 <= b6_3;
b7 <= b7_3;
b8 <= b8_3;
case(cnt_3)
8'd1: begin
in1 <= suma_11;
w1 <= w1_31 ;
w2 <= w2_31 ;
w3 <= w3_31 ;
w4 <= w4_31 ;
w5 <= w5_31 ;
w6 <= w6_31 ;
w7 <= w7_31 ;
w8 <= w8_31 ;
end
8'd2: begin
in1 <= sumb_11;
w1 <= w1_32 ;
w2 <= w2_32 ;
w3 <= w3_32 ;
w4 <= w4_32 ;
w5 <= w5_32 ;
w6 <= w6_32 ;
w7 <= w7_32 ;
w8 <= w8_32 ;
end
8'd3: begin
in1 <= sumc_11;
w1 <= w1_33 ;
w2 <= w2_33 ;
w3 <= w3_33 ;
w4 <= w4_33 ;
w5 <= w5_33 ;
w6 <= w6_33 ;
w7 <= w7_33 ;
w8 <= w8_33 ;
end
8'd4: begin
in1 <= sumd_11;
w1 <= w1_34 ;
w2 <= w2_34 ;
w3 <= w3_34 ;
w4 <= w4_34 ;
w5 <= w5_34 ;
w6 <= w6_34 ;
w7 <= w7_34 ;
w8 <= w8_34 ;
end
8'd5: begin
in1 <= sume_11;
w1 <= w1_35 ;
w2 <= w2_35 ;
w3 <= w3_35 ;
w4 <= w4_35 ;
w5 <= w5_35 ;
w6 <= w6_35 ;
w7 <= w7_35 ;
w8 <= w8_35 ;
end
8'd6: begin
in1 <= sumf_11;
w1 <= w1_36 ;
w2 <= w2_36 ;
w3 <= w3_36 ;
w4 <= w4_36 ;
w5 <= w5_36 ;
w6 <= w6_36 ;
w7 <= w7_36 ;
w8 <= w8_36 ;
end
8'd7: begin
in1 <= sumg_11;
w1 <= w1_37 ;
w2 <= w2_37 ;
w3 <= w3_37 ;
w4 <= w4_37 ;
w5 <= w5_37 ;
w6 <= w6_37 ;
w7 <= w7_37 ;
w8 <= w8_37 ;
end
8'd8: begin
in1 <= sumh_11;
w1 <= w1_38 ;
w2 <= w2_38 ;
w3 <= w3_38 ;
w4 <= w4_38 ;
w5 <= w5_38 ;
w6 <= w6_38 ;
w7 <= w7_38 ;
w8 <= w8_38 ;
end
default:begin
in1<=0;
w1 <= 0 ;
w2 <= 0 ;
w3 <= 0 ;
w4 <= 0 ;
w5 <= 0 ;
w6 <= 0 ;
w7 <= 0 ;
w8 <= 0 ;
end
endcase
end
else
in1<=21'd0;
end
endmodule |
module layer_2(
input sys_clk ,
input sys_rst_n ,
input start_flag ,
output [32:0] data_out ,
output out_valid
);
wire [32:0] data_max_out ;
wire data_max_valid ;
max_data_generate max_data_generate(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.data_start (start_flag ),
.data_out_valid (data_max_valid ),
.data_out (data_max_out )
);
maxpooling maxpooling_inst(
.clk (sys_clk ),
.rst_n (sys_rst_n ),
.input_data (data_max_out ),
.valid_input (data_max_valid ),
.out_data (data_out ),
.out_valid (out_valid )
);
endmodule |
module pic_input(
input clk ,
input rst_n ,
input pic_start ,
output pic_out_valid ,
output [15:0] data_pic
);
wire [15:0] data_pic_out ;
reg [15:0] data_pic_reg ;
reg [ 9:0] addr_pic ;
reg work_en_pic ;
reg pic_out_valid_reg ;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
data_pic_reg <= 16'b0;
else if (data_pic_out)
data_pic_reg <= data_pic_out;
else
data_pic_reg <= data_pic_reg;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
pic_out_valid_reg <= 1'b0;
else if (work_en_pic && addr_pic == 9'd1)
pic_out_valid_reg <= 1'b1;
else if (addr_pic == 10'd784)
pic_out_valid_reg <= 1'b0;
else
pic_out_valid_reg <= pic_out_valid_reg;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
addr_pic <= 10'b0;
else if (work_en_pic && addr_pic == 10'd784)
addr_pic <= 10'd784;
else if (work_en_pic)
addr_pic <= addr_pic + 1'b1;
else
addr_pic <= addr_pic;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
work_en_pic <= 1'b0;
else if (pic_start)
work_en_pic <= 1'b1;
else if (addr_pic == 10'd784)
work_en_pic <= 1'b0;
end
assign data_pic = data_pic_reg;
assign pic_out_valid = pic_out_valid_reg;
rom_0_388 rom_pic(
.clka (clk ),
.addra (addr_pic ),
.douta (data_pic_out )
);
endmodule |
module conv#(
/*parameter conv_w_0_0 = 16'd1 ,
parameter conv_w_0_1 = 16'd1 ,
parameter conv_w_0_2 = 16'd1 ,
parameter conv_w_0_3 = 16'd1 ,
parameter conv_w_0_4 = 16'd1 ,
parameter conv_w_1_0 = 16'd1 ,
parameter conv_w_1_1 = 16'd1 ,
parameter conv_w_1_2 = 16'd1 ,
parameter conv_w_1_3 = 16'd1 ,
parameter conv_w_1_4 = 16'd1 ,
parameter conv_w_2_0 = 16'd1 ,
parameter conv_w_2_1 = 16'd1 ,
parameter conv_w_2_2 = 16'd1 ,
parameter conv_w_2_3 = 16'd1 ,
parameter conv_w_2_4 = 16'd1 ,
parameter conv_w_3_0 = 16'd1 ,
parameter conv_w_3_1 = 16'd1 ,
parameter conv_w_3_2 = 16'd1 ,
parameter conv_w_3_3 = 16'd1 ,
parameter conv_w_3_4 = 16'd1 ,
parameter conv_w_4_0 = 16'd1 ,
parameter conv_w_4_1 = 16'd1 ,
parameter conv_w_4_2 = 16'd1 ,
parameter conv_w_4_3 = 16'd1 ,
parameter conv_w_4_4 = 16'd1 ,
parameter conv_b = 16'd1*/
parameter conv_w_0_0 = 16'd1 ,
parameter conv_w_0_1 = 16'd2 ,
parameter conv_w_0_2 = 16'd3 ,
parameter conv_w_0_3 = 16'd4 ,
parameter conv_w_0_4 = 16'd5 ,
parameter conv_w_1_0 = 16'd6 ,
parameter conv_w_1_1 = 16'd7 ,
parameter conv_w_1_2 = 16'd8 ,
parameter conv_w_1_3 = 16'd9 ,
parameter conv_w_1_4 = 16'd10 ,
parameter conv_w_2_0 = 16'd11 ,
parameter conv_w_2_1 = 16'd12 ,
parameter conv_w_2_2 = 16'd13 ,
parameter conv_w_2_3 = 16'd14 ,
parameter conv_w_2_4 = 16'd15 ,
parameter conv_w_3_0 = 16'd16 ,
parameter conv_w_3_1 = 16'd17 ,
parameter conv_w_3_2 = 16'd18 ,
parameter conv_w_3_3 = 16'd19 ,
parameter conv_w_3_4 = 16'd20 ,
parameter conv_w_4_0 = 16'd21 ,
parameter conv_w_4_1 = 16'd22 ,
parameter conv_w_4_2 = 16'd23 ,
parameter conv_w_4_3 = 16'd24 ,
parameter conv_w_4_4 = 16'd25 ,
parameter conv_b = 16'b1
)
(
input clk ,
input rst_n ,
input signed [15:0] data_pic ,
input pic_valid ,
output reg out_valid ,
output reg signed [32:0] data_out
);
wire signed [15:0] row1_out ;
wire signed [15:0] row2_out ;
wire signed [15:0] row3_out ;
wire signed [15:0] row4_out ;
wire signed [23:0] out_reg [24:0] ;
wire signed [32:0] data_out_reg ;
reg out_valid_flag ;
reg [4:0] conv_cnt ;
reg work_en_conv ;
reg [ 9:0] count ;
reg signed [15:0] win_conv [24:0] ;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
count <= 10'b0;
else if (count == 10'd784)
count <= 10'd784;
else if (work_en_conv)
count <= count + 1'b1;
else
count <= count;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
work_en_conv <= 1'b0;
else if (count == 10'd784)
work_en_conv <= 1'd0;
else if (pic_valid)
work_en_conv <= 1'b1;
else
work_en_conv <= work_en_conv;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
conv_cnt <= 5'b0;
else if (conv_cnt == 5'd28 && work_en_conv && count >= 10'd112 && count <= 10'd783)
conv_cnt <= 5'b1;
else if (work_en_conv && count >= 10'd112 && count <= 10'd783)
conv_cnt <= conv_cnt + 1'b1;
else
conv_cnt <= 5'b0;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)begin
win_conv[ 0] <= 16'd0;
win_conv[ 1] <= 16'd0;
win_conv[ 2] <= 16'd0;
win_conv[ 3] <= 16'd0;
win_conv[ 4] <= 16'd0;
win_conv[ 5] <= 16'd0;
win_conv[ 6] <= 16'd0;
win_conv[ 7] <= 16'd0;
win_conv[ 8] <= 16'd0;
win_conv[ 9] <= 16'd0;
win_conv[10] <= 16'd0;
win_conv[11] <= 16'd0;
win_conv[12] <= 16'd0;
win_conv[13] <= 16'd0;
win_conv[14] <= 16'd0;
win_conv[15] <= 16'd0;
win_conv[16] <= 16'd0;
win_conv[17] <= 16'd0;
win_conv[18] <= 16'd0;
win_conv[19] <= 16'd0;
win_conv[20] <= 16'd0;
win_conv[21] <= 16'd0;
win_conv[22] <= 16'd0;
win_conv[23] <= 16'd0;
win_conv[24] <= 16'd0;
end
else if (count >= 10'd112 && count <= 10'd783)begin
win_conv[ 0] <= row4_out;
win_conv[ 1] <= row3_out;
win_conv[ 2] <= row2_out;
win_conv[ 3] <= row1_out;
win_conv[ 4] <= data_pic;
win_conv[ 5] <= win_conv[ 0];
win_conv[ 6] <= win_conv[ 1];
win_conv[ 7] <= win_conv[ 2];
win_conv[ 8] <= win_conv[ 3];
win_conv[ 9] <= win_conv[ 4];
win_conv[10] <= win_conv[ 5];
win_conv[11] <= win_conv[ 6];
win_conv[12] <= win_conv[ 7];
win_conv[13] <= win_conv[ 8];
win_conv[14] <= win_conv[ 9];
win_conv[15] <= win_conv[10];
win_conv[16] <= win_conv[11];
win_conv[17] <= win_conv[12];
win_conv[18] <= win_conv[13];
win_conv[19] <= win_conv[14];
win_conv[20] <= win_conv[15];
win_conv[21] <= win_conv[16];
win_conv[22] <= win_conv[17];
win_conv[23] <= win_conv[18];
win_conv[24] <= win_conv[19];
end
else begin
win_conv[ 0] <= win_conv[ 0];
win_conv[ 1] <= win_conv[ 1];
win_conv[ 2] <= win_conv[ 2];
win_conv[ 3] <= win_conv[ 3];
win_conv[ 4] <= win_conv[ 4];
win_conv[ 5] <= win_conv[ 5];
win_conv[ 6] <= win_conv[ 6];
win_conv[ 7] <= win_conv[ 7];
win_conv[ 8] <= win_conv[ 8];
win_conv[ 9] <= win_conv[ 9];
win_conv[10] <= win_conv[10];
win_conv[11] <= win_conv[11];
win_conv[12] <= win_conv[12];
win_conv[13] <= win_conv[13];
win_conv[14] <= win_conv[14];
win_conv[15] <= win_conv[15];
win_conv[16] <= win_conv[16];
win_conv[17] <= win_conv[17];
win_conv[18] <= win_conv[18];
win_conv[19] <= win_conv[19];
win_conv[20] <= win_conv[20];
win_conv[21] <= win_conv[21];
win_conv[22] <= win_conv[22];
win_conv[23] <= win_conv[23];
win_conv[24] <= win_conv[24];
end
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
data_out <= 33'b0;
else if (out_valid_flag)
data_out <= data_out_reg;
else
data_out <= 33'b0;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
out_valid <= 1'b0;
else if (out_valid_flag)
out_valid <= 1'b1;
else
out_valid <= 1'b0;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
out_valid_flag <= 1'b0;
else if (count >= 10'd112 && conv_cnt >= 5'd5 && conv_cnt <= 5'd28)
out_valid_flag <= 1'b1;
else
out_valid_flag <= 1'b0;
end
assign data_out_reg = out_reg[0] + out_reg[1] + out_reg[2] + out_reg[3] + out_reg[4] + out_reg[5] + out_reg[6] + out_reg[7] + out_reg[8] + out_reg[9] + out_reg[10] + out_reg[11] + out_reg[12] + out_reg[13] + out_reg[14] + out_reg[15] + out_reg[16] + out_reg[17] + out_reg[18] + out_reg[19] + out_reg[20] + out_reg[21] + out_reg[22] + out_reg[23] + out_reg[24] + conv_b;
shift_ram_conv_5_5 row1(
.CLK (clk ),
.D (data_pic ),
.CE (work_en_conv ),
.Q (row1_out )
);
shift_ram_conv_5_5 row2(
.CLK (clk ),
.D (row1_out ),
.CE (work_en_conv ),
.Q (row2_out )
);
shift_ram_conv_5_5 row3(
.CLK (clk ),
.D (row2_out ),
.CE (work_en_conv ),
.Q (row3_out )
);
shift_ram_conv_5_5 row4(
.CLK (clk ),
.D (row3_out ),
.CE (work_en_conv ),
.Q (row4_out )
);
//column 0
mult_16 mult0_4(
.CLK (clk ),
.A (conv_w_0_4 ),
.B (win_conv[ 0] ),
.P (out_reg[ 0] )
);
mult_16 mult1_4(
.CLK (clk ),
.A (conv_w_1_4 ),
.B (win_conv[ 1] ),
.P (out_reg[ 1] )
);
mult_16 mult2_4(
.CLK (clk ),
.A (conv_w_2_4 ),
.B (win_conv[ 2] ),
.P (out_reg[ 2] )
);
mult_16 mult3_4(
.CLK (clk ),
.A (conv_w_3_4 ),
.B (win_conv[ 3] ),
.P (out_reg[ 3] )
);
mult_16 mult4_4(
.CLK (clk ),
.A (conv_w_4_4 ),
.B (win_conv[ 4] ),
.P (out_reg[ 4] )
);
// column 1
mult_16 mult0_3(
.CLK (clk ),
.A (conv_w_0_3 ),
.B (win_conv[ 5] ),
.P (out_reg[ 5] )
);
mult_16 mult1_3(
.CLK (clk ),
.A (conv_w_1_3 ),
.B (win_conv[ 6] ),
.P (out_reg[ 6] )
);
mult_16 mult2_3(
.CLK (clk ),
.A (conv_w_2_3 ),
.B (win_conv[ 7] ),
.P (out_reg[ 7] )
);
mult_16 mult3_3(
.CLK (clk ),
.A (conv_w_3_3 ),
.B (win_conv[ 8] ),
.P (out_reg[ 8] )
);
mult_16 mult4_3(
.CLK (clk ),
.A (conv_w_4_3 ),
.B (win_conv[ 9] ),
.P (out_reg[ 9] )
);
//column 2
mult_16 mult0_2(
.CLK (clk ),
.A (conv_w_0_2 ),
.B (win_conv[10] ),
.P (out_reg[10] )
);
mult_16 mult1_2(
.CLK (clk ),
.A (conv_w_1_2 ),
.B (win_conv[11] ),
.P (out_reg[11] )
);
mult_16 mult2_2(
.CLK (clk ),
.A (conv_w_2_2 ),
.B (win_conv[12] ),
.P (out_reg[12] )
);
mult_16 mult3_2(
.CLK (clk ),
.A (conv_w_3_2 ),
.B (win_conv[13] ),
.P (out_reg[13] )
);
mult_16 mult4_2(
.CLK (clk ),
.A (conv_w_4_2 ),
.B (win_conv[14] ),
.P (out_reg[14] )
);
// column 3
mult_16 mult0_1(
.CLK (clk ),
.A (conv_w_0_1 ),
.B (win_conv[15] ),
.P (out_reg[15] )
);
mult_16 mult1_1(
.CLK (clk ),
.A (conv_w_1_1 ),
.B (win_conv[16] ),
.P (out_reg[16] )
);
mult_16 mult2_1(
.CLK (clk ),
.A (conv_w_2_1 ),
.B (win_conv[17] ),
.P (out_reg[17] )
);
mult_16 mult3_1(
.CLK (clk ),
.A (conv_w_3_1 ),
.B (win_conv[18] ),
.P (out_reg[18] )
);
mult_16 mult4_1(
.CLK (clk ),
.A (conv_w_4_1 ),
.B (win_conv[19] ),
.P (out_reg[19] )
);
// column 4
mult_16 mult0_0(
.CLK (clk ),
.A (conv_w_0_0 ),
.B (win_conv[20] ),
.P (out_reg[20] )
);
mult_16 mult1_0(
.CLK (clk ),
.A (conv_w_1_0 ),
.B (win_conv[21] ),
.P (out_reg[21] )
);
mult_16 mult2_0(
.CLK (clk ),
.A (conv_w_2_0 ),
.B (win_conv[22] ),
.P (out_reg[22] )
);
mult_16 mult3_0(
.CLK (clk ),
.A (conv_w_3_0 ),
.B (win_conv[23] ),
.P (out_reg[23] )
);
mult_16 mult4_0(
.CLK (clk ),
.A (conv_w_4_0 ),
.B (win_conv[24] ),
.P (out_reg[24] )
);
endmodule |
module maxpooling(
input clk ,
input rst_n ,
input valid_input ,
input [32:0] input_data ,
output out_valid ,
output [32:0] out_data
);
reg [ 9:0] count ;
reg [ 4:0] max_cnt ;
reg out_flag ;
wire [32:0] ram_reg ;
wire [32:0] max_col_1_reg ;
wire [32:0] max_col_2_reg ;
reg [32:0] win_pool [3:0] ;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
count <= 10'd0;
else if (valid_input)
count <= count + 1'b1;
else
count <= count;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
max_cnt <= 5'd0;
else if (count >= 10'd25 && count <= 10'd576 && max_cnt == 5'd24)
max_cnt <= 5'd1;
else if (count >= 10'd25 && count <= 10'd576)
max_cnt <= max_cnt + 1'b1;
else
max_cnt <= max_cnt;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
out_flag <= 1'd0;
else if (max_cnt >= 5'd1 && max_cnt <= 5'd23)
out_flag <= ~ out_flag;
else
out_flag <= 1'b0;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)begin
win_pool[0] <= 32'd0;
win_pool[1] <= 32'd0;
win_pool[2] <= 32'd0;
win_pool[3] <= 32'd0;
end
else if (count >= 10'd24 && count <= 10'd576)begin
win_pool[0] <= ram_reg;
win_pool[1] <= input_data;
win_pool[2] <= win_pool[0];
win_pool[3] <= win_pool[1];
end
else begin
win_pool[0] <= win_pool[0];
win_pool[1] <= win_pool[1];
win_pool[2] <= win_pool[2];
win_pool[3] <= win_pool[3];
end
end
assign max_col_1_reg = win_pool[0] > win_pool[1] ? win_pool[0] : win_pool[1];
assign max_col_2_reg = win_pool[2] > win_pool[3] ? win_pool[2] : win_pool[3];
assign out_data = out_valid == 1'b0 ? 32'd0 : max_col_2_reg > max_col_1_reg ? max_col_2_reg : max_col_1_reg;
assign out_valid = count >= 10'd24 && max_cnt >= 5'd2 && max_cnt <=5'd24 && out_flag ? 1'b1 : 1'b0;
data_fifo fifo_inst(
.CLK (clk ),
.D (input_data ),
.CE (valid_input),
.Q (ram_reg )
);
endmodule |
module rainbow_generate(
input clk ,
input rst_n ,
input [ 9:0] x_pix ,
input [ 9:0] y_pix ,
output reg [23:0] data
);
parameter red = 24'hFF0000;
parameter green = 24'h00FF00;
parameter blue = 24'h0000FF;
parameter purple = 24'h9B30FF;
parameter yellow = 24'hFFFF00;
parameter cyan = 24'h00FFFF;
parameter orange = 24'hFFA500;
parameter white = 24'hFFFFFF;
parameter bar_wide = 10'd640 / 10'd8;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data <= 24'b0;
end
else begin
if(x_pix < bar_wide * 11'd1)
data <= red;
else if(x_pix < bar_wide * 11'd2)
data <= green;
else if(x_pix < bar_wide * 11'd3)
data <= blue;
else if(x_pix < bar_wide * 11'd4)
data <= purple;
else if(x_pix < bar_wide * 11'd5)
data <= yellow;
else if(x_pix < bar_wide * 11'd6)
data <= cyan;
else if(x_pix < bar_wide * 11'd7)
data <= orange;
else
data <= white;
end
end
endmodule |
module relu(
input [32:0] A ,
output [32:0] B
);
assign B = A[32] == 1'b0 ? A : 33'b0;
endmodule |
module vga_top(
input sys_clk ,
input sys_rst_n ,
output hs ,
output vs ,
output clk_25MHz ,
output [23:0] color_rgb
);
wire [ 9:0] x_pix ;
wire [ 9:0] y_pix ;
wire [23:0] data ;
vga vga_inst(
.clk (clk_25MHz ),
.rst_n (sys_rst_n ),
.data (data ),
.hs (hs ),
.vs (vs ),
.x_pix (x_pix ),
.y_pix (y_pix ),
.color_rgb (color_rgb )
);
rainbow_generate inst(
.clk (clk_25MHz ),
.rst_n (sys_rst_n ),
.x_pix (x_pix ),
.y_pix (y_pix ),
.data (data )
);
PLL_25MHz clk_25MHz_generate(
.refclk (sys_clk ),
.rst (~sys_rst_n ),
.outclk_0 (clk_25MHz ),
.locked (locked )
);
endmodule |
module max_data_generate(
input clk ,
input rst_n ,
input data_start ,
output data_out_valid ,
output [32:0] data_out
);
wire [32:0] data_out_out ;
reg [32:0] data_out_reg ;
reg [ 9:0] addr ;
reg work_en ;
reg data_out_valid_reg ;
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
data_out_reg <= 16'b0;
else if (data_out_out)
data_out_reg <= data_out_out;
else
data_out_reg <= data_out_reg;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
data_out_valid_reg <= 1'b0;
else if (work_en && addr == 9'd1)
data_out_valid_reg <= 1'b1;
else if (addr == 10'd576)
data_out_valid_reg <= 1'b0;
else
data_out_valid_reg <= data_out_valid_reg;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
addr <= 10'b0;
else if (work_en && addr == 10'd576)
addr <= 10'd576;
else if (work_en)
addr <= addr + 1'b1;
else
addr <= addr;
end
always @ (posedge clk or negedge rst_n)begin
if (!rst_n)
work_en <= 1'b0;
else if (data_start)
work_en <= 1'b1;
else if (addr == 10'd576)
work_en <= 1'b0;
end
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
rom_max_data rom_max_data(
.clka (clk ),
.addra (addr ),
.douta (data_out_out )
);
endmodule |
module top;
reg clk = 1;
reg tick_60hz = 0;
reg [15:0] keys = 0;
wire out;
cpu cpu0(.clk(clk),
.tick_60hz(tick_60hz),
.tick_next(1'b1),
.keys(keys),
.out(out),
.scr_busy(1'b0),
.scr_read(1'b0));
initial
forever #1 clk = ~clk;
initial
forever begin
#98 tick_60hz = 1;
#2 tick_60hz = 0;
end
initial utils.timeout(10000);
task reset;
integer i;
begin
for (i = 0; i < 'h1000; i++)
cpu0.mem0.data[i] = 0;
$readmemh("font.hex", cpu0.mem0.data, 'h030, 'h07f);
cpu0.addr = 0;
cpu0.pc = 'h200;
cpu0.dt = 0;
cpu0.st = 0;
cpu0.state = cpu0.STATE_NEXT;
end
endtask
integer i;
`define run(name) \
$display("Running %s", name); \
reset; \
$readmemh(name, cpu0.mem0.data, 'h200, 'hFFF); \
wait (cpu0.state == cpu0.STATE_STOP);
initial begin
$dumpfile(`VCD_FILE);
$dumpvars;
`run("build/test_jump.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
`run("build/test_call.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
`run("build/test_add.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
`run("build/test_mem.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
`run("build/test_jump_v0.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
keys <= 'b10101010;
`run("build/test_keys.hex");
keys <= 'b00000000;
utils.assert_equal(cpu0.mem0.data['h020], 'b10101010);
`run("build/test_screen.hex");
for (i = 'h100; i < 'h200; i++)
utils.assert_equal(cpu0.mem0.data[i], 0);
`run("build/test_drw.hex");
utils.assert_equal(cpu0.mem0.data['h138], 'b00100000);
utils.assert_equal(cpu0.mem0.data['h140], 'b01100000);
utils.assert_equal(cpu0.mem0.data['h148], 'b00100000);
utils.assert_equal(cpu0.mem0.data['h150], 'b00100000);
utils.assert_equal(cpu0.mem0.data['h158], 'b01110000);
utils.assert_equal({cpu0.mem0.data['h110], cpu0.mem0.data['h111]}, 'b00110000_00110000);
utils.assert_equal({cpu0.mem0.data['h118], cpu0.mem0.data['h119]}, 'b00111100_11110000);
utils.assert_equal({cpu0.mem0.data['h120], cpu0.mem0.data['h121]}, 'b00111100_11110000);
utils.assert_equal({cpu0.mem0.data['h128], cpu0.mem0.data['h129]}, 'b00111100_11110000);
utils.assert_equal({cpu0.mem0.data['h130], cpu0.mem0.data['h131]}, 'b00110000_00110000);
// collision
utils.assert_equal(cpu0.mem0.data['h02f], 1);
`run("build/test_bcd.hex");
utils.assert_equal(cpu0.mem0.data['h020], 'h42);
// This program should wait 5 ticks
i = $time;
`run("build/test_timers.hex");
utils.assert_equal(($time - i) / 100, 5);
utils.assert_equal(out, 1);
$finish;
end
endmodule // Top |
module cpu(input wire clk,
input wire tick_60hz,
input wire tick_next,
input wire [15:0] keys,
output wire out,
input wire scr_busy,
input wire scr_read,
input wire [7:0] scr_read_idx,
output reg [7:0] scr_read_byte,
output reg scr_read_ack);
assign out = st != 0;
// Press 0 + F to activate debug mode
wire debug_mode = (keys == 16'b1000_0000_0000_0010);
// Memory map:
// 000..01F: stack (16 x 2 bytes)
// 020..02F: registers (16 x 1 byte)
// 030..07F: font (16 x 5 bytes)
// 100..1FF: screen (32 lines x 8 bytes)
// Memory
reg mem_read = 0;
reg [11:0] mem_read_idx;
wire [7:0] mem_read_byte;
wire mem_read_ack;
reg mem_write = 0;
reg [11:0] mem_write_idx;
reg [7:0] mem_write_byte;
mem mem0(clk,
mem_read, mem_read_idx, mem_read_byte, mem_read_ack,
mem_write, mem_write_idx, mem_write_byte);
localparam
STATE_NEXT = 0,
STATE_FETCH_HI = 1,
STATE_FETCH_LO = 2,
STATE_POP_HI = 3,
STATE_POP_LO = 4,
STATE_PUSH_HI = 5,
STATE_PUSH_LO = 6,
STATE_DECODE = 7,
STATE_TRANSFER_LOAD = 8,
STATE_TRANSFER_STORE = 9,
STATE_CLEAR = 10,
STATE_LOAD_VX = 11,
STATE_LOAD_VY = 12,
STATE_LOAD_V0 = 13,
STATE_STORE_VX = 14,
STATE_STORE_CARRY = 15,
STATE_BCD_1 = 16,
STATE_BCD_2 = 17,
STATE_BCD_3 = 18,
STATE_GPU = 19,
// ...
STATE_STOP = 31;
reg[4:0] state = STATE_NEXT;
// BCD
wire [1:0] bcd_1;
wire [3:0] bcd_2, bcd_3;
bcd bcd0(vx, bcd_1, bcd_2, bcd_3);
// GPU
reg gpu_draw = 0;
reg [11:0] gpu_addr;
reg [3:0] gpu_lines;
reg [5:0] gpu_x;
reg [4:0] gpu_y;
wire gpu_busy;
wire gpu_collision;
wire gpu_read;
wire [11:0] gpu_read_idx;
wire gpu_write;
wire [11:0] gpu_write_idx;
wire [7:0] gpu_write_byte;
gpu gpu0(.clk(clk),
.draw(gpu_draw),
.addr(gpu_addr),
.lines(gpu_lines),
.x(gpu_x),
.y(gpu_y),
.busy(gpu_busy),
.collision(gpu_collision),
.mem_read(gpu_read),
.mem_read_idx(gpu_read_idx),
.mem_read_byte(mem_read_byte), // pass-through
.mem_read_ack(mem_read_ack), // pass-through
.mem_write(gpu_write),
.mem_write_idx(gpu_write_idx),
.mem_write_byte(gpu_write_byte));
// Memory loads and stores
always @(*) begin
mem_read = 0;
mem_write = 0;
mem_read_idx = 0;
case (state)
STATE_NEXT, STATE_STOP: begin
mem_read = scr_read;
mem_read_idx = {4'h1, scr_read_idx};
if (debug_mode) begin
if (scr_read_idx < 'h30)
// Show stack and registers
mem_read_idx = {4'h0, scr_read_idx};
else
// Show beginning of program memory
mem_read_idx = {4'h2, scr_read_idx - 8'h30};
end
end
STATE_FETCH_HI: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = pc[11:0];
end
STATE_FETCH_LO: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = pc[11:0] + 1;
end
STATE_LOAD_VX: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = 'h20 + {8'b0, x};
end
STATE_LOAD_VY: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = 'h20 + {8'b0, y};
end
STATE_LOAD_V0: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = 'h20;
end
STATE_POP_HI: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = 2 * sp;
end
STATE_POP_LO: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = 2 * sp + 1;
end
STATE_PUSH_HI: begin
mem_write = 1;
mem_write_idx = 2 * sp - 2;
mem_write_byte = {4'b0, ret_pc[11:8]};
end
STATE_PUSH_LO: begin
mem_write = 1;
mem_write_idx = 2 * sp - 1;
mem_write_byte = ret_pc[7:0];
end
STATE_TRANSFER_LOAD: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = transfer_src_addr + {4'b0, transfer_counter};
end
STATE_TRANSFER_STORE: begin
mem_write = 1;
mem_write_idx = transfer_dest_addr + {4'b0, transfer_counter};
mem_write_byte = mem_read_byte;
end
STATE_CLEAR: begin
mem_write = 1;
mem_write_idx = transfer_dest_addr + {4'b0, transfer_counter};
mem_write_byte = 0;
end
STATE_STORE_VX: begin
mem_write = 1;
mem_write_idx = 'h20 + {8'b0, x};
mem_write_byte = new_vx;
end
STATE_STORE_CARRY: begin
mem_write = 1;
mem_write_idx = 'h2F;
mem_write_byte = {7'b0, carry};
end
STATE_BCD_1: begin
mem_write = 1;
mem_write_idx = addr;
mem_write_byte = {6'b0, bcd_1};
end
STATE_BCD_2: begin
mem_write = 1;
mem_write_idx = addr + 1;
mem_write_byte = {4'b0, bcd_2};
end
STATE_BCD_3: begin
mem_write = 1;
mem_write_idx = addr + 2;
mem_write_byte = {4'b0, bcd_3};
end
STATE_GPU: begin
mem_read = gpu_read;
mem_read_idx = gpu_read_idx;
mem_write = gpu_write;
mem_write_idx = gpu_write_idx;
mem_write_byte = gpu_write_byte;
end
endcase
end
// Registers
reg [11:0] pc = 'h200;
reg [11:0] ret_pc;
reg [11:0] addr = 0;
reg [11:0] transfer_src_addr, transfer_dest_addr;
reg [7:0] transfer_counter;
reg [3:0] sp = 0;
reg [7:0] dt = 0;
reg [7:0] st = 0;
// Instruction
reg [15:0] instr;
wire [3:0] a = instr[15:12];
wire [3:0] x = instr[11:8];
wire [3:0] y = instr[7:4];
wire [3:0] z = instr[3:0];
wire [7:0] yz = instr[7:0];
wire [11:0] xyz = instr[11:0];
reg [7:0] vx, vy, new_vx;
reg carry;
wire needs_carry = a == 'h8 && (z == 'h4 || z == 'h5 || z == 'h6 || z == 'h7 || z == 'hE);
// Can go to the next instruction (for rate limiting by tick_next)
reg next = 1;
wire [31:0] rng_state;
rng rng(.clk(clk), .out(rng_state), .user_input(&keys));
integer i;
always @(posedge clk) begin
if (tick_60hz) begin
$display($time, " tick, dt = %x st = %x", dt, st);
if (dt != 0)
dt <= dt - 1;
if (st != 0)
st <= st - 1;
end
if (tick_next)
next <= 1;
scr_read_ack <= 0;
case (state)
STATE_NEXT, STATE_STOP: begin
if (scr_read && mem_read_ack) begin
scr_read_ack <= 1;
scr_read_byte <= mem_read_byte;
end
if (state == STATE_NEXT && !scr_busy && next) begin
next <= 0;
state <= STATE_FETCH_HI;
end
end
STATE_FETCH_HI:
if (mem_read_ack) begin
instr[15:8] <= mem_read_byte;
state <= STATE_FETCH_LO;
end
STATE_FETCH_LO:
if (mem_read_ack) begin
instr[7:0] <= mem_read_byte;
if (a == 'hB)
// JP V0, xyz
state <= STATE_LOAD_V0;
else
// TODO check if necessary?
state <= STATE_LOAD_VX;
end
STATE_LOAD_VX:
if (mem_read_ack) begin
vx <= mem_read_byte;
// TODO check if necessary?
state <= STATE_LOAD_VY;
end
STATE_LOAD_VY:
if (mem_read_ack) begin
vy <= mem_read_byte;
state <= STATE_DECODE;
end
STATE_LOAD_V0:
if (mem_read_ack) begin
vx <= mem_read_byte;
state <= STATE_DECODE;
end
STATE_STORE_VX:
state <= needs_carry ? STATE_STORE_CARRY : STATE_NEXT;
STATE_STORE_CARRY:
state <= STATE_NEXT;
STATE_POP_HI:
if (mem_read_ack) begin
pc[11:8] <= mem_read_byte[3:0];
state <= STATE_POP_LO;
end
STATE_POP_LO:
if (mem_read_ack) begin
pc[7:0] <= mem_read_byte;
state <= STATE_NEXT;
end
STATE_PUSH_HI:
state <= STATE_PUSH_LO;
STATE_PUSH_LO:
state <= STATE_NEXT;
STATE_TRANSFER_LOAD:
if (mem_read_ack)
state <= STATE_TRANSFER_STORE;
STATE_TRANSFER_STORE:
if (transfer_counter == 0)
state <= STATE_NEXT;
else begin
transfer_counter <= transfer_counter - 1;
state <= STATE_TRANSFER_LOAD;
end
STATE_CLEAR:
if (transfer_counter == 0)
state <= STATE_NEXT;
else begin
transfer_counter <= transfer_counter - 1;
end
STATE_BCD_1:
state <= STATE_BCD_2;
STATE_BCD_2:
state <= STATE_BCD_3;
STATE_BCD_3:
state <= STATE_NEXT;
STATE_GPU:
begin
gpu_draw <= 0;
if (!gpu_draw && !gpu_busy) begin
carry <= gpu_collision;
state <= STATE_STORE_CARRY;
end
end
STATE_DECODE: begin
$display($time, " run [%x] %x", pc, instr);
pc <= pc + 2;
state <= STATE_NEXT;
case (a)
4'h0:
case (xyz)
'h0E0: begin
$display($time, " instr: CLS");
transfer_dest_addr <= 'h100;
transfer_counter <= 'hFF;
state <= STATE_CLEAR;
end
'h0EE: begin
$display($time, " instr: RET");
sp <= sp - 1;
state <= STATE_POP_HI;
end
'h0FD: begin
$display($time, " instr: EXIT");
state <= STATE_STOP;
end
default: begin
$display($time, " instr: NOP");
end
endcase
4'h1: begin
$display($time, " instr: JP %x", xyz);
pc <= xyz;
end
4'h2: begin
$display($time, " instr: CALL %x", xyz);
sp <= sp + 1;
state <= STATE_PUSH_HI;
ret_pc <= pc + 2;
pc <= xyz;
end
4'h3: begin
$display($time, " instr: SE V%x, %x", x, yz);
if (vx == yz)
pc <= pc + 4;
end
4'h4: begin
$display($time, " instr: SNE V%x, %x", x, yz);
if (vx != yz)
pc <= pc + 4;
end
4'h5: begin
$display($time, " instr: SE V%x, V%x", x, y);
if (vx == vy)
pc <= pc + 4;
end
4'h9: begin
$display($time, " instr: SNE V%x, V%x", x, y);
if (vx != vy)
pc <= pc + 4;
end
4'h6: begin
$display($time, " instr: LD V%x, %x", x, yz);
new_vx <= yz;
state <= STATE_STORE_VX;
end
4'h7: begin
$display($time, " instr: ADD V%x, %x", x, yz);
new_vx <= vx + yz;
state <= STATE_STORE_VX;
end
4'h8: begin
case (z)
4'h0: begin
$display($time, " instr: LD V%x, V%x", x, y);
new_vx <= vy;
state <= STATE_STORE_VX;
end
4'h1: begin
$display($time, " instr: OR V%x, V%x", x, y);
new_vx <= vx | vy;
state <= STATE_STORE_VX;
end
4'h2: begin
$display($time, " instr: AND V%x, V%x", x, y);
new_vx <= vx & vy;
state <= STATE_STORE_VX;
end
4'h3: begin
$display($time, " instr: XOR V%x, V%x", x, y);
new_vx <= vx ^ vy;
state <= STATE_STORE_VX;
end
4'h4: begin
$display($time, " instr: ADD V%x, V%x", x, y);
new_vx <= vx + vy;
carry <= ((vx + vy) >= 'h100) ? 1 : 0;
state <= STATE_STORE_VX;
end
4'h5: begin
$display($time, " instr: SUB V%x, V%x", x, y);
new_vx <= vx - vy;
carry <= (vx > vy) ? 1 : 0;
state <= STATE_STORE_VX;
end
4'h6: begin
$display($time, " instr: SHR V%x", x);
new_vx <= vx >> 1;
carry <= vx[0];
state <= STATE_STORE_VX;
end
4'h7: begin
$display($time, " instr: SUBN V%x, V%x", x, y);
new_vx <= vy - vx;
carry <= (vy > vx) ? 1 : 0;
state <= STATE_STORE_VX;
end
4'hE: begin
$display($time, " instr: SHL V%x", x);
new_vx <= vx << 1;
carry <= vx[7];
state <= STATE_STORE_VX;
end
default: ;
endcase
end
4'hA: begin
$display($time, " instr: LD I, %x", xyz);
addr <= xyz;
end
4'hB: begin
$display($time, " instr: JP V0, %x", xyz);
// STATE_LOAD_V0 loaded V0 into vx
pc <= xyz + {4'b0, vx};
end
4'hC: begin
$display($time, " instr: RND V%x, %x", x, yz);
new_vx <= rng_state[15:8] & yz;
state <= STATE_STORE_VX;
end
4'hD: begin
$display($time, " instr: DRW V%x, V%x, %x", x, y, z);
gpu_draw <= 1;
gpu_addr <= addr;
gpu_lines <= z;
gpu_x <= vx[5:0];
gpu_y <= vy[4:0];
state <= STATE_GPU;
end
4'hE: begin
case (yz)
8'h9E: begin
$display($time, " instr: SKP V%x", x);
// In debug mode, assume no keys are pressed.
if (!debug_mode && keys[vx[3:0]])
pc <= pc + 4;
end
8'hA1: begin
$display($time, " instr: SKNP V%x", x);
// In debug mode, assume no keys are pressed.
if (debug_mode || !keys[vx[3:0]])
pc <= pc + 4;
end
default: ;
endcase
end
4'hF: begin
case (yz)
8'h07: begin
$display($time, " instr: LD V%x, DT", x);
new_vx <= dt;
state <= STATE_STORE_VX;
end
8'h0A: begin
$display($time, " instr: LD V%x, K", x);
if (keys == 0)
pc <= pc;
else begin
for (i = 15; i >= 0; i--)
if (keys[i])
vx <= i[7:0];
end
end
8'h15: begin
$display($time, " instr: LD DT, V%x", x);
dt <= vx;
end
8'h18: begin
$display($time, " instr: LD ST, V%x", x);
st <= vx;
end
8'h1E: begin
$display($time, " instr: ADD I, V%x", x);
addr <= addr + {4'b0, vx};
end
8'h29: begin
$display($time, " instr: LD F, V%x", x);
addr <= 'h30 + vx * 5;
end
8'h33: begin
$display($time, " instr: LD B, V%x", x);
state <= STATE_BCD_1;
end
8'h55: begin
$display($time, " instr: LD [I], V%x", x);
transfer_src_addr <= 'h020;
transfer_dest_addr <= addr;
transfer_counter <= {4'b0, x};
state <= STATE_TRANSFER_LOAD;
end
8'h65: begin
$display($time, " instr: LD V%x, [I]", x);
transfer_src_addr <= addr;
transfer_dest_addr <= 'h020;
transfer_counter <= {4'b0, x};
state <= STATE_TRANSFER_LOAD;
end
default: ;
endcase
end
endcase
end
endcase
end
endmodule |
module gpu(input wire clk,
input wire draw,
input wire [11:0] addr,
input wire [3:0] lines,
input wire [5:0] x,
input wire [4:0] y,
output wire busy,
output reg collision,
output reg mem_read,
output reg [11:0] mem_read_idx,
input wire [7:0] mem_read_byte,
input wire mem_read_ack,
output reg mem_write,
output reg [11:0] mem_write_idx,
output reg [7:0] mem_write_byte);
localparam WIDTH = 8;
localparam
STATE_IDLE = 0,
STATE_LOAD_SPRITE = 1,
STATE_LOAD_MEM_LEFT = 2,
STATE_STORE_MEM_LEFT = 3,
STATE_LOAD_MEM_RIGHT = 4,
STATE_STORE_MEM_RIGHT = 5;
reg [3:0] lines_left;
reg [3:0] shift;
reg use_right;
reg [11:0] sprite_addr;
reg [7:0] screen_addr;
reg [15:0] sprite_word;
reg [7:0] screen_byte;
wire [11:0] mem_idx_left = {4'h1, screen_addr};
// Wrap the last 3 bits to wrap a line correctly (a line is 8 bytes)
wire [11:0] mem_idx_right = {4'h1, screen_addr[7:3], screen_addr[2:0] + 1'b1};
reg [3:0] state = STATE_IDLE;
assign busy = state != STATE_IDLE;
// Memory access
always @(*) begin
mem_read = 0;
mem_read_idx = 0;
mem_write = 0;
mem_write_idx = 0;
mem_write_byte = 0;
case (state)
STATE_LOAD_SPRITE: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = sprite_addr;
end
STATE_LOAD_MEM_LEFT: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = mem_idx_left;
end
STATE_LOAD_MEM_RIGHT: if (!mem_read_ack) begin
mem_read = 1;
mem_read_idx = mem_idx_right;
end
STATE_STORE_MEM_LEFT: begin
mem_write = 1;
mem_write_idx = mem_idx_left;
mem_write_byte = screen_byte;
$display($time, " gpu: [%x] = %b", mem_idx_left, screen_byte);
end
STATE_STORE_MEM_RIGHT:
if (use_right) begin
mem_write = 1;
mem_write_idx = mem_idx_right;
mem_write_byte = screen_byte;
$display($time, " gpu: [%x] = %b", mem_idx_right, screen_byte);
end
endcase
end
always @(posedge clk)
case (state)
STATE_IDLE:
if (draw) begin
$display($time, " gpu: draw %x (%x lines) at (%x, %x)",
addr, lines, x, y);
lines_left <= lines - 1;
sprite_addr <= addr;
screen_addr <= y * WIDTH + x / 8;
shift <= x % 8;
use_right <= (x % 8 != 0);
collision <= 0;
state <= STATE_LOAD_SPRITE;
end
STATE_LOAD_SPRITE:
if (mem_read_ack) begin
sprite_word <= {mem_read_byte, 8'b0} >> shift;
state <= STATE_LOAD_MEM_LEFT;
end
STATE_LOAD_MEM_LEFT:
if (mem_read_ack) begin
screen_byte <= mem_read_byte ^ sprite_word[15:8];
collision <= collision | |(mem_read_byte & sprite_word[15:8]);
state <= STATE_STORE_MEM_LEFT;
end
STATE_STORE_MEM_LEFT:
state <= STATE_LOAD_MEM_RIGHT;
STATE_LOAD_MEM_RIGHT:
if (mem_read_ack) begin
if (use_right) begin
screen_byte <= mem_read_byte ^ sprite_word[7:0];
collision <= collision | |(mem_read_byte & sprite_word[7:0]);
end
state <= STATE_STORE_MEM_RIGHT;
end
STATE_STORE_MEM_RIGHT:
if (lines_left == 0)
state <= STATE_IDLE;
else begin
sprite_addr <= sprite_addr + 1;
screen_addr <= screen_addr + WIDTH;
lines_left <= lines_left - 1;
state <= STATE_LOAD_SPRITE;
end
endcase
endmodule |
module screen_bridge(input wire clk,
input wire tick_60hz,
input wire read,
input wire [5:0] row_idx,
input wire [6:0] column_idx,
output reg [7:0] data,
output reg ack,
output wire scr_busy,
output wire scr_read,
output wire [7:0] scr_read_idx,
input wire [7:0] scr_read_byte,
input wire scr_read_ack);
reg [7:0] buffer [0:1023];
wire [9:0] buffer_read_idx = {row_idx[2:0], column_idx};
// 8 x 4 rectangle (scanned in horizontal stripes, output in vertical ones)
reg [7:0] rect [0:3];
// Num of rectangle on screen
reg [5:0] rect_num = 0;
// Index of byte (horizontal stripe) in rectangle
reg [1:0] rect_scan_idx = 0;
// Index of vertical stripe in rectangle (16 double-pixel stripes)
reg [3:0] rect_write_idx = 0;
assign scr_read = state == STATE_READ_RECT && !scr_read_ack;
assign scr_read_idx = {rect_num[5:3], rect_scan_idx, rect_num[2:0]};
wire [9:0] buffer_write_idx = {rect_num, rect_write_idx};
wire [7:0] buffer_write_byte = {rect[3][7], rect[3][7],
rect[2][7], rect[2][7],
rect[1][7], rect[1][7],
rect[0][7], rect[0][7]};
localparam
STATE_READ_RECT = 0,
STATE_WRITE_RECT = 1,
STATE_WAIT = 2;
assign scr_busy = state != STATE_WAIT;
reg [1:0] state = STATE_READ_RECT;
reg draw_next = 0;
always @(posedge clk) begin
if (tick_60hz)
draw_next <= 1;
ack <= 0;
if (read) begin
ack <= 1;
data <= buffer[buffer_read_idx];
end
case (state)
STATE_READ_RECT: begin
if (scr_read_ack) begin
rect[rect_scan_idx] <= scr_read_byte;
rect_scan_idx <= rect_scan_idx + 1;
if (rect_scan_idx == 'b11) begin
state <= STATE_WRITE_RECT;
end
end
end
STATE_WRITE_RECT: begin
buffer[buffer_write_idx] <= buffer_write_byte;
rect_write_idx <= rect_write_idx + 1;
if (rect_write_idx[0]) begin
rect[0] <= rect[0] << 1;
rect[1] <= rect[1] << 1;
rect[2] <= rect[2] << 1;
rect[3] <= rect[3] << 1;
end
if (rect_write_idx == 'b1111) begin
rect_num <= rect_num + 1;
if (rect_num == 'b111111)
state <= STATE_WAIT;
else
state <= STATE_READ_RECT;
end
end
STATE_WAIT:
if (draw_next) begin
draw_next <= 0;
state <= STATE_READ_RECT;
end
endcase
end
endmodule |
module top;
reg clk = 1;
reg draw = 0;
reg [11:0] addr;
reg [3:0] lines;
reg [5:0] x;
reg [4:0] y;
wire busy, collision;
wire mem_read;
wire [11:0] mem_read_idx;
wire [7:0] mem_read_byte;
wire mem_read_ack;
wire mem_write;
wire [11:0] mem_write_idx;
wire [7:0] mem_write_byte;
mem #(.debug(1))
mem0(clk,
mem_read,
mem_read_idx,
mem_read_byte,
mem_read_ack,
mem_write,
mem_write_idx,
mem_write_byte);
gpu gpu0(clk,
draw, addr, lines, x, y,
busy, collision,
mem_read, mem_read_idx, mem_read_byte, mem_read_ack,
mem_write, mem_write_idx, mem_write_byte);
initial
forever #1 clk = ~clk;
initial utils.timeout(10000);
integer i;
initial begin
for (i = 100; i < 'h300; i++)
mem0.data[i] = 0;
mem0.data['h42] = 'b11111111;
mem0.data['h43] = 'b11000011;
mem0.data['h44] = 'b11000011;
mem0.data['h45] = 'b11000011;
mem0.data['h46] = 'b11111111;
end
task draw_sprite;
input [11:0] _addr;
input [3:0] _lines;
input [7:0] _x, _y;
begin
draw <= 1;
addr <= _addr;
lines <= _lines;
x <= _x;
y <= _y;
#2 draw <= 0;
#2 wait (!busy);
end
endtask
initial begin
$dumpfile(`VCD_FILE);
$dumpvars;
#2;
draw_sprite('h42, 5, 0, 0);
utils.assert_equal(collision, 0);
utils.assert_equal(mem0.data['h100], 'b11111111);
utils.assert_equal(mem0.data['h108], 'b11000011);
utils.assert_equal(mem0.data['h110], 'b11000011);
utils.assert_equal(mem0.data['h118], 'b11000011);
utils.assert_equal(mem0.data['h120], 'b11111111);
// erase
draw_sprite('h42, 5, 0, 0);
utils.assert_equal(collision, 1);
utils.assert_equal(mem0.data['h100], 0);
utils.assert_equal(mem0.data['h108], 0);
utils.assert_equal(mem0.data['h110], 0);
utils.assert_equal(mem0.data['h118], 0);
utils.assert_equal(mem0.data['h120], 0);
// y = 28 (test wrapping bottom)
draw_sprite('h42, 5, 0, 28);
utils.assert_equal(collision, 0);
utils.assert_equal(mem0.data['h1e0], 'b11111111);
utils.assert_equal(mem0.data['h1e8], 'b11000011);
utils.assert_equal(mem0.data['h1f0], 'b11000011);
utils.assert_equal(mem0.data['h1f8], 'b11000011);
utils.assert_equal(mem0.data['h100], 'b11111111);
draw_sprite('h42, 5, 0, 28); // erase
// x = 5
draw_sprite('h42, 5, 5, 0);
utils.assert_equal(collision, 0);
utils.assert_equal({mem0.data['h100], mem0.data['h101]}, 'b00000111_11111000);
utils.assert_equal({mem0.data['h108], mem0.data['h109]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h110], mem0.data['h111]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h118], mem0.data['h119]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h120], mem0.data['h121]}, 'b00000111_11111000);
draw_sprite('h42, 5, 5, 0); // erase
// x = 61 (test wrapping right)
draw_sprite('h42, 5, 61, 0);
utils.assert_equal(collision, 0);
utils.assert_equal({mem0.data['h107], mem0.data['h100]}, 'b00000111_11111000);
utils.assert_equal({mem0.data['h10f], mem0.data['h108]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h117], mem0.data['h110]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h11f], mem0.data['h118]}, 'b00000110_00011000);
utils.assert_equal({mem0.data['h127], mem0.data['h120]}, 'b00000111_11111000);
$finish;
end
endmodule |
module bcd(input wire [7:0] abc,
output wire [1:0] a,
output reg [3:0] b,
output reg [3:0] c);
assign a = abc >= 200 ? 2 : abc >= 100 ? 1 : 0;
wire [6:0] bc = abc - 100 * a;
// See Hacker's Delight, Integer division by constants:
// https://www.hackersdelight.org/divcMore.pdf
reg [6:0] q;
reg [3:0] r;
always @(*) begin
q = (bc >> 1) + (bc >> 2);
q = q + (q >> 4);
q = q >> 3;
r = bc - q * 10;
if (r < 10) begin
b = q;
c = r;
end else begin
b = q + 1;
c = r - 10;
end
end
endmodule |
module utils;
task assert_true;
input x;
begin
if (!x) begin
$error($time, " Assertion failed");
$finish_and_return(1);
end
end
endtask
task assert_equal;
input [31:0] x;
input [31:0] y;
begin
if (x != y) begin
$error($time, " %x != %x", x, y);
$finish_and_return(1);
end
end
endtask
task timeout;
input [31:0] n;
begin
#n;
$error($time, " Timed out after %d ticks", n);
$finish_and_return(1);
end
endtask
endmodule |
module rng(input wire clk,
output wire [31:0] out,
input wire user_input);
reg [31:0] state = 42;
reg [31:0] next;
assign out = state;
always @(*) begin
next = state;
next = next ^ (next << 13);
next = next ^ (next >> 17);
next = next ^ (next << 5);
if (user_input) begin
next = next ^ (next << 13);
next = next ^ (next >> 17);
next = next ^ (next << 5);
end
end
always @(posedge clk) begin
state <= next;
end
endmodule |
module mem(input wire clk,
input wire read,
input wire [11:0] read_idx,
output reg [7:0] read_byte,
output reg read_ack = 0,
input wire write,
input wire [11:0] write_idx,
input wire [7:0] write_byte);
parameter debug = 0;
reg [7:0] data[0:'hFFF];
initial $readmemh("font.hex", data, 'h030, 'h07f);
// for icebram to replace
initial $readmemh("random.hex", data, 'h200, 'hfff);
always @(posedge clk) begin
read_ack <= 0;
if (read) begin
if (debug)
$display($time, " load [%x] = %x", read_idx, data[read_idx]);
read_byte <= data[read_idx];
read_ack <= 1;
end
if (write) begin
if (debug)
$display($time, " store [%x] = %x", write_idx, write_byte);
data[write_idx] <= write_byte;
end
end
endmodule |
module top;
reg [7:0] abc = 0;
wire [1:0] a;
wire [3:0] b, c;
bcd bcd0(abc, a, b, c);
initial begin
$monitor($time, " %d -> %d %d %d", abc, a, b, c);
$dumpfile(`VCD_FILE);
$dumpvars;
repeat (256) begin
#1;
utils.assert_equal(abc, a * 100 + b * 10 + c);
utils.assert_true(a < 10 && b < 10 && c < 10);
abc += 1;
end
#1 $finish;
end
endmodule |
module ext18#(parameter DEPTH=18)(
input [DEPTH-1:0] a,
output reg [31:0] b
);
always@(a)
begin
if(a[DEPTH-1] == 1)//ÓзûºÅÀ©Õ¹
begin
b[31:0] = 32'hffffffff;
b[DEPTH-1:0] = a[DEPTH-1:0];
end
else
begin
b[31:0] = 32'h00000000;
b[DEPTH-1:0] = a[DEPTH-1:0];
end
end
endmodule |
module cpu(
input clk,
input [31:0] inst,
input reset,
input [31:0] mrdata,
output [31:0] pc_out,
output [31:0] maddr,
output [31:0] mwdata,
output IM_R,
output DM_CS,
output DM_R,
output DM_W,
output [31:0]alu_r
);
wire RF_W,M1,M2,M3,M4,M5,M6,sign_ext,zero;
wire [2:0] ALUC;
wire[31:0] mux1_out,mux2_out,mux3_out,mux4_out,mux5_out,alu_out;
wire [31:0] rf_rdata1,rf_rdata2;
wire [31:0] ext5_out,ext16_out,ext18_out;
wire [31:0] npc_out;
wire [31:0] join_out;
wire [27:0] temp1,temp2;
assign alu_r = alu_out;
assign maddr = alu_out;
assign mwdata = rf_rdata2;
assign temp1 = inst[25:0]<<2;
assign temp2 = inst[15:0]<<2;
wire [4:0]mux6_out = M6 ? inst[20:16]:inst[15:11];
decoder cpu_decoder(inst,clk,zero,IM_R,M3,M4,ALUC,M2,RF_W,M5,M1,DM_CS,DM_R,DM_W,M6,sign_ext);
PC cpu_pc(clk,reset,mux1_out,pc_out);
NPC cpu_npc(pc_out,npc_out);
JOIN cpu_join(temp1,pc_out[31:28],join_out);
regfile cpu_regfile(clk,reset,RF_W,inst[25:21],inst[20:16],mux6_out,mux2_out,rf_rdata1,rf_rdata2);
alu cpu_alu(mux3_out,mux4_out,ALUC,alu_out,zero);
ext5 cpu_ext5(inst[10:6],ext5_out);
ext16 cpu_ext16(inst[15:0],sign_ext,ext16_out);
ext18 cpu_ext18(temp2,ext18_out);
mux2x32 mux1(join_out,mux5_out,M1,mux1_out);
mux2x32 mux2(mrdata,alu_out,M2,mux2_out);
mux2x32 mux3(ext5_out,rf_rdata1,M3,mux3_out);
mux2x32 mux4(rf_rdata2,ext16_out,M4,mux4_out);
mux2x32 mux5(npc_out,(ext18_out+pc_out+4),M5,mux5_out);
endmodule |
module top_tb;
reg clk_in;
reg reset;
wire clk;
wire [31:0]pc;
wire [31:0]inst;
wire IM_R;
wire DM_CS;
wire DM_R;
wire DM_W;
wire [31:0]alu_r;
top uut(clk_in,reset,clk,pc,inst,addr,rdata,wdata,IM_R,DM_CS,DM_R,DM_W,alu_r);
// 不同的initial块是并行的，块内部顺序执行
initial
begin
clk_in = 0;
forever #100 clk_in = ~clk_in;
end
initial
begin
reset = 0;
#50 reset=1;
#10 reset=0;
#2000 $stop;
end
initial // 用iverilog+gtkwave仿真时用到的
begin
$dumpfile("wave.vcd"); //生成的vcd文件名称
$dumpvars(0, top_tb); //tb模块名称
end
endmodule |
module mux2x32#(parameter WIDTH=32)(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input select,
output reg [WIDTH-1:0] r
);
always @*
begin
case(select)
1'b0:
r=a;
1'b1:
r=b;
endcase
end
endmodule |
module imem(
input [31:0] a,
input IM_R,
output [31:0] rd
);
reg [31:0] RAM[2047:0];
initial
begin
$readmemh("imem.txt",RAM);
end
assign rd=(IM_R)?RAM[a[31:2]]:32'bx;
endmodule |
module decoder(
input [31:0] inst,
input clk,
input zero,
output IM_R,
output M3,
//output M4_0,
//output M4_1,
output M4,
output [2:0] ALUC,
output M2,
output RF_W,
//output RF_CLK,
output M5,
output M1,
output DM_CS,
output DM_R,
output DM_W,
output M6,
output sign_ext
);
wire [5:0] func=inst[5:0];
wire [5:0] op=inst[31:26];
wire r_type=~|op;
wire addu,subu,ori,sll,lw,sw,beq,j_i;
assign addu=r_type &func[5]&~func[4]&~func[3]&~func[2]&~func[1]&func[0];
assign subu=r_type &func[5]&~func[4]&~func[3]&~func[2]&func[1]&func[0];
assign ori=~op[5]&~op[4]&op[3]&op[2]&~op[1]&op[0];
assign sll=r_type &~func[5]&~func[4]&~func[3]&~func[2]&~func[1]&~func[0];
assign lw=op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0];
assign sw=op[5]&~op[4]&op[3]&~op[2]&op[1]&op[0];
assign beq=~op[5]&~op[4]&~op[3]&op[2]&~op[1]&~op[0];
assign j_i=~op[5]&~op[4]&~op[3]&~op[2]&op[1]&~op[0];
assign IM_R=1;
assign RF_W=addu|subu|ori|sll|lw;
assign DM_CS=lw|sw;
assign DM_R=lw;
assign DM_2=sw;
assign DM_W=sw;
assign ALUC[2]=0;
assign ALUC[1]=ori|sll;
assign ALUC[0]=subu|beq|sll;
assign M1=addu|subu|ori|sll|beq|lw|sw;
assign M2=addu|subu|ori|sll|beq|j_i|sw;
assign M3=addu|subu|ori|j_i|beq|lw|sw;
//assign M4_0=ori;
//assign M4_1=lw|sw;
assign M4=lw|sw|ori;
assign M5=beq&zero;
assign M6=ori|lw;
assign sign_ext=lw | sw;
endmodule |
module JOIN(
input [27:0] a,
input [3:0] b,
output [31:0] s
);
assign s[31:28]=b;
assign s[27:0]=a;
endmodule |
module ext16#(parameter DEPTH=16)(
input [DEPTH-1:0] a,
input sign_ext,
output reg [31:0] b
);
always@(a or sign_ext)
begin
if(sign_ext==1 && a[DEPTH-1]==1)
begin
b[31:0]=32'hffffffff;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
else
begin
b[31:0]=32'h00000000;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
end
endmodule |
module top(
input clk_in,
input reset,
output clk,
output [31:0]pc,
output [31:0]inst,
output [31:0]addr,
output [31:0]rdata,
output [31:0]wdata,
output IM_R,
output DM_CS,
output DM_R,
output DM_W,
output [31:0]alu_r
);
assign clk = clk_in;
cpu sccpu(clk_in,inst,reset,rdata,pc,addr,wdata,IM_R,DM_CS,DM_R,DM_W,alu_r);
imem imemory(pc, IM_R, inst);
dmem scdmem(clk_in,reset,DM_CS,DM_W,DM_R,addr,wdata,rdata);
endmodule |
module ext5 #(parameter DEPTH=5)(
input [DEPTH-1:0] a,
output reg [31:0] b
);
always@(a)
begin
if(a[DEPTH-1]==1)
begin
b[31:0]=32'hffffffff;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
else
begin
b[31:0]=32'h00000000;
b[DEPTH-1:0]=a[DEPTH-1:0];
end
end
endmodule |
module regfile(
input clk,
input rst,
input we,
input [4:0] raddr1,
input [4:0] raddr2,
input [4:0] waddr,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] array_reg[31:0];
integer i;
always@(posedge clk,posedge rst)
begin
if(rst)
begin
i=0;
while(i<32)
begin
array_reg[i]=0;
i=i+1;
end
end
else if(we)
begin
if(waddr!=0)
array_reg[waddr]=wdata;
end
end
assign rdata1=array_reg[raddr1];
assign rdata2=array_reg[raddr2];
endmodule |
module PC(
input clk,
input rst,
input [31:0] data_in,
output reg [31:0] data_out
);
always@(posedge clk,posedge rst)
begin
if(rst)
data_out<=32'b0;
else
data_out<=data_in;
end
endmodule |