module counter
# (
    parameter w = 1
) 
(
    input            clk,
    input            reset,
    input            en,
    output [w - 1:0] cnt
);

    wire [w - 1:0] q;
    wire [w - 1:0] d = q + 1'b1;

    register # (w) i_reg (clk, reset, en, d, q);
    
    assign cnt = q;

endmodule