module fpga_100hz_gen (
  input  wire  clk25mhz,
  input  wire  reset_n,
  output wire  clk100hz
  );

  reg [16:0]  reg_cntr;

  reg         reg_clk100hz;

  // Counter overflow at 200Hz
  always @(posedge clk25mhz or negedge reset_n)
  begin
    if (~reset_n)
      reg_cntr <= {17{1'b0}};
    else
      if (reg_cntr==124999)
        reg_cntr <= {17{1'b0}};
      else
        reg_cntr <= reg_cntr + {{16{1'b0}}, 1'b1};
  end

  // Toggle at 200Hz -> 100Hz clock
  always @(posedge clk25mhz or negedge reset_n)
  begin
    if (~reset_n)
      reg_clk100hz <= 1'b0;
    else
      if (reg_cntr==124999)
        reg_clk100hz <= ~reg_clk100hz;
  end

  assign clk100hz = reg_clk100hz;

endmodule