module tb_insert_training_pattern;

    reg         clk         = 1'b1;
    reg         clock_train = 1'b0;
    reg         align_train = 1'b0;
    reg  [71:0] in_data;
    wire [79:0] out_data;
    reg  [11:0] count;

initial begin
    count       = 12'b0;
    clock_train = 1'b1;  
    align_train = 1'b0;  
    in_data = 72'hFFFFFFFFFFFFFFFFFF;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        if(count == 100) begin clock_train = 1'b0; align_train = 1'b1; end
        if(count == 200) begin clock_train = 1'b0; align_train = 1'b0; end
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        count = count + 1;
    end
end

insert_training_pattern i_insert_training_pattern(
    .clk         (clk),
    .clock_train (clock_train),
    .align_train (align_train),
    .in_data     (in_data),
    .out_data    (out_data)
);

endmodule