module smallfifo16(input rst,
		 
		   input         clk_in,
		   input [15:0]  fifo_in,
		   input         fifo_en,

		   output        fifo_full,

		   input         clk_out,
		   output [15:0] fifo_out,
		   output        fifo_empty,
		   input         fifo_rd);


   vga_fifo_dc#(.AWIDTH(4),.DWIDTH(16)) 
   fifo0(.rclk (clk_out),
         .wclk (clk_in),
         .rclr (~rst),
         .wclr (~rst),
         .wreq (fifo_en),
         .d (fifo_in),
         .rreq (fifo_rd),
         .q (fifo_out),
         .empty (fifo_empty),
         .full (fifo_full));
   
   
endmodule