module Constants(input clock, input [5:0] io_wide_bus, output reduced, output [2: 0] out);

  reg reduce_it;
  assign reduced = reduce_it;

  AndOr mod(reduce_it, 1'b0, 1'b1, out[0], out[1], out[2]);
  
  always @(posedge clock) begin
    reduce_it = |io_wide_bus;
  end
endmodule