module fm_3d_mu_dif (
  clk_core,
  rst_x,
  // bus side port
  i_bstr,
  i_bdata,
  o_back,
  // internal port
  o_istr,
  o_idata,
  i_iack
);

parameter P_WIDTH = 36;
////////////////////////////
// I/O definitions
////////////////////////////
input         i_bstr;         // input strobe
input  [P_WIDTH-1:0]
              i_bdata;        // input data (Write Data + BE)
output        o_back;         // output acknowledge

output        o_istr;         // output strobe
output [P_WIDTH-1:0]
              o_idata;        // output data
input         i_iack;         // input acknowledge

input         clk_core;            // system clock
input         rst_x;          // system reset

/////////////////////////
//  register definition
/////////////////////////
// input register
reg           r_bstr;
reg    [P_WIDTH-1:0]
              r_bdata;

/////////////////////////
//  wire definition
/////////////////////////
/////////////////////////
//  assign statement
/////////////////////////
assign o_istr = r_bstr;
assign o_idata = r_bdata;
assign o_back = i_iack;
/////////////////////////
//  always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstr <= 1'b0;
  end else begin
    if (i_iack) r_bstr <= i_bstr;
  end
end

always @(posedge clk_core) begin
  if (i_iack) r_bdata <= i_bdata;
end

endmodule