module clk_divider(clk_i, clk_o);

input wire clk_i;
output reg clk_o;

reg int_clk;

initial begin
  clk_o <= 0;
  int_clk <= 0;
end

always @(posedge clk_i) begin
  int_clk <= ~int_clk;
end

always @(posedge int_clk) begin
  clk_o <= ~clk_o;
end

endmodule