module e203_subsys_pllclkdiv(
  input rst_n,
  input test_mode,
  input divby1,
  input [5:0] div, 
  input clk,// The PLL clock
  output clkout // The divided Clock
  );

  wire [5:0] div_cnt_r; 
  wire div_cnt_sat = (div_cnt_r == div);
  wire [5:0] div_cnt_nxt = div_cnt_sat ? 6'b0 : (div_cnt_r + 1'b1); 
  wire div_cnt_ena = (~divby1);
  sirv_gnrl_dfflr #(6) div_cnt_dfflr (div_cnt_ena, div_cnt_nxt, div_cnt_r, clk, rst_n);

  wire flag_r; 
  wire flag_nxt = ~flag_r;
  wire flag_ena = div_cnt_ena & div_cnt_sat;
  sirv_gnrl_dfflr #(1) flag_dfflr (flag_ena, flag_nxt, flag_r, clk, rst_n);


  wire plloutdiv_en = divby1 | 
                    ((~flag_r) & div_cnt_sat); 

  e203_clkgate u_pllclkdiv_clkgate(
    .clk_in   (clk        ),
    .test_mode(test_mode  ),
    .clock_en (plloutdiv_en),
    .clk_out  (clkout)
  );
endmodule