module top
(
  clk_i,
  data_i,
  data_r_o
);

  input [15:0] data_i;
  output [31:0] data_r_o;
  input clk_i;

  bsg_link_iddr_phy
  wrapper
  (
    .data_i(data_i),
    .data_r_o(data_r_o),
    .clk_i(clk_i)
  );


endmodule