module tb_uart;

    reg clk = 0;
    reg reset = 0;

    wire rx = 0;
    wire tx;

    reg[7:0] wrdata;
    reg transmit;

    wire[7:0] rddata;
    wire received;

    simpleuart uart1 (
        .clk        (clk),
	    .reset      (reset),

        .baud_divider   (16'd 1250),

        .data_write (wrdata),
        .transmit   (transmit),
        .ready (),

        .data_read  (),
        .received   (),

        .tx         (tx),
        .rx         (rx)
    );

    simpleuart uart2 (
        .clk        (clk),
	    .reset      (reset),

        .baud_divider   (16'd 1250),

        .data_write (8'h 00),
        .transmit   (1'b 0),
        .ready (),

        .data_read  (rddata),
        .received   (received),

        .tx         (rx),
        .rx         (tx)
    );

    always #1 clk = !clk;

    initial begin
        $dumpfile(`__def_vcd_file);
        $dumpvars(0, tb_uart);

        # 1 transmit = 0;

        # 5 reset = 0;
        # 5 reset = 1;
        # 5 reset = 0;

        # 20 wrdata = 8'h 81;
        # 5 transmit = 1;
        # 5 transmit = 0;

        // # 400 wrdata = 8'h FF;
        // # 1 transmit = 1;
        // # 1 transmit = 0;

        // # 800 wrdata = 8'h 01;
        // # 1 transmit = 1;
        // # 1 transmit = 0;

        //# 15E3 $finish;
        # 250E3 $finish;
        //# 1E6 $finish;
    end

endmodule