module edge_detection(
    input i_clk,
    input i_reset,
    input i_signal,
    output reg o_post_edge,
    output reg o_nedge_edge
);


reg signal_new, signal_old; 

always @(posedge i_clk) begin
    if (!i_reset) begin
        signal_old <= i_signal;
        signal_new <= i_signal;
        o_post_edge <= 0;
        o_nedge_edge <= 0;
    end else begin
        signal_new <= i_signal;
        signal_old <= signal_new;
        o_post_edge <= signal_new & (~signal_old);
        o_nedge_edge <= (~signal_new) & signal_old;
    end
end

endmodule