module RT_D_MUX(RT_D_Sel,RD2,RF_WD_E,RF_WD_M,RF_WD_W,RT_D);
//input
    input [31:0] RT_D_Sel;

    input [31:0] RD2;
    input [31:0] RF_WD_E;
    input [31:0] RF_WD_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RT_D;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RT_D=RD2;
            case(RT_D_Sel)
                E:RT_D=RF_WD_E;
                M:RT_D=RF_WD_M;
                W:RT_D=RF_WD_W;
            endcase
        end

endmodule