module nedge_edge_detection(
    input i_clk,
    input i_reset,
    input i_signal,
    output reg o_nedge_edge
);


reg signal_old; 

always @(posedge i_clk) begin
    if (!i_reset) begin
        signal_old <= i_signal;
        o_nedge_edge <= 0;
    end else begin
        signal_old <= i_signal;
        o_nedge_edge <= (~i_signal) & signal_old;
    end
end

endmodule