module tb_scrambler_reset_inserter;

    reg clk = 1'b1;

    reg  [71:0] in_data;
    wire [71:0] out_data;

    localparam [8:0] BS = 9'b110111100;  // K28.5

initial begin
    
    in_data      = 72'b0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        #1
        in_data[8:0] = BS;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
        #1
        in_data      = 72'b0;
        #3
        clk = ~clk;
        #4
        clk = ~clk;
    end
end

scrambler_reset_inserter  i_scrambler_reset_inserter(
    .clk      (clk),
    .in_data  (in_data),
    .out_data (out_data)
);

endmodule