module foo(input clk, input i1, input i2, input [15:0] i3,
	   output o1, output reg o2, output reg [7:0] o3);

	wire [7:0] shift_in, shift_out;
	wire foo_1, foo_2;
	reg bar_1, bar_2;

	/* Test parameterized module: pass n = 3 */
	shift_n #(3) shift_foo(shift_in, shift_out);

	/*
	 * {initial begin} is a one-time init function
	 * which will be executed at the very beginning.
	 * It feels like a constructor.
	 */
	initial begin
		bar_1 = 1;

		/*
		 * 1) Delayed assignment: wait 5 cycles before executing
		 *    right-handle statement.
		 * 2) Intra-assignment delay: after executing right-handle
		 *    statement, wait 5 cycles to assign the value to left-hand.
		 *
		 * Both are just used in simulation. Not for synthesis.
		 */
		#5 bar_1 = 0;
		bar_1 = #5 1;

		$display("Howdy");
		$display("`AAA");
	end

	/*
	 * Blocking assignment:
	 * bar_2 will not be executed until bar_1 was assigned.
	 * This is like C code.
	 */
	always @ (posedge clk) begin
		bar_1 = i1;
		bar_2 = i2;
	end

endmodule