module testShift();
    reg clock, d;
    wire [1:0] qa;
    wire [1:0] qb;
    shiftA A(qa, clock, d);
    shiftB B(qb, clock, d);
    always
        #10 clock = ~clock;
    always
        #20 d = ~d;
    initial
    begin
        #0; d=0; clock=0;
        #200 $finish;
    end

endmodule