module rvfi_bus_util_fifo #(
	parameter WIDTH = 8,
	parameter DEPTH = 3
) (
	input clock,
	input reset,

	input              in_valid,
	output             in_ready,
	input  [WIDTH-1:0] in_data,

	output             out_valid,
	input              out_ready,
	output [WIDTH-1:0] out_data
);

	wire [WIDTH-1:0] stage_data [0:DEPTH];
	wire [DEPTH:0] stage_valid;
	wire [DEPTH:0] stage_ready;

	genvar i;
	generate for (i = 0; i < DEPTH; i = i + 1) begin
		rvfi_bus_util_fifo_stage #(.WIDTH(WIDTH)) stage (
			.clock(clock),
			.reset(reset),
			.in_data(stage_data[i]),
			.out_data(stage_data[i+1]),
			.in_valid(stage_valid[i]),
			.out_valid(stage_valid[i+1]),
			.in_ready(stage_ready[i]),
			.out_ready(stage_ready[i+1])
		);
	end endgenerate

	assign stage_valid[0] = in_valid;
	assign stage_data[0] = in_data;
	assign in_ready = stage_ready[0];

	assign out_valid = stage_valid[DEPTH];
	assign stage_ready[DEPTH] = out_ready;
	assign out_data = stage_data[DEPTH];
endmodule