module itlb_tr_sub(
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [21 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [21 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [21 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

itlb_tr_blk itlb_tr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra(addra_wire),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb(addrb_wire),
	.doutb(doutb));

endmodule