module xyloni
(
  input BTN1,
  input BTN2_J2_7,
  input [14:0] GPIO_J1_IN,
  input [13:0] GPIO_J2_IN,
  input [8:0] GPIO_J3_IN,
  input RXD,
  input SD_DI,
  input SPI_MISO,
  input i_sysclk,
  input i_pll_locked,
  output [14:0] GPIO_J1_OUT,
  output [14:0] GPIO_J1_OE,
  output [13:0] GPIO_J2_OUT,
  output [13:0] GPIO_J2_OE,
  output [8:0] GPIO_J3_OUT,
  output [8:0] GPIO_J3_OE,
  output LED1,
  output LED2,
  output LED3_J2_6,
  output LED4_J2_5,
  output SD_CS,
  output SD_DO,
  output SD_SCLK,
  output SPI_MOSI,
  output SPI_SCLK,
  output SPI_SS,
  output TXD
);


endmodule