module ram_32_56(
        input wire clk,
        input wire rst,
        // Read port
        input wire [4:0] raddr,
        input wire re,
        output reg [55:0] rd,
        // Write port
        input wire [4:0] waddr,
        input wire [55:0] wr,
        input wire we
   );

    reg [55:0] mem [0:31];

    always @(posedge clk) begin
        if (!rst) begin
            if (re) begin
                rd <= mem[raddr];
            end
            // W
            if (we) begin
                mem[waddr] <= wr;
            end
        end
    end

endmodule