module stud_synchronizer
	#(parameter N=4,
	  parameter WIDTH = 16)
	(	input clk_i, rst_n_i,
		input [WIDTH-1:0] input_i,
		output [WIDTH-1:0] output_o);

	genvar i;
	genvar w;
	wire [WIDTH-1:0] buffer [0:N-1];
	generate
		/* Generate chain for each bit in WIDTH*/
		for(w = 0; w < WIDTH; w = w + 1) begin
			/* First FF in chain*/
			stud_d_flip_flop d0(clk_i, rst_n_i, input_i[w], buffer[0][w]);
			/* Every other FF in chain*/
			for(i = 1; i < N; i = i + 1) begin
				stud_d_flip_flop d_mid (clk_i, rst_n_i, buffer[i-1][w], buffer[i][w]);
			end
		end
	endgenerate
	assign output_o = buffer[N-1];	
endmodule