module led_1second(
             clk,
             reset,
             led_a
             );
input  clk;
input  reset;
output led_a;   

reg reg_led_a;


reg reg_1s_flag;
reg reg_ms_flag;
reg reg_us_flag;
//reg reg_1m_flag;
//reg [5:0] reg_s_count;
reg [9:0] reg_ms_count;
reg [9:0] reg_us_count;
reg [5:0] reg_clk_count;

//¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ªbegin ÒÔÏÂ´úÂëµÄ¹¦ÄÜ£ºÊµÏÖ1·ÖÖÓ¼ÆÊý£¬²¢²úÉúÒ»¸öÒ»·ÖÖÓ±êÖ¾¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª¡ª

//clk¼ÆÊýÆ÷£¬µ±¼Æµ½50 ¸öÊ±ÖÓ£¨50MHZµÄÊ±ÖÓ£¬ÖÜÆÚÊÇ20ns£©Ê±ÇåÁã£¬Ò²¾ÍÊÇ1000ms = 1Î¢Ãë
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_clk_count <= 6'b00000;
  else  if( reg_clk_count == 49) reg_clk_count <= 6'b00000;
  else  reg_clk_count <= reg_clk_count + 1;
end

//²úÉú1us±êÖ¾ reg_us_flag
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_us_flag <= 0;
  else  if( reg_clk_count == 49) reg_us_flag <= 1;
  else  reg_us_flag <= 0;
end
//us ¼ÆÊýÆ÷£¬µ±¼Æµ½1000us Ê±ÇåÁã£¬Ò²¾ÍÊÇ1ºÁÃë
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_us_count <= 0;
  else  if( reg_us_count == 999) reg_us_count <= 10'h000;
  else  if( reg_us_flag) reg_us_count <= reg_us_count + 1;
end

//²úÉú1ms±êÖ¾ reg_ms_flag
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_ms_flag <= 0;
  else  if( reg_us_count == 999) reg_ms_flag <= 1;
  else  reg_ms_flag <= 0;
end
//ms ¼ÆÊýÆ÷£¬µ±¼Æµ½1000ms Ê±ÇåÁã£¬Ò²¾ÍÊÇ1ÃëÖÓ
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_ms_count <= 0;
  else  if( reg_ms_count == 999) reg_ms_count <= 10'h000;
  else  if( reg_ms_flag) reg_ms_count <= reg_ms_count + 1;
end

//²úÉú1s ±êÖ¾reg_1s_flag
always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_1s_flag <= 0;
  else  if( reg_ms_count == 999) reg_1s_flag <= 1;
  else  reg_1s_flag <= 0;
end


always @(posedge clk or negedge reset)
begin
  if (~reset)
     reg_led_a <= 0;
  else  if( reg_1s_flag == 1) reg_led_a <= ~reg_led_a;
  else  reg_led_a <= reg_led_a;
end

assign led_a = reg_led_a ;


endmodule