module RS_M_MUX(RS_M_Sel,V1_M,RF_WD_W,RS_M);
//input
    input [31:0] RS_M_Sel;

    input [31:0] V1_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RS_M;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RS_M=V1_M;
            case(RS_M_Sel)
                W:RS_M=RF_WD_W;
            endcase
        end

endmodule