module RS_D_MUX(RS_D_Sel,RD1,RF_WD_E,RF_WD_M,RF_WD_W,RS_D);
//input
    input [31:0] RS_D_Sel;

    input [31:0] RD1;
    input [31:0] RF_WD_E;
    input [31:0] RF_WD_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RS_D;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RS_D=RD1;
            case(RS_D_Sel)
                E:RS_D=RF_WD_E;
                M:RS_D=RF_WD_M;
                W:RS_D=RF_WD_W;
            endcase
        end

endmodule