module rvfi_bus_util_fifo_stage #(
	parameter WIDTH = 8
) (
	input clock,
	input reset,

	input              in_valid,
	output             in_ready,
	input  [WIDTH-1:0] in_data,

	output             out_valid,
	input              out_ready,
	output [WIDTH-1:0] out_data
);

	reg [WIDTH-1:0] buffered;
	reg buffer_valid;

	wire in_txn = in_valid && in_ready;
	wire out_txn = out_valid && out_ready;

	assign out_data = buffer_valid ? buffered : in_data;
	assign in_ready = out_ready || !buffer_valid;
	assign out_valid = in_valid || buffer_valid;

	always @(posedge clock) begin
		if (reset) begin
			buffer_valid <= 0;
		end else begin
			if (in_txn != out_txn)
				buffer_valid <= in_txn;
		end
		if (in_txn)
			buffered <= in_data;
	end

endmodule