module simple_spi_master_wb #(
    parameter BASE_ADR = 32'h2100_0000,
    parameter CONFIG = 8'h00,
    parameter DATA = 8'h04
) (
    input wb_clk_i,
    input wb_rst_i,
    input [31:0] wb_adr_i,
    input [31:0] wb_dat_i,
    input [3:0] wb_sel_i,
    input wb_we_i,
    input wb_cyc_i,
    input wb_stb_i,
    output wb_ack_o,
    output [31:0] wb_dat_o,

    output	 hk_connect,	// Connect to housekeeping SPI
    output	 spi_enabled,	// Use to mux pins with GPIO control
    input 	 sdi,	 // SPI input
    output 	 csb,	 // SPI chip select
    output 	 sck,	 // SPI clock
    output 	 sdo,	 // SPI output
    output 	 sdoenb, // SPI output enable
    output	 irq	 // interrupt output
);

    wire [31:0] simple_spi_master_reg_cfg_do;
    wire [31:0] simple_spi_master_reg_dat_do;

    wire resetn = ~wb_rst_i;
    wire valid = wb_stb_i && wb_cyc_i;
    wire simple_spi_master_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
    wire simple_spi_master_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));

    wire [1:0] reg_cfg_we = (simple_spi_master_reg_cfg_sel) ?
		(wb_sel_i[1:0] & {2{wb_we_i}}): 2'b00;
    wire reg_dat_we = (simple_spi_master_reg_dat_sel) ? (wb_sel_i[0] & wb_we_i): 1'b0;
    wire reg_dat_wait;

    wire [31:0] mem_wdata = wb_dat_i;
    wire reg_dat_re = simple_spi_master_reg_dat_sel && !wb_sel_i && ~wb_we_i;

    assign wb_dat_o = (simple_spi_master_reg_cfg_sel) ? simple_spi_master_reg_cfg_do :
		simple_spi_master_reg_dat_do;
    assign wb_ack_o = (simple_spi_master_reg_cfg_sel || simple_spi_master_reg_dat_sel)
		&& (!reg_dat_wait);

    simple_spi_master spi_master (
    	.resetn(resetn),
    	.clk(wb_clk_i),
    	.reg_cfg_we(reg_cfg_we),
    	.reg_cfg_di(mem_wdata),
    	.reg_cfg_do(simple_spi_master_reg_cfg_do),
    	.reg_dat_we(reg_dat_we),
    	.reg_dat_re(reg_dat_re),
    	.reg_dat_di(mem_wdata),
    	.reg_dat_do(simple_spi_master_reg_dat_do),
    	.reg_dat_wait(reg_dat_wait),

	.hk_connect(hk_connect),	// Attach to housekeeping SPI slave
	.spi_enabled(spi_enabled),	// Mux pins with GPIO
    	.sdi(sdi),	 // SPI input
    	.csb(csb),	 // SPI chip select
    	.sck(sck),	 // SPI clock
    	.sdo(sdo),	 // SPI output
	.irq_out(irq)	 // interrupt
    );
endmodule