module or1200_reg2mem_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		addr, lsu_op, regdata, memdata);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg [ 1 : 0 ] addr_cml_3;
reg [ 4 - 1 : 0 ] lsu_op_cml_3;
reg [ 4 - 1 : 0 ] lsu_op_cml_2;
reg [ 4 - 1 : 0 ] lsu_op_cml_1;
reg [ 32 - 1 : 0 ] regdata_cml_3;
reg [ 32 - 1 : 0 ] regdata_cml_2;
reg [ 32 - 1 : 0 ] regdata_cml_1;



parameter width = `OR1200_OPERAND_WIDTH;

//
// I/O
//
input	[1:0]			addr;
input	[`OR1200_LSUOP_WIDTH-1:0]	lsu_op;
input	[width-1:0]		regdata;
output	[width-1:0]		memdata;

//
// Internal regs and wires
//
reg	[7:0]			memdata_hh;
reg	[7:0]			memdata_hl;
reg	[7:0]			memdata_lh;
reg	[7:0]			memdata_ll;

assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};

//
// Mux to memdata[31:24]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_hh
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_3 or addr_cml_3 or regdata_cml_3) begin
	casex({lsu_op_cml_3, addr_cml_3[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata_cml_3[7:0];
		{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata_cml_3[15:8];
		default : memdata_hh = regdata_cml_3[31:24];
	endcase
end

//
// Mux to memdata[23:16]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_hl
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_3 or addr_cml_3 or regdata_cml_3) begin
	casex({lsu_op_cml_3, addr_cml_3[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata_cml_3[23:16];
		default : memdata_hl = regdata_cml_3[7:0];
	endcase
end

//
// Mux to memdata[15:8]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_lh
// replace(s): addr, lsu_op, regdata
always @(lsu_op_cml_3 or addr_cml_3 or regdata_cml_3) begin
	casex({lsu_op_cml_3, addr_cml_3[1:0]})	// synopsys parallel_case
		{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata_cml_3[7:0];
		default : memdata_lh = regdata_cml_3[15:8];
	endcase
end

//
// Mux to memdata[7:0]
//

// SynEDA CoreMultiplier
// assignment(s): memdata_ll
// replace(s): regdata
always @(regdata_cml_3)
	memdata_ll = regdata_cml_3[7:0];


always @ (posedge clk_i_cml_1) begin
lsu_op_cml_1 <= lsu_op;
regdata_cml_1 <= regdata;
end
always @ (posedge clk_i_cml_2) begin
lsu_op_cml_2 <= lsu_op_cml_1;
regdata_cml_2 <= regdata_cml_1;
end
always @ (posedge clk_i_cml_3) begin
addr_cml_3 <= addr;
lsu_op_cml_3 <= lsu_op_cml_2;
regdata_cml_3 <= regdata_cml_2;
end
endmodule