module NEU_VALID ( BCLK, VALIN, WADR, WREN, RADR, VALOUT );

	input			BCLK;
	input	[23:0]	VALIN;
	input	 [4:0]	WADR;
	input			WREN;
	input	 [4:0]	RADR;
	
	output	[23:0]	VALOUT;
	
	reg		[23:0]	cvalid [0:31];	// Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
	reg		[23:0]	ramout;
	reg		[23:0]	valhold;
	reg				gleich;

	always @(posedge BCLK) ramout <= cvalid[RADR];
	always @(posedge BCLK) if (WREN) cvalid[WADR] <= VALIN;
	
	always @(posedge BCLK) valhold <= VALIN;
	always @(posedge BCLK) gleich  <= WREN & (RADR == WADR);
	
	assign VALOUT = gleich ? valhold : ramout;
	
endmodule