module tb_test_source_800_600_RGB_444_ch1;

    reg clk = 1'b0;


initial begin
        forever #10 clk = ~clk; // generate a clock
    end     

    wire        ready = 1'b1;
    wire [2:0]  stream_channel_count = 3'b1;
    wire [23:0] M_value;
    wire [23:0] N_value;
    wire [11:0] H_visible;
    wire [11:0] V_visible;
    wire [11:0] H_total;
    wire [11:0] V_total;
    wire [11:0] H_sync_width;
    wire [11:0] V_sync_width;
    wire [11:0] H_start;
    wire [11:0] V_start;
    wire        H_vsync_active_high;
    wire        V_vsync_active_high;
    wire        flag_sync_clock;
    wire        flag_YCCnRGB;
    wire        flag_422n444;
    wire        flag_YCC_colour_709;
    wire        flag_range_reduced;
    wire        flag_interlaced_even;
    wire  [1:0] flags_3d_Indicators;
    wire  [4:0] bits_per_colour;

    wire [72:0] raw_data;

test_source_800_600_RGB_444_ch1 i_test_source(
        .M_value              (M_value),
        .N_value              (N_value),
        
        .H_visible            (H_visible),
        .H_total              (H_total),
        .H_sync_width         (H_sync_width),
        .H_start              (H_start),    
        
        .V_visible            (V_visible),
        .V_total              (V_total),
        .V_sync_width         (V_sync_width),
        .V_start              (V_start),
        .H_vsync_active_high  (H_vsync_active_high),
        .V_vsync_active_high  (V_vsync_active_high),
        .flag_sync_clock      (flag_sync_clock),
        .flag_YCCnRGB         (flag_YCCnRGB),
        .flag_422n444         (flag_422n444),
        .flag_range_reduced   (flag_range_reduced),
        .flag_interlaced_even (flag_interlaced_even),
        .flag_YCC_colour_709  (flag_YCC_colour_709),
        .flags_3d_Indicators  (flags_3d_Indicators),
        .bits_per_colour      (bits_per_colour), 
        .stream_channel_count (stream_channel_count),
        
        .clk          (clk),
        .ready        (ready),
        .data         (raw_data)
    );

endmodule