module cr_cp0_randclk(
  randclk_psr_mod_en_w13
);

// &Ports; @25
output       randclk_psr_mod_en_w13; 

// &Regs; @26

// &Wires; @27
wire         randclk_psr_mod_en_w13; 


// &Force("bus","seu_cp0_randclk_mod_en",31,0); @31

//assign randclk_oreg_vec_mod_en_w22 = 1'b0;
//assign randclk_psr_c_mod_en_w2     = 1'b0;
assign randclk_psr_mod_en_w13      = 1'b0;
//assign randclk_psr_epsr_mod_en_w46 = 1'b0;


// &ModuleEnd; @47
endmodule