module color_lut (
	input 					read_clk,
	input 		[7:0] 	input_index,
	output reg 	[23:0] 	output_color,
	input						write_clk,
	input 		[7:0] 	write_address,
	input 		[23:0]	write_data,
	input 					write_enable
);

reg [23:0] mem [255:0];

always @(posedge read_clk) output_color <= mem[input_index];

always @(posedge write_clk) if (write_enable) mem[write_address] <= write_data;

endmodule