module RAM128X1S_1 (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);

    parameter INIT = 128'h00000000000000000000000000000000;

    output O;

    input  A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;

    reg  [127:0] mem;
    wire [6:0] adr;

    assign adr = {A6, A5, A4, A3, A2, A1, A0};
    assign O = mem[adr];

    initial 
        mem = INIT;

    always @(negedge WCLK) 
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule