module testbench;

localparam TIMEOUT = (1<<10);
reg clock;

wire LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5;

always #5 clock = clock === 1'b0;

top dut (
	.CLK(clock),
	.LEDR_N(LEDR_N),
	.LEDG_N(LEDG_N),
	.LED1(LED1),
	.LED2(LED2),
	.LED3(LED3),
	.LED4(LED4),
	.LED5(LED5)
);

initial begin
	if ($test$plusargs("vcd")) begin
		$dumpfile("testbench.vcd");
		$dumpvars(0, testbench);
	end
end

reg [31:0] cycles = 0;

always @(posedge clock) begin
	cycles <= cycles + 32'h1;
	if (cycles >= TIMEOUT) begin
		$display("Simulated %0d cycles", cycles);
		$finish;
	end
end

endmodule