module spram_16x2048_8x4096 (
	clk,
	rce,
	ra,
	rq,
	wce,
	wa,
	wd
);
	input clk;
	input rce;
	input [11:0] ra;
	output reg [7:0] rq;
	input wce;
	input [10:0] wa;
	input [15:0] wd;
	reg [15:0] memory [0:2047];
	always @(posedge clk) begin
		if (rce)
			rq <= memory[ra / 2][(ra % 2) * 8+:8];
		if (wce)
			memory[wa] <= wd;
	end
	integer i;
	initial for (i = 0; i < 2048; i = i + 1)
		memory[i] = 0;
endmodule