module chooseFrom2 #(parameter N=32) (req,fin,a,b,out,sel);
input req;
input [N-1:0] a,b;
output reg [N-1:0] out=0;
output reg fin=1'b1;
input sel;
reg finBuf=1'b0;

always@(posedge req or posedge finBuf) begin
    if(finBuf) begin
        if(sel) out<=a;
        else out<=b;  
        fin<=1'b1;
        finBuf<=1'b0;
     end
     else begin
        finBuf<=1'b1;
        fin<=1'b0;
        out<=0;
     end
end


endmodule