module DiffCheck
(
    input clock,
    input [23:0] rgb1,
    input [23:0] rgb2,
    output reg result
);

    reg [7:0] r, g, b, r_q, g_q, b_q;
    reg [8:0] t, gx, u, t_q, gx_q;
    reg [9:0] y, v;

    // if y is inside (-96..96)
    reg y_inside, u_inside, v_inside;

    always_ff @(posedge clock) begin
        // stage 1
        r <= rgb1[7:1]   - rgb2[7:1];
        g <= rgb1[15:9]  - rgb2[15:9];
        b <= rgb1[23:17] - rgb2[23:17];

        // stage 2
        t <= $signed(r) + $signed(b);
        gx <= { g[7], g };
        { r_q, g_q, b_q } <= { r, g, b };

        // stage 3
        y <= $signed(t) + $signed(gx);
        u <= $signed(r_q) - $signed(b_q);
        v <= $signed({g_q, 1'b0}) - $signed(t);

        // stage 4
        // if y is inside (-96..96)
        y_inside <= (y < 10'h60 || y >= 10'h3a0);
        // if u is inside (-16, 16)
        u_inside <= (u < 9'h10 || u >= 9'h1f0);
        // if v is inside (-24, 24)
        v_inside <= (v < 10'h18 || v >= 10'h3e8);

        // stage 5
        result <= !(y_inside && u_inside && v_inside);
    end
endmodule