module altr_hps_interface_register
    (
    input  wire              clk,       // clock
    input  wire              rst_n,     // async reset
    input  wire              test_ctrl, // test control
    input  wire              scanen,    // scan enable
    input  wire              data_in,   // data in
    input  wire              scan_in,   // scan in
    output wire              data_out   // data out
     );

`ifdef ALTR_HPS_INTEL_MACROS_OFF

    reg   dff1;
    wire  muxsel;

   assign  muxsel = scanen | test_ctrl;

   
   always @(posedge clk or negedge rst_n)
   begin
      if (!rst_n)
         dff1     <= 1'b0;
      else
         dff1 <= muxsel ? scan_in : data_in;
   end
  assign data_out = dff1;

`else


`endif

endmodule // altr_hps_interface_register