module M_div16__div0 (
in_inum,
in_iden,
out_ret,
in_run,
out_done,
reset,
out_clock,
clock
);
input signed [15:0] in_inum;
input signed [15:0] in_iden;
output signed [15:0] out_ret;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
wire  [16:0] _w_diff;
wire  [15:0] _w_num;
wire  [15:0] _w_den;

reg  [16:0] _d_ac;
reg  [16:0] _q_ac;
reg  [4:0] _d_i;
reg  [4:0] _q_i;
reg signed [15:0] _d_ret;
reg signed [15:0] _q_ret;
reg  [1:0] _d_index,_q_index = 3;
assign out_ret = _q_ret;
assign out_done = (_q_index == 3);


assign _w_diff = _q_ac-_w_den;
assign _w_num = in_inum;
assign _w_den = in_iden;

`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (in_run || out_done));
`endif
always @* begin
_d_ac = _q_ac;
_d_i = _q_i;
_d_ret = _q_ret;
_d_index = _q_index;
// _always_pre
(* full_case *)
case (_q_index)
0: begin
// _top
_d_ac = {{15{1'b0}},_w_num[15+:1]};
_d_ret = {_w_num[0+:15],1'b0};
_d_index = 1;
end
1: begin
// __while__block_1
if (_q_i!=16) begin
// __block_2
// __block_4
if (_w_diff[16+:1]==0) begin
// __block_5
// __block_7
_d_ac = {_w_diff[0+:15],_q_ret[15+:1]};
_d_ret = {_q_ret[0+:15],1'b1};
// __block_8
end else begin
// __block_6
// __block_9
_d_ac = {_q_ac[0+:15],_q_ret[15+:1]};
_d_ret = {_q_ret[0+:15],1'b0};
// __block_10
end
// __block_11
_d_i = _q_i+1;
// __block_12
_d_index = 1;
end else begin
_d_index = 2;
end
end
2: begin
// __block_3
_d_index = 3;
end
3: begin // end of 
end
default: begin 
_d_index = {2{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase
// _always_post
end

always @(posedge clock) begin
_q_ac <= _d_ac;
_q_i <= (reset | ~in_run) ? 0 : _d_i;
_q_ret <= (reset | ~in_run) ? 0 : _d_ret;
_q_index <= reset ? 3 : ( ~in_run ? 0 : _d_index);
end

endmodule