module ARITH ( a, b, sel, out1 );
  input [4:0] a, b;
  input sel;
  output [4:0] out1;
  reg [4:0] out1;

always @(sel, a, b)

  begin
    case({sel})
        1'b0: out1 <= a + b;
        1'b1: out1 <= a - b;
    endcase
  end



endmodule