module a(clock,
		a_in,
		b_in,
		out);

input	clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0]    out;
reg [`BITS-1:0]    out;
wire [`BITS-1:0] temp;

d mya_d(clock, a_in[0], b_in[0], temp[0]);
d mya_d2(clock, a_in[1], b_in[0], temp[1]);

always @(posedge clock)
begin
	out <= a_in + b_in + temp;
end

endmodule