module adder_8bit(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output [7:0] sum,
    output cout
);
    wire[6:0] carry;

    genvar i;
    generate
        for(i = 0; i < 7; i = i + 1) begin : gen_full_adder
            if (i == 0) begin
                full_adder_1bit fa(a[i], b[i], cin, sum[i], carry[i]);
            end else begin
                full_adder_1bit fa(a[i], b[i], carry[i-1], sum[i], carry[i]);
            end
        end
    endgenerate

    full_adder_1bit fa_last(a[7], b[7], carry[6], sum[7], cout);
endmodule