module buslvds(
	doutp,
	oe,
	din,
	p,
	n
);


input wire	doutp;
input wire	oe;
output wire	din;
inout wire	p;
inout wire	n;
wire oebout;
wire oeout;

wire	[0:0] SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;





pdo	b2v_inst(
	.i(doutp),
	.oein(oe),
	.o(SYNTHESIZED_WIRE_2),
	.obar(SYNTHESIZED_WIRE_3),
	.oebout(oebout),
	.oeout(oeout));

assign	din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;

assign	SYNTHESIZED_WIRE_1 =  ~oe;


twentynm_io_obuf	b2v_inst3(
	.i(SYNTHESIZED_WIRE_2),
	.oe(oeout),
	.o(p),
	.obar());


twentynm_io_obuf	b2v_inst4(
	.i(SYNTHESIZED_WIRE_3),
	.oe(oebout),
	.o(n),
	.obar());


diffin	b2v_inst5(
	.datain(p),
	.datain_b(n),
	.dataout(SYNTHESIZED_WIRE_0));


endmodule