module mactable_dpcam_dpram #(
	parameter ADDR_WIDTH = 8,
	parameter DATA_WIDTH = 8,
	parameter RAM_STYLE = "block"
)
(
	input wire clk,
	input wire [DATA_WIDTH-1:0]dina,
	input wire [ADDR_WIDTH-1:0]addra,
	input wire [ADDR_WIDTH-1:0]addrb,
	input wire wea,
	output wire [DATA_WIDTH-1:0]douta,
	output wire [DATA_WIDTH-1:0]doutb
);

(* ram_style = RAM_STYLE *) reg [DATA_WIDTH-1:0]ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0]rdouta; 
reg [ADDR_WIDTH-1:0]rdoutb;
integer i;

assign douta = rdouta;
assign doutb = rdoutb;

initial begin
	for (i = 0; i < 2**ADDR_WIDTH; i = i + 1) begin
		ram[i] = 0;
	end
end

always @(posedge clk) begin
	if (wea) begin
		ram[addra] <= dina;
	end
	rdouta <= ram[addra];
	rdoutb <= ram[addrb];
end

endmodule