module delay_bit #(
	parameter integer DELAY = 1
)(
	input  wire d,
	output wire q,
	input  wire clk
);

	reg [DELAY-1:0] dl;

	generate
		if (DELAY > 1)
			always @(posedge clk)
				dl <= { dl[DELAY-2:0], d };
		else
			always @(posedge clk)
				dl <= d;
	endgenerate

	assign q = dl[DELAY-1];

endmodule // delay_bit