module nor_sel(
  //input
  data_in,
  sel_in,
  //out
  data_out
);
parameter    SEL_BIT  = 5;
parameter    SEL_NUM  = 32;
parameter    DATA     = 10;

input   [SEL_NUM*DATA-1:0]        data_in;
input   [SEL_BIT-1:0]                 sel_in;

output  [DATA-1:0]                data_out;


//wire definition
wire [SEL_NUM-1:0]          sel_onehot;
wire [(SEL_NUM+1)*DATA-1:0] tmp_sel_out; 
//reg definition


assign tmp_sel_out[DATA-1:0]  = {DATA{1'b0}};
generate
genvar i;
for(i=0;i<SEL_NUM;i=i+1)
begin: SEL_OUT
  assign sel_onehot[i]                 = sel_in[SEL_BIT-1:0] == i;
  assign tmp_sel_out[(i+1)*DATA+:DATA] = ({DATA{sel_onehot[i]}} & data_in[DATA*i+:DATA])
                                        | tmp_sel_out[DATA*i+:DATA];
end
endgenerate
assign data_out[DATA-1:0]             = tmp_sel_out[DATA*SEL_NUM+:DATA];

endmodule