module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE);

    parameter INIT = 16'h0000;

    output O;

    input  A0, A1, A2, A3, D, WCLK, WE;

    reg  [15:0] mem;
    wire [3:0] adr;

    assign adr = {A3, A2, A1, A0};
    assign O = mem[adr];

    initial
        mem = INIT;

    always @(negedge WCLK)
        if (WE == 1'b1)
            mem[adr] <= #100 D;

endmodule