module multiplier (
	output [31:0] multiplier_result,
	input [31:0] op1,
	input [31:0] op2,
	input [1:0] mul_sel
);
	wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
	wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};

	reg [63:0] result;

	always @ (*) begin
		case (mul_sel)
			`MUL_LO, `MUL_HI:
				result = $signed(sext_op1) * $signed(sext_op2);
			`MUL_HI_SU:
				result = $signed(sext_op1) * {32'h0, op2};
			`MUL_HI_UU:
				result = {32'h0, op1} * {32'h0, op2};
			default:
				result = 0;
		endcase
	end

	assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule