module data_arrays_0_ext(
  input RW0_clk,
  input [5:0] RW0_addr,
  input RW0_en,
  input RW0_wmode,
  input [3:0] RW0_wmask,
  input [31:0] RW0_wdata,
  output [31:0] RW0_rdata
);

  fakeram45_64x32 mem (
    .clk      (RW0_clk   ),
    .rd_out   (RW0_rdata  ),
    .ce_in    (RW0_en    ),
    .we_in    (RW0_wmode     ),
    .w_mask_in({  {8{RW0_wmask[3]}}
                 ,{8{RW0_wmask[2]}}
                 ,{8{RW0_wmask[1]}}
                 ,{8{RW0_wmask[0]}}}
      ),
    .addr_in  (RW0_addr  ),
    .wd_in    (RW0_wdata  )
  );

endmodule