module 	c(clock, 
		c_in, 
		d_in, 
		out1);

// SIGNAL DECLARATIONS
input	clock;
input c_in;
input d_in;
output  out1;
wire     out1;
wire temp;
wire temp2;

d myc_d(clock, c_in, d_in, temp2);

assign out1 = temp + d_in;
assign temp = c_in + temp2;

endmodule