module or1200_dc_fsm_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		
	// Clock and reset
	clk, rst,

	// Internal i/f to top level DC
	dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
	tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
	dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
	burst, tag_we, dc_addr
);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg  dc_en_cml_3;
reg  dc_en_cml_2;
reg  dc_en_cml_1;
reg  dcqmem_ci_i_cml_3;
reg  dcqmem_ci_i_cml_2;
reg  dcqmem_ci_i_cml_1;
reg  tagcomp_miss_cml_3;
reg  tagcomp_miss_cml_2;
reg  tagcomp_miss_cml_1;
reg  biudata_valid_cml_3;
reg  biudata_valid_cml_2;
reg  biudata_valid_cml_1;
reg  biudata_error_cml_3;
reg  biudata_error_cml_2;
reg [ 31 : 0 ] start_addr_cml_3;
reg [ 31 : 0 ] saved_addr_cml_2;
reg [ 31 : 0 ] saved_addr_cml_1;
reg  biu_read_cml_3;
reg [ 31 : 0 ] saved_addr_r_cml_3;
reg [ 31 : 0 ] saved_addr_r_cml_2;
reg [ 31 : 0 ] saved_addr_r_cml_1;
reg [ 2 : 0 ] state_cml_3;
reg [ 2 : 0 ] state_cml_2;
reg [ 2 : 0 ] state_cml_1;
reg [ 2 : 0 ] cnt_cml_3;
reg [ 2 : 0 ] cnt_cml_2;
reg [ 2 : 0 ] cnt_cml_1;
reg  hitmiss_eval_cml_3;
reg  hitmiss_eval_cml_2;
reg  hitmiss_eval_cml_1;
reg  store_cml_3;
reg  store_cml_2;
reg  store_cml_1;
reg  load_cml_3;
reg  load_cml_2;
reg  load_cml_1;
reg  cache_inhibit_cml_3;
reg  cache_inhibit_cml_2;
reg  cache_inhibit_cml_1;
reg  first_store_hit_ack_cml_3;
reg  first_store_hit_ack_cml_2;
reg  first_store_hit_ack_cml_1;



//
// I/O
//
input				clk;
input				rst;
input				dc_en;
input				dcqmem_cycstb_i;
input				dcqmem_ci_i;
input				dcqmem_we_i;
input	[3:0]			dcqmem_sel_i;
input				tagcomp_miss;
input				biudata_valid;
input				biudata_error;
input	[31:0]			start_addr;
output	[31:0]			saved_addr;
output	[3:0]			dcram_we;
output				biu_read;
output				biu_write;
output				first_hit_ack;
output				first_miss_ack;
output				first_miss_err;
output				burst;
output				tag_we;
output	[31:0]			dc_addr;

//
// Internal wires and regs
//
reg	[31:0]			saved_addr_r;
reg	[2:0]			state;
reg	[2:0]			cnt;
reg				hitmiss_eval;
reg				store;
reg				load;
reg				cache_inhibit;
wire				first_store_hit_ack;

//
// Generate of DCRAM write enables
//

// SynEDA CoreMultiplier
// assignment(s): dcram_we
// replace(s): biudata_valid, load, cache_inhibit, first_store_hit_ack
assign dcram_we = {4{load_cml_3 & biudata_valid_cml_3 & !cache_inhibit_cml_3}} | {4{first_store_hit_ack_cml_3}} & dcqmem_sel_i;

// SynEDA CoreMultiplier
// assignment(s): tag_we
// replace(s): biudata_valid, biu_read, cache_inhibit
assign tag_we = biu_read_cml_3 & biudata_valid_cml_3 & !cache_inhibit_cml_3;

//
// BIU read and write
//

// SynEDA CoreMultiplier
// assignment(s): biu_read
// replace(s): tagcomp_miss, hitmiss_eval, load
assign biu_read = (hitmiss_eval_cml_2 & tagcomp_miss_cml_2) | (!hitmiss_eval_cml_2 & load_cml_2);

// SynEDA CoreMultiplier
// assignment(s): biu_write
// replace(s): store
assign biu_write = store_cml_2;


// SynEDA CoreMultiplier
// assignment(s): dc_addr
// replace(s): saved_addr, hitmiss_eval
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval_cml_2 ? saved_addr_cml_2 : start_addr;
assign saved_addr = saved_addr_r;

//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;

// SynEDA CoreMultiplier
// assignment(s): first_miss_err
// replace(s): state
assign first_miss_err = ((state_cml_1 == `OR1200_DCFSM_CLOAD) | (state_cml_1 == `OR1200_DCFSM_CSTORE)) & biudata_error;

//
// Assert burst when doing reload of complete cache line
//

// SynEDA CoreMultiplier
// assignment(s): burst
// replace(s): tagcomp_miss, state, cache_inhibit
assign burst = (state_cml_3 == `OR1200_DCFSM_CLOAD) & tagcomp_miss_cml_3 & !cache_inhibit_cml_3
		| (state_cml_3 == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
		| (state_cml_3 == `OR1200_DCFSM_SREFILL4)
`endif
		;

//
// Main DC FSM
//

// SynEDA CoreMultiplier
// assignment(s): saved_addr_r, state, cnt, hitmiss_eval, store, load, cache_inhibit
// replace(s): dc_en, dcqmem_ci_i, tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr_r, state, cnt, hitmiss_eval, cache_inhibit, store, load
always @(posedge clk or posedge rst) begin
	if (rst) begin
		state <= #1 `OR1200_DCFSM_IDLE;
		saved_addr_r <= #1 32'b0;
		hitmiss_eval <= #1 1'b0;
		store <= #1 1'b0;
		load <= #1 1'b0;
		cnt <= #1 3'b000;
		cache_inhibit <= #1 1'b0;
	end
	else begin  cache_inhibit <= cache_inhibit_cml_3; load <= load_cml_3; store <= store_cml_3; hitmiss_eval <= hitmiss_eval_cml_3; cnt <= cnt_cml_3; state <= state_cml_3; saved_addr_r <= saved_addr_r_cml_3;
	case (state_cml_3)	// synopsys parallel_case
		`OR1200_DCFSM_IDLE :
			if (dc_en_cml_3 & dcqmem_cycstb_i & dcqmem_we_i) begin	// store
				state <= #1 `OR1200_DCFSM_CSTORE;
				saved_addr_r <= #1 start_addr_cml_3;
				hitmiss_eval <= #1 1'b1;
				store <= #1 1'b1;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else if (dc_en_cml_3 & dcqmem_cycstb_i) begin		// load
				state <= #1 `OR1200_DCFSM_CLOAD;
				saved_addr_r <= #1 start_addr_cml_3;
				hitmiss_eval <= #1 1'b1;
				store <= #1 1'b0;
				load <= #1 1'b1;
				cache_inhibit <= #1 1'b0;
			end
			else begin							// idle
				hitmiss_eval <= #1 1'b0;
				store <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
		`OR1200_DCFSM_CLOAD: begin		// load
			if (dcqmem_cycstb_i & dcqmem_ci_i_cml_3)
				cache_inhibit <= #1 1'b1;
			if (hitmiss_eval_cml_3)
				saved_addr_r[31:13] <= #1 start_addr_cml_3[31:13];
			if ((hitmiss_eval_cml_3 & !dcqmem_cycstb_i) ||					// load aborted (usually caused by DMMU)
			    (biudata_error_cml_3) ||										// load terminated with an error
			    ((cache_inhibit_cml_3 | dcqmem_ci_i_cml_3) & biudata_valid_cml_3)) begin	// load from cache-inhibited area
				state <= #1 `OR1200_DCFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else if (tagcomp_miss_cml_3 & biudata_valid_cml_3) begin	// load missed, finish current external load and refill
				state <= #1 `OR1200_DCFSM_LREFILL3;
				saved_addr_r[3:2] <= #1 saved_addr_r_cml_3[3:2] + 1'd1;
				hitmiss_eval <= #1 1'b0;
				cnt <= #1 `OR1200_DCLS-2;
				cache_inhibit <= #1 1'b0;
			end
			else if (!tagcomp_miss_cml_3 & !dcqmem_ci_i_cml_3) begin	// load hit, finish immediately
				state <= #1 `OR1200_DCFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				load <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else						// load in-progress
				hitmiss_eval <= #1 1'b0;
		end
		`OR1200_DCFSM_LREFILL3 : begin
			if (biudata_valid_cml_3 && (|cnt_cml_3)) begin		// refill ack, more loads to come
				cnt <= #1 cnt_cml_3 - 3'd1;
				saved_addr_r[3:2] <= #1 saved_addr_r_cml_3[3:2] + 1'd1;
			end
			else if (biudata_valid_cml_3) begin			// last load of line refill
				state <= #1 `OR1200_DCFSM_IDLE;
				load <= #1 1'b0;
			end
		end
		`OR1200_DCFSM_CSTORE: begin		// store
			if (dcqmem_cycstb_i & dcqmem_ci_i_cml_3)
				cache_inhibit <= #1 1'b1;
			if (hitmiss_eval_cml_3)
				saved_addr_r[31:13] <= #1 start_addr_cml_3[31:13];
			if ((hitmiss_eval_cml_3 & !dcqmem_cycstb_i) ||	// store aborted (usually caused by DMMU)
			    (biudata_error_cml_3) ||						// store terminated with an error
			    ((cache_inhibit_cml_3 | dcqmem_ci_i_cml_3) & biudata_valid_cml_3)) begin	// store to cache-inhibited area
				state <= #1 `OR1200_DCFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				store <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
`ifdef OR1200_DC_STORE_REFILL
			else if (tagcomp_miss_cml_3 & biudata_valid_cml_3) begin	// store missed, finish write-through and doq load refill
				state <= #1 `OR1200_DCFSM_SREFILL4;
				hitmiss_eval <= #1 1'b0;
				store <= #1 1'b0;
				load <= #1 1'b1;
				cnt <= #1 `OR1200_DCLS-1;
				cache_inhibit <= #1 1'b0;
			end
`endif
			else if (biudata_valid_cml_3) begin			// store hit, finish write-through
				state <= #1 `OR1200_DCFSM_IDLE;
				hitmiss_eval <= #1 1'b0;
				store <= #1 1'b0;
				cache_inhibit <= #1 1'b0;
			end
			else						// store write-through in-progress
				hitmiss_eval <= #1 1'b0;
			end
`ifdef OR1200_DC_STORE_REFILL
		`OR1200_DCFSM_SREFILL4 : begin
			if (biudata_valid_cml_3 && (|cnt_cml_3)) begin		// refill ack, more loads to come
				cnt <= #1 cnt_cml_3 - 1'd1;
				saved_addr_r[3:2] <= #1 saved_addr_r_cml_3[3:2] + 1'd1;
			end
			else if (biudata_valid_cml_3) begin			// last load of line refill
				state <= #1 `OR1200_DCFSM_IDLE;
				load <= #1 1'b0;
			end
		end
`endif
		default:
			state <= #1 `OR1200_DCFSM_IDLE;
	endcase end
end


always @ (posedge clk_i_cml_1) begin
dc_en_cml_1 <= dc_en;
dcqmem_ci_i_cml_1 <= dcqmem_ci_i;
tagcomp_miss_cml_1 <= tagcomp_miss;
biudata_valid_cml_1 <= biudata_valid;
saved_addr_cml_1 <= saved_addr;
saved_addr_r_cml_1 <= saved_addr_r;
state_cml_1 <= state;
cnt_cml_1 <= cnt;
hitmiss_eval_cml_1 <= hitmiss_eval;
store_cml_1 <= store;
load_cml_1 <= load;
cache_inhibit_cml_1 <= cache_inhibit;
first_store_hit_ack_cml_1 <= first_store_hit_ack;
end
always @ (posedge clk_i_cml_2) begin
dc_en_cml_2 <= dc_en_cml_1;
dcqmem_ci_i_cml_2 <= dcqmem_ci_i_cml_1;
tagcomp_miss_cml_2 <= tagcomp_miss_cml_1;
biudata_valid_cml_2 <= biudata_valid_cml_1;
biudata_error_cml_2 <= biudata_error;
saved_addr_cml_2 <= saved_addr_cml_1;
saved_addr_r_cml_2 <= saved_addr_r_cml_1;
state_cml_2 <= state_cml_1;
cnt_cml_2 <= cnt_cml_1;
hitmiss_eval_cml_2 <= hitmiss_eval_cml_1;
store_cml_2 <= store_cml_1;
load_cml_2 <= load_cml_1;
cache_inhibit_cml_2 <= cache_inhibit_cml_1;
first_store_hit_ack_cml_2 <= first_store_hit_ack_cml_1;
end
always @ (posedge clk_i_cml_3) begin
dc_en_cml_3 <= dc_en_cml_2;
dcqmem_ci_i_cml_3 <= dcqmem_ci_i_cml_2;
tagcomp_miss_cml_3 <= tagcomp_miss_cml_2;
biudata_valid_cml_3 <= biudata_valid_cml_2;
biudata_error_cml_3 <= biudata_error_cml_2;
start_addr_cml_3 <= start_addr;
biu_read_cml_3 <= biu_read;
saved_addr_r_cml_3 <= saved_addr_r_cml_2;
state_cml_3 <= state_cml_2;
cnt_cml_3 <= cnt_cml_2;
hitmiss_eval_cml_3 <= hitmiss_eval_cml_2;
store_cml_3 <= store_cml_2;
load_cml_3 <= load_cml_2;
cache_inhibit_cml_3 <= cache_inhibit_cml_2;
first_store_hit_ack_cml_3 <= first_store_hit_ack_cml_2;
end
endmodule