module ram_16x1k_dp (
  clka,
  ena,
  wea,
  addra,
  dina,
  douta,
  clkb,
  enb,
  web,
  addrb,
  dinb,
  doutb
);

  input clka;
  input ena;
  input [1 : 0] wea;
  input [9 : 0] addra;
  input [15 : 0] dina;
  output [15 : 0] douta;
  input clkb;
  input enb;
  input [1 : 0] web;
  input [9 : 0] addrb;
  input [15 : 0] dinb;
  output [15 : 0] doutb;

  // WARNING: This file provides a module declaration only, it does not support
  //          direct instantiation. Please use an instantiation template (VEO) to
  //          instantiate the IP within a design.

endmodule