module skew_channels (
    input clk,
    input [79:0]  in_data,
    output [79:0] out_data
    );

  reg [59:0] delay0;
  reg [39:0] delay1;
  reg [19:0] delay2;

  assign out_data[79:60] = delay2[19:0];
  assign out_data[59:40] = delay1[19:0];
  assign out_data[39:20] = delay0[19:0];
  assign out_data[19:0]  = in_data[19:0];

always @(posedge clk) begin
    delay2 <= delay1[39:20];
    delay1 <= delay0[59:20];
    delay0 <= in_data[79:20];
end

endmodule