module bsg_front_side_bus_hop_in
(
  clk_i,
  reset_i,
  ready_o,
  v_i,
  data_i,
  v_o,
  data_o,
  ready_i
);

  input [15:0] data_i;
  output [4:0] v_o;
  output [79:0] data_o;
  input [4:0] ready_i;
  input clk_i;
  input reset_i;
  input v_i;
  output ready_o;
  wire [4:0] v_o,sent_r,sent_n;
  wire [79:0] data_o;
  wire ready_o,N0,N1,N2,N3,N4,data_o_0__15_,data_o_0__14_,data_o_0__13_,data_o_0__12_,
  data_o_0__11_,data_o_0__10_,data_o_0__9_,data_o_0__8_,data_o_0__7_,data_o_0__6_,
  data_o_0__5_,data_o_0__4_,data_o_0__3_,data_o_0__2_,data_o_0__1_,data_o_0__0_,
  fifo_v,fifo_yumi,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
  N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
  reg sent_r_0_sv2v_reg,sent_r_1_sv2v_reg,sent_r_2_sv2v_reg,sent_r_3_sv2v_reg,
  sent_r_4_sv2v_reg;
  assign sent_r[0] = sent_r_0_sv2v_reg;
  assign sent_r[1] = sent_r_1_sv2v_reg;
  assign sent_r[2] = sent_r_2_sv2v_reg;
  assign sent_r[3] = sent_r_3_sv2v_reg;
  assign sent_r[4] = sent_r_4_sv2v_reg;
  assign data_o[15] = data_o_0__15_;
  assign data_o[31] = data_o_0__15_;
  assign data_o[47] = data_o_0__15_;
  assign data_o[63] = data_o_0__15_;
  assign data_o[79] = data_o_0__15_;
  assign data_o[14] = data_o_0__14_;
  assign data_o[30] = data_o_0__14_;
  assign data_o[46] = data_o_0__14_;
  assign data_o[62] = data_o_0__14_;
  assign data_o[78] = data_o_0__14_;
  assign data_o[13] = data_o_0__13_;
  assign data_o[29] = data_o_0__13_;
  assign data_o[45] = data_o_0__13_;
  assign data_o[61] = data_o_0__13_;
  assign data_o[77] = data_o_0__13_;
  assign data_o[12] = data_o_0__12_;
  assign data_o[28] = data_o_0__12_;
  assign data_o[44] = data_o_0__12_;
  assign data_o[60] = data_o_0__12_;
  assign data_o[76] = data_o_0__12_;
  assign data_o[11] = data_o_0__11_;
  assign data_o[27] = data_o_0__11_;
  assign data_o[43] = data_o_0__11_;
  assign data_o[59] = data_o_0__11_;
  assign data_o[75] = data_o_0__11_;
  assign data_o[10] = data_o_0__10_;
  assign data_o[26] = data_o_0__10_;
  assign data_o[42] = data_o_0__10_;
  assign data_o[58] = data_o_0__10_;
  assign data_o[74] = data_o_0__10_;
  assign data_o[9] = data_o_0__9_;
  assign data_o[25] = data_o_0__9_;
  assign data_o[41] = data_o_0__9_;
  assign data_o[57] = data_o_0__9_;
  assign data_o[73] = data_o_0__9_;
  assign data_o[8] = data_o_0__8_;
  assign data_o[24] = data_o_0__8_;
  assign data_o[40] = data_o_0__8_;
  assign data_o[56] = data_o_0__8_;
  assign data_o[72] = data_o_0__8_;
  assign data_o[7] = data_o_0__7_;
  assign data_o[23] = data_o_0__7_;
  assign data_o[39] = data_o_0__7_;
  assign data_o[55] = data_o_0__7_;
  assign data_o[71] = data_o_0__7_;
  assign data_o[6] = data_o_0__6_;
  assign data_o[22] = data_o_0__6_;
  assign data_o[38] = data_o_0__6_;
  assign data_o[54] = data_o_0__6_;
  assign data_o[70] = data_o_0__6_;
  assign data_o[5] = data_o_0__5_;
  assign data_o[21] = data_o_0__5_;
  assign data_o[37] = data_o_0__5_;
  assign data_o[53] = data_o_0__5_;
  assign data_o[69] = data_o_0__5_;
  assign data_o[4] = data_o_0__4_;
  assign data_o[20] = data_o_0__4_;
  assign data_o[36] = data_o_0__4_;
  assign data_o[52] = data_o_0__4_;
  assign data_o[68] = data_o_0__4_;
  assign data_o[3] = data_o_0__3_;
  assign data_o[19] = data_o_0__3_;
  assign data_o[35] = data_o_0__3_;
  assign data_o[51] = data_o_0__3_;
  assign data_o[67] = data_o_0__3_;
  assign data_o[2] = data_o_0__2_;
  assign data_o[18] = data_o_0__2_;
  assign data_o[34] = data_o_0__2_;
  assign data_o[50] = data_o_0__2_;
  assign data_o[66] = data_o_0__2_;
  assign data_o[1] = data_o_0__1_;
  assign data_o[17] = data_o_0__1_;
  assign data_o[33] = data_o_0__1_;
  assign data_o[49] = data_o_0__1_;
  assign data_o[65] = data_o_0__1_;
  assign data_o[0] = data_o_0__0_;
  assign data_o[16] = data_o_0__0_;
  assign data_o[32] = data_o_0__0_;
  assign data_o[48] = data_o_0__0_;
  assign data_o[64] = data_o_0__0_;

  bsg_two_fifo_width_p16
  fifo
  (
    .clk_i(clk_i),
    .reset_i(reset_i),
    .ready_o(ready_o),
    .data_i(data_i),
    .v_i(v_i),
    .v_o(fifo_v),
    .data_o({ data_o_0__15_, data_o_0__14_, data_o_0__13_, data_o_0__12_, data_o_0__11_, data_o_0__10_, data_o_0__9_, data_o_0__8_, data_o_0__7_, data_o_0__6_, data_o_0__5_, data_o_0__4_, data_o_0__3_, data_o_0__2_, data_o_0__1_, data_o_0__0_ }),
    .yumi_i(fifo_yumi)
  );

  assign sent_n[0] = (N0)? 1'b1 : 
                     (N7)? sent_r[0] : 1'b0;
  assign N0 = N6;
  assign sent_n[1] = (N1)? 1'b1 : 
                     (N10)? sent_r[1] : 1'b0;
  assign N1 = N9;
  assign sent_n[2] = (N2)? 1'b1 : 
                     (N13)? sent_r[2] : 1'b0;
  assign N2 = N12;
  assign sent_n[3] = (N3)? 1'b1 : 
                     (N16)? sent_r[3] : 1'b0;
  assign N3 = N15;
  assign sent_n[4] = (N4)? 1'b1 : 
                     (N19)? sent_r[4] : 1'b0;
  assign N4 = N18;
  assign v_o[0] = fifo_v & N20;
  assign N20 = ~sent_r[0];
  assign N5 = sent_n[0] & N21;
  assign N21 = ~fifo_yumi;
  assign N6 = v_o[0] & ready_i[0];
  assign N7 = ~N6;
  assign v_o[1] = fifo_v & N22;
  assign N22 = ~sent_r[1];
  assign N8 = sent_n[1] & N23;
  assign N23 = ~fifo_yumi;
  assign N9 = v_o[1] & ready_i[1];
  assign N10 = ~N9;
  assign v_o[2] = fifo_v & N24;
  assign N24 = ~sent_r[2];
  assign N11 = sent_n[2] & N25;
  assign N25 = ~fifo_yumi;
  assign N12 = v_o[2] & ready_i[2];
  assign N13 = ~N12;
  assign v_o[3] = fifo_v & N26;
  assign N26 = ~sent_r[3];
  assign N14 = sent_n[3] & N27;
  assign N27 = ~fifo_yumi;
  assign N15 = v_o[3] & ready_i[3];
  assign N16 = ~N15;
  assign v_o[4] = fifo_v & N28;
  assign N28 = ~sent_r[4];
  assign N17 = sent_n[4] & N29;
  assign N29 = ~fifo_yumi;
  assign N18 = v_o[4] & ready_i[4];
  assign N19 = ~N18;
  assign fifo_yumi = N32 & sent_n[0];
  assign N32 = N31 & sent_n[1];
  assign N31 = N30 & sent_n[2];
  assign N30 = sent_n[4] & sent_n[3];

  always @(posedge clk_i) begin
    if(reset_i) begin
      sent_r_0_sv2v_reg <= 1'b0;
      sent_r_1_sv2v_reg <= 1'b0;
      sent_r_2_sv2v_reg <= 1'b0;
      sent_r_3_sv2v_reg <= 1'b0;
      sent_r_4_sv2v_reg <= 1'b0;
    end else if(1'b1) begin
      sent_r_0_sv2v_reg <= N5;
      sent_r_1_sv2v_reg <= N8;
      sent_r_2_sv2v_reg <= N11;
      sent_r_3_sv2v_reg <= N14;
      sent_r_4_sv2v_reg <= N17;
    end 
  end


endmodule