module RAM128X1D (DPO, SPO, A, D, DPRA, WCLK, WE);

    parameter INIT = 128'h0;

    output DPO, SPO;

    input  [6:0] A;
    input  [6:0] DPRA;
    input  D;
    input  WCLK;
    input  WE;

    reg [127:0] mem;


    assign SPO = mem[A];
    assign DPO = mem[DPRA];


    initial 
         mem = INIT;

    always @(posedge WCLK) 
	if (WE == 1'b1)
	    mem[A] <= #100 D;


endmodule