module adder_sat_8(
    input wire [7:0] a, // unsigned
    input wire [7:0] b, // signed
    output wire [7:0] c // unsigned
);

    wire [8:0] a_ext = {1'b0, a};
    wire [8:0] b_ext = {b[7], b};
    wire [8:0] add = a_ext + b_ext;
    assign c = add[8] ? (b[7] ? (8'h00) : (8'hFF)) : (add[7:0]);

endmodule