module delay_bit #(
	parameter integer DELAY = 1
)(
	input  wire d,
	output wire q,
	input  wire clk
);

	// Signals
	wire [4:0] addr = DELAY - 2;
	wire ff_in;

	// Generate SRL if needed (or bypass if not)
	generate
		if (DELAY > 17) begin
			SRLC32E srl_I (
				.Q(ff_in),
				.A(addr),
				.CE(1'b1),
				.CLK(clk),
				.D(d)
			);
		end else if (DELAY > 1) begin
			SRL16E srl_I (
				.Q(ff_in),
				.A0(addr[0]),
				.A1(addr[1]),
				.A2(addr[2]),
				.A3(addr[3]),
				.CE(1'b1),
				.CLK(clk),
				.D(d)
			);
		end else begin
			assign ff_in = d;
		end
	endgenerate

	// Generate flip-flop if needed (or bypass if not)
	generate
		if (DELAY > 0) begin
			FDRE ff_I (
				.Q(q),
				.C(clk),
				.CE(1'b1),
				.D(ff_in),
				.R(1'b0)
			);
		end else begin
			assign q = ff_in;
		end
	endgenerate

endmodule // delay_bit