module tb_compare;

    reg clk = 1'b0;


initial begin
        forever #10 clk = ~clk; // generate a clock
    end     

    wire  [2:0] stream_channel_count;
    wire [72:0] data;
    wire        ready;

    wire  [2:0] v_stream_channel_count;
    wire [72:0] v_data;
    wire        v_ready;


test_source i_test_source(
    .clk                  (clk),
    .stream_channel_count (stream_channel_count),
    .ready                (ready),
    .data                 (data)
);

test_source_cmp i_v_test_source_cmp(
    .clk                  (clk),
    .stream_channel_count (v_stream_channel_count),
    .ready                (v_ready),
    .data                 (v_data)
);

    wire [72:0] diff = data ^ v_data;
endmodule