module BusVsBus (SB, DB, ADH, SB_DB, SB_ADH);

	inout [7:0] SB;
	inout [7:0] DB;
	inout [7:0] ADH;
	input SB_DB;
	input SB_ADH;

	tranif1 sb_db [7:0] (SB, DB, {8{SB_DB}});
	tranif1 sb_adh [7:0] (SB, ADH, {8{SB_ADH}});

endmodule // BusVsBus