module i2c_interconnect
(
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_I" *)    output  wire    s0_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_O" *)    input   wire    s0_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_T" *)    input   wire    s0_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_I" *)    output  wire    s0_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_O" *)    input   wire    s0_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_T" *)    input   wire    s0_sda_t,
    
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_I" *)    output  wire    s1_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_O" *)    input   wire    s1_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_T" *)    input   wire    s1_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_I" *)    output  wire    s1_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_O" *)    input   wire    s1_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_T" *)    input   wire    s1_sda_t,

    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_I" *)     input   wire    m_scl_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_O" *)     output  wire    m_scl_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_T" *)     output  wire    m_scl_t,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_I" *)     input   wire    m_sda_i,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_O" *)     output  wire    m_sda_o,
    (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_T" *)     output  wire    m_sda_t
);

/*-------------------------------------------------------------------------------------------------------------------------------------*/ 

    assign s0_scl_i = m_scl_i;
    assign s1_scl_i = m_scl_i;
    
    assign s0_sda_i = m_sda_i;
    assign s1_sda_i = m_sda_i;
    
    assign m_scl_o = s0_scl_o & s1_scl_o;
    assign m_scl_t = s0_scl_t & s1_scl_t;
    
    assign m_sda_o = s0_sda_o & s1_sda_o;
    assign m_sda_t = s0_sda_t & s1_sda_t;
    
endmodule