module top_memory (
clk         , // Clock Input
address     , // Address Input
data_in     , // 
data_out1    , // 
data_out2    , // 
data_out3    , // 
cs          , // Chip Select
we          , // Write Enable/Read Enable
oe            // Output Enable
);

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;

//--------------Input Ports----------------------- 
input                  clk         ;
input [ADDR_WIDTH-1:0] address     ;
input                  cs          ;
input                  we          ;
input                  oe          ; 
input [DATA_WIDTH-1:0] data_in     ;

//--------------Inout Ports----------------------- 
output [DATA_WIDTH-1:0]  data_out1   ;
output [DATA_WIDTH-1:0]  data_out2   ;
output [DATA_WIDTH-1:0]  data_out3   ;

    ram_sp_sr_sw mem1 (.clk(clk), .address(address), .data_in(data_in),
		       .data_out(data_out1), .cs(cs), .we(we), .oe(oe) );

    ram_sp_ar_sw mem2 (.clk(clk), .address(address), .data_in(data_in),
		       .data_out(data_out1), .cs(cs), .we(we), .oe(oe) );

    ram_sp_ar_aw mem3 (.address(address), .data_in(data_in),
		       .data_out(data_out1), .cs(cs), .we(we), .oe(oe) );

endmodule