module TB_WeightsRAM;
    reg clk;
    reg [2:0] addr;
    wire [127:0] weights;
    
    WeightsRAM_R uut( .clk(clk), .addr(addr), .weights(weights));
    
    always #5 clk = ~clk;
    
    initial begin
        clk = 0;
        addr = 3'd0;
        #10;
        addr = 3'd1;
        #10;
        addr = 3'd5;
        #10;
        addr = 3'd7;
        #10;
    end
    
    
endmodule