module axi_dacfifo_address_buffer #(

  parameter ADDRESS_WIDTH = 4,
  parameter DATA_WIDTH = 16)(

  input                         clk,
  input                         rst,
  input                         wea,
  input      [DATA_WIDTH-1:0]   din,

  input                         rea,
  output     [DATA_WIDTH-1:0]   dout);

  reg   [ADDRESS_WIDTH-1:0]     waddr;
  reg   [ADDRESS_WIDTH-1:0]     raddr;


  always @(posedge clk) begin
    if (rst == 1'b1) begin
      waddr <= 0;
      raddr <= 0;
    end else begin
      waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr;
      raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr;
    end
  end

  ad_mem #(
    .DATA_WIDTH (DATA_WIDTH),
    .ADDRESS_WIDTH (ADDRESS_WIDTH))
  i_mem (
    .clka (clk),
    .wea (wea),
    .addra (waddr),
    .dina (din),
    .clkb (clk),
    .reb (1'b1),
    .addrb (raddr),
    .doutb (dout));

endmodule