module WRPORT ( WRITE, DRAM_Q, WRDATA, ENBYTE, VADDR, DADDR, WDAT, CAP_Q, ENB );

	input			WRITE;
	input  [127:0]	DRAM_Q;
	input	[31:0]	WRDATA;
	input	 [3:0]	ENBYTE;
	input	 [3:2]	VADDR;
	input	 [3:2]	DADDR;
	
	output [127:0]	WDAT;
	
	output	reg	[31:0]	CAP_Q;
	output	reg	[15:0]	ENB;
	
	assign WDAT = WRITE ? {WRDATA,WRDATA,WRDATA,WRDATA} : DRAM_Q;
	
	always @(DADDR or DRAM_Q)
	  case (DADDR)
	    2'b00 : CAP_Q = DRAM_Q[31:0];
		2'b01 : CAP_Q = DRAM_Q[63:32];
		2'b10 : CAP_Q = DRAM_Q[95:64];
		2'b11 : CAP_Q = DRAM_Q[127:96];
	  endcase
	  
	always @(WRITE or VADDR or ENBYTE)
	  case ({WRITE,VADDR})
	     3'b100 : ENB = {4'd0  ,4'd0  ,4'd0  ,ENBYTE};
	     3'b101 : ENB = {4'd0  ,4'd0  ,ENBYTE,4'd0  };
	     3'b110 : ENB = {4'd0  ,ENBYTE,4'd0  ,4'd0  };
	     3'b111 : ENB = {ENBYTE,4'd0  ,4'd0  ,4'd0  };
		default : ENB = 16'hFFFF;
	  endcase
	  
endmodule