module tiny1_soc(
                 input  clk,
                 input  rst, // external reset button

                 input  RXD,
                 output TXD,

                 output LED1,
                 output LED2,
                 output LED3,
                 output LED4,
                 output LED5
`ifndef ICESTICK
                 ,output LED6,
                 output LED7,
                 output LED8
`endif
                 );

   
	reg [7:0] resetn_counter = 0;
        wire           resetn = &resetn_counter;
  
	always @(posedge clk) begin
		if (!resetn)
			resetn_counter <= resetn_counter + 1;
	end


   
   wire [7:0]           leds;
   wire [7:0]           rleds;

   outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(leds[0]), .rd(rleds[0]));
   outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(leds[1]), .rd(rleds[1]));
   outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(leds[2]), .rd(rleds[2]));
   outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(leds[3]), .rd(rleds[3]));
   outpin led4 (.clk(clk), .we(1'b1), .pin(LED5), .wd(leds[4]), .rd(rleds[4]));
`ifndef ICESTICK
   outpin led5 (.clk(clk), .we(1'b1), .pin(LED6), .wd(leds[5]), .rd(rleds[5]));
   outpin led6 (.clk(clk), .we(1'b1), .pin(LED7), .wd(leds[6]), .rd(rleds[6]));
   outpin led7 (.clk(clk), .we(1'b1), .pin(LED8), .wd(leds[7]), .rd(rleds[7]));
`endif
   
   wire [7:0]           uart_din;
   wire                 uart_valid;
   wire                 uart_ready;
   wire                 uart_wr;
   wire                 uart_rd;
   
   wire [7:0]           uart_dout;

   tiny1_cpu cpu(.clk(clk),
                 .rst(resetn),
                 .uart_din(uart_din),
                 .uart_valid(uart_valid),
                 .uart_ready(uart_ready),
                 .uart_out(uart_dout),
                 .uart_rd(uart_rd),
                 .uart_wr(uart_wr),
                 .leds(leds)
                 );
   
   wire                 uart_RXD;
   inpin _rcxd(.clk(clk), .pin(RXD), .rd(uart_RXD));

   wire                 uart_busy;

   assign uart_ready = ~uart_busy;
   
   buart _uart (
                .clk(clk),
                .resetq(1'b1),
                .rx(uart_RXD),
                .tx(TXD),
                .rd(uart_rd),
                .wr(uart_wr),
                .valid(uart_valid),
                .busy(uart_busy),
                .tx_data(uart_dout),
                .rx_data(uart_din));
   
endmodule