module altr_hps_clkgate_or (
  clk,
  clk_gate,
  clk_o
);

// -------------------
// Port declarations
// -------------------

input clk;
input clk_gate;
output clk_o;

// -----
// RTL
// -----

`ifdef ALTR_HPS_INTEL_MACROS_OFF
//assign clk_o = clk | clk_gate;
//fixed behavioral model to match cgc81
reg clk_enable_lat;
 
always @ (clk or clk_gate)
  begin
    if (clk)
      clk_enable_lat <= clk_gate;
  end
 
assign clk_o = clk | clk_enable_lat;

`else

`endif

endmodule