module sin_dds(clk,rst_n,fword,pword,data_out,data_change);
`define OUT_WIDTH 8
`define ADDR_WIDTH 10

input clk;      //å®ä¹ç³»ç»æ¶é
input rst_n;    //å¤ä½ä¿¡å·
input [`ADDR_WIDTH-1:0]fword;           //å®ä¹é¢çæ§å¶å­
input [`ADDR_WIDTH-1:0]pword;           //å®ä¹ç¸ä½æ§å¶å­
 
output [`OUT_WIDTH-1:0] data_out;      //è¾åºæ³¢å½¢æ°æ®
output data_change;          //æ³¢å½¢æ°æ®åçæ¹åæ å¿ä½

//------------------------------ç¸ä½ç´¯å å¨é¨å-----------------------------
reg [`ADDR_WIDTH-1:0] fre_add;
always @ (posedge clk or negedge rst_n) begin 
   if(!rst_n) fre_add <= `ADDR_WIDTH'd0;
	else fre_add <= fre_add + fword;//ç¸ä½ç´¯å 
end
				  
reg [`ADDR_WIDTH-1:0] rom_addr;
always @ (posedge clk or negedge rst_n) begin 
    if(!rst_n)
    	rom_addr <= `ADDR_WIDTH'd0;
	else 
		rom_addr <= fre_add+pword;//æ³¢å½¢å°å
end 

//----------------------æ°æ®ååæ å¿ä½äº§çæ¨¡å----------------------
reg [`ADDR_WIDTH-1:0]register1;
reg [`ADDR_WIDTH-1:0]register2;
always @ (posedge clk or negedge rst_n) begin 
   if(!rst_n) begin
		 register1 <= `ADDR_WIDTH'd0;
		 register2 <= `ADDR_WIDTH'd0;
		 end
	 else begin 
	    register1 <= rom_addr;
		register2 <= register1;
	 end
end
assign  data_change = (register1 == register2)? 1'd0:1'd1;  
//ä¸¤æ¬¡æ°æ®æ¯è¾å¼ä¸åï¼è¯´ææ°æ®åçæ¹å

//-----------------------------ROMæ¨¡åä¾å------------------------------------
rom	rom_inst1 (
	.addra ( rom_addr ),
	.clka ( clk ),
	.douta ( data_out )
	);

endmodule 