module dspclkpll (
	inclk0,
	c0,
	c1);

	input	  inclk0;
	output	  c0;
	output	  c1;

	wire [5:0] sub_wire0;
	wire [0:0] sub_wire5 = 1'h0;
	wire [1:1] sub_wire2 = sub_wire0[1:1];
	wire [0:0] sub_wire1 = sub_wire0[0:0];
	wire  c0 = sub_wire1;
	wire  c1 = sub_wire2;
	wire  sub_wire3 = inclk0;
	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};

	altpll	altpll_component (
				.inclk (sub_wire4),
				.clk (sub_wire0)
				// synopsys translate_off
,
				.fbin (),
				.pllena (),
				.clkswitch (),
				.areset (),
				.pfdena (),
				.clkena (),
				.extclkena (),
				.scanclk (),
				.scanaclr (),
				.scandata (),
				.scanread (),
				.scanwrite (),
				.extclk (),
				.clkbad (),
				.activeclock (),
				.locked (),
				.clkloss (),
				.scandataout (),
				.scandone (),
				.sclkout1 (),
				.sclkout0 (),
				.enable0 (),
				.enable1 ()
				// synopsys translate_on

);
	defparam
		altpll_component.clk1_divide_by = 1,
		altpll_component.clk1_phase_shift = "0",
		altpll_component.clk0_duty_cycle = 50,
		altpll_component.lpm_type = "altpll",
		altpll_component.clk0_multiply_by = 1,
		altpll_component.inclk0_input_frequency = 15625,
		altpll_component.clk0_divide_by = 1,
		altpll_component.clk1_duty_cycle = 50,
		altpll_component.pll_type = "AUTO",
		altpll_component.clk1_multiply_by = 2,
		altpll_component.clk0_time_delay = "0",
		altpll_component.intended_device_family = "Cyclone",
		altpll_component.operation_mode = "NORMAL",
		altpll_component.compensate_clock = "CLK0",
		altpll_component.clk1_time_delay = "0",
		altpll_component.clk0_phase_shift = "0";


endmodule