module uart_out_np #( parameter ClockFrequency = 12000000, parameter BaudRate = 9600 )(
        input clock,
        input reset,

        input [7:0] out_data,
        input       out_valid,
        output      out_ready,

        output uart_tx
    );

    // Assert out_valid for (at least) one clock cycle to start transmission of out_data
    // out_data is latched so that it doesn't have to stay valid while it is being sent

    generate
        if( ClockFrequency < BaudRate * 8 && ( ClockFrequency % BaudRate != 0 ) ) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested BaudRate rate");
    endgenerate

    `ifdef SIMULATION
        wire BitTick = 1'b1;  // output one bit per clock cycle
    `else
        wire BitTick;
        uart_out_baudrate_gen #( ClockFrequency, BaudRate ) tickgen( .clock( clock ), .enable( ~out_ready ), .tick( BitTick ) );
    `endif

    reg [3:0] uart_state = 0;
    wire uart_ready = (uart_state==0);
    assign out_ready = uart_ready;

    reg [7:0] uart_shift = 0;
    always @(posedge clock)
    begin
        if ( reset ) begin
            uart_state <= 0;
        end else begin
            if( uart_ready & out_valid )
                uart_shift <= out_data;
            else
                if(uart_state[3] & BitTick)
                    uart_shift <= (uart_shift >> 1);

            case(uart_state)
                4'b0000: if(out_valid) uart_state <= 4'b0100;
                4'b0100: if(BitTick) uart_state <= 4'b1000;  // start bit
                4'b1000: if(BitTick) uart_state <= 4'b1001;  // bit 0
                4'b1001: if(BitTick) uart_state <= 4'b1010;  // bit 1
                4'b1010: if(BitTick) uart_state <= 4'b1011;  // bit 2
                4'b1011: if(BitTick) uart_state <= 4'b1100;  // bit 3
                4'b1100: if(BitTick) uart_state <= 4'b1101;  // bit 4
                4'b1101: if(BitTick) uart_state <= 4'b1110;  // bit 5
                4'b1110: if(BitTick) uart_state <= 4'b1111;  // bit 6
                4'b1111: if(BitTick) uart_state <= 4'b0010;  // bit 7
                4'b0010: if(BitTick) uart_state <= 4'b0000;  // stop1  -  state<=4'b0011 for stop2
                4'b0011: if(BitTick) uart_state <= 4'b0000;  // stop2
                default: if(BitTick) uart_state <= 4'b0000;
            endcase
        end
    end

    assign uart_tx = (uart_state<4) | (uart_state[3] & uart_shift[0]);  // put together the start, data and stop bits

endmodule