module counter_tb();

	reg clk, reset, enable;
	wire [3:0] counter1, counter2;

	initial begin
		$display("Time clk reset enable counter1 counter2");
		$monitor("%g %b %b %b %b %b",
			$time, clk, reset, enable, counter1, counter2);
		
		clk = 1;
		reset = 0;
		enable = 0;

		#5 reset = 1;
		#10 reset = 0;

		#5 enable = 1;
		#100 enable = 0;

		#10 $finish;
	end

	/* Clock generator */
	always begin
		#5 clk = ~clk;
	end

	counter counter_foo(clk, reset, enable, counter1);
	counter counter_bar(clk, reset, enable, counter2);

endmodule