module RS_E_MUX(RS_E_Sel,V1_E,RF_WD_M,RF_WD_W,RS_E);
//input
    input [31:0] RS_E_Sel;

    input [31:0] V1_E;
    input [31:0] RF_WD_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RS_E;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RS_E=V1_E;
            case(RS_E_Sel)
                M:RS_E=RF_WD_M;
                W:RS_E=RF_WD_W;
            endcase
        end

endmodule