module debounce(
    input       clk25,      // 25MHz clock
    input       rst,        // active high reset
    
    input       sig_in,     // input signal
    output reg  sig_out     // debounced output signal
);

wire clk_enb;       // enable triggering at clk25 divided by 64
reg [5:0] clk_div;  // clock divider counter

reg sig_ff1;        // first  input signal synchronizer
reg sig_ff2;        // second input signal synchronizer

assign clk_enb = (clk_div == 6'd0);

// clock divider
always @(posedge clk25 or posedge rst)
begin
    if (rst)
        clk_div <= 6'd0;
    else
        clk_div <= clk_div + 6'd1;
end

// debounce timer
always @(posedge clk25 or posedge rst)
begin
    if (rst)
    begin
        sig_out <= 1'b0;
        sig_ff1 <= 1'b0;
        sig_ff2 <= 1'b0;
    end
    else if (clk_enb)
    begin
        // this runs ar approximately 391k Hz
        // giving a debounce time of around 2.5us
        sig_ff1 <= sig_in;
        sig_ff2 <= sig_ff1;
        if ((sig_ff1 ^ sig_ff2) == 1'd0)
        begin
            sig_out <= sig_ff2;
        end
    end
end

endmodule