module aibio_pulsegen_top
		(
		//---------Supply pins----------//
		input vddcq,
		input vss,
		//---------Input pins----------//
		input [15:0] i_clkph,
		input [3:0] i_dll_even_phase1_sel,
		input [3:0] i_dll_odd_phase1_sel,
		input [3:0] i_dll_even_phase2_sel,
		input [3:0] i_dll_odd_phase2_sel,
		//--------Output pins-----------//
		output o_clk_even,
		output o_clk_odd,
		output o_pulseclk_even,
		output o_pulseclk_odd
		);

wire [3:0]dll_even_phase2_sel_int;
wire [3:0]dll_odd_phase2_sel_int;

wire dll_even_phase2_selb_3;
wire dll_odd_phase2_selb_3;

assign dll_even_phase2_selb_3 = ~i_dll_even_phase2_sel[3];
assign dll_odd_phase2_selb_3 = ~i_dll_odd_phase2_sel[3];
assign dll_even_phase2_sel_int = {dll_even_phase2_selb_3,i_dll_even_phase2_sel[2:0]};
assign dll_odd_phase2_sel_int = {dll_odd_phase2_selb_3,i_dll_odd_phase2_sel[2:0]};

assign o_clk_even = ~i_clkph[i_dll_even_phase1_sel];
assign o_clk_odd = ~i_clkph[i_dll_odd_phase1_sel];
assign o_pulseclk_even = o_clk_even && (i_clkph[dll_even_phase2_sel_int]);
assign o_pulseclk_odd = o_clk_odd && (i_clkph[dll_odd_phase2_sel_int]);

endmodule