module dual_port_ram #(parameter ADDR_WIDTH = 5, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
       
          output wire [DATA_WIDTH - 1 : 0]      dout
);

        reg [ADDR_WIDTH - 1 : 0] raddr_reg;
        reg [DATA_WIDTH - 1 : 0] mem [0 : (2**ADDR_WIDTH) - 1] /* synthesis syn_ramstyle="uram" */;

        assign dout = mem[raddr_reg] ;
        
        always @(posedge clk) begin
            raddr_reg <= raddr;
        end
        
        always@ (posedge clk) begin
            if (write_en) begin
                mem[waddr] <= din;
            end
        end

endmodule