module aibnd_inv ( clkout, clk, vccl_aibnd, vssl_aibnd );

output  clkout;

input  clk, vccl_aibnd, vssl_aibnd;

// List of primary aliased buses

/*
specify 
    specparam CDS_LIBNAME  = "aibnd_lib";
    specparam CDS_CELLNAME = "aibnd_inv";
    specparam CDS_VIEWNAME = "schematic";
endspecify
*/

assign clkout = ~clk ; 

endmodule