module \$__CC_BRAM_20K_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 14;
	parameter CFG_DBITS = 20;
	parameter CFG_ENABLE_A = 1;
	parameter CFG_ENABLE_B = 1;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;

	// 512 x 40 bit
	parameter [20479:0] INIT = 20480'b0;

	input CLK2;
	input CLK3;

	// write side of the memory
	input [15:0] A1ADDR;
	input [19:0] A1DATA;
	input [19:0] A1EN;

	// read side of the memory
	input [15:0] B1ADDR;
	output [19:0] B1DATA;
	input [0:0] B1EN;

	// unconnected signals
	wire [19:0] A_DO;
	wire ECC_1B_ERR, ECC_2B_ERR;

	localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 2) ? 256 : 320;

	function [319:0] permute_init;
		input [INIT_CHUNK_SIZE-1:0] chunk;
		integer i;
		begin
			if (CFG_DBITS <= 2) begin
				for (i = 0; i < 64; i = i + 1) begin
					permute_init[i * 5 +: 5] = {1'b0, chunk[i * 4 +: 4]};
				end
			end else begin
				permute_init = chunk;
			end
		end
	endfunction

	// internal signals
	generate
		wire [15:0] ADDRA;
		wire [15:0] ADDRB;

		if (CFG_DBITS == 1) begin: blk
			assign ADDRA = {A1ADDR[13:5], 1'b0, A1ADDR[4:0], 1'b0};
			assign ADDRB = {B1ADDR[13:5], 1'b0, B1ADDR[4:0], 1'b0};
		end
		else if (CFG_DBITS == 2) begin: blk
			assign ADDRA = {A1ADDR[12:4], 1'b0, A1ADDR[3:0], 2'b0};
			assign ADDRB = {B1ADDR[12:4], 1'b0, B1ADDR[3:0], 2'b0};
		end
		else if (CFG_DBITS == 5) begin: blk
			assign ADDRA = {A1ADDR[11:3], 1'b0, A1ADDR[2:0], 3'b0};
			assign ADDRB = {B1ADDR[11:3], 1'b0, B1ADDR[2:0], 3'b0};
		end
		else if (CFG_DBITS == 10) begin: blk
			assign ADDRA = {A1ADDR[10:2], 1'b0, A1ADDR[1:0], 4'b0};
			assign ADDRB = {B1ADDR[10:2], 1'b0, B1ADDR[1:0], 4'b0};
		end
		else if (CFG_DBITS == 20) begin: blk
			assign ADDRA = {A1ADDR[9:1], 1'b0, A1ADDR[0], 5'b0};
			assign ADDRB = {B1ADDR[9:1], 1'b0, B1ADDR[0], 5'b0};
		end

		CC_BRAM_20K #(
			`include "brams_init_20.vh"
			.LOC("UNPLACED"),
			.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
			.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
			.RAM_MODE("TDP"),
			.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
			.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
			.A_EN_INV(1'b0), .B_EN_INV(1'b0),
			.A_WE_INV(1'b0), .B_WE_INV(1'b0),
			.A_DO_REG(1'b0), .B_DO_REG(1'b0),
			.ECC_EN(1'b0)
		) _TECHMAP_REPLACE_ (
			.A_DO(A_DO),
			.B_DO(B1DATA),
			.ECC_1B_ERR(ECC_1B_ERR),
			.ECC_2B_ERR(ECC_2B_ERR),
			.A_CLK(CLK2),
			.B_CLK(CLK3),
			.A_EN(1'b1),
			.B_EN(B1EN),
			.A_WE(|A1EN),
			.B_WE(1'b0),
			.A_ADDR(ADDRA),
			.B_ADDR(ADDRB),
			.A_DI(A1DATA),
			.B_DI(20'b0),
			.A_BM(A1EN),
			.B_BM(20'b0)
		);
	endgenerate

endmodule