module top (
	input clk,
	input reset
);

	wire stall;

	wire [31:0] fetch_addr;
	wire fetch_request;
	wire fetch_data_valid;
	
	wire [31:0] memory_addr;
	wire [31:0] write_data;
	wire [3:0] write_mask;
	wire memory_request;
	wire memory_request_type;
	wire memory_data_valid;

	wire[31:0] request_data;

	wire [31:0] ptbr;
	wire vm_enable;

	datapath dpath(.clk(clk), .reset(reset), .stall(stall),
		.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
		.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
		.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid),
		.request_data(request_data), .vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));

	memory_system ms(.clk(clk), .reset(reset), .stall(stall),
		.request_data(request_data),
		.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb),
		.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
		.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
		.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid));

endmodule