module cmsdk_ahb_to_ahb_apb_async_sample_and_hold #(
      parameter WIDTH = 32
   ) (
      input  wire             CLK,
      input  wire             EN,
      input  wire             MASK,
      input  wire [WIDTH-1:0] D,
      output wire [WIDTH-1:0] Q
   );

   // --------
   // Clock enabled D-type register.

   reg [WIDTH-1:0] q_q;

   always @(posedge CLK)
      if(EN)
         q_q <= D;

   // --------
   // Mask with hard AND gate.

   assign Q = q_q & {WIDTH{~MASK}};

endmodule