module cmsdk_ahb_to_ahb_apb_async_launch #(
      parameter WIDTH = 32
   ) (
      input  wire             CLK,
      input  wire             RSTn,
      input  wire             EN,
      input  wire [WIDTH-1:0] D,
      output wire [WIDTH-1:0] Q
   );

   // --------
   // Clock enabled D-type register.

   reg [WIDTH-1:0] q_q;

   always @(posedge CLK or negedge RSTn)
      if(~RSTn)
         q_q <= 1'b0;
      else if(EN)
         q_q <= D;

   assign Q = q_q;

endmodule