module dual_port_syn //syncrhonous dual port ram(uses block ram)
	#(
		parameter ADDR_WIDTH=11, //12k by 8 RAM (16k block RAM)
					 DATA_WIDTH=8
	)
	(
		input clk,
		input we,
		input[DATA_WIDTH-1:0] din,
		input[ADDR_WIDTH-1:0] addr_a,addr_b, //addr_a for writing address, addr_b for reading address
		output[DATA_WIDTH-1:0] dout
	);
	reg[DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
	reg[ADDR_WIDTH-1:0]addr_b_q;
	
	always @(posedge clk) begin
		if(we) ram[addr_a]=din;
		addr_b_q<=addr_b;
	end
	assign dout=ram[addr_b_q];
	
endmodule