module p_mul (

input           clock   ,
input           resetn  ,

input           valid   ,
output [ 0:0]   ready   ,

input           mul_l   ,
input           mul_h   ,
input           clmul   ,
input  [4:0]    pw      ,

input  [31:0]   crs1    ,
input  [31:0]   crs2    ,

output [31:0]   result

);

wire [31:0]   padd_lhs    ; // Left hand input
wire [31:0]   padd_rhs    ; // Right hand input.

wire [ 4:0]   padd_pw     ; // Pack width to operate on
wire [ 0:0]   padd_sub    ; // Subtract if set, else add.

wire [32:0]   padd_carry  ; // Carry bits
wire [31:0]   padd_result ; // Result of the operation

//
// Instance of the packed multipler core module
p_mul_core i_p_mul_core(
.clock      (clock      ),
.resetn     (resetn     ),
.valid      (valid      ), // Input is valid
.ready      (ready      ), // Output is ready
.mul_l      (mul_l      ), // Low half of result?
.mul_h      (mul_h      ), // High half of result?
.clmul      (clmul      ), // Do a carryless multiply?
.pw         (pw         ), // Pack width specifier
.crs1       (crs1       ), // Source register 1
.crs2       (crs2       ), // Source register 2
.result     (result     ), // [Carryless] multiply result
.padd_lhs   (padd_lhs   ), // Left hand input
.padd_rhs   (padd_rhs   ), // Right hand input.
.padd_pw    (padd_pw    ), // Pack width to operate on
.padd_sub   (padd_sub   ), // Subtract if set, else add.
.padd_carry (padd_carry ), // Carry bits
.padd_result(padd_result)  // Result of the operation
);

//
// Packed adder instance
p_addsub i_paddsub (
.lhs    (padd_lhs   ), // Left hand input
.rhs    (padd_rhs   ), // Right hand input.
.pw     (padd_pw    ), // Pack width to operate on
.sub    (padd_sub   ), // Subtract if set, else add.
.c_out  (padd_carry ), // Carry out
.result (padd_result)  // Result of the operation
);

endmodule