module an_io_phdet_ff_ln (q, dn, dp, rst_n, clk_p `ifndef INTCNOPWR ,vcc ,vss `endif);
        output q;
        input dn, dp, rst_n, clk_p;
        reg notifier;
        wire delayed_dn, delayed_dp, delayed_clk_p;
`ifndef INTCNOPWR
input vcc, vss;
`endif

        // Function
        wire int_fwire_Iq, int_fwire_r, xcr_0;

        not (int_fwire_r, rst_n);
        altos_dff_r_err (xcr_0, delayed_clk_p, delayed_dp, int_fwire_r);
        altos_dff_r (int_fwire_Iq, notifier, delayed_clk_p, delayed_dp, int_fwire_r, xcr_0);
        buf (q, int_fwire_Iq);

        // Timing
        specify
                (posedge clk_p => (q+:dp)) = 0;
                $setuphold (posedge clk_p, posedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn);
                $setuphold (posedge clk_p, negedge dn, 0, 0, notifier,,, delayed_clk_p, delayed_dn);
                $setuphold (posedge clk_p, posedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp);
                $setuphold (posedge clk_p, negedge dp, 0, 0, notifier,,, delayed_clk_p, delayed_dp);
                $width (posedge clk_p, 0, 0, notifier);
        endspecify
endmodule