module aibcr3_dlycell_dcc(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p
);

wire VDD_val;
wire VSS_val;

wire out_p_int;

assign VDD_val = 1'b1;
assign VSS_val = 1'b0;

aibcr3_dlycell_dcc__w_sup XDUT (
    .bk( bk ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p_int ),
    .VDD( VDD_val ),
    .VSS( VSS_val )
);

// from tttt_25_0p850_0p970
assign #(20, 24) out_p = out_p_int;

endmodule