module RAM256X1S (O, A, D, WCLK, WE);

    parameter INIT = 256'h0;

    output O;

    input  [7:0] A;
    input  D;
    input  WCLK;
    input  WE;

    reg  [255:0] mem;

    initial
         mem = INIT;

    assign O = mem[A];

    always @(posedge WCLK) 
	if (WE == 1'b1)
	    mem[A] <= #100 D;


endmodule