module SRLC32E (Q, Q31, A, CE, CLK, D);

    parameter INIT = 32'h00000000;

    output Q;
    output Q31;

    input  [4:0] A;
    input  CE, CLK, D;

    reg  [31:0] data;


    assign  Q = data[A];
    assign  Q31 = data[31];

    initial
    begin
          assign  data = INIT;
          while (CLK === 1'b1 || CLK===1'bX) 
            #10; 
          deassign data;
    end

    always @(posedge CLK)
	if (CE == 1'b1) 
	    data <= #100 {data[30:0], D};


endmodule