module uart_out  #( parameter PipeSpec = `PS_DATA( 8 ), parameter ClockFrequency = 12000000, parameter BaudRate = 9600 ) (
        input clock,
        input reset,

        inout [`P_w(PipeSpec)-1:0] pipe_in,

        output pin_tx
    );

    wire [`P_Data_w(PipeSpec)-1:0] in_data;
    wire                     in_valid;
    wire                     in_ready;

    p_unpack_data        #( .PipeSpec( PipeSpec ) ) in_unpack_d ( pipe_in, in_data);
    p_unpack_valid_ready #( .PipeSpec( PipeSpec ) ) in_unpack_vr( pipe_in, in_valid, in_ready );

    // start and stop signals are ignored - packetization has to be escaped
    uart_out_np #( .ClockFrequency( ClockFrequency ), .BaudRate( BaudRate ) )  u_o_np (
            clock, reset,

            in_data, in_valid, in_ready,

            pin_tx
        );

endmodule