module pci_async_reset_flop (
  data_in, clk_in, async_reset_data_out, reset_in
);

input      data_in;
input      clk_in;
output     async_reset_data_out;
input      reset_in;

reg        async_reset_data_out;

always @(posedge clk_in or posedge reset_in)
begin
  if (reset_in)
  begin
    async_reset_data_out <= #`FF_DELAY 1'b0;
  end
  else
  begin
    async_reset_data_out <= #`FF_DELAY data_in;
  end
end

endmodule