module TestCounters_Run();

	reg CLK;
	reg DownCount;

	always #25 CLK = ~CLK;

	UpCounterTest up_counter (.CLK(CLK));
	DownCounterTest down_counter (.CLK(CLK));
	RevCounterTest rev_counter (.CLK(CLK), .DownCount(DownCount));

	initial begin

		CLK <= 1'b0;

		$dumpfile("test_counters.vcd");
		$dumpvars(0, up_counter);
		$dumpvars(1, down_counter);
		$dumpvars(2, rev_counter);

		DownCount <= 1'b0;
		repeat (256) @ (posedge CLK);

		DownCount <= 1'b1;
		repeat (256) @ (posedge CLK);

		$finish;
	end

endmodule // TestCounters_Run