module sub32 (
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result)/* synthesis synthesis_clearbox = 1 */;

	input	[31:0]  dataa;
	input	[31:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[31:0]  result;

endmodule