module x_s3e_dpram (
	/********** |[g A **********/
	input  wire				   clka,  // NbN
	input  wire [`SpmAddrBus]  addra, // AhX
	input  wire [`WordDataBus] dina,  // «Ýf[^
	input  wire				   wea,	  // «ÝLø
	output reg	[`WordDataBus] douta, // ÇÝoµf[^
	/********** |[g B **********/
	input  wire				   clkb,  // NbN
	input  wire [`SpmAddrBus]  addrb, // AhX
	input  wire [`WordDataBus] dinb,  // «Ýf[^
	input  wire				   web,	  // «ÝLø
	output reg	[`WordDataBus] doutb  // ÇÝoµf[^
);

	/**********  **********/
	reg [`WordDataBus] mem [0:`SPM_DEPTH-1];

	/********** ANZXi|[g Aj **********/
	always @(posedge clka) begin
		// ÇÝoµANZX
		if ((web == `ENABLE) && (addra == addrb)) begin
			douta	  <= #1 dinb;
		end else begin
			douta	  <= #1 mem[addra];
		end
		// «ÝANZX
		if (wea == `ENABLE) begin
			mem[addra]<= #1 dina;
		end
	end

	/********** ANZXi|[g Bj **********/
	always @(posedge clkb) begin
		// ÇÝoµANZX
		if ((wea == `ENABLE) && (addrb == addra)) begin
			doutb	  <= #1 dina;
		end else begin
			doutb	  <= #1 mem[addrb];
		end
		// «ÝANZX
		if (web == `ENABLE) begin
			mem[addrb]<= #1 dinb;
		end
	end

endmodule