module RT_E_MUX(RT_E_Sel,V2_E,RF_WD_M,RF_WD_W,RT_E);
//input
    input [31:0] RT_E_Sel;

    input [31:0] V2_E;
    input [31:0] RF_WD_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RT_E;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RT_E=V2_E;
            case(RT_E_Sel)
                M:RT_E=RF_WD_M;
                W:RT_E=RF_WD_W;
            endcase
        end

endmodule