module darkcache_sim;

    // clock

    reg CLK = 0;
    
    integer i;
    
    initial for(i=0;i!=100;i=i+1) #10 CLK = !CLK;

    // reset

    reg [2:0] RES = -1;
    
    always@(posedge CLK) RES <= RES ? RES-1 : 0;

    // logic

    wire  HLT,HIT,DTREQ;

    reg  [2:0]      DLEN=0;
    reg             RW=1;
    reg  [3:0]      DTACK=0;
    reg  [31:0]     ADDR=0,DATA=0;
    wire [31:0]     DATO;
    
    assign HLT = DLEN && !HIT;
    
    always@(posedge CLK)
    begin
        // core part
    
        if(!RES && !HLT)
        begin
            DLEN <= 1; // 1 byte
            if(DLEN)
            begin
                ADDR <= ADDR==10 ? 5 : ADDR+1;
                if(ADDR==10) RW <= !RW;
            end
        end
        
        // slow memory part

        DTACK <= DTACK ? DTACK-1 : DTREQ ? 1 : 0;
        if(DTREQ) DATA  <= ADDR[3:0] + (ADDR[3:0]+1)*256 + (ADDR[3:0]+2)*65536 + (ADDR[3:0]+3)*16777216;
    end

    wire [3:0] DEBUG;

    darkcache icache(CLK,RES?1'b1:1'b0,RW,DLEN,ADDR,DATA,DATO,HIT,DTREQ,DTREQ?DTACK==1:1'b0,DEBUG);

endmodule