module util_clkdiv #(
  parameter SIM_DEVICE = "CYCLONE5",
  parameter CLOCK_TYPE = "Global Clock") (

  input   clk,
  input   reset,
  output  clk_out,
  output  reset_out
 );

reg enable;
reg reset_d1;

assign reset_out = reset | reset_d1;

always @(posedge clk) begin
  reset_d1 <= reset;
end

always @(posedge clk) begin
  enable <= ~enable;
end

generate if (SIM_DEVICE == "CYCLONE5") begin
	cyclonev_clkena #(
		.clock_type ("Global Clock"),
		.ena_register_mode ("falling edge"),
		.lpm_type ("cyclonev_clkena")
  ) clock_divider_by_2 (
	.ena(enable),
	.enaout(),
	.inclk(clk),
//	.clkselect (2'b0),
	.outclk(clk_out));

end endgenerate

endmodule  // util_clkdiv