module syncpls (
    input logic t_clk, //transmitting clock.
    input logic t_rst_n, //reset in t_clk domain.
    input logic t_pulse, //input pulse in t_clk domain.
    input logic r_clk, //receiving clock.
    input logic r_rst_n, //reset in r_clk_domain.
    output logic r_pulse); //output pulse in r_clk domain.

    logic t_tgl, r_tgl;

    pls2tgl pls2tgl_inst (
        .tgl(t_tgl),
        .pulse(t_pulse),
        .clk(t_clk), 
        .rst_n(t_rst_n));
    
    sync3 sync3_inst (
        .q(r_tgl),
        .d(t_tgl), 
        .clk(r_clk), 
        .rst_n(r_rst_n));
    
    tgl2pls tgl2pls_inst(
        .pulse(r_pulse), 
        .q(),
        .d(r_tgl),
        .clk(r_clk), 
        .rst_n(r_rst_n));
endmodule