module M_main__mem_mem(
input      [11-1:0]                in_mem_addr,
output reg  [32-1:0]    out_mem_rdata,
input      [(32)/8-1:0]         in_mem_wenable,
input      [32-1:0]                in_mem_wdata,
input      clock
);
reg  [32-1:0] buffer[1536-1:0];
always @(posedge clock) begin
  out_mem_rdata <= buffer[in_mem_addr];
end
integer i;
always @(posedge clock) begin
  for (i = 0; i < (32)/8; i = i + 1) begin
    if (in_mem_wenable[i]) begin
      buffer[in_mem_addr][i*8+:8] <= in_mem_wdata[i*8+:8];
    end
  end
end
initial begin
 buffer[0] = 32'h00002137;
 buffer[1] = 32'h80010113;
 buffer[2] = 32'h00000097;
 buffer[3] = 32'h018080E7;
 buffer[4] = 32'h00000317;
 buffer[5] = 32'h00830067;
 buffer[6] = 32'h00000000;
 buffer[7] = 32'h00008067;
 buffer[8] = 32'hFF010113;
 buffer[9] = 32'h00012623;
 buffer[10] = 32'h000027B7;
 buffer[11] = 32'h00F00713;
 buffer[12] = 32'h00E7A223;
 buffer[13] = 32'h00200793;
 buffer[14] = 32'h000026B7;
 buffer[15] = 32'h00800713;
 buffer[16] = 32'h0080006F;
 buffer[17] = 32'h00100793;
 buffer[18] = 32'h00F6A223;
 buffer[19] = 32'h00179793;
 buffer[20] = 32'hFEF74AE3;
 buffer[21] = 32'hFF5FF06F;
 buffer[22] = 32'h00002040;
 buffer[23] = 32'h00002020;
 buffer[24] = 32'h00002010;
 buffer[25] = 32'h00002008;
 buffer[26] = 32'h00002004;
end

endmodule