module Register_CE (q, d, ce, clk);
  parameter N = 1;
  input            clk;
  output reg [N-1:0] q;
  input      [N-1:0] d;
  input 	          ce;
  initial q = {N{1'b0}};
  always @(posedge clk)
    if (ce) q <= d;
endmodule // REGISTER_CE