module DFFSR(C, D, Q, S, R);
    input C, D, S, R;
    output reg Q;
    always @(posedge C, posedge S, posedge R)
        if (S)
            Q <= 1'b1;
        else if (R)
            Q <= 1'b0;
        else
            Q <= D;
endmodule