module audiodac (
`ifdef USE_POWER_PINS
	inout 			vccd1,
	inout 			vssd1,
`endif
	// FIFO interface
	input		[15:0]	fifo_i,
	input			fifo_rdy_i,
	output 			fifo_ack_o,
	output			fifo_full_o,
	output			fifo_empty_o,
	// housekeeping
	input			rst_n_i,
	input			clk_i,
	// configuration bits
	input			mode_i, 	// 0 = 1st, 1 = 2nd order SD-mod
	input 		[3:0]	volume_i,	// 0 = off, 1 = min volume, 15 = max volume
	input		[1:0]	osr_i, 		// 0 = 32; 1 = 64, 2 = 128, 3 = 256
	// ds-modulator outputs
	output			ds_o,		// single-bit SD-modulator output
	output 			ds_n_o,		//  plus the complementary output
	// test modes
	input			tst_sinegen_en_i,
	input		[3:0]	tst_sinegen_step_i,
	input			tst_fifo_loop_i
);

	wire		[15:0]	data_audio, data_sine;
	wire			audio_rd;

	wire [15:0] data = tst_sinegen_en_i ? data_sine : data_audio;

	audiodac_fifo fifo (
		.fifo_data_i(fifo_i),
		.fifo_rdy_i(fifo_rdy_i),
		.fifo_ack_o(fifo_ack_o),
		.fifo_full_o(fifo_full_o),
		.fifo_empty_o(fifo_empty_o),
		.audio_data_o(data_audio),
		.audio_rd_i(audio_rd),
		.rst_n_i(rst_n_i),
		.clk_i(clk_i),
		.tst_fifo_loop_i(tst_fifo_loop_i)
	);

	audiodac_dsmod dsmod (	
		.audio_i(data),
		.audio_rd_o(audio_rd),
		.rst_n_i(rst_n_i),
		.clk_i(clk_i),
		.mode_i(mode_i),
		.volume_i(volume_i),
		.osr_i(osr_i),
		.ds_o(ds_o),
		.ds_n_o(ds_n_o)
	);

	audiodac_sinegen sinegen (
		.data_o(data_sine),
		.data_rd_i(audio_rd),
		.rst_n_i(rst_n_i),
		.clk_i(clk_i),
		.tst_sinegen_en_i(tst_sinegen_en_i),
		.tst_sinegen_step_i(tst_sinegen_step_i)
	);


endmodule // audiodac