module ram16k(input clk,
	      input [12:0] 	addr,
	      input [15:0] 	data_in,
	      output [15:0] data_out,
	      input 		we,
	      input 		re);

   // Only low half is available anyway
   ram8k_low r1(.clk(clk),
                .addr(addr[11:0]),
                .data_in(data_in),
                .data_out(data_out),
                .we(we&(~addr[12])),
                .re(re&(~addr[12])));
endmodule