module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);

parameter DELAY=5;


input rst, clk, stb_i, cyc_i;
input [15:0] addr;
output ack_o;
output [31:0] data;


reg ack_o;
reg [31:0] data;

reg [7:0] buff [0:65535];
//reg [7:0] buff [8388607:0];
reg [2:0] cnt;
integer i;


initial
begin
//  for (i=0; i<65536; i=i+1)
//    buff [i] = 8'h00;
  $readmemh("../../../bench/in/oc8051_xrom.in", buff);
end

always @(posedge clk or posedge rst)
begin
  if (rst) begin
    data <= #1 31'h0;
    ack_o <= #1 1'b0;
  end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
    data <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
    ack_o <= #1 1'b1;
  end else
    ack_o <= #1 1'b0;
end

always @(posedge clk or posedge rst)
begin
  if (rst)
    cnt <= #1 DELAY;
  else if (cnt == 3'b000)
    cnt <= #1 DELAY;
  else if (stb_i)
    cnt <= #1 cnt - 3'b001;
  else cnt <= #1 DELAY;
end

endmodule