module IO(
  input clk, resetn,

  input            mem_valid,
  output reg       mem_ready,

  input     [31:0] mem_addr,
  input     [31:0] mem_wdata,
  input     [ 3:0] mem_wstrb,
  output reg   [31:0] mem_rdata,
  output    [ 3:0] io
);
  assign io = io_int;
  
  reg [3:0] io_int;
  reg       mem_valid_reg;

  always @(posedge clk) begin
    if (!resetn) begin
      io_int <= 0;
      mem_ready <= 0;
      mem_rdata <= 0;
      mem_valid_reg <= 0;
    end else begin
      if ((mem_valid == 1) && (mem_valid_reg == 0))
        mem_ready <= 1;
      if (mem_ready)
        mem_ready <= 0;

      mem_valid_reg <= mem_valid;

      if ((mem_valid == 1) && (mem_valid_reg == 0)) begin
        // rx_BD_adr
        if (mem_addr[7:2] == 6'h10) begin
          mem_rdata <= {28'd0, io_int};
          if (mem_wstrb==4'hF) io_int <= mem_wdata[3:0];
        end
      end
    end
  end

endmodule