module axis_slr_register_source #(
  parameter WIDTH = 8
) (
  input  wire             clk,
  input  wire             rst,

  input  wire             din_valid,
  input  wire [WIDTH-1:0] din,
  output wire             din_ready,

  output wire             dout_valid,
  output wire [WIDTH-1:0] dout,
  input  wire             dout_ready
);

  (* USER_SLL_REG="true" *)                     reg  sll_valid   = 1'b0;
  (* USER_SLL_REG="true", shreg_extract="no" *) reg  [WIDTH-1:0] sll_data;
  (* USER_SLL_REG="true", keep="true" *)        reg  sll_ready   = 1'b0;
  (* keep="true" *)                             reg  sll_ready_r = 1'b0;

  // Register input, including ready signal
  always @(posedge clk) begin
    sll_data    <= din;
    sll_valid   <= din_valid & sll_ready_r;
    sll_ready   <= dout_ready;
    sll_ready_r <= sll_ready;

    if (rst)
      sll_ready_r <= 1'b0;
  end

  assign dout_valid = sll_valid;
  assign dout       = sll_data;
  assign din_ready  = sll_ready_r;

endmodule