module dpram_128x8 (
	input clk,
	input wen,
	input ren,
	input[0:6] waddr,
	input[0:6] raddr,
	input[0:7] d_in,
	output[0:7] d_out );

		dpram_128x8_core memory_0 (
			.wclk		(clk),
			.wen		(wen),
			.waddr		(waddr),
			.data_in	(d_in),
			.rclk		(clk),
			.ren		(ren),
			.raddr		(raddr),
			.d_out		(d_out) );

endmodule