module CC_PLL #(
  parameter PLL_CFG = 96'b0,
  parameter REF_CLK = "", // e.g. "10.0"
  parameter OUT_CLK = "", // e.g. "50.0"
  parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
  parameter LOW_JITTER = 1,
  parameter CI_FILTER_CONST = 2,
  parameter CP_FILTER_CONST = 4
  )(
  input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
  input USR_LOCKED_STDY_RST, USR_SET_SEL,
  output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
  output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
  );

  //parameter clk_freq = 40000000; // 40 MHz clk 
  reg clk_out;
  always 
  begin  
    clk_out <= 1'b1;
    #25.5;// (1.0/40000000/2);
    clk_out <= 1'b0;
    #25.5;//(1.0/40000000/2);
  end
  assign CLK180 = clk_out;
  assign CLK0 = clk_out;
  endmodule