module LATCHRN (
  input RSTN, // Reset signal
  input WE, // Write enable
  input D, // Data input
  output Q, // Q output
  output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;

//-------------Code Starts Here---------
always @ (RSTN or WE or D) begin
  if (~RSTN) begin
    q_reg <= 1'b0;
  end else if (1'b1 == WE) begin
    q_reg <= D;
  end
end

// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
  assign Q = q_reg;
  assign QN = ~q_reg;
`else
  assign Q = 1'bZ;
  assign QN = !Q;
`endif

endmodule