module MUXF7_D (LO, O, I0, I1, S);

    output LO, O;
    reg    O, LO;

    input  I0, I1, S;

	always @(I0 or I1 or S)
            if (S) begin
		O = I1;
		LO = I1;
            end
	    else begin
		O = I0;
		LO = I0;
	    end
endmodule