module ExtraCounter (
	PHI1, PHI2, TRES2, n_ready, T1,
	n_T2, n_T3, n_T4, n_T5);

	input PHI1;
	input PHI2;
	input TRES2;
	input n_ready;
	input T1;

	output n_T2;
	output n_T3;
	output n_T4;
	output n_T5;

	wire t1_latch_nq;
	wire [3:0] nq;

	dlatch t1_latch (.d(T1), .en(PHI2), .nq(t1_latch_nq));

	ExtraCounter_SRBit sr [3:0] (
		.PHI1(PHI1),
		.PHI2(PHI2),
		.nd({nq[2:0],t1_latch_nq}),
		.n_EN(n_ready),
		.RES(TRES2),
		.nq(nq),
		.nsout({n_T5,n_T4,n_T3,n_T2}));

endmodule // ExtraCounter