module dual_port_ram_lattice #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            wclk, 
          input wire                            rclk,
          output reg [DATA_WIDTH - 1 : 0]       dout
);

    reg [DATA_WIDTH - 1 : 0] mem [(1<<ADDR_WIDTH)-1:0];
    
    always @(posedge wclk)  begin// Write memory.
        if (write_en) begin
            mem[waddr] <= din; // Using write address bus.
        end
    end
   
    always @(posedge rclk) begin // Read memory.
        dout <= mem[raddr]; // Using read address bus.
    end
endmodule