module cxapbasyncbridge_cdc_capt_sync (clk, resetn, d_async, sync_en, q);

  parameter WIDTH = 4;

  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input                clk;
  input                resetn;
  input [WIDTH-1:0]    d_async;     // May be connected to an asynchronous input
  input                sync_en;
  output [WIDTH-1:0]   q;


  // ------------------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------
  wire [WIDTH-1:0]     d_noz;
  reg  [WIDTH-1:0]     d_sync1;
  reg  [WIDTH-1:0]     q;

`ifdef ARM_CDC_CHECK

  cxapbasyncbridge_cdc_random #(WIDTH) u_cdc_random_z(
                             .din (d_async),
                             .dout (d_noz)
                             );

`else

  assign d_noz = d_async;

`endif

  always @(posedge clk or negedge resetn)
    if (!resetn)
      begin
        d_sync1 <= {WIDTH{1'b0}};
        q <= {WIDTH{1'b0}};
      end
    else if(sync_en)
      begin
        d_sync1 <= d_noz;
        q <= d_sync1;
      end
      
endmodule