module SoftCLK_LFSR_Bit(
	ACLK1,
	sin, F1, F2,
	sout, n_sout);

	input ACLK1;

	input sin;
	input F1;
	input F2;

	output sout;
	output n_sout;

	wire inlatch_out;
	dlatch in_latch (
		.d(F2 ? sin : (F1 ? 1'b1 : 1'bz)),
		.en(1'b1), .nq(inlatch_out));
	dlatch out_latch (.d(inlatch_out), .en(ACLK1), .q(n_sout), .nq(sout));

endmodule // SoftCLK_LFSR_Bit