module dual_port_sram_16kb (
  input wclk,
  input wen,
  input [10:0] waddr,
  input [7:0] data_in,
  input rclk,
  input ren,
  input [10:0] raddr,
  output [7:0] data_out
);

  reg [7:0] ram[2047:0];
  reg [7:0] internal;

  assign data_out = internal;

  always @(posedge wclk) begin
    if(wen) begin
      ram[waddr] <= data_in;
    end
  end

  always @(posedge rclk) begin
    if(ren) begin
      internal <= ram[raddr];
    end
  end

endmodule