module aibcr3_str_ioload ( in, vcc, vssl );

input  in, vcc, vssl;

// Buses in the design

wire  net5;


// specify 
//     specparam CDS_LIBNAME  = "aibcr_lib";
//     specparam CDS_CELLNAME = "aibcr_str_ioload";
//     specparam CDS_VIEWNAME = "schematic";
// endspecify

assign net5 = ~in ;

endmodule