module soc_gated_clk_cell(
  clk_in,
  external_en,
  SE,
  clk_out
);

input  clk_in;
input  external_en ;
input  SE;
output clk_out;

//reg    clk_en_af_latch;
//always @(clk_in or external_en)
//begin
//  if(!clk_in)
//    clk_en_af_latch <= external_en;
//end
//
//reg clk_en ;
//always @ (SE or clk_en_af_latch )
//begin
//    clk_en <= clk_en_af_latch || SE ;
//end
assign clk_out = clk_in;
   
endmodule   