module pipe_reg_rst #(
    parameter WIDTH=1, // width of the input and output signals
    parameter N=2, // depth of synchronizer
    parameter INIT=1'b0
)(
    input  wire             clk,
    input  wire             rst,

    input  wire [WIDTH-1:0] in,
    output wire [WIDTH-1:0] out
);

 (* srl_style="register", keep="true", shreg_extract="no" *)
 reg [WIDTH-1:0] sync_reg [N-1:0];

  integer i;

  always @(posedge clk) begin
    if (rst)
      sync_reg[0] <= {WIDTH{INIT}};
    else
      sync_reg[0] <= in;

    for (i = 1; i < N; i = i + 1)
      if (rst)
        sync_reg[i] <= sync_reg[i-1];
      else
        sync_reg[i] <= {WIDTH{INIT}};
  end

  assign out = sync_reg[N-1];

endmodule