module sync2
  ( input     clk,
    input     data_in,
    output    data_out );

  reg         sync_ff1, sync_ff2;

  always @(posedge clk)
    begin
      sync_ff1 <= #1 data_in;
      sync_ff2 <= #1 sync_ff1;
    end

  assign data_out = sync_ff2;

endmodule // sync2