module ram_generic_1rw1r(
    input wire clk,
    input wire rst,
    // Read write port
    input wire [ABITS-1:0] addr0,
    input wire re0,
    output reg [DBITS-1:0] rd0,
    input wire [DBITS-1:0] wr0,
    input wire we0,
    // Read only port
    input wire [ABITS-1:0] addr1,
    input wire re1,
    output reg [DBITS-1:0] rd1
);

    parameter DBITS = 8;
    parameter ABITS = 12;
    localparam DEPTH = (1 << ABITS);

    reg [DBITS-1:0] mem [0:DEPTH-1];

    always @(posedge clk) begin
        if (!rst) begin
            if (re0) begin
                rd0 <= mem[addr0];
            end
            else if (we0) begin
                mem[addr0] <= wr0;
            end
            
            if (re1) begin
                rd1 <= mem[addr1];
            end
        end
    end

endmodule