module pcie_pipe_v6 #
(
   parameter           NO_OF_LANES = 8, 
   parameter           LINK_CAP_MAX_LINK_SPEED = 4'h1,
   parameter           PIPE_PIPELINE_STAGES = 0    // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
   // Pipe Per-Link Signals
   input   wire        pipe_tx_rcvr_det_i       ,
   input   wire        pipe_tx_reset_i          ,  
   input   wire        pipe_tx_rate_i           ,  
   input   wire        pipe_tx_deemph_i         ,  
   input   wire [2:0]  pipe_tx_margin_i         ,  
   input   wire        pipe_tx_swing_i          ,  

   output  wire        pipe_tx_rcvr_det_o       ,
   output  wire        pipe_tx_reset_o          ,  
   output  wire        pipe_tx_rate_o           ,  
   output  wire        pipe_tx_deemph_o         ,  
   output  wire [2:0]  pipe_tx_margin_o         ,  
   output  wire        pipe_tx_swing_o          ,  
   
   // Pipe Per-Lane Signals - Lane 0
   output  wire [ 1:0] pipe_rx0_char_is_k_o     ,
   output  wire [15:0] pipe_rx0_data_o          ,
   output  wire        pipe_rx0_valid_o         ,
   output  wire        pipe_rx0_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx0_status_o        ,
   output  wire        pipe_rx0_phy_status_o    ,
   output  wire        pipe_rx0_elec_idle_o     ,
   input   wire        pipe_rx0_polarity_i      ,
   input   wire        pipe_tx0_compliance_i    ,
   input   wire [ 1:0] pipe_tx0_char_is_k_i     ,
   input   wire [15:0] pipe_tx0_data_i          ,
   input   wire        pipe_tx0_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx0_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx0_char_is_k_i     ,
   input  wire [15:0]  pipe_rx0_data_i         ,
   input  wire         pipe_rx0_valid_i         ,
   input  wire         pipe_rx0_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx0_status_i        ,
   input  wire         pipe_rx0_phy_status_i    ,
   input  wire         pipe_rx0_elec_idle_i     ,
   output wire         pipe_rx0_polarity_o      ,
   output wire         pipe_tx0_compliance_o    ,
   output wire [ 1:0]  pipe_tx0_char_is_k_o     ,
   output wire [15:0]  pipe_tx0_data_o          ,
   output wire         pipe_tx0_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx0_powerdown_o     , 
   
   // Pipe Per-Lane Signals - Lane 1
   output  wire [ 1:0] pipe_rx1_char_is_k_o     ,
   output  wire [15:0] pipe_rx1_data_o         ,
   output  wire        pipe_rx1_valid_o         ,
   output  wire        pipe_rx1_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx1_status_o        ,
   output  wire        pipe_rx1_phy_status_o    ,
   output  wire        pipe_rx1_elec_idle_o     ,
   input   wire        pipe_rx1_polarity_i      ,
   input   wire        pipe_tx1_compliance_i    ,
   input   wire [ 1:0] pipe_tx1_char_is_k_i     ,
   input   wire [15:0] pipe_tx1_data_i          ,
   input   wire        pipe_tx1_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx1_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx1_char_is_k_i     ,
   input  wire [15:0]  pipe_rx1_data_i         ,
   input  wire         pipe_rx1_valid_i         ,
   input  wire         pipe_rx1_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx1_status_i        ,
   input  wire         pipe_rx1_phy_status_i    ,
   input  wire         pipe_rx1_elec_idle_i     ,
   output wire         pipe_rx1_polarity_o      ,
   output wire         pipe_tx1_compliance_o    ,
   output wire [ 1:0]  pipe_tx1_char_is_k_o     ,
   output wire [15:0]  pipe_tx1_data_o          ,
   output wire         pipe_tx1_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx1_powerdown_o     , 

   // Pipe Per-Lane Signals - Lane 2
   output  wire [ 1:0] pipe_rx2_char_is_k_o     ,
   output  wire [15:0] pipe_rx2_data_o         ,
   output  wire        pipe_rx2_valid_o         ,
   output  wire        pipe_rx2_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx2_status_o        ,
   output  wire        pipe_rx2_phy_status_o    ,
   output  wire        pipe_rx2_elec_idle_o     ,
   input   wire        pipe_rx2_polarity_i      ,
   input   wire        pipe_tx2_compliance_i    ,
   input   wire [ 1:0] pipe_tx2_char_is_k_i     ,
   input   wire [15:0] pipe_tx2_data_i          ,
   input   wire        pipe_tx2_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx2_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx2_char_is_k_i     ,
   input  wire [15:0]  pipe_rx2_data_i         ,
   input  wire         pipe_rx2_valid_i         ,
   input  wire         pipe_rx2_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx2_status_i        ,
   input  wire         pipe_rx2_phy_status_i    ,
   input  wire         pipe_rx2_elec_idle_i     ,
   output wire         pipe_rx2_polarity_o      ,
   output wire         pipe_tx2_compliance_o    ,
   output wire [ 1:0]  pipe_tx2_char_is_k_o     ,
   output wire [15:0]  pipe_tx2_data_o          ,
   output wire         pipe_tx2_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx2_powerdown_o     , 

   // Pipe Per-Lane Signals - Lane 3
   output  wire [ 1:0] pipe_rx3_char_is_k_o     ,
   output  wire [15:0] pipe_rx3_data_o         ,
   output  wire        pipe_rx3_valid_o         ,
   output  wire        pipe_rx3_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx3_status_o        ,
   output  wire        pipe_rx3_phy_status_o    ,
   output  wire        pipe_rx3_elec_idle_o     ,
   input   wire        pipe_rx3_polarity_i      ,
   input   wire        pipe_tx3_compliance_i    ,
   input   wire [ 1:0] pipe_tx3_char_is_k_i     ,
   input   wire [15:0] pipe_tx3_data_i          ,
   input   wire        pipe_tx3_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx3_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx3_char_is_k_i     ,
   input  wire [15:0]  pipe_rx3_data_i         ,
   input  wire         pipe_rx3_valid_i         ,
   input  wire         pipe_rx3_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx3_status_i        ,
   input  wire         pipe_rx3_phy_status_i    ,
   input  wire         pipe_rx3_elec_idle_i     ,
   output wire         pipe_rx3_polarity_o      ,
   output wire         pipe_tx3_compliance_o    ,
   output wire [ 1:0]  pipe_tx3_char_is_k_o     ,
   output wire [15:0]  pipe_tx3_data_o          ,
   output wire         pipe_tx3_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx3_powerdown_o     , 
   
   // Pipe Per-Lane Signals - Lane 4
   output  wire [ 1:0] pipe_rx4_char_is_k_o     ,
   output  wire [15:0] pipe_rx4_data_o         ,
   output  wire        pipe_rx4_valid_o         ,
   output  wire        pipe_rx4_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx4_status_o        ,
   output  wire        pipe_rx4_phy_status_o    ,
   output  wire        pipe_rx4_elec_idle_o     ,
   input   wire        pipe_rx4_polarity_i      ,
   input   wire        pipe_tx4_compliance_i    ,
   input   wire [ 1:0] pipe_tx4_char_is_k_i     ,
   input   wire [15:0] pipe_tx4_data_i          ,
   input   wire        pipe_tx4_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx4_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx4_char_is_k_i     ,
   input  wire [15:0]  pipe_rx4_data_i         ,
   input  wire         pipe_rx4_valid_i         ,
   input  wire         pipe_rx4_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx4_status_i        ,
   input  wire         pipe_rx4_phy_status_i    ,
   input  wire         pipe_rx4_elec_idle_i     ,
   output wire         pipe_rx4_polarity_o      ,
   output wire         pipe_tx4_compliance_o    ,
   output wire [ 1:0]  pipe_tx4_char_is_k_o     ,
   output wire [15:0]  pipe_tx4_data_o          ,
   output wire         pipe_tx4_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx4_powerdown_o     , 
   
   // Pipe Per-Lane Signals - Lane 5
   output  wire [ 1:0] pipe_rx5_char_is_k_o     ,
   output  wire [15:0] pipe_rx5_data_o         ,
   output  wire        pipe_rx5_valid_o         ,
   output  wire        pipe_rx5_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx5_status_o        ,
   output  wire        pipe_rx5_phy_status_o    ,
   output  wire        pipe_rx5_elec_idle_o     ,
   input   wire        pipe_rx5_polarity_i      ,
   input   wire        pipe_tx5_compliance_i    ,
   input   wire [ 1:0] pipe_tx5_char_is_k_i     ,
   input   wire [15:0] pipe_tx5_data_i          ,
   input   wire        pipe_tx5_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx5_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx5_char_is_k_i     ,
   input  wire [15:0]  pipe_rx5_data_i         ,
   input  wire         pipe_rx5_valid_i         ,
   input  wire         pipe_rx5_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx5_status_i        ,
   input  wire         pipe_rx5_phy_status_i    ,
   input  wire         pipe_rx5_elec_idle_i     ,
   output wire         pipe_rx5_polarity_o      ,
   output wire         pipe_tx5_compliance_o    ,
   output wire [ 1:0]  pipe_tx5_char_is_k_o     ,
   output wire [15:0]  pipe_tx5_data_o          ,
   output wire         pipe_tx5_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx5_powerdown_o     , 
   
   // Pipe Per-Lane Signals - Lane 6
   output  wire [ 1:0] pipe_rx6_char_is_k_o     ,
   output  wire [15:0] pipe_rx6_data_o         ,
   output  wire        pipe_rx6_valid_o         ,
   output  wire        pipe_rx6_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx6_status_o        ,
   output  wire        pipe_rx6_phy_status_o    ,
   output  wire        pipe_rx6_elec_idle_o     ,
   input   wire        pipe_rx6_polarity_i      ,
   input   wire        pipe_tx6_compliance_i    ,
   input   wire [ 1:0] pipe_tx6_char_is_k_i     ,
   input   wire [15:0] pipe_tx6_data_i          ,
   input   wire        pipe_tx6_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx6_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx6_char_is_k_i     ,
   input  wire [15:0]  pipe_rx6_data_i         ,
   input  wire         pipe_rx6_valid_i         ,
   input  wire         pipe_rx6_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx6_status_i        ,
   input  wire         pipe_rx6_phy_status_i    ,
   input  wire         pipe_rx6_elec_idle_i     ,
   output wire         pipe_rx6_polarity_o      ,
   output wire         pipe_tx6_compliance_o    ,
   output wire [ 1:0]  pipe_tx6_char_is_k_o     ,
   output wire [15:0]  pipe_tx6_data_o          ,
   output wire         pipe_tx6_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx6_powerdown_o     , 
   
   // Pipe Per-Lane Signals - Lane 7
   output  wire [ 1:0] pipe_rx7_char_is_k_o     ,
   output  wire [15:0] pipe_rx7_data_o         ,
   output  wire        pipe_rx7_valid_o         ,
   output  wire        pipe_rx7_chanisaligned_o ,
   output  wire [ 2:0] pipe_rx7_status_o        ,
   output  wire        pipe_rx7_phy_status_o    ,
   output  wire        pipe_rx7_elec_idle_o     ,
   input   wire        pipe_rx7_polarity_i      ,
   input   wire        pipe_tx7_compliance_i    ,
   input   wire [ 1:0] pipe_tx7_char_is_k_i     ,
   input   wire [15:0] pipe_tx7_data_i          ,
   input   wire        pipe_tx7_elec_idle_i     ,
   input   wire [ 1:0] pipe_tx7_powerdown_i     , 

   input  wire [ 1:0]  pipe_rx7_char_is_k_i     ,
   input  wire [15:0]  pipe_rx7_data_i         ,
   input  wire         pipe_rx7_valid_i         ,
   input  wire         pipe_rx7_chanisaligned_i ,
   input  wire [ 2:0]  pipe_rx7_status_i        ,
   input  wire         pipe_rx7_phy_status_i    ,
   input  wire         pipe_rx7_elec_idle_i     ,
   output wire         pipe_rx7_polarity_o      ,
   output wire         pipe_tx7_compliance_o    ,
   output wire [ 1:0]  pipe_tx7_char_is_k_o     ,
   output wire [15:0]  pipe_tx7_data_o          ,
   output wire         pipe_tx7_elec_idle_o     ,
   output wire [ 1:0]  pipe_tx7_powerdown_o     , 

   // Non PIPE signals
   input   wire [ 5:0] pl_ltssm_state         ,
   input   wire        pipe_clk               , 
   input   wire        rst_n 
);

//******************************************************************//
// Reality check.                                                   //
//******************************************************************//

    localparam Tc2o  = 1;      // clock to out delay model


    wire [ 1:0] pipe_rx0_char_is_k_q     ;
    wire [15:0] pipe_rx0_data_q          ;
    wire [ 1:0] pipe_rx1_char_is_k_q     ;
    wire [15:0] pipe_rx1_data_q          ;
    wire [ 1:0] pipe_rx2_char_is_k_q     ;
    wire [15:0] pipe_rx2_data_q          ;
    wire [ 1:0] pipe_rx3_char_is_k_q     ;
    wire [15:0] pipe_rx3_data_q          ;
    wire [ 1:0] pipe_rx4_char_is_k_q     ;
    wire [15:0] pipe_rx4_data_q          ;
    wire [ 1:0] pipe_rx5_char_is_k_q     ;
    wire [15:0] pipe_rx5_data_q          ;
    wire [ 1:0] pipe_rx6_char_is_k_q     ;
    wire [15:0] pipe_rx6_data_q          ;
    wire [ 1:0] pipe_rx7_char_is_k_q     ;
    wire [15:0] pipe_rx7_data_q          ;

//synthesis translate_off
//   initial begin
//      $display("[%t] %m NO_OF_LANES %0d  PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
//   end
//synthesis translate_on
    
    generate

      pcie_pipe_misc_v6 # (

        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

      )
      pipe_misc_i (

        .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
        .pipe_tx_reset_i(pipe_tx_reset_i),
        .pipe_tx_rate_i(pipe_tx_rate_i),
        .pipe_tx_deemph_i(pipe_tx_deemph_i),
        .pipe_tx_margin_i(pipe_tx_margin_i),
        .pipe_tx_swing_i(pipe_tx_swing_i),
  
        .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
        .pipe_tx_reset_o(pipe_tx_reset_o),
        .pipe_tx_rate_o(pipe_tx_rate_o),
        .pipe_tx_deemph_o(pipe_tx_deemph_o),
        .pipe_tx_margin_o(pipe_tx_margin_o),
        .pipe_tx_swing_o(pipe_tx_swing_o)          ,
  
        .pipe_clk(pipe_clk),
        .rst_n(rst_n)
    );


      pcie_pipe_lane_v6 # (

        .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

      ) 
      pipe_lane_0_i (

        .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),
        .pipe_rx_data_o(pipe_rx0_data_q),
        .pipe_rx_valid_o(pipe_rx0_valid_o),
        .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
        .pipe_rx_status_o(pipe_rx0_status_o),
        .pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
        .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
        .pipe_rx_polarity_i(pipe_rx0_polarity_i),
        .pipe_tx_compliance_i(pipe_tx0_compliance_i),
        .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
        .pipe_tx_data_i(pipe_tx0_data_i),
        .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
        .pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
  
        .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
        .pipe_rx_data_i(pipe_rx0_data_i),
        .pipe_rx_valid_i(pipe_rx0_valid_i),
        .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
        .pipe_rx_status_i(pipe_rx0_status_i),
        .pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
        .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
        .pipe_rx_polarity_o(pipe_rx0_polarity_o),
        .pipe_tx_compliance_o(pipe_tx0_compliance_o),
        .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
        .pipe_tx_data_o(pipe_tx0_data_o),
        .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
        .pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
  
        .pipe_clk(pipe_clk),
        .rst_n(rst_n)

      );

      if (NO_OF_LANES >= 2) begin

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_1_i (

          .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),
          .pipe_rx_data_o(pipe_rx1_data_q),
          .pipe_rx_valid_o(pipe_rx1_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx1_status_o),
          .pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx1_polarity_i),
          .pipe_tx_compliance_i(pipe_tx1_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
          .pipe_tx_data_i(pipe_tx1_data_i),
          .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
          .pipe_rx_data_i(pipe_rx1_data_i),
          .pipe_rx_valid_i(pipe_rx1_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx1_status_i),
          .pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx1_polarity_o),
          .pipe_tx_compliance_o(pipe_tx1_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
          .pipe_tx_data_o(pipe_tx1_data_o),
          .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

      end
      else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
          assign pipe_rx1_char_is_k_o = 2'b00;
          assign pipe_rx1_data_o = 16'h0000;
          assign pipe_rx1_valid_o = 1'b0;
          assign pipe_rx1_chanisaligned_o = 1'b0;
          assign pipe_rx1_status_o = 3'b000;
          assign pipe_rx1_phy_status_o = 1'b0;
          assign pipe_rx1_elec_idle_o = 1'b1;
          assign pipe_rx1_polarity_o = 1'b0;
          assign pipe_tx1_compliance_o = 1'b0;
          assign pipe_tx1_char_is_k_o = 2'b00;
          assign pipe_tx1_data_o = 16'h0000;
          assign pipe_tx1_elec_idle_o = 1'b1;
          assign pipe_tx1_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      end      

      if (NO_OF_LANES >= 4) begin

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
        ) 
        pipe_lane_2_i (

          .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),
          .pipe_rx_data_o(pipe_rx2_data_q),
          .pipe_rx_valid_o(pipe_rx2_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx2_status_o),
          .pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx2_polarity_i),
          .pipe_tx_compliance_i(pipe_tx2_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
          .pipe_tx_data_i(pipe_tx2_data_i),
          .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
          .pipe_rx_data_i(pipe_rx2_data_i),
          .pipe_rx_valid_i(pipe_rx2_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx2_status_i),
          .pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx2_polarity_o),
          .pipe_tx_compliance_o(pipe_tx2_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
          .pipe_tx_data_o(pipe_tx2_data_o),
          .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_3_i (

          .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),
          .pipe_rx_data_o(pipe_rx3_data_q),
          .pipe_rx_valid_o(pipe_rx3_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx3_status_o),
          .pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx3_polarity_i),
          .pipe_tx_compliance_i(pipe_tx3_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
          .pipe_tx_data_i(pipe_tx3_data_i),
          .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
          .pipe_rx_data_i(pipe_rx3_data_i),
          .pipe_rx_valid_i(pipe_rx3_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx3_status_i),
          .pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx3_polarity_o),
          .pipe_tx_compliance_o(pipe_tx3_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
          .pipe_tx_data_o(pipe_tx3_data_o),
          .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

      end
      else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
          assign pipe_rx2_char_is_k_o = 2'b00;
          assign pipe_rx2_data_o = 16'h0000;
          assign pipe_rx2_valid_o = 1'b0;
          assign pipe_rx2_chanisaligned_o = 1'b0;
          assign pipe_rx2_status_o = 3'b000;
          assign pipe_rx2_phy_status_o = 1'b0;
          assign pipe_rx2_elec_idle_o = 1'b1;
          assign pipe_rx2_polarity_o = 1'b0;
          assign pipe_tx2_compliance_o = 1'b0;
          assign pipe_tx2_char_is_k_o = 2'b00;
          assign pipe_tx2_data_o = 16'h0000;
          assign pipe_tx2_elec_idle_o = 1'b1;
          assign pipe_tx2_powerdown_o = 2'b00;

          assign pipe_rx3_char_is_k_o = 2'b00;
          assign pipe_rx3_data_o = 16'h0000;
          assign pipe_rx3_valid_o = 1'b0;
          assign pipe_rx3_chanisaligned_o = 1'b0;
          assign pipe_rx3_status_o = 3'b000;
          assign pipe_rx3_phy_status_o = 1'b0;
          assign pipe_rx3_elec_idle_o = 1'b1;
          assign pipe_rx3_polarity_o = 1'b0;
          assign pipe_tx3_compliance_o = 1'b0;
          assign pipe_tx3_char_is_k_o = 2'b00;
          assign pipe_tx3_data_o = 16'h0000;
          assign pipe_tx3_elec_idle_o = 1'b1;
          assign pipe_tx3_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      end      

      if (NO_OF_LANES >= 8) begin

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_4_i (

          .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),
          .pipe_rx_data_o(pipe_rx4_data_q),
          .pipe_rx_valid_o(pipe_rx4_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx4_status_o),
          .pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx4_polarity_i),
          .pipe_tx_compliance_i(pipe_tx4_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
          .pipe_tx_data_i(pipe_tx4_data_i),
          .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
          .pipe_rx_data_i(pipe_rx4_data_i),
          .pipe_rx_valid_i(pipe_rx4_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx4_status_i),
          .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx4_polarity_o),
          .pipe_tx_compliance_o(pipe_tx4_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
          .pipe_tx_data_o(pipe_tx4_data_o),
          .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_5_i (

          .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),
          .pipe_rx_data_o(pipe_rx5_data_q),
          .pipe_rx_valid_o(pipe_rx5_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx5_status_o),
          .pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx5_polarity_i),
          .pipe_tx_compliance_i(pipe_tx5_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
          .pipe_tx_data_i(pipe_tx5_data_i),
          .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
          .pipe_rx_data_i(pipe_rx5_data_i),
          .pipe_rx_valid_i(pipe_rx5_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx5_status_i),
          .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx5_polarity_o),
          .pipe_tx_compliance_o(pipe_tx5_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
          .pipe_tx_data_o(pipe_tx5_data_o),
          .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_6_i (

          .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),
          .pipe_rx_data_o(pipe_rx6_data_q),
          .pipe_rx_valid_o(pipe_rx6_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx6_status_o),
          .pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx6_polarity_i),
          .pipe_tx_compliance_i(pipe_tx6_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
          .pipe_tx_data_i(pipe_tx6_data_i),
          .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
          .pipe_rx_data_i(pipe_rx6_data_i),
          .pipe_rx_valid_i(pipe_rx6_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx6_status_i),
          .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx6_polarity_o),
          .pipe_tx_compliance_o(pipe_tx6_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
          .pipe_tx_data_o(pipe_tx6_data_o),
          .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

        pcie_pipe_lane_v6 # (
  
          .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)

        ) 
        pipe_lane_7_i (

          .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),
          .pipe_rx_data_o(pipe_rx7_data_q),
          .pipe_rx_valid_o(pipe_rx7_valid_o),
          .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
          .pipe_rx_status_o(pipe_rx7_status_o),
          .pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
          .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
          .pipe_rx_polarity_i(pipe_rx7_polarity_i),
          .pipe_tx_compliance_i(pipe_tx7_compliance_i),
          .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
          .pipe_tx_data_i(pipe_tx7_data_i),
          .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
          .pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
  
          .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
          .pipe_rx_data_i(pipe_rx7_data_i),
          .pipe_rx_valid_i(pipe_rx7_valid_i),
          .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
          .pipe_rx_status_i(pipe_rx7_status_i),
          .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
          .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
          .pipe_rx_polarity_o(pipe_rx7_polarity_o),
          .pipe_tx_compliance_o(pipe_tx7_compliance_o),
          .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
          .pipe_tx_data_o(pipe_tx7_data_o),
          .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
          .pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
      
          .pipe_clk(pipe_clk),
          .rst_n(rst_n)

        );

      end
      else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
          assign pipe_rx4_char_is_k_o = 2'b00;
          assign pipe_rx4_data_o = 16'h0000;
          assign pipe_rx4_valid_o = 1'b0;
          assign pipe_rx4_chanisaligned_o = 1'b0;
          assign pipe_rx4_status_o = 3'b000;
          assign pipe_rx4_phy_status_o = 1'b0;
          assign pipe_rx4_elec_idle_o = 1'b1;
          assign pipe_rx4_polarity_o = 1'b0;
          assign pipe_tx4_compliance_o = 1'b0;
          assign pipe_tx4_char_is_k_o = 2'b00;
          assign pipe_tx4_data_o = 16'h0000;
          assign pipe_tx4_elec_idle_o = 1'b1;
          assign pipe_tx4_powerdown_o = 2'b00;

          assign pipe_rx5_char_is_k_o = 2'b00;
          assign pipe_rx5_data_o = 16'h0000;
          assign pipe_rx5_valid_o = 1'b0;
          assign pipe_rx5_chanisaligned_o = 1'b0;
          assign pipe_rx5_status_o = 3'b000;
          assign pipe_rx5_phy_status_o = 1'b0;
          assign pipe_rx5_elec_idle_o = 1'b1;
          assign pipe_rx5_polarity_o = 1'b0;
          assign pipe_tx5_compliance_o = 1'b0;
          assign pipe_tx5_char_is_k_o = 2'b00;
          assign pipe_tx5_data_o = 16'h0000;
          assign pipe_tx5_elec_idle_o = 1'b1;
          assign pipe_tx5_powerdown_o = 2'b00;

          assign pipe_rx6_char_is_k_o = 2'b00;
          assign pipe_rx6_data_o = 16'h0000;
          assign pipe_rx6_valid_o = 1'b0;
          assign pipe_rx6_chanisaligned_o = 1'b0;
          assign pipe_rx6_status_o = 3'b000;
          assign pipe_rx6_phy_status_o = 1'b0;
          assign pipe_rx6_elec_idle_o = 1'b1;
          assign pipe_rx6_polarity_o = 1'b0;
          assign pipe_tx6_compliance_o = 1'b0;
          assign pipe_tx6_char_is_k_o = 2'b00;
          assign pipe_tx6_data_o = 16'h0000;
          assign pipe_tx6_elec_idle_o = 1'b1;
          assign pipe_tx6_powerdown_o = 2'b00;

          assign pipe_rx7_char_is_k_o = 2'b00;
          assign pipe_rx7_data_o = 16'h0000;
          assign pipe_rx7_valid_o = 1'b0;
          assign pipe_rx7_chanisaligned_o = 1'b0;
          assign pipe_rx7_status_o = 3'b000;
          assign pipe_rx7_phy_status_o = 1'b0;
          assign pipe_rx7_elec_idle_o = 1'b1;
          assign pipe_rx7_polarity_o = 1'b0;
          assign pipe_tx7_compliance_o = 1'b0;
          assign pipe_tx7_char_is_k_o = 2'b00;
          assign pipe_tx7_data_o = 16'h0000;
          assign pipe_tx7_elec_idle_o = 1'b1;
          assign pipe_tx7_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      end      

    endgenerate

//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

    assign pipe_rx0_char_is_k_o  = pipe_rx0_char_is_k_q;
    assign pipe_rx0_data_o = pipe_rx0_data_q;
    assign pipe_rx1_char_is_k_o  = pipe_rx1_char_is_k_q;
    assign pipe_rx1_data_o = pipe_rx1_data_q;
    assign pipe_rx2_char_is_k_o  = pipe_rx2_char_is_k_q;
    assign pipe_rx2_data_o = pipe_rx2_data_q;
    assign pipe_rx3_char_is_k_o  = pipe_rx3_char_is_k_q;
    assign pipe_rx3_data_o = pipe_rx3_data_q;
    assign pipe_rx4_char_is_k_o  = pipe_rx4_char_is_k_q;
    assign pipe_rx4_data_o = pipe_rx4_data_q;
    assign pipe_rx5_char_is_k_o  = pipe_rx5_char_is_k_q;
    assign pipe_rx5_data_o = pipe_rx5_data_q;
    assign pipe_rx6_char_is_k_o  = pipe_rx6_char_is_k_q;
    assign pipe_rx6_data_o = pipe_rx6_data_q;
    assign pipe_rx7_char_is_k_o  = pipe_rx7_char_is_k_q;
    assign pipe_rx7_data_o = pipe_rx7_data_q;

//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

endmodule