module clock_enable(
	input Clk_100M,
	output slow_clk_en
);
    reg [26:0]counter=0;
	
    always @(posedge Clk_100M)
    begin
       counter <= (counter>=24999) ? 0 : counter + 1;
    end

    assign slow_clk_en = (counter == 24999) ? 1'b1 : 1'b0;
endmodule