module axis_slr_register_dest #(
  parameter WIDTH = 8,
  parameter DEPTH = 16
) (
  // System Signals
  input  wire             clk,
  input  wire             rst,

  // Slave side
  input  wire             din_valid,
  input  wire [WIDTH-1:0] din,
  output wire             din_ready,

  // Master side
  output wire             dout_valid,
  output wire [WIDTH-1:0] dout,
  input  wire             dout_ready
);

  // Make sure SLL Registers are used for crossing SLR boundary
  (* USER_SLL_REG="true" *)                     reg  sll_valid = 1'b0;
  (* USER_SLL_REG="true", shreg_extract="no" *) reg  [WIDTH-1:0] sll_data;
  (* USER_SLL_REG="true", keep="true" *)        reg  sll_ready = 1'b0;

  // If FIFO is empty or downstream can accept we ready the input to avoid overflow
  always @(posedge clk) begin
    sll_ready <= dout_ready | ~dout_valid;
    sll_data  <= din;
    sll_valid <= din_valid;
  end

  wire dout_ready_n;

  simple_axis_srl_fifo #(
    .WIDTH (WIDTH),
    .DEPTH (DEPTH)
  ) srl_fifo (
    .clk        (clk),
    .rst        (rst),

    .din        (sll_data),
    .din_valid  (sll_valid),

    .dout       (dout),
    .dout_valid (dout_valid),
    .dout_ready (dout_ready_n),

    .count      ()
  );

  assign din_ready    = sll_ready;
  assign dout_ready_n = dout_ready & dout_valid;


endmodule