module p_pipe2data #( parameter PipeSpec = `PS_def ) (
        input clock,
        input reset,

        inout [`P_m(PipeSpec):0] pipe,

        output [`P_Data_m(PipeSpec):0] data,
        output data_valid
    );

    wire [`P_Data_m(PipeSpec):0] in_data;
    wire in_valid;
    reg  in_ready;

    p_unpack_valid_ready #( .PipeSpec(PipeSpec) ) p_u_v( pipe, in_valid, in_ready );
    p_unpack_data #( .PipeSpec(PipeSpec) ) p_u_d( pipe, in_data  );

    reg [`P_Data_m(PipeSpec):0] p2d_data;
    reg                         p2d_data_valid;

    always @(posedge clock) begin
        if ( reset ) begin
            p2d_data <= 0;
            p2d_data_valid <= 0;
            in_ready <= 1;
        end else begin
            if ( in_valid ) begin
                p2d_data <= in_data;
                p2d_data_valid <= 1;
            end
        end
    end

    assign data = p2d_data;
    assign data_valid = p2d_data_valid;

endmodule