module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0 (
		input  wire        Sys_Clk_clk_clk,                                //                              Sys_Clk_clk.clk
		input  wire        Char_Buf_DMA_reset_reset_bridge_in_reset_reset, // Char_Buf_DMA_reset_reset_bridge_in_reset.reset
		input  wire [31:0] Char_Buf_DMA_avalon_dma_master_address,         //           Char_Buf_DMA_avalon_dma_master.address
		output wire        Char_Buf_DMA_avalon_dma_master_waitrequest,     //                                         .waitrequest
		input  wire        Char_Buf_DMA_avalon_dma_master_read,            //                                         .read
		output wire [7:0]  Char_Buf_DMA_avalon_dma_master_readdata,        //                                         .readdata
		output wire        Char_Buf_DMA_avalon_dma_master_readdatavalid,   //                                         .readdatavalid
		input  wire        Char_Buf_DMA_avalon_dma_master_lock,            //                                         .lock
		output wire [10:0] Onchip_SRAM_s2_address,                         //                           Onchip_SRAM_s2.address
		output wire        Onchip_SRAM_s2_write,                           //                                         .write
		input  wire [31:0] Onchip_SRAM_s2_readdata,                        //                                         .readdata
		output wire [31:0] Onchip_SRAM_s2_writedata,                       //                                         .writedata
		output wire [3:0]  Onchip_SRAM_s2_byteenable,                      //                                         .byteenable
		output wire        Onchip_SRAM_s2_chipselect,                      //                                         .chipselect
		output wire        Onchip_SRAM_s2_clken                            //                                         .clken
	);

	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest;   // Char_Buf_DMA_avalon_dma_master_agent:av_waitrequest -> Char_Buf_DMA_avalon_dma_master_translator:uav_waitrequest
	wire    [7:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata;      // Char_Buf_DMA_avalon_dma_master_agent:av_readdata -> Char_Buf_DMA_avalon_dma_master_translator:uav_readdata
	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess;   // Char_Buf_DMA_avalon_dma_master_translator:uav_debugaccess -> Char_Buf_DMA_avalon_dma_master_agent:av_debugaccess
	wire   [31:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address;       // Char_Buf_DMA_avalon_dma_master_translator:uav_address -> Char_Buf_DMA_avalon_dma_master_agent:av_address
	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read;          // Char_Buf_DMA_avalon_dma_master_translator:uav_read -> Char_Buf_DMA_avalon_dma_master_agent:av_read
	wire    [0:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable;    // Char_Buf_DMA_avalon_dma_master_translator:uav_byteenable -> Char_Buf_DMA_avalon_dma_master_agent:av_byteenable
	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid; // Char_Buf_DMA_avalon_dma_master_agent:av_readdatavalid -> Char_Buf_DMA_avalon_dma_master_translator:uav_readdatavalid
	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock;          // Char_Buf_DMA_avalon_dma_master_translator:uav_lock -> Char_Buf_DMA_avalon_dma_master_agent:av_lock
	wire          char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write;         // Char_Buf_DMA_avalon_dma_master_translator:uav_write -> Char_Buf_DMA_avalon_dma_master_agent:av_write
	wire    [7:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata;     // Char_Buf_DMA_avalon_dma_master_translator:uav_writedata -> Char_Buf_DMA_avalon_dma_master_agent:av_writedata
	wire    [0:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount;    // Char_Buf_DMA_avalon_dma_master_translator:uav_burstcount -> Char_Buf_DMA_avalon_dma_master_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                                 // rsp_mux:src_valid -> Char_Buf_DMA_avalon_dma_master_agent:rp_valid
	wire   [74:0] rsp_mux_src_data;                                                                  // rsp_mux:src_data -> Char_Buf_DMA_avalon_dma_master_agent:rp_data
	wire          rsp_mux_src_ready;                                                                 // Char_Buf_DMA_avalon_dma_master_agent:rp_ready -> rsp_mux:src_ready
	wire    [0:0] rsp_mux_src_channel;                                                               // rsp_mux:src_channel -> Char_Buf_DMA_avalon_dma_master_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                         // rsp_mux:src_startofpacket -> Char_Buf_DMA_avalon_dma_master_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                           // rsp_mux:src_endofpacket -> Char_Buf_DMA_avalon_dma_master_agent:rp_endofpacket
	wire   [31:0] onchip_sram_s2_agent_m0_readdata;                                                  // Onchip_SRAM_s2_translator:uav_readdata -> Onchip_SRAM_s2_agent:m0_readdata
	wire          onchip_sram_s2_agent_m0_waitrequest;                                               // Onchip_SRAM_s2_translator:uav_waitrequest -> Onchip_SRAM_s2_agent:m0_waitrequest
	wire          onchip_sram_s2_agent_m0_debugaccess;                                               // Onchip_SRAM_s2_agent:m0_debugaccess -> Onchip_SRAM_s2_translator:uav_debugaccess
	wire   [31:0] onchip_sram_s2_agent_m0_address;                                                   // Onchip_SRAM_s2_agent:m0_address -> Onchip_SRAM_s2_translator:uav_address
	wire    [3:0] onchip_sram_s2_agent_m0_byteenable;                                                // Onchip_SRAM_s2_agent:m0_byteenable -> Onchip_SRAM_s2_translator:uav_byteenable
	wire          onchip_sram_s2_agent_m0_read;                                                      // Onchip_SRAM_s2_agent:m0_read -> Onchip_SRAM_s2_translator:uav_read
	wire          onchip_sram_s2_agent_m0_readdatavalid;                                             // Onchip_SRAM_s2_translator:uav_readdatavalid -> Onchip_SRAM_s2_agent:m0_readdatavalid
	wire          onchip_sram_s2_agent_m0_lock;                                                      // Onchip_SRAM_s2_agent:m0_lock -> Onchip_SRAM_s2_translator:uav_lock
	wire   [31:0] onchip_sram_s2_agent_m0_writedata;                                                 // Onchip_SRAM_s2_agent:m0_writedata -> Onchip_SRAM_s2_translator:uav_writedata
	wire          onchip_sram_s2_agent_m0_write;                                                     // Onchip_SRAM_s2_agent:m0_write -> Onchip_SRAM_s2_translator:uav_write
	wire    [2:0] onchip_sram_s2_agent_m0_burstcount;                                                // Onchip_SRAM_s2_agent:m0_burstcount -> Onchip_SRAM_s2_translator:uav_burstcount
	wire          onchip_sram_s2_agent_rf_source_valid;                                              // Onchip_SRAM_s2_agent:rf_source_valid -> Onchip_SRAM_s2_agent_rsp_fifo:in_valid
	wire  [102:0] onchip_sram_s2_agent_rf_source_data;                                               // Onchip_SRAM_s2_agent:rf_source_data -> Onchip_SRAM_s2_agent_rsp_fifo:in_data
	wire          onchip_sram_s2_agent_rf_source_ready;                                              // Onchip_SRAM_s2_agent_rsp_fifo:in_ready -> Onchip_SRAM_s2_agent:rf_source_ready
	wire          onchip_sram_s2_agent_rf_source_startofpacket;                                      // Onchip_SRAM_s2_agent:rf_source_startofpacket -> Onchip_SRAM_s2_agent_rsp_fifo:in_startofpacket
	wire          onchip_sram_s2_agent_rf_source_endofpacket;                                        // Onchip_SRAM_s2_agent:rf_source_endofpacket -> Onchip_SRAM_s2_agent_rsp_fifo:in_endofpacket
	wire          onchip_sram_s2_agent_rsp_fifo_out_valid;                                           // Onchip_SRAM_s2_agent_rsp_fifo:out_valid -> Onchip_SRAM_s2_agent:rf_sink_valid
	wire  [102:0] onchip_sram_s2_agent_rsp_fifo_out_data;                                            // Onchip_SRAM_s2_agent_rsp_fifo:out_data -> Onchip_SRAM_s2_agent:rf_sink_data
	wire          onchip_sram_s2_agent_rsp_fifo_out_ready;                                           // Onchip_SRAM_s2_agent:rf_sink_ready -> Onchip_SRAM_s2_agent_rsp_fifo:out_ready
	wire          onchip_sram_s2_agent_rsp_fifo_out_startofpacket;                                   // Onchip_SRAM_s2_agent_rsp_fifo:out_startofpacket -> Onchip_SRAM_s2_agent:rf_sink_startofpacket
	wire          onchip_sram_s2_agent_rsp_fifo_out_endofpacket;                                     // Onchip_SRAM_s2_agent_rsp_fifo:out_endofpacket -> Onchip_SRAM_s2_agent:rf_sink_endofpacket
	wire          char_buf_dma_avalon_dma_master_agent_cp_valid;                                     // Char_Buf_DMA_avalon_dma_master_agent:cp_valid -> router:sink_valid
	wire   [74:0] char_buf_dma_avalon_dma_master_agent_cp_data;                                      // Char_Buf_DMA_avalon_dma_master_agent:cp_data -> router:sink_data
	wire          char_buf_dma_avalon_dma_master_agent_cp_ready;                                     // router:sink_ready -> Char_Buf_DMA_avalon_dma_master_agent:cp_ready
	wire          char_buf_dma_avalon_dma_master_agent_cp_startofpacket;                             // Char_Buf_DMA_avalon_dma_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          char_buf_dma_avalon_dma_master_agent_cp_endofpacket;                               // Char_Buf_DMA_avalon_dma_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                  // router:src_valid -> cmd_demux:sink_valid
	wire   [74:0] router_src_data;                                                                   // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                  // cmd_demux:sink_ready -> router:src_ready
	wire    [0:0] router_src_channel;                                                                // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                          // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                            // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          onchip_sram_s2_agent_rp_valid;                                                     // Onchip_SRAM_s2_agent:rp_valid -> router_001:sink_valid
	wire  [101:0] onchip_sram_s2_agent_rp_data;                                                      // Onchip_SRAM_s2_agent:rp_data -> router_001:sink_data
	wire          onchip_sram_s2_agent_rp_ready;                                                     // router_001:sink_ready -> Onchip_SRAM_s2_agent:rp_ready
	wire          onchip_sram_s2_agent_rp_startofpacket;                                             // Onchip_SRAM_s2_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          onchip_sram_s2_agent_rp_endofpacket;                                               // Onchip_SRAM_s2_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                              // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire   [74:0] cmd_demux_src0_data;                                                               // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                              // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [0:0] cmd_demux_src0_channel;                                                            // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                      // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                        // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                              // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire   [74:0] rsp_demux_src0_data;                                                               // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                              // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [0:0] rsp_demux_src0_channel;                                                            // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                      // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                        // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          cmd_mux_src_valid;                                                                 // cmd_mux:src_valid -> Onchip_SRAM_s2_cmd_width_adapter:in_valid
	wire   [74:0] cmd_mux_src_data;                                                                  // cmd_mux:src_data -> Onchip_SRAM_s2_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                                 // Onchip_SRAM_s2_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [0:0] cmd_mux_src_channel;                                                               // cmd_mux:src_channel -> Onchip_SRAM_s2_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                         // cmd_mux:src_startofpacket -> Onchip_SRAM_s2_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                           // cmd_mux:src_endofpacket -> Onchip_SRAM_s2_cmd_width_adapter:in_endofpacket
	wire          onchip_sram_s2_cmd_width_adapter_src_valid;                                        // Onchip_SRAM_s2_cmd_width_adapter:out_valid -> Onchip_SRAM_s2_agent:cp_valid
	wire  [101:0] onchip_sram_s2_cmd_width_adapter_src_data;                                         // Onchip_SRAM_s2_cmd_width_adapter:out_data -> Onchip_SRAM_s2_agent:cp_data
	wire          onchip_sram_s2_cmd_width_adapter_src_ready;                                        // Onchip_SRAM_s2_agent:cp_ready -> Onchip_SRAM_s2_cmd_width_adapter:out_ready
	wire    [0:0] onchip_sram_s2_cmd_width_adapter_src_channel;                                      // Onchip_SRAM_s2_cmd_width_adapter:out_channel -> Onchip_SRAM_s2_agent:cp_channel
	wire          onchip_sram_s2_cmd_width_adapter_src_startofpacket;                                // Onchip_SRAM_s2_cmd_width_adapter:out_startofpacket -> Onchip_SRAM_s2_agent:cp_startofpacket
	wire          onchip_sram_s2_cmd_width_adapter_src_endofpacket;                                  // Onchip_SRAM_s2_cmd_width_adapter:out_endofpacket -> Onchip_SRAM_s2_agent:cp_endofpacket
	wire          router_001_src_valid;                                                              // router_001:src_valid -> Onchip_SRAM_s2_rsp_width_adapter:in_valid
	wire  [101:0] router_001_src_data;                                                               // router_001:src_data -> Onchip_SRAM_s2_rsp_width_adapter:in_data
	wire          router_001_src_ready;                                                              // Onchip_SRAM_s2_rsp_width_adapter:in_ready -> router_001:src_ready
	wire    [0:0] router_001_src_channel;                                                            // router_001:src_channel -> Onchip_SRAM_s2_rsp_width_adapter:in_channel
	wire          router_001_src_startofpacket;                                                      // router_001:src_startofpacket -> Onchip_SRAM_s2_rsp_width_adapter:in_startofpacket
	wire          router_001_src_endofpacket;                                                        // router_001:src_endofpacket -> Onchip_SRAM_s2_rsp_width_adapter:in_endofpacket
	wire          onchip_sram_s2_rsp_width_adapter_src_valid;                                        // Onchip_SRAM_s2_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire   [74:0] onchip_sram_s2_rsp_width_adapter_src_data;                                         // Onchip_SRAM_s2_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          onchip_sram_s2_rsp_width_adapter_src_ready;                                        // rsp_demux:sink_ready -> Onchip_SRAM_s2_rsp_width_adapter:out_ready
	wire    [0:0] onchip_sram_s2_rsp_width_adapter_src_channel;                                      // Onchip_SRAM_s2_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          onchip_sram_s2_rsp_width_adapter_src_startofpacket;                                // Onchip_SRAM_s2_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          onchip_sram_s2_rsp_width_adapter_src_endofpacket;                                  // Onchip_SRAM_s2_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          onchip_sram_s2_agent_rdata_fifo_src_valid;                                         // Onchip_SRAM_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] onchip_sram_s2_agent_rdata_fifo_src_data;                                          // Onchip_SRAM_s2_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	wire          onchip_sram_s2_agent_rdata_fifo_src_ready;                                         // avalon_st_adapter:in_0_ready -> Onchip_SRAM_s2_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_out_0_valid;                                                     // avalon_st_adapter:out_0_valid -> Onchip_SRAM_s2_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                                      // avalon_st_adapter:out_0_data -> Onchip_SRAM_s2_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                     // Onchip_SRAM_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                     // avalon_st_adapter:out_0_error -> Onchip_SRAM_s2_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (8),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (1),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (1),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (1),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) char_buf_dma_avalon_dma_master_translator (
		.clk                    (Sys_Clk_clk_clk),                                                                   //                       clk.clk
		.reset                  (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),                                    //                     reset.reset
		.uav_address            (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (Char_Buf_DMA_avalon_dma_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (Char_Buf_DMA_avalon_dma_master_waitrequest),                                        //                          .waitrequest
		.av_read                (Char_Buf_DMA_avalon_dma_master_read),                                               //                          .read
		.av_readdata            (Char_Buf_DMA_avalon_dma_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (Char_Buf_DMA_avalon_dma_master_readdatavalid),                                      //                          .readdatavalid
		.av_lock                (Char_Buf_DMA_avalon_dma_master_lock),                                               //                          .lock
		.av_burstcount          (1'b1),                                                                              //               (terminated)
		.av_byteenable          (1'b1),                                                                              //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                              //               (terminated)
		.av_begintransfer       (1'b0),                                                                              //               (terminated)
		.av_chipselect          (1'b0),                                                                              //               (terminated)
		.av_write               (1'b0),                                                                              //               (terminated)
		.av_writedata           (8'b00000000),                                                                       //               (terminated)
		.av_debugaccess         (1'b0),                                                                              //               (terminated)
		.uav_clken              (),                                                                                  //               (terminated)
		.av_clken               (1'b1),                                                                              //               (terminated)
		.uav_response           (2'b00),                                                                             //               (terminated)
		.av_response            (),                                                                                  //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                              //               (terminated)
		.av_writeresponsevalid  ()                                                                                   //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (11),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_sram_s2_translator (
		.clk                    (Sys_Clk_clk_clk),                                //                      clk.clk
		.reset                  (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_sram_s2_agent_m0_address),                // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_sram_s2_agent_m0_burstcount),             //                         .burstcount
		.uav_read               (onchip_sram_s2_agent_m0_read),                   //                         .read
		.uav_write              (onchip_sram_s2_agent_m0_write),                  //                         .write
		.uav_waitrequest        (onchip_sram_s2_agent_m0_waitrequest),            //                         .waitrequest
		.uav_readdatavalid      (onchip_sram_s2_agent_m0_readdatavalid),          //                         .readdatavalid
		.uav_byteenable         (onchip_sram_s2_agent_m0_byteenable),             //                         .byteenable
		.uav_readdata           (onchip_sram_s2_agent_m0_readdata),               //                         .readdata
		.uav_writedata          (onchip_sram_s2_agent_m0_writedata),              //                         .writedata
		.uav_lock               (onchip_sram_s2_agent_m0_lock),                   //                         .lock
		.uav_debugaccess        (onchip_sram_s2_agent_m0_debugaccess),            //                         .debugaccess
		.av_address             (Onchip_SRAM_s2_address),                         //      avalon_anti_slave_0.address
		.av_write               (Onchip_SRAM_s2_write),                           //                         .write
		.av_readdata            (Onchip_SRAM_s2_readdata),                        //                         .readdata
		.av_writedata           (Onchip_SRAM_s2_writedata),                       //                         .writedata
		.av_byteenable          (Onchip_SRAM_s2_byteenable),                      //                         .byteenable
		.av_chipselect          (Onchip_SRAM_s2_chipselect),                      //                         .chipselect
		.av_clken               (Onchip_SRAM_s2_clken),                           //                         .clken
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (74),
		.PKT_ORI_BURST_SIZE_L      (72),
		.PKT_RESPONSE_STATUS_H     (71),
		.PKT_RESPONSE_STATUS_L     (70),
		.PKT_QOS_H                 (59),
		.PKT_QOS_L                 (59),
		.PKT_DATA_SIDEBAND_H       (57),
		.PKT_DATA_SIDEBAND_L       (57),
		.PKT_ADDR_SIDEBAND_H       (56),
		.PKT_ADDR_SIDEBAND_L       (56),
		.PKT_BURST_TYPE_H          (55),
		.PKT_BURST_TYPE_L          (54),
		.PKT_CACHE_H               (69),
		.PKT_CACHE_L               (66),
		.PKT_THREAD_ID_H           (62),
		.PKT_THREAD_ID_L           (62),
		.PKT_BURST_SIZE_H          (53),
		.PKT_BURST_SIZE_L          (51),
		.PKT_TRANS_EXCLUSIVE       (46),
		.PKT_TRANS_LOCK            (45),
		.PKT_BEGIN_BURST           (58),
		.PKT_PROTECTION_H          (65),
		.PKT_PROTECTION_L          (63),
		.PKT_BURSTWRAP_H           (50),
		.PKT_BURSTWRAP_L           (50),
		.PKT_BYTE_CNT_H            (49),
		.PKT_BYTE_CNT_L            (47),
		.PKT_ADDR_H                (40),
		.PKT_ADDR_L                (9),
		.PKT_TRANS_COMPRESSED_READ (41),
		.PKT_TRANS_POSTED          (42),
		.PKT_TRANS_WRITE           (43),
		.PKT_TRANS_READ            (44),
		.PKT_DATA_H                (7),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_SRC_ID_H              (60),
		.PKT_SRC_ID_L              (60),
		.PKT_DEST_ID_H             (61),
		.PKT_DEST_ID_L             (61),
		.ST_DATA_W                 (75),
		.ST_CHANNEL_W              (1),
		.AV_BURSTCOUNT_W           (1),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) char_buf_dma_avalon_dma_master_agent (
		.clk                   (Sys_Clk_clk_clk),                                                                   //       clk.clk
		.reset                 (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),                                    // clk_reset.reset
		.av_address            (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (char_buf_dma_avalon_dma_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (char_buf_dma_avalon_dma_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (char_buf_dma_avalon_dma_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (char_buf_dma_avalon_dma_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (char_buf_dma_avalon_dma_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                                 //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                                  //          .data
		.rp_channel            (rsp_mux_src_channel),                                                               //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                         //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                           //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                                 //          .ready
		.av_response           (),                                                                                  // (terminated)
		.av_writeresponsevalid ()                                                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (101),
		.PKT_ORI_BURST_SIZE_L      (99),
		.PKT_RESPONSE_STATUS_H     (98),
		.PKT_RESPONSE_STATUS_L     (97),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (92),
		.PKT_PROTECTION_L          (90),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (87),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (88),
		.PKT_DEST_ID_L             (88),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (1),
		.ST_DATA_W                 (102),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) onchip_sram_s2_agent (
		.clk                     (Sys_Clk_clk_clk),                                    //             clk.clk
		.reset                   (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),     //       clk_reset.reset
		.m0_address              (onchip_sram_s2_agent_m0_address),                    //              m0.address
		.m0_burstcount           (onchip_sram_s2_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (onchip_sram_s2_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (onchip_sram_s2_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (onchip_sram_s2_agent_m0_lock),                       //                .lock
		.m0_readdata             (onchip_sram_s2_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (onchip_sram_s2_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (onchip_sram_s2_agent_m0_read),                       //                .read
		.m0_waitrequest          (onchip_sram_s2_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (onchip_sram_s2_agent_m0_writedata),                  //                .writedata
		.m0_write                (onchip_sram_s2_agent_m0_write),                      //                .write
		.rp_endofpacket          (onchip_sram_s2_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (onchip_sram_s2_agent_rp_ready),                      //                .ready
		.rp_valid                (onchip_sram_s2_agent_rp_valid),                      //                .valid
		.rp_data                 (onchip_sram_s2_agent_rp_data),                       //                .data
		.rp_startofpacket        (onchip_sram_s2_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (onchip_sram_s2_cmd_width_adapter_src_ready),         //              cp.ready
		.cp_valid                (onchip_sram_s2_cmd_width_adapter_src_valid),         //                .valid
		.cp_data                 (onchip_sram_s2_cmd_width_adapter_src_data),          //                .data
		.cp_startofpacket        (onchip_sram_s2_cmd_width_adapter_src_startofpacket), //                .startofpacket
		.cp_endofpacket          (onchip_sram_s2_cmd_width_adapter_src_endofpacket),   //                .endofpacket
		.cp_channel              (onchip_sram_s2_cmd_width_adapter_src_channel),       //                .channel
		.rf_sink_ready           (onchip_sram_s2_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (onchip_sram_s2_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (onchip_sram_s2_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (onchip_sram_s2_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (onchip_sram_s2_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (onchip_sram_s2_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (onchip_sram_s2_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (onchip_sram_s2_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (onchip_sram_s2_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (onchip_sram_s2_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                      // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                      //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                       //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                      //                .error
		.rdata_fifo_src_ready    (onchip_sram_s2_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_sram_s2_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (onchip_sram_s2_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                              //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (103),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_sram_s2_agent_rsp_fifo (
		.clk               (Sys_Clk_clk_clk),                                 //       clk.clk
		.reset             (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.in_data           (onchip_sram_s2_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_sram_s2_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_sram_s2_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_sram_s2_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_sram_s2_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_sram_s2_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_sram_s2_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_sram_s2_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_sram_s2_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_sram_s2_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router router (
		.sink_ready         (char_buf_dma_avalon_dma_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (char_buf_dma_avalon_dma_master_agent_cp_valid),         //          .valid
		.sink_data          (char_buf_dma_avalon_dma_master_agent_cp_data),          //          .data
		.sink_startofpacket (char_buf_dma_avalon_dma_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (char_buf_dma_avalon_dma_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (Sys_Clk_clk_clk),                                       //       clk.clk
		.reset              (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),        // clk_reset.reset
		.src_ready          (router_src_ready),                                      //       src.ready
		.src_valid          (router_src_valid),                                      //          .valid
		.src_data           (router_src_data),                                       //          .data
		.src_channel        (router_src_channel),                                    //          .channel
		.src_startofpacket  (router_src_startofpacket),                              //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                 //          .endofpacket
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (onchip_sram_s2_agent_rp_ready),                  //      sink.ready
		.sink_valid         (onchip_sram_s2_agent_rp_valid),                  //          .valid
		.sink_data          (onchip_sram_s2_agent_rp_data),                   //          .data
		.sink_startofpacket (onchip_sram_s2_agent_rp_startofpacket),          //          .startofpacket
		.sink_endofpacket   (onchip_sram_s2_agent_rp_endofpacket),            //          .endofpacket
		.clk                (Sys_Clk_clk_clk),                                //       clk.clk
		.reset              (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                           //       src.ready
		.src_valid          (router_001_src_valid),                           //          .valid
		.src_data           (router_001_src_data),                            //          .data
		.src_channel        (router_001_src_channel),                         //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                      //          .endofpacket
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (Sys_Clk_clk_clk),                                //       clk.clk
		.reset              (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                               //      sink.ready
		.sink_channel       (router_src_channel),                             //          .channel
		.sink_data          (router_src_data),                                //          .data
		.sink_startofpacket (router_src_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                         //          .endofpacket
		.sink_valid         (router_src_valid),                               //          .valid
		.src0_ready         (cmd_demux_src0_ready),                           //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                           //          .valid
		.src0_data          (cmd_demux_src0_data),                            //          .data
		.src0_channel       (cmd_demux_src0_channel),                         //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                   //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                      //          .endofpacket
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (Sys_Clk_clk_clk),                                //       clk.clk
		.reset               (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                              //       src.ready
		.src_valid           (cmd_mux_src_valid),                              //          .valid
		.src_data            (cmd_mux_src_data),                               //          .data
		.src_channel         (cmd_mux_src_channel),                            //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                      //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                        //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                           //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                           //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                         //          .channel
		.sink0_data          (cmd_demux_src0_data),                            //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                   //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                      //          .endofpacket
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_demux rsp_demux (
		.clk                (Sys_Clk_clk_clk),                                    //       clk.clk
		.reset              (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
		.sink_ready         (onchip_sram_s2_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (onchip_sram_s2_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (onchip_sram_s2_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (onchip_sram_s2_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (onchip_sram_s2_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (onchip_sram_s2_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_src0_ready),                               //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                               //          .valid
		.src0_data          (rsp_demux_src0_data),                                //          .data
		.src0_channel       (rsp_demux_src0_channel),                             //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                       //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                          //          .endofpacket
	);

	Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (Sys_Clk_clk_clk),                                //       clk.clk
		.reset               (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                              //       src.ready
		.src_valid           (rsp_mux_src_valid),                              //          .valid
		.src_data            (rsp_mux_src_data),                               //          .data
		.src_channel         (rsp_mux_src_channel),                            //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                      //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                        //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                           //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                           //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                         //          .channel
		.sink0_data          (rsp_demux_src0_data),                            //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                   //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                      //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (40),
		.IN_PKT_ADDR_L                 (9),
		.IN_PKT_DATA_H                 (7),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (8),
		.IN_PKT_BYTEEN_L               (8),
		.IN_PKT_BYTE_CNT_H             (49),
		.IN_PKT_BYTE_CNT_L             (47),
		.IN_PKT_TRANS_COMPRESSED_READ  (41),
		.IN_PKT_TRANS_WRITE            (43),
		.IN_PKT_BURSTWRAP_H            (50),
		.IN_PKT_BURSTWRAP_L            (50),
		.IN_PKT_BURST_SIZE_H           (53),
		.IN_PKT_BURST_SIZE_L           (51),
		.IN_PKT_RESPONSE_STATUS_H      (71),
		.IN_PKT_RESPONSE_STATUS_L      (70),
		.IN_PKT_TRANS_EXCLUSIVE        (46),
		.IN_PKT_BURST_TYPE_H           (55),
		.IN_PKT_BURST_TYPE_L           (54),
		.IN_PKT_ORI_BURST_SIZE_L       (72),
		.IN_PKT_ORI_BURST_SIZE_H       (74),
		.IN_ST_DATA_W                  (75),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (76),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (80),
		.OUT_PKT_BURST_SIZE_L          (78),
		.OUT_PKT_RESPONSE_STATUS_H     (98),
		.OUT_PKT_RESPONSE_STATUS_L     (97),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (82),
		.OUT_PKT_BURST_TYPE_L          (81),
		.OUT_PKT_ORI_BURST_SIZE_L      (99),
		.OUT_PKT_ORI_BURST_SIZE_H      (101),
		.OUT_ST_DATA_W                 (102),
		.ST_CHANNEL_W                  (1),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) onchip_sram_s2_cmd_width_adapter (
		.clk                  (Sys_Clk_clk_clk),                                    //       clk.clk
		.reset                (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                  //      sink.valid
		.in_channel           (cmd_mux_src_channel),                                //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                          //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                            //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                  //          .ready
		.in_data              (cmd_mux_src_data),                                   //          .data
		.out_endofpacket      (onchip_sram_s2_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (onchip_sram_s2_cmd_width_adapter_src_data),          //          .data
		.out_channel          (onchip_sram_s2_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (onchip_sram_s2_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (onchip_sram_s2_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (onchip_sram_s2_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                              // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (76),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (77),
		.IN_PKT_BURSTWRAP_L            (77),
		.IN_PKT_BURST_SIZE_H           (80),
		.IN_PKT_BURST_SIZE_L           (78),
		.IN_PKT_RESPONSE_STATUS_H      (98),
		.IN_PKT_RESPONSE_STATUS_L      (97),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (82),
		.IN_PKT_BURST_TYPE_L           (81),
		.IN_PKT_ORI_BURST_SIZE_L       (99),
		.IN_PKT_ORI_BURST_SIZE_H       (101),
		.IN_ST_DATA_W                  (102),
		.OUT_PKT_ADDR_H                (40),
		.OUT_PKT_ADDR_L                (9),
		.OUT_PKT_DATA_H                (7),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (8),
		.OUT_PKT_BYTEEN_L              (8),
		.OUT_PKT_BYTE_CNT_H            (49),
		.OUT_PKT_BYTE_CNT_L            (47),
		.OUT_PKT_TRANS_COMPRESSED_READ (41),
		.OUT_PKT_BURST_SIZE_H          (53),
		.OUT_PKT_BURST_SIZE_L          (51),
		.OUT_PKT_RESPONSE_STATUS_H     (71),
		.OUT_PKT_RESPONSE_STATUS_L     (70),
		.OUT_PKT_TRANS_EXCLUSIVE       (46),
		.OUT_PKT_BURST_TYPE_H          (55),
		.OUT_PKT_BURST_TYPE_L          (54),
		.OUT_PKT_ORI_BURST_SIZE_L      (72),
		.OUT_PKT_ORI_BURST_SIZE_H      (74),
		.OUT_ST_DATA_W                 (75),
		.ST_CHANNEL_W                  (1),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) onchip_sram_s2_rsp_width_adapter (
		.clk                  (Sys_Clk_clk_clk),                                    //       clk.clk
		.reset                (Char_Buf_DMA_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
		.in_valid             (router_001_src_valid),                               //      sink.valid
		.in_channel           (router_001_src_channel),                             //          .channel
		.in_startofpacket     (router_001_src_startofpacket),                       //          .startofpacket
		.in_endofpacket       (router_001_src_endofpacket),                         //          .endofpacket
		.in_ready             (router_001_src_ready),                               //          .ready
		.in_data              (router_001_src_data),                                //          .data
		.out_endofpacket      (onchip_sram_s2_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (onchip_sram_s2_rsp_width_adapter_src_data),          //          .data
		.out_channel          (onchip_sram_s2_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (onchip_sram_s2_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (onchip_sram_s2_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (onchip_sram_s2_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                              // (terminated)
	);

	Computer_System_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (Sys_Clk_clk_clk),                                // in_clk_0.clk
		.in_rst_0_reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (onchip_sram_s2_agent_rdata_fifo_src_data),       //     in_0.data
		.in_0_valid     (onchip_sram_s2_agent_rdata_fifo_src_valid),      //         .valid
		.in_0_ready     (onchip_sram_s2_agent_rdata_fifo_src_ready),      //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                   //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                  //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                  //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                   //         .error
	);

endmodule