module clk_enable(
    input wire clk_in,
    input wire reset,
	input wire[15:0] divider,
    output reg clk_en
);

	reg [15:0] count = 0;

	always @(posedge clk_in) begin
		if (reset == 1) begin
			clk_en <= 0;
			count <= 0;
		end	else begin
			if (count >= divider) begin
				clk_en <= 1'b1;
				count <= 0;
			end else begin
				clk_en <= 1'b0;
				count <= count + 1'b1;
			end
		end
	end

endmodule