module AddSub
  (
   input wire 	      alufn0,
   input wire [31:0]  a,
   input wire [31:0]  b,

   output wire [31:0] s,
   output wire 	      z,
   output wire 	      v,
   output wire 	      n
   );

   wire [31:0] 	      xb;

   integer 	      i = 0;
   
   assign xb = b ^ {32{alufn0}};
   assign s = a + xb + alufn0;
   assign z = (s == 32'h00000000);
   assign v = (a[31] & xb[31] & (~s[31])) + ((~a[31]) & (~xb[31]) & s[31]);
   assign n = s[31]; 

endmodule