module MUX_RD_RAW(RD_RAW_Sel,DM_RD,Pr_RD,RD_RAW);
//interface
	input [31:0] RD_RAW_Sel;

	input [31:0] DM_RD;
	input [31:0] Pr_RD;

	output reg [31:0] RD_RAW;

//select logic
	always @(*)
		begin
			case(RD_RAW_Sel)
				0:RD_RAW=DM_RD;
				1:RD_RAW=Pr_RD;
			endcase
		end
endmodule