module reqAndSimple #(parameter reqNumber=3) (reqs,fin);
input [reqNumber-1:0] reqs;
output wire fin;

wire [reqNumber:0] reqsConnect;
assign reqsConnect[0]=reqs[0];
assign fin=reqsConnect[reqNumber];

genvar i;
generate
for(i=0;i<reqNumber;i=i+1)
begin:reqTogetherSimple
    assign reqsConnect[i+1]=reqsConnect[i]&reqs[i];
end
endgenerate



endmodule