  module clk_wiz_0
    (
     // Clock in ports
     input  clk_in1,
     // Clock out ports
     output clk_out1,
     output clk_out2,
     output clk_out3,
     // Status and control signals
     output locked
     );

    clk_wiz_0_clk_wiz inst
      (
       // Clock in ports
       .clk_in1(clk_in1),
       // Clock out ports
       .clk_out1(clk_out1),
       .clk_out2(clk_out2),
       .clk_out3(clk_out3),
       // Status and control signals
       .locked(locked)
       );

endmodule