module ram_generic_1r1w(
    input wire clk,
    input wire rst,
    // Read port
    input wire [6:0] raddr,
    output wire [31:0] rd,
    input wire re,
    // Write port
    input wire [6:0] waddr,
    input wire [31:0] wr,
    input wire we
);

    parameter DBITS = 8;
    parameter ABITS = 12;
    localparam DEPTH = (1 << ABITS);

    reg [DBITS-1:0] mem [0:DEPTH-1];
    reg [DBITS-1:0] rd_reg;

    always @(posedge clk) begin
        if (!rst) begin
            if (we) begin
                mem[waddr] <= wr;
            end
            
            if (re) begin
                rd_reg <= mem[raddr];
            end
        end
    end

    assign rd = rd_reg;

endmodule