module top
# (
    parameter width = 8
)
(
    input                    clock,
    input                    reset_n,

    input      [width - 1:0] up_data,
    input                    up_valid,
    output                   up_ready,

    output     [width - 1:0] down_data,
    output                   down_valid,
    input                    down_ready
);

    wire       [width - 1:0] i12_data;
    wire                     i12_valid;
    wire                     i12_ready;

    pipeline_stomach # (.width (width))
    pipeline_stomach_inst_1
    (
        .down_data  ( i12_data  ),
        .down_valid ( i12_valid ),
        .down_ready ( i12_ready ),

        .*
    );

    pipeline_stomach # (.width (width))
    pipeline_stomach_inst_2
    (
        .up_data    ( i12_data  ),
        .up_valid   ( i12_valid ),
        .up_ready   ( i12_ready ),

        .*
    );

endmodule