module mux_2level_basis_input2_mem2(in,
                                    mem,
                                    mem_inv,
                                    out);
//
input [0:1] in;
//
input [0:1] mem;
//
input [0:1] mem_inv;
//
output [0:0] out;

//
//


//
//



//
//
//
//

wire [0:0] out_inv;
	sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0(
	                                    .Q1(in[0]),
	                                    .Q2(in[1]),
	                                    .S0(mem[0]),
	                                    .S0B(mem_inv[0]),
	                                    .S1(mem[1]),
	                                    .S1B(mem_inv[1]),
	                                    .Z(out_inv[0])
	                                    );
	sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0(
	                                    .A(out_inv[0]),
	                                    .Y(out[0])
	                                    );
endmodule