module pulse_generator #(parameter WIDTH = 32) (
  input  wire             clk,          /* clock */
  input  wire             reset,        /* reset */
  input  wire [WIDTH-1:0] period,       /* period, in clk cycles */
  input  wire [WIDTH-1:0] pulse_width,  /* pulse width, in clk cycles */
  output reg              pulse         /* pulse */
);
  reg [WIDTH-1:0] count = 0;

  always @(posedge clk) begin
    if (reset | count <= 1)
      count <= period;
    else
      count <= count - 1;

    pulse <= (count > (period - pulse_width));
  end

endmodule //pulse_generator