module t_flip_flop_behavioral (
    input       clk,        // Clock
    input       t,          // Inputs
    output reg  q,          // Output
    output      qbar);      //

    parameter   HOLD   = 1'b0,
                TOGGLE = 1'b1;

    // INTERNAL WIRES
    assign qbar = ~q;

    always @(posedge clk) begin
        case({t})
            HOLD :    q <= q;
            TOGGLE :  q <= ~q;
        endcase
    end

endmodule