module aibcr3_dlycell_dcc_rep ( output co_p, output out_p, input bk, input ci_p, input in_p );

aibcr3_dlycell_dcc I7 (.co_p(co_p), .out_p(out_p), .bk(bk), .ci_p(ci_p),.in_p(in_p));

//`ifdef TIMESCALE_EN
//                timeunit 1ps;
//                timeprecision 1ps;
//`endif
//
//output  co_p, out_p;
//
//input  bk, ci_p, in_p;
//
//wire bkbl;
//
//parameter   BUF_DELAY = 20;
//
//assign net0150 = ~in_p;
//assign bkb     = ! bk;
//assign net0173 = ! (net0150 & bk);
//assign net0174 = ! (net0150 & bkb);
//assign bkl     = ! (net0173 & bkbl);
//assign bkbl    = ! (net0174 & bkl);
//
//assign #BUF_DELAY co_p = bkl? in_p : 1'b0;
//assign #BUF_DELAY out_p = bkl? ci_p : in_p;

endmodule