module e203_dtcm_ram(

  input                              sd,
  input                              ds,
  input                              ls,

  input                              cs,  
  input                              we,  
  input  [`E203_DTCM_RAM_AW-1:0] addr, 
  input  [`E203_DTCM_RAM_MW-1:0] wem,
  input  [`E203_DTCM_RAM_DW-1:0] din,          
  output [`E203_DTCM_RAM_DW-1:0] dout,
  input                              rst_n,
  input                              clk

);

wire wren =  we & cs;

wire [3:0]wea;
assign wea = (wren) ? wem : 4'b0;

wire rden;
assign rden = (~we) & cs;

// bram_32 u_e203_dtcm_gnrl_ram(
//
//	.doa    (dout),
//	.dia    (din ),
//	.addra  (addr),
//	.wea    (wea ),
//	.cea    (cs  ),
//	.clka   (clk ),
//	.rsta   (1'b0)
//    );
 
 riscv_ram32 u_e203_dtcm_gnrl_ram
 (
	.address(addr),
	.byteena(wea),
	.clock  (clk),
	.data   (din),
	.rden   (rden),
	.wren   (wren),
	.q      (dout)
	);
	
//  sirv_gnrl_ram #(
//      `ifndef E203_HAS_ECC//{
//    .FORCE_X2ZERO(0),
//      `endif//}
//    .DP(`E203_DTCM_RAM_DP),
//    .DW(`E203_DTCM_RAM_DW),
//    .MW(`E203_DTCM_RAM_MW),
//    .AW(`E203_DTCM_RAM_AW) 
//  ) u_e203_dtcm_gnrl_ram(
//  .sd  (sd  ),
//  .ds  (ds  ),
//  .ls  (ls  ),
//
//  .rst_n (rst_n ),
//  .clk (clk ),
//  .cs  (cs  ),
//  .we  (we  ),
//  .addr(addr),
//  .din (din ),
//  .wem (wem ),
//  .dout(dout)
//  );
                                                      
endmodule