module or1200_gmultp2_32x32_cm4 (
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		 X, Y, CLK, RST, P );


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg [ 64 - 1 : 0 ] p0_cml_3;
reg [ 64 - 1 : 0 ] p0_cml_2;
reg [ 64 - 1 : 0 ] p0_cml_1;
reg [ 64 - 1 : 0 ] p1_cml_3;
reg [ 64 - 1 : 0 ] p1_cml_2;
reg [ 64 - 1 : 0 ] p1_cml_1;



input   [`OR1200_W-1:0]  X;
input   [`OR1200_W-1:0]  Y;
input           CLK;
input           RST;
output  [`OR1200_WW-1:0]  P;

reg     [`OR1200_WW-1:0]  p0;
reg     [`OR1200_WW-1:0]  p1;
integer 		  xi;
integer 		  yi;

//
// Conversion unsigned to signed
//
always @(X)
	xi <= X;

//
// Conversion unsigned to signed
//
always @(Y)
	yi <= Y;

//
// First multiply stage
//


// SynEDA CoreMultiplier
// assignment(s): p0
// replace(s): p0
always @(posedge CLK) 
                p0 <= #1 xi * yi; 


//
// Second multiply stage
//

// SynEDA CoreMultiplier
// assignment(s): p1
// replace(s): p0, p1
always @(posedge CLK)
                p1 <= #1 p0_cml_3; 


// SynEDA CoreMultiplier
// assignment(s): P
// replace(s): p1
assign P = p1_cml_3;


always @ (posedge clk_i_cml_1) begin
p0_cml_1 <= p0;
p1_cml_1 <= p1;
end
always @ (posedge clk_i_cml_2) begin
p0_cml_2 <= p0_cml_1;
p1_cml_2 <= p1_cml_1;
end
always @ (posedge clk_i_cml_3) begin
p0_cml_3 <= p0_cml_2;
p1_cml_3 <= p1_cml_2;
end
endmodule