module dp_register_decode(
   input         clk,

   input         de,
   input  [7:0]  data,
   input  [7:0]  addr,
   input         invalidate,

   output reg        valid,
 
   output reg [7:0]  revision,
   output reg        link_rate_2_70,
   output reg        link_rate_1_62,
   output reg        extended_framing,
   output reg [3:0]  link_count,
   output reg [7:0]  max_downspread,
   output reg [7:0]  coding_supported,
   output reg [15:0] port0_capabilities,
   output reg [15:0] port1_capabilities,
   output reg [7:0]  norp
);

initial begin
    valid              = 1'b0;
    revision           = 8'b0;
    link_rate_2_70     = 1'b0;
    link_rate_1_62     = 1'b0;
    extended_framing   = 1'b0;
    link_count         = 3'b0;
    max_downspread     = 8'b0;
    coding_supported   = 8'b0;
    port0_capabilities = 16'b0;
    port1_capabilities = 16'b0;
    norp               = 8'b0;
end

always @(posedge clk) begin
    if(de == 1'b1) begin
        valid    <= 1'b0;
        case(addr)
            8'h00: begin
                       revision <= data;
                   end
            8'h01: begin
                       case(data) 
                              8'h0A:   begin
                                           link_rate_2_70 <= 1'b1;
                                           link_rate_1_62 <= 1'b1;
                                       end
                              8'h06:   begin
                                           link_rate_2_70 <= 1'b0;
                                           link_rate_1_62 <= 1'b1;
                                       end
                              default: begin
                                           link_rate_2_70 <= 1'b0;
                                           link_rate_1_62 <= 1'b0;
                                       end
                       endcase
                   end
            8'h02: begin
                       extended_framing <= data[7];
                       link_count       <= data[3:0];         
                   end
            8'h03: begin
                       max_downspread   <= data;
                   end
            8'h04: begin
                       norp             <= data;
                   end
            8'h06: begin
                       coding_supported <= data;    
                   end
            8'h08: begin
                       port0_capabilities[7:0] <= data;
                   end
            8'h09: begin
                       port0_capabilities[15:8]<= data;
                   end
            8'h0A: begin
                       port1_capabilities[7:0] <= data;
                   end
            8'h0B: begin
                       port1_capabilities[15:8]<= data;
                       valid <= 1'b1;
                   end
        endcase

        //----------------------------------------------
        // Allow for an external event to invalidate the 
        // outputs (e.g. hot plug)
        //----------------------------------------------
        if(invalidate == 1'b1) begin
           valid <= 1'b0;
        end
    end
end
endmodule