module spi_341432284947153491 #(
	parameter INBITS = 4,
	parameter OUTBITS = 4
) (
	input                reset, // synchronous internal reset
	input                clk, // system clock
	input                sclk, // negative polarity
	input                ce, // active low
	input                sin,
	output               sout,
	input  [INBITS-1:0]  inputs,
	output [OUTBITS-1:0] outputs
);

	// Note: We shift IN the IO OUTPUTS. We shift OUT the IO INPUTS.
	reg [OUTBITS-1:0] inlatch; // serial input latch (latch on CE rising edge)
	reg [OUTBITS-1:0] inbuf; // serial input buffer (latch on CE rising edge)
	reg [INBITS-1:0] outlatch; // serial output latch (latch on CE falling edge)
	
	assign sout = outlatch[0];
	assign outputs = inlatch;

	wire ce_posedge, ce_negedge;
	posedge_341432284947153491 pe_ce(.clk(clk), .in(ce), .pedge(ce_posedge));
	negedge_341432284947153491 ne_ce(.clk(clk), .in(ce), .nedge(ce_negedge));

	wire sclk_posedge, sclk_negedge;
	posedge_341432284947153491 pe_sclk(.clk(clk), .in(sclk), .pedge(sclk_posedge));
	negedge_341432284947153491 ne_sclk(.clk(clk), .in(sclk), .nedge(sclk_negedge));

	always @(posedge clk) begin
		if (reset) begin
			inbuf <= 0;
			inlatch <= 0;
			outlatch <= 0;
		end else if (ce_posedge) begin
			inlatch <= inbuf;
		end else if (ce_negedge) begin
			outlatch <= inputs;
		//end else if (ce) begin
			//inbuf <= 0;
			//outlatch <= 0;
		end else begin
			if (sclk_posedge) begin
				outlatch <= { 1'b0, outlatch[INBITS-1:1] };
			end else if (sclk_negedge) begin
				inbuf <= { inbuf[OUTBITS-2:0], sin };
			end
		end
	end

endmodule