module alu(
	input [1:0] A,
	input [1:0] B,
	input [3:0] opcode,
	output [7:0] ALU_Out
);

    reg [7:0] ALU_Result;
    assign ALU_Out = ALU_Result; // ALU out
    always @(*)
    begin
        case(opcode)
        4'b0000: // Addition
           ALU_Result = A + B ; 
        4'b0001: // Subtraction
           ALU_Result = A - B ;
        4'b0010: // Multiplication
           ALU_Result = A * B;
        4'b0011: // Division
           ALU_Result = A/B;
        4'b0100: // Logical shift left one time
           ALU_Result = A<<1;
         4'b0101: // Logical shift right one time
           ALU_Result = A>>1;
         4'b0110: // Logical shift left B times
           ALU_Result = A<<B;
         4'b0111: // Logical shift right B times
           ALU_Result = A>>B;
          4'b1000: //  Logical and 
           ALU_Result = A & B;
          4'b1001: //  Logical or
           ALU_Result = A | B;
          4'b1010: //  Logical xor 
           ALU_Result = A ^ B;
          4'b1011: //  Logical nor
           ALU_Result = ~(A | B);
          4'b1100: // Logical nand 
           ALU_Result = ~(A & B);
          4'b1101: // Logical xnor
           ALU_Result = ~(A ^ B);
          4'b1110: // Greater comparison
           ALU_Result = (A>B)?4'd1:4'd0 ;
          4'b1111: // Equal comparison   
            ALU_Result = (A==B)?4'd1:4'd0 ;
          default: ALU_Result = A + B ; 
        endcase
    end
 endmodule