module cla_16bit(
    input [16:1] A,
    input [16:1] B,
    input Cin,
    output [16:1] S,
    output Cout
);

    wire [16:0] C; // Internal carry bits, C[0] is Cin
    wire [16:1] G; // Generate terms
    wire [16:1] P; // Propagate terms

    assign C[0] = Cin;

    // Generate and propagate terms
    genvar i;
    generate
        for (i = 1; i <= 16; i = i + 1) begin : gen_prop
            assign G[i] = A[i] & B[i];   // Generate
            assign P[i] = A[i] | B[i];   // Propagate
            assign C[i] = G[i] | (P[i] & C[i-1]); // Carry
        end
    endgenerate

    // Calculate sum and carry out
    for (i = 1; i <= 16; i = i + 1) begin : sum_loop
        assign S[i] = A[i] ^ B[i] ^ C[i-1]; // Sum bit
    end

    assign Cout = C[16]; // Final carry-out

endmodule