module framebuf_bram(
    input wire clk,
    input wire wr_en,
    input wire [8:0] rd_addr,
    input wire [8:0] wr_addr,
    input wire [7:0] data_in,
    output reg [7:0] data_out
);
   reg [7:0] memory [0:511];
   integer i;

   initial begin
      for(i = 0; i <= 511; i=i+1) begin
         memory[i] = 8'b0;
      end
   end

   always @(posedge clk) begin
      if (wr_en) begin
         memory[wr_addr] <= data_in;
      end
      data_out <= memory[rd_addr];
   end
endmodule