module rf_dist_cm2(
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input [5 : 0] a;
input [31 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

reg	[31:0]		mem [63:0];
integer i;

initial begin
	for (i = 0; i < 64; i = i + 1) begin
		mem[i] <= 32'h0;
	end
end

//
// Write port
//
always @(posedge clk)
	if (we) mem[a] <= #1 d;

//
// Read port A
//

assign spo = mem[a];
assign dpo = mem[dpra];

endmodule