module LogicModule
  (
   input wire [5:0]  alufn,
   input wire [31:0] a,
   input wire [31:0] b,

   output reg [31:0] res
   );

   integer 	     i = 0;

   always @(alufn[3:0], a, b) begin
       for (i = 0; i < 32; i = i + 1) begin
           res[i] = alufn[{{a[i]}, {b[i]}}];
       end 
   end

endmodule