module aibnd_str_ioload ( inp);

input  inp;

// Buses in the design

wire    net07;

assign vcc_aibnd = 1'b1;
assign vss_aibnd = 1'b0;


//specify 
//    specparam CDS_LIBNAME  = "aibnd_lib";
//    specparam CDS_CELLNAME = "aibnd_str_ioload";
//    specparam CDS_VIEWNAME = "schematic";
//endspecify

assign net07 = ~inp ;

endmodule