module NV_NVDLA_CDMA_CVT_cell (
   cfg_mul_in_rsc_z //|< i
  ,cfg_in_precision //|< i
  ,cfg_out_precision //|< i
  ,cfg_truncate //|< i
  ,chn_alu_in_rsc_vz //|< i
  ,chn_alu_in_rsc_z //|< i
  ,chn_data_in_rsc_vz //|< i
  ,chn_data_in_rsc_z //|< i
  ,chn_data_out_rsc_vz //|< i
  ,nvdla_core_clk //|< i
  ,nvdla_core_rstn //|< i
  ,chn_alu_in_rsc_lz //|> o
  ,chn_data_in_rsc_lz //|> o
  ,chn_data_out_rsc_lz //|> o
  ,chn_data_out_rsc_z //|> o
  );
input [15:0] cfg_mul_in_rsc_z;
input [1:0] cfg_in_precision;
input [1:0] cfg_out_precision;
input [5:0] cfg_truncate;
input chn_alu_in_rsc_vz;
input [15:0] chn_alu_in_rsc_z;
input chn_data_in_rsc_vz;
input [16:0] chn_data_in_rsc_z;
input chn_data_out_rsc_vz;
input nvdla_core_clk;
input nvdla_core_rstn;
output chn_alu_in_rsc_lz;
output chn_data_in_rsc_lz;
output chn_data_out_rsc_lz;
output [15:0] chn_data_out_rsc_z;
wire [15:0] cfg_mul_in;
wire [17:0] chn_alu_ext;
wire [15:0] chn_alu_in;
wire chn_alu_prdy;
wire chn_alu_pvld;
wire [17:0] chn_data_ext;
wire [16:0] chn_data_in;
wire [15:0] chn_data_out;
wire [15:0] chn_dout;
wire chn_in_prdy;
wire chn_in_pvld;
wire chn_out_prdy;
wire chn_out_pvld;
wire chn_sync_prdy;
wire chn_sync_pvld;
wire [15:0] dout_int16_sat;
wire [7:0] dout_int8_sat;
wire mon_sub_c;
wire [33:0] mul_data_out;
wire [33:0] mul_dout;
wire mul_out_prdy;
wire mul_out_pvld;
wire [17:0] sub_data_out;
wire [17:0] sub_dout;
wire sub_out_prdy;
wire sub_out_pvld;
wire [16:0] tru_data_out;
wire [16:0] tru_dout;
wire tru_out_prdy;
wire tru_out_pvld;
// synoff nets
// monitor nets
// debug nets
// tie high nets
// tie low nets
// no connect nets
// not all bits used nets
// todo nets
assign chn_in_pvld = chn_data_in_rsc_vz;
assign chn_alu_pvld = chn_alu_in_rsc_vz;
assign chn_data_in[16:0] = chn_data_in_rsc_z[16:0];
assign chn_alu_in[15:0] = chn_alu_in_rsc_z[15:0];
assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0];
assign chn_out_prdy = chn_data_out_rsc_vz;
assign chn_data_in_rsc_lz = chn_in_prdy;
assign chn_alu_in_rsc_lz = chn_alu_prdy;
assign chn_data_out_rsc_lz = chn_out_pvld;
assign chn_data_out_rsc_z[15:0] = chn_data_out[15:0];
assign chn_sync_pvld = chn_alu_pvld & chn_in_pvld;
assign chn_alu_prdy = chn_sync_prdy & chn_in_pvld;
assign chn_in_prdy = chn_sync_prdy & chn_alu_pvld;
assign chn_data_ext[17:0] = {{1{chn_data_in[16]}}, chn_data_in[16:0]};
assign chn_alu_ext[17:0] = {{2{chn_alu_in[15]}}, chn_alu_in[15:0]};
//sub
assign {mon_sub_c,sub_dout[17:0]} = $signed(chn_data_ext[17:0]) -$signed(chn_alu_ext[17:0]);
NV_NVDLA_CDMA_CVT_CELL_pipe_p1 pipe_p1 (
   .nvdla_core_clk (nvdla_core_clk) //|< i
  ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
  ,.chn_sync_pvld (chn_sync_pvld) //|< w
  ,.sub_dout (sub_dout[17:0]) //|< w
  ,.sub_out_prdy (sub_out_prdy) //|< w
  ,.chn_sync_prdy (chn_sync_prdy) //|> w
  ,.sub_data_out (sub_data_out[17:0]) //|> w
  ,.sub_out_pvld (sub_out_pvld) //|> w
  );
//mul
assign mul_dout[33:0] = $signed(sub_data_out[17:0]) * $signed(cfg_mul_in[15:0]);
NV_NVDLA_CDMA_CVT_CELL_pipe_p2 pipe_p2 (
   .nvdla_core_clk (nvdla_core_clk) //|< i
  ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
  ,.mul_dout (mul_dout[33:0]) //|< w
  ,.mul_out_prdy (mul_out_prdy) //|< w
  ,.sub_out_pvld (sub_out_pvld) //|< w
  ,.mul_data_out (mul_data_out[33:0]) //|> w
  ,.mul_out_pvld (mul_out_pvld) //|> w
  ,.sub_out_prdy (sub_out_prdy) //|> w
  );
//truncate
NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(34 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(6 )) u_shiftright_su (
   .data_in (mul_data_out[33:0]) //|< w
  ,.shift_num (cfg_truncate[5:0]) //|< i
  ,.data_out (tru_dout[16:0]) //|> w
  );
//signed
//unsigned
assign tru_data_out[16:0] = tru_dout[16:0];
assign tru_out_pvld = mul_out_pvld;
assign mul_out_prdy = tru_out_prdy;
NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(16 )) u_saturate_int16 (
   .data_in (tru_data_out[16:0]) //|< w
  ,.data_out (dout_int16_sat[15:0]) //|> w
  );
NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(8 )) u_saturate_int8 (
   .data_in (tru_data_out[16:0]) //|< w
  ,.data_out (dout_int8_sat[7:0]) //|> w
  );
assign chn_dout = (cfg_out_precision[1:0] == 1 ) ? dout_int16_sat[15:0] : {{(16 - 8 ){dout_int8_sat[8 -1]}},dout_int8_sat[7:0]};
NV_NVDLA_CDMA_CVT_CELL_pipe_p3 pipe_p3 (
   .nvdla_core_clk (nvdla_core_clk) //|< i
  ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
  ,.chn_dout (chn_dout[15:0]) //|< w
  ,.chn_out_prdy (chn_out_prdy) //|< w
  ,.tru_out_pvld (tru_out_pvld) //|< w
  ,.chn_data_out (chn_data_out[15:0]) //|> w
  ,.chn_out_pvld (chn_out_pvld) //|> w
  ,.tru_out_prdy (tru_out_prdy) //|> w
  );
endmodule // NV_NVDLA_CDMA_CVT_cell