module reg4
(
input [3:0] d_i,
input rst_n,
input clk,
output [3:0] q_o
);

reg [3:0] q;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        q <= 4'b0000;
    end
    else begin
        q <= d_i;
    end
end

assign q_o = q;

endmodule