module dual_port_ram #(parameter ADDR_WIDTH = 32, DATA_WIDTH = 32) (
          input wire [ADDR_WIDTH - 1 : 0]       waddr, 
          input wire [ADDR_WIDTH - 1 : 0]       raddr,
          
          input wire [DATA_WIDTH - 1 : 0]       din,
          input wire                            write_en, 
          input wire                            clk, 
          output wire [DATA_WIDTH - 1 : 0]      dout
);


    dual_port_ram_lattice #(.ADDR_WIDTH (ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH)) dual_port_ram_lattice_i (
            .waddr (waddr),
            .raddr (raddr),
            
            .din (din),
            .write_en (write_en),
            
            .wclk (clk),
            .rclk (clk),
            .dout (dout) );
            
endmodule