module tb_iceZ0mb1e;

    initial begin
        $dumpfile(`__def_vcd_file);
        $dumpvars(0, tb_iceZ0mb1e);

        //# 15E3 $finish;
        # 250E3 $finish;
        //# 1E6 $finish;
    end

    reg clk = 0;
    always #1 clk = !clk;

    inout [7:0] P1_out;
    inout [7:0] P2_out;
	wire i2c_scl;
	wire i2c_sda_out;
	wire i2c_sda_in;
	wire i2c_sda_oen;
    output sclk, cs, mosi;
    input miso;
    wire rx = 0;
    wire tx;

    iceZ0mb1e t1 (
        .clk        (clk),
        .uart_txd   (tx),
        .uart_rxd   (rx),
		.i2c_scl	(i2c_scl),
		.i2c_sda_in	(i2c_sda_in),
		.i2c_sda_out	(i2c_sda_out),
		.i2c_sda_oen	(i2c_sda_oen),
    	.spi_sclk	(spi_sclk),
		.spi_mosi	(spi_mosi),
		.spi_miso	(spi_miso),
    	.spi_cs		(spi_cs),
		.P1_out		(P1_out),
		.P1_in		(8'h55),
		.P1_oen		(),
		.P2_out		(P2_out),
		.P2_in		(8'hAA),
		.P2_oen		(),
		.debug		()
    );

endmodule