module hsync(
    input clk,
    output reg line_clk = 0,
    output reg [15:0] h_val = 0
    );
    
    always @(posedge clk)
    begin
        if (h_val == 800) begin h_val = 0; line_clk = 1; end
        else begin h_val = h_val + 1; line_clk = 0; end
    end
endmodule