module c3lib_ckg_lvt_8x(

  tst_en,
  clk_en,
  clk,
  gated_clk

);

    input wire tst_en;
    input wire clk_en;
    input wire clk;
    output wire gated_clk;

`ifdef BEHAVIORAL
    var logic latch_d;
    var logic latch_q;

    // Formulate control signal
    assign latch_d = clk_en | tst_en;

    // Latch control signal
    always_latch if (~clk) latch_q <= latch_d;

    // Actual clk gating gate
    assign gated_clk = clk & latch_q;
`else
    b15cilb01ah1n08x5 icg_cell (.clkout(gated_clk), .en(clk_en), .te(tst_en), .clk(clk));
`endif


endmodule