module stud_first_order_modulator
#(
    parameter BITWIDTH = 16             // audio data input width
)
(
    input n_rst_i,                      // active low synchronous reset
    input clk_i,                        // clock input

    input [BITWIDTH - 1 : 0] data_i,    // audio data input (unsigned)

    output reg mod_o                    // 1 bit modulator output
);

// feedback line
reg [BITWIDTH - 1 : 0] fb;
reg [BITWIDTH - 1 : 0] fb_next;

// accumulator
reg [BITWIDTH : 0] acc;
reg [BITWIDTH : 0] acc_next;

// modulator output
reg mod_next;

// combinatorics
always @* begin
    // least significant bits of the accumulator get delayed by 1 clock cycle
    // and then fed back into the accumulator
    fb_next = acc[BITWIDTH - 1 : 0];
    acc_next = {1'b0, data_i} + {1'b0, fb};

    // most significant bit of the accumulator becomes the output
    mod_next = acc[BITWIDTH];
end

// registers
always @(posedge clk_i) begin
    if (!n_rst_i) begin
        // synchronously reset register values
        fb <= {BITWIDTH {1'b0}};
        acc <= {BITWIDTH + 1 {1'b0}};
        mod_o <= 1'b0;
    end else begin
        fb <= fb_next;
        acc <= acc_next;

        mod_o <= mod_next;
    end
end

endmodule