module Register_R (q, d, rst, clk);
  parameter N = 1;
  parameter INIT = {N{1'b0}};
  input            clk;
  input            rst;
  output reg [N-1:0] q;
  input      [N-1:0] d;
  initial q = INIT;
  always @(posedge clk)
    if (rst) q <= INIT;
    else q <= d;
endmodule // REGISTER_R