module MUX_RF_A3(RF_A3_Sel,Ins,A3);
//interface
	input [31:0] RF_A3_Sel;

	input [31:0] Ins;
	
	output reg [4:0] A3;
	
//select logic
	always @(*)
		begin
			A3=Ins[20:16];
			case(RF_A3_Sel)
				0:A3=Ins[20:16];	//RT
				1:A3=Ins[15:11];	//RD
				2:A3=32'd31;		//0x31
			endcase
		end
	
endmodule