module EvenOdd (V8, RES, nHPLA_5, RESCL, EvenOddOut);

	input V8;
	input RES;
	input nHPLA_5;
	input RESCL;
	output EvenOddOut;

	wire q1;
	wire q2;
	wire nq2;

	sdff FF_1 (.d(nq2), .phi_keep(V8), .q(q1));
	sdffr FF_2 (.d(q1), .res(), .phi_keep(~V8), .q(q2), .nq(nq2));

	nor (EvenOddOut, q2, nHPLA_5, ~RESCL);

endmodule // EvenOdd