module top(
	input clk,
	output D1,
	output D2,
	output D3,
	output D4,
	output D5,
	output D6,
	output D7,
	output D8,
	output uart_txd,
	input uart_rxd,
	output i2c_scl,
	inout  i2c_sda,
    output spi_sclk,
	output spi_mosi,
	output  spi_miso,
    output spi_cs
);

	wire[7:0] port_a;
	wire[7:0] port_b;

	assign D1 = port_a[0];
	assign D2 = port_a[1];
	assign D3 = port_a[2];
	assign D4 = port_a[3];
	assign D5 = port_a[4];
	assign D6 = port_a[5];
	assign D7 = port_a[6];
	assign D8 = port_a[7];

	iceZ0mb1e core (
		.clk		(clk),
		.uart_txd	(uart_txd),
		.uart_rxd	(uart_rxd),
		.i2c_scl	(i2c_scl),
		.i2c_sda	(i2c_sda),
    	.spi_sclk	(spi_sclk),
		.spi_mosi	(spi_mosi),
		.spi_miso	(spi_miso),
    	.spi_cs		(spi_cs),
		.port_a		(port_a),
		.port_b		(port_b),
		.debug		()
	);

endmodule