module an_io_double_edge_ff (clk_in, reset_n, test_enable_n, data_in, data_out `ifndef INTCNOPWR ,vcc ,vss `endif);
input  [1:0] clk_in;            // clk_in[0] is p, clk_in[1] is n
input        reset_n;           // Reset active low
input        test_enable_n;     // Reset active low
input  [1:0] data_in;
output [1:0] data_out;          // Complimentary output
reg notifier;

`ifndef INTCNOPWR
input vcc, vss;
`endif
wire [1:0] clk_buf_n;

assign clk_buf_n[1] = ~(test_enable_n & clk_in[1]);
assign clk_buf_n[0] = ~(test_enable_n & clk_in[0]);
wire  delayed_clk_in_1;
wire  delayed_clk_in_0;
wire  delayed_data_in_1;
wire  delayed_data_in_0;

reg  [1:0] lat;
always @(reset_n or clk_buf_n[0] or data_in[0])
  if (~reset_n)          lat[0] <= 1'b0;
  else if (clk_buf_n[0]) lat[0] <= data_in[0];

always @(reset_n or clk_buf_n[1] or data_in[1])
  if (~reset_n)          lat[1] <= 1'b0;
  else if (clk_buf_n[1]) lat[1] <= data_in[1];

assign data_out[0] = (clk_in[0] &  lat[0]) | (clk_in[1] &  lat[1]) | ( lat[0] &  lat[1]);
assign data_out[1] = (clk_in[0] & ~lat[0]) | (clk_in[1] & ~lat[1]) | (~lat[0] & ~lat[1]);
	specify
                if (~test_enable_n) 
	       			(data_in[0] => data_out[1]) = 0;
                if (~test_enable_n) 
                		(data_in[1] => data_out[1]) = 0;
		if (~test_enable_n)
                		(clk_in[0] => data_out[1]) = 0;
		if (test_enable_n)
                		(posedge clk_in[0] => (data_out[1]:data_in[0])) = (0,0);
		if (test_enable_n)
                		(posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(posedge clk_in[1] => (data_out[1]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(data_in[0] => data_out[0]) = 0;
		if (~test_enable_n)
                		(data_in[1] => data_out[0]) = 0;
		if (~test_enable_n)
                		(clk_in[0] => data_out[0]) = 0;
		if (test_enable_n)
		                (posedge clk_in[0] => (data_out[0]:data_in[0])) = (0,0);
		if (test_enable_n)
                		(posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0);
		if (~test_enable_n)
                		(posedge clk_in[1] => (data_out[0]:data_in[1])) = (0,0);
		$setuphold (posedge clk_in[1], posedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1);
		$setuphold (posedge clk_in[1], negedge data_in[1], 0, 0, notifier,,, delayed_clk_in_1, delayed_data_in_1);
		$setuphold (posedge clk_in[0], posedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0);
		$setuphold (posedge clk_in[0], negedge data_in[0], 0, 0, notifier,,, delayed_clk_in_0, delayed_data_in_0);
		$width (posedge clk_in[1], 0, 0, notifier);
		$width (posedge clk_in[0], 0, 0, notifier);
	endspecify
endmodule