module nt_timestamp (
  // clock and reset
  input wire        clk,
  input wire        rstn,

  // number of clock cycles between two counter increments
  input wire [7:0]  cycles_per_tick_i,

  // timestamp counter output
  output reg [23:0] timestamp_o
);

  reg [7:0] tick_cntr;

  // process increments output timestamp_o counter every cycles_per_tick_i
  // cycles. when maximum value is reached, counter is reset to zero
  always @(posedge clk) begin
    if (~rstn) begin
      timestamp_o <= 24'b0;
    end else begin
      if (tick_cntr == (cycles_per_tick_i - 1)) begin
        if (timestamp_o == 24'hFFFFFF) begin
          timestamp_o <= 24'b0;
        end else begin
          timestamp_o <= timestamp_o + 24'b1;
        end
      end else begin
        timestamp_o <= timestamp_o;
      end
    end
  end

  // process increments tick_cntr every clock cycle. When cycles_per_tick_i is
  // reached, counter is reset
  always @(posedge clk) begin
    if (~rstn) begin
      tick_cntr <= 8'b0;
    end else begin
      if (tick_cntr >= (cycles_per_tick_i - 1)) begin
        tick_cntr <= 8'b0;
      end else begin
        tick_cntr <= tick_cntr + 8'b1;
      end
    end
  end

endmodule