module dtlb_mr_sub_cm2(
		clk_i_cml_1,
		cmls,
		
	clka,
	ena,
	wea,
	addra,
	dina,
	clkb,
	addrb,
	doutb);


input clk_i_cml_1;
input cmls;




input clka;
input ena;
input [0 : 0] wea;
input [5 : 0] addra;
input [13 : 0] dina;
input clkb;
input [5 : 0] addrb;
output [13 : 0] doutb;

wire ena_wire;
wire [0 : 0] wea_wire;
wire [5 : 0] addra_wire;
wire [13 : 0] dina_wire;
wire [5 : 0] addrb_wire;

assign ena_wire = ena;
assign wea_wire = wea;
assign addra_wire = addra;
assign dina_wire = dina;
assign addrb_wire = addrb;

dtlb_mr_blk_cm2 dtlb_mr_blki(
	.clka(clka),
	.ena(ena_wire),
	.wea(wea_wire),
	.addra({cmls, addra_wire}),
	.dina(dina_wire),
	.clkb(clkb),
	.addrb({cmls, addrb_wire}),
	.doutb(doutb));

endmodule