module ram_1r_1w (/*AUTOARG*/
  // Outputs
  rd_data, 
  // Inputs
  clk, wr_addr, wr_en, wr_data, rd_addr
  );

  parameter  width = 8;
  parameter  depth = 128;
  parameter  addr_sz = 7;

  input               clk;
  input [addr_sz-1:0] wr_addr;
  input               wr_en;
  input [width-1:0]   wr_data;

  input [addr_sz-1:0] rd_addr;
  output [width-1:0]  rd_data;

  reg [width-1:0]     mem [0:depth-1];

  always @(posedge clk)
    begin
      if (wr_en)
        mem[wr_addr] <= #1 wr_data;
    end

  assign rd_data = mem[rd_addr];

endmodule // ram_1r_1w