module c_BIN_NAND_DLATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0,
     output [0:0] out_1
);

wire net_0 = in_0;
wire net_1 = net_0;
wire net_2 = in_1;
wire net_3 = net_2;

wire net_4;
wire net_5;
wire net_6;
wire net_7;
wire net_8;

assign out_0 = net_7;
assign out_1 = net_8;

f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_2),
.out_0(net_4)
);

f_22Z LogicGate_1 (
.in_1(net_3),
.in_0(net_6),
.out_0(net_5)
);

f_2 LogicGate_2 (
.in_0(net_1),
.out_0(net_6)
);

c_BIN_NAND_SR_LATCH SavedGate_0 (
.in_0(net_4),
.in_1(net_5),
.out_0(net_7),
.out_1(net_8)
);

endmodule