module adder_32bit(
  input [31:0] A,
  input [31:0] B,
  output [31:0] S,
  output C32
);

  wire [16:0] C;
  wire [16:0] S_intermediate;
  
  cla_16bit cla0(.A(A[15:0]), .B(B[15:0]), .C_in(1'b0), .S(S_intermediate[15:0]), .C_out(C[0]));
  cla_16bit cla1(.A(A[31:16]), .B(B[31:16]), .C_in(C[0]), .S(S_intermediate[31:16]), .C_out(C[1]));
  
  assign S = {S_intermediate[31], S_intermediate[31:16]};
  assign C32 = C[1];
  
endmodule