module \$__CC_BRAM_20K_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 14;
	parameter CFG_DBITS = 40;
	parameter CFG_ENABLE_A = 1;
	parameter CFG_ENABLE_B = 1;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;

	// 512 x 40 bit
	parameter [20479:0] INIT = 20480'b0;

	input CLK2;
	input CLK3;

	// write side of the memory
	input [15:0] A1ADDR;
	input [39:0] A1DATA;
	input [39:0] A1EN;

	// read side of the memory
	input [15:0] B1ADDR;
	output [39:0] B1DATA;
	input [0:0] B1EN;

	// unconnected signals
	wire ECC_1B_ERR, ECC_2B_ERR;

	// internal signals
	wire [15:0] ADDRA = {A1ADDR, 7'b0};
	wire [15:0] ADDRB = {B1ADDR, 7'b0};

	localparam INIT_CHUNK_SIZE = 320;

	function [319:0] permute_init;
		input [INIT_CHUNK_SIZE-1:0] chunk;
		integer i;
		begin
			permute_init = chunk;
		end
	endfunction

	CC_BRAM_20K #(
		`include "brams_init_20.vh"
		.LOC("UNPLACED"),
		.A_RD_WIDTH(0), .B_RD_WIDTH(CFG_DBITS),
		.A_WR_WIDTH(CFG_DBITS), .B_WR_WIDTH(0),
		.RAM_MODE("SDP"),
		.A_WR_MODE("NO_CHANGE"), .B_WR_MODE("NO_CHANGE"),
		.A_CLK_INV(!CLKPOL2), .B_CLK_INV(!CLKPOL3),
		.A_EN_INV(1'b0), .B_EN_INV(1'b0),
		.A_WE_INV(1'b0), .B_WE_INV(1'b0),
		.A_DO_REG(1'b0), .B_DO_REG(1'b0),
		.ECC_EN(1'b0)
	) _TECHMAP_REPLACE_ (
		.A_DO(B1DATA[19:0]),
		.B_DO(B1DATA[39:20]),
		.ECC_1B_ERR(ECC_1B_ERR),
		.ECC_2B_ERR(ECC_2B_ERR),
		.A_CLK(CLK2),
		.B_CLK(CLK3),
		.A_EN(1'b1),
		.B_EN(B1EN),
		.A_WE(|A1EN),
		.B_WE(1'b0),
		.A_ADDR(ADDRA),
		.B_ADDR(ADDRB),
		.A_DI(A1DATA[19:0]),
		.B_DI(A1DATA[39:20]),
		.A_BM(A1EN[19:0]),
		.B_BM(A1EN[39:20])
	);

endmodule