module tb_gtx_tx_reset_controller;

    reg  clk = 1'b0;
    reg  powerup_channel;
    reg  plllock;
    reg  txresetdone;
    reg  ref_clk;
    
    wire tx_running;
    wire txreset;
    wire txuserrdy;
    wire txpmareset;
    wire txpcsreset;
    wire pllpd;
    wire pllreset;
    wire plllocken;
    wire resetsel;

    reg [15:0] count;
    
initial begin
    count           = 16'd0;

    powerup_channel = 1'b1;
    plllock         = 1'b0;
    txresetdone     = 1'b0;
    ref_clk         = 1'b0;
    
    forever begin
        #1
        if(count == 16'd500) begin
            powerup_channel = 1'b0;
        end
        
        if(count == 16'd700) begin
            plllock = 1'b1;
        end

        if(count == 16'd1000) begin
            txresetdone = 1'b1;
        end

        #4
        ref_clk = 1'b1;
        clk = 1'b1;
        
        #5
        clk     = 1'b0;
        ref_clk = 1'b0;
        count   = count + 1;
    end 
    
end     
 
    
gtx_tx_reset_controller i_gtx_tx_reset_controller(
  .clk (clk),

  .ref_clk         (ref_clk),
  .powerup_channel (powerup_channel),
  .plllock         (plllock),         
  .txresetdone     (txresetdone),

  .tx_running      (tx_running),
  .txreset         (txreset),
  .txuserrdy       (txuserrdy),
  .txpmareset      (txpmareset),
  .txpcsreset      (txpcsreset),
  .pllpd           (pllpd),
  .pllreset        (pllreset),
  .plllocken       (plllocken),
  .resetsel        (resetsel)
);
endmodule