module clockgen (input clk_i,
                 input  rst_n_i,
                 output clk1_o,
                 output clk2_o);
   reg [3:0]            counter_q;

   always @(posedge clk_i)
     begin
        if (~rst_n_i)
          counter_q <= 4'b0;
        else
          begin
             counter_q <= counter_q + 1'b1;
          end
     end
   assign clk1_o = counter_q[1];
   assign clk2_o = counter_q[3];
endmodule // clockgen