module counter (input clk_i,
                input  rst_n_i,
                input  load_i,
                input[3:0]  load_value_i,
                output[3:0] count_value_o,
                output count_valid_o);

   reg [3:0]                counter_q;
   reg                      count_valid_q;

   assign count_value_o = counter_q;
   assign count_valid_o = count_valid_q;
   
   always @(posedge clk_i)
     begin
        if (~rst_n_i)
          begin
             counter_q <= 4'b0;
             count_valid_q <= 1'b0;
          end
        else
          begin
             if (load_i)
               begin
                  counter_q <= load_value_i;
                  count_valid_q <= 1'b0;
               end
             else
               begin
                  counter_q <= counter_q + 1'b1;
                  count_valid_q <= 1'b1;
               end
          end
     end
endmodule // counter