module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );

	input	 [3:0]	PACKET;	// [3:2] Paketnumber , [1:0] Startaddress
	input	[63:0]	DP_Q;
	input	 [1:0]	SIZE;
	output	[31:0]	WRDATA;
	output	 [3:0]	ENBYTE;

	reg		 [3:0]	ENBYTE;
	reg		 [7:0]	dbyte0,dbyte1,dbyte2,dbyte3;
	wire			switch;
	
// Data packet 	[ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]
// Address , i.e. 001 : one DWORD
// gives  2 packets : 1. packet             [-B6-----B5-----B4-]
// 2. packet, Address + 4           							 [-B7-]
// Addresse , i.e. 010 : one QWORD
// gives  3 packets : 1. packet             [-B1-----B0-]
// 2. packet, Address + 4 					[-B5-----B4-----B3-----B2-]
// 3. packet, Address + 8 								  [-B7-----B6-]

//	SIZE PACKET ADR : Outputbus 
//		00	00	00		 x  x  x B4
//		00	00	01		 x  x B4  x
//		00	00	10		 x B4  x  x
//		00	00	11		B4  x  x  x

//		01	00	00		 x  x B5 B4
//		01	00	01		 x B5 B4  x
//		01	00	10		B5 B4  x  x
//		01	00	11		B4  x  x  x
//		01	10	11		 x  x  x B5

//		10	00	00		B7 B6 B5 B4
//		10	00	01		B6 B5 B4  x
//		10	10	01		 x  x  x B7
//		10	00	10		B5 B4  x  x
//		10	10	10		 x  x B7 B6
//		10	00	11		B4  x  x  x
//		10	10	11		 x B7 B6 B5

//		11	00	00		B3 B2 B1 B0
//		11	10	00		B7 B6 B5 B4
//		11	00	01		B2 B1 B0  x
//		11	01	01		B6 B5 B4 B3
//		11	10	01		 x  x  x B7
//		11	00	10		B1 B0  x  x
//		11	01	10		B5 B4 B3 B2
//		11	10	10		 x  x B7 B6
//		11	00	11		B0  x  x  x
//		11	01	11		B4 B3 B2 B1
//		11	10	11		 x B7 B6 B5

	assign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);
	
	always @(DP_Q or switch or PACKET)
		case (PACKET[1:0])
		  2'b00 : dbyte0 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
		  2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
		  2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
		  2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] :  DP_Q[15:8];
		endcase
		
	always @(DP_Q or switch or PACKET)
		case (PACKET[1:0])
		  2'b00 : dbyte1 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
		  2'b01 : dbyte1 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
		  2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
		  2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
		endcase
		
	always @(DP_Q or switch or PACKET)
		case (PACKET[1:0])
		  2'b00 : dbyte2 =    switch ? DP_Q[23:16] : DP_Q[55:48];
		  2'b01 : dbyte2 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
		  2'b10 : dbyte2 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
		  2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
		endcase

	always @(DP_Q or switch or PACKET)
		case (PACKET[1:0])
		  2'b00 : dbyte3 =    switch ? DP_Q[31:24] : DP_Q[63:56];
		  2'b01 : dbyte3 =    switch ? DP_Q[23:16] : DP_Q[55:48];
		  2'b10 : dbyte3 =    switch ?  DP_Q[15:8] : DP_Q[47:40];
		  2'b11 : dbyte3 =    switch ?   DP_Q[7:0] : DP_Q[39:32];
		endcase
		
	assign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};

	always @(SIZE or PACKET)
		casex ({SIZE,PACKET})
		  6'b00_xx_00 : ENBYTE = 4'b0001;	// BYTE
		  6'b00_xx_01 : ENBYTE = 4'b0010;
		  6'b00_xx_10 : ENBYTE = 4'b0100;
		  6'b00_xx_11 : ENBYTE = 4'b1000;
		 //
		  6'b01_xx_00 : ENBYTE = 4'b0011;	// WORD
		  6'b01_xx_01 : ENBYTE = 4'b0110;
		  6'b01_xx_10 : ENBYTE = 4'b1100;
		  6'b01_0x_11 : ENBYTE = 4'b1000;
		  6'b01_1x_11 : ENBYTE = 4'b0001;
		 //
		  6'b11_xx_00 : ENBYTE = 4'b1111;	// QWORD
		  6'b11_00_01 : ENBYTE = 4'b1110;
		  6'b11_01_01 : ENBYTE = 4'b1111;
		  6'b11_1x_01 : ENBYTE = 4'b0001;
		  6'b11_00_10 : ENBYTE = 4'b1100;
		  6'b11_01_10 : ENBYTE = 4'b1111;
		  6'b11_1x_10 : ENBYTE = 4'b0011;
		  6'b11_00_11 : ENBYTE = 4'b1000;
		  6'b11_01_11 : ENBYTE = 4'b1111;
		  6'b11_1x_11 : ENBYTE = 4'b0111;
		 //	
		  6'b10_xx_00 : ENBYTE = 4'b1111;	// DWORD
		  6'b10_0x_01 : ENBYTE = 4'b1110;
		  6'b10_1x_01 : ENBYTE = 4'b0001;
		  6'b10_0x_10 : ENBYTE = 4'b1100;
		  6'b10_1x_10 : ENBYTE = 4'b0011;
		  6'b10_0x_11 : ENBYTE = 4'b1000;
		  6'b10_1x_11 : ENBYTE = 4'b0111;
		endcase
		  
endmodule