module or1200_genpc_cm4(
		clk_i_cml_1,
		clk_i_cml_2,
		clk_i_cml_3,
		
	// Clock and reset
	clk, rst,

	// External i/f to IC
	icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
	icpu_rty_i, icpu_adr_i,

	// Internal i/f
	branch_op, except_type, except_prefix,
	branch_addrofs, lr_restor, flag, taken, except_start,
	binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
	genpc_freeze, genpc_stop_prefetch, no_more_dslot
);


input clk_i_cml_1;
input clk_i_cml_2;
input clk_i_cml_3;
reg  icpu_rty_i_cml_3;
reg  icpu_rty_i_cml_2;
reg [ 31 : 0 ] icpu_adr_i_cml_1;
reg [ 3 - 1 : 0 ] branch_op_cml_1;
reg [ 4 - 1 : 0 ] except_type_cml_1;
reg  except_prefix_cml_3;
reg  except_prefix_cml_2;
reg  except_prefix_cml_1;
reg [ 31 : 2 ] branch_addrofs_cml_1;
reg [ 31 : 0 ] lr_restor_cml_1;
reg  flag_cml_1;
reg  except_start_cml_3;
reg  except_start_cml_2;
reg  except_start_cml_1;
reg [ 31 : 2 ] binsn_addr_cml_1;
reg [ 31 : 0 ] epcr_cml_1;
reg [ 31 : 0 ] spr_dat_i_cml_3;
reg [ 31 : 0 ] spr_dat_i_cml_2;
reg [ 31 : 0 ] spr_dat_i_cml_1;
reg  spr_pc_we_cml_3;
reg  spr_pc_we_cml_2;
reg  genpc_refetch_cml_3;
reg  genpc_refetch_cml_2;
reg  no_more_dslot_cml_3;
reg  no_more_dslot_cml_2;
reg [ 31 : 2 ] pcreg_cml_3;
reg [ 31 : 2 ] pcreg_cml_2;
reg [ 31 : 2 ] pcreg_cml_1;
reg [ 31 : 0 ] pc_cml_3;
reg [ 31 : 0 ] pc_cml_2;
reg  genpc_refetch_r_cml_3;
reg  genpc_refetch_r_cml_2;
reg  genpc_refetch_r_cml_1;



//
// I/O
//

//
// Clock and reset
//
input				clk;
input				rst;

//
// External i/f to IC
//
output	[31:0]			icpu_adr_o;
output				icpu_cycstb_o;
output	[3:0]			icpu_sel_o;
output	[3:0]			icpu_tag_o;
input				icpu_rty_i;
input	[31:0]			icpu_adr_i;

//
// Internal i/f
//
input	[`OR1200_BRANCHOP_WIDTH-1:0]	branch_op;
input	[`OR1200_EXCEPT_WIDTH-1:0]	except_type;
input					except_prefix;
input	[31:2]			branch_addrofs;
input	[31:0]			lr_restor;
input				flag;
output				taken;
input				except_start;
input	[31:2]			binsn_addr;
input	[31:0]			epcr;
input	[31:0]			spr_dat_i;
input				spr_pc_we;
input				genpc_refetch;
input				genpc_stop_prefetch;
input				genpc_freeze;
input				no_more_dslot;

//
// Internal wires and regs
//
reg	[31:2]			pcreg;
reg	[31:0]			pc;
reg				taken;	/* Set to in case of jump or taken branch */
reg				genpc_refetch_r;

//
// Address of insn to be fecthed
//

// SynEDA CoreMultiplier
// assignment(s): icpu_adr_o
// replace(s): icpu_adr_i, except_start
assign icpu_adr_o = !no_more_dslot & !except_start_cml_1 & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i_cml_1 : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;

//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;

//
// genpc_freeze_r
//

// SynEDA CoreMultiplier
// assignment(s): genpc_refetch_r
// replace(s): genpc_refetch, genpc_refetch_r
always @(posedge clk or posedge rst)
	if (rst)
		genpc_refetch_r <= #1 1'b0;
	else begin  genpc_refetch_r <= genpc_refetch_r_cml_3; if (genpc_refetch_cml_3)
		genpc_refetch_r <= #1 1'b1;
	else
		genpc_refetch_r <= #1 1'b0; end

//
// Async calculation of new PC value. This value is used for addressing the IC.
//

// SynEDA CoreMultiplier
// assignment(s): pc
// replace(s): branch_op, except_type, except_prefix, branch_addrofs, lr_restor, flag, except_start, binsn_addr, epcr, spr_dat_i, pcreg
always @(pcreg_cml_1 or branch_addrofs_cml_1 or binsn_addr_cml_1 or flag_cml_1 or branch_op_cml_1 or except_type_cml_1
	or except_start_cml_1 or lr_restor_cml_1 or epcr_cml_1 or spr_pc_we or spr_dat_i_cml_1 or except_prefix_cml_1) begin
	casex ({spr_pc_we, except_start_cml_1, branch_op_cml_1})	// synopsys parallel_case
		{2'b00, `OR1200_BRANCHOP_NOP}: begin
			pc = {pcreg_cml_1 + 30'd1, 2'b0};
		end
		{2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_J: pc <= branch_addrofs_cml_1 %h", $time, branch_addrofs_cml_1);
// synopsys translate_on
`endif
			pc = {branch_addrofs_cml_1, 2'b0};
		end
		{2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_JR: pc <= lr_restor_cml_1 %h", $time, lr_restor_cml_1);
// synopsys translate_on
`endif
			pc = lr_restor_cml_1;
		end
		{2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_BAL: pc %h = binsn_addr_cml_1 %h + branch_addrofs_cml_1 %h", $time, binsn_addr_cml_1 + branch_addrofs_cml_1, binsn_addr_cml_1, branch_addrofs_cml_1);
// synopsys translate_on
`endif
			pc = {binsn_addr_cml_1 + branch_addrofs_cml_1, 2'b0};
		end
		{2'b00, `OR1200_BRANCHOP_BF}:
			if (flag_cml_1) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BF: pc %h = binsn_addr_cml_1 %h + branch_addrofs_cml_1 %h", $time, binsn_addr_cml_1 + branch_addrofs_cml_1, binsn_addr_cml_1, branch_addrofs_cml_1);
// synopsys translate_on
`endif
				pc = {binsn_addr_cml_1 + branch_addrofs_cml_1, 2'b0};
			end
			else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
				pc = {pcreg_cml_1 + 30'd1, 2'b0};
			end
		{2'b00, `OR1200_BRANCHOP_BNF}:
			if (flag_cml_1) begin
				pc = {pcreg_cml_1 + 30'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
			end
			else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
				$display("%t: BRANCHOP_BNF: pc %h = binsn_addr_cml_1 %h + branch_addrofs_cml_1 %h", $time, binsn_addr_cml_1 + branch_addrofs_cml_1, binsn_addr_cml_1, branch_addrofs_cml_1);
// synopsys translate_on
`endif
				pc = {binsn_addr_cml_1 + branch_addrofs_cml_1, 2'b0};
			end
		{2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("%t: BRANCHOP_RFE: pc <= epcr_cml_1 %h", $time, epcr_cml_1);
// synopsys translate_on
`endif
			pc = epcr_cml_1;
		end
		{2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
			pc = {(except_prefix_cml_1 ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type_cml_1, `OR1200_EXCEPT_V};
		end
		default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
			$display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
			pc = spr_dat_i_cml_1;
		end
	endcase
end


// SynEDA CoreMultiplier
// assignment(s): taken
// replace(s): branch_op, flag, except_start
always @(pcreg or branch_addrofs or binsn_addr or flag_cml_1 or branch_op_cml_1 or except_type
	or except_start_cml_1 or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
	casex ({spr_pc_we, except_start_cml_1, branch_op_cml_1})	// synopsys parallel_case
		{2'b00, `OR1200_BRANCHOP_NOP}: begin
			taken = 1'b0;
		end
		{2'b00, `OR1200_BRANCHOP_J}: begin
			taken = 1'b1;
		end
		{2'b00, `OR1200_BRANCHOP_JR}: begin
			taken = 1'b1;
		end
		{2'b00, `OR1200_BRANCHOP_BAL}: begin
			taken = 1'b1;
		end
		{2'b00, `OR1200_BRANCHOP_BF}:
			if (flag_cml_1) begin
				taken = 1'b1;
			end
			else begin
				taken = 1'b0;
			end
		{2'b00, `OR1200_BRANCHOP_BNF}:
			if (flag_cml_1) begin
				taken = 1'b0;
			end
			else begin
				taken = 1'b1;
			end
		{2'b00, `OR1200_BRANCHOP_RFE}: begin
			taken = 1'b1;
		end
		{2'b01, 3'bxxx}: begin
			taken = 1'b1;
		end
		default: begin
			taken = 1'b0;
		end
	endcase
end

//
// PC register
//

// SynEDA CoreMultiplier
// assignment(s): pcreg
// replace(s): icpu_rty_i, except_prefix, except_start, spr_dat_i, spr_pc_we, genpc_refetch, no_more_dslot, pcreg, pc
always @(posedge clk or posedge rst)
	if (rst)
//		pcreg <= #1 30'd63;
		pcreg <= #1 ({(except_prefix_cml_3 ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
	else begin  pcreg <= pcreg_cml_3; if (spr_pc_we_cml_3)
		pcreg <= #1 spr_dat_i_cml_3[31:2];
	else if (no_more_dslot_cml_3 | except_start_cml_3 | !genpc_freeze & !icpu_rty_i_cml_3 & !genpc_refetch_cml_3)
//	else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
		pcreg <= #1 pc_cml_3[31:2]; end


always @ (posedge clk_i_cml_1) begin
icpu_adr_i_cml_1 <= icpu_adr_i;
branch_op_cml_1 <= branch_op;
except_type_cml_1 <= except_type;
except_prefix_cml_1 <= except_prefix;
branch_addrofs_cml_1 <= branch_addrofs;
lr_restor_cml_1 <= lr_restor;
flag_cml_1 <= flag;
except_start_cml_1 <= except_start;
binsn_addr_cml_1 <= binsn_addr;
epcr_cml_1 <= epcr;
spr_dat_i_cml_1 <= spr_dat_i;
pcreg_cml_1 <= pcreg;
genpc_refetch_r_cml_1 <= genpc_refetch_r;
end
always @ (posedge clk_i_cml_2) begin
icpu_rty_i_cml_2 <= icpu_rty_i;
except_prefix_cml_2 <= except_prefix_cml_1;
except_start_cml_2 <= except_start_cml_1;
spr_dat_i_cml_2 <= spr_dat_i_cml_1;
spr_pc_we_cml_2 <= spr_pc_we;
genpc_refetch_cml_2 <= genpc_refetch;
no_more_dslot_cml_2 <= no_more_dslot;
pcreg_cml_2 <= pcreg_cml_1;
pc_cml_2 <= pc;
genpc_refetch_r_cml_2 <= genpc_refetch_r_cml_1;
end
always @ (posedge clk_i_cml_3) begin
icpu_rty_i_cml_3 <= icpu_rty_i_cml_2;
except_prefix_cml_3 <= except_prefix_cml_2;
except_start_cml_3 <= except_start_cml_2;
spr_dat_i_cml_3 <= spr_dat_i_cml_2;
spr_pc_we_cml_3 <= spr_pc_we_cml_2;
genpc_refetch_cml_3 <= genpc_refetch_cml_2;
no_more_dslot_cml_3 <= no_more_dslot_cml_2;
pcreg_cml_3 <= pcreg_cml_2;
pc_cml_3 <= pc_cml_2;
genpc_refetch_r_cml_3 <= genpc_refetch_r_cml_2;
end
endmodule