module fifo_1d_fwft (
    input  wire             clk,
    input  wire             rst,
    input  wire [WIDTH-1:0] a_data,
    input  wire             a_valid,
    output wire             a_ready,
    output wire [WIDTH-1:0] b_data,
    output wire             b_valid,
    input  wire             b_ready
);

    parameter WIDTH = 64;

    reg [WIDTH-1:0] fifo;
    reg fifo_full;
    always @(posedge clk) begin
        if (rst) begin
            fifo_full <= 1'b0;
        end
        else begin
            if (a_ready && a_valid) begin
                fifo <= a_data;
                if (!b_ready)
                    fifo_full <= 1'b1;
            end
            else if (b_ready)
                fifo_full <= 1'b0;
        end
    end
    assign b_valid = fifo_full || a_valid;
    assign b_data = fifo_full ? fifo : a_data;
    assign a_ready = !fifo_full;

endmodule