module ram_256_32(
    input wire clk,
    input wire rst,
    // Read port
    input wire [7:0] raddr,
    output wire [31:0] rd,
    input wire re,
    // Write port
    input wire [7:0] waddr,
    input wire [31:0] wr,
    input wire we
);

`ifdef SKY130
    // Collision avoidance policy: write take priority
    wire re_ca = ((raddr == waddr) && we) ? 1'b0 : re;

    // No 128_32 macro provided, so...
    sky130_sram_1kbyte_1rw1r_32x256_8 mem(
        .clk0(clk),
        .csb0(!we),
        .web0(!we),
        .wmask0(4'hF),
        .addr0(waddr),
        .din0(wr),
        .dout0(),
        .clk1(clk),
        .csb1(!re_ca),
        .addr1(raddr),
        .dout1(rd)
    );
`else
    reg [31:0] mem [0:127];
    reg [31:0] rd_reg;

    always @(posedge clk) begin
        if (!rst) begin
            if (we) begin
                mem[waddr] <= wr;
            end
            
            if (re) begin
                rd_reg <= mem[raddr];
            end
        end
    end

    assign rd = rd_reg;
`endif

endmodule