module hbmc_arst_sync #
(
    parameter integer C_SYNC_STAGES = 3
)
(
    input   wire    clk,
    input   wire    arst,
    output  wire    rst
);
    
    hbmc_bit_sync #
    (
        .C_SYNC_STAGES  ( C_SYNC_STAGES ),
        .C_RESET_STATE  ( 1'b1          )
    )
    hbmc_bit_sync_inst
    (
        .arst   ( arst ),
        .clk    ( clk  ),
        .d      ( 1'b0 ),
        .q      ( rst  )
    );
    
endmodule