module ft245_axi_fifo_32_8
(
    // Inputs
     input           clk_i
    ,input           rst_i
    ,input           inport_valid_i
    ,input  [ 31:0]  inport_data_i
    ,input           outport_accept_i

    // Outputs
    ,output          inport_accept_o
    ,output [  7:0]  outport_data_o
    ,output          outport_valid_o
);



reg       valid_q;
reg [7:0] data_q;

reg [1:0] idx_q;

wire      accept_w;

//-----------------------------------------------------------------
// Last valid data detection
//-----------------------------------------------------------------
wire last_data_w = (idx_q == 2'd3);

//-----------------------------------------------------------------
// Data
//-----------------------------------------------------------------
reg [7:0] data_r;

always @ *
begin
    data_r = 8'b0;
    case (idx_q)
    2'd0: data_r = inport_data_i[7:0];
    2'd1: data_r = inport_data_i[15:8];
    2'd2: data_r = inport_data_i[23:16];
    2'd3: data_r = inport_data_i[31:24];
    endcase
end

always @ (posedge clk_i )
if (rst_i)
    data_q <= 8'b0;
else if (accept_w)
    data_q <= data_r;

assign outport_data_o = data_q;

//-----------------------------------------------------------------
// Valid
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
    valid_q <= 1'b0;
else if (accept_w)
    valid_q <= inport_valid_i;

assign outport_valid_o = valid_q;

//-----------------------------------------------------------------
// Data read index
//-----------------------------------------------------------------
always @ (posedge clk_i )
if (rst_i)
    idx_q <= 2'b0;
else if (last_data_w && accept_w)
    idx_q <= 2'b0;
else if (accept_w && inport_valid_i)
    idx_q <= idx_q + 2'd1;

//-----------------------------------------------------------------
// Accept
//-----------------------------------------------------------------
assign accept_w = !outport_valid_o || (outport_valid_o && outport_accept_i);

// Entire word consumed, pop...
assign inport_accept_o = accept_w && last_data_w;




endmodule