module delay #(parameter N=10) (req,fin);
input req;
output wire fin;

(* dont_touch="true" *) wire [N-1:0] c /*synthesis noprune*/;  
// (* dont_touch="true" *) and /*synthesis noprune*/ make it work on both Xilinx platform and Altera platform. 

reg rec=1'b0;
assign c[0]=rec;
assign fin = c[N-1];

always@(posedge req or posedge fin) begin
	if(fin) rec<=1'b0;
	else rec<=1'b1;
end

genvar i;
generate 
	for(i=1;i<N;i=i+1)
	begin:delays
		assign c[i]=rec&(c[i-1]);
	end
endgenerate

endmodule