module delay_bus #(
	parameter integer DELAY = 1,
	parameter integer WIDTH = 1
)(
	input  wire [WIDTH-1:0] d,
	output wire [WIDTH-1:0] q,
	input  wire clk
);
	genvar i;

	// Variables / Signals
	wire [4:0] addr = DELAY - 2;
	wire [WIDTH-1:0] ff_in;

	// Generate SRL if needed (or bypass if not)
	generate
		if (DELAY > 17) begin
			for (i=0; i<WIDTH; i=i+1)
				SRLC32E srl_I (
					.Q(ff_in[i]),
					.A(addr),
					.CE(1'b1),
					.CLK(clk),
					.D(d[i])
				);
		end else if (DELAY > 1) begin
			for (i=0; i<WIDTH; i=i+1)
				SRL16E srl_I (
					.Q(ff_in[i]),
					.A0(addr[0]),
					.A1(addr[1]),
					.A2(addr[2]),
					.A3(addr[3]),
					.CE(1'b1),
					.CLK(clk),
					.D(d[i])
				);
		end else begin
			assign ff_in = d;
		end
	endgenerate

	// Generate flip-flop if needed (or bypass if not)
	generate
		if (DELAY > 0) begin
			for (i=0; i<WIDTH; i=i+1)
				FDRE ff_I (
					.Q(q[i]),
					.C(clk),
					.CE(1'b1),
					.D(ff_in[i]),
					.R(1'b0)
				);
		end else begin
			assign q = ff_in;
		end
	endgenerate

endmodule // delay_bus