module OutPort(DB_bit, W4016, nACLK2, ACLK1, OUT_val);

	inout DB_bit;
	input W4016;
	input nACLK2;
	input ACLK1;
	output OUT_val;

	wire ff_out;
	wire ACLK5;

	assign ACLK5 = ~nACLK2;		// Other ACLK

	RegisterBit out_ff (
		.d(DB_bit),
		.ena(W4016),
		.ACLK1(ACLK1),
		.q(ff_out) );

	wire n_latch_out;

	dlatch out_latch (
		.d(ff_out),
		.en(ACLK5),
		.nq(n_latch_out) );

	assign OUT_val = ~n_latch_out;

endmodule // OutPort