module Core6502 (n_NMI, n_IRQ, n_RES, PHI0, PHI1, PHI2, RDY, SO, RnW, SYNC, A, D);

	input n_NMI;		// Non-maskable interrupt signal, active low
	input n_IRQ;		// Maskable interrupt signal, active low
	input n_RES;		// Reset signal, active low
	input PHI0;			// Reference clock signal
	output PHI1;		// First half-cycle, processor in `Set RW / Address` mode
	output PHI2;		// Second half-cycle, processor in `Read/Write Data` mode
	input RDY;			// Processor Ready (1: ready)
	input SO;			// Forced setting of the overflow flag (V)
	output RnW;			// Data bus direction (R/W=1: processor reads data, R/W=0: processor writes)
	output SYNC;		// The processor is on cycle T1 (opcode fetch)
	output [15:0] A;	// Address bus
	inout [7:0] D; 		// Data bus (bidirectional)

	assign PHI1 = ~PHI0;
	assign PHI2 = PHI0;
	assign SYNC = 1'b0;

	reg [31:0] regdump_rom [0:32767];
	wire [23:0] regdump_addr;

	initial begin
		$readmemh("regdump.mem", regdump_rom);
	end

	RegDumpProcessor rp (
		.PHI0(PHI0), 
		.n_RES(n_RES),
		.RnW(RnW), 
		.addr_bus(A), 
		.data_bus(D),
		.regdump_data(regdump_rom[regdump_addr]), 
		.regdump_addr(regdump_addr) );

endmodule // Core6502