module mactable_dpcam_line_array #(
	parameter ADDR_WIDTH = 8,
	parameter KEY_WIDTH = 8
)
(
	input wire clk,
	input wire rst,
	input wire [ADDR_WIDTH-1:0]set_addr,
	input wire [KEY_WIDTH-1:0]set_key,
	input wire set_clr,
	input wire set_valid,
	input wire [KEY_WIDTH-1:0]req_key0,
	input wire [KEY_WIDTH-1:0]req_key1,
	input wire req_valid,
	output wire [2**ADDR_WIDTH-1:0]line_match0,
	output wire [2**ADDR_WIDTH-1:0]line_match1
);

localparam MEM_WIDTH = KEY_WIDTH;

reg [MEM_WIDTH-1:0]mem[2**ADDR_WIDTH-1:0];
reg [2**ADDR_WIDTH-1:0]active;

reg [2**ADDR_WIDTH-1:0]match[1:0];
wire [KEY_WIDTH-1:0]key[2**ADDR_WIDTH-1:0];

integer i;
genvar g;

generate for (g = 0; g < 2**ADDR_WIDTH; g = g + 1) begin
	wire [MEM_WIDTH-1:0]mem_tmp;
	assign mem_tmp = mem[g];
	assign key[g] = mem_tmp;
end endgenerate

assign line_match0 = match[0];
assign line_match1 = match[1];

/* Initial */
initial begin
	for (i = 0; i < 2**ADDR_WIDTH; i = i + 1) begin
		mem[i] = 0;
	end
end

/* Set */
always @(posedge clk) begin
	if (rst == 1'b1) begin
		active = {KEY_WIDTH{1'b0}};
	end else begin
		if (set_valid == 1'b1) begin
			for (i = 0; i < 2**ADDR_WIDTH; i = i + 1) begin
				if (set_addr == i) begin
					mem[i] <= set_key;
					active[i] <= ~set_clr;
				end
			end
		end
	end
end

/* Request */
always @(posedge clk) begin
	if (rst == 1'b1) begin
		match[0] <= {2**ADDR_WIDTH{1'b0}};
		match[1] <= {2**ADDR_WIDTH{1'b0}};
	end else begin
		if (req_valid == 1'b1) begin
			for (i = 0; i < 2**ADDR_WIDTH; i = i + 1) begin
				match[0][i] <= ((key[i] ^ req_key0) == 0) & active[i];
				match[1][i] <= ((key[i] ^ req_key1) == 0) & active[i];
			end
		end
	end
end

endmodule