module mem_1r1w # (
  parameter BYTES_PER_LINE = 4,
  parameter ADDR_WIDTH     = 11,
  parameter LINE_SIZE      = 8*BYTES_PER_LINE
)(
  input  wire                      clka,
  input  wire                      ena,
  input  wire [BYTES_PER_LINE-1:0] wea,
  input  wire [ADDR_WIDTH-1:0]     addra,
  input  wire [LINE_SIZE-1 :0]     dina,

  input  wire                      clkb,
  input  wire                      enb,
  input  wire [ADDR_WIDTH-1:0]     addrb,
  output wire [LINE_SIZE-1 :0]     doutb
);

(* ram_style = "block" *)
reg [LINE_SIZE-1:0] mem [0:(2**ADDR_WIDTH)-1];
reg [LINE_SIZE-1:0] mem_out;
integer i;

always @ (posedge clka)
  if (ena)
    for (i = 0; i < BYTES_PER_LINE; i = i + 1)
      if (wea[i] == 1'b1)
        mem[addra][i*8 +: 8]  <= dina[i*8 +: 8];

always @ (posedge clkb)
  if (enb)
    mem_out <= mem[addrb];

assign doutb = mem_out;

endmodule