module c_BIN_NAND_SR_LATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0,
     output [0:0] out_1
);

wire net_0 = in_0;
wire net_1 = in_1;

wire net_2;
wire net_3;
wire net_4 = net_2;
wire net_5 = net_3;

assign out_0 = net_4;
assign out_1 = net_5;

f_22Z LogicGate_0 (
.in_1(net_0),
.in_0(net_3),
.out_0(net_2)
);

f_22Z LogicGate_1 (
.in_1(net_2),
.in_0(net_1),
.out_0(net_3)
);

endmodule