module sw_dolut_tb;

	// Inputs
	reg iT;
	reg iB;
	reg c;
	reg vcc;

	// Outputs
	wire oT;
	wire oB;

	// Instantiate the Unit Under Test (UUT)
	sw_dolut uut (
		.iT(iT), 
		.iB(iB), 
		.c(c), 
		.vcc(vcc), 
		.oT(oT), 
		.oB(oB)
	);

	initial begin
		// Initialize Inputs
		iT = 0;
		iB = 0;
		c = 0;
		vcc = 1'b1;

		// Wait 100 ns for global reset to finish
		#100;
		iT = 1;
		iB = 0;
		c = 0;
		
		#100;
		iT = 1;
		iB = 0;
		c = 1;
		
		#100;
		iT = 0;
		iB = 1;
		c = 0;
		
		#100;
		iT = 0;
		iB = 1;
		c = 1;
		
		#100;
		iT = 0;
		iB = 1;
		c = 1;
		
		#100;
		iT = 1;
		iB = 1;
		c = 1;
      

		
	end
      
endmodule