module XYRegBit (PHI2, Reg_SB, SB_Reg, SB_bit, dbg);

	input PHI2;
	input Reg_SB;
	input SB_Reg;
	inout SB_bit;
	output dbg; 			// Not on a real chip

	wire d;
	assign d = SB_Reg ? SB_bit : (PHI2 ? not_nq : 1'bz);

	wire hold_latch_nq;
	wire not_nq;
	dlatch hold_latch (.d(d), .en(1'b1), .q(dbg), .nq(hold_latch_nq));
	not (not_nq, hold_latch_nq);

	assign SB_bit = Reg_SB ? not_nq : 1'bz;

endmodule // XYRegBit