module fm_cmn_dinterface (
  clk_core,
  rst_x,
  // bus side port
  i_bstr,
  i_bdata,
  o_back,
  // internal port
  o_istr,
  o_idata,
  i_iack
);

parameter P_WIDTH = 36;
////////////////////////////
// I/O definitions
////////////////////////////
input         i_bstr;         // input strobe
input  [P_WIDTH-1:0]
              i_bdata;        // input data (Write Data + BE)
output        o_back;         // output acknowledge

output        o_istr;         // output strobe
output [P_WIDTH-1:0]
              o_idata;        // output data
input         i_iack;         // input acknowledge

input         clk_core;            // system clock
input         rst_x;          // system reset

/////////////////////////
//  register definition
/////////////////////////
// input register
reg           r_bstr;
reg    [P_WIDTH-1:0]
              r_bdata;
reg           r_back;

/////////////////////////
//  wire definition
/////////////////////////
wire          w_empty;
/////////////////////////
//  assign statement
/////////////////////////
assign o_istr = !w_empty;
assign o_back = r_back;
/////////////////////////
//  always statement
/////////////////////////
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstr <= 1'b0;
  end else begin
    r_bstr <= i_bstr;
  end
end

always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_back <= 1'b0;
  end else begin
    r_back <= i_iack;
  end
end

always @(posedge clk_core) begin
  r_bdata <= i_bdata;
end

/////////////////////////
//  module instanciation
/////////////////////////
// input data fifo
fm_cmn_ififo #(P_WIDTH) u_ififo (  // Write Data + BE
//fm_cmn_bfifo #(P_WIDTH,3) fifo (  // Write Data + BE
//  .o_dnum(),
  .i_wstrobe(r_bstr),
  .i_dt(r_bdata),
  .o_full(),
  .i_renable(i_iack),
  .o_dt(o_idata),
  .o_empty(w_empty),
  .clk_core(clk_core),
  .rst_x(rst_x)
);

endmodule