module tri_fu_mul_bthmux(
   x,
   sneg,
   sx,
   sx2,
   right,
   left,
   q
);
   input   x;
   input   sneg;		// do not flip the input (add)
   input   sx;		// shift by 1
   input   sx2;		// shift by 2
   input   right;		// bit from the right (lsb)
   output  left;		// bit from the left
   output  q;		// final output

   wire    center;
   wire    q_b;

   assign center = x ^ sneg;

   assign left = center;		//output-- rename, no gate

   assign q_b = (~((sx & center) | (sx2 & right)));

   assign q = (~q_b);		// output--

endmodule