module b(clock,
		a_in,
		b_in,
		out);

input	clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire [`BITS-1:0] temp2;
output [`BITS-1:0]    out;
reg [`BITS-1:0] out;

c myb_c(clock, a_in[0], b_in[0], temp2[0]);
c myb_c2(clock, a_in[0], b_in[1], temp2[1]);

always @(posedge clock)
begin
	temp <= a_in + b_in - temp2;
	out <= a_in + temp;
end

endmodule