module M_main (
out_leds,
in_run,
out_done,
reset,
out_clock,
clock
);
output  [7:0] out_leds;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
wire signed [15:0] _w_div0_ret;
wire _w_div0_done;
wire signed [15:0] _c_num;
assign _c_num = 20043;
wire signed [15:0] _c_den;
assign _c_den = 41;
reg signed [15:0] _t_result;

reg  [7:0] _d_leds;
reg  [7:0] _q_leds;
reg signed [15:0] _d_div0_inum,_q_div0_inum;
reg signed [15:0] _d_div0_iden,_q_div0_iden;
reg  [1:0] _d_index,_q_index = 3;
reg  _autorun = 0;
reg  _div0_run = 0;
assign out_leds = _q_leds;
assign out_done = (_q_index == 3) & _autorun;
M_div16__div0 div0 (
.in_inum(_q_div0_inum),
.in_iden(_q_div0_iden),
.out_ret(_w_div0_ret),
.out_done(_w_div0_done),
.in_run(_div0_run),
.reset(reset),
.clock(clock));



`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (out_done));
`endif
always @* begin
_d_leds = _q_leds;
_d_div0_inum = _q_div0_inum;
_d_div0_iden = _q_div0_iden;
_d_index = _q_index;
_div0_run = 1;
_t_result = 0;
// _always_pre
(* full_case *)
case (_q_index)
0: begin
// _top
_d_div0_inum = _c_num;
_d_div0_iden = _c_den;
_div0_run = 0;
_d_index = 1;
end
1: begin
// __block_1
if (_w_div0_done == 1) begin
_d_index = 2;
end else begin
_d_index = 1;
end
end
2: begin
// __block_2
_t_result = _w_div0_ret;
$display("%d / %d = %d",_c_num,_c_den,_t_result);
_d_leds = _t_result[0+:8];
_d_index = 3;
end
3: begin // end of 
end
default: begin 
_d_index = {2{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase
// _always_post
end

always @(posedge clock) begin
_q_leds <= _d_leds;
_q_index <= reset ? 3 : ( ~_autorun ? 0 : _d_index);
_autorun <= reset ? 0 : 1;
_q_div0_inum <= _d_div0_inum;
_q_div0_iden <= _d_div0_iden;
end

endmodule