module Display  // source/rtl/Display.v(19)
  (
  clk,
  lcd_xpos,
  lcd_ypos,
  rst_n,
  lcd_data
  );

  input clk;  // source/rtl/Display.v(25)
  input [11:0] lcd_xpos;  // source/rtl/Display.v(27)
  input [11:0] lcd_ypos;  // source/rtl/Display.v(28)
  input rst_n;  // source/rtl/Display.v(26)
  output [23:0] lcd_data;  // source/rtl/Display.v(30)

  parameter H_DISP = 1280;
  parameter V_DISP = 1024;
  wire [23:0] n1;
  wire n0;

  mult_u12_u12_o24 mult0 (
    .i0(lcd_xpos),
    .i1(lcd_ypos),
    .o(n1));  // source/rtl/Display.v(93)
  reg_ar_as_w24 reg0 (
    .clk(clk),
    .d(n1),
    .reset({n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0,n0}),
    .set(24'b000000000000000000000000),
    .q(lcd_data));  // source/rtl/Display.v(93)
  not u1 (n0, rst_n);  // source/rtl/Display.v(90)

endmodule 