module top_mido(
 input reset,
 input clk,
//-----------------------------------mdio ½Ó¿Ú---------------------------------
 output  mdc,//Êä³ö¸øÍâ²¿Ð¾Æ¬µÄÊ±ÖÓ
 inout  mdio,
 output [3:0] port_link
);


/************Ä£¿éÁ¬½ÓÇø**************/
 wire req_enb;//Ê¹ÄÜÐÅºÅ£¬ÀàËÆÓÚÆ¬Ñ¡ÐÅºÅ
 wire [1:0] req_op;   //±¾´ÎÇëÇóµÄ²Ù×÷Ä£Ê½ [1]ÓÐÐ§Îª¶Á£¬[0]ÓÐÐ§ÎªÐ´
 wire [4:0] phy_addr;//phyÐ¾Æ¬Ñ¡Ôñ
 wire [4:0] reg_addr;//phyÐ¾Æ¬ÖÐµÄ¼Ä´æÆ÷Ñ¡Ôñ
 wire [15:0] data_phy;
 //--------------¸øÓÃ»§µÄµ±Ç°Ã¦ÏÐÐÅºÅ---------------------
 wire work_flag;//1:ÕýÔÚ¹¤×÷×´Ì¬   0£º´¦ÓÚÏÐÖÃ×´Ì¬
//-----------------------------------
 wire [15:0] data_sta;
 wire  sta_enb;
 
mdio_mdc mdio_mdc(
.reset(reset),
.clk(clk),
//-----------------------------------mdio ½Ó¿Ú---------------------------------
.mdc(mdc),//Êä³ö¸øÍâ²¿Ð¾Æ¬µÄÊ±ÖÓ
.mdio(mdio),
 //--------------ÓÃ»§¸ø³öµÄ²Ù×÷Ö¸Áî×é---------------------
.req_enb(req_enb),//Ê¹ÄÜÐÅºÅ£¬ÀàËÆÓÚÆ¬Ñ¡ÐÅºÅ
.req_op(req_op),   //±¾´ÎÇëÇóµÄ²Ù×÷Ä£Ê½ [1]ÓÐÐ§Îª¶Á£¬[0]ÓÐÐ§ÎªÐ´
.phy_addr(phy_addr),//phyÐ¾Æ¬Ñ¡Ôñ
.reg_addr(reg_addr),//phyÐ¾Æ¬ÖÐµÄ¼Ä´æÆ÷Ñ¡Ôñ
.data_phy(data_phy),
 //--------------¸øÓÃ»§µÄµ±Ç°Ã¦ÏÐÐÅºÅ---------------------
.work_flag(work_flag),//1:ÕýÔÚ¹¤×÷×´Ì¬   0£º´¦ÓÚÏÐÖÃ×´Ì¬
//-----------------------------------
.data_sta(data_sta),
.sta_enb(sta_enb)
);

reg_access reg_access (
.clk(clk),
.data_sta(data_sta),
.phy_addr(phy_addr),
.port_link(port_link),
.reg_addr(reg_addr),
.req_enb(req_enb),
.req_op(req_op),
.reset(reset),
.sta_enb(sta_enb),
.work_bit(work_flag)
);

endmodule