module pipeline #
(
    parameter   PIPE_WIDTH  = 32,
    parameter   PIPE_STAGES = 8
)
(
    input   wire                        clk,
    input   wire                        cen,
    input   wire                        srst,
    input   wire    [PIPE_WIDTH - 1:0]  pipe_in,
    output  wire    [PIPE_WIDTH - 1:0]  pipe_out
);
    
/*-------------------------------------------------------------------------------------------------------------------------------------*/
    
    genvar i;
    
    generate
        for (i = 0; i < PIPE_WIDTH; i = i + 1) begin: loop
        
            reg [PIPE_STAGES - 1:0] pipe_gen;
            
            always @(posedge clk) begin
                if (srst) begin
                    pipe_gen <= {PIPE_STAGES{1'b0}};
                end else begin
                    if (cen) begin
                        pipe_gen <= (PIPE_STAGES > 1)? {pipe_gen[PIPE_STAGES - 2:0], pipe_in[i]} : pipe_in[i];
                    end
                end
            end
            
            assign pipe_out[i] = pipe_gen[PIPE_STAGES - 1];
        end
    endgenerate
    
endmodule