module MEM_BLK_V5_0( clk,
                     write_en,
                     read_en,
                     wr_addr,
                     rd_addr,
                     data_in,
                     data_out,
                     rst
                   );

parameter addr_value = 4  ;
parameter data_width = 16 ;
parameter mem_depth      = 16 ;


input                    clk;       // input clk.
input                    write_en;    // Write Signal to put datainto fifo.
input                    read_en ;
input  [(addr_value-1):0]  wr_addr;   // Write Address.
input  [(addr_value-1):0]  rd_addr;   // Read Address.
input  [(data_width-1):0]   data_in;   // DataIn in to Memory Block
input                    rst ;

output [(data_width-1):0]   data_out;  // Data Out from the Memory Block(FIFO)

reg  [(data_width-1):0] data_out;  

reg    [(data_width-1):0] FIFO[0:(mem_depth-1)];


initial begin
data_out = 0 ;
end




always @(posedge clk)
begin
   if (rst == 1'b1)
      data_out <= 0 ; 
   else
      begin
        if (read_en == 1'b1) 
          data_out  <= FIFO[rd_addr];
      end
end

always @(posedge clk)
begin
   if(write_en ==1'b1)
      FIFO[wr_addr] <= data_in;
end

endmodule