module SspRevAnd (
// Inputs
                 TieOff1,
                 TieOff2,
// Outputs
                 Revision
                 );

// Inputs
input        TieOff1;  // AND gate input 1
input        TieOff2;  // AND gate input 2
// Outputs
output       Revision; // AND gate output

// ---------------------------------------------------------------------
//
//                              SspRevAnd
//                              =========
//
// ---------------------------------------------------------------------
//
// Overview
// ========
//   This module contains a single AND gate to be used as a
// place-holder cell to mark the Revision of the Ssp.
// The 2 input pins will be tied-off at the top level of the
// hierarchy. These "TieOffs" can be identified during layout
// and re-wired to "VDD" or "VSS" if needed.
//
// ---------------------------------------------------------------------


// ---------------------------------------------------------------------
// Register declarations
// ---------------------------------------------------------------------


// ---------------------------------------------------------------------
//
// Main body of code
// =================
//
// ---------------------------------------------------------------------



assign Revision = TieOff1 & TieOff2;

endmodule