module shift_n(input [7:0] in, output [7:0] out);
	/*
	 * The parameter n feels like an argument passed down
	 * by caller. It truly is, but in a weird way.
	 *
	 * And we initialize to 2. GCC has an option to have compile
	 * error is n is not set before use. Does Verilog compiler
	 * has similar stuff?
	 */
	parameter n = 2;
	assign out = (in << n);
endmodule