module test_module_bb(clk, G0, G1, G2_0, G2_1, G18_0, G18_1);
    input clk, G0, G1;
    input G2_0,G2_1;
    output G18_0,G18_1;
    wire G3, G4, G5;

    ff DFF_0(.CK (clk), .D (G3), .Q (G4));
    and AND2_0(G3, G0, G1);
    and AND2_1(G18_1, G5, G2_1);
    ff DFF_1(.CK (clk), .D(G2_0), .Q(G5));
    ff DFF_2(.CK (clk), .D(G5), .Q(G18_0));
endmodule