module adc_clk_generation(
   input wire ndecision_finish,   // 0 = comparator finished
   input wire enable_loop,        // 1 = self clocked loop enabled
   output wire clk_dig,           // clk for digital core
   output wire clk_comp,          // clk for comparator
   input wire enable_dlycontrol,  // 0 = max delays, 1 = configured delays
   input wire [4:0] dlycontrol1,  // delay1 = N times 5ns up to 100ns
   input wire [4:0] dlycontrol2,  // delay2 = N times 5ns up to 100ns
   input wire [4:0] dlycontrol3   // delay3 = N times 5ns up to 100ns
);
   wire _ndecision_finish_delayed_;
   wire _clk_dig_delayed_;
   wire _net_1_;

   delaycell  #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_1 
   (
        .in(ndecision_finish), 
        .enable_dlycontrol(enable_dlycontrol), 
        .dlycontrol(dlycontrol1), 
        .out(_ndecision_finish_delayed_)
   );
   assign clk_dig = ~_ndecision_finish_delayed_;
   delaycell  #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_2 
   (
        .in(clk_dig),
        .enable_dlycontrol(enable_dlycontrol), 
        .dlycontrol(dlycontrol2), 
        .out(_clk_dig_delayed_)
    );
   nand(_net_1_,_clk_dig_delayed_,~enable_loop);
   delaycell  #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_3 
   (
        .in(_net_1_),
        .enable_dlycontrol(enable_dlycontrol), 
        .dlycontrol(dlycontrol3), 
        .out(clk_comp)
    );
endmodule