module csc_top
(
  Clock,
  ClockEnable,
  Reset,
  Red,
  Green,
  Blue,
  Y,
  Cb,
  Cr
);

  parameter TOP_OUT_SIZE  =  8; // uncomment to get  8-bit input & output...
//  parameter TOP_OUT_SIZE  = 10; // uncomment to get 10-bit input & output...

  input  Clock; 
  input  ClockEnable; 
  input  Reset; 
  input  [(TOP_OUT_SIZE - 1):0] Red; 
  input  [(TOP_OUT_SIZE - 1):0] Green; 
  input  [(TOP_OUT_SIZE - 1):0] Blue; 
  output [(TOP_OUT_SIZE - 1):0] Y; 
  output [(TOP_OUT_SIZE - 1):0] Cb; 
  output [(TOP_OUT_SIZE - 1):0] Cr; 

  reg [(TOP_OUT_SIZE - 1):0] Y;
  reg [(TOP_OUT_SIZE - 1):0] Cb;
  reg [(TOP_OUT_SIZE - 1):0] Cr;

  // Define internal signals
  reg [(TOP_OUT_SIZE - 1):0] R; 
  reg [(TOP_OUT_SIZE - 1):0] G; 
  reg [(TOP_OUT_SIZE - 1):0] B; 

  wire [(TOP_OUT_SIZE - 1):0] Y_sig; 
  wire [(TOP_OUT_SIZE - 1):0] Cb_sig; 
  wire [(TOP_OUT_SIZE - 1):0] Cr_sig; 

  // Input registers (should be pushed into IOBs)
  always @(posedge Clock or posedge Reset)
  begin : In_Reg
    if (Reset)
    begin
      R <= 0;
      G <= 0;
      B <= 0;
    end
    else if (ClockEnable)
    begin
      R <= Red ; 
      G <= Green ; 
      B <= Blue ; 
    end 
  end 

  // Output registers (should be pushed into IOBs)
  always @(posedge Clock or posedge Reset)
  begin : Out_Reg
    if (Reset)
    begin
      Y  <= 0;
      Cb <= 0;
      Cr <= 0;
    end
    else if (ClockEnable)
    begin
      Y  <= Y_sig ; 
      Cb <= Cb_sig ; 
      Cr <= Cr_sig ; 
    end 
  end 


  // CSC instantiation
  csc  #(TOP_OUT_SIZE) CSC_module
  (
    .Clock(Clock),
    .ClockEnable(ClockEnable),
    .Reset(Reset),
    .R(R),
    .G(G),
    .B(B),
    .Y(Y_sig),
    .Cb(Cb_sig),
    .Cr(Cr_sig)
  );


endmodule