module MUX2 #(parameter Width=32,parameter defaultValue=0) (req1,req2,in1,in2,out);
input req1,req2;
input [Width-1:0] in1,in2;
output wire [Width-1:0] out;
wire req;
wire sel;
reg sel1=1'b0,sel2=defaultValue;  // 0:choose in1, 1:choose in2

assign out=sel?in1:in2;
assign sel=(sel1==sel2);

always@(posedge req1) sel1<=sel2;
always@(posedge req2) sel2<=~sel1;

endmodule