module rf_sub_cm4_24(
		clk_i_cml_3,
		cmls,
		
	a,
	d,
	dpra,
	clk,
	we,
	spo,
	dpo);


input clk_i_cml_3;
input [1:0] cmls;

reg [ 4 : 0 ] a_cml_3;



input [4 : 0] a;
input [31 : 0] d;
input [4 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;

rf_dist_cm4 rf_disti(
	.a({cmls, a_cml_3}),
	.d(d),
	.dpra({cmls, dpra}),
	.clk(clk),
	.we(we),
	.spo(spo),
	.dpo(dpo));

always @ (posedge clk_i_cml_3) begin
a_cml_3 <= a;
end

endmodule