module tb_idle_pattern_inserter;

    reg clk = 1'b1;

    reg channel_ready = 1'b1;
    reg source_ready  = 1'b1;

    reg  [72:0] in_data;
    wire [71:0] out_data;
    reg  [15:0] count;

initial begin
    
    in_data      = 80'b0;
    channel_ready = 1'b1;
    source_ready  = 1'b1;
    count         =    0;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
    #4
    clk = ~clk;
   
    forever begin
        case(count)
           100: in_data = 73'h1444333332222211111;
           200: in_data = 73'h0444333332222211111;
        endcase
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        #4
        clk = ~clk;
        count = count + 1;
    end
end

idle_pattern_inserter  i_idle_pattern_inserter(
    .clk            (clk),
    .channel_ready  (channel_ready),
    .source_ready   (source_ready),
    .in_data        (in_data),
    .out_data       (out_data)
);

endmodule