module ram16k(input clk,
	      input [12:0] 	addr,
	      input [15:0] 	data_in,
	      output [15:0] data_out,
	      input 		we,
	      input 		re);

   wire [15:0]                  data_out_low;
   wire [15:0]                  data_out_high;
   wire                         we_low;
   wire                         re_low;

   wire                         we_high;
   wire                         re_high;

   // Each block is 4048 words; each, in turn,
   //     made of two 2024 word block
   ram8k_low r1(.clk(clk),
                .addr(addr[11:0]),
                .data_in(data_in),
                .data_out(data_out_low),
                .we(we_low),
                .re(re_low));
  
   ram8k_high r2(.clk(clk),
                 .addr(addr[11:0]),
                 .data_in(data_in),
                 .data_out(data_out_high),
                 .we(we_high),
                 .re(re_high));

   reg                          on_high;
   always @(posedge clk) on_high <= addr[12];
   
   assign data_out = on_high?data_out_high:data_out_low;
   assign we_high   = addr[12]&we;
   assign we_low    = (~addr[12])&we;
   
   assign re_low    = 1;
   assign re_high   = 1;
   
endmodule // ram16k