module sync_level2pulse(
  clk,
  rst_b,
  sync_in,
  sync_out,
  sync_ack
);


input          clk;
input          rst_b;
input          sync_in;
output         sync_out;
output         sync_ack;

reg            sync_ff;

wire           clk;
wire           rst_b;
wire           sync_in;
wire           sync_out;
wire           sync_ack;

wire           sync_out_level;

sync_level2level x_sync_level2level (
  .clk      (clk),
  .rst_b    (rst_b),
  .sync_in  (sync_in),
  .sync_out (sync_out_level)
);

always @ (posedge clk or negedge rst_b)
begin
  if (!rst_b)
    sync_ff <= 1'b0;
  else
    sync_ff <= sync_out_level;
end

assign sync_out = sync_out_level & ~sync_ff;
assign sync_ack = sync_out_level;

endmodule