module DMUX ( DRAM_Q, ADDR, CAP_Q );

	input  [127:0]	DRAM_Q;
	input	 [3:2]	ADDR;
	
	output	reg	[31:0]	CAP_Q;
	
	always @(ADDR or DRAM_Q)
	  case (ADDR)
	    2'b00 : CAP_Q = DRAM_Q[31:0];
		2'b01 : CAP_Q = DRAM_Q[63:32];
		2'b10 : CAP_Q = DRAM_Q[95:64];
		2'b11 : CAP_Q = DRAM_Q[127:96];
	  endcase
	  
endmodule