module fm_line_mem (
  clk_vi,
  rst_x,
  i_clear,
  i_dt,
  i_renable,
  o_dt
);

// set default parameters
parameter P_WIDTH = 16;
parameter P_RANGE = 10;
parameter P_DEPTH = 640;
////////////////////////////
// I/O definition
////////////////////////////
input         clk_vi;       // system clock
input         rst_x;        // system reset
input         i_clear;      // write strobe
input  [P_WIDTH-1:0] i_dt;  // write data
input         i_renable;    // read enable
output [P_WIDTH-1:0] o_dt;  // read data

/////////////////////////
//  Register definition
/////////////////////////
reg [P_RANGE-1:0] r_write_counter;
reg [P_RANGE-1:0] r_read_counter;
/////////////////////////
//  wire definition
/////////////////////////
wire             w_we;
wire             w_re;
wire [P_RANGE-1:0] w_read_counter_inc;
wire [P_RANGE-1:0] w_read_counter;
/////////////////////////
//  assign statement
/////////////////////////

assign w_read_counter_inc = r_read_counter + 1'b1;
assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
assign w_we = i_renable;
assign w_re = i_renable;
////////////////////////
// always statement
///////////////////////
  // write side
  always @(posedge clk_vi or negedge rst_x) begin
    if (~rst_x) begin
      r_write_counter <= 'd0;
    end else begin
      if (i_clear)  r_write_counter <= 'd0;
      else if (w_we) r_write_counter <= r_write_counter + 1'b1;
    end
  end

  // read side
  always @(posedge clk_vi or negedge rst_x) begin
    if (~rst_x) begin
      r_read_counter <= 'd0;
    end else begin
      if (i_clear)   r_read_counter <= 'd0;
      else if (w_re) r_read_counter <= w_read_counter_inc;
    end
  end

///////////////////
// module instance
///////////////////
    fm_cmn_bram_01 #(P_WIDTH, P_RANGE) bram_00 (
        .clk(clk_vi),
        .we(w_we),
        .a(r_write_counter),
        .dpra(w_read_counter),
        .di(i_dt),
        .spo(),
        .dpo(o_dt)
    );
endmodule