module pic
  (input clk_i, input rst_i, input cyc_i, input stb_i,
   input [2:0] adr_i, 
   input we_i, 
   input [31:0] dat_i, 
   output reg [31:0] dat_o, 
   output reg ack_o, 
   output reg int_o,
   input [31:0] irq
   );

   reg [31:0] 	pol, edgen, pending, mask;   // register bank
   reg [31:0] 	lirq, dirq;                  // latched irqs, delayed latched irqs
   
   // latch interrupt inputs
   always @(posedge clk_i)
     lirq <=  irq;
   
   // generate delayed latched irqs
   always @(posedge clk_i)
     dirq <=  lirq;

   // generate actual triggers
   function trigger;
      input 	edgen, pol, lirq, dirq;
      reg 	edge_irq, level_irq;
      begin
	 edge_irq  = pol ? (lirq & ~dirq) : (dirq & ~lirq);
	 level_irq = pol ? lirq : ~lirq;
	 trigger = edgen ? edge_irq : level_irq;
      end
   endfunction
   
   reg  [31:0] irq_event;
   integer     n;
   always @(posedge clk_i)
     for(n = 0; n < 32; n = n+1)
       irq_event[n] <=  trigger(edgen[n], pol[n], lirq[n], dirq[n]);

   // generate wishbone register bank writes
   wire        wb_acc = cyc_i & stb_i;                   // WISHBONE access
   wire        wb_wr  = wb_acc & we_i;                   // WISHBONE write access

   always @(posedge clk_i)
     if (rst_i)
       begin
          pol   <=  0;              // clear polarity register
          edgen <=  0;              // clear edge enable register
          mask  <=  0;              // mask all interrupts
       end
     else if(wb_wr)                               // wishbone write cycle??
       case (adr_i) // synopsys full_case parallel_case
         3'd0 : edgen <=  dat_i;        // EDGE-ENABLE register
         3'd1 : pol   <=  dat_i;        // POLARITY register
         3'd2 : mask  <=  dat_i;        // MASK register
         3'd3 : ;                       // PENDING register is a special case (see below)
	 3'd4 : ;                       // Priority encoded live (pending & ~mask)
       endcase

   // pending register is a special case
   always @(posedge clk_i)
     if (rst_i)
       pending <=  0;            // clear all pending interrupts
     else if ( wb_wr & (adr_i == 3'd3) )
       pending <=  (pending & ~dat_i) | irq_event;
     else
       pending <=  pending | irq_event;

   wire [31:0] live_enc;
   priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) );
   
   always @(posedge clk_i)
      case (adr_i) // synopsys full_case parallel_case
        3'd0 : dat_o <= edgen;
        3'd1 : dat_o <= pol;
        3'd2 : dat_o <= mask;
        3'd3 : dat_o <= pending;
	3'd4 : dat_o <= live_enc;
      endcase

   always @(posedge clk_i)
     ack_o <=  wb_acc & !ack_o;

   always @(posedge clk_i)
     if(rst_i)
       int_o <=  0;
     else
       int_o <=  |(pending & ~mask);
   
endmodule