module oc8051_ram (clk, rst, rd_addr, rd_data, wr_addr, wr_data, wr);
// clk          clock
// rd_addr      read addres
// rd_data      read data
// wr_addr      write addres
// wr_data      write data
// wr           write


input clk, wr, rst;
input [7:0] rd_addr, wr_addr, wr_data;
output [7:0] rd_data;

wire [7:0] dob;
RAMB4_S8_S8 ram1(.DOA(rd_data), .DOB(dob), .ADDRA({1'b0, rd_addr}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
                .RSTA(rst), .ADDRB({1'b0, wr_addr}), .DIB(wr_data), .ENB(1'b1), .CLKB(clk), .WEB(wr), .RSTB(rst));


endmodule