module ConstGen (ADL, ADH, Z_ADL0, Z_ADL1, Z_ADL2, Z_ADH0, Z_ADH17);

	inout [7:0] ADL;
	inout [7:0] ADH;
	input Z_ADL0;
	input Z_ADL1;
	input Z_ADL2;
	input Z_ADH0;
	input Z_ADH17;

	assign ADL[0] = Z_ADL0 ? 1'b0 : 1'bz;
	assign ADL[1] = Z_ADL1 ? 1'b0 : 1'bz;
	assign ADL[2] = Z_ADL2 ? 1'b0 : 1'bz;

	assign ADH[0] = Z_ADH0 ? 1'b0 : 1'bz;
	assign ADH[7:1] = Z_ADH17 ? 7'b0000000 : 7'bzzzzzzz;

endmodule // ConstGen