module  ogfx_reg_vram_addr (

// OUTPUTs
    vid_ram_addr_nxt_o,                     // Next Video-RAM address

// INPUTs
    mclk,                                   // Main system clock
    puc_rst,                                // Main system reset
    display_width_i,                        // Display width
    gfx_mode_1_bpp_i,                       // Graphic mode  1 bpp resolution
    gfx_mode_2_bpp_i,                       // Graphic mode  2 bpp resolution
    gfx_mode_4_bpp_i,                       // Graphic mode  4 bpp resolution
    gfx_mode_8_bpp_i,                       // Graphic mode  8 bpp resolution
    gfx_mode_16_bpp_i,                      // Graphic mode 16 bpp resolution
    vid_ram_addr_i,                         // Video-RAM address
    vid_ram_addr_init_i,                    // Video-RAM address initialization
    vid_ram_addr_step_i,                    // Video-RAM address step
    vid_ram_width_i,                        // Video-RAM width
    vid_ram_msk_mode_i,                     // Video-RAM Mask mode enable
    vid_ram_win_mode_i,                     // Video-RAM Windows mode enable
    vid_ram_win_x_swap_i,                   // Video-RAM X-Swap configuration
    vid_ram_win_y_swap_i,                   // Video-RAM Y-Swap configuration
    vid_ram_win_cl_swap_i                   // Video-RAM CL-Swap configuration
);

// OUTPUTs
//=========
output [`APIX_MSB:0] vid_ram_addr_nxt_o;    //  Next Video-RAM address

// INPUTs
//=========
input                mclk;                  // Main system clock
input                puc_rst;               // Main system reset
input  [`LPIX_MSB:0] display_width_i;       // Display width
input                gfx_mode_1_bpp_i;      // Graphic mode  1 bpp resolution
input                gfx_mode_2_bpp_i;      // Graphic mode  2 bpp resolution
input                gfx_mode_4_bpp_i;      // Graphic mode  4 bpp resolution
input                gfx_mode_8_bpp_i;      // Graphic mode  8 bpp resolution
input                gfx_mode_16_bpp_i;     // Graphic mode 16 bpp resolution
input  [`APIX_MSB:0] vid_ram_addr_i;        // Video-RAM address
input                vid_ram_addr_init_i;   // Video-RAM address initialization
input                vid_ram_addr_step_i;   // Video-RAM address step
input  [`LPIX_MSB:0] vid_ram_width_i;       // Video-RAM width
input                vid_ram_msk_mode_i;    // Video-RAM Mask mode enable
input                vid_ram_win_mode_i;    // Video-RAM Windows mode enable
input                vid_ram_win_x_swap_i;  // Video-RAM X-Swap configuration
input                vid_ram_win_y_swap_i;  // Video-RAM Y-Swap configuration
input                vid_ram_win_cl_swap_i; // Video-RAM CL-Swap configuration


//=============================================================================
// 1)  PARAMETER DECLARATION
//=============================================================================
reg  [`APIX_MSB:0] vid_ram_line_addr;
reg  [`LPIX_MSB:0] vid_ram_column_count;

// Detect when the current line refresh is done
wire               vid_ram_line_done   = vid_ram_addr_step_i & (vid_ram_column_count>=(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));

// Compute increment value depending on mask mode
wire [`APIX_MSB:0] plus_one_val        =  {`APIX_MSB+1{gfx_mode_1_bpp_i  & ~vid_ram_msk_mode_i}} & {         {{`VRAM_MSB{1'b0}}, 1'b1}, 4'b0000} |
                                          {`APIX_MSB+1{gfx_mode_2_bpp_i  & ~vid_ram_msk_mode_i}} & {1'b0,    {{`VRAM_MSB{1'b0}}, 1'b1}, 3'b000 } |
                                          {`APIX_MSB+1{gfx_mode_4_bpp_i  & ~vid_ram_msk_mode_i}} & {2'b00,   {{`VRAM_MSB{1'b0}}, 1'b1}, 2'b00  } |
                                          {`APIX_MSB+1{gfx_mode_8_bpp_i  & ~vid_ram_msk_mode_i}} & {3'b000,  {{`VRAM_MSB{1'b0}}, 1'b1}, 1'b0   } |
                                          {`APIX_MSB+1{gfx_mode_16_bpp_i |  vid_ram_msk_mode_i}} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1}         } ;

// Mux between initialization value and display width
wire   [`LPIX_MSB:0] vid_ram_width_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;

// Zero extension for LINT cleanup
wire [`APIX_MSB*3:0] vid_ram_width_norm  =  {{`APIX_MSB*3-`LPIX_MSB{1'b0}}, vid_ram_width_mux};

// Select base address for next calculation
wire   [`APIX_MSB:0] next_base_addr      =  (vid_ram_addr_init_i | ~vid_ram_line_done | ~vid_ram_win_mode_i) ? vid_ram_addr_i :
                                                                                                               vid_ram_line_addr  ;
// Compute next address
wire   [`APIX_MSB:0] next_addr           =   next_base_addr
                                           + (vid_ram_width_norm[`APIX_MSB:0] & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? (~vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                           - (vid_ram_width_norm[`APIX_MSB:0] & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? ( vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
                                           + (plus_one_val                    & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : (~vid_ram_win_mode_i & ~vid_ram_addr_init_i)}})
                                           - (plus_one_val                    & {`APIX_MSB+1{(~vid_ram_addr_init_i & vid_ram_win_mode_i) ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});

wire                 update_line_addr    =  (vid_ram_addr_init_i | vid_ram_line_done) & vid_ram_win_mode_i;
wire                 update_pixel_addr   =   update_line_addr    | vid_ram_addr_step_i;

// Start RAM address of currentely refreshed line
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)               vid_ram_line_addr  <=  {`APIX_MSB+1{1'b0}};
  else if (update_line_addr) vid_ram_line_addr  <=  next_addr;

// Current RAM address of the currentely refreshed pixel
wire [`APIX_MSB:0] vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;

// Count the pixel number in the current line
// (used to detec the end of a line)
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_init_i)  vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_line_done)    vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
  else if (vid_ram_addr_step_i)  vid_ram_column_count  <=  vid_ram_column_count + {{`LPIX_MSB+1-5{1'b0}}, plus_one_val[4:0]};


endmodule // ogfx_reg_vram_addr