module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_HOLD,
				   IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );

	input	BCLK;
	input	READ,DACC_OK;
	input	DC_ACC,DPTE_ACC,DC_MDONE;
	input	DRAM_WR;
	input	IC_READ,IACC_OK,DATA_HOLD;
	input	IC_ACC,IPTE_ACC,IC_MDONE;
	input	KOLLISION;
	
	output	reg [7:0]	STATSIGS;

	always @(posedge BCLK)
		begin
			STATSIGS[7] <= KOLLISION;						// 7 : from ICACHE : collisions
			STATSIGS[6] <= IPTE_ACC;						// 6 : Instruction PTE access
			STATSIGS[5] <= IC_ACC & IC_MDONE;				// 5 : Instruction Memory read
			STATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD;	// 4 : Instruction read , can be IO-Port too !
			STATSIGS[3] <= DRAM_WR;							// 3 : Data write
			STATSIGS[2] <= DPTE_ACC;						// 2 : Data PTE access
			STATSIGS[1] <= DC_ACC & DC_MDONE;				// 1 : Data Memory read
			STATSIGS[0] <= READ & DACC_OK;					// 0 : Data read , can be IO-Port too !
		end
		
endmodule