module MUX_ALU_B(ALU_B_Sel,RT,Ext,B);
//interface
	input [31:0] ALU_B_Sel;
	
	input [31:0] RT;
	input [31:0] Ext;
	
	output reg [31:0] B;
	
//select logic
	always @(*)
		begin
			B=RT;
			case(ALU_B_Sel)
				0:B=RT;
				1:B=Ext;
			endcase
		end

endmodule