module EvenOdd_2C07 (n_PCLK, PCLK, BLNK, H0_D, VPLA_8, VPLA_9, EvenOddOut);

	input n_PCLK;
	input PCLK;
	input BLNK;
	input H0_D;
	input VPLA_8;
	input VPLA_9;
	output EvenOddOut; 		// Don't mind the name, it's just historically that way. In fact, it's more like `Sprite_Workaround`.

	wire latch1_q;
	wire latch2_q;
	wire latch3_in;
	wire latch3_nq;
	wire tmp;

	dlatch latch1 (.d(VPLA_9), .en(n_PCLK), .q(latch1_q));
	dlatch latch2 (.d(VPLA_8), .en(n_PCLK), .q(latch2_q));
	dlatch latch3 (.d(latch3_in), .en(PCLK), .nq(latch3_nq));
	rsff FF_1 (.r(latch2_q), .s(latch1_q), .nq());

	nand (tmp, BLNK, latch3_nq);
	nor (EvenOddOut, ~H0_D, tmp, n_PCLK);

endmodule // EvenOdd_2C07