module lab11(reset,clk,out1,out10,row,column,light);
input reset,clk;

//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [7:0]row;
output [7:0]column;
output [2:0]light;

wire [6:0]out1;
wire [6:0]out10;
wire [7:0]row;
wire [7:0]column;
wire [2:0]light;
//

//logic counter neeed to declear as reg
reg [31:0]count;
reg [4:0]second;
reg safe;
//

displayNumber DISNUM (.in(second),.out10(out10),.out1(out1));
displayGraph DISGPH (.safe(safe),.row(row),.column(column),.count(count));
displayLight DISLIT (.in(second),.safe(safe),.light(light));

always@(posedge clk,negedge reset)
begin
    if(reset)
    begin
        count<=32'd0;
        second<=5'd13;
        safe<=1'b1;
    end
    else
    begin
        if(count==`TimeExpire)
        begin
            count<=32'd0;
            if(second==5'd0&&safe==1'b1)
            begin
                second=5'd7;
                safe=1'b0;
            end
            else if(second==5'd0&&safe==1'b0)
            begin
                second=5'd13;
                safe=1'b1;
            end
            else
            begin
                second=second-1'b1;
            end
        end
        else count<=count+32'd1;
    end
end
endmodule