module Z80Reg(
	input wire RESET,
	input wire [7:0]rstatus,	// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
	input wire M1,
	input wire [5:0]WE,			// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
	input wire CLK,
	input wire [15:0]ALU8OUT,	// CPU data out bus (output of alu8)
	input wire [7:0]DI,			// CPU data in bus
	output reg [7:0]DO,			// CPU data out bus
	input wire [15:0]ADDR,		// CPU addr bus
	input wire [7:0]CONST,
	output reg [7:0]ALU80,
	output reg [7:0]ALU81,
	output reg [15:0]ALU160,
	output wire[7:0]ALU161,
	input wire [7:0]ALU8FLAGS,			
	output wire [7:0]FLAGS,
	
	input wire [1:0]DO_SEL,		// select DO betwen ALU8OUT lo and th register
	input wire ALU160_sel,		// 0=REG_RSEL, 1=PC
	input wire [3:0]REG_WSEL,	// rdow:    	[3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x  ----- [0] = 0HI,1LO
	input wire [3:0]REG_RSEL,	// mux_rdor:   [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP   ----- [0] = 0HI, 1LO
	input wire DINW_SEL,			// select RAM write data between (0)ALU8OUT, and 1(DI)
	input wire XMASK,				// 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
	input wire [2:0]ALU16OP,	// ALU16OP
	input wire WAIT				// wait
	);
	
// latch registers
	reg [15:0]pc=0;				// program counter
	reg [15:0]sp;					// stack pointer
	reg [7:0]r;						// refresh
	reg [15:0]flg = 0;
	reg [7:0]th;					// temp high

// internal wires	
	wire [3:0]SELW;		// RAM W port sel
	wire [3:0]SELR;		// RAM R port sel
	reg [15:0]DIN;		// RAM W in data
	reg [15:0]mux_rdor;	// (3)A reversed mixed with TL, (4)I mixed with R (5)SP
	
//------------------------------------ RAM block registers ----------------------------------
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero

	reg [15:0] regs[13:0];
	always @(posedge CLK) begin : regs_block
		reg [3:0] i;
		if(WE[0] & !WAIT) regs[SELW][7:0]  <= DIN[7:0];
		if(WE[1] & !WAIT) regs[SELW][15:8] <= DIN[15:8];
		if(RESET) for(i=0; i<14; i=i+1'd1) regs[i] <= 0; // not really needed but added to prevent warning
	end

	wire [15:0] rdor = regs[SELR];
	wire [15:0] rdow = regs[SELW];

	wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
	wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
	always @(posedge CLK)
		if(!WAIT) begin
			if(WE[2]) th <= DI;
			if(WE[3]) sp <= ADDR1;
			if(WE[4]) pc <= ADDR1;
			if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; 
			else if(M1) r[6:0] <= r[6:0] + 1'd1;
			if(WE[5])
				if(rstatus[0]) flg[15:8] <= flgmux;
				else flg[7:0] <= flgmux;
		end
	
	assign ALU161 = th;
	assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
	
	always @* begin
		DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
		ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
		ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
		ALU160 = ALU160_sel ? pc : mux_rdor;
	
		case({REG_WSEL[3], DO_SEL})
			0:	DO = ALU80;
			1:	DO = th;
			2: DO = FLAGS;
			3: DO = ALU8OUT[7:0];
			4: DO = pc[15:8];
			5: DO = pc[7:0];
			6:	DO = sp[15:8];
			7: DO = sp[7:0];
		endcase
		case({ALU16OP == 4, REG_RSEL[3:0]})
			5'b01001, 5'b11001:								mux_rdor = {rdor[15:8], r};
			5'b01010, 5'b01011: 								mux_rdor = sp;
			5'b01100, 5'b01101, 5'b11100, 5'b11101:	mux_rdor = {8'b0, CONST};
			default:		mux_rdor = rdor;
		endcase 
	end
	
	RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
	RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));

endmodule