module map_bram (
    input             clk_i,
    input      [9:0] addr_i,
    output reg [7:0] data_o
);

reg [7:0] mem [0:511];

initial $readmemh("./tilemap.hex",mem);

always @(posedge clk_i) begin
    data_o <= mem[addr_i];
end

endmodule