module SMEMemoryMux (
	input		Select,
	
	input [9:0]		ReadAddressIn0,    // Expanded for Rel 0 on 6/18
	input [9:0]		ReadAddressIn1,    // Expanded for Rel 0 on 6/18
	output[9:0]		ReadAddressOut,    // Expanded for Rel 0 on 6/18
	
	input [9:0]		WriteAddressIn0,
	input [9:0]		WriteAddressIn1,
	output[9:0]		WriteAddressOut,
	
	input [8:0]		DataToMemoryIn0,
	input [8:0]		DataToMemoryIn1,
	output[8:0]		DataToMemoryOut,
	
	input [17:0]	DataFromMemoryIn0,
	input [17:0]	DataFromMemoryIn1,
	output[17:0]	DataFromMemoryOut,
	
	input			ReadEnableIn0,
	input			ReadEnableIn1,
	output			ReadEnableOut,
	
	input			WriteEnableIn0,
	input			WriteEnableIn1,
	output			WriteEnableOut,
	
	input			ReadClockIn0,
	input			ReadClockIn1,
	output			ReadClockOut	
	);
	
	assign ReadAddressOut = (Select) ? ReadAddressIn1 : ReadAddressIn0;
	assign WriteAddressOut = (Select) ? WriteAddressIn1 : WriteAddressIn0;
	assign DataToMemoryOut = (Select) ? DataToMemoryIn1 : DataToMemoryIn0;
	assign DataFromMemoryOut = (Select) ? DataFromMemoryIn1 : DataFromMemoryIn0;
	assign ReadEnableOut = (Select) ? ReadEnableIn1 : ReadEnableIn0;
	assign WriteEnableOut = (Select) ? WriteEnableIn1 : WriteEnableIn0;
	assign ReadClockOut = (Select) ? ReadClockIn1 : ReadClockIn0;

endmodule