module darksimv;

    reg CLK = 0;
    
    reg RES = 1;

    initial while(1) #(500e6/`BOARD_CK) CLK = !CLK; // clock generator w/ freq defined by config.vh

    integer i;

    initial
    begin
`ifdef __ICARUS__
        $dumpfile("darksocv.vcd");
        $dumpvars();

    `ifdef __REGDUMP__
        for(i=0;i!=`RLEN;i=i+1)
        begin
            $dumpvars(0,soc0.core0.REGS[i]);
        end
    `endif
`endif
        $display("reset (startup)");
        #1e3    RES = 0;            // wait 1us in reset state
        //#1000e3 RES = 1;            // run  1ms
        //$display("reset (restart)");
        //#1e3    RES = 0;            // wait 1us in reset state
        //#1000e3 $finish();          // run  1ms
    end

    wire TX;
    wire RX = 1;

`ifdef __SDRAM__

    // sdram sim model!

    wire        S_NWE,S_CLK;
    reg [15:0]  S_DBFF = 0;  
    wire [15:0] S_DB = S_NWE ? S_DBFF : 16'hzzzz;

    always@(posedge S_CLK)
    begin
        if(S_NWE==0) S_DBFF <= S_DB;
    end

`endif

    darksocv soc0
    (
        .XCLK(CLK),
        .XRES(|RES),
`ifdef __SDRAM__        
        .S_CLK(S_CLK),
        .S_NWE(S_NWE),
        .S_DB (S_DB),
`endif        
        .UART_RXD(RX),
        .UART_TXD(TX)
    );

endmodule