module i2s_sync_cell (
  input   wire     clk,
  input   wire     rst_n,
  input   wire     din,
  output  wire     dout
  );

  reg   sync1;
  reg   sync2;

  // synchroniser
  always @ (posedge clk or negedge rst_n)
    if (!rst_n)
      begin
       sync1  <= 1'b0;
       sync2  <= 1'b0;
      end
    else
      begin
        sync1 <= din;
        sync2 <= sync1;
      end
  
  assign dout = sync2;

endmodule  