module divider #(
    parameter SYSTEM_FREQ = 6250,
    parameter HZ = 8
) (
    input  clk,
    input  reset,
    output divider
);
  localparam CYCLES = SYSTEM_FREQ / HZ;
  reg [$clog2(CYCLES) -1:0] cnt;
  always @(posedge clk) begin
    if (reset) begin
      cnt <= 0;
    end else begin
      cnt <= cnt + 1;
      /* verilator lint_off WIDTH */
      if (cnt >= (CYCLES - 1)) begin
        cnt <= 0;
      end
      /* verilator lint_on WIDTH */
    end
  end
  assign divider = cnt == 0;
endmodule