module Standard_Cell_CLK_GATE(
Q, 
CK, 
EN, 
SE
);
   output Q;
   input CK;
   input EN;
   input SE;

wire	E;
reg	q_tmp;
assign E = SE | EN;

always @(E or CK)
begin 
    if(!CK)
	q_tmp = E;
end

assign Q = q_tmp & CK;


endmodule