module SRegBit (PHI2, S_SB, S_ADL, SB_S, S_S, SB_bit, ADL_bit, S_dbg, SS_dbg);

	input PHI2;
	input S_SB;
	input S_ADL;
	input SB_S;
	input S_S;
	inout SB_bit;
	inout ADL_bit;
	output S_dbg; 		// Not on a real chip
	output SS_dbg; 		// Not on a real chip

	wire d;
	assign d = SB_S ? SB_bit : (S_S ? out_latch_nq : 1'bz);

	wire in_latch_nq;
	wire out_latch_nq;
	dlatch in_latch (.d(d), .en(1'b1), .q(SS_dbg), .nq(in_latch_nq)); 		// Shadow Stack reg
	dlatch out_latch (.d(in_latch_nq), .en(PHI2), .nq(out_latch_nq)); 		// Stack reg
	assign S_dbg = out_latch_nq;

	assign SB_bit = S_SB ? out_latch_nq : 1'bz;
	assign ADL_bit = S_ADL ? out_latch_nq : 1'bz;

endmodule // SRegBit