module CLG2(x1, y1, x2, y2, c1,
            s1, s2, c3);

input x1, y1, x2, y2, c1;
wire p1, c2, p2, g1, g2;
output s1, s2, c3;

assign p1 = x1 ^ y1;
assign p2 = x2 ^ y2;
assign g1 = x1 & y1;
assign g2 = x2 & y2;

assign c2 = g1 | (p1 & c1);
assign c3 = g2 | (p2 & g1) | (p2 & p1 & c1);

assign s1 = c1 ^ p1;
assign s2 = c2 ^ p2;

endmodule