module ram_single_port (clk, we, addr, data_in, data_out);

   parameter DATA_WIDTH = 8;
   parameter ADDR_WIDTH = 5;
   parameter DEPTH = 2**ADDR_WIDTH;

   input clk, we;
   input [ADDR_WIDTH-1:0] addr;
   input [DATA_WIDTH-1:0] data_in;
   output [DATA_WIDTH-1:0] data_out;

   reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
  
   reg [ADDR_WIDTH-1:0] addr_reg;
   integer i;
   initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

   always @(posedge clk) begin
       addr_reg <= addr;
       if (we) 
           ram[addr] <= data_in;
   end

   assign data_out = ram[addr_reg];


/////  clk ___^^^___^^^___^^^___^^^___^^^___
//
//      we ___^^^^^^______^^^^^^^^^^^^______
//      di ___XXXXXX______YYYYYYZZZZZZ______
//    addr ___AAAAAA______BBBBBBCCCCCC______
//addr_reg _________AAAAAA______BBBBBBCCCCCC
//      do _________XXXXXX______YYYYYYZZZZZZ

endmodule