module aibcr3_latch (
	input wire E,
	input wire CDN,
	input wire D,
	output reg Q
);

wire latch_reset;
assign latch_reset = !CDN;

//cadence async_set_reset "latch_reset"
//synopsys async_set_reset "latch_reset"
always@(*) begin
	if (latch_reset) Q <= 0;
	else if (E) Q <= D;
end
endmodule