module butter_test();

   reg rst, CLOCK_50;
   reg [31:0] counter;
   reg        audio_input_ready;
   // DDS update signal for testing
   reg [31:0] dds_accum;
   // DDS LUT
   reg [31:0] sine_out;
   wire [31:0] my_out;

   // make reset
   initial begin
      counter = 32'b0;
      CLOCK_50 = 1'b0;
      audio_input_ready = 1'b0;
      dds_accum = 32'd0;
      sine_out = 32'h7fff_ffff;
      rst = 1'b0;
      #50
        rst = 1'b1;
      #100
        rst = 1'b0;
   end

   // make clock
   always begin
      #10
        CLOCK_50 = !CLOCK_50;
   end

   always begin
      #1000000
        sine_out = ~sine_out;
   end

   always begin
      #20813
        audio_input_ready = 1;
      #20
        audio_input_ready = 0;
   end

   // update phase accumulator
   // sync to audio data rate (48kHz) using audio_input_ready signal
   /*always @(posedge CLOCK_50) begin //CLOCK_50
    // Fout = (sample_rate)/(2^32)*(constant)
    // then Fout=48000/(2^32)*(44739242) = 500 Hz
    if (audio_input_ready) dds_accum <= dds_accum + 32'd44739242;
   end*/
   // DDS sine wave ROM
   //sync_rom sineTable(CLOCK_50, dds_accum[31:24], sine_out);

   //Filter: cutoff=0.145833
   IIR6_32bit_fixed filter(
                            .audio_out (my_out),
                            .audio_in (sine_out),
                            .scale (3'd3),
                            .b1 (32'h226C),
                            .b2 (32'hCE8B),
                            .b3 (32'h2045B),
                            .b4 (32'h2B07A),
                            .b5 (32'h2045B),
                            .b6 (32'hCE8B),
                            .b7 (32'h226C),
                            .a2 (32'h21DC9D38),
                            .a3 (32'hC2BABD8C),
                            .a4 (32'h3C58991F),
                            .a5 (32'hDDFDB62D),
                            .a6 (32'hA5FA11C),
                            .a7 (32'hFEAA19B2),
                            .clk(CLOCK_50),
                            .data_val(audio_input_ready),
                            .rst(rst),
                            .audio_out_val(audio_out_val)
                            ); //end filter

endmodule