module bsg_flow_counter
(
  clk_i,
  reset_i,
  v_i,
  ready_i,
  yumi_i,
  count_o
);

  output [6:0] count_o;
  input clk_i;
  input reset_i;
  input v_i;
  input ready_i;
  input yumi_i;
  wire [6:0] count_o;
  wire enque;

  bsg_counter_up_down_max_val_p64_init_val_p0_max_step_p1
  \gen_blk_0.counter 
  (
    .clk_i(clk_i),
    .reset_i(reset_i),
    .up_i(enque),
    .down_i(yumi_i),
    .count_o(count_o)
  );

  assign enque = v_i & ready_i;

endmodule