module pci_sync_module
(
					set_clk_in,
					delete_clk_in,
					reset_in,
					delete_set_out,
					block_set_out,
					delete_in
);

// system inputs from two clock domains
input	set_clk_in;
input	delete_clk_in;
input	reset_in;
// control outputs
output	delete_set_out;
output	block_set_out;
// control input
input	delete_in;

// internal signals
reg		del_bit;
wire	meta_del_bit;
reg		sync_del_bit;
reg		delayed_del_bit;
wire	meta_bckp_bit;
reg		sync_bckp_bit;
reg		delayed_bckp_bit;


// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
always@(posedge delete_clk_in or posedge reset_in)
begin
	if (reset_in)
		del_bit <= 1'b0;
	else
	begin
		if (!delayed_bckp_bit && sync_bckp_bit)
			del_bit <= 1'b0;
		else if (delete_in)
			del_bit <= 1'b1;
	end
end
assign	block_set_out = del_bit;

// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop	#(1, 0) delete_sync
(
    .data_in        (del_bit),
    .clk_out        (set_clk_in),
    .sync_data_out  (meta_del_bit),
    .async_reset    (reset_in)
) ;

// Final synchronization of del_bit signal to the set clock domain
always@(posedge set_clk_in or posedge reset_in)
begin
	if (reset_in)
		sync_del_bit <= 1'b0;
	else
		sync_del_bit <= meta_del_bit;
end

// Delayed sync_del_bit signal for one clock period pulse generation
always@(posedge set_clk_in or posedge reset_in)
begin
	if (reset_in)
		delayed_del_bit <= 1'b0;
	else
		delayed_del_bit <= sync_del_bit;
end

assign	delete_set_out = !delayed_del_bit && sync_del_bit;

// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop	#(1, 0) clear_delete_sync
(
    .data_in        (sync_del_bit),
    .clk_out        (delete_clk_in),
    .sync_data_out  (meta_bckp_bit),
    .async_reset    (reset_in)
) ;

// Final synchronization of sync_del_bit signal to the delete clock domain
always@(posedge delete_clk_in or posedge reset_in)
begin
	if (reset_in)
		sync_bckp_bit <= 1'b0;
	else
		sync_bckp_bit <= meta_bckp_bit;
end

// Delayed sync_bckp_bit signal for one clock period pulse generation
always@(posedge delete_clk_in or posedge reset_in)
begin
	if (reset_in)
		delayed_bckp_bit <= 1'b0;
	else
		delayed_bckp_bit <= sync_bckp_bit;
end

endmodule