module RT_M_MUX(RT_M_Sel,V2_M,RF_WD_W,RT_M);
//input
    input [31:0] RT_M_Sel;

    input [31:0] V2_M;
    input [31:0] RF_WD_W;

//output
    output reg [31:0] RT_M;

//logic
    parameter E=1,
              M=2,
              W=3;

    always @(*)
        begin
            RT_M=V2_M;
            case(RT_M_Sel)
                W:RT_M=RF_WD_W;
            endcase
        end

endmodule