module top
(
  clk_i,
  reset_i,
  v_i,
  ready_o,
  opA_i,
  signed_opA_i,
  opB_i,
  signed_opB_i,
  gets_high_part_i,
  v_o,
  result_o,
  yumi_i
);

  input [31:0] opA_i;
  input [31:0] opB_i;
  output [31:0] result_o;
  input clk_i;
  input reset_i;
  input v_i;
  input signed_opA_i;
  input signed_opB_i;
  input gets_high_part_i;
  input yumi_i;
  output ready_o;
  output v_o;

  bsg_imul_iterative
  wrapper
  (
    .opA_i(opA_i),
    .opB_i(opB_i),
    .result_o(result_o),
    .clk_i(clk_i),
    .reset_i(reset_i),
    .v_i(v_i),
    .signed_opA_i(signed_opA_i),
    .signed_opB_i(signed_opB_i),
    .gets_high_part_i(gets_high_part_i),
    .yumi_i(yumi_i),
    .ready_o(ready_o),
    .v_o(v_o)
  );


endmodule