module Alu
  (
   input wire [5:0]  alufn,
   input wire [31:0] a,
   input wire [31:0] b,

   output reg [31:0] alu,
   output wire 	     z,
   output wire 	     v,
   output wire 	     n
   );

   wire [31:0] 	     asRes, cmpRes, shftRes, boolRes, mulRes;

   AddSub as_inst_0(.alufn0(alufn[0]), .a(a), .b(b), .s(asRes), .z(z), .v(v), .n(n));
   CmpModule cmp_inst_0(.alufn(alufn[2:1]), .a(a), .b(b), .cmp(cmpRes));
   LogicModule log_inst_0(.alufn(alufn), .a(a), .b(b), .res(boolRes));
   ShifterModule shft_inst_0(.alufn(alufn[1:0]), .a(a), .b(b[4:0]), .res(shftRes));
   MultModule mult_inst_0(.a(a), .b(b), .res(mulRes));

   always @(*) begin
       #3
         casex (alufn)
           6'b00xx0x: 
             alu = asRes;
           6'b00xx1x: 
             alu = mulRes;
           6'b01xxxx: 
             alu = boolRes;
           6'b10xxxx: 
             alu = shftRes;
           6'b11xxxx: 
             alu = cmpRes;
           default:
             alu = 32'h00000000;
         endcase        
   end
endmodule