module aibcr3_dcc_dlyline64(
    input  wire b63,
    input  wire [63:0] bk,
    input  wire dlyin,
    output wire a63,
    output wire dlyout
);

wire VDD_val;
wire VSS_val;

assign VDD_val = 1'b1;
assign VSS_val = 1'b0;

aibcr3_dcc_dlyline64__w_sup XDUT (
    .b63( b63 ),
    .bk( bk ),
    .dlyin( dlyin ),
    .a63( a63 ),
    .dlyout( dlyout ),
    .VDD( VDD_val ),
    .VSS( VSS_val )
);

endmodule