module tb_data_stream;

reg        tx_symbol_clk;
reg        tx_align_train;       
reg        tx_clock_train;       
reg        tx_link_established;
reg f;

wire [72:0] msa_merged_data;
wire        test_signal_ready;
wire  [2:0] stream_channel_count;

initial begin
  tx_symbol_clk       = 1'b0;
  tx_align_train      = 1'b0;
  tx_clock_train      = 1'b0;
  tx_link_established = 1'b1;
end

always begin
  #4    // Should be 135MHz, but 125 is close enough for simulation
  tx_symbol_clk = ~tx_symbol_clk;
  #4    // Should be 135MHz, but 125 is close enough for simulation
  tx_symbol_clk = ~tx_symbol_clk;
  $display("%b %b", 
         msa_merged_data[8:0],  msa_merged_data[26:18]
  );

  $display("%b %b", 
         msa_merged_data[17:9], msa_merged_data[35:27]
  );
end

///////////////////////////////////////////////////
// Video pipeline
/////////////////////////////////////////%/////////
test_source i_test_source(
        .clk                  (tx_symbol_clk),
        .stream_channel_count (stream_channel_count),
        .ready                (test_signal_ready),
        .data                 (msa_merged_data)
    );

wire [79:0] tx_symbols;
main_stream_processing i_main_stream_processing(
        .symbol_clk          (tx_symbol_clk),
        .tx_link_established (tx_link_established),
        .source_ready        (test_signal_ready),
        .tx_clock_train      (tx_clock_train),
        .tx_align_train      (tx_align_train),
        .in_data             (msa_merged_data),
        .tx_symbols          (tx_symbols)
    );

endmodule