module nt_packet_counter (
  // clock and resets
  input wire clk,
  input wire rstn,
  input wire rst_sw,

  // AXI4-Stream signals
  input wire axis_tvalid,
  input wire axis_tready,
  input wire axis_tlast,

  output reg [31:0]    cntr_o
);

  always @(posedge clk) begin
    if (~rstn | rst_sw) begin
      cntr_o <= 32'b0;
    end else begin
      if (axis_tvalid & axis_tready & axis_tlast) begin
        // packet transfer completed, increment counter
        cntr_o <= cntr_o + 1;
      end else begin
        cntr_o <= cntr_o;
      end
    end
  end

endmodule