module spi_slave(
    (* clkbuf_inhibit *) input i_sclk,
    input i_ss,
    input i_mosi,
    input i_echo,
    input [3:0] i_nib_send,
    output o_miso,
    output reg o_rec_nib_ready,
    output reg [3:0] o_nib_rec
);


reg [3:0] tx_shift_reg;
reg [3:0] rx_shift_reg;
reg [1:0] bit_cnt;


always @(posedge i_sclk) begin
    if (i_ss) begin
        rx_shift_reg <= 0;
    end else begin    
        rx_shift_reg <= {rx_shift_reg[2:0], i_mosi};
    end
end

always @(posedge i_sclk) begin
    if (i_ss) begin
        bit_cnt <= 2'b11;
    end
    else begin
        bit_cnt <= bit_cnt + 1'b1;
    end
end 


always @(negedge i_sclk) 
begin
    if (i_ss) begin
        o_rec_nib_ready <= 0;
        o_nib_rec <= 0;
        tx_shift_reg <= 0;
    end
    else if (bit_cnt == 2'b11) begin
        o_rec_nib_ready <= 1;
        o_nib_rec <= rx_shift_reg;
        if (i_echo) begin
            tx_shift_reg <= rx_shift_reg;
        end else begin
            tx_shift_reg <= i_nib_send;
        end
    end
    else begin
        o_rec_nib_ready <= 0;
        tx_shift_reg <= {tx_shift_reg[2:0], 1'b0};
    end
end

assign o_miso = tx_shift_reg[3];

endmodule