module aibcr3_svt16_scdffsdn_cust ( Q, scQ, CK, 
     D, SDN, SE, SI );

output  Q, scQ;

input  SDN, CK, D, SE, SI;

wire Q, net023, se_n, SI, D;
reg  scQ;

assign se_n = !SE;
assign Q = scQ;
assign net023 = se_n ? D : SI;

always@(posedge CK or negedge SDN) begin
        if (!SDN) begin
                scQ <= 1'b1;
        end
        else begin
                scQ <= net023;
        end
end

endmodule