module debounce(
	input clk,
	input in,
	output out
);

	wire slow_clk_en;
	wire Q1,Q2,Q2_bar,Q0;

	clock_enable u1(clk,slow_clk_en);
	my_dff_en d0(clk,slow_clk_en,in,Q0);
	my_dff_en d1(clk,slow_clk_en,Q0,Q1);
	my_dff_en d2(clk,slow_clk_en,Q1,Q2);
	
	assign Q2_bar = ~Q2;
	assign out = Q1 & Q2_bar;
endmodule