module cxapbasyncbridge_cdc_corrupt_gry (
  clk, 
  resetn, 
  sync,
  d_async,
  q_async
  );

  parameter WIDTH = 1;
  
  // ------------------------------------------------------
  // port declaration
  // ------------------------------------------------------
  input               clk; 
  input               resetn; 
  input               sync;
  input  [WIDTH-1:0]  d_async;
  output [WIDTH-1:0]  q_async;

  // -------------------------------------------
  // reg/wire declarations
  // ------------------------------------------------------

`ifdef ARM_CDC_CHECK

  reg      [WIDTH-1:0]  d_latch;
  reg      [WIDTH-1:0]  out_async;
  reg      [WIDTH-1:0]  corrupt;
  wire     [WIDTH-1:0]  change_vector;
  wire                  change;

  integer            i;

  //Bypass when in sync mode
  assign q_async = (sync) ? d_async : out_async;

  //Latch to detect changes in d_async
  always @(d_async)
     d_latch <= d_async; 

  //Create change vector (single delta cycle)
  assign change_vector = (d_async ^ d_latch);

  //Create a change pulse (single delta cycle)
  assign change = |change_vector;
  
  //Corrupt bits 
  always @(posedge clk or posedge change)
    begin 
       if (change) begin
          corrupt <= change_vector;
       end else begin
          corrupt <= {WIDTH{1'b0}};
       end
    end

  always @(corrupt or d_async)
    for (i = 0; i < WIDTH; i=i+1) begin
       out_async[i] = corrupt[i] ? 1'bz : d_async[i];
    end   
  
`else

  assign q_async = d_async;

`endif
  
endmodule