module  main_stream_processing (
		input         symbol_clk,
        input         tx_link_established,
        input         source_ready,
        input         tx_clock_train,
        input         tx_align_train,
        input  [72:0] in_data,
        output [79:0] tx_symbols
  );

wire [71:0] signal_data;
wire [71:0] sr_inserted_data;
wire [71:0] scrambled_data;
wire [79:0] before_skew;
wire [79:0] final_data;
 
localparam [7:0] delay_index = 8'b11100100;

/////////////////////////////////////////////////////////
// Flick between the idle pattern and a valid data stream
// at the time when the in_data's high bit is set
/////////////////////////////////////////////////////////
idle_pattern_inserter i_idle_pattern_inserter( 
		.clk              (symbol_clk),
		.channel_ready    (tx_link_established),
		.source_ready     (source_ready),
		
		.in_data          (in_data),
		.out_data         (signal_data)
    );

/////////////////////////////////////////////////////////
// Change the 512th Blank Start (BS) symbol into a 
// Scrambler Reset (SR) symbol
/////////////////////////////////////////////////////////
scrambler_reset_inserter i_scrambler_reset_inserter( 
		.clk       (symbol_clk),
		.in_data   (signal_data),
		.out_data  (sr_inserted_data)
	);

/////////////////////////////////////////////////////////
// Now scramble the data stream - only scrambles the data
// symbols, the K symbols go through unscrambled.
/////////////////////////////////////////////////////////
scrambler_all_channels i_scrambler( 
		.clk        (symbol_clk),
		.bypass0    (1'b0),
		.bypass1    (1'b0),
		.in_data    (sr_inserted_data),
		.out_data   (scrambled_data)
	);

/////////////////////////////////////////////////////////
// This allows the controller to send the two training 
// patterns, allowing the link drive levels to be set up
/////////////////////////////////////////////////////////
insert_training_pattern i_insert_training_pattern(
        .clk               (symbol_clk),
        .clock_train       (tx_clock_train),
        .align_train       (tx_align_train), 
        ///////////////////////////////////////////////////////
        // Adds one bit per symbol - the force_neg parity flag         
        // This takes the 72-bit wide data word to 80 bits.
        ///////////////////////////////////////////////////////
        .in_data           (scrambled_data),
        .out_data          (before_skew)
    );

/////////////////////////////////////////////////////////
// The last step is to skew the data channels (zero cycles
// cycles for channel zero, two cycle for channel one, 
// four for channel two and six for channel three.
/////////////////////////////////////////////////////////
skew_channels i_skew_channels(
        .clk               (symbol_clk),
        .in_data           (before_skew),
        .out_data          (tx_symbols)
    );

endmodule