module FIFO_TOP ( W_CLK, R_CLK, W_rst_n, R_rst_n, W_inc, R_inc, W_Data, Full, 
        Empty, R_Data );
  input [7:0] W_Data;
  output [7:0] R_Data;
  input W_CLK, R_CLK, W_rst_n, R_rst_n, W_inc, R_inc;
  output Full, Empty;
  wire   n14, n15, n16, n17, n18, n19, n20, n21, _0_net_, n1, n2, n6, n12, n13
;
  wire   [4:0] Wq2_rptr;
  wire   [4:0] W_ptr;
  wire   [3:0] W_Addr;
  wire   [4:0] Rq2_wptr;
  wire   [4:0] R_ptr;
  wire   [3:0] R_Addr;

  FIFO_Write_Pointer FIFO_Write_Pointer_F1 ( .W_CLK(W_CLK), .W_rst_n(W_rst_n), 
        .W_inc(W_inc), .Wq2_rptr(Wq2_rptr), .W_Full(Full), .W_ptr(W_ptr), 
        .W_Addr(W_Addr) );
  FIFO_R_Pointer FIFO_R_Pointer_F2 ( .R_CLK(R_CLK), .R_rst_n(R_rst_n), .R_inc(
        R_inc), .Rq2_wptr(Rq2_wptr), .R_empty(Empty), .R_ptr(R_ptr), .R_Addr(
        R_Addr) );
  ASYNC_FIFO_RAM ASYNC_FIFO_RAM_F3 ( .W_CLK(W_CLK), .W_CLK_en(_0_net_), 
        .W_Data(W_Data), .W_Addr(W_Addr), .R_Addr({R_Addr[3:2], n13, n12}), 
        .R_Data({n14, n15, n16, n17, n18, n19, n20, n21}) );
  Sync_R2W Sync_R2W_F4 ( .W_CLK(W_CLK), .W_rst_n(W_rst_n), .R_ptr(R_ptr), 
        .Wq2_rptr(Wq2_rptr) );
  Sync_W2R Sync_W2R_F5 ( .R_CLK(R_CLK), .R_rst_n(R_rst_n), .W_ptr(W_ptr), 
        .Rq2_wptr(Rq2_wptr) );
  CLKBUFX32M U2 ( .A(n14), .Y(R_Data[7]) );
  CLKINVX2M U3 ( .A(n17), .Y(n6) );
  CLKBUFX32M U4 ( .A(R_Addr[1]), .Y(n13) );
  CLKBUFX32M U5 ( .A(R_Addr[0]), .Y(n12) );
  CLKINVX32M U6 ( .A(n1), .Y(_0_net_) );
  NAND2X12M U7 ( .A(W_inc), .B(n2), .Y(n1) );
  CLKINVX40M U8 ( .A(Full), .Y(n2) );
  CLKBUFX32M U9 ( .A(n15), .Y(R_Data[6]) );
  CLKINVX32M U10 ( .A(n6), .Y(R_Data[4]) );
  CLKBUFX32M U11 ( .A(n21), .Y(R_Data[0]) );
  CLKBUFX32M U12 ( .A(n19), .Y(R_Data[2]) );
  CLKBUFX32M U13 ( .A(n16), .Y(R_Data[5]) );
  CLKBUFX32M U14 ( .A(n20), .Y(R_Data[1]) );
  CLKBUFX32M U15 ( .A(n18), .Y(R_Data[3]) );
endmodule