module ShifterModule
  (
   input [1:0] 	       alufn,
   input signed [31:0] a,
   input signed [4:0]  b,

   output reg [31:0]   res
   );

   always @(alufn[1:0], a, b[4:0]) begin
       case (alufn[1:0])
         2'b00: 
           res = a << b[4:0];
         2'b01: 
           res = a >> b[4:0];
         2'b10: 
           res = a;
         2'b11: 
           res = a >>> b[4:0];
       endcase // case (alufn[1:0])
   end // always @ (alufn[1:0], a, b[4:0])
   
endmodule