module dual_port_ram_1k (
  input clk,
  input wen,
  input ren,
  input [6:0] waddr,
  input [6:0] raddr,
  input [7:0] din,
  output [7:0] dout
);

    dual_port_sram_1kb memory_0 (
      .wclk    (clk),
      .wen    (wen),
      .waddr    (waddr),
      .data_in  (din),
      .rclk    (clk),
      .ren    (ren),
      .raddr    (raddr),
      .data_out    (dout) );

endmodule