module pr_region_default_sysid_qsys_0 (
		input  wire        clock,    //           clk.clk
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address,  //              .address
		input  wire        reset_n   //         reset.reset_n
	);

	altera_avalon_sysid_qsys #(
		.ID_VALUE  (-87110914),
		.TIMESTAMP (0)
	) sysid_qsys_0 (
		.clock    (clock),    //   input,   width = 1,           clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,         reset.reset_n
		.readdata (readdata), //  output,  width = 32, control_slave.readdata
		.address  (address)   //   input,   width = 1,              .address
	);

endmodule