module c_BIN_ZOOK_DLATCH (
     input [0:0] in_0,
     input [0:0] in_1,
     output [0:0] out_0
);

wire net_0 = in_0;
wire net_1 = in_1;

wire net_2;
wire net_3 = net_2;

assign out_0 = net_3;

f_Z00K00KKK LogicGate_0 (
.in_2(net_0),
.in_0(net_2),
.in_1(net_1),
.out_0(net_2)
);

endmodule