module cr_lsu_randclk(
  randclk_dp_size_buf_mod_en_w5
);

// &Ports; @25
output       randclk_dp_size_buf_mod_en_w5; 

// &Regs; @26

// &Wires; @27
wire         randclk_dp_size_buf_mod_en_w5; 


// &Force("input","seu_lsu_randclk_mod_en"); @31
// &Force("bus","seu_lsu_randclk_mod_en",31,0); @32
//assign randclk_ctrl_req_mod_en_w2 = 1'b0;

assign randclk_dp_size_buf_mod_en_w5 = 1'b0;


// &ModuleEnd; @76
endmodule