module mf_ddio_bidir_12 (
	datain_h,
	datain_l,
	inclock,
	oe,
	outclock,
	dataout_h,
	dataout_l,
	padio);

	input	[11:0]  datain_h;
	input	[11:0]  datain_l;
	input	  inclock;
	input	  oe;
	input	  outclock;
	output	[11:0]  dataout_h;
	output	[11:0]  dataout_l;
	inout	[11:0]  padio;

	wire [11:0] sub_wire0;
	wire [11:0] sub_wire1;
	wire [11:0] dataout_h = sub_wire0[11:0];
	wire [11:0] dataout_l = sub_wire1[11:0];

	altddio_bidir	ALTDDIO_BIDIR_component (
				.datain_h (datain_h),
				.datain_l (datain_l),
				.inclock (inclock),
				.oe (oe),
				.outclock (outclock),
				.padio (padio),
				.dataout_h (sub_wire0),
				.dataout_l (sub_wire1),
				.aclr (1'b0),
				.aset (1'b0),
				.combout (),
				.dqsundelayedout (),
				.inclocken (1'b1),
				.oe_out (),
				.outclocken (1'b1),
				.sclr (1'b0),
				.sset (1'b0));
	defparam
		ALTDDIO_BIDIR_component.extend_oe_disable = "OFF",
		ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF",
		ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V",
		ALTDDIO_BIDIR_component.invert_output = "OFF",
		ALTDDIO_BIDIR_component.lpm_hint = "UNUSED",
		ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir",
		ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED",
		ALTDDIO_BIDIR_component.power_up_high = "OFF",
		ALTDDIO_BIDIR_component.width = 12;


endmodule