module dummy_proc
        #(
            parameter   DATA_WIDTH = 16
        )
        (
            input   wire                        reset,
            input   wire                        clk,
            
            input   wire    [DATA_WIDTH-1:0]    s_data,
            input   wire                        s_valid,
            output  wire                        s_ready,
            
            output  wire    [DATA_WIDTH-1:0]    m_data,
            output  wire                        m_valid,
            input   wire                        m_ready
        );
    
    reg     [1:0]   reg_busy = 0;
    always @(posedge clk) begin
//      reg_busy <= {$random()};
        reg_busy <= reg_busy + 1;
    end
    wire            busy = (reg_busy != 0);
    
    assign m_data  = s_data;
    assign m_valid = s_valid && !busy;
    assign s_ready = m_ready && !busy;
    
endmodule