module aib_dcc_dlyline64_aib_dlycell_no_flop_3__w_sup(
    input  wire bk,
    input  wire ci_p,
    input  wire in_p,
    output wire co_p,
    output wire out_p,
    inout  wire VDD,
    inout  wire VSS
);

wire bk1;
wire bk_mid;

aib_dcc_dlyline64_inv_1__w_sup XBKInv0 (
    .in( bk ),
    .out( bk_mid ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_inv_1__w_sup XBKInv1 (
    .in( bk_mid ),
    .out( bk1 ),
    .VDD( VDD ),
    .VSS( VSS )
);

aib_dcc_dlyline64_aib_dlycell_core_1__w_sup XCore (
    .bk1( bk1 ),
    .ci_p( ci_p ),
    .in_p( in_p ),
    .co_p( co_p ),
    .out_p( out_p ),
    .VDD( VDD ),
    .VSS( VSS )
);

endmodule