module assert_impl (clk, reset_, antedecent, consequent);
    parameter msg = "assert_impl_msg";
    input clk;
    input reset_;
    input antedecent;
    input consequent;
    always @(posedge clk) begin
        if(reset_ === 1) begin
            if(antedecent && !consequent) begin
                $display("%c[1;31m",27);
                $display("%s %m",msg);
                $display("%c[0m",27);
                $finish;
            end
        end
    end
endmodule