module MUX_RF_WD(RF_WD_Sel,AO,RD,PC8,HI,LO,CP0_RD,RF_WD);
//interface
	input [31:0] RF_WD_Sel;

	input [31:0] AO;
	input [31:0] RD;
	input [31:0] PC8;
	input [31:0] HI;
	input [31:0] LO;
	input [31:0] CP0_RD;

//select logic
	output reg [31:0] RF_WD;

	always @(*)
		begin
			RF_WD=AO;
			case(RF_WD_Sel)
				0:RF_WD=AO;		//ALU.RST
				1:RF_WD=RD;		//DM.RD
				2:RF_WD=PC8;	//PC8
				3:RF_WD=HI;		//HI
				4:RF_WD=LO;		//LO
				5:RF_WD=CP0_RD;	//CP0.RD
			endcase
		end

endmodule