module FILTCMP ( DRAMSZ, RADR, DRAM_A, ADR_EQU, TAGDAT );

	input	 [2:0]	DRAMSZ;
	input	[28:4]	RADR,DRAM_A;
	
	output			ADR_EQU;
	output reg	[28:12]	TAGDAT;

	reg	   [28:23]	adram;
	
	always @(DRAMSZ or RADR)
		casex (DRAMSZ)
		  3'b000 : TAGDAT = {6'd0,RADR[22:12]};	//   8 MB
		  3'b001 : TAGDAT = {5'd0,RADR[23:12]};	//  16 MB
		  3'b010 : TAGDAT = {4'd0,RADR[24:12]};	//  32 MB
		  3'b011 : TAGDAT = {3'd0,RADR[25:12]};	//  64 MB
		  3'b100 : TAGDAT = {2'd0,RADR[26:12]};	// 128 MB
		  3'b101 : TAGDAT = {1'b0,RADR[27:12]};	// 256 MB
		  3'b11x : TAGDAT =       RADR[28:12] ;	// 512 MB
		endcase
		
	always @(DRAMSZ or DRAM_A)	// The address comparator is only used in the data cache.
		casex (DRAMSZ)
		  3'b000 : adram =  6'd0;					//   8 MB
		  3'b001 : adram = {5'd0,DRAM_A[23]};   	//  16 MB
		  3'b010 : adram = {4'd0,DRAM_A[24:23]};	//  32 MB
		  3'b011 : adram = {3'd0,DRAM_A[25:23]};	//  64 MB
		  3'b100 : adram = {2'd0,DRAM_A[26:23]};	// 128 MB
		  3'b101 : adram = {1'd0,DRAM_A[27:23]};	// 256 MB
		  3'b11x : adram =       DRAM_A[28:23] ;	// 512 MB
		endcase

	assign ADR_EQU = {TAGDAT,RADR[11:4]} == {adram,DRAM_A[22:4]};

endmodule