module data_forwarding
   (
   input  wire        clk_i,
   input  wire        bist_enable_i,
   input  wire        y_select_i,
   input  wire [39:0] rddata_i,
   input  wire [39:0] bist_rddata_i,
   output wire [39:0] bist_rddata_o
    );


   reg 		      use_own_data;

   always @(posedge clk_i) begin
      use_own_data <= (bist_enable_i == 1'b1) && y_select_i;
   end
   
   assign bist_rddata_o = (use_own_data)? rddata_i : bist_rddata_i;

endmodule //data_forwarding