module ram_16x1k_sp (
  clka,
  ena,
  wea,
  addra,
  dina,
  douta
);

input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;

//============
// RAM
//============

ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (

// OUTPUTs
    .ram_dout     ( douta),      // RAM data output

// INPUTs
    .ram_addr     ( addra),      // RAM address
    .ram_cen      (~ena),        // RAM chip enable (low active)
    .ram_clk      ( clka),       // RAM clock
    .ram_din      ( dina),       // RAM data input
    .ram_wen      (~wea)         // RAM write enable (low active)
);


endmodule // ram_16x1k_sp