module my_uart_tx
(
	input			clk,
	input			rst_n,
	input	[7:0]	rx_data,
	input			rx_int,
	output			uart_tx,
	input			clk_bps,
	output			bps_start
);

//---------------------------------------------------------
reg 	rx_int0,rx_int1,rx_int2;	//rx_intÐÅºÅ¼Ä´æÆ÷£¬²¶×½ÏÂ½µÑØÂË²¨ÓÃ
wire 	neg_rx_int;					//rx_intÏÂ½µÑØ±êÖ¾Î»

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
    begin
		rx_int0 <= 1'b0;
		rx_int1 <= 1'b0;
		rx_int2 <= 1'b0;
	end
	else 
    begin
		rx_int0 <= rx_int;
		rx_int1 <= rx_int0;
		rx_int2 <= rx_int1;
	end

assign neg_rx_int =  ~rx_int1 & rx_int2;	//²¶×½µ½ÏÂ½µÑØºó£¬neg_rx_intÀ­¸ß±£³ÖÒ»¸öÖ÷Ê±ÖÓÖÜÆÚ

//---------------------------------------------------------
reg	[7:0] 	tx_data;		//´ý·¢ËÍÊý¾ÝµÄ¼Ä´æÆ÷
reg 		bps_start_r;
reg 		tx_en;			//·¢ËÍÊý¾ÝÊ¹ÄÜÐÅºÅ£¬¸ßÓÐÐ§
reg	[3:0] 	num;

always @ (posedge clk or negedge rst_n) 
	if(!rst_n) 
    begin
		bps_start_r <= 1'bz;
		tx_en 		<= 1'b0;
		tx_data 	<= 8'd0;
	end
	else if(neg_rx_int) 
    begin		                    //½ÓÊÕÊý¾ÝÍê±Ï£¬×¼±¸°Ñ½ÓÊÕµ½µÄÊý¾Ý·¢»ØÈ¥
		bps_start_r <= 1'b1;
		tx_data 	<= rx_data;		//°Ñ½ÓÊÕµ½µÄÊý¾Ý´æÈë·¢ËÍÊý¾Ý¼Ä´æÆ÷
		tx_en 		<= 1'b1;		//½øÈë·¢ËÍÊý¾Ý×´Ì¬ÖÐ
	end
	else if(num == 4'd10) 
    begin		                    //Êý¾Ý·¢ËÍÍê³É£¬¸´Î»
		bps_start_r <= 1'b0;
		tx_en		<= 1'b0;
	end

assign bps_start = bps_start_r;

//---------------------------------------------------------
reg uart_tx_r;

always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
    begin
		num 		<= 4'd0;
		uart_tx_r 	<= 1'b1;
	end
	else if(tx_en) 
    begin
		if(clk_bps)	
        begin
			num <= num+1'b1;
			case (num)
				4'd0: uart_tx_r <= 1'b0; 		//·¢ËÍÆðÊ¼Î»
				4'd1: uart_tx_r <= tx_data[0];	//·¢ËÍbit0
				4'd2: uart_tx_r <= tx_data[1];	//·¢ËÍbit1
				4'd3: uart_tx_r <= tx_data[2];	//·¢ËÍbit2
				4'd4: uart_tx_r <= tx_data[3];	//·¢ËÍbit3
				4'd5: uart_tx_r <= tx_data[4];	//·¢ËÍbit4
				4'd6: uart_tx_r <= tx_data[5];	//·¢ËÍbit5
				4'd7: uart_tx_r <= tx_data[6];	//·¢ËÍbit6
				4'd8: uart_tx_r <= tx_data[7];	//·¢ËÍbit7
				4'd9: uart_tx_r <= 1'b1;		//·¢ËÍ½áÊøÎ»
			 	default: uart_tx_r <= 1'b1;
			endcase
		end
		else if(num == 4'd10)
                num <= 4'd0;		//¸´Î»
	end

assign uart_tx = uart_tx_r;

endmodule