module single_port_ram_lattice #(parameter ADDR_WIDTH = 14, DATA_WIDTH = 16) (
            input  wire [ADDR_WIDTH - 1 : 0]         addr,
            input  wire [DATA_WIDTH - 1 : 0]         din,
            input  wire [DATA_WIDTH / 8 - 1 : 0]     write_en, 
            input  wire                              clk,
            output wire [DATA_WIDTH - 1 : 0]         dout
);

     single_port_ram_lattice_16Kx16 one_blk (
                .addr       (addr),
                .din        (din),
                .write_en   (write_en),
                .clk        (clk),
                .dout       (dout));
                
endmodule