module CKLNQD12 (
  TE
 ,E
 ,CP
 ,Q
 );
input TE ;
input E ;
input CP ;
output Q ;
reg qd;
always @(negedge CP)
    qd <= TE | E;
assign Q = CP & qd;
//PREICG_X1N_A7P5PP60TR_C8 uicg(.E (E), .CK (CP), .SE (TE), .ECK (Q));
endmodule