module aq_dtu_cdc_lvl(
  clk,
  dst_lvl,
  rst_n,
  src_lvl
);

// &Ports; @21
input        clk;    
input        rst_n;  
input        src_lvl; 
output       dst_lvl; 

// &Regs; @22
reg          sync1;  
reg          sync2;  
reg          sync3;  

// &Wires; @23
wire         clk;    
wire         dst_lvl; 
wire         rst_n;  
wire         src_lvl; 


always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    begin
      sync1 <= 1'b0;
      sync2 <= 1'b0;
      sync3 <= 1'b0;
    end
  else 
    begin
      sync1 <= src_lvl;
      sync2 <= sync1;  
      sync3 <= sync2;
    end
end
assign dst_lvl = sync3;

// &ModuleEnd; @42
endmodule