module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
    input                   clock,
    input        [DWIDTH:0] data /*verilator public*/,
    input        [AWIDTH:0] rdaddress /*verilator public*/,
    input        [AWIDTH:0] wraddress /*verilator public*/,
    input                   wren /*verilator public*/,
    output logic [DWIDTH:0] q /*verilator public*/
);

(* max_depth = 1024 *) (* ramstyle = "no_rw_check" *) logic [DWIDTH:0] ram[0:NUMWORDS-1];

always_ff@(posedge clock) begin
    if(wren) ram[wraddress] <= data;
    q <= ram[rdaddress];
end

endmodule