module Max2AudioDac(clk, mute, din, bclk, wclk, lout, rout);

	output [23:0] lout;
	output [23:0] rout;
	
	input clk;
	input din;
	input bclk;
	input wclk;
	input mute;
	
	reg [23:0] leftReg;
	reg [23:0] rightReg;
	reg [0:23] shift;
	reg [1:0]  bclkState;
	reg [4:0]  counter;
	reg wsd = 0;
	reg wsdEdge = 0;
	
	wire bclkRise = (bclkState == 2'b01);
	wire bclkFall = (bclkState == 2'b10);
	wire wsp = wsd ^ wsdEdge;
	
	assign lout = leftReg;
	assign rout = rightReg;
	
	initial leftReg = 0;
	initial rightReg = 0;
	
	always @(posedge clk)
	begin
		bclkState <= {bclkState, bclk};
	end
	 
	always @(posedge clk)
	begin
		if (bclkRise)
		begin
			wsd <= wclk;
		end
	end

	always @(posedge clk)
	begin
		if (bclkRise)
		begin
			wsdEdge <= wsd;
		end
	end
  
	always @(posedge clk)
	begin
		if (bclkFall)
		begin
			if (wsp)
			begin
				counter <= 0;
			end
			else if (counter < 24)
			begin
				counter <= counter + 1;
			end
		end
	end
  
	always @(posedge clk)
	begin
		if (bclkRise)
		begin
			if (wsp)
			begin
				shift <= 0;
			end
			
			if (counter < 24)
			begin
				shift[counter] <= din;
			end
		end
	end

	always @(posedge clk)
	begin
		if (mute)
		begin
			leftReg <= 0;
		end
		else
		begin
			if (bclkRise)
			begin
				if (wsd && wsp)
				begin
					leftReg <= {~shift[0], shift[1:23]};
				end
			end
		end
	end

	always @(posedge clk)
	begin
		if (mute)
		begin
			rightReg <= 0;
		end
		else
		begin
			if (bclkRise)
			begin
				if (!wsd && wsp)
				begin
					rightReg <= {~shift[0], shift[1:23]};
				end
			end
		end
	end
			
endmodule