module reqRst (req,rst,fin);
input req,rst;
output wire fin;

reg reqBuf=1'b0;
reg rstBuf=1'b1;
assign fin=reqBuf&rstBuf;

always@(posedge req or posedge fin) begin
    if(fin) reqBuf<=1'b0;
    else reqBuf<=1'b1;
end

always@(posedge rst or posedge fin) begin
    if(fin) rstBuf<=1'b0;
    else rstBuf<=1'b1;
end

endmodule