module cmsdk_ahb_to_apb_async_syn (
// --------------------------------------------------------------------------
// Port Definitions
// --------------------------------------------------------------------------
  input  wire      clk,
  input  wire      resetn,

  input  wire      enable,
  input  wire      d_in,

  output wire      d_out);

  // --------------------------------------------------------------------------
  // Internal wires
  // --------------------------------------------------------------------------
  reg         sync_reg_1;
  reg         sync_reg_2;

  // --------------------------------------------------------------------------
  // Start of main code
  // --------------------------------------------------------------------------

  // Double flip-flop syncrhonizer
  always @(posedge clk or negedge resetn)
  begin
  if (~resetn)
    begin
    sync_reg_1 <= 1'b0;
    sync_reg_2 <= 1'b0;
    end
  else if (enable)
    begin
    sync_reg_1 <= d_in;
    sync_reg_2 <= sync_reg_1;
    end
  end

  assign  d_out = sync_reg_2;

endmodule