module aibcr3aux_top_master  
   (
    output wire  o_por_vcchssi,
    output wire  o_por_vccl,
    output wire  osc_clkout,
    inout  wire  device_detect, //Shrink aux74/75 due to limit microbump/C4 bump pin
    inout  wire  por,   //Shrink aux85/87 pin due to limit microbump/C4 bump pin
    input        m_por_ovrd, 
    input        i_osc_clk 
     ); 
     
`ifdef LEVEL_SHIFTER_TEST
wire   vccl_aibcr3aux;
wire   vcc_aibcr3aux;
`else
wire   vccl_aibcr3aux = 1'b1;
wire   vcc_aibcr3aux  = 1'b1;
`endif
wire   vssl_aibcr3aux =1'b0;

//Changed instantiation to match with the schematic, Jennifer 05/04/18
wire por_out;     //After IO buffer
wire por_out_vcc; //After level shifter
aibcr3aux_pasred_baldwin xpasred (
     .iopad_crdet(device_detect),
     .vssl_aibcr3aux(vssl_aibcr3aux),
     .vccl_aibcr3aux(vccl_aibcr3aux),
     .iopad_dn_por(por),
     .dn_por(por_dummy));
assign o_por_vcc = (m_por_ovrd & por_out_vcc); 
assign osc_clkout = i_osc_clk;
assign o_por_vcchssi = o_por_vcc;
assign o_por_vccl = 1'b0;

aibcr3_lvshift_vcc xlvlshf1 (
     .vccl_aibcr3aux(vccl_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
     .out(por_out_vcc), .in(por));  //Output go to AND gate to produce o_por_vccl

endmodule