module ram_16x1k_sp (
  clka,
  ena,
  wea,
  addra,
  dina,
  douta
);

  input clka;
  input ena;
  input [1 : 0] wea;
  input [9 : 0] addra;
  input [15 : 0] dina;
  output [15 : 0] douta;

  // WARNING: This file provides a module declaration only, it does not support
  //          direct instantiation. Please use an instantiation template (VEO) to
  //          instantiate the IP within a design.

endmodule