module altera_up_edge_detection_data_shift_register (
	clken,
	clock,
	shiftin,
	shiftout,
	taps);

	parameter DW	= 10;
	parameter SIZE	= 720;

	input	  clken;
	input	  clock;
	input	[DW:1]  shiftin;
	output	[DW:1]  shiftout;
	output	[DW:1]  taps;

	wire [DW:1] sub_wire0;
	wire [DW:1] sub_wire1;
	wire [DW:1] taps = sub_wire0[DW:1];
	wire [DW:1] shiftout = sub_wire1[DW:1];

	altshift_taps	altshift_taps_component (
				.clken (clken),
				.clock (clock),
				.shiftin (shiftin),
				.taps (sub_wire0),
				.shiftout (sub_wire1));
	defparam
		altshift_taps_component.lpm_type = "altshift_taps",
		altshift_taps_component.number_of_taps = 1,
		altshift_taps_component.tap_distance = SIZE,
		altshift_taps_component.width = DW;


endmodule