module M_main (
out_leds,
in_run,
out_done,
reset,
out_clock,
clock
);
output  [4:0] out_leds;
input in_run;
output out_done;
input reset;
output out_clock;
input clock;
assign out_clock = clock;
wire  [11:0] _w_cpu_mem_addr;
wire  [3:0] _w_cpu_mem_wenable;
wire  [31:0] _w_cpu_mem_wdata;
wire _w_cpu_done;
wire  [31:0] _w_mem_mem_rdata;
wire  [0:0] _c_reg_miso;
assign _c_reg_miso = 0;
reg  [0:0] _t_prev_mem_rw;
reg  [31:0] _t_memio_rdata;
reg  [31:0] _t_mem_wenable;
reg  [31:0] _t_mem_wdata;
reg  [10:0] _t_mem_addr;

reg  [11:0] _d_prev_mem_addr = 0;
reg  [11:0] _q_prev_mem_addr = 0;
reg  [31:0] _d_cycle = 0;
reg  [31:0] _q_cycle = 0;
reg  [4:0] _d_leds;
reg  [4:0] _q_leds;
reg  [1:0] _d_index,_q_index = 3;
reg  _autorun = 0;
reg  _cpu_run = 0;
assign out_leds = _q_leds;
assign out_done = (_q_index == 3) & _autorun;
M_rv32i_cpu__cpu cpu (
.in_mem_rdata(_t_memio_rdata),
.out_mem_addr(_w_cpu_mem_addr),
.out_mem_wenable(_w_cpu_mem_wenable),
.out_mem_wdata(_w_cpu_mem_wdata),
.out_done(_w_cpu_done),
.in_run(_cpu_run),
.reset(reset),
.clock(clock));

M_main__mem_mem __mem__mem(
.clock(clock),
.in_mem_wenable(_t_mem_wenable),
.in_mem_wdata(_t_mem_wdata),
.in_mem_addr(_t_mem_addr),
.out_mem_rdata(_w_mem_mem_rdata)
);


`ifdef FORMAL
initial begin
assume(reset);
end
assume property($initstate || (out_done));
`endif
always @* begin
_d_prev_mem_addr = _q_prev_mem_addr;
_d_cycle = _q_cycle;
_d_leds = _q_leds;
_d_index = _q_index;
_cpu_run = 1;
// _always_pre
// __block_1
_t_mem_wenable = _w_cpu_mem_wenable&{4{~_w_cpu_mem_addr[11+:1]}};
_t_memio_rdata = (_q_prev_mem_addr[11+:1]&_q_prev_mem_addr[4+:1]) ? {31'b0,_c_reg_miso}:_w_mem_mem_rdata;
_d_prev_mem_addr = _w_cpu_mem_addr;
_t_prev_mem_rw = _w_cpu_mem_wenable[0+:1];
_t_mem_wdata = _w_cpu_mem_wdata;
_t_mem_addr = _w_cpu_mem_addr;
if (_w_cpu_mem_addr[11+:1]) begin
// __block_2
// __block_4
_d_leds = _t_mem_wdata[0+:5]&{5{_w_cpu_mem_addr[0+:1]}};
if (_w_cpu_mem_addr[0+:1]) begin
// __block_5
// __block_7
$display("[cycle %d] LEDs: %b",_q_cycle,_d_leds);
// __block_8
end else begin
// __block_6
end
// __block_9
if (_w_cpu_mem_addr[4+:1]) begin
// __block_10
// __block_12
$display("[cycle %d] SPI write %b",_q_cycle,_t_mem_wdata[0+:3]);
// __block_13
end else begin
// __block_11
end
// __block_14
// __block_15
end else begin
// __block_3
end
// __block_16
_d_cycle = _q_cycle+1;
// __block_17
(* full_case *)
case (_q_index)
0: begin
// _top
_cpu_run = 0;
_d_index = 1;
end
1: begin
// __block_18
if (_w_cpu_done == 1) begin
_d_index = 2;
end else begin
_d_index = 1;
end
end
2: begin
// __block_19
_d_index = 3;
end
3: begin // end of 
end
default: begin 
_d_index = {2{1'bx}};
`ifdef FORMAL
assume(0);
`endif
 end
endcase
// _always_post
end

always @(posedge clock) begin
_q_prev_mem_addr <= _d_prev_mem_addr;
_q_cycle <= _d_cycle;
_q_leds <= _d_leds;
_q_index <= reset ? 3 : ( ~_autorun ? 0 : _d_index);
_autorun <= reset ? 0 : 1;
end

endmodule