module delay_bus #(
	parameter integer DELAY = 1,
	parameter integer WIDTH = 1
)(
	input  wire [WIDTH-1:0] d,
	output wire [WIDTH-1:0] q,
	input  wire clk
);

	genvar i;
	reg [WIDTH-1:0] dl[0:DELAY-1];

	always @(posedge clk)
		dl[0] <= d;

	generate
		for (i=1; i<DELAY; i=i+1)
			always @(posedge clk)
				dl[i] <= dl[i-1];
	endgenerate

	assign q = dl[DELAY-1];

endmodule // delay_bus