module  DAC121S101 (
 
// OUTPUTs
    vout,                           // Peripheral data output
 
// INPUTs
    din,                            // SPI Serial Data
    sclk,                           // SPI Serial Clock
    sync_n                          // SPI Frame synchronization signal (low active)
);

// OUTPUTs
//=========
output       [11:0] vout;           // Peripheral data output
 
// INPUTs
//=========
input               din;            // SPI Serial Data
input               sclk;           // SPI Serial Clock
input               sync_n;         // SPI Frame synchronization signal (low active)
 

//============================================================================
// 1) SPI INTERFACE
//============================================================================

// SPI Transfer Start detection
reg  sync_dly_n;
always @ (negedge sclk)
  sync_dly_n <= sync_n;

wire spi_tfx_start = ~sync_n & sync_dly_n;
   

// Data counter
reg [3:0] spi_cnt;
wire      spi_cnt_done = (spi_cnt==4'hf);
always @ (negedge sclk)
  if (sync_n)              spi_cnt <=  4'hf;
  else if (spi_tfx_start)  spi_cnt <=  4'he;
  else if (~spi_cnt_done)  spi_cnt <=  spi_cnt-1;

wire spi_tfx_done = sync_n & ~sync_dly_n & spi_cnt_done;

   
// Value to be shifted in
reg  [15:0] dac_shifter;
always @ (negedge sclk)
  dac_shifter <=  {dac_shifter[14:0], din};


// DAC Output value
reg  [11:0] vout;
always @ (negedge sclk)
  if (spi_tfx_done)
    vout <=  dac_shifter[11:0];


endmodule // DAC121S101