module dct_syn(clk, ena, rst, dstrb, din, dout, den);

	input clk;
	input ena;
	input rst;

	input dstrb;
	input [7:0] din;
	
	output [11:0] dout;
	output den;

	//
	// DCT unit
	//

	// As little as 11bits coefficients can be used while
	// all errors remain in the decimal bit range (dout[0])
	// total errors =  5(14bit resolution)
	//              = 12(13bit resolution)
	//              = 26(12bit resolution)
	//              = 54(11bit resolution)
	fdct #(13) dut (
		.clk(clk),
		.ena(1'b1),
		.rst(rst),
		.dstrb(dstrb),
		.din(din),
		.dout(dout),
		.douten(den)
	);

endmodule