module RAM64X2S (O0, O1, A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE);

    parameter INIT_00 = 64'h0000000000000000;
    parameter INIT_01 = 64'h0000000000000000;

    output O0, O1;

    input  A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;

    reg  [63:0] mem1;
    reg  [63:0] mem2;

    wire [5:0] adr;

    assign adr = {A5, A4, A3, A2, A1, A0};
    assign O0 = mem1[adr];
    assign O1 = mem2[adr];

    initial  begin
        mem1 = INIT_00;
        mem2 = INIT_01;
    end

    always @(posedge WCLK) 
        if (WE == 1'b1) begin
            mem1[adr] <= #100 D0;
            mem2[adr] <= #100 D1;
        end

endmodule