module tb_hotplug_detect;

    reg        clk100;
    wire [7:0] debug;

    reg        hpd;
    reg        auxch_in;
    wire       auxch_out;
    wire       auxch_tri;

        // Datapath requirements
    reg  [2:0] stream_channel_count;
    reg  [2:0] source_channel_count;

        // Datapath control
    wire       tx_clock_train;
    wire       tx_align_train;

        // Transceiver management
    wire [3:0] tx_powerup_channel;

    wire       tx_preemp_0p0;
    wire       tx_preemp_3p5;
    wire       tx_preemp_6p0;
           
    wire       tx_swing_0p4;
    wire       tx_swing_0p6;
    wire       tx_swing_0p8;
          
    reg  [3:0] tx_running;
    wire       tx_link_established;

    reg  [19:0] count;
initial begin
    clk100               = 1'b0;
    hpd                  = 1'b0;
    auxch_in             = 1'b0;
        // Datapath requirements
    stream_channel_count = 3'b001;
    source_channel_count = 3'b001;
    tx_running           = 4'b0000;
    count                = 16'b0;
end

initial begin
    forever begin
        if(count == 100) begin
            hpd = 1'b1;
        end
        if(count == 250000) begin   // IRQ PULSE
            hpd = 1'b0;
        end
        if(count == 400000) begin
            hpd = 1'b1;
        end
        if(count == 750000) begin
            hpd = 1'b0;
        end
        #5 
        clk100 = ~clk100; // generate a clock
        #5 
        clk100 = ~clk100; // generate a clock
        count = count +1;
    end     
end     


channel_management i_channel_management(
        .clk100               (clk100),
        .debug                (debug),

        .hpd                  (hpd),
        .auxch_in             (auxch_in),
        .auxch_out            (auxch_out),
        .auxch_tri            (auxch_tri),

        // Datapath requirements
        .stream_channel_count (stream_channel_count),
        .source_channel_count (source_channel_count),

        // Datapath control
        .tx_clock_train       (tx_clock_train),
        .tx_align_train       (tx_align_train),

        // Transceiver management
        .tx_powerup_channel   (tx_powerup_channel),

        .tx_preemp_0p0        (tx_preemp_0p0),
        .tx_preemp_3p5        (tx_preemp_3p5),
        .tx_preemp_6p0        (tx_preemp_6p0),
           
        .tx_swing_0p4         (tx_swing_0p4),
        .tx_swing_0p6         (tx_swing_0p6),
        .tx_swing_0p8         (tx_swing_0p8),
 
        .tx_running           (tx_running),
        .tx_link_established  (tx_link_established)
);

endmodule