module ram_1024_8(
    input wire clk,
    input wire rst,
    // Read write port
    input wire [9:0] addr0,
    input wire re0,
    output wire [7:0] rd0,
    input wire [7:0] wr0,
    input wire we0,
    // Read only port
    input wire [9:0] addr1,
    input wire re1,
    output wire [7:0] rd1
);

`ifdef SKY130
    sky130_sram_1kbyte_1rw1r_8x1024_8 mem(
        .clk0(clk),
        .csb0(!(re0 || we0)),
        .web0(!we0),
        .wmask0(1'b1),
        .addr0(addr0),
        .din0(wr0),
        .dout0(rd0),
        .clk1(clk),
        .csb1(!re1),
        .addr1(addr1),
        .dout1(rd1)
    );
`else
    reg [7:0] mem [0:1023];
    reg [7:0] rd0_reg;
    reg [7:0] rd1_reg;

    always @(posedge clk) begin
        if (!rst) begin
            if (re0) begin
                rd0_reg <= mem[addr0];
            end
            else if (we0) begin
                mem[addr0] <= wr0;
            end
            
            if (re1) begin
                rd1_reg <= mem[addr1];
            end
        end
    end

    assign rd0 = rd0_reg;
    assign rd1 = rd1_reg;
`endif

endmodule