module uart_top
#(
    parameter BPS_SET      =   96,  //²¨ÌØÂÊ9600
    parameter CLK_PERIORD  =   40   //Ê±ÖÓÖÜÆÚ40ns(25MHz)
)
(
	input 	wire	ext_clk_25m,	//Íâ²¿ÊäÈë25MHzÊ±ÖÓÐÅºÅ
	input 	wire	ext_rst_n,		//Íâ²¿ÊäÈë¸´Î»ÐÅºÅ£¬µÍµçÆ½ÓÐÐ§
	input 	wire	uart_rx,		//UART½ÓÊÕÊý¾ÝÐÅºÅ
	output 	wire	uart_tx			//UART·¢ËÍÊý¾ÝÐÅºÅ
);													

//-------------------------------------
wire clk_25m;	//PLLÊä³ö25MHzÊ±ÖÓ
wire clk_50m;	//PLLÊä³ö50MHzÊ±ÖÓ
wire clk_100m;	//PLLÊä³ö100MHzÊ±ÖÓ
wire sys_rst_n;	//PLLÊä³öµÄlockedÐÅºÅ£¬×÷ÎªFPGAÄÚ²¿µÄ¸´Î»ÐÅºÅ£¬µÍµçÆ½¸´Î»£¬¸ßµçÆ½Õý³£¹¤×÷

//-------------------------------------
wire bps_start1,bps_start2;	//½ÓÊÕµ½Êý¾Ýºó£¬²¨ÌØÂÊÊ±ÖÓÆô¶¯ÐÅºÅÖÃÎ»
wire clk_bps1,clk_bps2;     //clk_bps_r¸ßµçÆ½Îª½ÓÊÕÊý¾ÝÎ»µÄÖÐ¼ä²ÉÑùµã,Í¬Ê±Ò²×÷Îª·¢ËÍÊý¾ÝµÄÊý¾Ý¸Ä±äµã 
wire [7:0] rx_data;         //½ÓÊÕÊý¾Ý¼Ä´æÆ÷£¬±£´æÖ±ÖÁÏÂÒ»¸öÊý¾ÝÀ´µ½
wire rx_int;                //½ÓÊÕÊý¾ÝÖÐ¶ÏÐÅºÅ,½ÓÊÕµ½Êý¾ÝÆÚ¼äÊ¼ÖÕÎª¸ßµçÆ½

//-------------------------------------
//PLLÀý»¯
pll_test u_pll_test
(
	.refclk		    (ext_clk_25m	),
	.reset		    (~ext_rst_n		),
	.extlock	    (sys_rst_n		),
	.clk0_out	    (clk_25m		),
	.clk1_out	    (clk_50m		),
	.clk2_out	    (clk_100m		)
);

    //UART½ÓÊÕÐÅºÅ²¨ÌØÂÊÉèÖÃ
speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD    )
)
speed_rx

(	
    .clk            (clk_25m        ),	//²¨ÌØÂÊÑ¡ÔñÄ£¿é
    .rst_n          (sys_rst_n      ),
    .bps_start      (bps_start1     ),
    .clk_bps        (clk_bps1       )
);

	//UART½ÓÊÕÊý¾Ý´¦Àí
my_uart_rx	my_uart_rx
(		
	.clk            (clk_25m        ),	//½ÓÊÕÊý¾ÝÄ£¿é
	.rst_n          (sys_rst_n      ),
	.uart_rx        (uart_rx        ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.clk_bps        (clk_bps1       ),
	.bps_start      (bps_start1     )
);
		
//-------------------------------------

	//UART·¢ËÍÐÅºÅ²¨ÌØÂÊÉèÖÃ													
speed_setting
#(
	.BPS_SET	    (BPS_SET	    ),
	.CLK_PERIORD	(CLK_PERIORD	)
)
speed_tx
(	
	.clk            (clk_25m        ),	//²¨ÌØÂÊÑ¡ÔñÄ£¿é
	.rst_n          (sys_rst_n      ),
	.bps_start      (bps_start2     ),
	.clk_bps        (clk_bps2       )
);
						
	//UART·¢ËÍÊý¾Ý´¦Àí
my_uart_tx	my_uart_tx
(		
	.clk            (clk_25m        ),	//·¢ËÍÊý¾ÝÄ£¿é
	.rst_n          (sys_rst_n      ),
	.rx_data        (rx_data        ),
	.rx_int         (rx_int         ),
	.uart_tx        (uart_tx        ),
	.clk_bps        (clk_bps2       ),
	.bps_start      (bps_start2     )
);


endmodule