module speed_setting
#(
    parameter BPS_SET      =   96,  //²¨ÌØÂÊ
    parameter CLK_PERIORD  =   40   //Ê±ÖÓÖÜÆÚ40ns(25MHz)
)
(
	input	clk,		//25MHzÖ÷Ê±ÖÓ
	input	rst_n,		//µÍµçÆ½¸´Î»ÐÅºÅ
	input	bps_start,	//½ÓÊÕµ½Êý¾Ýºó£¬²¨ÌØÂÊÊ±ÖÓÆô¶¯ÐÅºÅÖÃÎ»
	output	clk_bps		//clk_bpsµÄ¸ßµçÆ½Îª½ÓÊÕ»òÕß·¢ËÍÊý¾ÝÎ»µÄÖÐ¼ä²ÉÑùµã
);

`define BPS_PARA	(10_000_000/CLK_PERIORD/BPS_SET)	//10_000_000/`CLK_PERIORD/96;
`define BPS_PARA_2	(`BPS_PARA/2)						//BPS_PARA/2;	

reg	[12:0] cnt;		    //·ÖÆµ¼ÆÊý
reg clk_bps_r;	        //²¨ÌØÂÊÊ±ÖÓ¼Ä´æÆ÷
reg	[2:0] uart_ctrl;	//uart²¨ÌØÂÊÑ¡Ôñ¼Ä´æÆ÷

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        cnt <= 13'd0;
	else if((cnt == `BPS_PARA) || !bps_start)
        cnt <= 13'd0;	    //²¨ÌØÂÊ¼ÆÊýÇåÁã
	else
        cnt <= cnt + 1'b1;  //²¨ÌØÂÊÊ±ÖÓ¼ÆÊýÆô¶¯
end

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
        clk_bps_r <= 1'b0;
	else if(cnt == `BPS_PARA_2)
        clk_bps_r <= 1'b1;			//clk_bps_r¸ßµçÆ½Îª½ÓÊÕÊý¾ÝÎ»µÄÖÐ¼ä²ÉÑùµã,Í¬Ê±Ò²×÷Îª·¢ËÍÊý¾ÝµÄÊý¾Ý¸Ä±äµã
	else
        clk_bps_r <= 1'b0;
end

assign clk_bps = clk_bps_r;

endmodule