module hierclock(
                 input        clk_i,
                 input        rst_n_i,
                 input [3:0]  a_i,
                 input [3:0]  b_i,
                 input        a_ld_i,
                 input        b_ld_i,
                 output [3:0] a_count_o,
                 output a_count_valid_o,
                 output [3:0] b_count_o,
                 output b_count_valid_o
                 );
   wire                 clk1_int;
   wire                 clk2_int;

   clockgen U1 (.clk_i(clk_i), 
                .rst_n_i(rst_n_i), 
                .clk1_o(clk1_int), 
                .clk2_o(clk2_int));
   
   counter  U2(.clk_i(clk1_int),.rst_n_i(rst_n_i),.load_i(a_ld_i), 
               .load_value_i(a_i), 
               .count_value_o(a_count_o), 
               .count_valid_o(a_count_valid_o)
               );
   counter  U3(.clk_i(clk2_int), .rst_n_i(rst_n_i), .load_i(b_ld_i), 
               .load_value_i(b_i), 
               .count_value_o(b_count_o), 
               .count_valid_o(b_count_valid_o)
               );
   
endmodule // hierclock