module ft245_axi_fifo_8_32
(
    // Inputs
     input           clk_i
    ,input           rst_i
    ,input           inport_valid_i
    ,input  [  7:0]  inport_data_i
    ,input           outport_accept_i

    // Outputs
    ,output          inport_accept_o
    ,output          outport_valid_o
    ,output [ 31:0]  outport_data_o
);



wire       flush_w = !inport_valid_i;
wire       space_w = !outport_valid_o || outport_accept_i;

//-----------------------------------------------------------------
// Data write index
//-----------------------------------------------------------------
reg [1:0]  idx_q;
always @ (posedge clk_i )
if (rst_i)
    idx_q <= 2'b0;
else if (flush_w)
    idx_q <= 2'b0;
else if (inport_valid_i && inport_accept_o)
    idx_q <= idx_q + 2'd1;

//-----------------------------------------------------------------
// Data
//-----------------------------------------------------------------
reg [31:0] data_q;
reg [31:0] data_r;

always @ *
begin
    data_r = 32'b0;
    case (idx_q)
    2'd0: data_r = {24'b0,  inport_data_i};
    2'd1: data_r = {16'b0,  inport_data_i, data_q[7:0]};
    2'd2: data_r = {8'b0,   inport_data_i, data_q[15:0]};
    2'd3: data_r = {inport_data_i, data_q[23:0]};
    endcase
end

always @ (posedge clk_i )
if (rst_i)
    data_q <= 32'b0;
else if (inport_valid_i && inport_accept_o)
    data_q <= data_r;

//-----------------------------------------------------------------
// Valid
//-----------------------------------------------------------------
reg valid_q;

always @ (posedge clk_i )
if (rst_i)
    valid_q <= 1'b0;
else if (flush_w && idx_q != 2'd0)
    valid_q <= 1'b1;
else if (inport_valid_i && inport_accept_o && idx_q == 2'd3)
    valid_q <= 1'b1;
else if (outport_accept_i)
    valid_q <= 1'b0;

//-----------------------------------------------------------------
// Outputs
//-----------------------------------------------------------------
assign outport_valid_o = valid_q;
assign outport_data_o  = data_q;

assign inport_accept_o = space_w;

endmodule