module normalization # (
    parameter DATA_BITWIDTH = 16
) (
    input wire clk,
    input wire rst,
    input wire [1:0] state,

    input wire [DATA_BITWIDTH-1:0] input_tdata,
    input wire input_tvalid,

    output reg [DATA_BITWIDTH-1:0] output_shift,
    output reg output_shift_left
);

    reg [DATA_BITWIDTH - 1:0]   max_value, new_shift;
    reg                         new_shift_left;
    integer i;

    always @(posedge clk) begin
        if (rst) begin
            max_value <= 0;
            new_shift <= 0;
            new_shift_left <= 0;

        end else if (state == `ST_PREAM_RECEPTIVE) begin
            max_value <= 0;
            output_shift <= new_shift;
            output_shift_left <= new_shift_left;

        end else if (input_tvalid && input_tdata > max_value) begin
                for (i = 0; i < DATA_BITWIDTH; i = i + 1)
                    if (input_tdata[i]) begin
                        new_shift_left <= i < 8;
                        /* verilator lint_off WIDTH */
                        new_shift <= (i < 8) ? 7 - i : i - 7;
                    end

                max_value <= input_tdata;
        end
    end


endmodule