1. Field of the Invention
This invention relates to photolithography and more particularly to a photolithography test structure for electrically measuring the amount of notching associated with the fabrication of a conductive component.
2. Background of the Relevant Art
Lithography, also referred to as photolithography, and sometimes as pattern printing, is a processing methodology by which a pattern is transferred to a target surface or substrate. A pattern is transferred from a mask onto a substrate, which involves the steps of coating, exposing and developing photosensitive resist placed across the substrate. The substrate is first prepared for patterning by removing foreign materials from the substrate surface. An oxide such as, e.g., SiO.sub.2 is then allowed to grow across the clean substrate. Photolithography processing may begin by placing the photosensitive material, often called "photoresist" or "resist", across the prepared substrate surface. Spin coating a liquid photoresist across the substrate is well known, and provides a suitable thin film of protective covering upon the substrate area. The mask is then placed in contact with the photoresist or in close proximity with the photoresist. A light source is configured behind the mask allowing radiation to pass through select portions of the mask and onto the photoresist. Emitted radiation is preferably within the ultraviolet (UV) region. A pattern of photoresist exposed to the UV light is either polymerized or solubilized depending upon the type of photoresist used. A polymerized pattern is one which becomes hardened and substantially resistant to selective removal. On the other hand, solubilized pattern is softened and easily dissolved by a solvent.
Photoresist can be either positive or negative. Negative resist includes resist which becomes polymerized at the locations where UV light strikes the resist. Exposed negative resist becomes polymerized and is considerably less soluble in the developing solvent. Conversely, positive resist includes resist which becomes solubilized at regions exposed to UV light. Exposed positive photoresist becomes considerably more soluble in the developing solvent. The formulation of photoresist (either negative or positive) is well known. Oftentimes, photoresist includes a resist polymer combined with a sensitizer. The sensitizer makes the polymer light-sensitive. An adhesion promoter can also be added to allow the resin to adhere to the substrate material. A thinner may also be added to the viscous resin to allow it to spread more uniformly over the substrate. Numerous types of chemical compositions for each of these components are well known in the art. Typical negative resists include a combination of cyclized polyisoprene polymer resin with bis-azido compounds. A suitable positive resist includes phenol formaldehyde novolak resin combined with a naphthoquinone diazide sensitizer. The chemical composition for positive resist may depend upon the type of solvents or developers used to remove the solubilized photoresist.
After the photoresist is coated across the substrate and exposed to UV light, solubilized photoresist is then removed or developed. Various diluents or developers such as nitrobenzene, acetic acid, xylene and benzene can be used to remove a negative solubilized photoresist. Positive resist developers may include sodium hydroxide, potassium hydroxide, or tetramethylammonium hydroxide to form an alkaline solution. It is understood, however, that other formulations of diluents may be used, as would be apparent to one of skill in this art. The above diluents are but a few exemplary solvents chosen from a long list of suitable developing agents. The chemical composition of a selected solvent can be altered provided the essential function of the solvent remains, namely, to remove all the photoresist at select areas while keeping almost all the underneath layer intact.
After select areas of photoresist are removed, the resulting substrate is subjected to an etchant. Surface areas not having overlying photoresist are etched to remove unwanted, underlying material such as silicon dioxide, silicon nitride, or metallization. Various types of etchants may be used such as chemical (wet etchant), electrical chemical, pure plasma etchant, reactive ion etchant (RIE), ion beam milling, sputtering and high temperature vapor etchant. Wet etchant includes various aqueous etching solutions such as HF-based solutions for silicon substrate, hot H.sub.3 PO.sub.4 for silicon nitride and cold H.sub.3 PO.sub.4 for aluminum metallization. Another popular etching methodology includes plasma etchants, and combination plasma/RIE etchant performed in low pressure gaseous plasma. Plasma etchants are more commonly used in fine geometry applications. Plasma etchants usually contain fluorine or chlorine, for example, CF.sub.4. Like plasma etching, ion beam milling is classified as dry etchant, and is often performed in a vacuum (typically 10.sup.-5 torr). Sputtering done in relatively low vacuum is quite slow, and may produce surface damage. Vapor etching generally requires temperatures in the order of 1000.degree. C. and is mostly used in an insitu cleanup before epitaxial deposition. As such, wet etching, plasma etching, or the combination plasma/RIE etching and vapor phase etching provide suitable etching methodology and remain well known to those of skill in this art.
Etching completely through thin layers such as silicon dioxide present a difficult set of problems encountered by the process engineer. The etch material used is ordinarily selective and will slow or stop its etching action when the underlying desired layer is reached. It may, however, continue to etch laterally and into, e.g., silicon dioxide material underneath non-removed photoresist. Wet etching is particularly prone to this problem, generally known as "undercutting." Etchants that behave in this manner are often defined as "isotropic." That is, isotropic etchants are those which etch at the same rate in all directions. Anisotropic etching implies that a substantial difference exists in etch rates in different directions. For example, anisotropic etching may mean an appreciable etching in a direction normal to the substrate surface and essentially no etching laterally. Thus, there appears differing etch rates in different crystallographic directions. Anisotropic etch mechanisms often appear in combination plasma/RIE etching processes. Due to plasma/RIE etchants' ability to anisotropically etch, plasma/RIE etchants are preferably used for fine-line geometries where undercutting must be minimized.
Undercutting presents a serious problem during the etching process. However, before etching is begun, another problem may arise completely dissimilar from undercutting but which may have the same effect. Namely, "notching" occurs during photoresist exposure/develop and prior to etching. Notching is defined herein as the shift or movement of the demarcation line between solubilized and polymerized photoresist. The image upon the mask and associated image edge should be duplicated at an exact, corresponding location upon the substrate. However, select image edges are often shifted between the mask and the substrate due to the relative shift in the demarcation line. Shift in demarcation causes more or less photoresist to be developed on one side of the line than what should be developed in an ideal situation without notching. As such, the image developed upon the substrate will appear shifted, larger or smaller than the same image upon the mask. For example, positive photoresist may be overdeveloped between the mask images transferred over photoresist causing the resulting image on the substrate to appear shifted or smaller than its target size. Notching is therefore a problem associated with all photolithography processes involving organic-based, positive photoresist.
Illustrated in FIGS. 1-3 are photolithography steps utilizing positive photoresist and a near proximity mask according to a conventional design. It is understood, however, that any type of photoresist may be used as well as any type of optical projection printing provided the designed result is achieved--i.e., the transferal of a mask pattern upon a substrate topography.
Referring to FIG. 1, a substrate 12 such as bulk silicon substrate can be used upon which an integrated circuit may be produced. Substrate 12 may, in the alternative, be any substrate upon which a conductive trace element can be produced thereupon, including phenolic-impregnated material or epoxy-impregnated glass upon which a printed wiring board or printed circuit board can be produced. Still further, substrate 12 may include a printed wiring board upon which trace elements are placed. Shown in FIG. 1, substrate 12 may be substantially planar having diffusion areas 14 placed into the upper surface of substrate 12 to form semiconductor diffusion regions commonly found in an integrated circuit. Still further, field oxide regions 16 are placed between active areas, the field oxide may be several thousand Angstroms thick. Accordingly, diffusion areas 14 are placed within substrate 12 between field oxide regions 16 and gate areas 18. Self-aligned diffusion process is commonly known in the art and often defined as self-aligned polysilicon gate process.
Photolithography is used and repeated to place each of the thin films 14, 16, and 18 onto and into substrate 12. A resulting topography may include many steep peaks and valleys of uneven upper surface. An insulating barrier 20 may be placed across the uneven topography to provide electrical isolation from the upper, subsequent-placed layers. Barrier 20 is generally thin and may be several hundred Angstroms, and is placed between gate 18 and substrate 12 to form a gate oxide region 22. Barrier 20 may also be placed over the top of gate 18 as shown. Barrier 20 may be made from thermal oxides generated from a silicon reaction with oxygen at high temperatures or, alternatively, barrier 20 can be made from chemical vapor deposition (CVD) oxides which are well known in the art. Another type of barrier 22 can be placed above gate area 18 in lieu of or in addition to barrier 20. Barrier 22 can be made of organic silicates, often called "glass." Glass material is a dielectric and provides inner layer insulation between metallization layers and between metallization and lower active regions. The inner layer insulation can be spun over the top of the uneven upper surface. Inner layer dielectrics, such as alkoxysilane, acyloxysilane, tetraethoxysilane (TEOS), phosphosilicate (PSG) or silicon polymer may be used in their liquid form and placed across substrate 12 similar in manner to photoresist placement. The organic silicate is converted to a silica film when heated. There are varying types of glass which can be used. PSG or TEOS generally decomposed into silica between 200.degree. C. to 900.degree. C. depending upon the thickness of the film.
Silica is ordinarily used as diffusion dopant sources and therefore can have doping impurity added to the material. Still further, PSG or TEOS can be used to mask diffusions for lead protection. Even still further, PSG or TEOS can be used as spin-ons for interlevel insulator. In FIG. 1, barrier 22 is used to insulate between gate 18 and overlying metallization layer 24. In order to remain as an insulating layer, barrier 22 must remain crack-free over the operating temperature range and not produce enough stress in the substrate to introduce the defects. The primary advantage of using inner layer dielectrics is the simplicity by which they can be applied to an upper substrate topography. When glasses are used as an interlevel insulator, they have the additional advantage of topography planarization. As shown in FIG. 1, barrier 22 is spun on to help smooth the valleys and peaks of the underlying topography to form a more planar upper surface. As will be appreciated below, a more planar surface helps reduce the notching effect present in photolithography.
Placed across the top of metallization layer 24 is photoresist 26. Thus, FIG. 1 illustrates current processing of metallization layer 24 using photoresist 26. Processing involves transferal of mask 28, and pattern arranged therein, upon metallization 24. Mask 28 contains regions of transparent and opaque material. Chromium is most commonly used as the opaque material and is designated as reference numeral 30.
Illustrated in FIG. 2 is a plurality of light beams which travel through mask 28 in regions not containing opaque structures. Light beams 32 include transmitted beams 34 and reflected beams 36. Transmitted beams are defined as those which impinge upon photoresist 26 and terminate at the lower boundary between photoresist 26 and metallization 24. Reflected beams are those beams which reflect from metallization 24 and back into photoresist 26. Reflection can occur perpendicular to the upper surface of photoresist 26 provided metallization layer is substantially parallel to that upper surface. However, if metallization layer, being somewhat reflective, is not perpendicular to the upper surface of photoresist 26, then reflected beams 36 disperse laterally within photoresist 26.
As defined herein, metallization layer 24 is any layer of conductive material connected between elements placeable upon substrate 12. The elements may be circuit devices integrated upon a single monolithic device, or they may be printed wiring board leads which require interconnect to couple the circuits or leads together at selected locations. Accordingly, metallization layer 24 can be any conductive layer including, but not limited to, metallic films which can be etched in an elongated trace interconnect having a resistance in the range less than 100 .OMEGA./cm of length. Metallization layer 24 can be made of an aluminum metallic compound or any other form of metallic, low-resistive material which (i) is easy to deposit, (ii) adheres well to underlying insulating material 22, (iii) provides a good ohmic contact to underlying diffusion areas, and (iv) is easy to selectively etch.
Metallization 24 can be placed across the entire surface region using varying techniques including but not limited to vacuum deposition. Vacuum deposition implies filament evaporation, electron beam evaporation and sputtering techniques well known in the art. Furthermore, chemical vapor deposition (CVD) and electroplating can also be used as suitable methods of coating a thin film of highly conductive material 24.
FIG. 2 illustrates the movement of demarcation line 38 separating solubilized and polymerized photoresist. Reflected beams 36 extend laterally from the upper reflective surface of metallization layer 24 to an area directly above the desired final interconnect structure 40. As such, demarcation line 38 moves from a target position to an area laterally to the right or left of its original position (provided upper surface of photoresist is configured in a horizontal plane as shown). Using positive photoresist and the example shown in FIGS. 2 and 3, structure 40 appears somewhat smaller in size than its desired configuration. The smaller shape is caused by "notching" or developing of photoresist above the desired interconnect shape. More photoresist is exposed in a lateral direction causing the resulting notching effect near the periphery of the shape. Photoresist is removed by a suitable solvent, the underlying structure 40 is slightly removed at one or more edges of its outer periphery underneath the exposed or notched photoresist. Shown in FIG. 3 is a resulting trace structure 40 having a notched outer edge angled toward the sloped, steeply angled surface from which beam 36 is reflected.
Notching of an interconnect is a result of both (i) a reflective surface underneath the photoresist and (ii) severe sloping sidewalls of a reflective surface spaced near the interconnect structure. The sloped reflective surface is brought about by previous photolithography steps. Whether the underlying surface is metallization or is an insulating material, either surface is reflective of impinging UV radiation. While notching cannot be eliminated, more recent conventional photoresist such as inorganic-based photoresist can be used which limits notching. In an effort to minimize notching, removal of the photoresist directly perpendicular to the photoresist surface is always desired and can be greatly enhanced by anisotropic, inorganic photoresist. Inorganic photoresist proves impractical in many applications. In addition, inorganic photoresist cannot entirely eliminate the notching phenomena.
If notching cannot be entirely eliminated, it is important that it be monitored to determine its effect on the resulting product. It would be advantageous to model a test structure susceptible to notching and to characterize the resulting product according to the magnitude of the notching effect demonstrated in the test structure. If the magnitude of notching can be accurately measured during the photolithography process, the cause of product failure can be characterized more accurately and possibly attributed to notching. As such, it is important that a test structure be used to monitor and attribute notching magnitude to each resulting product. The operator can then make a valued decision as to a threshold amount of notching of which the photolithography process cannot exceed and still produce operable conductive components or interconnect.