The present invention relates to dynamic random access memory, and more specifically, to low power states of dynamic random access memory.
Dynamic random access memory (DRAM) is a general-purpose high-performance memory device suitable for use in a broad range of applications. DRAM allows high bandwidth for multiple, simultaneous, randomly addressed memory transactions.
A particular DRAM may include a pair of low power consumption states for lowering overall system power consumption during periods when data of the DRAM is not accessed. These low power consumption states are the nap and powerdown states. The powerdown (PDN) state is the lowest power state available. In this state the information in the DRAM core is maintained with self-refresh, using an internal timer to refresh the memory. The PDN state has a relatively long exit latency period because of clock resynchronization. An internal clock in the memory is turned off during the PDN state and needs to be resynchronized to an external clock in order to permit normal memory access.
The nap (NAP) state is another low power state in which either self-refresh or refresh-activate (REFA) refresh methods are used to maintain the information in the DRAM core. The NAP state has a shorter exit latency period because the internal clocks in the memory system remain synchronized relative to the external clock signal.
Although the NAP and PDN states are distinct states and have certain differences, in the present application they will often be discussed together as a NAP/PDN state.
FIG. 1 illustrates a state diagram of a prior art memory. State 110 is the NAP/PDN state. The states used to enter into the NAP/PDN state are not illustrated in this figure. The memory may remain in the NAP/PDN state 110 for a period of time. A signal 120 sent by the CPU is received by the memory controller to initiate exit from the NAP/PDN state, moving the memory to the wait for NAP exit delay state 130. The memory is awakened, clocks are resynchronized, and other xe2x80x9cclean-upxe2x80x9d steps are taken at this point. The time used for these steps is the xe2x80x9cNAP exit delayxe2x80x9d, tNXB, or xe2x80x9cPDN exit delayxe2x80x9d, tpXB.
After the NAP exit delay or PDN exit delay, the system receives simultaneous quiet times on the row-access-control and column-access-control signal pins of the memory. This moves the memory to the looking-for-packet-frame state 140.
FIG. 2 illustrates a timing diagram of the prior art system. The clock-to-master (CTM) and clock-from-master (CFM) signals 270 are used by the memory to time data to and from the memory controller. The row-access-control signals 210 and column-access-control signals 220 carry data that identifies the memory location for memory access. The DQAO . . . 8 and DQBO . . . 8 signals 230 are read/write data signals on a data transfer bus.
The SCK signal 240 is a clock signal that is used to time the exit from the NAP/PDN mode. The CMD signal 250 is a command signal used to initiate exiting from the NAP/PDN state. The CMD signal 250 is sampled on both the rising edge and the falling edge of SCK signal 240. To signal the exit from the NAP/PDN mode, the CMD signal 250 transitions from a 0 on a first falling clock edge 242 to a 1 on the next rising clock edge 244. Therefore, if after a falling and rising edge of SCK signal 240 there is a xe2x80x9c01xe2x80x9d on the CMD input, NAP/PDN state will be exited. On a falling edge 242 of the SCK signal 240, the SIOin signal 260 indicates whether the exit is from a NAP state or a PDN state.
In PDN mode, the CTM/CFM clocks 270 are stopped and must be restarted and stabilized for time tCE before a PDN exit command can be sent. In NAP mode, the CTM/CFM clocks 270 are running, and the nap exit command can be sent whenever needed. In both cases, dynamic locked loops (DLLs) in the DRAMs must be restarted and the internal timing circuits of the memory must be resynchronized. After the CTM/CFM clocks 270 become stable, a 0 or 1 is sent on the SIO input 260 on the next falling edge 242 of the SCK signal 240, for NAP or PDN exit, respectively.
On the next rising edge 244 of the SCK signal 240, a data signal, PDEV signal 280, is sent on the DQx pins. The PDEV signal 280 identifies which among several DRAM devices is being woken up from the NAP/PDN state.
Depending upon the DQ select data bit setting for the DRAM device selected to exit NAP/PDN state, the exit delay time begins at either a first falling edge 246 or a second falling edge 248 of SCK signal 240. At time tNXB or tPXBxe2x80x94referring either to NAP exit delay or PDN exit delayxe2x80x94after falling edge 246 or 248, the row-access-control signals 210 and column-access-control signals 220 must enter a quiet state. The quiet cycles 290 on the row-access-control 210 and column-access-control signals 220 must occur exactly tNXB or tPXB after the appropriate falling edge of the SCK signal 240. During the quiet cycle, which lasts at least eight clock cycles of the CTM/CFM signals 270 (at least two clock cycles of the SCK signal 240) no commands may be placed on the row-access-control signal pins 210 or the column-access-control signal pins 220.
Timing a quiet cycle requires complex processing. If commands appear on the row-access-control signals 210 or column-access-control signals 220 during the required quiet time, the memory may be corrupted. Therefore, a worst case scenario must be taken into consideration when designing the memory controller. In the prior art, the memory itself is not aware of the quiet time scheduling and expects a quiet time 290 at an exact time after the tNXB or tPXB.
DRAMs are often used in highly pipelined systems. Pipelined systems generally send interrelated and interwoven commands to memory. In order to process a quiet signal 290 at the appropriate time, the commands that would normally be sent during that period must be rescheduled or held for later processing (stalled). All of the commands that are related to the rescheduled commands must be considered. For example, a row-access-control signal 210 may be sent on the row pins. A column-access-control signal 220 must be sent a fixed period after the row signal. This may disrupt pipelining and result in incomplete commands that may result in corrupted data.
One prior art solution is to insert a buffer time prior to the expiration of the NAP/PDN delay. For a time tbuff prior to the expiration of the delay tNXB or tPXB no new instructions are sent on the pipeline. The time tbuff is set such that, prior to the expiration of the delay tNXB or tPXB, all instructions and data that follow the last pipelined instruction can be completed. Thus, for example, tbuff is sufficiently long to permit a response for a read query from memory. However, tbuff inserts a delay into the pipeline and slows down instruction processing.
In the prior art, the quiet cycle is timed simultaneously on the row-access-control signal 210 and column-access-control signal 220 pins. Because the DRAM may address the row-access-control signal 210 and column-access-control signal 220 pins separately, both must be made inactive separately. This requires additional processing in the memory controller. Additionally, because of the cushioning of related commands around the quiet time 290 a longer delay in the signals being sent to the memory may be introduced.
Therefore, a better method of exiting a memory from a low power state would be advantageous.
A method and apparatus for exiting a memory from a low power state is disclosed. The method includes initiating an exit from the low power state. The method also includes waiting during an exit delay time period. The method further includes scheduling a quiet time command in an addressing pipeline, where the memory transitions from the low power state to a normal power state in response to a quiet time in response to the quiet time command.