The present disclosure relates generally to the field of semiconductor processing, and more specifically to a new method of interconnect metallization for devices with relatively small feature sizes. Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having geometries of 0.1 μm and even 90 nm feature sizes and smaller. As device geometries shrink, the interconnect resistance-capacitance (RC) time constant can increase unless design, process, and material changes are implemented to reduce the interconnect RC time constant delay. Solving the problems associated with new process implementations and equipment technology as well as device requirements have become increasingly challenging.
Metallization of integrated circuits can employ a process known as damascene, in which a substrate is inlaid with metal. Damascene and a related process known as dual damascene (both referred to henceforth as “damascene”) have become widely used in integrated circuit manufacturing for devices with geometries of 0.1 micron or less. Generally, the damascene process involves creating interconnect schemes by cutting trenches into a dielectric, and then filling those trenches with metal. Any excess metal is then polished away. Damascene methods often use copper as the bulk filling interconnect metal because of its low resistance. A copper interconnect is frequently covered with a metal barrier. Beyond 0.1 micron, however, the low resistance advantage of copper interconnects is diminished by the high resistance metal barrier around the copper interconnect. The metal barrier can cause a significant increase in the total RC time delay which causes device performance to degrade. Attempts to thin the metal barrier can result in reliability concerns, such as line-to-line leakage, time dependent dielectric breakdown (TDDB) lifetime, and bias-temperature stress (BTS).
As the metal barrier thickness decreases to 90 nm or less, the methods for depositing the metal barrier on the substrate also become less effective. Barrier layers are typically deposited by physical vapor deposition (PVD), however as the thickness decreases to 10 nm, potential step coverage and void formation can occur. Chemical vapor deposition (CVD) or atomic layer deposition (ALD) can provide improved step coverage over PVD, but often cannot provide high film purity or metal precursor penetration, especially when employed in conjunction with porous, low dielectric constant (k) materials. CVD or ALD deposited barriers also generally require post-treatment to drive out excess carbon from the deposited film in order to reduce the film's resistance. The metal oxide CVD (MOCVD) precursors contain significant amounts of carbon that become part of the film as the deposition reaction occurs within the vicinity of the substrate. Post treatment of the excess carbon can be an insitu plasma densification in which the barrier film may be formed into a dense stack of plasma densified metal layers.
Another problem associated with metal interconnects is poor reliability under a stressed environment. Reliability can degrade due to electromigration, in which a hydrostatic stress is placed on the interconnects, such as an applied current that induces atomic diffusion as momentum is transferred from flowing electrons to interconnect atoms. Electromigration can lead to shorts and cracks in and between interconnects, vias and trenches.