Static timing analysis (STA) is an essential step in the design of high speed very large scale integrated (VLSI) circuits. STA verifies that a VLSI chip will perform correctly at a required frequency before it is released for manufacturing.
Neighboring wires in a chip induce capacitive coupling effects (hereinafter also referred to crosstalk) on each other. As CMOS technology scales down, wires inside a chip become taller and thinner. In addition, due to the increase in the design complexity, wires are brought closer to each other. These, altogether, amplify the ratio of the coupling capacitance between the wires to their corresponding grounded capacitances, and thereby, increase the significance of crosstalk on the timing of a VLSI circuit due to the following reasons: 1) if the voltage signals at the output pins of two CMOS drivers which are connected to two neighboring wires are switching in the same direction (i.e., either both rising or both falling), the coupling capacitance between the two wires will force the signals to speed up since the effective capacitance seen by the CMOS drivers is reduced, 2) if the voltage signals at the output pins of two CMOS drivers that are connected to two neighboring wires switch in the opposite direction (i.e., one rising and another one falling), the coupling capacitance between the two wires will force the signals to slow down since the effective capacitance seen by the CMOS drivers are increased. In addition, coupling also causes erroneous or false switchings which may lead to functional failures in a circuit. It should be added that due to the increase in design complexity and wires' current density, inductive coupling effects on timing are becoming critical. Timing analysis considering coupling events is therefore, unavoidable.
Referring to FIG. 1a, there is shown a set of wires 101 on a chip with coupling between them. To perform coupling analysis, the nets in a design are typically classified into two major groups: 1) victim lines, and 2) aggressor lines. The wire between gate 102 and gate 103 is referred to as the victim 106, while all other neighboring wires 107 are referred to as aggressors to the victim. For instance, the wire driven by gate 104 and received by gate 105 is referred to as aggressor 107. A signal transitioning (switching) on one or multiple aggressors in the temporal vicinity of a victim line induces a signal temporarily on the victim due to electrical coupling. This is referenced as a noise bump. The noise bump can potentially change the logic value at 104 and cause a functional failure. In case the victim is undergoing a signal transition in the temporal vicinity of the time window when the aggressors switch, the induced noise causes a change in the signal propagation and transition time from 102 to 103. This change is often termed coupling induced delay push-out and can cause delay failures in the chip.
To account for functional and delay failures due to coupling during chip design and verification stages, a pessimistic situation is considered where all aggressors are assumed to be switching in a direction that causes the worst possible impact on the victim's timing as described in U.S. Pat. No. 6,615,395 to D. J. Hathaway et al. Only those aggressors whose switching time window overlaps with the victim are considered. The induced noise bump due to these aggressors on the victim is then analyzed for functional verification as well as timing analysis. It has been observed that due to the logical relationship between the lines, all aggressors of a victim line may not switch concurrently.
Referring to FIG. 1b, there is shown a net v coupled to four (aggressor) nets a1, a2, a3, and a4 having coupling capacitances C1, C2, C3 and C4, respectively. A falling transition on v is considered. In the absence of any functional information, the worst-case delay pushout on v is determined to exist when all its aggressors display a rising transition in the temporal proximity of v's falling transition. However, it is obvious from FIG. 1b that only one of a1 or a2, can rise in a given clock cycle. Similarly, it is observed that at most two of nets a2, a3, and a4 may be rising in a given clock cycle.
Referring back to FIG. 1a, and focusing on the timing impact of the coupling induced noise first, a significant drawback of the prior mentioned coupling analysis method is illustrated using an example of a victim net that is capacitively coupled to a set of aggressors. To compute the worst case impact of noise on the propagation delay and transition time of a given switching victim, it is assumed that all aggressors transition contemporaneously in the opposite direction of the victim line, yielding a pessimistic value for the noise injected on the victim. However, the functional relationship between aggressors may prohibit a scenario where all the aggressor transitions are contemporaneously in the same direction. For example, if the set of aggressors shown in FIG. 1a are the outputs of a decoder, only one of the set of aggressors may transition in a given direction within a clock cycle. In addition, the functional relationship existing between the victim and aggressors may restrict certain late-mode assumptions. Equivalent considerations are similarly applicable to the early-mode analysis when all the aggressors are assumed to be switching in the same direction of the victim. For illustrative purposes, the late-mode scenario will be considered hereinafter.
An approach to reduce pessimism is by accounting for the prior mentioned functional relationships during coupling analysis. However, exhaustive enumeration of all possible combinations of aggressor switchings that do not violate any functional relationship has an exponential complexity and is too time consuming, especially in the presence of a large number of aggressors. In addition, it is not immediately obvious how to evaluate which combination of aggressors satisfying the functional relationships is the worst case for a victim. A set of aggressor switching that satisfy given functional relationships (or logic constraints) is termed a feasible switching.
Prior art methods are described in papers by Chai et al., “Temporo-functional Crosstalk Noise Analysis”, Design Automation Conference 2003; and by Glebov et al., “Delay Noise Pessimism by Logic Correlations”, ICCAD 2004, both proposing the use of SAT (Satisfyability) and BDD (Binary Decision Diagram) solvers to obtain the worst set of aggressors that satisfy the functional relationships. These are impractical for complex circuits due to large run-times.