Many integrated circuits have signal lanes that support transmission and/or receipt of data signals. Those signal lanes can include circuitry (e.g., serializer/deserializer, or SERDES, circuits) to prepare bit data for transmission and/or to recover bit data after receipt. Some transmitter-side circuits include a finite impulse response (FIR) filter. Supporting increasing signal data rates can involve increasing the operating speed of the FIR filter. For example, some newer circuits can operate at data rates of 25 Gigabits per second or more. Often in such circuits, however, some functions operate at the full data rate, while other functions operate at sub-rates (e.g., half rate, quarter rate, eighth rate, etc.). While some conventional FIR filters have been designed to support different data rates, those designs have typically involved complex circuits that tend to be ineffective at high data rates (e.g., it can be impractical to close the timing for such circuits).