The subject inventive concept relates to a non-volatile memory system, and more particularly, to a method of managing flash memory in a memory system using a flash memory controller.
Semiconductor memory devices include volatile and non-volatile devices. Volatile semiconductor memory devices are characterized by fast read/write speeds, but lose stored data in the absence of applied power. In contrast, non-volatile semiconductor memory devices retain stored data in the absence of applied power by generally have slower read/write speeds.
Nonvolatile semiconductor memory devices include phase-change random access memory (PRAM), mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). With respect to MROM, PROM, and EPROM among these nonvolatile semiconductor memory devices, it is not easy for end users to readily reprogram stored information. On the other hand, EEPROM provides easily used electrical erase/write operations and is thus increasingly used for system programming requirements that need continuous update. EEPROM is also increasingly used to implement auxiliary memory devices. Flash EEPROMs (hereinafter, generically referred to as a flash memory) have very high integration density (i.e., data storage per unit area) as compared with other types of EEPROM and are very advantageous when used to implement large-capacity auxiliary memory devices.
Conventionally, disk storage media has been widely used to implement large-capacity storage devices and remains a cost effective form of data storage. However, disk storage devices are vulnerable to mechanical impact, have limited miniaturization prospects, have low physical reliability because of their constituent moving parts (e.g., motors and arms), and require sophisticated controllers. In contrast, flash memory is more mechanically robust due the lack of moving parts, requires much simpler controllers, and has a much smaller physical size. For these reasons, the flash memory is rapidly replacing disk storage devices in many applications.
As is understood by those skilled in the art, the reading/writing of data in flash memory is usually performed in page size units while the erasing of data is performed in block size units comprising a plurality of pages. Erasing is usually required before the rewriting of data during various update operations. This difference between read/write data size and erase data size is a unique feature to flash memory, as compared with other types of data storage devices. To provide compatibility with existing file systems, therefore, the flow of data to/from flash memory must be managed using special software (or a virtual file system) commonly referred to as a flash translation layer (FTL).
The FTL essentially maps physical blocks of data with corresponding logical blocks, where a logical block is “logically” referred to by a host while a physical block is physically stored in memory. Physical blocks are actually accessed within the flash memory in relation to requested logical block in accordance with a defined mapping technique implemented through the FTL. Thus, the FTL intermediately controls the execution of read/write operations by the flash memory in response to a request from the host. Even without a host request, the FTL may control certain internal operation (e.g., merge operations, wear-leveling operations, etc.) routinely performed by the flash memory.
The host usually sends a command (or “host request”) to a flash memory system and then waits for a response without specifically recognizing which operation is currently being performed by the flash memory. Yet, the response speed to a host request sufficiently influences the overall performance capabilities of the larger system incorporating the flash memory system.
It is of course possible that a host request may not be immediately responded to by the flash memory when the host request is received during execution of a current operation. For instance, if a read request is received from a host while data is being written to the flash memory, then the read operation cannot be immediately performed due to resource conflicts, such as unavailable I/O ports, data channels, etc. Only after the current write operation is completed can the read operation be performed by the flash memory and/or corresponding channel. Additionally, a read/write request may not be immediately responded to when a current internal operation (e.g., a merge operation or wear-leveling operation) is being performed by the flash memory.
Unfortunately, any delay in responding to a host request runs the risk of slowing the overall performance of the device or system incorporating the flash memory.