Modern copper electroplating for Damascene processes proceeds by a “bottom up” fill mechanism that preferentially fills high aspect ratio features such as the trenches and vias on a wafer surface. This is accomplished by depositing copper geometrically along the contours of the wafer surface, including the corners at the base of recessed features. Unfortunately, this process does not fill and planarize large aspect ratio features and requires significant “overburden.” Overburden is the additional copper deposited on the substrate to ensure that all low aspect ratio features are completely filled to the plane of the wafer isolating dielectric surface (the “field”). Since the bottom up fill does not occur in low aspect ratio features, the surface of the overburden typically follows the contours of the wafer surface recesses over these features. In most cases, the overburden on field regions is slightly thicker than the thickness of the Damascene layer, typically on the order of 1.2 times the depth of the deepest feature. So, for example, a damascene structure that has features 0.5 micrometers deep will require an overburden of approximately 0.7 to 0.8 micrometers.
Overburden is undesirable because it requires deposition of excess copper, that is essentially wasted, and because it requires an extra step of removing the overburden material. Thus, overburden represents additional materials costs (excess copper deposited) as well as decreased throughput/productivity. In current processes, overburden is removed by a planarization technique such as chemical mechanical polishing (CMP) or electropolishing. CMP is a relatively expensive process that uses generally corrosive chemical formulations on large pads to polish the surface of the integrated circuit. The process can be difficult to control and the polishing end-point can be difficult to detect. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of porous low-k dielectrics in semiconductor devices, modification of traditional CMP processes will be required, as current methods can crack and/or delaminate low-k materials, which typically have a very low compression strength and extreme fragility.
Still further, measures must be taken to avoid metal “dishing” and dielectric erosion during CMP. Erosion of the dielectric occurs from over-polishing, which is necessary to make sure all the metal is removed from the top of the dielectric. Dishing occurs on the soft metal, and reduces the thickness of the copper interconnects and increases the electrical resistance. The overall changes in the planarity caused by dishing and erosion can also lead to difficulties in obtaining good focus across the die during subsequent lithographic steps. More importantly, topography introduced by these effects is replicated at the next metal level. This makes CMP progressively more difficult as metal layers are added to the structure.
Alternatives to CMP include electrolytic etching techniques such as electropolishing or electroless etching. Compared to CMP, these are relatively low cost techniques. They also provide much higher processing rates. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. The process may be viewed as the reverse of electroplating. Various electropolishing techniques have been described and appear to be promising. The following patent documents, which are incorporated herein by reference for all purposes, describe important implementations of the process. Reid (U.S. patent application Ser. No. 09/758,307 filed Jan. 9, 2001) describes a method of electrochemical planarization of metal surfaces in which planarization rates are modulated by tight control of the distance between a metal layer to be planarized and a planar cathode (in conjunction with a highly resistive electrolyte). Mayer et al. (U.S. patent application Ser. No. 09/967,075 filed Sep. 28, 2001) describe a method of planarization of metal layers in which a “pad” is used to create localized fluid agitation (and/or physical contact) in raised regions relative to recessed regions to facilitate planarization. Other relevant techniques are described in 10/209,171 filed Jul. 29, 2002 by Drewery et al. and U.S. Pat. No. 6,315,883. Each of these documents is incorporated herein by reference.
Although these inventions address the need for improved electroplanarization in semiconductor device fabrication, ideally an electroplating process would produce little if any overburden. Short of that, an electroplating process that deposits copper with reduced overburden and improved planarity would be highly desirable. Generally both electropolishing and electroetching have limited ability to planarize a “contoured” surface. In contrast, CMP selectively removes metal from exposed surfaces and not from recessed ones. Therefore, if a damascene structured surface is planarized after filling all the recessed features, in principle the more economically useful techniques of electropolishing, electrochemical etching, or electroless etching can be used to remove the field metal, thereby replacing the more costly CMP removal/planarization process. One approach to avoid metal overburden is an approach that attempts to combine chemical-mechanical, or electropolishing with electroplating in a single module, as described in Patent Application Publication US2002/0011416 A1, by Talieh. In that disclosure, electroplating and polishing occur simultaneously on different portions of a single wafer, with portions of the work-piece surface shuffling between sections of a process module (e.g. by rotation). One portion of the wafer is being electroplated while simultaneously another section is being polished. In addition to creating a planarized product with minimal overburden, it claims that performing the planarization and film deposition steps in this rapid back and forth manner improves film crystallographic properties.
Another class of methods useful in overburden reduction and planarization is referred to as “planar plating”. As known in the art, so-called bottom-up fill (also referred to as “superfilling”) methods are used to fill high aspect ratio (i.e., deeper than wide) recess features. However, due to their physical limitations, these processes are not capable of filling low aspect ratio (structure such as contact pads and the like). Since both of these feature types can exist on every damascene integrated circuit interconnect level, research into a potentially low cost “planar plating” methods has been pursued. Various planar plating methods that attempt to modify the otherwise conformal plating behavior over recessed low aspect ratio region by modifying the plating method (bath additives, transport properties, field effects, etc.) have been reported.
Reid (U.S. Pat. No. 6,024,857) describes a planar plating method using a bath additive, which acts to fill recess regions and “level” (planarize) a surface during metal deposition. The molecule is chosen to block transport to the exposed surface but is larger than the recess structure and unable to adsorb onto the regions within or on the side of the feature, thereby allowing metal to preferentially plate there.
U.S. Pat. No. 6,534,116 by Bulent describes a planar plating method that employs a plating solution containing an additive that accelerates the plating rate. During plating, additives are described as being continually adsorbed onto the plating surface from the solution, but are removed preferentially from the exposed surfaces by an “external influence”. According to the disclosure, the additives remains in the recessed regions but is selectively removed from the exposed surfaces, enabling the process to produce a relatively planar deposit over a substrate initially containing a varying topography. The external influence used to selectively removes the adsorbate described in the '116 patent is a continuous pad rubbing. The patent states that the removal of the additive(s) adsorbed on the top portion of the work piece allows plating of the conductive material to take place preferentially in the cavity (recessed regions). The patent states that the process of removal must occur in such a fashion that the rate of removal of the adsorbate is greater than the rate of re-adsorption. The pad is brought in contact with the substrate, and is swept over the surface. The pad is described as having holes and creating a “mask” that is placed intermittently between the anode and the substrate, and moved with respect to the substrate, so that the holes sweep open and closed over the substrate, exposing and masking the anode. The process is termed “masked plating”. The mask-pulsed plating method is described as utilizing the differences between response times of various additives to achieve enhanced plating into the various features of the substrate surface. The mechanism involves “sweeping” the top surface of the substrate (field regions) by the mask, which does not make physical contact with the regions inside the features.
The use of a pad in continuous contact with the wafer creates a unique set of problems, and the influence of adsorption dynamics (diffusion, surface reaction rates, local consumption rates, etc.) can make process control very difficult. Furthermore, the process plating selectivity will always be less than optimal between recessed and exposed regions because the finite rate of additive readsorption will tend to reduce the plating selectivity. The mechanism of masked plating, and specifically the role of the mask-plating pad in creating differential plating activity remains unclear and leads to doubt regarding optimization, the method's robustness, and overall utility. Understanding a plating mechanism impacts the ability to design better processes and tool implementation strategies. In addition, while the desired properties of the pad have not been specified clearly, the continual contact of the pad to the surface and the associated continual wear will require significant pad conditioning to maintain performance and selectivity. This substantially limits the overall pad life. Replacement of the mask plating pad is not only potentially costly from a material standpoint, but also from a tool utilization and uptime standpoint.
Controlini et al. (U.S. Pat. No. 5,486,234) describes a method of spin-spray etching particularly suited for removing both the field metal and metal embedded in a substrate at substantially the same rate by using a suitable metal etchant onto a spinning wafer. The process etches the metal evenly on the entire surface of the wafer and is useful after the wafer has been electroplated and planarized, for example, by electropolishing. While this technique is sited as a substitute for chemical mechanical planarization, because it is a conformal operation, it requires an initially planar surface to be useful.
We describe herein a new planar plating method and its associated mechanism, referred to as “selective acceleration planarization” (referred to herein as “SAP”) having much greater planarity and reduced need for overplating. SAP employs the process step of exposing a wafer to certain plating additive (activation), followed by selective removal of the adsorbed additive. Removal is typically accomplished by rubbing (friction) the accelerator removal material with a stiff pad, selectively removing the additives from exposed regions. Effective selective additive removal subsequently enables field versus recess plating current-densities differences (referred to as contrast), and general planarization by plating (filling) recessed features at a substantially higher rate than in exposed (adsorbed additive free) regions. SAP plating is typically performed in a plating bath containing certain polarizing additives (known as suppressors) but is substantially free of accelerating additives. Suppressors are not effective in retarding the plating rate on surfaces having adsorbed accelerating additives. Note that it is not the desired objective of the SAP rubbing process to remove field exposed metal (via a CMP like planarization process), but simply to remove the accelerating plating bath additives from exposed surface. This process requires less work (e.g. lower pressure, rotation rate, time, etc.) than a process that removes field metal by CMP. The process forms a substantially planar copper electroplated layer over a surface comprising many recessed features. The peak-to-peak variation on the final plated metal surface is preferably significantly less than the height variation (topography) of the underlying seed layer (e.g., the resulting surface should contain height variation of not more than ˜200 Å over 100 micrometer features).