1. Field of the Invention
The present invention relates to a high voltage transistor and a method of manufacturing the same. More particularly, the present invention relates to a high voltage transistor of which a breakdown voltage is high and to methods of manufacturing the same.
2. Description of the Related Art
In general, a metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) includes three different operation regions.
FIG. 1 is a graph illustrating an electrical characteristic of a drain in an N channel enhancement type MOSFET.
As shown in FIG. 1, in the N channel enhancement type MOSFET, an inversion layer that is a conductive channel in a transistor is formed in a portion of the channel of the MOSFET, and the MOSFET is operated on condition that a threshold voltage Vt is positive and a voltage Vgs between a gate and a source of the MOSFET is over a threshold voltage Vt.
When the voltage Vgs is less than the threshold voltage Vt, the inversion layer is not formed and a current does not pass through the MOSFET. The region in which the voltage Vgs is less than the threshold voltage Vt is referred to as a cut-off region.
When the voltage Vgs is greater than the threshold voltage Vt and the MOSFET is operated, the amount of current passing though the MOSFET is determined in accordance with a voltage difference between the source and drain Vds. In a case in which the voltage difference Vds is relatively low, the current is linearly proportional to the voltage difference Vds. The region in which the current is linearly proportional to the voltage difference Vds is referred to as a triode region.
As the voltage difference Vds increases, a depth of the channel around the drain gradually decreases. Finally, when the voltage difference Vds is greater than a saturation voltage Vs corresponding to the voltage difference between the voltage Vgs and the threshold voltage Vt, the channel around the drain is pinched off. As a result, a depletion region instead of the inversion layer is formed in the channel, and electrons are moved through the depletion region by the voltage applied to the depletion layer. In addition, the amount of current passing through the MOSFET is not affected by an increase of the voltage difference Vds, and the MOSFET operates just like a static current source. The region in which the current amount is not affected by the increase of the Vds is referred to as a saturation region.
When the Vds is increased over the saturation region, the pinch-off region of the channel is gradually enlarged, and thus the channel is shortened. The shortening of the channel is generally referred to as channel length modulation. As the channel is shortened, the depletion region between the channel and the drain is enlarged, and the current Ids passing through the channel slightly increases as the voltage Vds increases.
In a case in which the voltage Vds is greater than a predetermined voltage Vb, the inversion layer disappears and only the depletion region is formed between the source and the drain of the MOSFET, and thus the current of the drain exceeds the saturation current Ids due to a current leakage at the drain of the MOSFET. The depletion region between the drain and the source of the MOSFET reduces the energy barrier and immobilizes the electrons. Thus, the current leaks from the drain. Current leakage from the drain is more prevalent when the channel length is less than or equal to about 2 μm. As the voltage Vds increases, the energy barrier also decreases, thereby increasing the leakage current. However, the leaking current is not substantially proportional to the increase of the voltage Vds. This phenomenon is referred to as a punch-through or a soft breakdown.
When the voltage Vds increases over the soft breakdown, the channel is broken down due to an avalanche effect. As the voltage Vds increases, an electric field intensity in the MOSFET becomes higher around the corner of the drain than at a central portion of the channel. The high intensity of the electric field increases the kinetic energy of a charge carrier to a level much higher than the kinetic energy at room temperature. The charge carrier of high kinetic energy is usually referred to as a hot carrier. When some of the hot carriers contact the surface of the substrate, and impacts the atoms of the substrate, a plurality of electron hole pairs is created. This phenomenon is referred to as an avalanche effect.
In the case of an N type MOSFET, holes accumulated on a P type substrate generate a forward-biased voltage between the source and the substrate. When the forward-biased voltage between the source and the substrate is about 0.6V, the electrons move from the source to the substrate. The movement of the electrons from the source to the substrate causes the same result as a bipolar npn transistor in parallel with the MOSFET. Accordingly, supplying even a small quantity of the holes to the substrate corresponding to a base of the transistor causes a large amount of current between an emitter and a collector, which is referred to as a conventional operation of a bipolar junction transistor. In the same way, a little increase of the voltage between the drain and the source generates a large amount of current in the channel, which is referred to as a channel breakdown.
As described above, the increase of the voltage for channel breakdown requires an increase of the channel length. However, the channel length increase is not desirable in accordance with a technological trend of high integration in semiconductor devices since the area occupied by a transistor is enlarged. In addition, because an electric field intensity of a corner portion of the drain is generally higher than that of a central portion of the channel in a conventional MOS transistor, a transistor structure having a high breakdown voltage is required to lower the electric field intensity at the corner portion of the drain and minimize or prevent hot carriers.
For example, Korean Laid-Open Publication No. 1999-51079 discloses a method of fabricating a semiconductor device using an etching process obliquely performed against an insulation layer. Particularly, a thin gate oxide layer is formed on an enlarged gate area for an N channel laterally-diffused metal-oxide-silicon (LDMOS) transistor, and a low temperature oxide layer is formed on the gate oxide layer as an insulation layer. Then, the gate oxide layer is wet-etched, thereby minimizing an insulation failure due to a high electrical field intensity at the enlarged gate area for the LDMOS transistor.
However, the field oxide layer of the LDMOS transistor extends to a whole P drift region in a substrate, so that there is a problem in that impurities in the P drift region are not exhausted.