1. Field of the Invention
The present invention relates to a memory cell structure of a semiconductor storage apparatus having an SRAM (Static RAM) memory cell.
2. Description of the Background Art
In recent years, it has been greatly demanded that the weights, thicknesses and sizes of electronic apparatuses should be reduced and the functions of the same apparatuses should be implemented at a high speed. Nowadays, it is essential that a microcomputer should be mounted on such electronic apparatuses. In the structure of the microcomputer, it is required that a memory having a large capacity and a high speed should be mounted. Moreover, it has been required that the capacity of a cache memory should be increased in order to implement a processing more quickly with the rapid spread and high performance of a personal computer. In other words, it has been necessary to increase the speed and capacity of an RAM to be used by a CPU during execution of a control program or the like.
While a DRAM (Dynamic RAM) and an SRAM are generally used for the RAM, the SRAM is usually used in a portion in which a processing is to be carried out at a high speed, for example, the cache memory. As the structure of a memory cell, there have been known an SRAM of a high resistance load type which is constituted by four transistors and two high resistance elements and an SRAM of a CMOS type which is constituted by six transistors. In particular, the SRAM of the CMOS type has a high reliability and is a present mainstream because of a very small leakage current during data hold.
In the memory cell, generally, a reduction in an element area implies the realization of an increase in a speed as well as a reduction in the size of a memory cell array. Conventionally, various layouts have been proposed for the memory cell structure in order to implement an operation of the SRAM to be carried out at a higher speed.
For example, according to xe2x80x9cSemiconductor Storage Apparatusxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 10-178110 (1998), a boundary line of a P well region and an N well region where an inverter constituting a memory cell is formed is arranged in parallel with a bit line so that a shape of a diffusion region in the P well region or the N well region and a shape of a cross connecting portion of two inverters can be simplified without a bent portion, resulting in a reduction in a cell area.
FIGS. 22 and 23 are views illustrating a layout structure of the xe2x80x9cSemiconductor Storage Apparatusxe2x80x9d disclosed in the Japanese Patent Application Laid-Open No. 10-178110 (1998) as seen on a plane. In particular, FIG. 22 shows a lower part including a diffusion region formed on a semiconductor substrate surface, a polycrystalline silicon film formed on an upper surface of the diffusion region and a first metal wiring layer formed on a first layer, and FIG. 23 shows an upper part including second and third metal wiring layers formed on second and third layers provided on an upper surface of the lower part.
As shown in FIG. 22, an N well region including PMOS transistors P101 and P102 is provided on a center of a memory cell, and a P well region including NMOS transistors N101 and N103 and a P well region including NMOS transistors N102 and N 104 are provided on both sides thereof.
The PMOS transistors P101 and P102 and the NMOS transistors N101 and N102 are mutually cross connected to constitute a CMOS inverter, that is, a flip-flop circuit, and the NMOS transistors N103 and N104 correspond to access gates (transfer gates).
As shown in FIG. 23, moreover, bit lines BL and {overscore (BL)} are separately formed as the second metal wiring layers and each of them is connected to one of semiconductor terminals of each of the access gate MOS transistors N103 and N104 provided thereunder. Moreover, a power line Vdd is formed as the second metal wiring layer in parallel with the bit line in a central part between the bit lines BL and {overscore (BL)}, and is connected to one of semiconductor terminals (sourcexe2x80x94drain regions) of each of the PMOS transistors P101 and P102 provided thereunder. Furthermore, a word line WL is formed as the third metal wiring layer in a direction orthogonal to the bit lines BL and {overscore (BL)} and is connected to gates of the NMOS transistors N103 and N104 provided thereunder. Moreover, a grounding conductor GND is formed as two third metal wiring layers in parallel with both sides of the word line WL.
Since the memory cell is formed in such a layout, an N-type diffusion region in the P well region provided with the MOS transistors N101 and N103 and an N-type diffusion region provided with the MOS transistors N102 and N104 can be formed rectilinearly in parallel with the bit lines BL and {overscore (BL)}. Thus, it is possible to prevent a wasteful region from being generated.
Moreover, a length of a cell in a transverse direction, that is, a length in a direction of the word line WL is relatively greater than a length in a longitudinal direction, that is, lengths of the bit lines BL and {overscore (BL)}. Therefore, a layout of a sense amplifier to be connected to the bit lines BL and {overscore (BL)} can easily be obtained, and furthermore, the number of cells to be connected to one word line can be decreased and a cell current flowing during reading, that is, a consumed power can be reduced.
While the memory cell of the SRAM is an example of a so-called 1-port SRAM, a multiprocessor technique has recently been introduced as one of means for implementing an increase in the speed of a computer and it has been required that a plurality of CPUs should share one memory area. More specifically, various layouts have been proposed for a 2-port SRAM in which access can be given from two ports to one memory cell.
According to xe2x80x9cStorage Cellxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 07-7089 (1995), for example, a second port is provided symmetrically with a first port and is simultaneously formed together with the first port on the same layer so that a structure of a 2-port SRAM is implemented. FIG. 24 shows a layout of the xe2x80x9cStorage Cellxe2x80x9d disclosed in the Japanese Patent Application Laid-Open No. 07-7089 (1995).
In FIG. 24, PMOS transistors P201 and P202 and NMOS transistors N201a, N202a, N201b and N202b are mutually cross connected to constitute a CMOS inverter, that is, a flip-flop circuit, and NMOS transistors NA, NB, NA2 and NB2 correspond to access gates (transfer gates).
More specifically, in FIG. 24, the NMOS transistors NA and NB can give access from one of ports through a word line WL1 and the NMOS transistors NA2 and NB2 can give access from the other port through a word line WL2.
In a layout of a conventional 1-port SRAM memory cell having a 6-transistor structure, there has been a problem in that a wiring capacity of a bit line is large because of an increase in a length in a direction of a bit line and an access time becomes long because of an increase in a line capacity. Moreover, the directions of an access transistor and a driver transistor are different from each other. Therefore, there has been a problem in that it is hard to carry out optimization to have a desirable dimension and to maintain a margin for a variation in manufacture due to mask misalignment.
Referring to the SRAM memory cell having the 6-transistor structure, the xe2x80x9cSemiconductor Storage Apparatusxe2x80x9d disclosed in the Japanese Patent Application Laid-Open No. 10-178110 (1998) proposing a layout structure having a small length in a direction of a bit line solves the problems for the 1-port SRAM. The same contents have also been disclosed in Japanese Patent Application Laid-Open No. 2001-28401.
In the xe2x80x9cSemiconductor Storage Apparatusxe2x80x9d, however, a 2-port SRAM generally comprising two sets of access gates and a driving type MOS transistor has not solved the problems described above. Moreover, the xe2x80x9cStorage Cellxe2x80x9d disclosed in the Japanese Patent Application Laid-Open No. 07-7089 (1995) has described a layout of a 2-port SRAM cell, and provides a layout in which a second port can easily be added without greatly changing a layout of a 1-port SRAM cell and does not have an object to reduce a size of the 2-port SRAM cell in a direction of a bit line.
Referring to an SRAM memory cell of a low power consumption type such as an SRAM memory cell having an 8-transistor structure of a low power consumption type which has a column selection signal line for further pressing a memory cell selected by a word line to be a row selection signal line into a direction of a column, similarly, a specific solving method for reducing a wiring length of a bit line has not been found.
It is an object of the present invention to provide a semiconductor storage apparatus comprising an SRAM memory cell having a low power consumption type transistor structure which can reduce a wiring length of a bit line.
The present invention is directed to a semiconductor storage apparatus including a memory cell having first and second inverters cross connected to each other, wherein first and second conductivity types are defined by one and another kinds, respectively, the first inverter has a first one kind field effect transistor and a first another kind field effect transistor, the second inverter has a second one kind field effect transistor and a second another kind field effect transistor, the first inverter has an output section including a connecting portion of one electrode of the first one kind field effect transistor and one electrode of the first another kind field effect transistor and an input section including a connecting portion of a control electrode of the first one kind field effect transistor and a control electrode of the first another kind field effect transistor, and the second inverter has an output section including a connecting portion of one electrode of the second one kind field effect transistor and one electrode of the second another kind field effect transistor and an input section including a connecting portion of a control electrode of the second one kind field effect transistor and a control electrode of the second another kind field effect transistor, the memory cell further includes third to sixth one kind field effect transistors, the third one kind field effect transistor has one electrode connected to a first storage terminal which is electrically connected to the output section of the first inverter and the input section of the second inverter and a control electrode connected to a row selection signal line, the fourth one kind field effect transistor has one electrode connected to the other electrode of the third one kind field effect transistor, the other electrode connected to a first bit line and a control electrode connected to a first column selection signal line, the fifth one kind field effect transistor has one electrode connected to a second storage terminal which is electrically connected to the output section of the second inverter and the input section of the first inverter and a control electrode connected to the row selection signal line, and the sixth one kind field effect transistor has one electrode connected to the other electrode of the fifth one kind field effect transistor, the other electrode connected to a second bit line and a control electrode connected to a second column selection signal line, and one of the first and second one kind field effect transistors is formed in a first another kind well region and the other is formed in a second another kind well region, the third and fourth one kind field effect transistors are formed in the first another kind well region, the fifth and sixth one kind field effect transistors are formed in the second another kind well region, the first and second another kind field effect transistors are formed in a one kind well region, and the first and second another kind well regions are arranged in a first direction with the one kind well region interposed therebetween and the first and second bit lines are extended in a second direction which is almost orthogonal to the first direction.
The first and second another kind well regions are arranged in the first direction with the one kind well region interposed therebetween, and the first and second bit lines are extended in the second direction which is almost orthogonal to the first direction. Therefore, the formation of the first and second another kind well regions does not influence the wiring lengths of the first and second bit lines.
As a result, the wiring lengths of the first and second bit lines can be reduced. Therefore, the semiconductor storage apparatus of the present invention can maintain a good access time.
Preferably, in the semiconductor storage apparatus of the present invention, the first one kind field effect transistor is formed in the second another kind well region, and the second one kind field effect transistor is formed in the first another kind well region.
The first and third one kind field effect transistors which have electrodes connected to the first storage terminal are separately formed into the second and first another kind well regions respectively, and the second and fifth one kind field effect transistors which have electrodes connected to the second storage terminal are separately formed into the first and second another kind well regions respectively.
Accordingly, in the case in which electrons generated by a rays or neutron rays are collected into one of the electrode regions of each of the first to third and fifth one kind field effect transistors which are formed in one of the first and second another kind well regions, the electrons are discharged from one of the electrode regions of the first to third and fifth one kind field effect transistors which are formed in the other another kind well region in which the influence of the generation of the electrons is prevented by the provision of the one kind well region. For example, the electrons collected into one of the electrode regions of the first one kind field effect transistor in the second another kind well region are discharged from one of the electrode regions of the third one kind field effect transistor in the first another kind well region through the first storage terminal and the electrons collected into one of the electrode regions of the second one kind field effect transistor in the first another kind well region are discharged from one of the electrode regions of the fifth one kind field effect transistor in the first another kind well region through the second storage terminal.
By such an operation, the generation of electrons to invert data held in the first and second storage terminals is offset. Consequently, the data are inverted with difficulty. As a result, it is possible to produce an effect that a soft error tolerance can be enhanced.
Preferably, in the semiconductor storage apparatus of the present invention, the row selection signal line includes first and second row selection signal lines, the first bit line includes a first positive-phase-sequence bit line and a first negative-phase-sequence bit line, the second bit line includes a second positive-phase-sequence bit line and a second negative-phase-sequence bit line, the control electrode of the third one kind field effect transistor is connected to the first row selection signal line, the other electrode of the fourth one kind field effect transistor is connected to the first positive-phase-sequence bit line, the control electrode of the fifth one kind field effect transistor is connected to the second row selection signal line, and the other electrode of the sixth field effect transistor is connected to the second negative-phase-sequence bit line, the memory cell includes seventh to tenth one kind field effect transistors, the seventh one kind field effect transistor has one electrode connected to the second storage terminal and a control electrode connected to the first row selection signal line, the eighth one kind field effect transistor has one electrode connected to the other electrode of the seventh one kind field effect transistor, the other electrode connected to a first negative-phase-sequence bit line and a control electrode connected to the first column selection signal line, the ninth one kind field effect transistor has one electrode connected to the first storage terminal and a control electrode connected to the second row selection signal line, and the tenth one kind field effect transistor has one electrode connected to the other electrode of the ninth one kind field effect transistor, the other electrode connected to a second positive-phase-sequence bit line and a control electrode connected to the second column selection signal line, and the seventh and eighth one kind field effect transistors are formed in the first another kind well region, the ninth and tenth one kind field effect transistors are formed in the second another kind well region, and the first and second positive-phase-sequence bit lines and the first and second negative-phase-sequence bit lines are extended in the second direction.
The third and ninth one kind field effect transistors which have electrodes connected to the first storage terminal are separately formed into the first and second another kind well regions respectively, and the fifth and seventh one kind field effect transistors which have electrodes connected to the second storage terminal are separately formed into the second and first another kind well regions respectively.
By the same operation as that of the semiconductor storage apparatus according to the present invention described above, therefore, the generation of electrons to invert the data held in the first and second storage terminals is offset. Consequently, the data are inverted with difficulty. As a result, it is possible to produce an effect that a soft error tolerance can be enhanced.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.