1. Field of the Invention
The present invention relates to a circuit with less power consumption, and more particularly, to a Schmitt-trigger circuit that consumes less electrical power by reducing the amount of the required DC current.
2. Description of the Prior Art
In the present days, many kinds of electrical products are manufactured each day. Except high operation speed, these new products are usually designed to consume less power. This is a very important topic because the employed chips of the electrical products usually have higher package densities than before. Otherwise, the chips may be destroyed when they keep active for a time interval over than a threshold. Accordingly, it is thought to decrease the DC (Direct Current) current that is used to drive the chips for work.
Those chips, such as flip-flops and shift registers, start their operations when the voltage levels at the input terminals rise or fall. Sometimes, the waveform at the input terminal will be distorted, so that the rising or falling time must be also prolonged to prevent operation from error. Typically, the variation at the voltage level of the input signal will change the logic states of the sequent transistors. However, the voltage potential at the input terminal may remain near Vcc/2 whatever the input signal rise or fall. Therefore, the chip will generate unstable outputs even there is only little variation at the voltage level of the input signal. A requirement is thus arisen to design a circuit, such as Schmitt-trigger circuit that enlarges the signal margins for the input signal. Accordingly, the chips can work steadily even there are still fluctuations at the input signal.
Referring to FIG. 1, which represents a diagram illustrative of the Schmitt-trigger circuit used conventionally (please refer to U.S. Pat. No. 3,984,703). Obviously, the transistors 101, 102, 103, and 104 are connected in series, with their gates coupled together for receiving the input signal (V.sub.in). The drains of the transistors 102 and 103, the gates of the transistors 105 and 106 are also tied together to derive the output signal (V.sub.out) for pipeline operations. As noted, the transistors 102 and 103 are connected as a comparator, and these two transistors are coupled in series across a source potential V.sub.cc to ground. Transistors 101, 104, 105, and 106 are employed to be potential dividers, and each the above-mentioned potential divider is series connected across the source potential V.sub.cc to ground.
Although the Schmitt-trigger circuit of the FIG. 1 provides relatively high input impedance (about 10.sup.12 ohms), however, some disadvantages still offer from the conventional Schmitt-trigger circuit. For example, when V.sub.in changes (i.e., rises or falls) very slowly, all the transistors in the Schmitt-trigger circuit will be turned on simultaneously. In addition, because V.sub.in may be derived from a reference circuit, which indicates that the V.sub.in can not be always kept at the reference voltage levels (such as V.sub.cc or ground), all the transistors of the Schmitt-trigger circuit will be also simultaneously conducted. Therefore, there will be a DC current path from V.sub.cc, through transistors 101, 102, 103, 104, to ground, and the DC current will be thought to consume additional and undesired electrical power. On the other hand, the size-ratio of the PMOS and NMOS transistors will be unbalanced if an extreme trigger point, such as higher or lower trigger point is required. Usually, it indicates that larger sizes of the PMOS and NMOS transistors will be needed to adjust the extreme trigger points, and more areas are occupied by the additional sizes of the transistors. A need has been arisen to disclose a Schmitt-trigger circuit for reducing the power consumption, and furthermore, to overcome the disadvantages of the conventional skills.