1. Field of the Invention
The invention relates to a semiconductor memory device, more particularly to one having a flexible configuration.
2. Description of the Related Art
With the growing trend toward SOC (system-on-a-chip) technology, it is inevitable to incorporate a variety of circuit building blocks, each performing a specific function of an electronic system, onto a single integrated circuit chip. This trend imposes a great burden on traditional VLSI circuit design techniques due to the fact that VLSI designers no longer start the circuit design from scratch. Instead, an IP (intellectual property) based design approach is performed. The IP-based design approach involves the use of circuit building blocks having specific functions that are well proven for the integration of the system chip.
Memory devices are usually needed in a system chip. Generally, many memory macros will be embedded within the system chip that commands these memories. The embedded memory macros may be volatile, such as SRAM and DRAM, or non-volatile, such as mask ROM, EPROM, EEPROM and flash memory, and can have parts that differ much in configuration from the standard stand-alone memory devices.
Reusability is a key factor in a design involving the SOC methodology. It can reduce the development time and thus shorten the time to market a product. A circuit building block with a specific fixed function can be reused for a variety of system chips, although some minor differences might exist for fitting the circuit building block into different circuit designs. As a necessary building block in a system chip, it is desirable for a memory device to have a flexible configuration so as to be adapted for use in a wide range of different system chips without the need for constructing a different memory macro for each chip. Although the memory device with the flexible configuration is motivated largely by its embedded utilization in a system chip, it can also be fabricated as a stand-alone chip to provide a flexible configuration in the design of a system board.
FIG. 1 is a schematic circuit block diagram illustrating a conventional memory device 1. In general, the memory device 1 comprises a memory array 10, an address decoder 12, and an input/output (I/O) circuit 14 that includes an input buffer portion 142 and an output sense amplifier portion 144. For convenience of explanation, a memory array 10 having a configuration of 256 words by 16 bits is taken as an example. Therefore, the address bus (AIN) has eight bits, which are decoded by the address decoder 12 to become 256 address select signals for addressing the 256 word lines of the memory array 10, respectively. The input buffer portion 142 has sixteen bit writing units, each of which passes an input data bit of a 16-bit input data bus (DIN) to the corresponding bit line of the memory array 10 under an asserted write enable (WEN) signal. The output sense amplifier portion 144 has sixteen bit sensing units, each of which senses an output data bit of the corresponding one of the bit lines of the memory array 10 and drives the corresponding output data line of a 16-bit output data bus (DOUT) under an asserted output enable (OEN) signal. In the conventional memory array 10, the sixteen bits of one word are simultaneously addressed for simultaneous writing under a common WEN signal, and for simultaneous reading under a common OEN signal.
For a single-port memory device as indicated in FIG. 1, the bit lines of the memory array 10 are shared by both the input buffer portion 142 and the output sense amplifier portion 144. However, a memory device having read and write ports that are separate is common in the art. One example of such a memory device is a dual-port memory commonly used as a FIFO memory. The dual-port memory needs separate addressing means, i.e. address bus and address decoder, for each port to address the word lines of the memory array.
FIG. 2 is a schematic circuit diagram illustrating a bit writing unit 1420 of the input buffer portion in a conventional volatile memory device, such as DRAM or SRAM. The conventional volatile memory device usually has a complementary bit line structure, i.e. B, BN. The bit writing unit 1420 has a buffer input terminal connected to the input data bus (DIN), a buffer output terminal connected to the corresponding bit line (B, BN) of the memory array, and a buffer enable terminal to receive the write enable (WEN) signal. The input data bus (DIN) is connected to the corresponding bit line (B, BN) of the memory array when the WEN signal is asserted, and is disconnected therefrom when the WEN signal is not asserted.
FIG. 3 is a schematic circuit diagram illustrating a bit sensing unit 1440 of the output sense amplifier portion in a conventional volatile memory device, such as DRAM or SRAM. The bit sensing unit 1440 has a sensing input terminal connected to the corresponding bit line (B, BN) of the memory array, a sensing output terminal connected to the output data bus (DOUT), and an output enable terminal to receive the output enable (OEN) signal. The bit lines (B, BN) of the memory array are sensed to drive the output data bus (DOUT) when the OEN signal is asserted.
FIG. 4 is a schematic circuit diagram illustrating a bit writing unit 1422 of the input buffer portion in a conventional non-volatile memory device, such as EPROM, EEPROM and flash memory. The bit writing unit 1422 also has a buffer input terminal connected to the input data bus (DIN), a buffer output terminal connected to the corresponding bit line (B) of the memory array, and a buffer enable terminal to receive the write enable (WEN) signal. However, the conventional non-volatile memory device needs a high voltage (Vpp) to drive a write current to the bit line (B) during a write operation of one of the binary logic levels, such as logic "1". The write current is turned off during a write operation of the opposite binary logic level, such as logic "0". The level shifter 1423 acts to control turning-on and turning-off of an NMOS transistor 1425. W denotes a logic input to the level shifter 1423, which corresponds to a logic AND operation of the input data bit from the input data bus (DIN) and the WEN signal. Q denotes an output of the level shifter 1423, which is used to drive an NMOS transistor 1425. As such, the NMOS transistor 1425 conducts the write current from the high voltage source (Vpp) when the input data bus (DIN) is at logic "1" and the WEN signal is asserted, and resists the write current when otherwise.
FIG. 5 is a schematic circuit block diagram illustrating an 8-to-256 address decoder 120 and 256 level shifters 122. A non-volatile memory device further needs a level shifter 122 associated with each word line of the memory array to apply different voltage levels to the corresponding word line during respective read and write operations. During a write operation, the word lines need a high voltage (Vpp) whereas, during a read operation, the word lines require a normal low voltage (Vcc).
FIG. 6 is a schematic circuit diagram illustrating the level shifter 122. Vsw is connected to a voltage switching circuit (not shown) that supplies the high voltage (Vpp) or the normal low voltage (Vcc) depending on whether the write operation or the read operation is to be performed. W denotes a logic input, while Q denotes an output.
For non-volatile memory devices, an erase mechanism (not shown) is further incorporated for erasing the programmed charges on cells of the memory array.