Semiconductor memory devices are used in a wide range of applications including, for example, digital logic circuits, microprocessors and computers. A steady demand exists for improved methods of manufacturing semiconductor memory devices, including, for example, both methods that reduce the size (and hence increase the level of integration) of the semiconductor memory devices and methods of increasing the operating speeds of the semiconductor memory devices.
Semiconductor memory devices may generally be classified into volatile and nonvolatile memory devices. Exemplary types of volatile memory devices include static and dynamic random access memory (RAM) devices. In static RAM devices, logical information (i.e., binary data) is stored by setting a logical condition of a bistable flipflop loop. In dynamic RAM devices, the logical information is stored as a charge level in a capacitor. Volatile semiconductor memory devices maintain stored data as long as the device is connected to a power supply, but lose the data when the power supply is cut off.
Nonvolatile memory devices include, for example, magnetic read only memory devices (MROM), programmable read only memory devices (PROM), erasable programmable read only memory devices (EPROM) and electrically erasable and programmable read only memory devices (EEPROM). Nonvolatile memory devices are able to retain stored data even when the power supply to the device is cut off. Depending upon the type of device, the stored data may either be immutable (i.e., unchangeable) or reprogrammable. Nonvolatile memory devices are widely used for storing program files and micro-codes in computer, aerospace, communications, customer electronics and numerous other applications. In addition, nonvolatile RAMs (nvRAMs) are often used in systems requiring frequent and high speed transfer and storage of data between volatile and nonvolatile storage modes.
Data stored in MROM, PROM, and EPROM nonvolatile semiconductor memory devices cannot be conveniently reprogrammed by general users because these types of devices generally are not designed to allow users to easily erase the data stored therein. In contrast, EEPROM nonvolatile semiconductor memory devices may be electrically erased and reprogrammed with new data. Consequently, EEPROM devices are typically used in applications where the stored data is updated and/or for auxiliary storage unit applications. In particular, flash EEPROMs (hereinafter, referred to as “flash memory devices”), which can have reasonably high integration densities, are often used in applications requiring large-capacity auxiliary storage units. NAND flash memory devices are often used instead of NOR flash memory devices because NAND flash memory devices generally exhibit higher integration density levels.
Conventional flash memory devices typically comprise a memory cell array that includes a plurality of memory blocks. The memory blocks may be independently operable in reading, erasing and programming operations. In some applications, the time required to erase a memory block or blocks may be a factor that restricts the performance of a system that includes the flash memory device. In order to reduce this erasing time, techniques have been proposed for simultaneously erasing multiple memory blocks of the memory cell array. Techniques for erasing two or more memory blocks of a flash memory device at the same time are disclosed, for example, in U.S. Pat. No. 5,841,721 entitled “MULTI-BLOCK ERASE AND VERIFICATION CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY VICE AND A METHOD THEREOF” and U.S. Pat. No. 5,999,446 entitled “MULTI-STATE FLASH EEPROM SYSTEM WITH SELECTIVE MULTI-SECTOR ERASE.”
As shown in FIG. 1, in erasing memory cells of a flash memory device, a voltage of 0V may be applied to a word line that is connected to the control gates of the flash memory cells, and an erasing voltage Verase, which is typically a high voltage (e.g., 20V), may be applied to the substrate (or a pocket P-well) in which the memory cells are formed. While these voltages are applied, the source and drain regions of each memory cell that is to be erased are conditioned in floating states. Under such bias conditions, charges stored in the floating gate of each memory cell that is to be erased are released into the pocket P-well by Fowler-Nordheim (F-N) tunneling effect. The time that it takes for the voltage of the pocket P-well to reach the erasing voltage Verase is a function of the capacitance between the pocket P-well and the word line (control gate).
During a multi-block erasing operation, word lines of the selected memory blocks that are to be erased are set to, for example, 0V, whereas word lines of deselected memory blocks (i.e., memory blocks that are not being erased) may be conditioned in floating states. When the word line is conditioned in a floating state, there is no capacitance between the pocket P-well and the floating word line. Consequently, the time it takes the voltage of the pocket P-well to reach the erasing voltage Verase may be a function of the number of memory blocks that are erased. For instance, as shown in FIG. 2, when two memory blocks are erased in a multi-block erasing operation, the voltage of the pocket P-well may increase along the solid line denoted by “A.” In contrast, when all of the memory blocks are erased in a multi-block erasing operation, the voltage of the pocket P-well may increase along the solid line denoted by “C.” Thus, as shown in FIG. 2, the time it takes for the voltage of the pocket P-well to reach the erasing voltage is variable based on the number of memory blocks to be erased and the capacitance between the pocket P-well and the word line.
In FIG. 2, T1 denotes the time at which the voltage of the pocket P-well reaches the erasing voltage when erasing two memory blocks. T2 similarly denotes the time at which the voltage of the pocket P-well reaches the erasing voltage when erasing M memory blocks, and T3 denotes the time at which the voltage of the pocket P-well reaches the erasing voltage when erasing all of the memory blocks.
While the time it takes the voltage of the pocket P-well to reach the erasing voltage is variable depending upon the number of memory blocks that are to be erased, the erasing time is constant regardless of the number of the memory blocks. Consequently, the smaller the number of memory blocks that are erased, the longer the erasing voltage is applied to the pocket P-well. For example, when two memory blocks are erased, the erasing voltage is applied to the pocket P-well for a time period that is ΔT1 longer than the time period for which the erasing voltage is applied to the pocket P-well when all of the memory blocks are erased. Similarly, when M memory blocks are erased (where here M is less than all of the memory blocks, but more than two memory blocks), the erasing voltage is applied to the pocket P-well for a time period that is ΔT2 longer than the time period for which the erasing voltage is applied to the pocket P-well when all of the memory blocks are erased. Thus, the smaller the number of memory blocks selected for erasure, the longer the time for which the erasing voltage is applied to the P-well, which increases the stress on the memory cells of the memory blocks. This stress from the erasing operations may cause deterioration of oxide films in the cell transistors, an increase of charge traps, and/or other problems that may result in a gradual or abrupt degradation in the reliability of the memory cells.