The introduction in recent years of large scale integrated circuits to the field of implantable pacemakers has contributed to the historical trend in that field toward greater circuit sophistication and flexibility of operation, while at the same time providing smaller physical size and lower power consumption. The additional circuit functions within a given physical size made possible by integrated circuits permit improved pacemaker performance in terms of external programming flexibility and the ability of the pacemaker to respond in different modes of operation as required to meet the needs of the patient in response to an increasing variety of heart conditions or contingencies. The decrease in the physical size of the pacemaker and the potentially lower current drain leading to increased useful life of the implanted device are important advantages of the use of the integrated circuit.
Of the various integrated circuit technologies that have been developed, perhaps the most widely used in heart pacemakers is complementary metal oxide semiconductor (CMOS) technology. Advantages of CMOS technology include very low current drain, reasonably high circuit density leading to a reasonably small sized circuit, and the fact that it is a well proven technology with many years of experience.
Integrated injection logic (I.sup.2 L) potentially has certain advantages over CMOS technology for an implantable heart pacemaker, but it is also subject to some potential disadvantages. One advantage of I.sup.2 L is greater circuit density, which potentially leads to an integrated circuit smaller by perhaps a factor of two than the same type of device in CMOS, and of course small size is important in the art of implantable pacemakers. Another potential advantage of I.sup.2 L is that it is cheaper to develop and build because it involves fewer masking steps and exotic processes like ion implantation, than CMOS. A possible further advantage of I.sup.2 L, although opinions in the industry are divided on this, is that I.sup.2 L is not subject to failure due to static buildup, which is sometimes thought to be the case with CMOS.
A particularly attractive advantage of I.sup.2 L for use in an implantable pacemaker is the compatibility of I.sup.2 L with analog bipolar technology. The masking and fabrication steps are very similar to bipolar technology, leading to the potential of providing both digital I.sup.2 L and analog bipolar circuits on the same chip. With present pacemakers using CMOS, most of the digital timing, decoding and control functions are performed on the CMOS chip, while another chip or chips are provided with analog circuits for the pulse output circuit, the sense amplifiers and the RF circuits used in remote programming. With I.sup.2 L many of these could be incorporated on the same chip as the timing and control logic.
However, I.sup.2 L is subject to a disadvantage as compared with CMOS in the area of current drain or power consumption. CMOS has inherently low current drain because the quiescent current for the gates is extremely small, whereas I.sup.2 L gates require a significant bias current. Further, it is known that switching speed in I.sup.2 L is heavily dependent upon bias current, with switching speed increasing with increasing bias. It is believed to be possible to make an I.sup.2 L chip to duplicate the functions of present CMOS pacemaker chips at a comparable current drain, by providing a very low bias current to the gates of the I.sup.2 L chip. However, the resulting slow switching speed of the gates can be a problem, and can cause degraded performance in at least some areas such as output pulse width control. A typical value for output pulse width in a pacemaker might be 0.5 milliseconds, with the exact value being selected by remote programming capability. If the timing and logic circuits responsible for pulse width control are operated at extremely low bias current, the resulting delays in switching time could create an error of perhaps 10 to 15 percent in pulse width control, and this would be considered unacceptable. In the case of circuitry for controlling pacemaker output rate, the relatively longer intervals between output pulses, typically 800 to 900 milliseconds, means that switching speed delays will be proportionately less significant.