The present disclosure relates to a variable-resistance memory device and its driving method. The variable-resistance memory device employs memory cells each including a memory element and an access transistor connected in series to the memory element. The memory element has a resistance varying in accordance with a voltage applied to the memory element.
There is known a variable-resistance memory device having a resistance varying in accordance with a voltage applied between electrodes separated away from each other by an insulation layer serving as a storage layer of the variable-resistance memory device. More information on this variable-resistance memory device is described in documents such as “K. Tsunoda, et al., ‘Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V,’ 2007 IEEE, pp. 267-270” and “K. Aratani, et al., ‘A Novel Resistance Memory with High Scalability and Nanosecond Switching,’ Technical Digest IEDM 2007, pp. 783-786” (hereinafter referred to as Non-Patent Documents 1 and 2). In particular, Non-Patent Document 1 discloses a memory making use of a transition metal oxide for making the insulation layer.
On the other hand, Non-Patent Document 2 discloses a memory created by laminating a conductive-ion supplying layer on an insulation layer serving as a storage layer between two electrodes. The memory employs memory cells each having a memory element and an access transistor connected to the memory element in series between first and second common lines which can be driven by adoption of an active-matrix driving method.
Since such a memory cell thus has one transistor T and a variable resistor R of the memory element, the memory is one of current-driven memories of the 1T1R type. This memory is referred to as a ReRAM.
In the ReRAM, the magnitude of the resistance of the memory element indicates whether data has been written into the memory element or deleted from the memory element. A pulse with a short duration time of the nanosecond order can be used for carrying out an operation to write data into the memory element or erase data from the memory element. Thus, serving as an NVM (nonvolatile memory) capable of operating at a high speed like a RAM (Random Access Memory), the ReRAM draws much attention.
In order for the ReRAM to be able to serve as a replacement for the flash memory which is the contemporary FG (Floating Gate)_NAND NVM, however, there are some barriers to surmount. One of the barriers is the fact that the data write/erase characteristic of the memory cell of the ReRAM is dependent on the number of data rewriting operations already carried out on the memory cell. For this reason, in accordance with the number of already performed data rewriting operations, proper operating conditions for applying a voltage to the memory cell are changed.
That is to say, if the operating conditions such as the frequency of the data rewriting operation are changed, stress caused by a data rewriting current/voltage as stress necessary and sufficient for the memory cell also changes as well. Excessively large stress caused by a data rewriting current/voltage increases a leak and changes the number of allowable data rewriting operations or, to be more specific, reduces the number of allowable data rewriting operations. Thus, excessively large stress is not desirable.
In other words, the ReRAM is capable of both guaranteeing the upper limit of the number of data rewriting operations and sustaining the data holding characteristic provided that stress caused by a data rewriting current/voltage as stress necessary and sufficient from time to time is given to the memory cell.
In the ReRAM field, as a technique for applying a proper current or voltage, there is known a technology for controlling a voltage applied to the gate electrode of the access transistor. More information on this technology is described in Non-Patent Document 1.
In accordance with the technique proposed in Non-Patent Document 1, the voltage applied to the gate electrode of the access transistor is adjusted in order to control the magnitude of a current flowing through the memory element as a current for making the resistance of the memory element small or large.
There are also known an MRAM making use of a TMR (Tunnel Magneto Resistance) effect and a variable-magnetism memory adopting a spin injection method. The variable-magnetism memory makes use of a physical phenomenon different from that of the ReRAM. In addition, the variable-magnetism memory and the ReRAM are similar to each other in that both the memories are a current driven memory having the 1T1R type in which every memory cell consists of a memory element and an access transistor.
In the fields of the MRAM and the memory adopting the spin injection method, there is known a technology for controlling a current applied in data writing and erasing operations by making use of a write line decoder. More information on this technology is described in documents such as PCT Patent Publication No. WO2007/015358 (hereinafter referred to as Patent Document 1).
FIG. 1 is a diagram showing the basic configuration of a write line decoder 200 shown in FIG. 4 of Patent Document 1.
The write line decoder 200 shown in the figure has six NMOS transistors N1 to N6 and three inverters INV1 to INV3.
The NMOS transistors N1 and N2 are connected to each other in series. The source electrode of the NMOS transistor N2 is connected to the ground. By the same token, the NMOS transistors N3 and N4 are connected to each other in series. The source electrode of the NMOS transistor N4 is connected to the ground.
An external write-current generation circuit 400 is capable of supplying a write current IW to the drain electrodes of the NMOS transistors N1 and N3.
A point connecting the NMOS transistor N1 to the NMOS transistor N2 is connected to a write line 210 through the NMOS transistor N5 serving as a column switch. By the same token, a point connecting the NMOS transistor N3 to the NMOS transistor N4 is connected to a write line 220 through the NMOS transistor N6 serving as a column switch.
A magnetic resistance element MRE is connected between the write lines 210 and 220 through a select transistor not shown in the figure. The current flowing through the magnetic resistance element MRE is controlled by inversion of the magnetization in a layer having free magnetic domains in accordance with the direction of the flowing current. That is to say, the resistance of the magnetic resistance element MRE is controlled.
The direction of the write current IW is changed by controlling the gate electrodes of the NMOS transistors N1 to N4 in accordance with a current direction signal DIR supplied by a source outside the write-line decoder 200 and logic generated by the inverters INV1 to INV3.
By carrying out this control, a write current IW1 flows when the NMOS transistors N1 and N4 are put in a turned-on state whereas the NMOS transistors N2 and N3 are put in a turned-off state. On the other hand, a write current IW2 conversely flows when the NMOS transistors N2 and N3 are put in a turned-on state whereas the NMOS transistors N1 and N4 are put in a turned-off state.
As is obvious from the above description, in accordance with Patent Document 1, inside the write-line decoder 200, for every two write lines serving as first and second common lines, a path transistor serving as a current switch is provided. The write-line decoder 200 controls the path transistor to enter a turned-on or turned-off state in order to control an operation to stop and supply the write current input to the write-line decoder 200. In this configuration, the gate electrode of an access transistor may be controlled by a common line to arbitrarily operate to write data into a memory element employed in any of memory cells laid out to form a matrix to serve as memory cells each including the access transistor or erase data from the memory element.