1. Field of the Invention
The invention is related to a memory cell and a manufacturing method thereof.
2. Description of Related Art
A memory is a semiconductor device designed for the purpose of storing information or data. As the functionalities of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. As a consequence, the demand for a memory is ever increasing. Among various memory devices, the non-volatile memory has the advantage of retaining stored data after being disconnected. Therefore, many electronic products require the non-volatile memory to maintain normal operation when the electronic products are turned on.
A typical non-volatile memory has a floating gate and a control gate fabricated by using doped polysilicon. As the memory is programmed, electrons injected into the floating gate can be uniformly distributed in the entire polysilicon floating gate. However, if the tunnel oxide layer under the polysilicon floating gate has a defect, a leakage current can be readily generated in the device and affect the reliability of the device.
Therefore, to solve the issue of current leakage in the non-volatile memory, one method utilizes a charge trapping layer to replace the polysilicon floating gate. An advantage of replacing the polysilicon floating gate with a charge trapping layer is that, when the device is programmed, the electrons are only stored in a portion of the charge trapping layer near the top of the source region or the drain region. The distribution pattern of the electrons in the charge trapping layer can be changed by changing the voltage applied to the control gate and the source region and the drain region on two sides, and the distribution pattern of the electrons in a single charge trapping layer can include two groups of electrons with a Gaussian distribution, a single group of electrons with a Gaussian distribution, or no electrons. Accordingly, the non-volatile memory having a charge trapping layer instead of a floating gate is a memory device capable of storing 2 bits per cell. Generally speaking, 2-bit data can be respectively stored on the left side (such as the left bit) or the right side (such as the right bit) of the charge trapping layer.
However, a flash memory may suffer from a second bit effect. That is, when a reading operation is performed on the left bit, the reading operation is affected by the right bit; or when the reading operation is performed on the right bit, the reading operation is affected by the left bit. In addition, the length of a channel is reduced as the memory is miniaturized, which makes the second bit effect more significant, thereby reducing the performance of the memory. Moreover, when the size of the memory is reduced, a spacing between the elements therein is shortened as well. As a result, program disturbance may readily occur and affect the reliability of the memory device when a programming operation is performed on a neighboring memory.