1. Field of the Invention
The present invention relates to switching and control circuitry in electronic circuits. More specifically, the present invention is a phase modulated phase-locked-loop circuit applied as a pulse width modulator.
2. Background Art
The desire to minimize power losses inherent to linear power devices brought about the development of high-frequency switching techniques, as applied in switching power supplies and class-D amplifiers, among other applications. In these applications, higher frequencies permit more compact magnetics and capacitances, along with higher control-loop response. And although EMI/RFI concerns be come greater at higher frequencies, they also become more manageable. Furthermore, in many applications, such as motor drives, higher frequencies permit easy filtering of the `chopped` output, producing cleanly linear electrical power, and keeping high-frequency harmonics from inducing eddy currents and other high-frequency effects into the load, and eliminating cable generated EMI concerns.
Although high-speed operation is compelling, it's application challenges magnetic materials and low-loss transistor construction, among other concerns. Of equal concern is a lack of high-speed control techniques, most notably pulse-width modulation (PWM), and phase modulation (PM).
Switching techniques require a digital controller employing pulse-width modulation (PWM) to convert an analog signal to a digital variable duty-cycle representation of it, which, in power electronics can then be used to control power devices (typically some species of transistor). The electric current in a load supplied from a power source is controlled by switching the source to the load through a repetition of "ON" and "OFF".
Although many power topologies use PWM techniques, the buck converter may be the simplest to implement. Furthermore, at low voltages and high speeds, synchronous rectification improves both the efficiency and the response of a buck converter by replacing the free-wheeling diode with a MOSFET.
The function of the PWM in a basic buck converter is shown in FIG. 1. The PWM 90 generates a control signal, which is then buffered 100, and drives the transistor (Q1) 20. Q120 in this illustration is a MOSFET transistor. When Q120 is "ON", current flows through the circuit, and when Q120 is "OFF", the shunt diode to ground (D1) 30 conducts. The duty-cycle of the buffered control signal, is filtered by L140 and C150, and generates a given output voltage Vout 110. The Vout signal 110 is sampled by the resistive network 60 and input to a comparator 80 along with a reference signal from a reference source 70. An error signal is produced from the comparator 80, is modulated by the PWM, and a new control signal is issued to Q120.
A prior art technique for converting an analog signal to a duty-cycle modulated digital is shown in FIG. 2. A reference clock 200 is used to establish a fundamental operating frequency, which is input to a ramp-wave generator 210. The ramp-wave signal is an input to an analog comparator 230 along with the external analog signal 220 that is intended to be pulse-width modulated. The PWM output 240 from the comparator 230 reflects whether the external analog input signal is greater-than or less-than the instantaneous value of the ramp-wave signal. The timing diagrams illustrate the relationship between the various signals. Thus, in the buck converter, the duty-cycle ratio (t/T) of the PWM signal is ideally a direct representation of the ratio of the analog input to the limits of the ramp-wave signal i.e. Vout=Vin(t/T).
This rather simple technique does have certain limitations. The fidelity of the PWM signal to the analog input is determined by the linearity of the ramp-wave signal. The performance of the comparator determines speed, accuracy and jitter. The ramp-wave signal causes the comparator to make decisions in the sub-millivolt region, making it very susceptible to noise-generating false, or multiple pulses. A simple ramp-wave generator is sensitive to the clock period, so spread-spectrum or variable frequency operation requires additional sophistication.
Multiple pulsing can be eliminated using hysteresis, however this has significant disadvantages that are well-known in the art. The multiple pulsing problem can be ameliorated with good design practices. And in some designs the pulsing problems can be debounced using a downstream R-S latch. In general, ramp-wave fidelity and comparator performance can be improved through refinements in design and processes, but these improvements are incremental, and are presently impractical beyond about 500 kHz.
Phase-Locked Loops (PLLs) synchronize a local Voltage Controlled Oscillator (VCO) to an external frequency input by means of an electronic servo loop. A basic digital PLL is illustrated in FIG. 3, and consists of a Phase Detector (PD) 310, a loop filter or Low Pass Filter (LPF) 320, a Voltage Controlled Oscillator (VCO) 330, and an external signal to phase-lock to (Input Frequency) 300.
The PD 310 compares the Input Frequency 300 with the VCO output 340 and generates a signal representing their phase difference. The phase difference signal is filtered through the LPF 320 to get an analog representation of the phase difference. The LPF 320 phase difference output is input to the VCO 330, which then adjusts its frequency to maintain a constant phase relationship between the Input Frequency 300 to produce a phase locked Output Frequency 340.
The basic PLL is readily modified as a phase modulator (PM) by summing an external control signal with the analog phase difference, just prior to input to the VCO. As shown in FIG. 4, a summing section 410 is placed between the LPF 320 and the VCO 330. An external control signal or Analog Modulated Input 400 is input to the summer 410 along with the LPF phase difference output signal. The resultant summed signal alters the VCO frequency, thereby altering the phase difference between the VCO and the Reference Oscillator (RO) or Input Frequency 300. This in turn alters the output of the PD 310, and after filtering in the LPF 320, nullifies the external control signal, thus tracking, in phase, the external control signal.
Analog phase modulators are extensively applied in communications, and are akin to FM. PLLs operate into the hundreds of MHz. The phase modulators demonstrate excellent linearity, and excellent noise tolerance. The analog phase modulator response is largely determined by the loop filter.
There have been attempts to address the aforementioned problems. Phase-locked-loops have found broad utility in communications and data circuits, typically where signals need to be synchronized or modulated. However, power applications have not taken advantage of this technique. The following patents are related in that they use phase-modulated PLL's, and only GB 2295060 uses PLL's in a power application
In U.S. Pat. No. 5,748,045, a digital PLL circuit is described for use in the recording area, and is used for recording with a PLL to acquire and synchronize read signals on a rotating magnetic recording medium. A PLL circuit uses a PWM circuit to convert a phase error signal to a pulse width modulation signal, wherein the phase error is a sampled/averaged value.
U.S. Pat. No. 5,548,679 discloses a digital PLL system that uses a phase comparator to convert the phase difference between the reference signal and the feedback signal into a binary value. It describes digital PLL techniques and enhancements. The system uses a frequency comparator to convert the frequency difference between the reference signal and feedback signal into another binary value. An automatic gain controller and PWM signal generator use the binary values to control circuit performance.
In EP0433120A1, there is described a PLL synthesizer circuit that uses the pulse width of a signal corresponding to the phase difference between a reference frequency and the synthesizer circuit oscillation frequency. Essentially this circuit is a pulse width detecting circuit and PLL synthesizer circuit used as a PLL lock detector.
A PLL control circuit is disclosed in GB2295060A, where the control circuit is provided by a phase-lock-loop arrangement with a pulse width modulated drive circuit. This patent describes PLL based circuits for power conversion, however these circuits use PLL to control the classic elements of the ramp-comparison technique.
Other related patents include U.S. Pat. No. 5,872,807, which is a spread spectrum clock generator and associated method, that describes a PLL used for spread spectrum clocking. In U.S. Pat. No. 5,914,984, there is described a method and device for pulse width modulation control using digital methods for generating PWM. And U.S. Pat. No. 5,936,565 discloses a digitally controlled duty cycle integration technique for synchronizing clocks.
What is needed is a way to convert an analog signal to a switched duty-cycle representation of the analog signal without the aforementioned problems. The digital signal can be amplified to the target power level and track the analog modulated input signal. In this manner, a PLL functions as a PWM, and with some external control circuitry, provides output voltage regulation. Such a circuit should reduce cost and complexity of existing switching schemes, reduce cost and real estate in the circuit design and topology. Finally, such a circuit should have excellent linearity and noise tolerance.