1. Field of the Invention
The present invention relates to a DC/DC converter and a control method thereof and, more particularly, to a DC/DC converter and a control method thereof whereby losses at a light load are reduced.
2. Description of the Prior Art
In a switching power supply or other power supply systems, a DC/DC converter is used as a device for isolatedly converting a DC input voltage to feed power to a load circuit. The DC/DC converters configured for such purposes are classified into the forward and flyback types depending on the difference in polarity between the primary and secondary windings of an isolation transformer. Examples of forward DC/DC converters are the converters disclosed in the U.S. Patents U.S. Pat. No. 4,441,146 and U.S. Pat. No. 4,959,764. Now, such a device as mentioned above is described.
FIG. 1 is the circuit diagram of a first example of a prior art DC/DC converter.
In FIG. 1, a symbol V11 denotes a DC input power supply, symbols C11, C12, C13 and C21 denote capacitors, symbols Q11 and Q12 denote switching devices, symbols D11, D12, D21 and D22 denote diodes, symbols Np and Ns denote windings, a symbol L21 denotes a coil, a symbol Lr denotes a leakage inductance, a symbol A denotes an error amplifier, and symbols CTL11 and CTL12 denote controllers. The capacitor C13 and switching device Q12 form an active clamp circuit, whereas the windings Np and Ns form a transformer T1 and the D21 and D22 form a rectifying circuit.
The positive-voltage side of the DC input power supply V11 is connected to one end of the capacitor C13 and one end of the winding Np. At this point, the leakage inductance Lr of the transformer T1 develops across those ends of the capacitor C13 and winding Np. The other end of the capacitor C13 is connected to one end of the switching device Q12. The winding Np is a primary winding, the other end of which is connected to one end of the switching device Q11. The switching device Q12 is a sub-switching device, the other end of which is connected to one end of the switching device Q11. The switching device Q11 is a main switching device, the other end of which is connected to the negative-voltage side of the DC input power supply V11.
The cathodes of the diodes D11 and D12 are respectively connected to one end each of the switching devices Q11 and Q12. The anodes of the diodes D11 and D12 are respectively connected to the other ends of the switching devices Q11 and Q12. The capacitors C11 and C12 are parallel-connected to the switching devices Q11 and Q12, respectively. The diode D11, capacitor C11 and switching device an Q11 form a MOSFET, wherein one end of the switching device Q11 serves as the drain and the other end as the source. Likewise, the diode D12, capacitor C12 and switching device Q12 form a MOSFET, wherein one end of the switching device Q12 serves as the drain and the other end as the source.
The winding Ns is a secondary winding, one end of which is connected to the anode of the diode D21 and the other end is connected to the anode of the diode D22. The diode D21 is a forward rectifier, the cathode of which is connected to one end of the coil L21. The diode D22 is a fly-wheel rectifier, the cathode of which is connected to one end of the coil L21. The coil L21 is an inductance device, the other end of which is connected to one end of the capacitor C21. The capacitor C21 is a smoothing capacitor, the other end of which is connected to the other end of the winding Ns. The negative end of the error amplifier A is connected to one end of the capacitor C21 and the positive end is connected to the other end of the capacitor C21 through a voltage reference (desired output voltage). Thus, the amplifier outputs a feedback signal which is the difference between the output voltage of the DC/DC converter and the desired output voltage. The controllers CTL11 and CTL12 turn on and off the switching devices Q11 and Q12, respectively.
Next, specific examples of the configurations of the controllers CTL11 and CTL12 are shown in FIG. 2 and described. The controller CTL11 is composed of an oscillator 11, a pulse width modulation (PWM) circuit 12, a delay circuit 13, and a driver 14. The oscillator 11 outputs an oscillation frequency signal. The PWM circuit 12 outputs a PWM signal according to the oscillation frequency signal from the oscillator 11 and the feedback signal from the error amplifier A. The delay circuit 13 delays the PWM signal of the PWM circuit 12. The driver 14 is given the output of the delay circuit 13, so that the driver turns on and off the switching device Q11. Each of these circuit elements is grounded to the negative-voltage side of the DC input power supply V11.
The controller CTL12 is composed of a delay circuit 21, a level shift circuit 22, and a driver 23. The delay circuit 21 is grounded to the negative-voltage side of the DC input power supply V11 and delays the PWM signal of the PWM circuit 11. The level shift circuit 22 is grounded to the negative-voltage side of the DC input power supply V11 and the other end of the switching device Q12. Thus, the level shift circuit 22 outputs a signal whose level is shifted to a high voltage, according to the output of the delay circuit 21 and the PWM signal of the PWM circuit 12. The driver 23 is grounded to the other end of the switching device Q12, and given the output of the level shift circuit 22 so that the driver turns on and off the switching device Q12.
Now, such a DC/DC converter as explained above is described by first referring to the general behavior thereof. The controllers CTL11 and CTL12 alternately turn on and off the switching devices Q11 and Q12, wherein a dead time is set in order to prevent the switching devices from turning on at the same time.
As indicated by a solid-line arrow in FIG. 1, a current flows through the diode D21 during the period wherein the switching device Q11 is on and the switching device Q12 is off. This current causes another current to be supplied to a load, which is not shown in the figure, and energizes the secondary-side coil L21 so that energy is stored therein.
During the period before the switching device Q11 turns off and switching device Q12 turns on, the current flowing through the diode D21 decreases and the current flowing through the diode D22 increases.
As indicated by a dashed-line arrow in FIG. 1, a current flows through the diode D22 during the period wherein the switching device Q11 is off and the switching device Q12 is on, because of the energy stored in the coil L21.
During the period before the switching device Q12 turns off and switching device Q11 turns on, the current flowing through the diode D22 decreases and the current flowing through the diode D21 increases.
Next, behaviors of the controllers CTL11 and CTL12 are described by first explaining their behaviors under a normal load, using FIG. 3. FIG. 3 is a timing chart showing the behavior of the DC/DC converter of FIG. 2 under a normal load. In FIG. 3, a symbol (a) denotes the drain-source voltage Vds of the switching device Q11, a symbol (b) denotes the drain-source current Ids of the switching device Q11, a symbol (c) denotes the drain-source voltage Vds of the switching device Q12, a symbol (d) denotes the drain-source current Ids of the switching device Q12, a symbol (e) denotes the gate-source voltage Vgs of the switching device Q11, i.e., the output of the driver 14, a symbol (f) denotes the output of the oscillator 11, a symbol (g) denotes the output of the PWM circuit 12, a symbol (h) denotes the output of the delay circuit 13, a symbol (i) denotes the gate-source voltage Vgs of the switching device Q12, i.e., the output of the driver 23, a symbol (j) denotes the output of the delay circuit 21, and a symbol (k) denotes the output of the level shift circuit 22.
At a time t0, the output of the oscillator 11 goes high. The PWM circuit 12 outputs a high-state signal when the feedback signal of the error amplifier A is high. This output signal causes the level shift circuit 22 to output a low-state signal. This output signal causes the driver 23 to turn on the switching device Q12.
At a time t1, the delay circuit 13 causes the PWM circuit 12 to output a delayed signal, lest the main switching device Q11 and the sub-switching device Q12 turn on at the same time. The output of the delay circuit 13 causes the driver 14 to turn on the switching device Q11.
At a time t2, the PWM circuit 12 inverts the signal thereof and outputs the signal to the delay circuits 13 and 21 and the level shift circuit 23 when a pulse width appropriate for the voltage of the feedback signal of the error amplifier A is reached. The signal of the delay circuit 21 rises when the signal of the PWM circuit 12 falls, lest the switching devices Q11 and Q12 turn on at the same time.
At a time t3, the output of the driver 14 goes low when the delay circuit 13 inverts the output thereof, thus turning off the switching device Q11. The delay circuit 21 remains high with the signal thereof kept delayed.
At a time t4, the signal of the delay circuit 21, when inverted, is amplified by the driver 23 so as to turn on the switching device Q12. The switching device Q12 remains on until the PWM circuit 12 inverts the output thereof once again (at a time t5).
Next, the behavior of the DC/DC converter under a light load is described by referring to FIG. 4. FIG. 4 is a timing chart showing the behavior of the DC/DC converter of FIG. 2 under a light load. In FIG. 4, a symbol (a) denotes the gate-source voltage Vgs of the switching device Q11, i.e., the output of the driver 14, a symbol (b) denotes the gate-source voltage Vgs of the switching device Q12, i.e., the output of the driver 23, a symbol (c) denotes the feedback signal of the error amplifier A, a symbol (d) denotes the output of the oscillator 11, a symbol (e) denotes the output of the PWM circuit 12, a symbol (f) denotes the output of the delay circuit 13, a symbol (g) denotes the output of the delay circuit 21, and a symbol (h) denotes the output of the level shift circuit 22.
During the period from a time t0 to a time t1, the switching device Q11 is prohibited from turning on when the feedback signal from the error amplifier A is low, even if the signal of the oscillator 11 is input to the PWM circuit 12. When the switching device Q11 becomes unable to turn on, a voltage is kept applied to the gate of the sub-switching device Q12, thus causing the sub-switching device Q12 to remain on. At this point, the clamp capacitor C13 and the leakage inductance Lr of the transformer T1 produce resonance, causing electricity stored in the capacitor C13 to discharge.
At a time t1, if a signal is input from the oscillator 11 to the PWM circuit 12 when the feedback signal is high, the output signal of the PWM circuit 12 is inverted. Consequently, a signal is input to the level shift circuit 22 and therefore the switching device Q12 turns off. Concurrently, the signal from the PWM circuit 12 is input to the delay circuit 13. Then, after a given delay, the switching device Q11 is turned on by the driver 14.
At a time t2, the signal of the PWM circuit 12 reaches a pulse width appropriate for the feedback signal of the error amplifier A, and is inverted. Following the inversion, the delay circuit 13 also inverts the signal thereof after a given delay, so that the switching device Q11 is turned of f by the driver 14 and therefore the capacitor C13 is charged. Concurrently, the signal of the PWM circuit 12 is input to the delay circuit 21, causing the signal thereof to rise.
At a time t3, the delay circuit 21 inverts the output signal thereof after a delay from the rise of the output so as not to cause the switching devices Q11 and Q12 to turn on at the same time. The output of the delay circuit 21 causes the level shift circuit 22 to invert the signal thereof, so that the switching device Q12 is turned off by the driver 23. At a time t4, the DC/DC converter goes back to the state existing at the time t0.
This means that under a light load, the DC/DC converter goes into intermittent oscillation wherein the main switching device Q11 is at a stop for a certain period because of the response characteristics of feedback control. Since the sub-switching device Q12 remains on during the period wherein the switching device Q11 is at a stop, electricity charged into the clamp capacitor C13 is discharged because of resonance produced by the capacitor C13 and the leakage inductance Lr. Consequently, the amount of energy of 0.5CV2f (C=capacitance of capacitor C13, V=voltage applied to capacitor C13, and f=output frequency of oscillator 11) is consumed as a loss.
For environmental reasons, there is a need to reduce the energy loss of electronic equipment, particularly to reduce the loss in the stand-by state of such equipment. Although the DC/DC converter with an active clamp circuit goes into intermittent oscillation under a light load, the sub-switching device Q12 remains on even if the main switching device Q11 turns off. This results in the problem that electricity stored in the clamp capacitor C13 is discharged and therefore large losses are unavoidable.
FIG. 5 is the circuit diagram of a second example of the prior art DC/DC converter. In FIG. 5, symbols C1 to C3 denote capacitors, symbols Q1 to Q4 denote n-type MOSFETs, symbols Np, Ns, Nfw, Nfl and Ni denote windings, a symbol L1 denotes a coil, a symbol RL denotes a load circuit, a symbol A denotes an error amplifier, and a symbol CTL denotes a controller. The windings Np, Ns, Nfw, Nfl and Ni form a transformer T1 and the MOSFETs Q3 and Q4 form a rectifying circuit. Note that the windings Np, Ns and Ni are correlated with one another as Npxe2x89xa7Ns greater than Ni in terms of the winding ratio.
One end of the capacitor C1 is connected to one end each of the capacitor C2 and winding Np. The other end of the capacitor C2 is connected to the drain of the MOSFET Q2. The winding Np is a primary winding, the other end of which is connected to the drain of the MOSFET Q1. The MOSFET Q2 is a sub-switch, the source of which is connected to the drain of the MOSFET Q1. The MOSFET Q1 is a main switch, the source of which is connected to the other end of the capacitor C1.
The winding Ns is a secondary winding, one end of which is connected to the source of the MOSFET Q3 and the other end is connected to the source of the MOSFET Q4. The winding Nfw is a drive winding, one end of which is connected to the source of the MOSFET Q3 and the other end is connected to the gate of the MOSFET Q3. The winding Nfl is also a drive winding, one end of which is connected to the source of the MOSFET Q4 and the other end is connected to the gate of the MOSFET Q4.
The MOSFETs Q3 and Q4 are first and second switches, the drains of which are connected to one end of the winding Ni. The other end of the winding Ni is connected to one end of the coil L1. The coil L1 is an inductance device, the other end of which is connected to one end of the capacitor C3. The capacitor C3 is an output capacitor, the other end of which is connected to the other end of the winding Ns. The load circuit RL is parallel-connected to the capacitor C3.
The negative end of the error amplifier A is connected to one end of the capacitor C1 and the positive end is connected to the other end of the capacitor C1 through a voltage reference. The controller CTL provides output to the gates of the MOSFETs Q1 and Q2 according to the output of the error amplifier A.
Now, such a DC/DC converter as explained above is described. FIGS. 6 and 7 are timing charts showing the behavior of the DC/DC converter of FIG. 5, wherein FIG. 7 is an enlarged view of FIG. 6. In FIGS. 6 and 7, a symbol (a) denotes the drain-source voltage Vds of the MOSFET Q1, a symbol (b) denotes the drain current Id of the MOSFET Q1, a symbol (c) denotes the drain current Id of the MOSFET Q2, a symbol (d) denotes the current IL of the coil L1, a symbol (e) denotes the gate-source voltage Vgs of the MOSFET Q2, a symbol (f) denotes the gate-source voltage Vgs of the MOSFET Q1, a symbol (g) denotes the gate-source voltage Vgs of the MOSFET Q3, and a symbol (h) denotes the gate-source voltage Vgs of the MOSFET Q4. A symbol (i) denotes the current INs of the winding Ns, a symbol (j) denotes the voltage VNs of the winding Ns, a symbol (k) denotes the voltage VNi of the winding Ni, a symbol (1) denotes the voltage VL1 of the coil L1, a symbol (m) denotes the drain current Id of the MOSFET Q4, a symbol (n) denotes the output current Ig of the capacitor C1, a symbol (o) denotes the voltage VC2 of the capacitor C2, and a symbol (p) denotes an output voltage Vo.
FIGS. 8 to 13 are circuit diagrams for explaining the behavior of the DC/DC converter of FIG. 5, and are indicated as equivalent circuits. FIG. 8 shows the polarity of each voltage, whereas FIGS. 9 to 13 illustrate the converter""s behavior for a time t3-t4 period, time t4-t5 period, time t5-t6 period, time t6-t7 period, and time t7-t8 period, respectively.
The capacitor C1 is a smoothing capacitor for changing a voltage provided by an AC power supply, which is not shown in the figure, into a DC voltage, and serves as a DC power supply. The error amplifier A compares the output voltage Vo with the level of the voltage reference. According to the result of comparison, the controller CTL turns on and off the MOSFETs Q1 and Q2 alternately, thereby keeping the output voltage Vo constant. Then, the DC voltage of the capacitor C1 is changed to a different voltage through the transformer T1.
In that case, the transformer T1 (drive windings Nfw and Nfl) causes the MOSFET Q3 to turn on and the MOSFET Q4 to turn off when the MOSFET Q1 is on. Conversely, the transformer T1 causes the MOSFET Q3 to turn off and the MOSFET Q4 to turn on when the MOSFET Q1 is off.
When the MOSFET Q3 is on, the current INs of the winding Ns charges the capacitor C3. When the MOSFET Q4 is on, the capacitor C3 is also charged by the inductance of the winding Ni and coil L1. The winding Ni reduces any ripple current to zero.
The capacitor C3 supplies power to the load circuit RL. Note that the time t0-t3 period is represented by the general behavior of the DC/DC converter and, therefore, excluded from the detailed description of the converter""s behavior.
During the period wherein the MOSFET Q2 is on, the output capacity of the MOSFET Q2 will have been discharged down to the forward voltage level of the MOSFET""s body diode. This means that the MOSFET Q2 turns off at a time t3. Consequently, a current flows from the clamp capacitor C2 to the winding Np of the transformer T1, thus charging the output capacity of the MOSFET Q2 up to a level equal to the voltage of the capacitor C2. Therefore, the drain-source voltage Vds of the MOSFET Q1 decreases to the voltage Vg of the input smoothing capacitor C1. As the result of a current flowing through the winding Np, the winding Nfl causes the MOSFET Q4 to turn on and the capacitor C3 to be discharged.
At a time t4, the controller CTL detects a light-load state (including no load) according to the output of the error amplifier A, and turns off the MOSFETs Q1 and Q2. This strategy is intended to reduce switching losses. The reason why the MOSFET Q2 is also turned off is because energy stored in the clamp capacitor C2 is discharged through a short-circuit consisting of the MOSFET Q2 and the winding Np of the transformer T1, causing losses to occur.
At a time t4, the current flowing from the clamp circuit (capacitor C2 and MOSFET Q2) to the winding Np comes to a stop. However, the current is forced to flow continuously by the leakage inductance of the winding Np. Consequently, the body diode of the MOSFET Q1 turns on and a current flows through the winding Np into the input smoothing capacitor C1.
Since the body diode of the MOSFET Q1 turns on, the drain-source voltage Vds of the MOSFET Q1 decreases down to the forward voltage level of the body diode.
The current thus produced causes the polarity of each winding to be reversed, and the winding Nfw causes the MOSFET Q3 to turn on. Once the MOSFET Q3 turns on, a discharge takes place in the direction from the secondary-side smoothing capacitor C3 through the windings Ns and Np to the primary-side smoothing capacitor C1, since xe2x80x9cnumber of turns of winding Ns greater than number of turns of winding Ni.xe2x80x9d
As the capacitor C1 is charged, the current being charged thereinto, i.e., the drain current Id of the MOSFET Q1, decreases and reaches zero finally.
At a time t5, the MOSFET Q3 is still on. This means that the current IL flowing through the coil L1 also flows through the windings Ni and Ns into the winding Np. Consequently, the output capacity of the MOSFET Q2, which has been charged in reverse polarity during the time t3-t4 period, is now charged up to the forward voltage level of the MOSFET Q2""s body diode. When the output capacity of the MOSFET Q2 is charged, the body diode thereof turns on and charges the capacitor C2. As the capacitor C2 is charged, the current IL of the coil L1 decreases.
Because of resonance produced by the capacitor C2, the output capacity of the MOSFET Q2 and the winding Np, a current begins to flow from the capacitor C2 to the winding Np. Consequently, the polarity of each winding reverses, causing the winding Nfl to turn on the MOSFET Q4 and therefore the current IL to flow in the opposite direction.
Because of resonance produced by the capacitor C2, the output capacity of the MOSFET Q2 and the winding Np, the polarity of each winding reverses once again, causing the winding Nfw to turn on the MOSFET Q3.
Since the converter""s behavior during the above-mentioned period is the same as that during the time t3-t4 period and the polarities of each voltage and current at a time t8 are also the same as those at the time t4, oscillation continues.
As described heretofore, the prior art DC/DC converter is placed in intermittent operation as a measure against losses under a light load. However, energy stored in the secondary-side smoothing capacitor C3 is re-generated on the primary side because of abnormal oscillation caused when the DC/DC converter is at a stop, causing the output voltage Vo to decrease rapidly. For this reason, losses at a light load increase, causing the problem that the period during which the DC/DC converter in intermittent operation is at a stop, becomes shorter.
An object of the present invention is to provide a DC/DC converter and a control method thereof whereby losses at a light load are reduced.