Modern data processing equipment utilize video display devices which provide a wide range of picture element (pixel) resolutions. For example, a computer graphics adapter (CGA) video interface card for an IBM-compatible personal computer provides a video image having 64,000 (320.times.200) pixel or dot positions in each displayed image, while a high-resolution 1k variable graphics adapter (VGA) video interface card provides 786,432 (1,024.times.768) pixel positions. Each of these video images is displayed in about the same amount of time, consequently, the frequency of the clock signal used to display the 1k VGA image is approximately twelve times that of the signal used to display the CGA image. In addition, there are other computer graphic interfaces which provide even greater resolution and thus, employ even higher-frequency dot clock signals.
In some computer graphics applications, it may be desirable to provide several levels of resolution. For example, a relatively low resolution display format may be preferred for preparing text or for determining image layout, since the smaller number of pixels in the image may translate to less elapsed time to generate or change the image. However, a relatively high-resolution display format may be preferred for applications such as desktop publishing in which high-quality text may be combined with high-resolution graphic images.
A VGA interface card, such as the VGA Wonder.TM. available from ATI Technologies Inc., is compatible with several video graphic display formats including CGA, EGA (640.times.350), VGA (640.times.480), Super VGA (800.times.600) and 1k VGA. In addition, the interface card supports text display formats having fewer pixels per screen image that even CGA. A flexible video interface of this type may use several different pixel clock signals having frequencies that range from approximately 100 MHz for the 1k VGA format to approximately 20 MHz for the CGA and text display formats.
Many of the currently available video display interface cards employ several clock oscillators or several resonant crystals with a single oscillator to produce these different clock frequencies. This duplication of circuitry increases the complexity and cost to the video display card over that of a card which employs a single oscillator having a single resonant crystal.
One clock generator integrated circuit (IC) which uses only a single crystal to provide multiple clock frequencies is the ATI8900, also available from ATI Technologies Inc. Using a 14.31818 MHz resonant crystal, this integrated circuit may be programmed to provide ten internally generated clock signals ranging in frequency between 28.322 MHz and 44.9 MHz. However, this IC does not generate the 100 MHz clock signals used for the high-resolution displays. Clock signals at these frequencies are generated externally and channeled through the IC via three input terminals.
Another clock signal generator IC is the Dp8512 manufactured by National Semiconductor Corporation. This IC produces multiple synchronous clock signals having different frequencies. These clock signals are produced simultaneously and are used to drive different components of a video graphics display system. All of these signals are referenced to a single clock signal, the frequency of which defines the pixel resolution of the video display. The IC may provide pixel clock signals having frequencies of up to 225 MHz. The frequency of the clock signal provided by this IC may be set by programming two internal counters which are configured with a voltage controlled oscillator (VCO), phase detector and loop filter in a phase locked loop (PLL) arrangement. The frequency of the signal produced by the VCO is determined by an external capacitor and Varactor diode, as well as by an external resonant crystal.
The VCO's in both of these IC's operate effectively in their respective PLL's only over a limited range of frequencies. This limited range occurs because the changes to the VCO circuitry or to its control voltage which tend to change its free-running frequency also tend to change its gain. The gain of the VCO combined with the gains of the other components of the PLL determine the response time of the PLL to a phase error. Thus, to accommodate applications which may require differing response times, it may be desirable to modify other components of the PLL to achieve a desired overall loop gain. In some instances the desired loop gain may not be realizable due to limitations of the other components or due to interfering noise signals.
Both of the clock signal generation IC's described above use external feedback capacitors in the circuitry for their respective VCO's. This is disadvantageous since the external capacitor uses two connecting pins on the IC and since it provides an entry point for interfering electrical signals (i.e. noise) which may affect the stability of the pixel clock signal.