1. Field of the Invention
The present invention generally relates to data processing systems, particularly diverse computing systems that require differing hardware designs, and more specifically to a method and system for configuring a development chip to allow rapid prototyping of customized user solutions.
2. Description of Related Art
Modern data processing systems are used in a wide variety of applications. The most commonly known data processing systems are the popular desktop and portable computing systems referred to as personal computers (PCs), as well as the more powerful mini-computers and mainframe computers. Those machines are general purpose computing systems, but there are many specialized data processing systems that are adapted for more narrow purposes. These special applications include, for example, process control, telecommunications, diagnostics, multimedia generation (visual rendering or audio signal processing), network connectivity, etc.
Certain hardware components are generally found in all of the foregoing data processing systems. First, every computing system has one or more central processing units, or cores. A processor core contains various execution units, such as arithmetic logic units, for carrying out program instructions, and various registers, such as general purpose or special purpose registers, which temporarily store operand data that is used by, or output from, the execution units. Every data processing system also uses one or more memory devices for storing data and program instructions. These memory devices typically include volatile memory, such as random-access memory (RAM). Many different types of RAM may be utilized, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and synchronous dynamic random-access memory (SDRAM). The volatile memory may be arranged in a single system array, or in a distributed array, such as with a non-uniform memory access (NUMA) design. Non-volatile memory devices are also used, e.g., read-only memory (ROM) which stores the boot instructions (firmware) for starting up the computing system. Other types of non-volatile memory may additionally be provided, such as electrically-erasable read-only memory (EEPROM). The processor cores are further coupled to a variety of peripheral, or input/output (I/O) devices. Several of these devices are provided primarily for the user interface, and include features such as a keyboard, display, and graphical pointing device (e.g., a “mouse”). Other peripheral devices may be more specialized in nature.
Given the diversity in the various functions of data processing systems, it is not surprising that they have significant differences in both hardware components and interconnection schemes. For example, there are many different bus standards for interconnecting the processor core(s) to the remaining components. These standards include, among others, the Industry Standard Architecture (ISA) bus, and the Peripheral Component Interconnect (PCI) bus. Different protocols or connectors may also be utilized to communicate with the peripheral devices, e.g., parallel ports or serial ports. These differences present serious challenges to manufacturers who attempt to fabricate multiple types of computing systems.
Current trends are moving to “system on a chip” solutions. They often include a number of cores whose function, depending upon their use with other cores, can be quite different. A simple example of this is a multi-processor system wherein one processor operates as the “service” processor, to manage and coordinate the functions of the remaining processors, or application-specific integrated circuits (ASICs). Due to the complexity of these designs, verification of the configuration along with the user logic is desired before proceeding to the costly and time-consuming process of releasing the final design, and then debugging system level errors. In the past, system level designers have depended upon either software simulation, or complex hardware emulation systems, to verify the designs. Both of these approaches, however, have significant drawbacks.
In the case of the software model, the simulation time is excessively long, typically resulting in an incomplete functional test. The hardware emulation method requires a large emulation box, where the source design is compiled into field programmable gate arrays (FPGAs), and a test pad is available for the simulation interface. While this method is faster than software simulation, it is expensive, complex, non-portable, and often still fails to operate at the full functional speed. Since these FPGA's often cannot function at full operational speed, then real-time applications cannot be adequately tested. The PGA approach also fails to provide adequate support for varying memory configurations.
A third option is to fabricate a unique test chip for each customer, but then the customer cannot experiment with different configurations during system bring-up, and fabricating a unique version for each configuration is very expensive. It would, therefore, be desirable to devise an improved method of creating rapid prototype data processing systems that would allow a single hardware solution to satisfy the complete matrix of possible legal configurations of user selected cores. It would be further advantageous if the method provided for quick re-configuration during the verification/debug period to best optimize the total solution of the user system, and thereby ensure that unique ASIC logic will correctly function with the internal control/buses of the selected cores.