1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to improving alignment/overlay performance for a fin field effect transistor device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET includes a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
Overlay performance is a known critical factor for advanced semiconductor manufacturing of 3-D FinFETs. Over time, these overlay performance requirements have become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable in some fin-based alignment mask concepts due to changes in lithography and etching process conditions. For example, as shown in FIG. 1(a)-(b), an alignment and overlay mark 10 of a prior art device 12 receives finification due to the mandrel overlay and etch process. In this case, image quality is poor for mark 10 because the fin profile, line end shortness, and line edge roughness for the fin greatly impact overlay measurement quality.