Semiconductor devices such as integrated circuits (ICs) are fabricated in or on a surface of a semiconductor substrate or wafer that is subsequently divided or diced into a number of discrete chips or dies each having a device or IC formed thereon. One or more dies are then enclosed in a package that provides physical and chemical protection of the die(s) while electrically connecting it with outside circuitry. Packages for semiconductor devices are available in the very wide variety of designs depending on the desired electrical connections out of the package, required heat dissipation, and other physical requirements, such optical transparency.
Molded packages, such as that shown in FIG. 1A, are produced by attaching the die 102 to a flag or die paddle 104 of a leadframe 106, electrically coupling circuit elements on the die to conductors or lead fingers 108 on the lead frame using a bonding wire 110, and encapsulating the die and at least a portion of the lead frame in a plastic molding compound 112 using an injection or transfer molding process. Molded packages 100 provide a number of advantages including a lower per unit cost, and the ability to simultaneously package multiple dies in a sheet or a number of strips, which are subsequently divided to yield individually packaged devices or ICs. However, molded packages 100 also suffer from a number of drawbacks or disadvantages.
Referring to FIGS. 1A and 1B, conventional molded packages 100 are asymmetrical along a vertical axis, often having a full-metal die paddle 104 exposed on the bottom of the package, while the bulk of the molding compound 112 is above the plane of the leadframe 106. This arrangement is problematic when the molding compound 112 has a high coefficient-of-thermal-expansion (CTE) relative to those of leadframe 106 and or die 102. For example, an optically clear plastic molding compound typically has a CTE of from about 60 to about 70 parts-per-million (ppm), while a copper (Cu) based leadframe has a CTE of about 15 to 20 ppm, and a silicon die a CTE of about 3 to 5 ppm. The mismatch of CTEs can produce warpage stresses in the resulting package 100 both during packaging and during in operation of the finished device, which can potentially delaminate the package, the packaged device or break electrical connections thereto.
In addition, bending or warpage of the package 100 can interrupt or degrade electrical or optical coupling to adjacent components. This is particularly a problem with optical devices packaged in an optically clear molding compound since bending or other mechanical stresses imposed thereon may cause degradation of optical performance by inducing changes in optical transmission properties of the package.
A block diagram illustrating a cross-sectional side view of the package 100 of FIG. 1A exhibiting warpage stress on the package caused by CTE mismatch is shown in FIG. 1B. In the example shown, optoelectronic devices on the die 102 were packaged in a transfer molding process using a heated optically clear, plastic molding compound 112. During cooling of the molded package 100 the top portion, consisting mainly of plastic molding compound, experiences a much greater contraction than the lower portion containing the metal leadframe 106, resulting in the warpage 114 shown.
Accordingly, there is a need for a low cost molded package and packaging method for semiconductor devices and ICs that reduces warpage stress due to CTE mismatch. It desirable that the package and method be suitable for use with optically clear plastic molding compound having a high CTE. It is still further desirable that the package and method be compatible with an automated backend assembly or packaging process.
The present invention provides a solution to these and other problems, and offers further advantages over conventional processes.