Video audio processing devices typically go to a standby state when power is turned off by remote control. In the standby state, only minimum necessary circuit elements (for example, a standby microcomputer) are provided with power, and the others (for example, a video signal decoder, an audio signal decoder, etc.) are not provided with power. This allows the device to be ready for use more quickly as compared to when the main power is turned on, while lowering power consumption.
Various dedicated signal processors or signal processing blocks (for example, a TS (Transport Stream) decoder, a video decoder, an audio decoder, etc.) are particularly incorporated into digital television broadcast receivers or the like. There are various compression coding methods for video and audio signals. Thus, in order to be compatible with all of those methods, each signal processing block loads a program into an internal instruction memory thereof and operates. Such programs are stored in an auxiliary storage, such as a flash memory, and are retained even if power is not supplied.
When the video audio processing device returns from the standby state, a program stored in the auxiliary storage is first loaded into a CPU that controls each signal processing block, and the CPU starts operating. Thereafter, programs for the respective signal processing blocks are read from the auxiliary storage by the CPU and then loaded into the instruction memories in the respective signal processing blocks. And when the loading of the programs into the signal processing blocks is complete, each signal processing block is activated by the CPU, and the video audio processing device returns to a normal operational state. For example, in the case of a digital television broadcast receiver, broadcast contents are displayed on the screen. Therefore, an improvement of performance relating to access to the auxiliary storage is an important factor in achieving a quick return from the standby state. A technique has been conventionally known in which performance relating to access to a flash memory, in particular, performance relating to write access, is improved to enhance the speed of the entire system (see Patent Document 1, for example).    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-529399