In the process of designing an integrated circuit, a circuit schematic representing the functional design of the circuit is converted to a circuit layout, which represents the physical layout used for manufacture. This conversion often introduces errors into the circuit layout which are corrected by a designer prior to manufacture. These errors are referred to as layout versus schematic (LVS) errors, and can include shorts, opens, incorrect connections between components, and port or net naming errors. While certain types of LVS errors, such as shorts or opens, are trivial to debug, incorrect connection and naming errors can be difficult to debug. LVS analysis tools typically report the locations in the layout and schematic where the LVS tool identified the errors, but these locations may be far away from the root cause of the error. In such situations, a designer has to manually search the layout and the schematic to locate the root cause. In some cases, the designer may be unable to find the root cause.