Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a protective covering. The semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by semiconductor dies and yet increase the capacity and/or speed of the resulting encapsulated assemblies. To meet these demands, semiconductor die manufacturers often stack multiple semiconductor dies vertically on top of each other to increase the capacity or performance of a microelectronic device within the limited volume on the circuit board or other element to which the semiconductor dies are mounted. In some semiconductor die stacks, the semiconductor dies are electrically interconnected using through silicon vias (TSVs). The TSVs enable the semiconductor dies to be stacked close to each other such that adjacent semiconductor dies are spaced apart from each other by only relatively small vertical distances. This, along with the relatively low inductance of the TSVs, enables higher data transfer rates. Also, since the dies are stacked vertically, the total footprint of the stack corresponds to the footprint of the largest die in the stack.
However, one concern with semiconductor die stacks is power delivery. For example, the current draw from semiconductor dies in the stack can be significant when the semiconductor dies are performing high power operations, which can result in poor power delivery to, for example, the uppermost semiconductor dies in the stack. Conventional methods for improving power delivery in semiconductor die stacks include increasing the TSV count of each semiconductor die in the stack to reduce the resistance of the power network. However, increasing the TSV count of the semiconductor dies often requires increasing the size of the semiconductor dies. Accordingly, there remains a need in the art for methods and systems for improving power delivery in semiconductor die stacks.