1. Field of the Invention
The present invention relates to a delay circuit, and in particular to an improved delay circuit which is capable of controlling an effective pulse width of a signal and implementing a proper delay time for a signal having a shorter pulse.
2. Description of the Background Art
Generally, for implementing predetermined functions using a plurality of semiconductor devices, a semiconductor circuit is designed to have a proper delay time of a corresponding signal for a synchronization between signals of the circuit. For example, in a dynamic random access memory, a predetermined delay time of an address signal is implemented to ensure address transition detection.
As shown in FIG. 1, the known delay circuit includes first and second inverters 1 and 2 as an inverting unit and a resistor R and a capacitor C connected between the first and second inverters 1 and 2. The delay time is determined by a logic threshold voltage of an inverter, a resistance component and a capacitance component of the capacitor.
The signal wave forms at each node are shown in FIGS. 2A through 2F. FIG. 2A illustrates an input signal IN, FIG. 2B illustrates a signal inverted by the first inverter 1, FIG. 2C illustrates a signal of the resistor R and the capacitor C, and FIG. 2D illustrates a signal inverted by the second inverter 2. The input signal IN is delayed by the delay amount of T as shown in FIG. 2D.
The signal waveform at the node A1 has a smoothly dropping curve by the resistor R and the capacitor C, and a PMOS transistor (not shown) constituting the second inverter 2 is operated at the point where the signal is delayed by the threshold voltage of the PMOS transistor. The cascaded delay circuits provide a signal (A5; FIG. 2F) having a predetermined delay time with respect to the input signal.
In the semiconductor circuit, when implementing a high speed signal process, the higher frequency of an input signal makes the pulse width narrower. In the above state, when delaying the signal much longer, the delay circuit as shown in FIG. 1 may be used. Since the delay circuit provides a lengthy delay time, if the width of the input pulse is shorter, the distortion is increased, so that the level of the input signal may be changed prior to the delay, and the signal itself may disappear. Namely, during the time over which one pulse is inputted, the next pulse is inputted, so that the pulse loss occurs.
In order to overcome the above problems, a plurality of delay circuits each providing a short delay time may be used for outputting a signal having a predetermined delay time.
For implementing a fine adjustment of the delay, a switching unit S is adapted to each delay circuit as shown in FIG. 3. Namely, in order to implement the fine delay time, a plurality of delay circuits which are capable of providing a short delay time are connected in multiple stages, so that the delay time is obtained based on the option with respect to the on/off setting of the switching unit S.
However, the above-described construction has the following drawbacks. Since the entire current of the circuit is the summed current which is generated by the operation of each inverter, so that the number of stages is proportional to the current consumption. Therefore, the current consumption is increased. Furthermore, when physically implementing the above circuit, the layout area of the circuit is increased. When the CMOS circuit is used, since the bulk of the NMOS transistor and the PMOS transistor applied on the semiconductor substrate is different, a larger occupied area relative to other devices is required.
In the known delay circuit, the rising time and falling time of the signal are similar thereby causing a different active width. Namely, when the signal is activated to a high level, the effective pulse width (until the pulse signal becomes a low level) is different from the pulse width of the inputted signal. This causes the effective pulse width to be different, resulting in a varied duty ratio.
In order to overcome the problem that the duty ratio is varied, the inverted signal may be used instead of using an activation with a logic high level, and then the signal may be delayed. To this end, the PMOS device and NMOS device are required to be used as a CMOS inverter for a duty ratio adjustment.
Therefore, the semiconductor devices are additionally used for increasing the device mounting area, so that it is difficult to implement a highly integrated device. When a fine adjustment is required for a delay time selection, more layout area is required.
As the dynamic random access memory device is highly integrated, and the operational speed of the same is increased, the delay circuit is used as an important element for eliminating a skew between a clock and a signal and implementing an accurate timing. Namely, the input signal should be transmitted to a predetermined element without error, and the duty ratio should be accurately adjusted.