Different portions of the same overall circuit may be required to operate at different clock speeds, and furthermore one or more of those clock speeds may be variable. Each portion operating at a given clock speed defines a respective clock domain. For example, FIG. 1 shows schematically an integrated circuit comprising a first circuit portion A clocked by a first clock signal clk-A defining a first clock domain A, and a second circuit portion B clocked by a second clock signal clk-B defining a second clock domain B. In this example, the first circuit A is to transfer data to the second circuit portion B, and furthermore the frequency of each of the first and second clock signals clk-A and clk-B is variable.
However, there are two issues with this: firstly, ensuring the data is passed from one clock domain to another in a synchronised manner; and secondly, ensuring that the transfer remains synchronised even when one or both of the clocks changes speed.
There are a number of standard mechanisms for crossing clock-domain boundaries between components of a silicon chip or other circuit. However, whilst these can provide sufficient bandwidth, they suffer from having significant latency due to the need to resolve metastability and for most high-bandwidth schemes to exchange handshake control signals in both directions across the interface. For high frequency systems, special high-gain flip-flops may also be required in order to provide a sufficiently high probability of resolving meta-stability.
Similarly, clock-frequency changes typically require clocks to be stopped whilst the dividers change frequency so that logic is not subject to glitches (which violate timing and cause functional errors). They also may require that traffic across the interface is stopped so that the interface is in a known “safe” state and accesses cannot be lost or corrupted.
It would be advantageous to provide an improved way of passing data between variable clock domains.