Embodiments of the present invention generally relate to integrated circuits and the processing for the manufacture of semiconductor devices. More particularly, embodiments of the present invention relate to flash EEPROM cell architecture for providing small cell size to nonvolatile memory devices.
In the semiconductor industry, Electrically Erasable Programmable Read-Only Memory (EEPROM) is classified as a non-volatile memory device because it can retain the stored data without the need of a power supply. Flash memory cell is one of the rapidly developed EEPROM memory devices. Since the structure of EEPROM is more complex compared to that of DRAM, a large integration of EEPROM memory also becomes more difficult.
In an EEPROM, each memory cell often has two transistors: an MOS transistor for control and a floating gate transistor for storage. The storage part of an EEPROM cell resembles a permanently-open or closed MOSFET transistor having two gates: a floating gate and a control gate. When the “floating gate” is charged, it holds the charge and impedes the flow of electrons from the control gate to the silicon (the 0 or 1 is determined by whether the actions of the control gate are blocked or not). Charging is accomplished by grounding the source and drain terminals and placing a voltage on the control gate. Applying a reverse voltage via the MOSFET transistor causes the charge to dissipate into the substrate.
The conventional flash EEPROM cell has two states (for storing binary information) depending on whether a charge is present at the floating gate or not. This arrangement has a disadvantage that the chip size increases proportionally with the number of memory cells. Typically, non-volatile memory devices have two types of structure: a stack gate structure and a split gate structure.
A stack gate structure generally includes a control gate on top and a floating gate underneath the control gate. The stack gate structure generally faces an over-erased problem. If a memory cell in the memory array architecture is over-erased, an undesirable leaking current will occur during the read operation of the other memory cells. The process for manufacturing a stack-gate memory cell is generally simpler than that having a split-gate structure. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have; because of that the split-gate structure of memory cell is more widely used.
The EEPROM memory device having the split gate structure includes a control gate, a floating gate and can have an additional gate known as a select gate, wherein the control gate is also disposed above the floating gate, but these two are laterally offset. Although the split-gate memory cell has no over erase problem, the formation of the additional gate, i.e. the select gate, requires more complex processing steps and consumes additional chip area. The split-gate memory cell is thus, generally larger than the stack-gate memory cell. The split-gate memory cell is difficult to scale down because the select gate and/or the control gate are not self-aligned to the floating gate.
Accordingly, it is seen that an improved cell architecture for split-gate EEPROM for providing smaller cell size is desired.