1. Field of the Invention
The present invention relates to the field of integrated circuits and more specifically to the implementation of buffer amplifiers in MOS-type integrated circuits.
2. Discussion of the Related Art
Generally, in an integrated circuit, the state of several primary components connected to a common line or bus has to be controlled based on logic signals. For this purpose, buffer amplifiers, the function of which is to adapt the impedance of the logic signal to the bus to be controlled, are used. In the case where it is desired to implement this type of control in a very fast way and where there may be a relatively large number of devices to be controlled, the aggregate capacitance of all of the devices can be high.
FIG. 1 shows a current type of buffer amplifier used in MOS technology. This buffer amplifier includes a single inverter including two P-channel and N-channel complementary MOS transistors, respectively, P1 and N1, connected in series between a high supply potential Vdd and the ground. The gates of transistors P1 and N1 are connected together to an input terminal E, and the common drain of transistors P1 and N1 is connected to an output terminal S. The equivalent load of the line or bus connected to terminal S has also been shown in the drawing in the form of a capacitor C.sub.L.
When the input signal is at the low level, the voltage on output terminal S is at the high level, and conversely. This primary buffer amplifier exhibits, as is well known, the disadvantage of being poorly adapted to high frequency operation. This is essentially due to the presence of a P-channel MOS transistor which is intrinsically slower than an N-channel MOS transistor. Thus, the transitions of the output from the low level to the high level necessarily have a reduced speed. This is all the more disturbing as the load connected to the output terminal is highly capacitive.
To overcome this disadvantage, P-channel MOS transistors having larger dimensions are used in order to supply a control current of greater amplitude on the output line. Of, course, this solution goes against the general objective of reduction of the dimensions of semiconductor devices and of the integrated circuits which contain them.
A second solution consists of separating the line connected to terminal S into a number of lines and using a buffer amplifier for each line. This solution of course results in an increase of the general dimension of the circuit.
Thus, the two solutions conventionally put forward lead to an increase of the dimension of the integrated circuit, which is itself a disadvantage. In addition, the fact that the input capacitance of the buffer amplifier increases with the dimensions or the number of transistors that it contains is also a disadvantage. Accordingly, the upstream circuits meant to supply input signal E are also adversely affected.
Of course, it has also been conventionally attempted to implement various more complex circuits replacing the primary circuit of FIG. 1, but the major disadvantages described hereabove (larger dimensions, limited speed of switching to the high state, and high input capacitance) are not basically solved.
As a consequence, conventionally, when it is desired to control, at high speed, a bus likely to be highly capacitive, bipolar-type integrated circuits or bipolar and MOS mixed technology integrated circuits are used.