As integrated circuit feature sizes decrease, the gate dielectric thickness of field effect transistors (FETs) also decreases. This decrease is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions decrease to maintain the proper device scale, and thus device operation. Another factor driving gate dielectric thickness reduction is the increased transistor drain current realized from a reduced gate dielectric thickness. The transistor drain current is proportional to the amount of charge induced in the transistor channel region by the voltage applied to the gate conductor. The amount of charge induced by a given voltage drop across the dielectric is a factor of the capacitance of the gate dielectric.
In order to achieve increased capacitance, gate dielectrics made from oxides such as SiOx are now as thin as 10 Å. These extremely thin gate oxides result in increased gate-to-channel leakage current, however. Problems such as this have led to the use of materials that have dielectric constants that are greater than the dielectric constant of silicon oxide, which has a k value of about 3.9. Higher k values, for example 20 or more, may be obtained with various transition metal oxides, such as an oxynitride film. These high-k materials allow high capacitances to be achieved with relatively thick dielectric layers. In this manner, the reliability problems associated with very thin dielectric layers can be avoided while improving transistor performance.
There are, however, fabrication problems associated with forming gate dielectric layers that include high-k materials. Generally, semiconductor fabrication utilizes one or more cluster tools, which comprises various process chambers that can be utilized in association with a wafer handling system or device to perform a variety of semiconductor processes. These processes can include, for example, oxidation, nitridation, annealing, deposition processes, and the like.
In the example of forming a gate dielectric comprising an oxynitride film, a cluster tool may be used to perform an oxidation process, a nitridation process, and an anneal process, wherein each process is typically performed in different process chambers. Between chambers, a wafer is transferred through a loadlock chamber. The loadlock chamber typically has a non-adjustable cooling plate maintained at a specific temperature to cool the wafer. The oxidation chamber, however, fails to maintain a uniform temperature across the wafer. It has been found that this variation in the temperature across the wafer may result in a variation in the equivalent oxide thickness (EOT), which in turn results in a variation of the Idsat between FETs. This variation may be observed not only with FETs on different wafers, but also between FETs on different dies on a single wafer and between FETs on a single die. The variation in the Idsat may adversely affect the circuitry and reduce yield, thereby increasing costs.
Accordingly, there is a need for a method and a structure to maintain a more uniform temperature over a wafer during processing.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.