An electrostatic discharge (ESD) event occurs when there is a transfer of energy between bodies that have different electrostatic potentials either through contact or through an ionized ambient discharge. Integrated circuits (ICs) with inadequate ESD protection are subject to catastrophic failure-including ruptured passivation, electrothermal migration, splattered aluminum, contact spiking, and dielectric failure. Sometimes an ESD event can damage a device even though the device continues to function. Damage of this type constitutes latent defects, which are hard to detect and significantly shortens the life of the device.
Integrated circuit (IC) manufacturers employ ESD protection circuits to protect ICs from damage due to ESD caused by the occurrence of an ESD event. A conventional ESD protection circuit 100 is shown in FIG. 1. These devices are used to drain ESD current 103 (divert the potentially damaging charge away from sensitive circuitry 101) upon the occurrence of an ESD event 105. In many cases ESD is received via input pin 107. There are many different types of ESD protection circuits that are currently available.
One shortcoming of conventional ESD protection circuits is their susceptibility to latchup. Latchup is a significant problem since an IC may stop functioning if ESD causes latchup in the ESD protection circuit. Moreover, the resulting unintentionally sustained supply current may destroy the IC.
Latchup of the ESD protection circuit can occur if the snapback trigger voltage and the snapback sustaining or holding voltage are not properly selected. The snapback trigger voltage and the snapback holding voltage are properly selected if the snapback trigger voltage is selected to be less than the IC oxide breakdown voltage and the snapback holding voltage is greater than the ESD protection circuit operating voltage.
When the holding voltage is less than the ESD protection circuit operating voltage and the MOSFET snapback is triggered, latch up can occur because the snapback condition may be sustained by the higher operating voltage. When the snapback trigger voltage is set too high then damage to the MOSFET can occur if an ESD event causes a voltage that is greater than the oxide breakdown voltage.
FIG. 2 shows a graph of a device whose snapback holding voltage VH is less than the device operating voltage Vdd. In FIG. 2, the operating voltage Vdd is more than sufficient to sustain the snapback condition. As previously discussed, the resulting unintentionally sustained supply current may cause enough damage to destroy an IC.
IC manufacturers attempt to select MOSFETs that have the proper snapback trigger voltage and the proper snapback holding voltage for use in ESD protection devices for IC applications. However, because this selection process is constrained by the IC manufacturing process and by circuit performance considerations, the optimal combination of snapback trigger voltage and snapback holding voltage is not always available. It should be appreciated that the MOSFET may fail if the operating voltage of the IC is higher than the snapback holding voltage and an operating voltage spike caused by an ESD event drives the MOSFET into a snapback condition that is sustained by the operating voltage. As discussed above, this may lead to a failure of the entire IC.