The manufacturing process of semiconductor devices and similar products such as flat panel displays, MEMS and memory discs, involves numerous process steps where layers are deposited, etched, coated and abraded by polishing. To control process step performance for each unit running in the production line it is important to monitor the physical parameters of the layers before, during, and after the respective process step. Some of the process steps involve selective etching or deposition of the layers to form patterns on the wafer such as metal lines, dielectric or Si trenches, Photo resist patterns etc.
Methods of measuring the layer thickness are well known and may include amongst others:
Reflectometry where interference between the reflected light from the top surface of the layer and the bottom interface of the layer can be traced back to the layer thickness, refractive index and extinction coefficient, and
Ellipsometry where the polarity difference between the light reflected from the top and bottom interfaces can be traced back to the layer physical parameters.
The most accurate measurements are achieved on samples where the layer parameters, i.e. thickness, refractive index and extinction coefficient are constant within the measuring beam spot area. The units being produced in the process, such as semiconductor devices, are constructed from a very complicated pattern structure with different layer thicknesses at different locations on the device. The space and width of the patterns vary but can be smaller than 0.1 micron, and the demands of technology constantly call for ever smaller features.
The common methods used in production lines to monitor process performance do not involve measuring production units at patterned areas but use instead samples not previously patterned which are run through the process and then measured using the classical methods of single layer measurement techniques.
Another way to avoid the complicated pattern structure is to include in the measurement tool a sophisticated alignment mechanism that pictures the device using a vision system, finds a large non-patterned area within the device using pattern recognition algorithms and navigates the measuring spot to the non-patterned area using a highly accurate motion mechanism. The method requires the measurement spot to be small enough to fit the non-patterned areas within the production units. Once alignment is complete the measurement is made on the non-patterned area using classical methods. Reference is herein made to FIG. 1b for an example of a measuring spot selected over a non-patterned area of a wafer during the manufacturing process, from which the thickness D may be obtained.
The above methods have limitations when used in the production line. Measurements on evidence samples or on non-patterned areas do not always correlate with the true thickness of the layers on top of the patterned areas, where different physical phenomena occur. The special run that is needed to produce the test sample has the effect of reducing actual production time using the machines and consumes additional raw materials. On the other hand measuring actual production units using the alignment technique takes time, requires sophisticated hardware and cannot be performed within the process chambers to monitor the process in real time.
PCT Patent Application No. WO 0012958 describes a measurement system known as TMS, which uses wide spot light beams reflected from within layers of a patterned device surface to make measurements of the lateral variation of thickness of transparent layers and in particular SiO2 layers. Unlike existing methods it can be used even over a heavily patterned area of a wafer such as that shown in FIG. 1c. The reflectance coefficient is transformed typically into the frequency domain from which it is possible to determine SiO2 layer physical parameters by separating information relating thereto from information coming from layers having different parameters.
A disadvantage with the TMS method is that there is a limit to the resolution of the measurements. As wafer layers get smaller it is more difficult to resolve between the layers using TMS, and higher resolution accuracies require more intensive calculation. The more intensive calculation undermines the principle advantage of TMS, which is that it is able to work in real time.