The drive for increasing DRAM densities has given rise to a number of different DRAM cell configurations. One way in which to classify DRAM cells having capacitors formed above the substrate, is to designate the vertical position (layer) of the storage capacitor relative to the vertical position (layer) of the bit line. This gives rise to two, general, self-descriptive groups; bit line-over-capacitor (BOC) cells, and capacitor-over-bit line (COB) cells. For BOC cells, the bit line contact is formed by etching a contact hole after the storage capacitor has been formed. As a result, the location of the bit line can limit the lateral extent of the storage capacitor. An example of a BOC cell is set forth in "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS" by Ema et al. appearing in IEDM 1988, pp. 592-595. The BOC cell appears in FIG. 1 of Ema et al. Other examples of BOC cells are set forth in U.S. Pat. No. 5,504,704 entitled SEMICONDUCTOR MEMORY DEVICE and issued to Sato et al. on Apr. 2, 1996, U.S. Pat. No. 5,188,975 entitled METHOD OF PRODUCING A CONNECTION HOLE FOR A DRAM HAVING AT LEAST THREE CONDUCTOR LAYERS IN A SELF ALIGNMENT MANNER issued to Kojima et al. on February, and in "Fully Self-Aligned 6F2 Cell Technology for Low Cost 1Gb DRAM" by Aoki et al. appearing in 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 22-23.
Unlike most BOC cells, COB cells provide more lateral room for the location of the storage capacitor. An illustration contrasting a COB cell with a BOC cell is set forth in FIG. 11 of Ema et al. The capacitor of the COB cell extends over both the access transistor gate and the bit line, and is limited in the lateral direction only by the adjacent storage capacitor.
Examples of other COB cells are disclosed in U.S. Pat. No. 5,428,235 entitled SEMICONDUCTOR MEMORY DEVICE INCLUDING IMPROVED CONNECTION STRUCTURE TO FET ELEMENTS and issued to Shimizu et al. on Jun. 27, 1995, U.S. Pat. No. 5,231,043 entitled CONTACT ALIGNMENT FOR INTEGRATED CIRCUITS issued to Chan et al. on Jul. 27, 1996, and in U.S. Pat. No. 5,053,351 entitled METHOD OF MAKING STACKED E-CELL CAPACITOR DRAM CELL issued to Fazan et al. on Oct. 1, 1991.
As DRAM densities continue to shrink, more complex manufacturing processes utilizing multiple conductive layers are needed to achieve acceptable cell capacitance while reducing DRAM cell size. This requires minimum tolerances in the placement of contacts and/or vias with respect to underlying conductive layers. Despite minimum tolerances, the possibility of unwanted shorts between the contact/vias and underlying layers is eliminated by ensuring that sufficient interlayer dielectric thickness exists therebetween. In order to reduce such tolerances, it is known in the prior art to use self-alignment techniques for both BOC and COB cells. Self-alignment techniques typically ensure that lower conductive layers are sufficiently insulated so as to allow for the overlap of a subsequently etched contact hole or via. For example, in the Kojima et al. patent and the Aoki et al. article, both the capacitor contacts and the bit line are self-aligned with the word lines. In both of these cases the word lines are isolated by a top dielectric and sidewall dielectrics. In the Chan et al. patent, differential dielectric deposition techniques followed by a blanket anisotropic etch, are used to form a self-aligned capacitor contact.
Commonly owned, copending U.S. patent application Ser. No. 08/456,090 discloses a BOC DRAM cell having a capacitor contact that is self-aligned with a word line, and provides increased capacitance.
Increasing the number of self-aligned steps used in the fabrication of an integrated circuit reduces the constraints on the placement of underlying layers, allowing for more compact designs and thus higher densities.