(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating a low leakage capacitor in an integrated circuit.
(2) Description of Prior Art
A continuing trend in the field of electronic integrated circuits is to increase the density of circuit functions per semiconductor unit of area. This increased density is obtained through reduction of the physical feature size of the elements in the integrated circuits.
For many manufacturers, dynamic random access memories (DRAM's) are the circuits which have the highest density and smallest feature size. However, the capacitance of a DRAM cannot be scaled at the same rate at which other circuit features are scaled back, beyond a certain point. One way therefore to maintain constant capacitance with decreasing feature size is to reduce the thickness of the dielectric material. This reduction brings with it increased susceptibility to higher leakage currents between the plates of the capacitor which in turn leads to a limitation on the voltage which can be applied across the capacitor. Since the charge stored is equal to the voltage across the capacitance times the capacitance, a reduction in the applied voltage requires a further increase in the capacitance in order to store the same charge, further aggravating the problem. The ability to store charge is then a function of either the thickness of the dielectric or the dielectric constant or the resistance to leakage current of the dielectric or the surface area of the capacitance.
Where silicon dioxide is the dielectric material, ultra thin dielectrics are difficult to fabricate as these dielectric films are particularly susceptible to pin holes and other defects. Furthermore, these films are prone to high leakage currents and complete breakdown of the dielectric barrier region if high voltages are placed across the capacitor.
A common technique to increase the dielectric constant of a capacitor is to increase the dielectric constant of the capacitor from that of pure silicon dioxide.
Another technique is to decrease the leakage current between the plates of the capacitor. Different types of dielectric materials (SiO.sub.2, Si.sub.3 N.sub.4, Ta.sub.2 O.sub.5) sandwiched between the two electrodes of a capacitor can result in the reduction of leakage current between the capacitor plates but this reduction is of limited extent. Additional methods and techniques are therefore needed to further reduce the leakage current.
The increase in surface area of the capacitance plates is in contradiction with the trend of reducing component size and is therefore an approach that is severely limited.
U.S. Pat. No. 5,352,623 (Kamiyama) shows a nitridation (RTN) process (using NH.sub.3 of a (forming a very thin SiON or Si-Rich oxide layer) (*) polysilicon electrode before a capacitor dielectric is formed there over. See Col. 4, lines 4-15. However, this generally shows the invention's (*), but differs from the exact process of the invention.
U.S. Pat. No. 5,438,012 (Kamiyama) shows a nitridation (RTN) process (using NH.sub.3) of a (*) polysilicon electrode before a capacitor dielectric is formed there over. However, this generally shows the invention's (*), but differs from the exact process of the invention.
U.S. Pat. No. 5,629,221 (Chao et al.). shows a N.sub.2 plasma treatment for a polysilicon gate, not capacitor.
U.S. Pat. No. 5,583,070 (Liao et al.) shows a N.sub.2 anneal of a polysilicon HSG layer and formation of a SiON/N/SiON capacitor dielectric layer.
U.S. Pat. No. 5,407,870 (Okada et al.) shows a N.sub.2 O or N.sub.2 plasma treatment to form a Si-Rich SiON layer over a poly electrode. Okada forms a Si-Rich SiON/O/Si-rich SiON capacitor dielectric layer. See cols. 3 and 4. Okada's N.sub.2 treatments do not include SiH.sub.4 in contrast to the invention's N.sub.2 and SiH.sub.4 plasma treatment. However, Okada is very close to the invention.
U.S. Pat. No. 5,250,456 (Bryant) shows a oxidation sealing layer over an ONO capacitor dielectric layer to reduce leakage and pinholes. See Col. 7, lines 21 to 34 and Col. 8. However, Bryant does not use the invention's N.sub.2 and SiH.sub.4.