1. Field of the Invention
The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment.
2. Description of the Related Art
In the development of a digital circuit design a simulation process is performed in order to verify the correct logical function and timing behavior. It is very important, that the model of the digital circuit design comprises correct runtimes of the signals. The simulation process may be performed by the support of an appropriate hardware and/or software.
According to the prior art the principle for validating the correct logical function and timing behavior of a circuit design comprises substantially the three following parts. In a first part only the logical function of said digital circuit design is validated. In a second part the timing behavior of said digital circuit design is validated. A timing analysis is performed in a third part. The functional validation on the one hand and the timing validation on the other hand are completely independent from each other.
FIG. 6 illustrates a flow chart diagram of a method for validating the logical function according to the prior art. The shown method refers to an RTL (Register Transfer Level) description, for example as a netlist description. In a first step 10 a model of a desired digital circuit design is provided. Said model is written in a Very High Speed Integrated Circuit hardware description language (VHDL). In a second step 12 a logic synthesis is performed. By this logic synthesis the abstract form of the digital circuit design is turned into a design implementation in terms of logic gates. The logic synthesis uses first assertions 24.
In a next step 14 a netlist is created. The netlist includes the elements of the digital circuit design and the connections between said elements. In particular, the netlist contains the information of those storage elements, which are provided for the real hardware. During a further step 16 a timing analysis is performed. The timing analysis uses second assertions 26. The result is checked in a step 17. If the result is not OK, then the method returns back to step 10 again. If the result is OK, then in a step 18 is shown that the netlist is clean from a timing point of view.
The steps 10, 12, 14, 16, 17 and 18 are used for the timing driven synthesis, the timing analysis and the release.
In a next step 20 a verification of the digital circuit design is performed. In the verification of step 20 the VHDL from the step 10 and the netlist from step 14 are used. The result is checked in a step 21. If the result is OK, then in a step 22 is shown that the netlist is clean from a logical and timing point of view.
The steps 10, 12, 14, 16, 17, 18, 20, 21 and 22 are used for the verification of RTL design description.
The logical function of the digital circuit design is validated within a cycle based environment on the basis of the RTL design description.
This approach according to the prior art has the disadvantage, that the timing assertions are not validated. Therefore timing problems could still exist and must be solved by a new release.