1. Field of the Invention
The invention relates in general to a method for fabricating a memory device, and more particularly to a method for fabricating a charge trapping memory device.
2. Description of the Related Art
In the process of fabricating a charge trapping memory device, such as a nitride charge storage device, a bottom oxide layer (BOX) is formed on a silicon (Si) substrate, and Si—O bonds are generated at the interface of the bottom oxide layer and silicon substrate as shown in FIG. 1A. Subsequently, a buried diffusion (BD) implantation is performed through the first oxide layer to form BD regions in the substrate. After the BD implantation, a lot of silicon dangling bonds are generated at the BOX/Si interface as shown in FIG. 1B. Afterwards, in a low-temperature metallization process, hydrogen (H) is introduced to form Si—H bonds at the BOX/Si interface as shown in FIG. 1C. Therefore, when the band-to-band tunneling hot hole (BTBT-HH) erase is performed on the nitride charge storage device 100 as shown in FIG. 1D, Si—H bonds at the BOX/Si interface are broken by hot holes (energy carried is about 4.7 eV), and an interface trap is generated at the interface of the BOX and the channel to carry negative charges QIT.
Referring to FIG. 1E, an I-V curve diagram of the device 100 is shown. Initially, there is no program-erase operation on the device 100, and the device 100 has an I-V curve C1. After program, the device 100 increases its threshold voltage VT to have an I-V curve C2. In a reliability test, the programmed device 100 is baked at a temperature of 150□ for about 24 hours to have an I-V curve C3. It can be seen from FIG. 1E that the I-V curve C3 after baking is very similar to the I-V curve C2 before baking, and thus the initial device 100 is stable. However, when the device 100 is programmed and erased by 10K cycles, the 10K-cycle programmed device 100 changes to have an I-V curve C4 whose slope is smaller than the curve C2 due to appearance of large amount of charges QIT. When the 10K-cycle programmed device 100 is baked for reliability test, the device 100 turns up to have a new I-V curve C5 whose threshold voltage VT is smaller than that VT of the curve C2 for an initial state by a value ΔVT.
As shown in FIG. 1F, when the cycle number of erase-program is increased, such as from 0 to 100K, the device 100 has an increasing sub-threshold swing SW, such as from 229.5 to 427 mV/dec due to the generation of the charges QIT at the BOX/Si interface whose density is increased from 0 to 1.6E−7coul/cm2, and the VT difference between program and erase state contributed by QIT is also increased from 0 to 41.9%. Therefore, the interface trap generation leads to SW degradation and thus reduces reliability of nitride charge storage products.