The present invention relates to a semiconductor integrated circuit and a method of designing the same and, more particularly, to a semiconductor integrated circuit suited to laying out standard cells.
Recently, the circuit scale of semiconductor integrated circuits is abruptly increasing, and demands for shortening the development time are also increasing.
Accordingly, a method has been extensively used which does not cause a circuit designer to plan and design a circuit configuration for realizing logic by himself or herself, but designs a circuit block for implementing a desired function by performing logic synthesis, placement, and routing by using software for performing logic synthesis.
In designing circuit blocks forming a semiconductor device as described above, a standard cell is used to perform logic synthesis and implement the circuit blocks by using software on the basis of functionally described design data.
A standard cell is a small-scale circuit (to be referred to as a cell hereinafter) preformed to realize basic logic, and prepared for each of a plurality of types of logic. In addition, even for single logic, a plurality of cells having different load driving forces, i.e., different sizes are prepared to control various loads. A set of a plurality of types of cells is called a standard cell library.
FIG. 7 is a plan view showing a conventional standard cell layout. In a surface portion of a semiconductor substrate, an N-type well region N1 and P-type well region P1 are placed. In the N-type well region N1, a gate electrode GE1 is formed on the substrate. On the two sides of the gate electrode GE1, a P-type impurity is ion-implanted to form P-type diffusion layers, thereby forming a PMOS transistor PM1. In the P-type diffusion layers, a source electrode SE1 is formed on a source region, and a drain electrode DE1 is formed on a drain region.
Likewise, in the P-type well region P1, the gate electrode GE1 is so formed as to extend, and an N-type impurity is ion-implanted on the two sides of the gate electrode GE1 to form N-type diffusion layers, thereby forming an NMOS transistor NM1. In the N-type diffusion layers, a source electrode SE2 is formed on a source region, and a drain electrode DE1 is formed on a drain region.
An N-type diffusion layer NS1 for fixing the substrate bias potential is placed in the end portion of the N-type well region N1, and a metal interconnection MW1 is placed around the N-type diffusion layer NS1. A P-type diffusion layer PS1 for fixing the substrate bias potential is placed in the end portion of the P-type well region P1, and a metal interconnection MW2 is placed around the P-type diffusion layer PS1. The source electrode SE1 is connected to the metal interconnection MW1, and the source electrode SE2 is connected to the metal interconnection MW2.
In the conventional device as described above, the diffusion layers and metal interconnections for applying the substrate bias potential to the P- and N-type wells formed in the surface of the semiconductor substrate are placed in a standard cell.
As these diffusion layers for fixing the substrate bias, impurities are ion-implanted by using masks to form the N-type diffusion layer NS1 in the N-type well and the P-type diffusion layer PS1 in the P-type well. As micropatterning progresses, however, it is found that the design rule for impurity ion implantation makes micropatterning difficult to perform, compared to the design rule for MOS transistor formation and metal interconnection. This makes it difficult to decrease a width d11 of the power lines MW1 and MW2 so formed as to surround the N- and P-type diffusion layers NS1 and PS1, respectively, shown in FIG. 7, thereby failing further micropatterning.
In addition, pin grids which define the pitch of metal interconnections is conventionally used as a reference for laying out cells and metal interconnections. FIG. 8 shows the pitch of metal pins MP as a pin grid pitch MGP.
Unfortunately, pin grids are not suited to the cell layout, so intervals between a gate electrode GE11 of a P-channel MOS transistor PM11 and N-channel MOS transistor NM11, a gate electrode GE12 of a P-channel MOS transistor PM12 and N-channel MOS transistor NM12, and a gate electrode GE13 of a P-channel MOS transistor PM13 and N-channel MOS transistor NM13 do not match the pin grids. In fact, the layout is random.
Consequently, as shown in FIG. 9, intervals between the gate electrodes of MOS transistors placed in the upper and lower portions are different from each other. More specifically, intervals between a gate electrode GE21 of a P-channel MOS transistor PM21 and N-channel MOS transistor NM21, a gate electrode GE22 of a P-channel MOS transistor PM22 and N-channel MOS transistor NM22, and a gate electrode GE23 of a P-channel MOS transistor PM23 and N-channel MOS transistor NM23 placed in the upper portion are different from intervals between a gate electrode GE24 of an N-channel MOS transistor NM24 and P-channel MOS transistor PM24, a gate electrode GE25 of an N-channel MOS transistor NM25 and P-channel MOS transistor PM25, a gate electrode GE26 of an N-channel MOS transistor NM26 and P-channel MOS transistor PM26, and a gate electrode GE27 of an N-channel MOS transistor NM27 and P-channel MOS transistor PM27 placed in the lower portion.
This layout difference between the gate electrodes of the upper and lower transistors poses the following problems.
Presently, in patterning the gate electrodes of MOS transistors by using a photomask, the phase of exposure light is shifted to increase the degree of micropatterning. Under the circumstances, if the gate electrodes of the upper and lower transistors are placed at irregular intervals as shown in FIG. 9, the degree of micropatterning is largely limited by the design rule.
FIG. 10 shows a diffusion layer D1 and gate electrodes G1 and G2 of transistors placed in the upper portion, and a diffusion layer D2 and gate electrode G3 of a transistor placed in the lower portion. Mask patterns MP1, MP2, and MP3 are placed in the upper portion as photomasks for patterning the upper gate electrodes G1 and G2. Mask patterns MP4 and MP5 are placed as photomasks for patterning the lower gate electrode G3. The positions of the upper gate electrodes G1 and G2 and the lower gate electrode G3 are different from each other.
Assuming that the first phase of exposure light comes in contact with the end face of the upper mask pattern MP1, the second phase comes in contact with the mask pattern MP2 adjacent to the mask pattern MP1, and the first phase comes in contact with the mask pattern MP3 adjacent to the mask pattern MP2. To pattern gate electrodes, therefore, different phases of light must come in contact with adjacent mask patterns.
Unfortunately, the lower mask patterns MP4 and MP5 are positioned between the upper mask patterns MP1 and MP3, so the second phase of light comes in contact with both of these lower mask patterns. This makes patterning impossible. A difference between the upper and lower mask patterns produces this phase contradiction.
To prevent this phase contradiction, it is necessary to increase the spacings between the upper mask patterns MP1, MP2, and MP3 and between the lower mask patterns MP4 and MP5, and this increases the cell size.
References disclosing semiconductor integrated circuits using the conventional standard cell are as follows.                Japanese Patent Laid-Open No. 10-154756        Japanese Patent Laid-Open No. 2001-168291        Japanese Patent Laid-Open No. 2000-22084        
As described above, a region for supplying the substrate potential conventionally interferes with micropatterning. In addition, although the cell placement is based on pin grids, the placement of the gate electrodes of MOS transistors is irregular. As a consequence, the cell area increases by large limitations on the design rules.