I. Field of the Disclosure
The technology of the disclosure relates generally to speed performance of integrated circuits (ICs), and more particularly to speed performance variations between processor cores in a central processing unit (CPU) provided in a system-on-a-chip (SoC).
II. Background
Integrated circuit (IC) computing devices have become commonplace throughout society. The increasing presence of such computing devices has accelerated in part because of the increasing functionality and versatility of such computing devices. This increase in functionality and versatility has been enabled by providing increasingly powerful processors in small packages as loosely recognized by Moore's Law. As a result, companies have been trying to increase functional integration in computing devices. Companies have also been trying to decrease package size of computing devices, especially in mobile computing devices.
In this regard, one technique to provide increased functionality in a computing device in a smaller package is by providing a system-on-a-chip (SoC). A SoC integrates a central processing unit (CPU) with other computing IC components (e.g., memory, memory controller, graphics processor, power management circuits, wireless radios, etc.) to provide the desired computing device, as opposed to providing these separate components off-chip from the CPU. Thus, while a SoC may be larger than a CPU chip, the SoC is typically smaller in size and contains much more functionality than providing a CPU in a dedicated CPU chip and the other computing components in separate chips.
Multiple processor core CPUs (also referred to as “multi-core processors”) are also starting to become widely adopted in SoCs to yield higher performance and for low power mobile applications. In this regard, FIG. 1 illustrates an example of a SoC 100. The SoC 100 in FIG. 1 includes four (4) processor cores 102(1)-102(4) provided in a single IC chip 104 (referred to as “chip 104”). One issue for the SoC 100 in FIG. 1 is that the processor cores 102(1)-102(4) may have different speed performances (i.e., maximum operating frequencies) even though the design of each processor core 102(1)-102(4) is the same. If core-to-core variations exist in the processor cores 102(1)-102(4) in the SoC 100 in FIG. 1, the overall chip 104 speed will be limited by the slowest processor core 102 in the SoC 100. However, the overall chip 104 leakage current will be dominated by the faster processor cores 102. Thus, if the speed performance of the faster processor cores 102 in the SoC 100 is increased beyond the speed performance of the slower processor core 102, the leakage of the SoC 100 increases without an overall speed performance benefit of the SoC 100.
In this regard. FIG. 2 is a maximum quiescent current (Iddq) pie chart 200 illustrating exemplary core-to-core Iddq variations 202(1)-202(4) of the processor cores 102(1)-102(4) in the SoC 100 in FIG. 1. Iddq testing is a known method to determine circuit process variations. Each processor core's 102(1)-102(4) Iddq variation 202(1)-202(4) in the pie chart 200 is defined as the result of the maximum Iddq minus the minimum Iddq, divided by the minimum Iddq. In this example, processor cores 102(1) and 102(3) contribute approximately 95% of the Iddq variation of the processor cores 102(1)-102(4) in the SoC 100.
Different speed performances in processor cores in a SoC may exist for several reasons. For example, the processor cores 102(1)-102(4) in the SoC 100 in FIG. 1 being located in different locations on the chip 104 can affect their relative performance speeds. As shown in FIG. 1, processor core 102(3) is located in a corner 106 of the chip 104. Processor cores 102(1), 102(4) are located near the corner 106 in the chip 104. Processor core 102(2) is located closer to a center 108 of the chip 104. Also, each processor core 102(1)-102(4) in the SoC 100 may be surrounded by different circuit blocks in the chip 104, which contribute differently to the thermal impact to each processor core 102(1)-102(4). Further, localized process variations during manufacturing of the SoC 100 could also vary threshold voltage levels (Vt) in the processor cores 102(1)-102(4) that cause variations in speed performance. Mechanical stress could also be different for each processor core 102(1)-102(4) due to location and device density.