As is well known, semiconductor devices can include an insulated gate field effect transistor (IGFET) type device. IGFET-type devices typically include a transistor gate separated from a channel region by a dielectric. A potential applied to a gate can then be varied to alter channel conductivity.
While many IGFET type devices are volatile (e.g., conventional metal-oxide-semiconductor FETs), nonvolatile devices may also include IGFET-like approaches. Nonvolatile IGFET-like devices typically retain electric charge through one or more methods (e.g., storing, trapping charge). One conventional nonvolatile device can be a floating gate electrically erasable programmable read only memory (EEPROM). A floating gate EEPROM can include a floating gate electrode situated between a control gate and a channel. Charge, including electrons and/or “holes”, may be stored in a floating gate electrode. Such a charge may alter a threshold voltage of a resulting nonvolatile IGFET-type device. As will be noted below, a drawback to any floating gate device can be higher programming and/or erase voltages with respect to other nonvolatile approaches.
Another nonvolatile IGFET type device can include a dielectric interface to trap charge. For example, devices have been proposed that include a metal gate formed over a dielectric of silicon nitride and silicon dioxide. Such devices have been referred to as metalnitride-oxide-semiconductor (MNOS) devices. A drawback to many MNOS devices has been lack of charge retention and/or uniformity of programming.
A third type of nonvolatile device may include one or more dielectric layers for storing charge. Such devices may be referred to generally as silicon-oxide-nitride-oxidesilicon (SONOS) type devices. One very basic type of SONOS device may include a polycrystalline silicon (“polysilicon”) gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon dioxide layers.
SONOS devices can have lower programming voltages than other conventional nonvolatile devices, such as some types of floating gate devices. In addition, the SONOS fabrication process can be compatible with standard complementary metal oxide semiconductor (CMOS) process technology. To maintain this compatibility, SONOS devices may be scaled along with other transistors used in the process. The ability of SONOS devices to maintain performance and reliability as they are scaled can be an important feature.
To better understand the formation of SONOS devices, a conventional way of forming a SONOS device is set forth in FIGS. 11 and 12A to 12F. FIG. 11 is a flowchart illustrating various process steps involved in creating an integrated circuit containing SONOS devices. FIGS. 12A-12F set forth a number of side cross-sectional views of a portion of an integrated circuit containing SONOS devices following the various conventional process steps described in FIG. 12.
The conventional process described in FIG. 11 is designated by the general reference character 1100. A conventional process 1100 may include the steps of growing a tunnel oxide (step 1102) in a furnace. Subsequently, wafers that now include the tunnel oxide can be transferred from a furnace to a different machine for growing other layers in an ONO dielectric for a SONOS-type device. In FIG. 11, such a step may include transferring wafers to a chemical vapor deposition (CVD) machine (step 1104).
A conventional method 1100 may further include depositing a silicon nitride layer over tunnel oxide in a CVD machine (step 1106), depositing a top oxide layer over a nitride layer in the same or a different CVD machine (step 1108), and depositing a polysilicon gate layer (step 1110).
The above steps may form various layers for a SONOS-type device. Such layers can then be patterned to form a SONOS-type transistor. Patterning steps may include forming a gate mask (step 1112), etching gate structures (step 1114), and depositing and etching a spacer layer (step 1116).
Referring to FIG. 12A, a side cross-sectional view of a portion of an integrated circuit prior to the beginning of a conventional process 1100 is shown. An integrated circuit portion includes a substrate 1200, and may include isolation regions 1202 formed by prior process steps. As an example, isolation regions 1202 may be formed by various conventional isolation processes including but not limited to shallow trench isolation (STI) or the local oxidation of silicon (LOCOS).
It is noted that a substrate 1200 may also include various impurity regions, formed by ion implantation and/or other diffusion methods. As but a few examples, n-type wells may be formed in a p-type substrate (or vice versa), or p-type wells may be formed within n-type wells (or vice versa).
Referring again to FIG. 11, a conventional process 1100 may begin by growing a tunnel oxide (step 1102) in a furnace. A portion of an integrated circuit following step 1102 is set forth in FIG. 12B. Referring to FIG. 12B, a portion of an integrated circuit includes a tunnel oxide 1204 on a substrate 1200.
A conventional process 1100 can continue by transferring a wafer from a furnace to a chemical vapor deposition (CVD) machine (step 1104). A conventional process 1100 can continue by depositing a silicon nitride layer in a CVD machine (step 1106). A portion of an integrated circuit following step 1104 is set forth in FIG. 12C. Referring to FIG. 12C, an integrated circuit may now be situated within a CVD machine. The integrated circuit portion can now include a nitride layer 1206 deposited over a tunnel oxide 1204. A nitride layer 1206 can conventionally include essentially only silicon nitride (Si3N4).
A conventional process 1100 can continue by depositing a top oxide layer (step 1108) in a chemical vapor deposition (CVD) machine. Referring to FIG. 12D, an example of a portion of an integrated circuit following step 1106 is set forth. A tunnel oxide 1204, a nitride layer 1206 and a top oxide layer 1208 may now be formed over a substrate 1200. A top oxide layer 1208 can be conventionally formed by chemical vapor deposition (CVD).
At this point, in a conventional process 1100, three layers of an ONO dielectric have been created in at least two different machines. More particularly, a tunnel oxide 1204 may be formed in one machine (a furnace particular adapted for growing an oxide), while a nitride layer 1206 and/or a top oxide layer 1208 may be formed in a different machine (a machine particularly adapted for depositing CVD films)
A conventional process 1100 can continue by depositing a polysilicon gate layer (step 1110). An example of a portion of an integrated circuit following a step 1108 is set forth in FIG. 12E. Referring to FIG. 12E, a polysilicon gate layer 1210 has been deposited on a top oxide layer 1208. As also shown in FIG. 12E, a gate protection insulator 1213 may also be formed over polysilicon gate layer 1210. It is noted that a polysilicon gate layer 1210 is conventionally formed in a different reaction chamber than the previous oxide-nitride-oxide layers. Further, a gate protection insulator 1213 may be formed in a different reaction chamber than a polysilicon gate layer 1210.
At this point, in a conventional process 1100, the silicon-oxide-nitride-oxide-silicon (SONOS) layers can correspond to a substrate 1200, tunnel oxide 1204, nitride layer 1206, top oxide layer 1208, and polysilicon gate layer 1210, respectively.
A conventional process 1100 may continue with lithography and etch steps to isolate and form SONOS devices. In conventional lithography, a gate mask may first be formed (step 1112). An example of a portion of an integrated circuit following step 1110 is set forth in FIG. 12E. A gate mask material 1212 can be deposited and patterned using any of various lithographic techniques. A gate mask material 1212 may generally consist of a photoresist material.
Following the formation of a gate mask (step 1112), gate structures can be etched (step 1114). Referring now to FIG. 12F, a portion of an integrated circuit following step 1112 is set forth. A suitable etching process can remove portions of the tunnel oxide 1204, nitride layer 1206, top oxide layer 1208, and polysilicon gate layer 1210 that are not covered by gate mask material 1212. In this manner, SONOS device gate structures 1216 can be formed on a substrate 1200.
A conventional process 1100 can continue by depositing and etching a spacer layer (step 1116). An example of a portion of an integrated circuit following step 1116 is set forth in FIG. 12F. Referring to FIG. 12F, a spacer layer 1214 can be formed that surrounds and electrically isolates SONOS gate structures 1216. A spacer layer 1214 may include silicon dioxide. Note that in FIG. 12F, a gate mask layer 1212 has been removed by suitable process means.
While the conventional process described may produce an integrated circuit containing SONOS devices of reasonable quality and performance, certain aspects of a process may be important in maintaining device performance and/or reliability. This can be particularly true as SONOS devices are scaled to realize lower programming voltages and/or in order to maintain compatibility with CMOS process technology.
ONO dielectric layers in SONOS-type devices may suffer from certain drawbacks as a SONOS-type device is scaled down, particularly as the thickness of the dielectric layers are scaled down to a point at which a tunnel oxide 1204 can be less than 25 Å thick, a nitride layer 1206 can be less than 100 Å thick and a top oxide layer 1208 can be less than 50 Å thick.
A tunnel oxide 1204 can provide an insulating layer between a silicon substrate and a nitride layer 1206. A nitride layer 1206 can be a dielectric layer between a tunnel oxide 1204 and a top oxide layer 1208 that can trap and/or store electric charge. A top oxide layer 1208 can function to electrically isolate a nitride storage layer 1206 and a polysilicon gate layer 1210.
For the reasons set above, the quality of a tunnel oxide 1204, a nitride layer 1206 and a top oxide layer 1208 can be important features in an ONO dielectric of a SONOS-type device.
The performance of an ONO dielectric of a SONOS-type device can be affected by various factors including thickness, uniformity of thickness, particle count, stress in the dielectric layers, and the quality of a interfaces present in an ONO dielectric.
Thickness can be an important character of an ONO dielectric in a SONOS-type device as a thin but robust dielectric can be important in maintaining device performance and reliability. This may be particularly important as SONOS devices are scaled to realize lower programming voltages and/or integrated to be compatible with decreasing geometry CMOS process technology.
Uniformity of the thickness of dielectric layers across a wafer can also be an important feature in a process. Uniformity in layer properties across a wafer can translate into uniformity in the performance of all devices formed on at the same wafer. This can increase yields and help ensure that device specifications are met.
Particle count can be another important character of ONO dielectric of SONOS-type devices. Increased particle account typically results in direct reductions in yields. Consequently, minimizing particle count is typically a continuing goal in semiconductor manufacturing processes.
Stress may also reduce the quality of ONO dielectric layers of SONOS-type devices.
In particular, stress may occur when different materials undergo thermal expansion at different rates. Temperature variation can be the main cause of the thermal expansion that can lead to stress in different dielectric layers. Stress can cause cracking in the dielectric layers, spiking in metal lines and/or void formation in conductive layers, thus reducing the quality of an ONO dielectric.
Interface quality may be affected by foreign elements, or the like. Such foreign elements may typically be introduced at an interface during a manufacturing process. As but a few of the many possible examples, foreign elements may include organic films, undesirable elements like boron, and/or particles.
A conventional manufacturing process for a SONOS-type device, such as that described above, can have various drawbacks. In a conventional process, wafers can be transferred to different machines for manufacturing different layers. For example, a tunnel oxide 1204 can be grown in one machine, while the remaining layers including a nitride layer 1206 and a top oxide layer 1208 can be deposited in another machine. A transfer of wafers among different machines can facilitate the introduction of foreign particles or elements onto a wafer, and thus increase a particle count for a wafer. Further, such particles or elements may settle at an interface between dielectric layers. This may adversely affect the performance of an ONO dielectric.
A conventional process can also subject wafers to broad temperature changes in forming different dielectric layers. This may also increase the particle count and increase the stress in dielectric layers. In particular, different layers of a SONOS-type dielectric can be formed under different temperature ranges. In addition to increasing stress, resulting temperature cycles can also cause variations of thickness in different parts of dielectrics.
In light of the limitations of the conventional process set forth above, it would be desirable to provide a method of forming ONO dielectric layers for a SONOS-type device that may have a higher quality than conventional approaches.