1. Field of the Invention
The present invention relates to a circuit arrangement for the detection of errors associated with the implementation of a processor instruction, and more particularly, to a small programmable array for the detection and correction of errors associated with instructions having an invalid microcode sequence.
2. Description of the Prior Art
The programming language utilized to program microprocessors or processors in general is commonly referred to as assembler language or assembly language. Each individual assembler instruction is referred to as a macroinstruction, and each macroinstruction usually consists of a plurality of microinstructions. Microinstructions are the basic or primitive instructions that the microprocessor or processor can perform. The macroinstructions are a higher level language then the microinstructions and typically require several states to complete execution. Depending on the particular microprocessor or processor, the microinstructions required to implement a specific macroinstruction will vary.
A microprocessor or processor system consists basically of three main modules; namely, the microcontrol logic module, the control memory logic module, and the data path module. The two major functional areas of concern are the microcontrol logic module and the control memory logic module. The data path module is responsible for the manipulation of data through the system. The microinstructions are stored in the control memory and are collectively referred to as the system or processor firmware. Each microinstruction consists of a plurality of fields including one field which is used in conjunction with the processor control flags and the operation code of the macroinstruction to determine the next sequential microinstruction to be executed. The other primary field is used to control the data path. The macroinstruction operation code is read by the microcontrol logic and determines which microroutine to execute next.
In high speed processors, the control memory is usually constructed of bipolar ROMS and PROMS and by replacing the particular ROM, the entire macroinstruction set can be changed. In conventional processors, ROM is widely used for implementing an on-chip control store (control memory). As compared with an off-chip control store, this approach eliminates chip-crossing in the critical path and offers a very large data width, both of which are crucial for the high speed performance of the system. ROM is chosen because it has a density which is approximately 10 times better than that of static RAM. However, ROM can only be programmed with mask levels during fabrication which becomes a major disadvantage during the system development stage. A simple microcode error can block the whole system development effort for a significant amount of time. It is therefore desirable to detect and correct instructions without having to reprogram to ROM.
U.S. Pat. No. 4,644,539 to Sato discusses a variety of earlier conventional circuit arrangements for processing a fault or an error occurring in a control memory. One such circuit arrangement for the detection and correction of errors associated with incorrect instructions comprises an error detecting circuit and an error correcting circuit together with a control memory loaded with a plurality of microinstructions. The error detecting circuit is for detecting an error of each microinstruction read out of the control memory while the error correcting circuit is for correcting the error to obtain a correct microinstruction. With this structure, each microinstruction is always sent from the control memory through both the error detecting circuit and the error correcting circuit even when an error is not detected by the error detecting circuit. Therefore, an increase of a machine cycle is inevitable.
In another conventional circuit arrangement, the error detection alone is normally carried out for each microinstruction read out of a control memory by the use of an error detection circuit. An error correction circuit is operated only when an error is detected by the error detection circuit. With this structure, it is possible to shorten the machine cycle as compared with the above-mentioned circuit arrangement. However, the error correction circuit corrects an error of each microinstruction each time an erroneous portion of control memory is accessed. Therefore, it takes a long time to process each microinstruction read out of the erroneous portion. This lengthens the average time of executing the microinstructions when the hardware error occurs in the control memory.
Both of the above described prior art circuit arrangements carry out not only error detection but also error correction on occurrence of an error. In order to enable the error correction, each microinstruction should be formed by an error correcting code. Although the error detection alone is simply possible by addition of one or more parity bits, such as error correcting code requires extra redundant bits greater in number than the parity bit or bits, as is well known in the art. Thus, use of the error correcting code results in the control memory of an increased bit capacity. In addition, neither of the above described prior art circuit arrangements can correct microcode errors resulting from programming mistakes.
One embodiment for correcting errors in microcode is disclosed by Chang et al. in IBM Tech. Dis. Bal. 31,11 (April 1989), which uses a programmable instruction detection circuit. When there is an error associated with the implementation of an instruction, the detection circuit can be programmed to recognize the op code, and the instruction can be treated as an un-implemented instruction. Software emulation can be written to execute the instruction and bypass the problem. However, this system cannot verify the correctness of the revised microcode.
Japanese Patent No. 58-16349 discloses a memory extension substituting system to facilitate the substitution of faulty instructions with error free instructions. In this patent, the implementation of the system is based on the detection of a particular address of the microinstruction rather than on the detection of a particular operational code of the instruction. When a particular address is detected, a substitute address pointing to an area of memory which has error free microinstructions is provided. A no-op cycle for timing purposes has to be inserted when the microinstruction is invalidated by the system. This no-op state can happen in the middle of the execution of an instruction, which can make the design and debugging of the system more difficult.
Japanese Patent No. 58-16350 also discloses a memory extension substituting system. In this patent, when the specific address of a microinstruction with a fault is detected by a coincidence means, a substitute instruction is provided. Basically, to correct n microinstructions, the detection circuit detects and generates replacement addresses for n microaddresses. However, it is only feasible to implement a system capable of handling n microinstructions, where n is limited to small numbers due to the limitation on the size and performance of the detection circuits.
Japanese Patent No. 59-85545 discloses a correcting and processing system for the contents of a system ROM. In this patent, the system disclosed provides for a technique which involves the bypassing of errors in the system ROM containing the system program, and not errors in the control store ROM which contains the microcode.