1. Technical Field
The present invention generally relates to a semiconductor device, and to a semiconductor memory device capable of supplying and measuring an electric current through a pad.
2. Related Art
In general, a semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device. The volatile memory device loses data stored therein when power is cut off, whereas the nonvolatile memory device retains data stored therein even though power is cut off.
The nonvolatile memory device includes various types of memory cells. Depending on the structures of the memory cells, the nonvolatile memory device may be classified into a flash memory device, ferroelectric RAM (FRAM) using a ferroelectric capacitor, magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, and a semiconductor memory device using chalcogenide alloys. Particularly, the semiconductor memory device is a nonvolatile memory device using a phase change, that is, a resistance change, according to a temperature change. For this reason, the semiconductor memory device is also called a variable resistance memory device.
The memory cell of the semiconductor memory device is made of a calcogen compound, that is, phase change materials, for example, a germanium (Ge)-antimony (Sb)-tellurium (Te) mixture (GST) (hereinafter referred to as “GST materials”). The GST materials have an amorphous state indicative of relatively high resistivity and a crystalline state having relatively low resistivity. The memory cell of the semiconductor memory device may store data “1” corresponding to the amorphous state and data “0” corresponding to the crystalline state. When the GST materials are heated, data corresponding to the amorphous state or the crystalline state is programmed into the memory cell of the semiconductor memory device. For example, the amorphous state or crystalline state of the GST materials may be controlled by controlling the amount of current for heating the GST materials and the time that it takes to supply the current.
As described above, the state of a memory cell of the phase change memory device is changed depending on a write current supplied to the memory cell. Furthermore, the state of a memory cell of the phase change memory device is determined depending on how much the memory cell can conduct current supplied thereto. In the write operation of the phase change memory device, if a write current is shifted by the influence of a write driver and peripheral circuits, memory cells may have an unexpected resistance distribution. In the read operation of the phase change memory device, if a sensing current is shifted by the influence of a sense amplifier and peripheral circuits, a resistance distribution of memory cells may not be precisely detected. For the reasons, a problem arises because a test in the memory cells may not be precisely performed.
Accordingly, there is a need for a scheme capable of supplying a write current to a memory cell or detecting the sensing current of a memory cell without the influence of relevant circuits in the test operation of a phase change memory device.