1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a transistor using an SOI (Semiconductor On Insulator) substrate.
2. Description of the Background Art
An ASIC (Application Specific Integrated Circuit) is desired to operate at high speed with low power consumption, like a logic LSI such as a microprocessor, and so is a gate array which is a form of the ASIC.
FIG. 36 is a cross section showing a structure of a bulk NMOS transistor. A junction capacitance C1 caused by a depletion layer 104 existing between an Si substrate 101 and a source region 102 (or a drain region 103) is large and a wiring capacitance C2 between a metal wire 105 disposed on an NMOS transistor and the Si substrate 101 through a LOCOS oxide film 108 is also large.
In this situation, proposed is a use of an SOI layer in a gate array. FIG. 37 is a cross section showing a structure of an SOI NMOS transistor. Since a transistor on an SOI layer 106 has a thick buried oxide film 107 thereunder, both the junction capacitance C1 and the wiring capacitance C2 thereof are smaller than those of the bulk NMOS transistor. That allows higher-speed operation and lower power consumption.
Moreover, a transistor of which the source and drain are formed in the SOI layer 106 (referred to as "SOI transistor" hereinafter) has a semiconductor (body) 110 which is in an electrically-floating state between a source region 102 and a drain region 103. A "body effect", which refers to an action that a threshold value Vth of the transistor rises due to a potential difference between the Si substrate 101 and the source region 102 when a source potential rises (in case of an NMOS transistor), is not caused in the SOI transistor unlike the bulk transistor. Therefore, the SOI transistor may be always used with a small threshold value and operate with low voltage. Thus, the SOI transistor needs only low power consumption.
In the SOI transistor, however, when the source-to-drain voltage reaches a certain level or more, impact-ionized charges near the drain region 103, e.g., positive holes in the NMOS transistor, do not escape into the Si substrate 101 to raise a potential at the body 110 which acts as a base of an NPN type parasitic bipolar transistor consisting of the body 101, the source region 102 and the drain region 103 since the body 101 where a channel is formed is in the floating state. Then, a current driven by the bipolar transistor is superposed on an original current of the SOI transistor. FIG. 38 is a graph showing a rise in current due to a parasitic bipolar effect. To avoid the parasitic bipolar effect, it is needed to fix the potential at the body 110 of the SOI transistor.
FIG. 39 is a plan view of a structure of field-shield isolation (referred to as "FS isolation" or "FS-isolated structure" hereinafter). FIGS. 40 and 41 are cross sections of FIG. 39 taken along the lines XXXX--XXXX, and XXXXI--XXXXI, respectively. An active region 111 having a width Lf is formed to become the source region 102 or the drain region 103. The active region 111 is provided with a source-drain contact 96 to establish an electrical connection with a wire (not shown). For simple illustration, a gate contact 97 of a gate electrode 109 is not shown in FIG. 39.
Similarly to a gate isolation by fixing a potential of the gate electrode 109 (e.g., by connecting the gate electrode 109 to the around GND through the gate contact 97 in a case of NMOS transistor) made in a direction of arrangement of the active region 111 (in vertical direction of FIG. 39), the FS isolation is a device isolation with an FS gate 91 achieved in a direction perpendicular to the vertical direction (in a horizontal direction of FIG. 39).
Specifically, the FS gate 91, like the gate electrode 109, is opposed to the SOI layer 106 with an insulative interlayer film interposed therebetween on both sides of the NMOS transistor, and when it is connected to the around GND, the NMOS transistor is isolated in the horizontal direction.
FIG. 42 is a cross section showing an isolation using a LOCOS oxide film (referred to as "LOCOS isolation" hereinafter) in the horizontal direction. When the LOCOS isolation is used, the SOI layer 106 is separated in the horizontal direction by the LOCOS oxide film 108 and hence it is impossible to provide a contact for supplying the SOI layer 106 with a predetermined potential. In contrast, when the FS isolation is used, the SOI layer 106 can extend also in the horizontal direction and hence it is possible to supply the SOI layer 106 with the predetermined fixed potential in the extension of the SOI layer 106. In this case, it is necessary to provide an FS gate contact 92 for supplying the FS gate 91 with the predetermined potential and a contact plug 93 for FS isolation as shown in FIG. 41, and on the other hand, it is necessary to provide a body contact 94 for supplying the body with the predetermined potential and the contact plug 93 (a region indicated by hatching can have higher impurity concentration in the SOI layer 106 with which the contact plug 93 comes into contact). Therefore, there is a need for a chipped portion 95 at a position to provide the body contact 94 in the FS gate 91, as shown in FIGS. 39 and 40.
This gate array, which supplies the body 110 with the predetermined potential, allows reduction in wiring capacitance, ensures high-speed operation and low power consumption and further prevents the parasitic bipolar effect. For example, the SOI transistor with FS-isolated structure may be used in an inverter.
FIG. 43A shows a symbol of an inverter and FIG. 43B shows a specific configuration thereof. The inverter consists of a PMOS transistor P1 and an NMOS transistor N1 connected in series between a potential point supplying a potential Vcc and the ground GND. Specifically, the source of PMOS transistor P1 is fixed to the potential Vcc and the source of NMOS transistor N1 is fixed to the ground potential GND. In this configuration, even if the SOI transistors with FS-isolated structure are used as the transistors P1 and N1 and the bodies of the transistors P1 and N1 are fixed to the potential Vcc and the ground potential GND, respectively, no potential difference exists between the respective bodies and sources and hence no body effect works ill on the inverter.
However, there may be a case where it is preferable not to fix the potential at the body 110 so as not to lose the advantage of no body effect.
FIG. 44A shows a symbol of an NAND circuit and FIG. 44B shows a specific configuration thereof. The NAND circuit consists of PMOS transistors P1 and P2 connected in parallel and NMOS transistors N1 and N2 connected in series between the potential point supplying the potential Vcc and the ground GND.
Since the sources of transistors P1, P2 and N2 are supplied with the potential Vcc, Vcc and the ground potential GND respectively, if the bodies of the transistors P1, P2 and N2 are supplied with the potential Vcc. Vcc and the ground potential GND respectively, no body effect is produced on the transistors. However, there may be a case where a potential higher than the ground potential GND is applied to the source of the transistor N1 which is not supplied with a fixed potential, and when the ground potential GND is applied to the body of the transistor N1, a threshold voltage rises due to the body effect. In this situation, the NAND circuit can not operate with low voltage and hardly avoids slow operation.
FIG. 45 shows a layout where vertical alignments of the active regions (referred to as "fields" hereinafter) are arranged in the horizontal direction (this layout is referred to as "master layout" hereinafter). As illustrated in disregard of the gate electrodes, the fields 10a to 10i are seen rectangular. The characters "P" and "N" in rectangles indicate fields to be provided with the PMOS transistor and the NMOS transistor, respectively. The fields provided with the PMOS transistor and the NMOS transistor are herein termed "p-type field" and "n-type field", respectively.
In the background art, when the FS isolation is used to supply the body 110 with the predetermined potential, all of the fields are FS-isolated (the fields 10a to 10i of FIG. 45 are each FS-isolated, and the field with FS-isolated structure is referred to as "FS-isolated field" hereinafter). Since the SOI layers 106 in a field are supplied with the predetermined potential in common (e.g., the ground potential GND in the NMOS transistor), the potentials at the bodies 110 of the transistors in the same field are all fixed. Then, there arises a problem of degradation in high-speed operation of the SOI transistor in a circuit including a transistor having the source which is not supplied with the fixed potential, such as an NAND circuit.
Furthermore, by supplying the gate electrode and the body with the same potential, it may become possible to positively utilize the parasitic bipolar effect to earn a driving current of the SOI transistor.