1. Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for using a suggested solution to speed up an iterative process, such as optical proximity correction, for simulating and correcting a layout on a semiconductor chip.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is xe2x80x9cline end shorteningxe2x80x9d and xe2x80x9cpullbackxe2x80x9d. For example, the upper portion of FIG. 1 illustrates a design of a transistor with a polysilicon line 102, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of FIG. 1 illustrates a printed image that results from the design. Note that polysilicon line 102 has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region.
Also note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
In order to compensate for line end shortening, designers often add additional features, such as xe2x80x9chammer heads,xe2x80x9d onto line ends (see top portion of FIG. 2). The upper portion of FIG. 2 illustrates a transistor with a polysilicon line 202, running from left to right, which forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. A hammer head 204 is included on the end of polysilicon line 202 to compensate for the line end shortening. As is illustrated in the bottom portion of FIG. 2, these additional features can effectively compensate for line end shortening in some situations.
These additional features are typically added to a layout automatically during a process known as optical proximity correction (OPC). For example, FIG. 3 illustrates line end geometry 302 (solid line) prior to OPC and the resulting corrected line end geometry 304 after OPC (dashed line). Note that the corrected line end geometry 304 includes regions with a positive edge bias in which the size of the original geometry 302 is increased, as well as regions of negative edge bias in which the size of the original geometry 302 is decreased.
Performing an operation, such as OPC, can be extremely time-consuming, because the operation typically involves numerous iterations of a time-consuming modeling and correction process. Furthermore, the operation must be applied to all of the cells that comprise a layout of an integrated circuit.
In order to speed up operations such as OPC, existing systems often perform hierarchical processing on a layout to identify identical cells that have the same surrounding environment. (Within this specification and the associated claims, the term xe2x80x9ccellxe2x80x9d refers to a unit of design, such as an arbitrary geometric region or potion of the layout.) If such identical instances of cells are identified, the existing systems can use a solution computed for one cell as a solution for all other identical instances of the cell. This saves a great deal of time for layouts that contain many instances of the same cell.
Unfortunately, existing systems cannot reuse solutions in cases where identical cells have different surrounding environments, or when a layout of a given cell differs only slightly from the layout of another cell.
Moreover, existing systems do a poor job of distributing the workload involved in computing solutions for cells across multiple processing nodes that are typically available in high-performance computing systems.
What is needed is a method and an apparatus that reuses a solution for a given cell in computing a solution for a cell with a different environment and/or a slightly different layout.
One embodiment of the invention provides a system for speeding up an iterative process that simulates and corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.
In a variation on this embodiment, the target cell is similar to the preceding cell if the layout of the target cell matches the layout of the preceding cell but the environment surrounding the target cell differs from the environment surrounding the preceding cell.
In a variation on this embodiment, if the previously calculated solution for the preceding cell is used as the initial input to the iterative process, the iterative process only operates on features within a border region located just inside the outside edge of the target cell that can be affected by the environment surrounding the target cell, and ignores features within the target cell that are not located within the border region.
In a variation on this embodiment, the target cell is similar to the preceding cell if the layout of the target cell differs from the layout of the preceding cell by less than a pre-specified amount. For example, in one embodiment of the present invention, the target cell is similar to the preceding cell if a specific percentage (say 95%) of the layout of the target cell is identical to the layout of the preceding cell.
In a variation on this embodiment, if the previously calculated solution for the preceding cell is used as the initial input for the iterative process, and if the iterative process produces a simulation result that differs significantly from the desired layout, the system restarts the iterative process using the desired layout instead of the previously calculated solution as the initial input to the iterative process.
In a variation on this embodiment, while performing the iterative process the system repeatedly simulates a current solution for the target cell to produce a current simulated layout. If the current manufactured result as determined by simulation (or xe2x80x9csimulated layoutxe2x80x9d) differs from the desired layout by less than a pre-specified amount, the system accepts the current solution as a final solution for the target cell. Otherwise, the system corrects the current solution to compensate for differences between the current simulated layout and the desired layout.
Note that the term xe2x80x9csimulatesxe2x80x9d as used in this specification and the associated claims refers to both simulation of optical effects as well as modeling of mask writing (e.g. E-Beam), resist and/or etch effects.
Thus, in one embodiment of the present invention, there are three primary outcomes from using the suggested solution approach: (1) further simulation and correction time are saved because the previous solution is accepted, additionally data volume can be significantly reduced; (2) the previous solution is further modified, but simulation and correction times are still significantly reduced since generally fewer edges are simulated and corrected; or (3) the previous simulation results are discarded and there is only a minor overall time penalty relative to the vast savings. Moreover, there are often significant data volume reductions.
In a variation on this embodiment, prior to considering the target cell, the system receives a specification for the layout of the integrated circuit, and divides the layout into a plurality of cells, whereby each cell can be independently subjected to the iterative process.
In a variation on this embodiment, the iterative process performs model-based optical proximity correction (OPC).
One embodiment of the invention provides a system for speeding up processing of a layout of an integrated circuit that has been divided into cells. The system operates by determining if a target cell in the layout is identical to a preceding cell for which there exists a previously calculated solution by comparing an identifier created from the target cell with an identifier created from the preceding cell. Note that the identifiers, which are also referred to as hash codes, hash keys or message digests, are computed from properties and/or descriptions of the respective cells. Hence, the terms xe2x80x9chash codexe2x80x9d and xe2x80x9cidentifierxe2x80x9d are used interchangeably throughout this specification and associated claims, and are meant to refer to values computed from properties and/or descriptions of cells.
If the target cell is identical to a preceding cell, the system uses the previously calculated solution as a solution for the target cell. Otherwise, if the target cell is not identical to the preceding cell, the system processes the target cell to produce the solution for the target cell. Note that this approach can also be used for a number of different processes, such as distributed fracturing or optical proximity correction.
In a variation on this embodiment, if the hash code created from the target cell matches the hash code created from the preceding cell, the system compares the complete layout of the target cell with the complete layout of the preceding cell to ensure that the target cell is identical to the preceding cell. This is useful because it may be possible for two different cells to have identical identifiers even though the cells are not the same. If the relative cost of comparing the layouts (geometrical boolean operations) is less than the cost of detecting the error after doing the other processing, this is usually a desirable option.
In a variation on this embodiment, determining if the target cell is identical to a preceding cell involves determining whether an area surrounding the target cell is identical to an area surrounding the preceding cell.
In a variation on this embodiment, prior to determining if the target cell is identical to the preceding cell, the system performs an overlap removal operation on the target cell and the preceding cell.
In a variation on this embodiment, the system distributes the plurality of cells to a set of parallel processors so that plurality of cells can be processed in parallel.
In a variation on this embodiment, processing the target cell involves performing, data fracturing, model-based optical proximity correction (OPC), rule-based optical proximity correction, or phase shifter assignment for the target cell.