1. Field of the Invention
This invention generally relates to methods and systems for determining if a defect detected on a specimen is a defect of interest or a nuisance. Some embodiments include determining a sub-pixel location of a defect detected on a specimen and determining if the defect is a defect of interest or a nuisance based on that location.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
An integrated circuit (IC) design may be developed using a method or system such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate the circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
The term “design data” as used herein generally refers to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive.
There are several currently used methods designed to decrease nuisance detection by either limiting the area scanned or by using only image data from selected areas. Examples of such methods include design-based care areas (CAs), methods that perform pixel to design alignment (PDA), and patch-based detection. Design-based CAs can be used to limit the area of inspection by either using design files to generate relatively small (but still multi-pixel) CAs or by looking for locations whose optical images look similar to optical images acquired at known hot spots and inspecting only those areas. Methods that perform PDA use design information to determine registration sites on the wafer. These locations can then be found in the optical image and used to determine the relative location of DOI in the optical images and thus the location of the DOI within the design. In patch-based detection, a projection of the optical image may be made. The projection allows the image to be segmented in one dimension into regions in which the DOI is expected and where it does not occur. The primary application of patch-based detection is to separate signals originating from N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) regions in static random access memory (SRAM).
While the currently used methods have been proven effective for a number of uses, these methods do have some limitations. For example, the above-described methods are limited by the size and uncertainty in location of the region they can define. In one such example, even methods that perform PDA and patch-based detection, which define relatively small regions, still define multi-pixel regions. The smallest regions being attempted by methods that perform PDA are 3×3 pixels, and the uncertainty in the positioning of the regions is believed to be at least +/−1 pixel if not more. Patch-based detection only segments the image along one dimension. In addition, one cannot control how the pixels align with the wafer structure during a scan requiring regions at least 2 pixels wide for a total area of at least 64 pixels for a 32×32 pixel optical patch image. In another example, methods that define care areas for inspection can typically only define a limited number of areas. Furthermore, patch-based detection is vulnerable to changes in the appearance of reference images that can occur due to sources such as wafer process variation and changes in focus offset. Information is lost when the projection of the patch image is made, and it is difficult to deal with multiple types of images, since their projections may be very similar but translated in space. Methods that perform PDA can also be sensitive to differences between the design file and the actual wafer. These differences can be magnified when the DOI locations are relatively far from the registration sites. Moreover, patch-based detection is (to date) only one dimensional. In addition, patch-based detection only works in memory areas.
Accordingly, it would be advantageous to develop systems and/or methods for determining if a defect detected on a specimen is a DOI or a nuisance that do not have one or more of the disadvantages described above.