The use of photolithographic and etching steps to produce via-holes in insulating layers formed during the semiconductor wafer processing are important and critical steps in the course of the manufacturing of Very Large Scale Integration (VLSI) silicon chips. For example, via-holes may be etched through an insulating layer, and a metal layer subsequently deposited thereon, filling the via-holes and providing an elecrrical contact with the underlying conductive layer, i.e., a polysilicon land or a monocrystalline silicon substrate.
With a continuous trend towards still further integration and microminiaturization of active/passive devices, the need for methods of producing extremely small via-holes becomes more acute. Known wet etching processes fail in that respect because of capillary problems, so that the liquid etchant cannot reach the bottom of the via-holes. Therefore, it clearly appears today that dry etching processes such as Plasma Etching and Reactive Ion Etching have a greater potential to produce extremely small via-holes of a diameter equal to or less than 1 micron.
Unfortunately, when dry etching processes are used, the etching direction is substantially anisotropic, i.e. in a vertical direction only, thereby producing via-holes with substantially vertical sidewalls. As a result, step coverage problems are encountered during metallization, with the metal layer being substantially thinner on the sidewalls and the step of the via-hole than elsewhere. These metal thickness irregularities can give rise to a risk of potential cracks and cause variations in the land resistances. As a result, they may cause subsequent metal land opens which in turn, sometimes result in a total failure of the functional circuit integrated in the chip.
Accordingly, in order to prevent such cracks from occurring, the slopes of these contact openings have to be tapered, i.e. as smooth as possible (about 60 deg.) to allow a good metal coverage.
In order to minimize or preferably to eliminate these step coverage problems, efforts have been made to develop dry etching methods for producing via-holes with sloped profiles through an insulating layer formed by a single dielectric material. One method of doing this has been to suggest the use of a conventional photoresist mask which has a sloped profile.
A technique to produce tapered via-holes in a patterned photoresist mask formed on an insulating layer consists of heating the structure so that the resist softens, and because of the surface tension, develops tapered walls.
Since the mask is anisotropically eroded to some degree by the plasma gas as the underlying insulating layer is etched, the result is replication of the mask profile, more or less, in the insulating layer.
This technique suffers from the difficulty of ensuring that the etch rate ratio equals the ratio of thicknesses and also limits the profile conformal to the shape assumed by the photoresist mask during the bake step (after the development of the resist).
Another method has been to use the sensitivity of certain photoresist compositions to erosion. It has been discovered that said erosion is substantially isotropic, making it possible to produce anisotropic etching results by the use of controlled isotropic photoresist erosion during the etching process.
This process suffers from the use of non-standard photoresist compositions.
In addition, various variables such as lithographic conditions, exposure parameters, surface topography and hole size seriously affect hole profiles and dimensions to such an extent that precision control by this method and reproducible results are very difficult to obtain.
Moreover, it is frequent in the silicon chip processing, and in particular in the manufacturing of MOSFET's, to etch extremely small contact via holes over either a silicon substrate or a polysilicon land through a thick composite insulating layer comprised of at least two dielectric materials having different etching rates, e.g., a layer of Phospho Silicate Glass (PSG) overlying a layer of silicon dioxide (SiO.sub.2). The problem of precision control mentioned above becomes even more acute when such a composite layer is used, because of the different etching rates of the two materials. If wet etchant is used to etch the via-hole, the openings become too large for high density circuits, because PSG etches much faster than thermally grown SiO.sub.2.
A first attempt to produce via-holes with sloped profiles in a composite insulating layer, while still fully complying with dry etching techniques, has been developed by the applicant and consisted of a succession of etch (using CHF.sub.3) and ash (using O.sub.2) steps.
The basic principle of this technique has been published in the IBM Technical Disclosure Bulletin: "Multi-step contour etching process", Vol. 27, No. 6, November 1984, pp. 3259-3260 and "Multi-step etching of dissimilar materials achieving selectivity and slope control", Vol. 28, No. 7, December 1985, pp. 3136-3137.
For example, real experiments were conducted in the manufacturing line of a typical CFET product, in the etching of conaact via-holes through a photoresist masked PSG/SiO.sub.2 composite insulating layer, to expose a portion of an underlying polysilicon layer. This process consisted of the following steps:
______________________________________ No. 1 Etching 3.6 min Ashing .4 min No. 2 Etching 3.1 min Ashing .6 min No. 3 Etching 2.2 min Ashing 1.1 min No. 4 Etching .5 min Ashing 2.2 min No. 5 Etching .6 min Ashing 3.3 min No. 6 Etching .7 min Ashing 1.0 min No. 7 Cleaning 1.0 min ______________________________________
This "multi-step" process has a long down time, because it implies 6 etching steps, each followed by an ashing step. Between two successive steps, long pumping sequences are necessary, to exhaust the previous gas system (e.g. CHF.sub.3) before filling with the following gas system (e.g. O.sub.2).
The total etch + ash time is 20.3 min. while the overall time including the pumping time is about 42.0 min. Such an overall time is a serious problem in a manufacturing line where high throughputs are desirable.
The "multistep" process is also characterized by its full anistropy. CHF.sub.3 etches vertically the composite oxide layer, but the photoresist mask is not attacked, while O.sub.2 does not attack the composite oxide layer but attacks the photoresist mask. The photoresist mask is attacked by O.sub.2 only if its openings are tapered. This implies a requirement to cure the photoresist mask in order to reflow the resist material. As a result of the reflow, vertical sidewalls are modified in tapered sidewalls. Unfortunately the use of a cured photoresist mask is a non-desired limitation. The ashing is only used for mask erosion. The anisotropic etching of oxide has a selective etch rate ratio between resist and oxide. The above process is characterized by its vertical etching component.
So there still exists a need for a dry etching method for producing a tapered via-hole with sloped profile in a photoresist masked composite insulating layer such as a PSG/SiO.sub.2 layer.