In important aspect of semiconductor structures, such as integrated circuits, is the ability to interconnect various components both on the same layer and in different layers of the integrated circuit. As integrated circuits and other semiconductor structures get smaller, the size of the relevant interconnects also decreases. Conventional interconnect deposition techniques include damascene processes of patterning the interconnect within another structure, such as a dielectric. The damascene process has been used for hundreds of years to produce jewelry and various other ornamental objects. However, with the continued reduction of integrated circuit size it becomes more difficult to utilize conventional techniques for forming interconnects and vertical interconnect accesses (“vias”), especially when high-aspect ratio structures are involved. This significantly limits the ability to continue using conventional interconnect deposition techniques.