In the present day as electronic devices and other devices are increasingly scaled to smaller dimensions, techniques for patterning substrates becomes increasingly challenging. For both planar devices such as planar transistor devices, as well as three dimensional devices, such a three dimensional memory devices, deep trenches or other deep structures may be used in the fabrication process. In order to from a deep trench or deep via or similar structure in a substrate, a patterned mask material may be used in portions of the substrate to be protected while etching of the substrate takes place where mask material is absent. The mask material may subsequently be removed once the substrate is etched to a target depth.
Devices such as vertical NAND (VNAND) memory devices (“NAND” refers to a negative- and logic gate) and dynamic random access memory (DRAM) devices may employ trenches or vias having etch depths of more than one micrometer, for example. Because etching of the substrate may also entail etching of the mask material, in order to preserve at least a portion of the mask for the complete etch process, the mask thickness may be similar to the etch depth in some cases. This situation is especially the case for common mask materials based at least in part on carbon. For example, so called hard mask materials having a similar etch rate to the substrate may be employed for etching a trench having a depth on the order of one micrometer. Additionally, the hard mask pattern features may have a high aspect ratio, meaning the height of the mask feature may be greater than the width of the mask feature, at least along one width direction. In some cases, an aspect ratio (height/width) of the mask feature may approach 10:1 or may be greater. A consequence of etch processing using such relatively thick masks may include faceting and clogging of the mask features during etching, bowing of an underlying etch feature in the substrate, or tapering of the etch feature in the substrate. The final patterned trench, via or other structure in the substrate may deviate from a target shape, such as a vertical trench.
Forming a patterned hard mask using a material having a relatively lower etch rate may in principle reduce the total thickness of the hard mask used in an etch process. A drawback is that patterning techniques to form a hard mask are impractical using effective hard mask materials such as Al2O3, having a very low etch rate for etches used to etch silicon for example.
With respect to these and other considerations the present embodiments are provided.