Electrical circuits requiring high power handling capability (>20 watts) while operating at high frequencies such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz) have in recent years become more prevalent. Because of the increase in high power, high frequency circuits there has been a corresponding increase in demand for transistors which are capable of reliably operating at radio frequencies and above while still being capable of handling higher power loads.
To provide increased power handling capabilities, transistors with a larger effective area have been developed. However, as the area of a transistor increases, the transistor, typically, becomes less suitable for high frequency operations. One technique for increasing the area of a transistor while still providing for high frequency operations is to use a plurality of transistor cells that are connected in parallel. Such may be provided using a plurality of gate fingers, thus, the source to drain distance may be kept relatively small while still providing for increased power handling capability. Conventionally, when a plurality of parallel transistor cells are connected in parallel on a single chip, the cells are evenly spaced such that the gate-to-gate distance between adjacent cells (referred to herein as “pitch” or “gate pitch”) is uniform.
When such multi-cell transistors are used in high frequency operations, they may generate a large amount of heat. As a device heats up, performance of the device typically degrades. Such degradation may be seen in gain, linearity and/or reliability. Thus, efforts have been made to keep junction temperatures of the transistors below a peak operating temperature. Typically, heatsinks and/or fans have been used to keep the devices cool so as to ensure proper function and reliability. However, cooling systems may be increase size, electrical consumption, costs and/or operating costs of systems employing such transistors.
With uniform pitch multi-cell transistors, the temperature of cells near the center of the array are typically greater than those of the cells at the periphery. This is generally the case because the cells at the periphery have a larger area and/or a greater thermal gradient to areas surrounding the cells. Thus, for example, adjacent cells near the center of the multi-cell array will each generate heat and thus, each side of the cells will be at an elevated temperature with respect to cells farther from the center. This results in a thermal profile that is roughly a bell curve with center junction temperatures being the hottest and with the outer most junctions having a substantially reduced operating temperature compared to the center junctions.
An uneven temperature distribution among the junctions of a device may reduce device linearity. For example, for a device with a plurality of evenly spaced gate fingers connected by a manifold, RF phasing errors may occur along both the gate manifold and the individual gate fingers as a result of differing gate resistance as a function of temperature. Conventionally, to address these issues the spacing between the gate fingers is widened and/or the length of the fingers are shortened and additional fingers added to achieve the same net active area. Both of these solutions may result in spreading the heat load generated in the center of the device over a wider area. These solutions also may result in a larger area for the multi-cell transistor that may reduce the number of die per wafer.