Q:

Using a Makefile with C

So I have three files:
jarvismarch.c (includes "jarvismarchtools.h")
jarvismarchtools.c
jarvismarchtools.h

I would like to use a makefile to compile the aforementioned files. How would I go about this?

A:

The typical minimal makefile looks like this:
OBJ = jarvismarch.o jarvismarchtools.o

all: $(OBJ)
        $(CC) -o jarvismarch $(OBJ)

Taking the comment of asveikau into account and adding a clean target it becomes:
OBJ = jarvismarch.o jarvismarchtools.o
BIN = jarvismarch

CFLAGS = -Wall -pedantic -ansi

all: $(BIN)

$(BIN): $(OBJ)
    $(CC) -o @ $(OBJ)

clean:
    rm -f $(OBJ) $(BIN)

(Windows users need to use .obj instead of .o)
I strongly recommend against using make. It might be simple at first, but once your project grows I highly recommend a more complete build tool like SCons, CMake or Boost.Build.

