In general, capacitors are components that are commonly used in chip fabrication and packaging designs for various purposes. For instance, on-chip capacitors are fundamental components for constructing semiconductor integrated circuits including, for example, memory arrays, charge pumps, RC filters, peaking amplifiers and various types of analog integrated circuits. In addition, capacitors are used in integrated circuits and chip packages for purposes of AC coupling and DC blocking. For example, capacitors can be implemented as series elements that couple RF energy from one part of a circuit to another part while blocking DC signals. In particular, in RF amplifier designs, DC blocking capacitors are used for interconnecting RF amplifier stages
Moreover, capacitors are commonly used in chip fabrication/package designs as decoupling capacitors to stabilize power supply voltages, i.e., minimize or eliminate power jitter. Indeed, high performance circuits require high capacitance, high quality (Q), and low-impedance decoupling capacitors between a DC power supply and ground lines to limit noise created by rapid switching of current, where such noise results from, inductive and capacitive parasitic impedances. The ability to reduce or eliminate such noise is particularly important for mixed-mode product designs (analog/digital), where it is necessary to work with very low signals. Insufficient decoupling capacitance can result in high power supply and ground noise.
In conventional designs, DC blocking and decoupling capacitors are implemented as discrete, off-chip components that are mounted inside a chip package module or on an electrical board (e.g., printed circuit board) on which a chip is mounted. Continuing advances in semiconductor IC chip fabrication and packaging technologies, however, is allowing the development of high-performance IC chips and chip package structures with increasingly higher levels of integration density, and lower fabrication costs. In this regard, IC chip and package designs utilize on-chip DC blocking and decupling capacitors, for example, to reduce chip package cost and to reduce module size. Moreover, the use of on-chip decoupling capacitors, for example, allows for higher performance designs as on-chip decoupling capacitors are more effective in reducing noise in power and ground lines when placed closer to the relevant loads.
Depending on the application, however, the use of on-chip capacitors can be problematic. For example, with high-density chip designs, there can be limited 2D/3D silicon space on the chip for building the integrated capacitors, resulting in practical limitations in integration density. Consequently, to achieve a desired level of integration for a given design, the sizes of the on-chip capacitors may be reduced, resulting in decreased performance. Moreover, the type of on-chip capacitor that is used in a given design may limit the level of performance and/or integration density achievable. For example, high-performance chips are typically fabricated using capacitor technologies that yield high quality factor (Q) capacitors, but such technologies do not scale well as integration density increases, as higher integration results in formation of capacitors with relatively poor performance due to increased parasitic impedances and plate resistance. Other capacitor technologies enable high-integration designs, but result in lower quality capacitors that are not useful in high-performance applications.
For instance, deep-trench or stacked capacitor techniques that are used in DRAM technology can be used to achieve high capacitance density, but can result in low quality capacitors. For instance, with such technologies, the thin dielectric layers that are formed on capacitor trench sidewalls and 3D-structures can not sustain high-voltage stress and thus, susceptible to breakdown. To address this problem, several capacitors must be serially connected to obtain an effective capacitance, but this technique results in four times increase in the area needed to construct the capacitors, and increase the cost of fabrication. Other conventional techniques using planar or 3-D MIM (metal-insulation-metal) capacitor, interdigitated structure, etc., may be used to form high-quality capacitors, but at the expense of consuming valuable silicon real estate on the chip front side.