Portable digital computers rely on rechargeable DC batteries to provide the electrical power necessary for operation. When the computer is powered on for processing operation, but allowed to remain idle, the battery continues nonetheless to supply current to all the components of the computer, including the central processing unit (CPU), memory, the chipset (e.g. the Southbridge) and the display of the computer. If the user fails to turn off the computer, the battery continues to supply full current and, eventually, becomes drained of the stored electrical power. The foregoing action leads to more frequent charging of the battery, and reduces the utility and usability of the computer system.
To reduce battery drain under such circumstances, a power management technique was previously introduced for portable computers, called the “sleep” mode. Typically, portable computers based on the INTEL X86 CPU and associated chip set, referred to as “PC's”, include multiple sleep modes (e.g. states of sleep mode). The multiple sleep modes enable the portable computer, when left idle, to selectively power down the components and devices of the computer in stages, although the main power remains on. With the computer spending an increasing amount of time idling, the computer progresses through increasingly deeper and deeper stages of sleep mode (and hence, greater reductions in power consumption). One of the deepest of those modes is characterized by all of the devices, including the CPU, but excepting the main memory (RAM) and the Southbridge chip, being powered down. This latter mode is typically referred to as “Suspend to RAM” (“STR”) or as “Power-on-Suspend” (“POS”) or like terms. In the STR condition power consumption is dramatically reduced and offers the greatest power reduction short of that power reduction obtained by turning off every component of the computer, the latter being referred to as “suspend to disk”, essentially completely shutting down the computer.
The sleep modes in the PC are defined and controlled by the operating system software, such as familiar Windows 9X, Unix, Linux and the like, in conjunction with the system BIOS of the computer. When in STR, the Southbridge portion of the chip set, which is responsible for power management of the PC, continues to monitor the keyboard and mouse (and/or resume key) of the PC for any user activity, signifying an end to the computer idle condition.
When the user later returns to perform computing and observes the computer is in a sleep mode, the user operates a “resume” key (or any key of the keyboard) or the like. That action initiates a chain of events in the computer transparent to the user, that restores full power to the CPU; and the computer recovers quickly. Return from the upper stages of the sleep mode recovers more quickly than recovery from the STR stage, the deepest stage after the Suspend to Disk stage, the latter recovery procedure being referred to as a “resume from STR”.
Of particular convenience, the user may immediately resume computing at the precise location in any application program that was active in the computer at the time the computer entered the sleep mode. To reach that point from the STR stage of sleep mode, the CPU processes a number of steps of the “boot-up” routine for the computer; steps that typically occur in a manner transparent to the user. The computer is able to resume where it left off, because, prior to entering STR, the computer preserved the complete state of all software applications and of all components and devices, including the CPU, in a memory that remained powered up during the “sleep”.
For the power management technique of sleep mode, the CPU and the external memory (DRAM) are independently supplied with power, that is, are located in separate power domains. In the deepest sleep mode, STR, power is removed from the CPU (and other electronic components of the computer, such as the display), while maintaining the DRAM memory and the Southbridge chip under power. The application programs and the state of those application programs (e.g. the CPU “context”) is preserved by transferring the state information to the DRAM.
In processing operation, the CPU executes application programs by continuously modifying both its internal state and memory contents according to the instructions of the program. The internal CPU memory of the X86 system resides in the same power domain as the CPU. Thus, whenever the CPU is powered down, such as for an STR procedure, the internal memory is also powered down, and normally results in the loss of that CPU context. In order for the CPU of the X86 system to resume processing of an application program on Resume from STR, the processor must at that time at least “know” the state of the program on entering STR. Before entering STR, the CPU executes an instruction (of the power management software) that saves the CPU context at a well defined location in external memory, such as the DRAM memory. That context information subsumes the state of the operating system and the state of the application program. By maintaining power to the DRAM during STR, the state information of the program is preserved, and is available for use later upon a Resume from STR.
Once the resume button is pressed and is detected by the Southbridge chip, power is reapplied to the CPU, which commences its start-up routines. The CPU processes the normal boot-up routine stored in the ROM of the BIOS chip. That boot up procedure initializes the internal registers of the CPU and flushes its caches, thereby establishing a baseline state for the CPU. The process takes a noticeable time in which to complete. However, prior to loading the operating system, such as Windows 9x, the routine checks to determine if the boot-up procedure is a “power up reset” as occurs upon initially powering up the computer, or instead is a Resume from STR. When the routine detects the latter condition, the computer “knows” that the state of the operating system software, any application program, and the corresponding CPU context already resides in the external memory (DRAM). The CPU then completes the boot-up procedure by restoring the device states, and, with a special instruction, finally restores the CPU context from the external memory. Thereafter, the CPU is able to simply proceed with executing the next application program instruction exactly where the CPU left off when entering STR.
In a stage of sleep mode that lies one stage above the STR stage, the penultimate stage (e.g. the pre-STR stage) referred to as “deep sleep”, existing operating systems issue an instruction to remove the system clock from the CPU, but to maintain the CPU powered up, continuing to consume battery power. The removal of the system clock reduces power consumption also, but that is not as great a reduction as when power is removed from the CPU, such as during STR. Without clock signals being applied, the CPU is no longer able to process (as would consume additional current), but maintains system context in the associated internal registers of the CPU. That context is not lost and is not required to be saved to external memory as is the case in entering the STR stage. As an advantage, the invention powers down the CPU in all sleep modes and preserves the CPU context, saving additional power.
Accordingly, an object of the invention is to reduce the power consumption of a computer during periods in which the computer is idle, providing a more effective sleep mode.
Another object of the invention is to promote the pre-STR stage of sleep mode in existing power management systems to the STR stage, creating an “Instant STR”, and reduce the time required by the computer system to return from that stage, ideally providing a Resume from STR that appears instantaneous.
And, a related object of the invention is to replace on-the-fly a CPU context maintaining sleep mode of existing computer systems that is governed by the operating system with a substitute sleep mode that affords a lower power consumption and remains transparent to the software.