The present invention relates in general to logic circuitry, and in particular, to self-timed logic circuitry.
Self-timed circuit techniques, once thought only as research-oriented projects, are quickly becoming mainstream in VLSI circuit applications. Requiring no clocks for operation, as does a traditional system, self-timed circuits operate asynchronously on the simple concept of demand. That is, a self-timed circuit operates only when asked to, generates the necessary outputs according to its own internal scheduling, and presents the results to the requester. Afterwards, the circuit xe2x80x9cgoes to sleepxe2x80x9d and awaits the next instruction/request. While asleep, no power is dissipated since no operation is taking place.
This is contrary to traditional synchronous systems where even when a circuit is not needed, there is at least power dissipated by the clock circuitry running through the system. This idle power can be significantxe2x80x94studies show that clocking power is approximately 30% of the overall power on a given VLSI circuit/chip. Consequently, self-timed circuits have at least a power advantage over traditional methods.
Self-timed circuits also have significant advantages over other techniques such as self-resetting. This approach requires no interaction between driving and receiving circuitry, creating scheduling and arrival time conflicts and complications. FIG. 1 shows an example of a self-timed logic circuit pipeline, or unit 100. Note in FIG. 1 that each block 101-104 labelled xe2x80x9cSelf-timed Logic Circuitxe2x80x9d can, itself, be a combination of self-timed circuits.
The operation of such a self-timed system is straightforward and is presented briefly below. Note that this example is an extremely small system. Also, note that each sub-block 101-104 labelled in FIG. 1 as a xe2x80x9cSelf-Timed Logic Circuitxe2x80x9d may, itself, contain multiple self-timed circuit stages and, thus, may also contain operation internally as described below:
The input source(s) indicates to the Self-Timed Logical Unit 100 by asserting the xe2x80x9crequestxe2x80x9d signal and enabling the xe2x80x9cdata inputsxe2x80x9d (a bus or multiple of bus signals). Note that the number of such sources is not limited to one, but is only shown as one in FIG. 1 for simplicity.
The first (receiving) Self-Timed Logic Circuit xe2x80x9caxe2x80x9d 101 notes that a xe2x80x9crequestxe2x80x9d has been made and returns the xe2x80x9cacknowledgexe2x80x9d signal to the source(s). This signifies to the sources that the information on the xe2x80x9cdata inputsxe2x80x9d has been received. The logic (not shown) that drives the source signals (xe2x80x9cdata inputsxe2x80x9d) is now free to de-assert the xe2x80x9cdata inputsxe2x80x9d, do other operations, etc., since the Self-Timed Logical Circuit xe2x80x9caxe2x80x9d 101 has received the input information and has begun operating.
Self-Timed Logic Circuit xe2x80x9caxe2x80x9d 101 operates on the xe2x80x9cdata inputsxe2x80x9d and produces a xe2x80x9cvalid output signalxe2x80x9d to Self-Timed Logic Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 along with xe2x80x9cdata output signalsxe2x80x9d. Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 receive the information and send xe2x80x9ccomplete outxe2x80x9d signals back to circuit xe2x80x9caxe2x80x9d 101 to signify capture of the incoming information. Circuit xe2x80x9caxe2x80x9d 101 is now free to de-assert the output information and, if necessary, receive further inputs from the logical unit input sources.
Self-Timed Logic Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 operate on the input information and produce xe2x80x9cvalid output signalsxe2x80x9d and xe2x80x9cdata output signalsxe2x80x9d, which are then sent to Self-Timed Logic Circuit xe2x80x9cdxe2x80x9d 104.
Circuit xe2x80x9cdxe2x80x9d 104 awaits for both xe2x80x9cvalid signalsxe2x80x9d to arrive, then returns a xe2x80x9ccomplete outxe2x80x9d signal back to both circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103. Circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103 are now able to de-assert their respective outputs and receive further information as necessary from circuit xe2x80x9caxe2x80x9d 101.
Self-Timed Logic Circuit xe2x80x9cdxe2x80x9d 104 operates on the information and produces a xe2x80x9cvalid output signalxe2x80x9d and xe2x80x9cdata output signalsxe2x80x9d to the external sink (not shown) in the overall chip system. Note that sinks (not shown) may be single or multiple, depending on the particular architecture and placement of a self-timed logical unit. When, the receiving units (sinks) signify that the information has been received (via xe2x80x9ccompletion signals from sinksxe2x80x9d) the Self-Timed Logic Circuit xe2x80x9cdxe2x80x9d 104 may de-assert its outputs and receive further information from circuits xe2x80x9cbxe2x80x9d 102 and xe2x80x9ccxe2x80x9d 103.
To control this operation, please refer to U.S. Pat. Nos. 5,565,798 and 5,708,374, which are hereby incorporated by reference herein.
As a result of this operation, it can be seen that in the general self-timed case, no registers are required. That is, in a completely self-timed system, the combination of valid/complete cycles removes the necessity of synchronization of internal units and sub-blocks as the units, in reality, time and clock themselves. Thus, self-timed circuits and systems synchronize themselves. Therefore, in the limit, a completely self-timed microprocessor, for example, would require no on-chip or off-chip clocks.
However, most self-timed circuitry is dynamic. As such, it is prone to errors created by noise events, as are all dynamic circuits, and, additionally, must distribute the self-timing clocks to every circuit. For example, consider the circuits of FIGS. 2A, 2B, and 2C, which were described in U.S. Pat. Nos. 5,565,798 and 5,708,374. (Some signals are not shown in FIG. 2A to reduce complexity and increase understanding of the present invention.) In this circuitry, each xe2x80x9cDomino Logic Rowxe2x80x9d of the xe2x80x9cSelf-Timed Macro Dataflowxe2x80x9d in FIG. 2C receives a clock signal (xe2x80x9cStrobexe2x80x9d or xe2x80x9cResetxe2x80x9d) from the control circuit in FIG. 2B. Note that each xe2x80x9cDomino Logic Rowxe2x80x9d is constructed of a collection of domino circuits.
One drawback of such a system is in the use of the dynamic circuits for all functions. That is, dynamic circuits are susceptible to noise events, which cause them to evaluate improperly and from which they cannot recover; they require a clock signal to be routed to each circuit, which increases the design complexity and the chip clocking loading; they create more on-chip noise due to precharge/evaluate events, fast edge rates, and the multitude of clock signals (noise coupling to adjacent lines); they cause test problems, particularly at elevated temperatures and voltages, much of which is necessary for reliability and screening; and they must wait upon the clock signal in order to start the evaluation process, which makes them susceptible to clock skew problems.
Static circuits, on the other hand, do not suffer from many of these issues: they can always recover from an incorrect evaluation, given enough time, and, consequently and importantly, a correct state can always be gained by waiting; they require no clock signals, which reduces the design complexity and global chip clock loading; they tend to reduce the overall chip noise as the precharge/evaluate nature is removed and the clock signals are not required; they are xe2x80x9cfriendlyxe2x80x9d to test at elevated temperatures and voltages as functionality is nearly always guaranteed; and they do not need to wait upon a clock signal for evaluation as one is not required. Also, they typically dissipate less power than their dynamic counterparts, mainly due to the removal of the clock signal to each circuit, which requires a switching clock signal every cycle regardless of the switching activity of the dynamic circuit. Examples of static circuits are illustrated in FIGS. 11A and 11B.
An important key, however, is performance. Dynamic circuits, with all their hazards and complications, consistently outperform static circuits in terms of delay. This means that critical circuit paths tend to be dynamic to produce the fastest chip possible, while non-critical circuit paths tend to be static to reduce power and design hazard as the performance is not critical (the chip (clock) speed is always set speed by the slowest possible path). In typical clock systems, this is not an issue as the latch boundaries separate the circuit styles, permitting static and dynamic circuits to coexist. This means, generally, that static and dynamic circuits can, effectively, be swapped in for one another without concern (the swapping can, obviously, change the delay and, thus, the critical path of the overall chip).
However, in a self-timed system, the use of static circuits is not as simple. For instance, consider the circuitry of FIG. 2C replaced with static circuitry (i.e., each xe2x80x9cDomino Logic Rowxe2x80x9d is replaced with a xe2x80x9cStatic Logic Rowxe2x80x9d). When the inputs (l through p) arrive, the circuitry of the first row begins to evaluate, regardless of the valid input signals. Similarly, the subsequent rows of the logic evaluate, ultimately producing the xe2x80x9cData Outputxe2x80x9d signals without regard to the valid and complete signals. The net result is that the interlocking concept created by the use of the dynamic circuits is lost when those circuits are replaced with static circuits. Consequently, the use of static circuits in such a system is nearly precluded.
The present invention addresses the foregoing limitations by providing a new self-timed circuitry system wherein static circuits can be used in a CMOS self-timed system. As a result, the benefits of static logic can be attained.
In one embodiment, the present invention is a self-timed logic circuit having a first transparent latch register for receiving one or more input data signals from one or more sources. The self-timed logic circuit also includes a control circuit operable for receiving one or more valid signals corresponding to each of the input data signals. A combinatorial static logic block then receives the one or more input data signals from the transparent latch register and performs one or more functions on the input data signals as a result of the static logic circuits within the logic block. A second transparent latch register then receives the output from the combinatorial static logic block. The control circuit will output the output data signals through the second transparent latch register to one or more sink circuits.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.