1. Field of the Invention
This invention relates to generally a digital multiplier and more particularly to a novel digital multiplier which is designed by using the neural network to simplify the network architecture and its circuits and to enhance its processing speed.
2. Description of the Prior Art
Recently, it has been gradually recognized that a typical digital computer having VON NEUMANN architecture is not suitable for a process requiring composite judgements or higher intellectual faculties despite a rapid development of the processing speed.
Furthermore, it is well known that the human brain allows the data to be processed in parallel type with associative memory and is also capable of recognition and memory from the partial information.
Accordingly, research involving so called neural computers which operate by imitating the parallel processing and associative memory concepts has been widely pursued all over the world.
In 1982, J. J. Hopfield proposed a neural network model which imitates the associative memory processing system of human brain, where the neural network is substituted with an anolog circuit and constructed with hardware using VLSI techniques (J. J. Hopfield, Proc. Nat'l. Acad. Sci. U.S.A., Vol. 79, P.P 2554-2558, April 1982).
Also, in 1986, J. J. Hopfield disclosed a model for solving the optimization problem and suggested a A/D converter as one example thereof. (D. W. Tank and J. J. Hopfield, IEEE Transactions on circuits and systems, Vol. CAS-33, No. 5, May 1986).
However, the above-mentioned A/D converter circuit has a drawback in that the A/D converter circuit becomes unstable due to the production of two local minimal values producing in the circuit.
For this reason, the A/D converter circuit should be provided with a separate compenstating circuit for stablization thereof.
On the other hand, in the typical digial multiplier, the binary multiplicand is multiplied in turn by each digit and these partial products are then added corresponding to each digit of the multiplier, so that an algorithm to obtain the final products is prosecuted.
At this time, the products have 2N bit, where the multiplicand having the binary N digits is multiplied by multiplier having N digits.
In order to implement the multiplication algorithm based upon VON NEUMANN concept, that is, the logic circuit concept, the serial multiplier and parallel multiplier are known.
However, the serial multiplier is relatively slow in the multiplier processing speed. The parallel multiplier has a multiplier processing speed faster than that of the serial multiplier, but has a drawback that it occupies a large area in the integrated circuit due to its complex circuit.