Embodiments of the present invention relate to circuits, and more particularly, to analog circuits for analog-to-digital converters.
Flash (or parallel) analog-to-digital converters (ADCs) are often employed in high speed communication devices in which it is desired to quickly convert an analog input voltage signal to a digital output voltage signal. FIG. 1 provides a high-level functional block diagram of a typical flash ADC. Differential voltage reference buffer 114 provides voltages VL2 and VL1 to resistor ladder network 106 at ports 116 and 118, respectively. Resistor ladder network 106 comprises 2nxe2x88x921 resistors 102. An analog input voltage signal is applied to analog input port 104, and 2nxe2x88x921 comparators 108 compare the latched analog input voltage to 2nxe2x88x921 voltages provided by resistor ladder network 106. The outputs of comparators 108 are provided to priority encoder 110, and priority encoder 110 encodes the outputs of comparators 108 into the digital output voltage on output port 112. The flash ADC of FIG. 1 is part of larger circuit 101, which may be, for example, a high speed communication device such as a Gigabit Ethernet PHY.
Resistor ladder network 106 is often implemented as one or more metallization layers in a silicon process, and as a result it tends to have a relatively low resistance. Resistor ladder network 106 is often bypassed with a large amount of capacitance, typically MOS (Metal Oxide Semiconductor) devices, as indicated by capacitors 120. It is usually desirable for differential voltage reference buffer 114 to provide a low impedance voltage source at ports 116 and 118 to resistor ladder network 106, where the voltage is stable with good immunity to low and high frequency power supply variations, as well as other environmental parameters.
FIG. 2 illustrates a functional diagram for differential voltage reference buffer 114 driving resistor ladder network 106. A reference voltage VREF2 is applied to the non-inverting input port of differential amplifier 202. Differential amplifier 202 and output stage 204 are configured to source a current I2 to port 116 and to provide reference voltage VREF2 at port 116. A reference voltage VREF1 is applied to the non-inverting input port of differential amplifier 206. Differential amplifier 206 and output stage 208 are configured to sink a current I1 from port 118 so as to provide reference voltage VRF1 at port 118. The average values Of I2 and I1 are substantially equal to each other, although the instantaneous values m ay not be equal due to capacitors 120.
FIG. 3A provides a circuit diagram for an OPAMP (operational amplifier) comprising differential amplifier 202 and output stage 204, and FIG. 3B provides a circuit diagram for an OPAMP comprising differential amplifier 206 and output stage 208. In FIG. 3A, a bias current biases a current mirror comprising nMOSFETs (n-Metal Oxide Semiconductor Field Effect Transistor) 302, 306, and 308. nMOSFET 306 provides bias current to a differential amplifier comprising nMOSFET differential pairs 310 and 312, and pMOSFET pairs 314 and 316. The gates of nMOSFETs 310 and 312 are the inverting and non-inverting input ports, respectively. The output stage comprises pMOSFET 318, which is Miller compensated via capacitor 320. nMOSFET 308 biases pMOSFET 318. Similar statements apply to the circuit of FIG. 3B.
Because of the relatively low resistance of resistor ladder network 106, a relatively large current is often needed to establish the correct voltage difference across resistor ladder network 106. As a result, the device sizes in output stages of differential voltage reference buffer 114 are often relatively large so as to handle the relatively large current through resistor ladder network 106. One consequence of this device size is that good PSSR (Power Supply Rejection Ratio) may be difficult to achieve. In particular, pMOSFETs tend to dominate the response from power supply variations compared to nMOSFETs because pMOSFETs are referenced to the supply voltage VDD and nMOSFETs are referenced to the ground (or substrate) voltage VSS. Furthermore, pMOSFETs in the signal path of an OPAMP may amplify power supply variations. In particular, pMOSFET 318 in the output stage of FIG. 3A may reduce the PSRR. However, improving the PSRR by employing external bypass capacitors may not be practical in a highly integrated environment such as a communication transceiver, e.g., a Gigabit Ethernet PHY.