1. Field of the Invention
The present disclosure relates to a phase locked loop realizing high bandwidth using a rising edge and a falling edge of a reference signal and a feedback signal.
2. Description of the Related Art
A phase locked loop PLL is a frequency feedback circuit for generating an output signal with desired frequency and phase in response to a reference signal (clock signal) inputted from an external device, and it has been widely used in a frequency synthesizer or a clock recovery circuit, etc.
FIG. 1 is a view illustrating schematically a charge pump type phase locked loop as an example of a conventional analog phase locked loop.
In FIG. 1, the conventional analog phase locked loop 100 includes a phase frequency detector (PFD) 110, a charge pump (CP 120), a loop filter 130 and a voltage control oscillator 140.
The phase frequency detector 110 outputs a phase difference signal by comparing a reference signal with a feedback signal. The charge pump 120 supplies charges in proportion to a pulse width of the phase difference signal, and the loop filter 130 changes a voltage according to change of amount of charged charges. The voltage control oscillator 140 outputs a signal having a specific frequency depending on the changed voltage, i.e. control voltage. The signal outputted from the voltage control oscillator 150 is inputted to the phase frequency detector 110 by feedback. The phase frequency detector 110 compares generally only one of a rising edge or a falling edge of the reference signal and the feedback signal, and outputs the signal in proportion to the phase difference of the reference signal and the feedback signal.
The analog phase locked loop 100 may include further a divider (not shown). The divider locates on a feedback path, and divides a frequency of the signal outputted from the voltage control oscillator 150.
In the conventional analog phase locked loop 100, the bandwidth of the analog phase locked loop 100 should be widened so as to enhance detection velocity of phase and frequency. However, the bandwidth of the phase locked loop 100 is limited to 1/10 or less of a frequency of the reference signal to assure stability of the phase locked loop 100, due to a sampling operation of detecting the phase difference at the rising edge or the falling edge of the reference signal and the feedback signal.
FIG. 2 is a view illustrating schematically conventional digital phase locked loop.
In FIG. 2, the conventional digital phase locked loop 200 includes a time-to-digital converter (TDC) 210, a digital loop filter (DLF) 220 and a digitally controlled oscillator (DCO) 230.
The TDC 210 outputs a digital code corresponding to phase difference between rising edges of a reference signal and a feedback signal. The digital loop filter 220 provides a digital code for controlling a frequency of the digitally controlled oscillator 230 by low-pass-filtering the digital code outputted from the TDC 210.
The digital phase locked loop 200 may include further also a divider (not shown). The divider locates on a feedback path, and divides a frequency of the signal outputted from the digitally controlled oscillator 230.
FIG. 3 is a view illustrating conceptually operation waveform of the digital phase locked loop in FIG. 2.
In FIG. 3, it is assumed that the TDC 210 outputs a digital code corresponding to negative decimal number when the rising edge of the feedback signal precedes the rising edge of the reference signal, and outputs a digital code corresponding to positive decimal number when the rising edge of the feedback signal follows the rising edge of the reference signal.
Since the rising edge of the feedback signal precedes the rising edge of the reference signal, the TDC 210 outputs the digital code corresponding to the negative decimal number, and an absolute value of an output of the TDC 210 reduces because phase difference between the rising edges of the signals reduces according as a time lapses. The digital loop filter 220 low-pas-filters the output of the TDC 210, thereby controlling the frequency of the digitally controlled oscillator 230 once every period.
However, the bandwidth of the conventional digital phase locked loop 200 is also limited to 1/10 or less of a frequency of the reference signal so as to assure stability, like the analog phase locked loop.