1. Field of the Invention (Technical Field)
The present invention relates to the field of digital signal processing.
Delta Sigma technology has been widely used in converting analog signals to digital signals, it has not been commonly applied in digital signal processing, because of the lack of Delta Sigma based linear processing circuits. Here, this invention is directed to an alternative method using a 1-bit DSP system to process Delta Sigma bit-streams directly.
2. Description of Related Art
In digital signal processing systems, the most important linear circuits are adders, coefficient multipliers, and compressors. To build those circuits with low noise and complexity, pure digital implementations are preferable. However, some previous Delta Sigma processing methods focused on modifying the Delta Sigma modulators, J. Melanson, “Signal processing system using delta-sigma modulation having an internal stabilizer path with direct output-to-integrator connection,” U.S. Pat. No. 7,696,913, 2010; J. Choi, S. Han, J. Jang, and H. Yu, “Structure of delta-sigma fractional divider,” U.S. Patent Publication No. 2003/0108143; M. Cho, Y. Kim, and J. Kwon, “Coefficient multiplier and digital delta sigma modulator using the same,” U.S. Patent Publication No. 2011/0140940, instead of processing the modulated bit-stream. Moreover some solutions are hindered by involving analog operations, A. Niwa and Y. Ueno, “Delta-sigma modulator and signal processing system,” U.S. Pat. No. 8,581,763, 2013; T. Moue, “Delta-sigma modulator and signal processing system,” U.S. Pat. No. 8,581,764, 2013; V. F. Dias, “Signal processing in the sigma-delta domain,” Microelectron. J., vol. 26, pp. 543-562, 1995, or tri-state digital circuits, C.-W. Ng, N. Wong, and T.-S. Ng, “Bit-stream adders and multipliers for tri-level sigma delta modulators,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 54, no. 12, pp. 1082-1086, December 2007, which increase the complexity of the circuits. Other designs are impeded by their ability of processing only first-order Delta Sigma bit-streams, N. Kouvaras, “Operations on delta-modulated signals and their application in the realization of digital filters,” Radio and Electronic Engineer, vol. 48, no. 9, pp. 431-438, September 1978; N. Kouvaras, “Some novel elements for delta-modulated signal processing,” Radio and Electronic Engineer, vol. 51, no. 5, pp. 241-250, May 1981; N. Kouvaras and J. Karakatsanis, “A technique for a substantial reduction of the quantization noise in the direct processing of delta-modulated signals,” Signal Processing, vol. 8, no. 1, pp. 107-119, 1985; N. Kouvaras, “Modular network for direct complete addition of delta modulated signals with minimum quantization error,” International Journal of Electronics, vol. 59, no. 5, pp. 587-595, 1985; H. Fujisaka, R. Kurata, M. Sakamoto, and M. Morisue, “Bit-stream signal processing and its application to communication systems,” Circuits, Devices and Systems, IEE Proceedings, vol. 149, no. 3, pp. 159-166, 2002; K. Matsuyama, H. Fujisaka, and T. Kamino, “Arithmetic and piecewise linear circuits for sigma-delta domain multi-level signal processing,” in 2005 International Symposium on Nonlinear Theory and its Applications (NOLTA 2005), October 2005, pp. 58-61; Y. Hidaka, H. Fujisaka, M. Sakamoto, and M. Morisue, “Piecewise linear operations on sigma-delta modulated signals,” in Electronics, Circuits and Systems, 2002. 9th International Conference on, vol. 3, 2002, pp. 983-986 vol. 3; D. Zrilic, “Method and apparatus for mixed analog and digital processing of delta modulated pulse streams including digital-to-analog conversion of a digital input signal,” U.S. Pat. No. 5,349,353, 1994; D. Zrilic, “Circuits and methods for functional processing of delta modulated pulse density stream,” U.S. Pat. No. 6,285,306, 2001; S. Horianopoulos, V. Anastassopoulos, and T. Deliyannis, “Design technique for hardware reduction in delta modulation fir filters,” International Journal of Electronics, vol. 71, no. 1, pp. 93-106, 1991; A. Pneumatikakis, V. Anastassopoulos, and T. Deliyannis, “Realization of a high-order iir delta sigma filter,” International Journal of Electronics, vol. 78, no. 6, pp. 1071-1089, 1995; P. O'Leary and F. Maloberti, “Bit stream adder for oversampling coded data,” Electronics Letters, vol. 26, no. 20, pp. 1708-1709, September 1990; Y. Liang, Z. Wang, Q. Meng, and X. Guo, “Design of high speed high SNR bit-stream adder based on delta sigma modulation,” Electronics Letters, vol. 46, no. 11, pp. 752-753, May 2010; D. McGrath, “Method and apparatus for processing sigma-delta modulated signals,” U.S. Pat. No. 5,990,818, 1999, which do not fit the widely used higher-order Delta Sigma modulators. Furthermore adders in Kouvaras can only take two inputs. So far the most promising structure of processing higher-order Delta Sigma bit-stream is the digital Delta Sigma modulator proposed by Fujisaka et al. in H. Fujisaka, M. Sakamoto, C.-J. Ahn, T. Kamio, and K. Haeiwa, “Sorter based arithmetic circuits for sigma-delta domain signal processing—part ii: Multiplication and algebraic functions,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, no. 9, pp. 1966-1979, September 2012. Although that system has achieved higher-order noise shaping with high signal-to-noise-plus-distortion-ratio (SNDR), the complicated sorting network in Fujisaka et al. requires a great amount of circuit resources, which may work better with future quantum device. T. Katao, Y. Suzuki, H. Fujisaka, T. Kamio, C.-J. Ahn, and K. Haeiwa, “Single-electron arithmetic circuits for sigma-delta domain signal processing,” in Nanotechnology, 2008. NANO '08. 8th IEEE Conference on, August 2008, pp. 729-732.
The Delta Sigma average adder proposed by N. Kouvaras [N. Kouvaras, “Operations on delta-modulated signals and their application in the realization of digital filters,” Radio and Electronic Engineer, vol. 48, no. 9, pp. 431-438, September 1978] is shown in FIG. 1. It uses a binary full adder with switched role of sum and carry output. It can take only two inputs. The analog value of the output bit stream is the average value of the two input bit stream, instead of the sum.
The Delta Sigma coefficient multiplier [N. Kouvaras, “Operations on delta-modulated signals and their application in the realization of digital filters,” Radio and Electronic Engineer, vol. 48, no. 9, pp. 431-438, September 1978] based on the average adder is shown in FIG. 2.
The tri-state Delta Sigma adder [IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 12, pp. 1082-1086, December 2007] is shown proposed by Chiu-Wa Ng. et al. is shown in FIG. 3. The circuit uses tri-state digital signals, which is not well compatible with current bi-state digital technology.
The digital Delta Sigma modulator proposed by David A. Johns [David A. Johns and David M. Lewis: Design and Analysis of Delta Sigma Based IIR Filter, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. Vol. 40, No. 4, April 1993, pp. 233-240] is shown in FIG. 4. The main application is digital filtering. The digital Delta Sigma modulator does not have a toggling multiplexer thus the output noise is high.
The Delta Sigma adder based on sorting network proposed by Fujisaka et. al., [H. Fujisaka, M. Sakamoto, C.-J. Ahn, T. Kamio, and K. Haeiwa, “Sorter based arithmetic circuits for sigma-delta domain signal processing—part ii: Multiplication and algebraic functions,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, no. 9, pp. 1966-1979, September 2012.] is shown in FIG. 5. The circuit uses complex sorting networks.