The present invention relates to an expanded memory of a so-called LIM system, which is a type of expanded memory system.
Recently, the memory capacity of personal computers has been increased, and a variety of expanded memory systems have been proposed. In an expanded memory of the LIM type, a portion of a memory address space of a central processing unit (CPU) is used as a window, and the CPU accesses a memory of a maximum of 8 MB through the window. The specification of the LIM system was developed by joint research of three U.S. companies, Lotus Development, Intel, and Microsoft Corp. The LIM expanded memory board is a commercially available product sold by Intel under the trademark "ABOVE BOARD".
FIG. 14 shows an arrangement of an expanded memory utilizing the LIM system. Four contiguous windows are provided for accessing the expanded memory in units of 16 KB. Each 16-KB window is called a physical page, and a combination of the four physical pages is called a page frame. The expanded memory that is accessed through each physical page has a 16-KB unit called a logical page. There are a maximum of 512 logical pages, and the total amount is 16 KB.times.512=8 MB. The correspondence between the physical and logical pages is established by changing the content of an I/O port address, which is called a page controlling register, under the control of the CPU. The CPU can access a maximum of 8-MB of expanded memory.
FIG. 15 is a block diagram of a prior-art system. Each expanded memory has a set number, and corresponds to an I/O port address of the page controlling register. Each expanded memory includes four page controlling registers. A page controlling register of physical page Y and set X (X=0, 1, 5, 6; Y=0, 1, 2, 3) has a format shown in FIG. 16. In FIG. 16, the bits of the page controlling register have the following meanings:
PE: page enable bit
0: disable
Mapping from physical page Y to a logical page is not performed in the range of the logical page of set X.
1: enable
Mapping from physical page Y to a logical page is performed in the range of the logical page of set X.
PAi: page address bit (i=0 to 6)
A logical page for mapping physical page Y is designated. If PE=0, this bit is invalid.
The system operation will be described below with reference to FIG. 15. CPU 110 accesses conventional memory 130, extended memory 140, and expanded memories 810, 820, 830, and 840 through system bus 120. When expanded memories 810, 820, 830, and 840 are to be accessed, CPU 110 sets arbitrary values in page controlling registers 811, 821, 831, and 841 by I/O write.
Assume that data in physical page Y is mapped to logical page Z (Z=0, 1, . . . , 511). Set X, including logical page Z to which physical page Y is to be mapped, is determined. An offset value for mapping data in physical page Y to the logical page of set X is then calculated. The offset value is set to be PAi, and the CPU I/O writes 8-bit data having PE=1 in the page controlling register of page Y and set X to which data is mapped. At the same time, the CPU I/O writes 8-bit data having PE=0 in the page controlling registers of other sets. Note that PAi in other page controlling registers is an arbitrary value. When CPU 110 performs memory access to physical page Y after data is set in the page controlling register, only a set having PE=1 of page controlling registers 811, 821, 831, and 841 is selected. The CPU executes memory access to corresponding ones of memory chips 813, 823, 833, and 843.
Along with development of the semiconductor technique, highly integrated memory chips can be used, and four expanded memories 810, 820, 830, and 840 shown in FIG. 15 can be formed on one board.
In addition, four expanded memories 810, 820, 830 and 840, conventional memory 130, and extended memory 140 can be integrated on one system board. However, in such a system, the control circuit is complicated and cost is undesirably high.
As for the expanded memory, the PA bit length of the page controlling register may be increased from 7 bits to 9 bits, so that all the 512 logical pages are controlled by a single page controlling register. However, with this system, the page controlling register is different from that in the prior-art system, resulting in poor software compatibility.