1. Field of the Invention
This invention relates to analog circuits for converting an input voltage into an output current, and more particularly to analog circuits for converting a differential input voltage to a differential output current.
2. Description of Related Art
A transconductor is a circuit which receives an input voltage and generates an output current. The magnitude of the output current is proportional to the input voltage received, and the ratio by which the output current changes for a given ratio of input voltage change is known as the conversion gain, or transconductance (G.sub.m =.DELTA.I.sub.out /V.sub.IN) of the transconductor. A differential transconductor receives a differential voltage impressed between two voltage input terminals, and generates a differential current between two current output terminals. The common-mode voltage of the two voltage input terminals is ignored. In other words, a first current is generated on one of the current output terminals, and a second current is generated on the other current output terminal, and the difference between the first and second currents is known as the differential current appearing at the pair of current output terminals.
A differential transconductor known in the art is shown in FIG. 1. A differential input voltage, V.sub.L -V.sub.R, is received between voltage input terminals 42 and 52, and a corresponding differential output current is generated between current output terminals 48 and 58. A current source circuit 30 includes a current source 32 which delivers a current of magnitude I.sub.O into summing node 36 and further includes a current source 34 which delivers a current of magnitude I.sub.O into summing node 38. Input circuit 40, which enhances the transconductance of transistor 46, includes an op-amp 44 having a non-inverting input coupled to the voltage input terminal 42 and an inverting input coupled to the summing node 36. The output of op-amp 44 drives the gate of transistor 46, which is a P channel MOS transistor. Transistor 46 couples summing node 36 to the current output terminal 48. A second input circuit 50, which enhances the transconductance of transistor 56, includes an op-amp 54 having a non-inverting input coupled to the voltage input terminal 52 and an inverting input coupled to summing node 38. The output of op-amp 54 drives the gate of transistor 56, which is also a P channel MOS transistor. Transistor 56 couples summing node 38 to the current output terminal 58. A resistor 35 having a resistance of R ohms couples summing node 36 to summing node 38. As is common with differential circuits, current source 32 and input circuit 40 are matched to current source 34 and input circuit 50, respectively, to provide balanced differential operation.
The operation of this circuit can best be understood by looking initially at the left-most portion. Input circuit 40 functions to force the voltage of summing node 36 to follow the input voltage, V.sub.L , received on voltage input terminal 42. This occurs because the op-amp 44 drives the gate of transistor 46 to a suitable voltage such that the voltage of summing node 36, which is coupled to the inverting input of op-amp 44, follows the input voltage, V.sub.L, coupled to the non-inverting input of op-amp 44. For example, if the voltage of summing node 36 is too high, the output of op-amp 44 is driven lower, thus providing more gate drive to P channel transistor 46. Consequently, a higher current flows through transistor 46 which lowers the voltage of summing node 36 until the voltage at summing node 36 is equal to the voltage at non-inverting input terminal of op-amp 44. Similarly, for the right-most portion, input circuit 50 functions to force the voltage of summing node 38 to follow the input voltage, V.sub.R, received on voltage input terminal 52 of op-amp 54. This occurs because the op-amp 54 drives the gate of transistor 56 to a suitable voltage such that the voltage of summing node 38, which is coupled to the inverting input of op-amp 54, follows the input voltage, V.sub.R, coupled to the non-inverting input of op-amp 54. Thus, with the voltage of summing node 36 following input voltage V.sub.L and the voltage of summing node 38 following input voltage V.sub.R, the differential input voltage V.sub.L -V.sub.R is placed across resistor 35, and causes a current I.sub.S of magnitude (V.sub.L -V.sub.R)/R to flow from summing node 36 to summing node 38. If V.sub.R is greater in magnitude than V.sub.L then a negative current I.sub.S flows from summing node 36 to summing node 38 which, of course, is equivalent to a positive current flow from summing node 38 to summing node 36.
Summing node 36 receives a current I.sub.O from current source 32, and sources a current I.sub.S flowing into summing node 38. Thus, the net current which is provided to the source of transistor 46 is I.sub.O -I.sub.S. The current, I.sub.L, coupled to current output terminal 48 must also be equal to I.sub.O -I.sub.S because the sum of currents received into any node must equal zero. Similarly, summing node 38 receives a current I.sub.O from current source 34, and receives a current I.sub.S flowing from summing node 36. Thus, the net current received into summing node 38 is I.sub.O +I.sub.S, which is coupled by transistor 56 to the current output terminal 58 as I.sub.R =I.sub.O +I.sub.S.
The topology of this circuit is generally known as a degenerated pair linearized by servo-feedback, and is also known as a linearized resistor-based transconductor. The distortion produced by transistors 46 and 56 is reduced by the loop gain of the op-amps 44, 54, respectively. The use of a resistor in setting the conversion gain of the transconductor results in high linearity, but also results in a conversion gain which is fixed by the choice of resistor value, and which varies with semiconductor process parameter variations. Notwithstanding these advantages, additional flexibility is desired to allow a wider variety of usage. In particular, a programmable transconductor would allow selecting the desired conversion gain after semiconductor manufacturing.