Conventionally, a thermal chemical vapor deposition (CVD) method has been used when forming insulation layers that require a high voltage withstand characteristic or an excellent leakage characteristic used for, for example, gate oxide films of semiconductor elements represented by, for example, a large scale integrated circuit (LSI), a charge coupled device (CCD) and a metal oxide semiconductor (MOS) transistor. However, when a silicon oxide film requiring a high insulation property is formed using the thermal CVD method as described above, the silicon substrate needs to be exposed to a high temperature. Then, there is a problem in that, when, for example, a conductive layer has been already formed on a silicon substrate by a low melting-point material such as, for example, a low melting-point metal or a high molecular compound, the low melting-point metal may be melted.
From the viewpoint of recent high integration of devices, what is needed is a high quality film that is excellent in coating property or uniformity over steps on, for example, a three dimensional structure and is free of impurities or physical defects in the insulation film or an interface. Atomic layer deposition (ALD) capable of forming a film by supplying a reactant gas repeatedly to a surface of a substrate substantially in atomic unit is known as one of effective means for solving these problems.
A technology of conducting different deposition processes within a single chamber, i.e. one chamber (a processing container) is disclosed in Japanese Patent Laid-Open Publication No. 2007-138295 (Patent Document 1).