1. Field of the Invention
The present invention relates to a metal oxide silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel layer to effectively adjust threshold voltage, to improve the uniformity of threshold voltage, to prevent the electric characteristics of the device, such as the breakdown voltage, the punch-through effect and the drain-induced barrier lowering (DIBL), from being deteriorated by isolating source/drain regions.
2. Description of prior Art
In general, the source/drain regions and the channel of the MOSFET are formed on a semiconductor substrate or a silicon-on-insulator (SOI) substrate using the ion implantation process. To use the MOSFET at high frequency, its channel length must be short. However, in the case where the channel length is short, the source/drain breakdown voltage is inevitably decreased and the drain-induced barrier lowering and the punch-through effects are caused to deteriorate the device. Furthermore, there exist the trade-off problem between high frequency and high breakdown voltage.
FIG. 1 is a cross sectional view illustrating a MOSFET in accordance with the first embodiment of a prior art.
As shown in FIG. 1, an active region is defined by forming a field oxide layer 2 by applying the thermal oxidation process to a semiconductor substrate 1, such as a silicon substrate. A channel region 12 is formed by implanting ions into the active region so as to adjust the threshold voltage. A gate electrode 4 is formed on the channel region 12 and a gate oxide layer is formed between the gate electrode 14 and the channel region 12. The low concentration ion implantation process is carried out so that lightly doped regions 5 are formed on the sidewalls of the gate electrode 4. Also, after forming the spacer oxide layer 6 on the both sidewalls of the gate electrode 4, a highly doped region 7 is formed in the semiconductor substrate 1 and both sides of the gate electrode, using the high concentration ion implantation process. Accordingly, the LDD structures, which includes the lighting and highly doped regions 5 and 7, are formed both sides of the gate electrode 4, respectively. For example, a source region 8A and a drain region 8B are formed in the semiconductor substrate 1, respectively. A metal silicide layer 9 is formed on the exposed gate electrode 4 and semiconductor substrate 1, and an interlayer insulation layer 10 is formed on the resulting structure. After forming contact holes exposing the source region 8A and the drain region 8B using the photolithography and etching processes, a metal wiring 11 is formed on the source region 8A and the drain region 8B.
As stated above, since the source regions 8A, the drain region 8B and the channel region 12 are formed in the single crystalline silicon substrate by the ion implantation processes, the length of the gate electrode 4 must be short to increase the operating speed of the device. However, the short gate electrode may cause the breakdown voltage to be decreased because of the short distance between the source region 8A and the drain region 8B. Also, because the drain-induced barrier lowering and the punch-through are generated in the depletion layer between the source region 8A and the drain region 8B, it may be very difficult to implement a high performance transistor.
In other words, there exist the inevitable trade-off problem between high frequency and the high breakdown voltage. It is difficult to make the concentration of the channel region 12 uniform and then the uniformity of the threshold voltage is poor. Furthermore, because the source region 8A and the drain region 8B are formed in the single crystalline silicon substrate by the ion implantation processes, the maximum value of the impurity concentration in the source and drain regions 8A and 8B is low and then a parasite resistivity will become higher.
FIG. 2 is a cross sectional view illustrating a MOSFET in accordance with the second embodiment of the prior art.
A silicon-on-insulator (SOI) substrate 21 consists of a lower silicon layer 21A, an insulting layer 21B and an upper silicon layer 21C. An active region 22 and a field region 23 are defined by forming a field oxide layer and by implanting impurity ions into the upper silicon layer 21C two times. If the first impurity ions are N-type (or P-type) ions, the second impurity ions are P-type (or N-type) ions. That is, if the active region 22 has N-type (or P-type) ions, the field region 23 has P-type (or N-type) ions.
As shown in FIG. 2, the active region is defined by forming the field oxide layer 23 by applying the thermal oxidation process to the semiconductor substrate 21, such as a silicon substrate. A channel region 24 is formed by implanting ions into the active region so as to adjust the threshold voltage. A gate electrode 26 is formed on the channel region 24 and a gate oxide layer is formed between the gate electrode 26 and the channel region 24. The low concentration ion implantation process is carried out so that lightly doped regions 27 are formed on the sidewalls of the gate electrode 26. Also, after forming the spacer oxide layer 28 on the both sidewalls of the gate electrode 26, a highly doped region 29 is formed in the active region and both sides of the gate electrode, using the high concentration ion implantation process. Accordingly, the LDD structures, which includes the lightly and highly doped regions 27 and 29, are formed both sides of the gate electrode 26, respectively. For example, a source region 30A and a drain region 30B are formed in the active region, respectively. A metal silicide layer 31 is formed on the exposed gate electrode 26 and the upper silicon layer 21c and an interlayer insulation layer 32 is formed on the resulting structure. After forming a contact hole exposing the source region 30A and the drain region 30B using the photolithography and etching processes, a metal wiring 33 is formed on the source region 30A and the drain region 30B.
As stated in the second embodiment, since the source regions 30A, the drain region 30B and the channel region 24 are formed in the upper silicon layer 21c of the single crystalline by the ion implantation processes, the length of the gate electrode 26 must be short to increase the operating speed of the device. However, the short gate electrode may cause the breakdown voltage to be decreased because of the short distance between the source region 30A and the drain region 30B. Also, because the drain-induced barrier lowering and the punch-through are generated in the depletion layer between the source region 30A and the drain region 30B, it may be very difficult to implement a high performance transistor.
In other words, there exist the inevitable trade-off problem between high frequency and the high breakdown voltage. It is difficult to make the concentration of the channel region 24 uniform and then the uniformity of the threshold voltage is poor. Furthermore, because the source region 30A and the drain region 30B are formed in the single crystalline silicon substrate by the ion implantation processes, the maximum value of the impurity concentration in the source and drain regions 30A and 30B is low and then a parasite resistivity is high.