Recent development of leading-edge CMOS (complementary MOS) devices with advancing miniaturization of transistors has encountered a problem of driving current degradation caused by depletions of gate electrodes. For the purpose of improving driving performance, a technology using metallic materials instead of traditional polycrystalline silicon, so called a metal gate technology, is being studied.
On the other hand, the miniaturization of the transistors requires thinning of gate insulating films, which causes an increase of gate leakage currents. For the purpose of reducing power consumption, the use of high dielectric constant materials (High-k material) to physically thicken the gate insulating film is being studied to reduce the gate leakage currents.
Materials of metal gate electrodes under consideration include pure metal and metal nitride or silicide materials and so on. Any material is required: (1) not to cause degradation of the gate insulating film at the time of the metal gate electrode formation; and (2) to allow threshold voltages (Vth) of an N-type MOSFET and a P-type MOSFET to be set to appropriate values.
In order to achieve a threshold voltage of ±0.5 eV or less in a CMOS transistor, the gate electrode is required to be made of a material having a work function equal to the midgap (4.6 eV) of Si or less, more desirably 4.4 eV or less, in the N-type MOSFET, and a material having a work function equal to the midgap (4.6 eV) of Si or more, more desirably 4.8 eV or more, in the P-type MOSFET.
As a means of realizing these requirements, a method for controlling Vth of a transistor (Dual metal gate technology) has been proposed in which the gate electrode of the N-type MOSFET and the gate electrode of the P-type MOSFET are made of a different metal or alloy having an optimal work function for each and are made through different processes, respectively.
For example, non-patent document 1 (International electron devices meeting technical digest 2002, p. 359) states that Ta and Ru formed on SiO2 have work functions of 4.15 eV and 4.95 eV, respectively, and the work function can be modulated by 0.8 eV between these two electrodes.
However, the dual metal gate technology requires individual formation of metal layers made of different kinds of metals or alloy having different work functions on a substrate and involves a process of removing the metal layer deposited on a gate insulating film of either P-type MOSFET or N-type MOSFET by etching technique. During the etching removal, the gate insulating film is degraded in quality, and consequently, the characteristics and reliability of the device are impaired.
On the other hand, a technique relating to a silicide gate electrode obtained by fully siliciding an electrode pattern of polycrystalline silicon with Ni has been proposed. In this technique, the electrode pattern of the polycrystalline silicon can be silicided through a salicide process after a high-temperature heat treatment for activating impurities in a source/drain diffusion region of a CMOS. This technique provides good compatibility with typical CMOS processes and does not require etching removal of deposited films on the gate insulating film, which is necessary in the dual metal gate technology, therefore preventing damage to the gate insulating film.
Especially, non-patent document 2 (International electron devices meeting technical digest 2004, p. 91) discloses that a MOSFET, including a HfSiON high dielectric constant film used as a gate insulating film and a fully silicided Ni silicide electrode used as a gate electrode, can control its wide-ranging effective work function by controlling the composition of the Ni silicide through the use of crystal phase formation. In addition, non-patent document 2 states that a threshold voltage of ±0.3 V is feasible by means of the formation of Ni3Si phase, NiSi phase and NiSi2 phase.