Bus arbitration protocols and methods for arbitrating bus access are well known in the art. Typically, the arbitration or protocol is designed to reduce the arbitration overhead when one of two subsystems continuously use a system bus. The arbitration protocol is also used to guarantee fairness thus insuring equal access to the system bus.
One example of an arbitration system decides who is sending and who is listening by way of a symmetrical protocol. Typically, three clock cycles are required in the symmetrical protocol where one cycle is used for sending a request, a second cycle is used for the arbitration, and a third cycle is used for the response with the proper selection.
Another example of an arbitration protocol uses a master-slave relationship where one system is the master and the other is the slave, such that the slave always makes requests for the bus while the master arbitrates whether to grant bus access to the slave. Like the symmetrical protocol, the master slave system requires at least three cycles to perform arbitration and grant bus access to any subsystem.
Multi-processor systems have shown that high bandwidth can be achieved using a cross-bar switch. Very large scale integration (VLSI) in semiconductor devices has led to the increased use of the cross-bar switch in semiconductor devices with requirements of low latency and high speed. One technique used multiple stages requiring several switches be set between input and output. Multiple stages increase latency and control complexity. Moreover, a particular problem with semiconductor devices communications, is the worst case delay resulting from two ports on a crossbar switch that are physically separated. In such an instance, communications must be carried out over long wire lengths on the semiconductor device in the range, of 2 to 10 millimeters. The communications frequently consist of an input buffer generating a request, and an output buffer generating an accept with the request and the accept traversing the long wire lengths.
It is desirable to have a crossbar switch protocol for reducing the number of cycles required for updating input/output data buffers by arbitration logic in a crossbar switch to one cycle.