1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device. Particularly, the present invention relates to a semiconductor device having a capacitor such as a DRAM (Dynamic Random Access Memory), and a method of fabricating such a semiconductor device.
2. Description of the Background Art
Reflecting the remarkable development of semiconductor devices in recent years, there is a great diversity in the category of semiconductor devices in accordance with their application and function. There are a plurality of methods in fabricating a semiconductor device of the same type. It is desirable to select an appropriate fabrication method matching their application and function. For example, there are various formation methods for a capacitor indispensable in a DRAM. It has become critical to select the optimum method of forming a capacitor according to the application and function.
A DRAM is generally constituted by a memory cell array which is the storage region to store various storage information, and a logic circuit controlling memory cells in the memory cell array for data input/output with an external source. A memory cell array is formed of a plurality of memory cells in a matrix, storing unitary storage information. In a general DRAM, a memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected to the MOS transistor to store information. Such a memory cell is well known as a one-transistor one-capacitor type memory cell.
FIG. 13 is a schematic sectional view of a one-transistor one-capacitor memory cell in a DRAM to describe a structure thereof. Referring to FIG. 13, a plurality of MOS transistors 120 are formed at a main surface of a semiconductor substrate 101 electrically isolated by an isolation film 102 which is an element isolation region. MOS transistor 120 includes a source/drain diffusion layer 121 at an active region of the main surface of semiconductor substrate 101.
Three major layers are deposited on the main surface of semiconductor substrate 101. As shown in FIG. 13, the gate electrode layer and the like of MOS transistor 120 are formed at the lower most layer A of the three layers. At the intermediate layer B, a capacitor 110 and the like are formed. At the top most layer C, a metal line 133 and the like connecting memory cells with each other are formed.
First, the lower most layer A will be described. The main surface of semiconductor substrate 101 is covered by a thin gate oxide film 122. A gate electrode layer 123 is formed at a predetermined position above gate oxide film 122. Although not depicted, gate electrode layer 123 is constituted by a floating gate formed of a polycrystalline silicon layer into which impurities are introduced (referred to as xe2x80x9cdoped polysilicon layerxe2x80x9d hereinafter), and a control gate formed of a tungsten silicide (WSi2) layer.
A silicon nitride film 125 is formed on gate electrode layer 123. A sidewall 124 formed of a silicon oxide film is provided at the sidewall of gate electrode layer 123. Regarding the pair of source/drain diffusion layers 121, a pad layer 131a is connected to one of source/drain diffusion layers 121 and each bit line 131b is connected to the other of source/drain diffusion layers 121. An interlayer insulating film 103 is formed all over the main surface of semiconductor substrate 101 so as to fill the gap between pad layer 131a and bit line 131b and cover the surface of MOS transistor 120.
The intermediate layer B will be described here. On interlayer insulating film 103 of the above-described lower most layer A, a silicon nitride film 104 that is a stopper film for the formation of a trench used to form a capacitor, and a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film 105 which is a spacer film are formed at the intermediate layer B. A trench for formation of a storage node is formed at a predetermined position in silicon nitride film 104 and BPTEOS film 105 so as to arrive at interlayer insulating film 103.
Capacitor 110 includes a storage node 111 which is a lower electrode, a capacitor dielectric layer 112, and a cell plate 113 which is an upper electrode. Storage node 111 is formed along the sidewall and bottom of the aforementioned trench. Storage node 111 is electrically connected to pad layer 131a at its bottom to be further connected to source/drain diffusion layer 121 of MOS transistor 120 via pad layer 131a. Cell plate 113 is formed facing storage node 111 with capacitor dielectric layer 112 therebetween.
At the top most layer C, interlayer insulating films 107 and 108 are formed so as to cover BPTEOS film 105 and capacitor 110 of the above-described intermediate layer B. A metal line 133 connecting metal cells with each other is formed in interlayer insulating films 107 and 108. Metal line 133 is electrically connected to source/drain diffusion layer 121 of MOS transistor 120 through a bit line 132 passing through intermediate layer B and a bit line 131b passing through lower most layer A.
A method of forming a DRAM capacitor of the foregoing structure will be described here. MOS transistor 120, pad layer 131a, bit line 131b and the like are formed in advance at the main surface of semiconductor substrate 101 in which isolation film 102 is formed. Lower most layer A is formed by providing an interlayer insulating film 103 so as to cover the surface thereof.
In the formation of a capacitor, first a silicon nitride film 104 is formed all over the main surface of interlayer insulating film 103 corresponding to the lower most layer A. Then, BPTEOS film 105 is formed thereon. A storage node formation trench is provided in silicon nitride film 104 and BPTEOS film 105 by conventional photolithography and etching techniques. Doped polysilicon layer 111 is formed so as to cover the sidewall and bottom of this storage node formation trench. Then, the surface of doped polysilicon layer 111 is roughened. This roughening process is applied to improve the capacitance of the capacitor.
The trench is filled with a photoresist. Using this photoresist as a mask, anisotropic etching is applied all over (etchback) until the surface of at least BPTEOS film 105 is exposed. When storage node 111 is formed by this etchback process, the photoresist in the trench is removed. Then, the native oxide film is removed by buffer hydrofluoric acid (BHF) using a mixture of hydrofluoric acid and ammonium fluoride. Following this removal, capacitor dielectric layer 112 and cell plate 113 are formed. Thus, a capacitor 110 is completed.
By forming a capacitor 110 using a silicon nitride film 104 which is a stopper film and a BPTEOS film 105 which is a spacer film, a cylinder type capacitor of a large capacitance can be obtained.
However, a semiconductor device fabricated by the above-described method had the problem that the reliability is low. This issue will be described in detail hereinafter.
The aforementioned roughening process is effected by growing crystal grains of silicon on the underlying layer which is the doped polysilicon layer. Conventionally, an etching process by BHF is carried out after the roughening process for the removal of the native oxide film. This BHF includes a mixture of hydrofluoric acid and ammonium fluoride. Silicon is etched by the ammonium fluoride.
The crystal grains readily fall off from the underlying layer. There is a possibility that these crystal grains will adhere onto the top surface of the BPTEOS film. The reattaching crystal grains may cause shorting between adjacent storage nodes, resulting in degradation of the reliability of the semiconductor device.
In etching back the doped polysilicon layer formed at the top face of the BPTEOS film, anisotropic etching was conventionally employed. This anisotropic etching generates residues along the sidewall of the pattern by the anisotropy of etching. Therefore, the upper end of the storage node will have a sharp edge along the sidewall when the etchback process is completed.
If an etching process is effected by BHF to remove the native oxide film, the top surface of the BPTEOS film will be removed. The aforementioned sharp edge portion will protrude from the top surface of the BPTEOS film. This protruding edge will easily be broken to fall off by vibration and the like encountered during the post process of rinsing. There is a possibility that the broken edge will adhere to the top surface of the BPTEOS to cause shorting between storage nodes. As a result, the reliability of the semiconductor device will be degraded.
Usage of a hydrofluoric acid solution (HF+H2O) instead of BHF is possible for removing the native oxide film. However, in such a case, the P (phosphorus) included in the storage node for application of conductivity will be eluted into the hydrofluoric acid solution in the form of phosphoric acid (PO3) from the surface of the storage node. This causes degradation of the conductivity of the storage node to reduce the capacitance of the capacitor. Thus, the reliability of the semiconductor device is degraded.
The foregoing problems were encountered when a spacer film is formed of a BPTEOS film. Japanese Patent Laying-Open No. 2001-203334 discloses a spacer film of a two-layered structure. A TEOS (Tetra Ethyl Ortho Silicate) film which is an etching stopper film is formed at the surface of BPTEOS film 105 which is a spacer film, as shown in FIG. 14, and the spacer film is formed on silicon nitride film 104. In this case, BPTEOS film 105 ensures the height of the capacitor whereas TEOS film 106 mainly functions as an etching stopper.
This TEOS film 106 is substantially absent of impurities such as phosphorous and boron. Therefore, TEOS film 106 is more difficult to be etched by the hydrofluoric acid solution than BPTEOS film 105, and plays the role of an etching stopper. It is therefore possible to use a hydrofluoric acid solution for the removal of the native oxide film from the surface of the storage node. In an etching process using hydrofluoric acid, silicon is less susceptible to etching than by etching using BHF including ammonium fluoride. It is therefore possible to prevent the silicon crystal grains of the storage node from falling off the underlying layer formed of doped polysilicon. Since shorting between storage nodes can be prevented, the reliability of the semiconductor device is improved.
It is to be noted that BPTEOS film 105 is formed by atmospheric CVD (chemical vapor deposition) and the film formation peak temperature is generally 300-450xc2x0 C. The time required for growing this film is several minutes. In contrast, a TEOS film is formed by CVD under reduced pressure, and the film formation peak temperature is approximately 680xc2x0 C. The time required for film growth is approximately one hour.
The demand for high speed and large capacity in recent semiconductor devices is high. Therefore, it is therefore necessary to facilitate minimization of the device per se. Furthermore, development of a system LSI (Large Scale Integrated circuit) corresponding to a combination of a semiconductor memory and logic circuit is now in progress in response to the versatility of information processing. Particularly, the combination of a DRAM memory circuit and a logic circuit to control this memory circuit, now called eDRAM, is viable to allow high speed processing for images of a great amount.
In the fabrication of such a system LSI, processing at low temperature in the fabrication process is required for the high performance of the logic circuit, in addition to miniaturization of the device per se. In order to prevent degradation of the performance of the logic circuit in the fabrication of the eDRAM, it is desirable to carry out processing at lower temperature in the capacitor formation step.
In the case where the formation step of the aforementioned cylinder type capacitor is employed, the TEOS film that does not substantially include impurities on the BPTEOS film has to be processed at the high temperature of 680xc2x0 C. for one hour. In the case where the logic circuit is formed on the same semiconductor substrate, degradation in performance thereof is significant. This becomes a bar for the system LSI.
If attention is focused on miniaturization, the capacitor forming the memory circuit must be integrated at a higher scale. Since there is a limit in reducing the size of the capacitor while ensuring the capacitance, then the only parameter which can be varied is to narrow the distance between adjacent capacitors. In the case where capacitors are located in close proximity, the reliability of the insulating film present therebetween is critical. Particularly, in the case where polysilicon residues are present, leakage may occur at the interface of the layered films to result in shorting. Occurrence of shorting is further expected when the insulating film located between the capacitors is a film grown at low temperature.
In view of the foregoing, an object of the present invention is to provide a semiconductor device fabrication method that allows formation of a capacitor with a heat treatment at lower temperature, and a semiconductor device thereof. A particular object of the present invention is to provide a semiconductor device with a capacitor having performance degradation of a logic circuit in a system LSI prevented, and a fabrication method of such a semiconductor device.
Another object of the present invention is to provide a semiconductor device that can have shorting between adjacent capacitors integrated at high scale prevented, and a method of fabricating such a semiconductor device.
According to an aspect of the present invention, a fabrication method of a semiconductor device with a memory circuit including a capacitor and a first field effect transistor, and a logic circuit including a second field effect transistor provided on the same semiconductor substrate includes the step of growing an insulating film for capacitor formation to form a capacitor in a trench. The semiconductor device fabrication method is characterized in that the insulating film for capacitor formation is grown at a temperature equal to or below a predetermined temperature at which level performance degradation of the logic circuit is not induced.
In the step of growing an insulating film for capacitor formation carried out after first and second field effect transistors are formed in the present fabrication method, the insulating film for capacitor formation is grown at a processing temperature of a level that does not degrade the performance of the second field effect transistor forming the logic circuit. Thus, a semiconductor device of high performance and high reliability can be provided. It is confirmed that the predetermined temperature at which level performance degradation of the logic circuit is not induced is approximately 600xc2x0 C. and below from experience. If a film growth process is effected at a higher temperature, there is a possibility of the electrical property of the field effect transistor forming the logic circuit being degraded.
In the semiconductor device fabrication method of the present aspect, the step of growing an insulating film for capacitor formation preferably includes the steps of: (1) forming a silicon nitride film on an interlayer insulating film formed so as to cover the first field effect transistor, (2) forming a first silicon oxide film including impurities by atmospheric pressure CVD on the silicon nitride film, and (3) forming a second silicon oxide film by either atmospheric pressure CVD or plasma CVD on the first silicon oxide film so as to be substantially absent of impurities.
By forming a second silicon oxide film substantially absent of impurities using either atmospheric pressure CVD or plasma CVD, processing can be effected at a temperature significantly lower than in the conventional case. Therefore, performance degradation of the logic circuit can be prevented.
In the semiconductor device fabrication method of the present aspect, the film formation peak temperature by atmospheric pressure CVD in growing the first silicon oxide film is preferably at least 300xc2x0 C. and not higher than 450xc2x0 C., and the film formation peak temperature by atmospheric pressure CVD in growing the second silicon oxide film is at least 300xc2x0 C. and not higher than 450xc2x0 C.
In the semiconductor device fabrication method of the present aspect, the film formation peak temperature by atmospheric pressure CVD in growing the first silicon oxide film is preferably at least 300xc2x0 C. and not more than 450xc2x0 C., and the film formation peak temperature by plasma CVD in growing the second silicon oxide film is preferably at least 200xc2x0 C. and not more than 300xc2x0 C.
According to another aspect of the present invention, a fabrication method of a semiconductor device with a memory circuit including a capacitor and a field effect transistor includes the steps of: (1) forming a silicon nitride film on an interlayer insulating film formed so as to cover the field effect transistor, (2) forming a silicon oxide film on the silicon nitride film, (3) forming a trench in the silicon nitride film and silicon oxide film so as to arrive at the interlayer insulating film, and forming an insulating film so as to cover the sidewall of the silicon oxide film forming the trench, and (4) forming a lower electrode of the capacitor in the trench so as to be electrically connected to a conductive region of the field effect transistor and located along the insulating film.
By the fabrication method of the present aspect, insulation between adjacent capacitors is ensured by the insulating film formed so as to cover the sidewall of the trench. Therefore, degradation in the performance and reliability due to increase in integration density can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.