1. Field of the Invention
The present invention relates to receivers for detecting transmitted binary frequency shift key (FSK) data and, more particularly, to a system for automatically eliminating DC offset in the FSK receiver.
2. Statement of the Problem
Digital radio transceivers are used in a variety of communications products. In particular, pagers, portable data terminals, and digital cellular telephones use digital radio transceivers. In all digital transceivers, the data that is to be transmitted must be encoded onto a radio frequency (RF) carrier for transmission. Also, a receiver must be able to demodulate a received signal. Further the receiver must process the demodulated signal to reproduce the digital data, usually binary logic level data, that was originally transmitted.
One commonly used technique in digital radio communication is called frequency shift keying (FSK). FSK technology involves using a first frequency (f.sub.1) to represent a first binary logic state, and a second frequency (f.sub.2) to represent the second binary logic state. The frequencies f.sub.1 and f.sub.2 are separated in the frequency spectrum sufficiently to allow accurate detection by the receiver. A frequency f.sub.0 between f.sub.1 and f.sub.2 is called the center frequency.
In digital radio receivers of this type, the receiver includes circuitry for demodulating the FSK signal. The demodulating circuit, called a discriminator, provides an analog output representing the FSK signal. An offset voltage is superimposed on or added to the demodulated analog signal. Ideally, this offset voltage has a fixed value and is known. If such an ideal signal existed, conversion of the demodulated analog signal to a binary logic level signal would be a simple matter of comparing the demodulated signal to the known offset voltage using a digital comparator.
In reality, however, the demodulated analog signal is offset by a variable amount caused by frequency mismatch between the transmitter and the receiver, as well as irregularities caused by temperature changes and variabilities in device performance. Hence, the offset voltage is not a fixed voltage, but instead continuously varies during operation.
Once the FSK signal is demodulated from the carrier by the receiver, the demodulated signal is compared to a threshold voltage or bias voltage. The bias voltage should be as close as possible to the offset voltage superimposed on the demodulated analog signal. Quite simply, if the demodulated signal is greater than the threshold voltage, the circuit interprets it as a logic HIGH, and if the demodulated signal is below the threshold voltage the circuit interprets it as a logic LOW. A difference between the offset voltage and the bias voltage causes some portions of the demodulated FSK signal to be too close to the bias voltage while causing other portions to be too far from the bias voltage to allow accurate conversion to a binary logic level signal. It is important that the receiver has some way of changing the threshold or bias voltage automatically to compensate for changes in the offset voltage and ensure accurate data decoding in adverse environments.
Several prior art offset compensation circuits are known. One technique attempts to correct offset voltage disturbances by adjusting the receiver local oscillator frequency until the received frequency and the local oscillator are in lock. The resulting circuity for this technique is quite complex and may be undesirable in a portable unit with limited space and power source capabilities. Also, this method can only compensate for offset voltage variations caused by frequency mismatch, and cannot compensate for variations caused by the receiver components themselves.
U.S. Pat. No. 4,575,863 issued to Butcher et al. on Mar. 11, 1986 describes a method which activates a bias circuit in the receiver during a portion of the received data that is regular and predictable (i.e. a long series of "1010" data). During the selected time period, a capacitor is allowed to charge to an average level of the demodulated data signal. Later, when the incoming data is not predictable or regular, as would be the case in normal data transmission, the capacitor voltage is used as a bias voltage. This method works well when the incoming signal is truly uniform and regular during the selected time period. However, distortions in the incoming signal, or distortions created by the receiver circuit itself, will lead to an erroneous determination of the correct offset voltage.
U.S. Pat. No. 4,929,851 issued to G. Pace on May 29, 1990 describes a method using a feedback system which adjusts the threshold for the voltage comparison by continuously integrating the demodulated signal and using the integrated signal as a threshold voltage. Again, this method works well when the FSK data is a uniform pattern of logic 1's and logic 0's so long as there is no miscellaneous distortion in the receiver or transmitter that would cause the center of the data to not be halfway between the minimum and maximum data states. Also, because this method determines the offset voltage by sampling the demodulated signal, it cannot account for any distortion or offset caused by the comparator.
Another type of offset correction circuit is shown in U.S. Pat. No. 5,052,021 issued to Goto et al. on Sep. 24, 1991 and in U.S. Pat. No. 5,027,352 issued to Goode on Jun. 25, 1991. In this technique the demodulated data signal is analyzed to find peak voltage and valley voltage levels. The peak and valley voltages are averaged together to find a center voltage which is used as the bias voltage. Once again, this method is sensitive to any type of distortion that would make the true logic center be different from the mathematical center of the peak and valley voltages. Also, this technique requires circuitry to sample and hold peak values, including circuitry to differentiate the demodulated data signal. The circuitry adds expense and complicates receiver design.
U.S. Pat. No. 5,175,749 issued to Ficht et al. on Dec. 29, 1992, involves injecting a locally generated signal at the center frequency into the radio receiver during idle periods. The analog output is then sampled during the idle period and stored and used during the active period as the bias voltage. This method offers the advantage of sampling the actual output so that offset or distortion caused by any of the components in the receiver circuit is accounted for. However, because the center frequency is locally created and injected into the receiver, distortion caused by front end components of the receiver or between frequency mismatch between the transmitter oscillator and the receiver oscillator is not accounted for.
A need exists, especially in communication environments, for a method and apparatus for automatically determining an offset voltage in an FSK receiver with a high degree of accuracy. Also, an apparatus and method are needed for determining offset voltage and correcting for that offset voltage with a minimum of circuitry. Further, a method for offset determination and compensation is needed which accounts for all sources of offset voltage variation and distortion in the receiver and transmitter circuits.
3. Solution to the Problem
The present invention provides a solution to the above problem by a system using a transmitter to broadcast an FSK signal, where the transmitter also periodically transmits a central frequency (f.sub.0) during a predetermined portion of the FSK signal. A receiver captures the transmitted FSK signal, and demodulates the FSK signal to provide an analog signal. The analog signal is DC coupled to one input of a comparator. The comparator generates a logic level binary output corresponding to the FSK signal. The other input of the comparator is coupled to a bias voltage. Preferably the bias voltage is provided by a digital to analog convertor (DAC).
A control circuit detects the predetermined portion of the FSK signal in which the center frequency is being transmitted. During the predetermined portion the control circuit samples the binary logic level output of the comparator, converts the binary logic level output to a digital error word, and uses the digital error word to control the DAC. Hence, the bias voltage is determined from the last stage comparator output and thus accounts for all sources of offset error in a circuit. This solves the above problem by determining an offset voltage in an FSK receiver with a high degree of accuracy. Also, by implementing the control circuitry in an on-board microprocessor, very little dedicated circuitry is needed to implement the method of the present invention.