1. Field of the Invention
The present invention relates to a CMOS integrated circuit.
2. Description of the Related Art
The related art which is known as the technique to save electrical power of an information processor relates to
1Ratio-less in CMOS design;
2Sleep/Standby condition and stop of clock in this condition.
The item 1 means that CMOS gate consumes only a sub-threshold leak current when an input is high level or low level. The term xe2x80x9cleak currentxe2x80x9d used in this specification means sub-threshold leak current, namely a steady leak current in such a condition that the input of CMOS gate is defined as high level or low level. Therefore, the charge and discharge current and switching transient current of CMOS circuit can be saved but the leak current cannot be saved in the sleep/standby condition by executing the items 1and 2.
The cited reference, Proceeding STARC Symposium, Sept. 1998, (Held in Tokyo), pp.100-109, discloses a leak current.
A leak current is determined by the threshold value voltage of MOS transistor. Here, there is a relationship that the smaller the threshold value voltage is, the larger the leak current becomes. According to this cited reference p.103, when a circuit is composed of a million transistors and is operated under the temperature of 125xc2x0 C., a leak current becomes 5 mA for the threshold value voltage of 0.3V, meanwhile a leak current becomes 1A for the threshold value voltage of 0.1V as illustrated in the figure. On the other hand, it is also known that when power source voltage is defined as Vcc and threshold value voltage as Vt, a drive current of MOS transistor is proportional to the square of (Vccxe2x88x92Vt). Therefore, if it is requested to raise the operation rate, the threshold value voltage must be set to a lower value and thereby a leak current increases.
The technique to save the leak current is described in the Technical Report of IEICE (the institute of electronics, information and communication engineers), June 1995, ICD95-41, pp.1-8. In this technique, a MOS transistor of higher threshold value is provided as a power switch in addition to an ordinary logical circuit to reduce a leak current during non-operating condition. Moreover, the Proceeding STARC symposium also describes that a MOS transistor of higher threshold value is used for switching of the circuit during the standby mode.
Moreover, IEEE Journal of Solid-State Circuits, Vol. 31, No.11 (Nov. 1996) pp1770-1779 describes that a leak current during the non-operating condition is lowered by controlling a substrate bias of MOS transistor during the standby mode to raise the threshold value voltage.
Moreover, the Japanese Unexamined Patent Publication No. HEI 8-274620 discloses an LSI covering the operation mode in which the threshold value voltage of MOS transistor is raised by controlling a substrate potential in order to save the power consumption through reduction of a leak current of CMOS.
However, these references do not describe how the leak current control is started and ended or describes that such start and end of control is performed by interruption control or mode control which is not related to the operation (instruction) to be executed by the circuit. Namely, a control system for controlling power consumption of the circuit has been provided in addition to the control system for controlling the execution (arithmetic operation).
Meanwhile, another technique for realizing low power consumption of processor is disclosed in the Japanese Unexamined Patent Publication No. HEI 10-20959. In this cited reference, a power control field is provided within the instruction code and thereby the microprocessor operates only the necessary function blocks by decoding the power control field. However, it is also described that a method for controlling the feeding of power supply and a method for controlling the feeding of clock signal are proposed as the method of controlling the electrical power.
However, the practical circuit for controlling the feeding of power supply is never disclosed and moreover, a steady leak current which flows even when the input of the CMOS gate is defined as the high level or low level is never described.
The technique for saving leak current during execution has never been known in the CMOS logical circuit, particularly in the processor in which the leak current is never neglected. Various references listed above for saving the leak current are related only to the particular condition in which the processor as a whole is not-operated and to the standby mode and do not yet describe the process to automatically reduce the leak current in relation to the arithmetic execution of processor.
The problem to be solved by the present invention relates to reduction of leak current during execution of processor.
Particularly when the threshold value of CMOS is low in order to raise the operation rate, reduction of leak current has an important meaning for reduction of power consumption because when the circuit is composed of a million transistors and is operated under the temperature of 125xc2x0 C., if the threshold value is 0.1V, a leak current becomes a value as large as 1A as described in the proceeding of STARC Symposium. Nowadays, it is well known that a highly precision LSI has the integration density of a million transistors or more.
In the processor having a plurality of circuit blocks in which at least one circuit block is used by the instruction signal included in the instruction set, it is decided whether the instruction signal is decoded and a circuit block is used by such instruction signal or not, the circuit block used allows a large leak current (a current flowing to the source and drain path connected in direct of CMOS when the gate to source voltage of PMOS or NMOS forming CMOS is 0V) to flow and the leak current is controlled to become low level for the circuit blocks not used.
Particularly, in the processor to execute the pipeline control, a control signal for controlling leak current is transferred in synchronization with the pipeline stage. Therefore, a high level leak current is allowed to flow into the circuit block in the pipeline stage for the arithmetic execution and the leak current is then controlled to a low level upon completion of the pipeline stage.
In addition, in this case, the leak current control is performed prior to the arithmetic execution of circuit block considering that the transitional condition for the leak current control does not give any influence on the arithmetic execution.
An example of circuit block is an ALU (Arithmetic Logical Unit) and when an instruction to use ALU is executed, the execution mode in which the leak current of ALU is high level is designated. On the occasion of executing the instruction for not using ALU, the execution mode in which the leak current of ALU is low level is designated. It is enough for the judging circuit to issue a designating signal regarding the level of leak current of ALU on the basis of the information that an instruction designates use of ALU or not and therefor it is concluded to decoding of instruction.
Another example of the circuit block is FPU (Floating Point Arithmetic Unit) and this circuit block is used to execute the FPU instruction by the instruction signal. Another example is a data memory which is used only when the instruction signal includes the loading execution (read from data memory) or store execution (write to data memory).
As explained above, the operation mode in which a leak current is high is applied when the circuit block requests operation and the operation mode in which a leak current is low is applied when the circuit block does not request operation. Thereby, the leak current generated in useless can be saved.