In order to realize high-density installation of semiconductor chips which is a key technology for making an electronic device smaller, lighter, and thinner, various packaging techniques of a semiconductor device have been developed.
As a technique concerning a packaging structure of a semiconductor device which reduces an area required in installing the semiconductor device onto a mother board, there have been developed: a pin-insert package such as DIP (Dual Inline Package); a surface installation package, such as SOP (Small Outline Package), performed by leading a periphery; a package such as BGA (Ball Grid Array) in which external output terminals are disposed on an under surface of the package in a lattice manner. Further, as a technique for realizing high-density installation by reducing an area ratio of a package with respect to semiconductor chips, various efforts have been made so as to narrow a pitch of the external output terminals and reduce a package size by making substrate wirings finer.
Further, as a multi-chip package in which a plurality of semiconductor chips are gathered so as to be installed into a single package, there has been developed a technique such as a chip-stacked package in which a plurality of semiconductor chips are stacked so as to realize higher-density installation. Further, as the multi-chip package, there has been developed a system-in package in which a plurality of semiconductor chips respectively having functions different from each other are sealed and systemized in a single package.
While, as a method for making an electronic device smaller, lighter, and thinner, a method different from high-density packaging and installation of the semiconductor chips attracts attention. This method uses such a system-on chip that: circuits such as a memory circuit, a logic circuit, and an analog circuit that have been conventionally provided separately from each other are provided in combination and are integrated in a single chip so as to function as a single system.
However, when circuits such as the memory circuit and the logic circuit are integrated in a single chip, this raises such problems that: it is difficult to reduce a voltage of the memory circuit, and it is necessary to perform an additional process for reducing noises occurring in the logic circuit. Further, when an analog circuit which has been conventionally constituted of a bipolar member is provided in combination with other circuits, it is difficult to manufacture the analog circuit by using the same CMOS as the memory circuit and the logic circuit.
Then, more attention is paid not to the system-on chip but to the system-in package, having the same function as the system-on chip, which can be developed in a shorter period and at lower cost.
As a conventional system-in-package semiconductor device, FIG. 9(a) and FIG. 9(b) show examples of a structure of a chip-stacked semiconductor device in which a plurality of semiconductor chips are stacked and wire-bonded. FIG. 9(a) is a plan view obtained by viewing the semiconductor device from above in a stacking direction, and FIG. 9(b) is a cross sectional view taken along E–E′ of FIG. 9(a). As shown in FIG. 9(b), the semiconductor device is arranged so that: a substrate 4 constituted of a polyimide substrate or a print substrate is used as a stacking base, and a semiconductor chip 2 and a smaller semiconductor chip 1 are stacked on and above the substrate 4 in this order. By using die-bonding layers 9, the substrate 4 and the semiconductor chip 2 are bonded to each other, and the semiconductor chip 1 and the semiconductor chip 2 are bonded to each other.
The semiconductor chips 1 and 2 respectively have wire-bondable bonding pads 15 . . . and 25 . . . each of which allows conduction with external parts. The bonding pads 15 . . . and 25 . . . are respectively connected to bonding terminals 6 . . . provided on the substrate 4. As shown in FIG. 19(b), in connecting these members, a wire bonding process using a metal wire such as wires 8 . . . is widely used. The wire bonding process is used also in a case where the stacking base is a lead frame.
Note that, there is also a case where the bonding pads of the stacked semiconductor chip are connected not to the bonding terminals provided on the substrate but to bonding pads of another stacked semiconductor chip.
As described above, in the case where the semiconductor chips are stacked and the chip and the substrate are electrically connected to each other by wire bonding, the chips are stacked so that sizes of the chips become smaller upward. This arrangement is made so that the stacked semiconductor chip does not cover the bonding pads of the lower semiconductor chip. The bonding terminals on the substrate are disposed outside the lowermost semiconductor chip. Thus, when the uppermost semiconductor chip and the lowermost semiconductor chip are different from each other in terms of the chip size, a distance between the bonding pad of the uppermost semiconductor chip and the bonding terminal on the substrate is long, so that also a length of the wire is long.
In the system-package semiconductor device arranged in the foregoing manner, when a logic/analog LSI is stacked on a memory LSI and they are wire-bonded to each other, there is the following problem.
It is often that the logic/analog LSI is much smaller than the memory LSI in terms of the chip size. Thus, in the semiconductor device arranged so that the logic/analog LSI which is different from the memory LSI in terms of the chip size is stacked on the memory LSI and they are wire-bonded to each other, the wire is made longer, so that the wire becomes brittle and the wire tends to drop off when the semiconductor chips are sealed. Further, there is such a problem that: the wire hangs down due to its weight, so that the wire touches another wire and the wire touches an edge of the lower semiconductor chip. In order to solve the problem, the following methods were proposed.
For example, Japanese Unexamined Patent Publication No. 257307/2001 (Tokukai 2001-257307)(Publication date: Sep. 21, 2001) discloses such an arrangement that: a semiconductor chip is stacked on another semiconductor chip having a rewiring layer which has been formed on its circuit surface in advance, and the rewiring layer relays a wire-bonding wire which extends from the upper semiconductor chip. Such arrangement makes the wire length for a single loop longer.
Further, Japanese Unexamined Patent Publication No. 76250/2002 (Tokukai 2002-76250)(Publication date: Mar. 15, 2002) discloses such an arrangement that: there is provided a polyimide tape on which a wiring layer for relaying a wire-bonding wire is disposed between the upper semiconductor chip and the lower semiconductor chip. Such arrangement makes the wire length for a single loop longer.
However, in the conventional semiconductor device having the rewiring layer on its circuit surface as described above, it is necessary to perform a step of additionally forming the rewiring layer for relaying the wire-bonding wire on the semiconductor chip that has been completely formed. Thus, this raises such a problem that: an electric property of a semiconductor element in the semiconductor chip having the rewiring layer deteriorates due to damages brought about by sputtering an aluminium film and performing a photolithography process such as exposure and etching process that are performed during the step of forming the rewiring layer.
Further, in forming wirings of the rewiring layer, when an etching resist is formed or removed during a step of additionally forming an insulating layer on the bonding pad of the semiconductor chip that has been completely formed, an impure material remains on a surface of the bonding pad. Then, this raises such a problem that the impure material deteriorates the bonding strength of the wire bonding.
Further, in wire bonding, when stress is exerted on the bonding pad of the rewiring layer formed on the semiconductor chip having the rewiring layer, the semiconductor element formed under the bonding pad of the rewiring layer may be damaged by the stress.
Further, in the semiconductor device having the wiring layer obtained by forming wirings on a polyimide tape, there is such a problem that: it is more difficult to form fine wirings than the technique of forming the rewiring layer on the semiconductor chip as described above. This is based on the following reason: since these techniques are different from each other in terms of a material and a photoresist device, in case of forming the rewiring layer on the semiconductor chip, a minimum wiring pitch can be set to not more than 1 μm, but in case of forming wirings on the polyimide tape, a minimum wiring pitch can be set to 50 to 60 μm at most in accordance with a current technique.
Further, polyimide which is a material for the wiring layer can more easily absorb water than other materials. Thus, this may bring about so-called reflow crack. The reflow crack is such that: when the semiconductor package is installed onto the substrate in accordance with thermal reflow, absorbed water swells, so that the wiring layer and the semiconductor chip formed thereon respectively exfoliate. Thus, this raises such a problem that the quality of the semiconductor device deteriorates.