(a) Field of the invention
The present invention relates generally to the field of fabrication of integrated circuits, and more particularly to the process of forming borderless metal to contact structure.
(b) Description of the Prior Art
In recent years, the sizes of the integrated circuits have become continuously smaller so that the packing densities of these IC devices have increased considerably. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 16M bit or even 64M bit DRAMs. In the conventional circuit design rule (see, for example, Niel Weste in "Principles of CMOS VLSI Design", p. 105, 1985), there must be a spacing for metal line 10 over contact 8 extension a each side to ensure lithography misalignment would not cause contact problem as shown in FIG. 1. Please referring now to FIG. 2, it shows a metal to contact structure according to the prior art FIG. 1. The metal 1 layer 4 is sputtered on a silicon substrate 2, and then an dielectric layer 6 covers the metal 1 layer 4. A contact 8 which is formed by the conventional lithography and plasma etching techniques is the place for metal 1 layer 4 and metal 2 layer 10 to be electrically contacted. As shown in FIG. 1, the pitch between two metal 2 lines must increase by 2a in order to satisfy the old design rule. Therefore, the packing density of the IC device becomes much smaller.
In today's sub-microm or even deep sub-microm VLSI technology, how to reduce the pitch between metal lines becomes a top priority.