The embodiments of the invention described below are related to a practical implementation of a data driven processor, i.e. one that gives good performance over a wider range of applications but at a relatively low cost.
The data driven architecture for a processor was developed to provide a better solution than the von Neumann architecture, to address the particular problem of processing a large amount of data using relatively few instructions. The von Neumann type processor is controlled by a clocked addressing scheme that can pull instructions and data from almost anywhere in memory. With little restriction on the type of instructions or the locations in memory that can be accessed, the von Neumann processor has the flexibility to run a wide range of different programs. In contrast, a data driven processor (“DDP”) is designed to be fed blocks of data that are typically consecutively stored in memory (or arrive as a stream) and are to be processed according to a program that has only a small number of instructions that operate on the data. These types of programs can be found in applications such as digital encoding and filtering of documents (used in reprographics copiers, for example) and of audio and video data. Examples of audio and video data applications include compression and decompression in portable, consumer information products such as digital cameras, mobile general purpose computers, and small media devices such as MP3 players. The DDP may be particularly suited for such battery-powered products due to its inherent power efficiency, as its power consumption quickly drops to essentially zero when there is no more input data for it to consume.
In most consumer products that have a DDP, a built-in host controller (“HC”) assists the DDP by orchestrating the feeding of instructions and incoming data to the individual processing elements of the DDP. For example, a primary, general purpose processor or embedded processor of a consumer product can be programmed to act as the HC. The HC instructs each of the processing elements of a DDP as to the task to be performed. The HC also controls the formation of data paths between the DDP and external memory, to receive the outgoing data, i.e., the results of consumption by the processing elements. The DDP can be equipped with a direct memory access (“DMA”) unit that delivers a stream of outgoing data, that originates from the individual processing elements of the DDP, to sequentially addressed memory locations that have been identified by the HC. A processing element of a typical DDP is not aware of the source of the incoming data; nor does it know where its result data is ultimately destined. That information is only known to the HC.