My question is how we can write effective address in 16, 32 or 64 bit modes. We know that the following is a valid effective address in 16 bit IA-32 protected:
[BX+SI]+disp8
Can we specify: [BH+SI]+disp8 as an address?

Also suppose we write a code for IA-32 protected, the following is a valid effective address:
[EAX]+disp32

But is , [AX]+disp32 a valid valid effective address? how about [AL]+disp32?

In real mode(16-bit) we have [BX]+disp8 but is "[BL]+disp8" valid?

And my last question is that how you write a valid address in 64 bit mode?

it seems that effective address is considered by some specific registers in different code segments. Like in 32 bits, [EAX] is valid and instruction format is decoded by using EAX and no format exists for AX.

in 64 , default is 32 and we can use EAX, EBX,... but with REX.w=1, we can use [RAX], i mean CPU considers RAX when decoding the instruction.