Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data are written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. The possible bit values that can be stored in an analog memory cell are also referred to as the memory states of the cell.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory, cell, i.e., each memory cell can be programmed to assume one of two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, can be programmed to assume more than two possible memory states and thus store two or more bits per memory cell. Various methods are known in the art for reading out the multi-bit data that are stored in such cells.
For example, U.S. Pat. No. 6,317,364, whose disclosure is incorporated herein by reference, describes a multi-state memory, which is said to use a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. In one embodiment, cells of the memory are read using a control gate in a binary search. The readout uses a sensing circuit consisting of a sense amplifier comparator, with one input lead that receives an input signal from the memory cell and another that receives a reference signal. The output of the comparator is used to update a Control Gate Register Element. The value stored in this element is used to provide the next control gate read voltage.
Takeuchi et al. suggest another cell readout technique in “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits 33:8 (1998), pages 1228-1238, which is incorporated herein by reference. The authors describe a cell that contains two “pages,” meaning that the two bits in the cell are programmed in different operations. The cell is read using a four-level column latch circuit, which is shared by two bit lines. The read operation is composed of three phases, during which the word line control gate voltage is set to three different bias values. As a result of this operation, the first and second, page data in the cell are read out on the cell bit line and latched in first and second latches, respectively, of the latch circuit.