Recent years, led by the consumer markets including smart phones, smart TVs and tablets, flash memories have been developing rapidly. Nevertheless, due to complex mask patterns, exorbitant manufacturing costs, increasingly large word line leakage and crosstalk between cells, and increasingly small number of electrons in floating gates, the size reduction capacity of the flash memories is greatly limited. It is estimated that the development of the size reduction capacity will be difficult to continue when the size reduces to 1z nm. Thus, emerging non-volatile memories such as CBRAM, MRAM, PRAM and RRAM gain increasing attention, wherein resistive random access memory RRAM, by virtue of high speed, large capacity, low power consumption, low cost and high reliability, is regarded as the most powerful candidate for flash memories.
Nevertheless, due to the effect of process, voltage and temperature (PVT), as shown in FIG. 1, there is a serious consistency problem with the resistance of the RRAM resistive units; that is, there are deviations in the resistance between wafers, between chips on the same wafer, and between different regions on the same chip. In addition, the resistance in both a high resistance state and a low resistance state presents normal distribution in a certain range. Therefore, it is difficult to provide a current-mode read circuit with a relatively ideal reference current.
In addition, it is not feasible to use a fixed reference current for it cannot track the deviations brought about by regions and temperatures in the high resistance state and low resistance state of the resistive units.
At present, it is common to use a shared reference cell to provide a reference current, as shown in FIG. 2. This allows tracking of the change of the resistance as the region and temperature change. Nevertheless, there is also a consistency problem with the resistance of the reference unit per se, and the reference currents generated by the reference unit also present normal distribution.
Therefore, it is necessary to find a suitable reference array structure to narrow the reference current distribution and improve the read margin, thereby increasing the read speed and read success rate.