Due to the large number of components in state of the art electronic circuits, most of their design and production is computer implemented. A representation of a circuit in a computer often includes a netlist and a set of timing constraints. Timing constraints might include specifications of clock signals, delay requirements at inputs and outputs in the circuit, and various exceptions, for example, specifications of false paths, multi-cycle paths, minimum or maximum delays and the like. Timing constraints can be automatically generated by tools or manually added/modified. Timing constraints for circuits can be specified using a text file representation, for example, using a SYNOPSYS DESIGN CONSTRAINTS (SDC) file.
One possible process in EDA compares timing constraints for different circuits (e.g., different versions of the same circuit). For example, during the circuit design process, a later description of a circuit may be obtained by performing transformations on an earlier description of the circuit. It may be desirable to compare the timing constraints of the two circuits, for example to ensure that the timing constraints are equivalent and no changes were introduced as a result of the transformation. Timing constraints may also be compared for allegedly equivalent circuits produced by different sources.
Conventional techniques for comparing timing constraints have some drawbacks. One approach is to structurally compare timing constraints of two circuits by doing iterative pairwise comparison of individual constraints. This approach can produce false positive results (incorrect reporting of mismatches as matches) because some circuit changes may alter the way in which the constraints are applied, resulting in different timing behaviors despite two circuits having the identical set of timing constraints. In addition, such approaches can produce false negative results (incorrect reporting of matches as mismatches) because two timing constraints, even though they do not match structurally, can produce the same timing behavior on the circuit. Thus, there is a need for improved approaches to comparing timing constraints for different circuit descriptions.