(1) Field of the Invention
The present invention generally relates to a synchronous communication system, such as a video transmission system. More specifically, the present invention is concerned with a device which transmits clock information about a clock signal used for sampling a video signal on the transmitter side, and a device which derives the clock signal from the clock information received via a transmission path in order to reproduce the video signal on the receiver side.
(2) Description of the Prior Art
In a synchronous communication system, it is necessary to transmit a clock signal used on the transmitter side to the receiver side in order to reproduce a video signal transmitted from the transmitter side. Conventionally, a synchronous method based on a stuffing technique is used for transmitting, to the receiver side, the clock signal used on the transmitter side. Another method is known, in which clock information is inserted into data transmitted to the receiver side. The present invention is concerned with the latter type.
FIG. 1A is a block diagram of a conventional clock information transmitting device. A horizontal synchronizing signal H is separated, by a synchronizing signal separator, from an input video signal which is generated by a video signal processing circuit (not shown) and is to be transmitted to the receiver side. The separated horizontal synchronizing signal H is input to a PLL (Phase-Locked Loop) circuit 5. As shown in FIG. 1A, the PLL circuit 5 is composed of a phase comparator (PC) 1, a lowpass filter (LPF) 2, a voltage-controlled oscillator (VCO) 3, and a frequency divider 4. The phase comparator 1 has a first input terminal receiving the horizontal synchronizing signal H, and an output signal of the frequency divider 4. The output signal of the frequency divider 4 has a frequency equal to [1/(455.times.2)] times that of an output signal (sampling clock signal) of the voltage-controlled oscillator 3. The frequency of the sampling clock signal of the voltage-controlled oscillator 3 is four times the frequency f.sub.SC (=3.58 MHz) of a color sub-carrier signal (4f.sub.SC =4.times.3.58 MHz) according to the NTSC standard. Thus, the output signal from the frequency divider 4 has a frequency equal to that of the horizontal synchronizing signal H (15.75 kHz).
The phase comparator 1 obtains the phase difference between the horizontal synchronizing signal H and the output signal of the frequency divider 4, and outputs a voltage signal corresponding to this phase difference to the voltage-controlled oscillator 3 via the lowpass filter 2. The oscillation frequency of the voltage-controlled oscillator 3 is based on the voltage signal from the lowpass filter 2. The sampling clock signal generated by the voltage-controlled oscillator 3 is output not only to the frequency divider 4 but also to one of two input terminals of a counter 8. The other input terminal of the counter 8 receives an output signal of a frequency divider 7, which frequency-divides a transmission clock signal f.sub.L generated by a clock generator 6. The transmission clock signal generated by the clock generator 6 has a frequency f.sub.L equal to 32.064 MHz.
The counter 8 counts the number of pulses contained in the sampling clock signal (4f.sub.SC) which are obtained during an interval between two consecutive pulses of the clock signal from the frequency divider 7. In FIG. 1A, the number of pulses obtained during the period is labeled as .DELTA.S.sub.S. The counter value .DELTA.S.sub.S in the counter 8 is output to a multiplexer (MUX) 9, which also receives a coded video signal via a digital processing circuit (not shown for the sake of simplicity). The multiplexer 9 inputs the counter value .DELTA.S.sub.S into control (auxiliary) bits in a frame format of a multiplexed signal, which is output to a transmission path in synchronism with the transmission clock signal.
FIG. 1B is a block diagram of a clock information receiving device, which is composed of a demultiplexer (DMUX) 21, a PLL circuit 28 and a frequency divider 29. The multiplexed signal is received by the demultiplexer 21, which separates the control bits from the multiplexed signal. The counter value .DELTA.S.sub.S indicated by the control bits is output to the PLL circuit 28. The coded video signal from the demultiplexer 21 is output to a digital processing circuit (not shown for the sake of simplicity). The transmission clock signal f.sub.L from the demultiplexer 21 is input to the frequency divider 29, which frequency-divides the transmission clock signal f.sub.L. A clock signal output by the frequency divider 29 has a frequency equal to that of the clock signal output by the frequency divider 7 shown in FIG. 1A.
The PLL circuit 28 is composed of a phase comparator (PC) 22, an adder 23, a flip-flop (FF) 24, a digital-to-analog (D/A) converter 25, a voltage-controlled oscillator (VCO) 26, and a counter 27. The counter value .DELTA.S.sub.S from the demultiplexer 21 is input to the phase comparator 22, which compares the counter value .DELTA.S.sub.S with a counter value .DELTA.S.sub.R in the counter 27, which counts the number of pulses contained in the output signal of the voltage-controlled oscillator 26 during an interval between two consecutive pulses of the clock signal from the frequency divider 29. The phase comparator 22 obtains the phase difference between the counter value .DELTA.S.sub.S and the counter value .DELTA.S.sub.R, and outputs a voltage signal corresponding to the phase difference to an integration circuit composed of the adder 23 and the flip-flop 24. When the voltage signal output by the phase comparator 22 is 0 V, the flip-flop 24 generates 0 V. When the voltage signal output by the phase comparator 22 is a level other than 0 V, the flip-flop 24 generates an integrated value in digital form. The output signal of the flip-flop 24 is converted into an analog signal by the D/A converter 25. The output signal of the D/A converter 25 adjusts the frequency of the oscillation signal generated by the voltage-controlled oscillator 26.
In the above-mentioned manner, the sampling clock signal is adjusted on the receiver side so that the counter value .DELTA.S.sub.R obtained on the receiver side always becomes equal to the counter value .DELTA.S.sub.S on the transmitter side. Hence, the sampling clock signal obtained on the receiver side always has the same frequency as that obtained on the transmitter side.
The conventional transmission system, however, has a disadvantage in that the PLL circuit 28 on the receiver side needs the D/A converter 25, hence making it very difficult to produce a compact clock information receiving device.