1. Field of the Invention
The present invention relates to electronic circuits, and, in particular, to signal generators, such as phase-locked loops.
2. Description of the Related Art
In many electronics applications, digital circuits are employed that operate with one or more clock signals. Personal computers commonly employ a processor that may operate based on a clock having a frequency of 350 MHz, and 1 GHz frequencies are becoming common. However, at such high frequencies, these digital circuits may radiate signals as electromagnetic energy, and these electromagnetic emissions may interfere with the operation of surrounding equipment. Since these emissions are based upon clock signals, high emitted energy “spikes” occur at these clock signal frequencies and their harmonics. Consequently, equipment is often shielded to prevent or minimize these emissions within certain frequency ranges, or operation is modified to spread the emitted energy over a wider frequency range, thereby decreasing the energy at any given frequency. One technique for modifying the operation of a digital circuit is to vary the clock frequency over a range of frequencies such that the average frequency is the desired clock frequency, but the emitted energy is now “spread” over the range of frequencies. Such variation of the clock is termed “spread spectrum” and reduces the interference from high-energy spikes at the clock frequency.
A synthesizer generating one or more clock signals often employs a phase-locked loop (PLL). A PLL is a circuit that generates a periodic output signal that has a constant phase and frequency with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference. In many applications, the frequency of the output signal is higher than the frequency of the input signal.
FIG. 1 shows a block diagram of a conventional fractional-N charge-pump phase-locked loop (PLL) 100. PLL 100 has a main signal path consisting of phase detector (PD) 102, charge pump 104, loop filter 106, and voltage-controlled oscillator (VCO) 108 and a feedback signal path consisting of feedback divider 110 controlled by accumulator 112. PD 102 compares the phase of an input reference clock signal 101 having frequency fref to the phase of a feedback signal 103 having frequency fdiv. Based on the comparison, PD 102 generates an error signal: either an UP signal (when the phase of reference signal 101 leads the phase of feedback signal 103) or a DOWN signal (when the phase of reference signal 101 lags the phase of feedback signal 103), where the magnitude of the error signal indicates the magnitude of the phase difference between the two signals. Charge pump 104 generates an amount of positive or negative charge Q based on the error signal from PD 102 and applies that charge to loop filter 106, which operates as an integrator that accumulates the net charge from the charge pump. The resulting loop-filter voltage VLF is applied to VCO 108, which generates a periodic VCO output signal 105, whose frequency fvco is a function of the applied loop-filter voltage, where the VCO output signal is the synthesized output signal of PLL 100.
VCO output signal 105 is also applied to feedback divider 110, which generates feedback signal 103 by dividing the VCO output signal by either integer value N or integer value N+1, depending on whether the value of carry-out control signal Cout from accumulator 112 is a 0 or a 1, respectively. Accumulator 112 receives fractional control input values K and F, which are used to generate the divider control signal Cout. In particular, at each clock cycle of reference signal 101, accumulator 112 increments a counter by K/F, where K and F are both integers and K<F. Whenever the accumulator counter rolls over to the next integer, accumulator 112 sets carry-out signal Cout to 1 for the next clock cycle. As such, the frequency fvco of VCO output signal 105 is related to the frequency fref of reference signal 101 according to Equation (1) as follows:fvco=fref*(N+K/F),  (1)where the value K/F determines the fractional value of the reference signal fref. Any fractional value can be achieved by selecting appropriate values for K and F.
One drawback to this technique is that feedback divider 110 will jump from N to N+1 whenever accumulator 112 generates consecutive carry-out values Cout of 0 and 1, respectively. Similarly, feedback divider 110 will jump from N+1 to N whenever accumulator 112 generates consecutive carry-out values of 1 and 0, respectively. In both cases, a relatively large spur is created at (K/F)*fref.
Another drawback to this technique is that the fractional spur is worse for small or large values of K/F (i.e., close to 0 or close to 1, respectively) than for intermediate values (i.e., close to ½). In these cases, loop filter 106 having a fixed loop bandwidth is less effective at filtering out the periodic phase hit, resulting in larger fractional spurs.
Another technique for achieving a PLL with fractional resolution is to use a VCO that generates F output signals having the same frequency but different phases, where the phase offset between each different consecutive pair of output signals is the same. A PLL having a fractional resolution of 1/F can be achieved by sequentially selecting from among the F different VCO output signals. One drawback to this technique is that the fractional resolution of the PLL is limited based on the number of output signals generated by the VCO.