Phase-locked loops find many applications. Among them is their use for recovering a clock signal out of a data signal stream. FIG. 1 shows a phase-locked loop (PLL) 110. In PLL 110, data 114 is coupled to a pulse gate circuit 120 also known as a pulse removing circuit. The pulse gate circuit 120 is coupled to a phase-frequency detector 118. The phase-frequency detector 118 is coupled to a charge pump 122, which in turn is coupled to a loop filter 126. The loop filter is coupled to a voltage controlled oscillator (VCO) 130. A feedback link 146 connects the output of the VCO 130 to the phase-frequency detector 118, as shown in FIG. 1. The VCO 130 has an output 134 for coupling a recovered clock signal 136 to a memory 138. The data 114 also is coupled directly to the memory 138 via data link 142. The recovered clock signal 136 clocks data 114 into memory 138.
A typical application of the PLL 110 is in a hard disk drive system. In the standard hard disk drive system, data needs to be sent from a disk drive 150 to memory 138 of, for example, a microprocessor. An example of data sent from disk drive 150 is servo data. Servo data contains positioning information of a head of a disk drive 150 with respect to the disk of the disk drive 150.
Clock signal information associated with data 114 is embedded in the data signal 114. In fact, such clock information may be available from voltage transitions of the data signal 114. Transmitting clock information along with the data 114 on data signal link 154 obviates the need for an extra link for the clock signal. Sometimes, an extra link is not even available, as in the case of a serial link, such as an RS-232 (Recommended Standard-232) link. Whether data is sent over serial or parallel data channels, in synchronous systems, clock information is needed for receiving the data. So embedded clock signal information has to be recovered from the data 114. This clock recovery is performed by PLL 110. PLL 110 frequency and phase locks onto the embedded clock signal information.
To minimize frequency and phase errors between the actual clock signal and the recovered clock signal 136, the recovered clock signal 136 is fed back via feedback link 146 to the pulse gate circuit 120. The pulse gate circuit 120 passes through a VCO pulse every time it receives a pulse on data signal link 154. The pulse gate circuit 120 transmits the recovered clock signal 136 to the phase-frequency detector 118. The phase-frequency detector 118 minimizes phase and frequency differences between the clock signal associated with data 114 and the recovered clock signal 136. When the PLL 110 is in a locked state, then the phase and frequency error between the recovered clock signal 136 and the clock signal in the data 114 is small or zero.
The PLL 110 can lose lock. Loss of lock is the state of the PLL when the phase and/or frequency differences between the recovered clock signal 136 and the clock of the data signal 114 have become substantial. A loss of lock of PLL 110 can occur, for instance, when, the loop filter 126 picks up electrical noise from the environment where the PLL 110 is located. This environmental noise may introduce a significant error into the recovered clock signal 136. The size of the noise error depends in part on the gain of the VCO 130. The larger the gain of the VCO 130, the larger will be the environmental noise induced error in the recovered clock signal 136.
The VCO 130 is an analog device. Consequently, the PLL 110 can achieve a high phase resolution of the recovered clock signal 136. However, typically analog adjustment of the phase and/or frequency of the recovered signal 136 is relatively slow. To increase the speed of adjusting the phase of the recovered clock signal 136, some PLL's 110 include a digital adjustment of the phase of the recovered signal 136 in addition to the analog adjustment. Digital adjustment by use of delay increment cells combined with analog adjustments may be utilized. The delay increment cells are part of a VCO. They provide initial digital adjustment of a signal at the output of the VCO. The delay increment cells are intended to provide for a relatively fast phase lock of a PLL. The circuit for the analog adjustment also is included in the same VCO. That circuit is for fine tuning of the phase of the signal at the VCO output. However, to double the precision of the digital adjustment, the number of delay increment cells would have to be doubled as well. Such doubling doubles the power consumption of the delay cells and will significantly enlarge the required area of the circuit.
Another drawback of the digital cell approach is that it requires a more complicated VCO design. Instead of being a standard device, such a VCO must be designed to include two tuning components: a digital component and an analog component. Typically more complicated designs result in greater expense, which results in overall a more expensive PLL. More complicated designs generally also are more prone to failures than simpler designs.