Many types of semiconductor devices exist for storing information. Generally the storage falls into one of two categories: long-term or short-term. Long-term storage devices include read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash nonvolatile memory (Flash NVM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), silicon-oxide-nitride-oxide on silicon (SONOS) memory, and many others. In many of these long-term storage devices the stored information comprises a quantity of electronic charge stored in a charge retention region of a semiconductor device. Long-term memories typically have relatively low leakage rates, so that they remain readable for a period on the order of years. Short-term storage devices generally are denser and more easily erased and rewritten than long-term storage devices, but typically suffer from relatively high leakage rates. These devices include well-known dynamic random-access memory (DRAM), switched-capacitor and capacitive trim circuits, and variants thereof. Because these devices lose their stored electronic charge typically on a timescale of microseconds to milliseconds, they need to be refreshed at least that often so that, over time, they maintain the stored information. Many circuits for refresh are well known to those of ordinary skill in the art of semiconductor design.
Many prior approaches exist for nonvolatile storage of electronic charge on floating-gate MOSFETs (metal-oxide semiconductor field effect transistors). Such approaches typically require the use of voltages higher than those needed for the operation of normal CMOS (complementary metal oxide semiconductor) logic, and/or they employ asymmetric charge control in that one technique is used to add charge to the floating gate, while a different technique (with corresponding different structure and/or different power requirements) is used to remove charge from the floating gate. In most approaches, the value of the stored charge on the floating gate cannot be read while the charge is undergoing modification.
Turning to FIG. 1, a typical prior art approach to such a device is illustrated in simplified form. A floating gate MOSFET 10 is formed on a p− substrate 12 of a semiconductor wafer. An n− well 14 is formed therein and in the n− well are formed a source region 16 and a drain region 18 of p+ material. Above the channel 20 between source 16 and drain 18 is a layer of insulator 21 such as silicon oxide (or nitride or oxynitride or other well-known insulating materials), which may be grown or deposited. Over the insulator 21 is formed a charge retention layer 22, or “floating gate” which is capable of retaining charge typically by being an isolated conductor of charge such as a metal or heavily doped polycrystalline silicon (polysilicon). An additional layer of insulator 24 is usually applied and a conductive control gate 26 usually tops out the structure. The control gate 26 is usually implemented in a second layer of heavily doped polysilicon. A common approach for adding charge to and/or removing charge from a floating-gate MOSFET is to use Fowler-Nordheim (FN) tunneling. FIGS. 2A, 2B and 2C are electron band diagrams illustrating a semiconductor, an insulator and a gate. FIG. 2A illustrates a condition with no voltage applied across the insulator. As illustrated in FIG. 2A, a relatively thick, pure, and low-leakage SiO2 insulator 27 forms a potential barrier 28 that isolates the gate 30 from a doped region 32 of a semiconductor substrate. In FN tunneling, illustrated in FIG. 2B, a voltage applied across the insulator 28 causes electrons to tunnel, via quantum-mechanical mechanisms, through the potential barrier 28 between the semiconductor 32 and the insulator 27 and into the conduction band of the insulator 27, and thereby to be transported to the gate 30. A voltage of opposite polarity likewise causes electrons to be transported from the gate 30, through the insulator 27, to the semiconductor 32. FN tunneling allows charge to accumulate on the floating gate 30, or to be removed therefrom.
Using Fowler-Nordheim tunneling for charge transfer has some drawbacks. First, it requires the use of voltages that typically exceed those available for normal CMOS circuit operation. Thus charge pumps or additional power supplies are required. Second, most implementations use transistors with control gates, with the control gate typically implemented from a second layer of polysilicon over the floating gate. This additional polysilicon layer increases the cost and complexity of device manufacture over the more common single-polysilicon CMOS processing. Third, because of the relatively high electric fields required to implement Fowler-Nordheim tunneling through an insulator, damage to the insulator gradually occurs, typically resulting in increased charge leakage. This damage usually manifests as a Stress-Induced Leakage Current (SILC), and is why most EEPROM or Flash nonvolatile memories have limited lifetimes (e.g. approximately 105 cycles in current commercial products).
An alternative to Fowler-Nordheim tunneling is direct tunneling. In direct tunneling, illustrated in FIG. 2C, the insulator 27 is thin enough such that appreciable tunneling occurs even when the voltage across the insulator 27 is less than the difference in electron affinities between the semiconductor 32 and the insulator 27 (e.g. 3.2 Volts for a silicon-SiO2 barrier). One significant benefit of using direct tunneling over Fowler-Nordheim tunneling is reduced insulator stress and reduced SILC, due to the lower insulator electric fields. Another significant benefit is that direct tunneling doesn't require voltages significantly higher than those needed for normal logic-CMOS operation. One reason that direct tunneling has not been widely used in electronics applications is that the insulator tends to leak electrons by the same direct-tunneling mechanism as is used to write or erase it, and thus cannot retain the charge on the floating gate for more than a short period of time (from milliseconds to perhaps hours or days). For memory applications, some have enhanced the effective retention time of direct-tunneling insulators by using control gates and refresh circuits to, in effect, make a low-refresh-rate DRAM. Others have modified the insulator and/or the floating gate to add a leakage-stop barrier to retard or reduce leakage. Both of these approaches are unavailable in standard single-poly logic CMOS due to the requirement for a control gate disposed over the floating gate, or to the requirement for specialized CMOS processing to add the leakage-stop barrier. A second reason that direct tunneling has not been widely used in electronics applications is that floating gates are typically associated with nonvolatile memories, and nonvolatile memories are typically optimized to store digital data, a byproduct of which, for example, is the fact that most nonvolatile memory devices don't allow simultaneous reading and writing or reading and erasing, regardless of whether they use FN or direct tunneling, or another mechanism to write or erase the floating gate. Consequently, direct-tunneling floating-gate circuits have been generally unavailable to CMOS circuit designers.
It would be desirable to provide a floating-gate memory device compatible with generic single-poly logic-CMOS process technology without requiring double-polysilicon control gates and without the need for modified CMOS processing, while using a direct tunneling approach for adding charge to and/or removing charge from the floating gate. It would also be desirable to provide a floating-gate memory device that allowed simultaneous reading and writing and/or reading and erasing, to facilitate the use of such floating-gate circuits in analog and/or digital circuit design.