It is well known that in the art of integrated circuit manufacture one of the primary goals is increasing the number of devices that can be placed into a given space on the semiconductor chip. As the traditional fabrication processes begin to approach their limits of reduction, process and device designers have increasingly turned their attention toward orienting the device elements vertically in a direction normal to the surface of the semiconductor wafer, rather than in the more traditional orientation of a horizontal or planar direction along the flat water surface. Thus, considerable attention has been applied to forming devices on pillars or mesas above the wafer surface or down into trenches into the wafer to take advantage of the extra versatility of the third dimension.
One of the more successful vertically oriented integrated circuit devices is the trench capacitor. Briefly, a trench capacitor is formed by forming a trench into the semiconductor substrate, lining the substrate with a thin dielectric layer and plugging the remainder of the trench with a semiconductor material. The semiconductor substrate and the semiconductor material plug are both doped with impurities to make them conductive allowing them to form the plates of the capacitor across the thin dielectric.
One such trench capacitor is used in the buried storage electrode (BSE) cell devised by M. Sakamoto, et al., "Buried Storage Electrode (BSE) Cell for Megabit DRAMs,"IEDM 1985 Digest, December, 1985, p. 710-713, and illustrated in FIG. 2. The BSE cell 10 is a dynamic random access memory (DRAM) cell having one-transistor 12 with the memory word line 14 as the gate of the transistor, the memory bit line 16 as the one of the source/drain regions where the other source/drain region 18 of the transistor 12 is tied to one plate 20 of the capacitor. The capacitor 22 is formed in a trench 24 which pierces the p.sup.- epi layer 26 to intersect and penetrate the p.sup.+ substrate 28. Capacitor 22 comprises two plates, the central conductive material plate 20 and the plate formed by p.sup.+ substrate 28 separated by thin dielectric film 30. Due to depletion layer spreading in the p.sup.- epi layer 26, most of the effective capacitance of the BSE cell 10 is in the p.sup.+ substrate 28. Because of its inherent punchthrough-free nature and high immunity against alpha-particle soft errors, the BSE cell 10 is suitable for high density integration.
The limitations on the trench capacitor, such as the trench capacitor 22 of BSE cell 10, are mainly due to the ability to etch and fill the trench 24. Trenches may typically have 6-7 micron (um) depths with approximately 1.5 .mu.m openings. Thus, one approach to increase the capacitance of capacitor 22 would be to form the trench 24 deeper to contact the p.sup.+ substrate.
The p.sup.- epi layer 26 also has a minimum limitation on thickness due to the outdiffusion of boron from the heavily doped p.sup.+ substrate 28. If the p.sup.+ substrate 28 is too close to the bottom of the n-well layer 29, or in other words, if the epi p.sup.- layer 26 is too thin, then the n-well 29 doping must be undesirably high to avoid punchthrough of the p.sup.+ source/drain region 31 junctionto-well depletion layer with the well-to-substrate depletion layer. Stated another way, the undesirable punchthrough effect or shorting of the carrier flow from the source/drain 31 to the substrate 28 would occur. This can be solved by heavy doping of the well 29. However, the extra heavy doping of the wall 29 in turn degrades the body effect of the p-channel metal-oxide-semiconductor transistor (PMOST) and increases the parasitic p.sup.+ junction capacitance.
Thus, while the principles behind the BSE cell are sound, the practical aspects of building a device dictate that the capacitor of the cell would not have the desired amount of capacitance, or if the correct capacitance were attained, the extra doping in the well of opposite conductivity required to raise the capacitance would undesirably affect the PMOST devices.