It is known in the state of the art that a Flash memory comprises at least a SRAM (Static Random Access Memory) cell. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors which form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors of the SRAM cell. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected with a pair of bit-lines used for storing a bit into, or reading a bit from, the SRAM cell.
A typical SRAM cell configuration is a latch connected by means of two pass transistors with a pair of bit-lines in turn connected with a charging circuit and with an input/output circuit. As shown in FIG. 1, the SRAM cell 1 comprises a pair of cross coupled inverters comprising a first storage node 11 and a second storage node 12 complementary to each another; each inverter comprises preferably (not shown in FIG. 1) a couple of MOS transistors, a PMOS transistor having the source terminal connected to the supply voltage Vcc and the drain terminal connected to the drain terminal of the NMOS transistor having the source terminal connected to ground GND. The SRAM cell 1 has the storage nodes or external terminals 11 and 12 connected with the respective bit-lines 21 and 22 by means of the pass transistors 31 and 32.
A charging circuit 50 provides to charge the bit-lines 21 and 22 and an input/output circuit 60 provides to write or read the SRAM cell; a decoder circuit 70 can be provided between the bit-lines 21 and 22 and the input/output circuit 60. The control gates of both the transistors 31, 32 are connected with a word-line WL. Writing into the cell comprises the unbalancing of the SRAM cell by unbalancing the bit-lines 21, 22. The input/output circuit 60 comprises, a buffer and an inverter and pass transistors 61, 62; when it needs writing a bit “0” in the SRAM cell 1 which stores a bit “1” one between the bit-lines 21, 22 is unbalanced by the circuit 60, that is the circuit 60 controls the bit-lines 21 and 22 to have opposite logic values.
A circuit scheme of the input/output circuit 60 is shown in FIG. 2 together with SRAM cell 1 and the pre-charge circuit 50. It should be noted that the decoder circuit 70 shown in FIG. 1 is omitted from FIG. 2. The circuit 60 includes a buffer 63 that has at the input terminal INPUT_DATA the bit “0” or the bit “1”, and the output terminal of the buffer 63 is connected with the bit-line 21 by means of the pass transistor 61 and with the bit-line 22 by means of the series of an inverter 64 and the pass transistor 62. When a bit “0” or a bit “1” is present at the input terminal of the buffer 63 the pass transistors 61 and 62 are enabled; for example when it is necessary to write a bit “0” in the SRAM cell 1 which stores a bit “1”, the pass transistors 61, 62 are enabled to unbalance the bit-line 21, 22 so that a bit “1” is present at the bit-line 21 and a bit “1” is present at the bit-line 22, that is the bit-line 21 is forced to the low voltage Li and the bit-line 22 is forced to the high voltage Hi. In this way, with the pass transistors 31, 32 enabled by the word-line WL, the bit “0” may be written into the SRAM cell 1. A new bit “0” or “1” may be written on the SRAM cell 1 only whether said SRAM cell stored currently a bit “1” or a bit “0”; in the other cases the bit currently stored in the SRAM cell will be confirmed.
Since data read and write operations of the above SRAM are well known in the art, the detailed descriptions thereof will be omitted. The SRAM according to the prior art does not, however, support a data write mask function in which data “0” and/or “1” to be written are masked to be released from being written into a selected memory cell.