1. Technical Field
The embodiments herein generally relate to dynamic range detection, and, more particularly, to dynamic range detection in CPUs in receivers.
2. Description of the Related Art
Typically central processing unit (CPU) architectures in digital signal processors do not support efficient implementation of block floating point processing on arrays. Even in architectures, where block floating is supported, a lot of control code needs to be added to take care of pre and post scaling of data blocks based on a dynamic range of signals at each stage. The problem with these existing methods is that the overheads in the control code for detecting the dynamic range of signals could be significant to the extent that it may run out of the available MIPS or cycles for a given application.
In addition it needs to support arithmetic data-path widths that are higher than the optimal. This potentially leads to bigger designs, consequently increasing area and leading to more than necessary power dissipation. Both fixed and floating-point implementations have their respective advantages. It is possible to achieve the dynamic range approaching that of floating-point arithmetic while working with fixed-point processors. This can be accomplished by using floating-point emulation software routines.
Fixed point representation is a real data type for a number that has a fixed number of digits after the radix point. Floating point describes a system for representing real numbers which supports a wide range of values. Numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. In fixed point processors it is possible to achieve the dynamic range of signals similar to that achieved in floating-point processors by using floating-point emulation software routines. Emulating floating-point behavior on a fixed-point processor is very cycle intensive, since the emulation routine manipulates all arithmetic computations to artificially implement floating-point math on a fixed-point device. This software emulation is only worthwhile if a small portion of the overall computation requires extended dynamic range. Hence, a cost-effective alternative for floating-point dynamic range implemented on a fixed-point processor is needed. This is where block floating point algorithm plays a significant role.
The block floating point algorithm is based on the block automatic gain control (AGC) concept. The AGC scales values at the input stage of a signal processing function and only adjusts the input signal power. The block floating point algorithm takes it a step further by tracking the signal strength from stage to stage to provide a more comprehensive scaling strategy and extended dynamic range. The floating-point emulation scheme discussed here is the block floating-point algorithm. The primary benefit of the block floating-point algorithm emanates from the fact that operations are carried out on a block basis using a common exponent. Here, each value in the block can be expressed in two components namely a mantissa and a common exponent. The common exponent is stored as a separate data word. This leads to a minimum hardware implementation compared to that of a conventional floating-point implementation.
The value of the common exponent is determined by the data element in the block with the largest amplitude. In order to compute the value of the exponent, the number of leading zeros or leading ones bits has to be determined. This is determined by the number of left shifts required for this data element to be normalized to the dynamic range of the processor. If a given block of data of the input signal consists entirely of small values, a large common exponent can be used to shift the small data values left and provide more dynamic range. On the other hand, if a data block contains large data values, then a small common exponent will be applied. Once the common exponent is computed, all data elements in the block are shifted up by that amount, in order to make optimal use of the available dynamic range. Scaling each value up by the common exponent increases the dynamic range of data elements in comparison to that of a fixed-point implementation.
In communication based applications an analog to digital converter (ADC) is used for sampling the input signals. The ADC specifications like Effective number of Bits (ENOB) etc are usually chosen on the basis of worst case channel conditions which is why these have sufficient Headroom beyond the required SNR requirements. This is shown in FIG. 1. FIG. 1 is a typical block diagram illustrating how worst case dynamic range is considered for ADC selection. However in an actual application these worst case conditions will not occur at all times. This will result in a variable and lesser than the maximum required dynamic range of the incoming sampled signals on an average while processing such samples for any signal processing function (like filtering, FFT etc). In a typical DSP CPU these sampled signals will be read for any signal processing operation and at the end of the signal processing tasks these will be written to a Data memory. Because of the varying nature of dynamic range of the incoming signal which is read, the output data from a signal processing is also likely to have some variation of dynamic range. This is why block floating point implementation of signal processing functions is useful so that it consumes lesser power, without sacrificing area.
There are some hardwired architectures for doing block floating point implementations for FFT computations. Since, they are hardwired blocks there is no overhead due in SW cycles consumption, though they would consume finite cycles. In addition, since these address only one class of signal processing functions like FFT, they cannot be reused for other classes.