This invention relates generally to a method of fabricating integrated circuits having capacitors, and more particularly, to a method of fabricating such circuits with vertical capacitors embedded in dielectrics.
integrated circuits typically have components in addition to the well-known components such as field effect and bipolar transistors. For example, capacitors are widely used to store charge in both analog and digital circuits such as the well-known dynamic random access memory (DRAM). A capacitor is formed by two conducting plates, generally parallel, that are spaced apart from each other by a dielectric. The stored charge is proportional to the product of the capacitance and voltage. The latter term is determined by system designers and, for some DRAMS, is in the range of 2 to 5 volts. The capacitance is proportional to the product of the plate area and dielectric constant divided by the distance between the plates. Regardless of the particular application, designers attempt to maximize the amount of charge stored by the capacitor subject, of course, to constraints imposed by fabrication costs and limited substrate area.
Many approaches to capacitor design and fabrication have been explored and several which have been published prior to the filing date of this application are briefly discussed below.
For example, U.S. Pat. No. 4,409,608, issued on Oct. 11, 1983 to Yoder, describes a recessed or embedded capacitor formed by removing material from a high resistivity substrate such as GaAs, and then filling the resulting recesses with a metal. The recesses are formed by a conventional lithographic technique. For example, a resist is deposited and patterned and the now exposed portions of the substrate removed to a desired depth. The resulting recesses are then filled with metal and the resist removed. The capacitor plates may be interleaved to increase the effective area of the capacitor plates.
Another approach is illustrated in U.S. Pat. No. 5,162,890, issued on Nov. 10, 1992 to Butler. This approach uses stacked capacitors; that is, a second capacitor is placed above a first capacitor and the two capacitors are connected in parallel. For example, in FIG. 8 of this patent, conducting plates of a first capacitor are formed by regions 38 and 42, and the conducting plates of a second capacitor are formed by regions 42 and 45. The dielectrics between the conducting plates are formed by regions 40 and 44 for the first and second capacitors, respectively. Stacked capacitors increase the capacitance per unit substrate area as compared to a single planar capacitor.
An approach to a capacitor formed in a dielectric with electrical contacts to the top and bottom electrodes in described in U.S. Pat. No. 6,168,991, issued on Jan. 2, 2001 to Choi. For example, FIG. 6 of this patent depicts a first electrode 20 and a second electrode 26 with a dielectric region 22 between the two electrodes. The embodiment depicted in FIG. 6 forms the capacitor in openings formed in a patterned dielectric 12 with the first electrode contacting a conductive plug 14. The layers forming the electrodes and the dielectric are sequentially deposited after the openings in the dielectric layer 12 are formed. The resulting capacitor requires only a single mask after transistor formation and is stated to be especially useful with DRAMs.
MIM (metal-insulator-metal) capacitors are widely used in both analog and mixed signal applications. An ability to integrate such capacitors into the back end of the line (BEOL) is desirable for many applications. A MIM capacitor is described by Armacost et al. in IEDM Technical Digest, 2000, pp 157-161. A sectional view of the capacitor is shown in FIG. 4 (a). There is a top plate above a bottom plate; both plates are defined lithographically and two masks are thus required. In addition to requiring two masks, the capacitor described therein has significant topography when finished.
A method of fabricating capacitors embedded in a back end of line (BEOL) or multi-level interconnects is described. The metal lines in BEOL may be formed by a dual or single damascene process used to fabricate an integrated circuit. The capacitor plates are separated from each other by a capacitor dielectric and are substantially perpendicular to a major surface of a silicon wafer on which the integrated circuit is formed. The plates and the dielectric layer have a planar surface.
Viewed from a first method aspect, the invention includes a method of fabricating an integrated circuit comprising the steps of: forming a dielectric layer on a substrate; patterning said dielectric layer to form trenches; forming first metal regions in said trenches, said first metal regions and said dielectric layer having a planar surface; patterning a resist layer to form openings which expose portions of said first metal regions and adjacent dielectric layer; etching said exposed metal regions and said dielectric to form trenches; depositing an insulating layer; forming second metal regions; and planarizing the surfaces of said first and second metal regions and said dielectric.
Viewed from a second method aspect, the invention includes a method of forming capacitors in a dielectric comprising the steps of: forming a plurality of trenches in a dielectric layer, said trenches being filled with a first metal to form first metal regions, said first metal regions and said dielectric layer forming a planar surface; selectively removing portions of said first metal regions and said adjacent dielectric; sequentially depositing a dielectric layer and a second metal; and planarizing said second metal, to form second metal regions, and said dielectric layer.
Viewed from a third method aspect, the invention is a method of fabricating an integrated circuit comprising the steps of: forming a plurality of devices in a semiconductor substrate, said devices having electrical contacts; forming at least one dielectric layer covering said devices and said substrate; fabricating capacitors in said at least one dielectric layer, said capacitors each having first and second plates separated by a second dielectric layer, said plates being formed in a trench and being substantially perpendicular to a major surface of the first dielectric layer; and forming electrical connections between said capacitors and said devices.