1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly a semiconductor device having a dummy pattern for reducing a difference in level, which appears on a surface of a filling film in a later step due to a trench isolation region of a small aspect ratio, and thereby improving a flatness of the surface as well as a method of manufacturing the same.
2. Description of the Background Art
As a result of polishing such as CMP (Chemical Mechanical Polishing) in a conventional process of manufacturing a semiconductor memory device, a difference in level appears on a surface of a filling film in a later step due to a trench isolation region of a small aspect ratio. For reducing this difference in level, it is well known to form a dummy pattern in the isolation region of the small aspect ratio.
For example, shallow trench isolation, which has been actually used in recent years, is implemented such that a portion which is not an active region entirely forms a wide trench of a small aspect ratio providing an isolation region with. This trench having a small aspect ratio causes a difference in level on the isolation region. A problem caused by this level difference will now be described below with reference to a CMOS (Complementary Metal Oxide Semiconductor) shown in FIG. 10, and then a conventional manner for overcoming the problem will be described.
In this CMOS, as shown in FIG. 10, a p-type Si substrate 101 is provided at its upper portion with an n-well region 102 having a predetermined depth from the surface of p-type Si substrate 101. A p-well region 105 having a predetermined depth from the surface of Si substrate 101 is formed in a region of Si substrate 101 right to n-well 102. As a result of trench isolation, convex regions 141a, 142a, 141b and 142b are formed, and concave regions 103 are formed between convex regions 141a and 142a and between convex regions 141b and 142b, respectively. Active regions, i.e., source/drain 109a and 110a as well as a gate oxide film 107a and a gate electrode layer 108a are formed on the upper portion of convex region 141a in n-well region 102. Source/drain 109b and 110b as well as gate oxide film 107b and gate electrode 108b are formed on the upper portion of convex region 141b in p-well 105. Concave regions 103 and a wide trench isolation region 200 are filled with filling oxide films 106. Source/drain 109a and 110a, gate oxide film 107a, gate electrode 108a, source/drain 109b and 110b, gate oxide film 107b and gate electrode 108b are covered with an interlayer oxide film 112. An interconnection layer 113 is formed on interlayer oxide film 112.
In the conventional CMOS having the above structure, a difference d1 in level is present between the bottom of wide trench isolation region 200 and tops of convex regions 141a and 141b, and trench isolation region 200 has a small aspect ratio. Therefore, filling oxide film 106 deposited in trench isolation region 200 has a concave top surface. After the deposition, processing such as CMP or etch-back is effected on the concave surface of oxide film 106 for flattening the same. However, the surface still has a concave form even after the flattening processing due to a significant influence of the concave form of the surface before the processing. As a result, a difference d2 in level is present between the highest and lowest portions of the concave surface of filling oxide film 106 formed in trench isolation region 200. In the final structure, interlayer oxide film 112 is formed on the concave filling oxide film 106 having the level difference d2, and interconnection layer 113 is formed on interlayer oxide film 112. The concave form still remains in this final structure, and a difference d3 in level is likewise present between the highest and lowest portions.
For overcoming the above problem, a manner shown in FIG. 11 may be employed in the prior art. In this manner, convex regions 143a and 143b shown in FIG. 11 are formed in a region, which corresponds to isolation region 200 in FIG. 10 having a small aspect ratio, simultaneously with convex regions 141a and 141b carrying transistors and convex regions 142a and 142b forming electrodes connected to interconnections. In other words, as shown in FIG. 11, isolation regions 103 leaving convex regions 143a and 143b are formed for trench isolation in the region corresponding to isolation region 200 shown in FIG. 10. This manner can suppress occurrence of level difference d3 which may appear after formation of interlayer oxide film 112, and can form interconnection layer 113 on substantially flat interlayer oxide film 112, as shown in FIG. 11.
However, convex regions 143a and 143b shown in FIG. 11, which are formed in the hollow region 200 of a small aspect ratio shown in FIG. 10 have an electrical conductivity. Therefore, in the structure shown in FIG. 11 wherein interconnection 113 crosses convex regions 143a and 143b under the same, unnecessary capacitor structures are formed between interconnection 113 and convex regions 143a and 143b, if a distance d4 between interconnection 113 and each of convex regions 143a and 143b is short.
Although not shown, convex regions 143a and 143b may overlap with gate electrodes of transistors located above them. In this case, an unnecessary capacitor structure is formed over a large area along the gate interconnection because the gate oxide film is thin. This results in increase in parasitic capacity and therefore deterioration of electrical characteristics so that a percent defective of the transistors increases, or a burn-in time for screening increases.
In the conventional structure provided with dummy convex regions as described above, interconnections arranged at a higher level increase the parasitic capacity and thus deteriorate the electrical characteristics so that good products cannot be produced.