1. Field of the Invention
The invention relates to capacitor arrays and, in particular, to a capacitor array layout technique which improves capacitor matching.
2. Description of the Related Art
A successive approximation analog-to-digital (A/D) converter uses a binary weighted capacitor array. For a binary search algorithm, the ideal size of these capacitors obeys the following ratios. The smallest capacitor has a single unit capacitance, the capacitance of the next one is two units, four units, eight units and up to 2n−1, wherein n is the bit resolution of the A/D converter. This requires a capacitance of 1024 units for a 10-bit A/D with the largest capacitor having 512 units.
To improve matching, capacitor array layout requires special attention. The capacitor array needs to be laid out so as to avoid process variations. FIG. 1 shows a conventional capacitor array layout. The capacitor array is laid out as a set of concentric capacitors with increasing radii based on the size of the capacitor. Good matching can be achieved since the symmetrical layout reduces the systematic mismatch by canceling the first order degradation. However, the routing of the inner capacitors induces significant parasitic capacitance. Since the parasitic capacitance associated with each binary-weighted capacitor is not in a binary-weighted relation, matching between the capacitors is thus degraded.
In many applications of binary-weighted capacitor array such as capacitor digital to analog converter (C-ADC), top plates of every capacitor are commonly connected, as shown in FIG. 2. If the parasitic capacitances induced by the routings associated with nodes MSB, MSB−1, . . . , LSB+1, and LSB are not in a binary-weighted relation, integral nonlinearity (INL) and differential nonlinearity (DNL) of a transfer curve of the digital to analog converter could be significant and may have a great impact on high resolution applications.