The present invention relates to metal lines used for flat panel display devices such as a liquid crystal display (LCD), a field emission display (FED), an electrophoretic display (EPD), a plasma display (PDP), an electrochromic display (ECD) and an electroluminescent display (ELD), a flat panel type image sensor employing an active matrix substrate, a printed wiring board employing a ceramic substrate and metal lines used in a variety of other fields, a method for fabricating the metal lines, a thin film transistor employing the metal lines and a display device.
In a flat panel display represented by the liquid crystal display (LCD), there is adopted a drive system holding a display material such as liquid crystals between a pair of substrates and applying a voltage to this display material. In this case, electric interconnecting lines made of a conductive material are arranged at least on one substrate.
For example, in the case of an active matrix drive type LCD, gate electrodes and data electrodes are arranged in a matrix form on one substrate (active matrix substrate) of a pair of substrates that hold the display material between them, and thin film transistors (TFTs) and pixel electrodes are arranged at the intersections of them. Normally, these gate electrodes and data electrodes are formed of a metal material of tantalum (Ta), aluminum (Al), molybdenum (Mo) or the like and formed into a film by a dry system film forming method such as the sputtering method.
If it is attempted to increase the area and improve the resolution of such a flat panel display, then a drive signal delay emerges as a serious problem due to increased line resistance and parasitic capacitance according as a drive frequency is increased.
Therefore, in order to solve the problem of the drive signal delay, it is tried to use copper (Cu) (bulk resistivity: 1.7 xcexcxcexa9xc2x7cm) having a smaller electric resistance for the interconnecting material in place of the conventional interconnecting material of Al (bulk resistivity: 2.7 xcexcxcexa9xc2x7cm), xcex1-Ta (bulk resistivity: 13.1 xcexcxcexa9xc2x7cm) and Mo (bulk resistivity: 5.8 xcexcxcexa9xc2x7cm). For example, xe2x80x9cLow Resistance Copper Address Line For TFT-LCDxe2x80x9d (Japan Display xe2x80x289 p.498-501) discloses the result of examination of a TFT-LCD that uses Cu as a gate electrode material. According to this reference document, there is a clear statement of the necessity of an improvement in adhesion property by providing a metal film of Ta or the like as a groundwork since a Cu film formed by the sputtering method has a degraded property of adhesion to a foundation glass substrate.
However, the Cu interconnecting line structure has the problems as follows.
That is, when forming both of a Cu film intended for a reduction in resistance and a groundwork metal Ta film intended for an improvement in the adhesion property of the Cu film by the sputtering method or the like by means of a vacuum film forming apparatus, the Cu film and the groundwork metal Ta film need individual film forming processes, and this increases the processes, leading to a cost increase. The Cu film and the groundwork Ta metal film also need individual etching processes, and this increases the processes, leading to a cost increase. Furthermore, the aforementioned Cu interconnecting line structure requires an increase in scale of the vacuum film forming apparatus and the etching apparatus in accordance with an increase in area of the display, i.e., an increase in film forming area, and this disadvantageously causes a production cost increase.
Accordingly, it is demanded to establish a Cu interconnecting line fabricating technique by a wet type plating system technique capable of forming a film at low cost without the need of any vacuum film forming apparatus.
On the other hand, Japanese Patent Laid-Open Publication No. HEI 2-83533 discloses the method of forming a Cu interconnecting line by a plating film forming technique without using any vacuum film forming process such as the sputtering method. In this case, a nickel (Ni) film and a gold (Au) film are successively formed by electroless plating on the groundwork of an ITO (Indium Tin Oxide) film, and a Cu film is further formed on them by electroless plating. With this arrangement, an electric interconnecting line having a Cu/Au/Ni laminate structure is provided.
The above-mentioned forming method is adopted because no sufficient adhesion property can be obtained when it is tried to form a Cu film by plating on a surface of an ITO film (indium tin oxide film) and because it is effective to interpose an Ni film having an excellent property of adhesion to the groundwork before forming the Cu film.
As shown in FIG. 8, if an electroless Cu plating film 102 is provided directly on this electroless Ni film 101, then there occurs the problem that the so-called xe2x80x9cblisteringxe2x80x9d defect of the separation of the Ni film 101 from the interface between the film and a groundwork ITO film 105 provided on a glass substrate 106 as a consequence of the permeation of a Cu plating solution through a pinhole 103 of the Ni film 101 tends to occur.
Accordingly, Japanese Patent Laid-Open Publication No. HEI 2-83533 adopts the method of forming an Ni film to a thickness of not smaller than 0.4 xcexcm, thereafter forming an Au film to a thickness of not smaller than 0.1 xcexcm on the surface of the Ni film by displacement plating and finally forming a Cu film to a thickness of not smaller than 0.8 xcexcm by electroless plating. This method resolves the defect of blistering that occurs after Cu plating by eliminating the pinhole of the Ni film.
According to the construction of Japanese Patent Laid-Open Publication No. HEI 2-83533, the total thickness of the Cu/Au/Ni plating film inevitably becomes 1 xcexcm or greater, as described hereinabove. According to this Japanese Patent Laid-Open Publication No. HEI 2-83533, there was no limitation on the total thickness of the plating on the precondition that the Cu/Au/Ni plating film was applied to a peripheral terminal portion of a liquid crystal display (LCD), and there was caused no problem if the total thickness of the plating film was formed to a thickness of 1 xcexcm or greater.
However, if it is tried to apply the aforementioned Cu/Au/Ni plating film to bus lines (signal lines and scanning lines) existing inside the LCD panel of the liquid crystal display (LCD), then there occurs the trouble as follows.
That is, if the bus lines have a difference in level of not smaller than 1 xcexcm, then the stepped portions sometimes exert a bad influence on the state of alignment of the liquid crystal layer. Furthermore, if there is a device structure in which other interconnecting lines extend across the plating interconnecting lines, then there is an increased probability of the occurrence of the disconnection of the interconnecting lines of the upper layer in the stepped portions.
Therefore, if it is tried to apply the Cu/Au/Ni plating film to the bus lines of the liquid crystal display device, then the total thickness of the plating film should preferably be restrained to a thickness of not greater than 0.5 xcexcm. In the case of the plating interconnecting lines of the Cu/Au/Ni structure, the Cu film dominates the electric performance of the interconnecting lines, whereas the Ni film merely plays the role of securing the property of adhesion to the groundwork. Therefore, if it is tried to reduce the total thickness of the Cu/Au/Ni plating film, then it is important to reduce the thickness of the Ni film in order to maintain the electric characteristics of the interconnecting lines.
However, it is required to set the thickness of the Ni film to a value of not smaller than 0.4 xcexcm in order to solve the defect of blistering as described hereinabove in the case of the metal lines described in the aforementioned Japanese Patent Laid-Open Publication No. 2-83533, and this has been a serious obstacle to the demand of reducing the total plating thickness.
Accordingly, it is an object of the present invention to provide a metal line structure in which no defect of blistering occurs on the surface of a Cu/Ni films or a Cu/Au/Ni film even if the thickness of a Ni plating film is reduced.
In order to achieve the aforementioned object, the present invention provides a metal line having a plating film structure in which a laminate film of a gold film and a copper film or a copper film is laminated by electroless plating on a nickel film formed by electroless plating, wherein
the nickel film has a phosphorus content x of:
10 wt %xe2x89xa6xxe2x89xa615 wt %, and wherein
the nickel film has a film thickness of 0.1 xcexcm or greater.
The present invention was made on the basis of the following experimental facts.
That is, in the case of the general electroless Ni plating that employs hypophosphite as a reductant, the deposit film generally becomes a eutectoid film of Ni (nickel) and P (phosphorus). However, it was discovered through experiments described later that the so-called high phosphorus content type Ni film having a phosphorus content x of 10 to 15 percent by weight was formed into a fine smooth film under the condition of a film thickness of not smaller than 0.1 xcexcm. This is presumably ascribed to the fact that the Ni film is deposited in an amorphous state when the phosphorus content becomes equal to or greater than eight percent by weight and consequently pinholes are hard to occur at the crystal grain boundaries. It is to be noted that the film quality is not good when the film thickness is smaller than 0.1 xcexcm since the sparse state of the Ni film becomes significant.
Then, no defect of blistering as observed in the conventional case occurred on the obtained Ni film even if the Cu film or the Cu/Au film was formed on the Ni film.
Therefore, employing the Ni film of the present structure enabled the formation of a plating film of the Cu/Ni structure or the Cu/Au/Ni structure with the Ni film of a thickness smaller than 0.4 xcexcm and facilitated the reduction in the total plating thickness.
In a metal line of one embodiment, the gold film has a thickness y of 0.005 xcexcmxe2x89xa6yxe2x89xa60.05 xcexcm.
This embodiment, which employs the high phosphorus content type Ni film, can obtain a fine Ni film having a smooth surface. Therefore, the Au film to be formed on this Ni film was reduced in thickness to a minimum of 0.005 xcexcm. It is otherwise possible to set the Au film to a thickness of not smaller than 0.05 xcexcm taking a process margin into consideration. However, taking the cost of an Au plating solution into consideration, the thickness should preferably be restrained to a thickness of not greater than 0.05 xcexcm. The metal line of this embodiment, of which the total thickness is reduced and the difference in level is accordingly reduced, can be adopted as signal lines and scanning lines inside the LCD panel.
In a metal line of another embodiment, the plating films have a total thickness z of 0.2 xcexcmxe2x89xa6zxe2x89xa61 xcexcm.
In this embodiment, the total thickness z of the Cu/Au/Ni plating film or the Cu/Ni plating film was set to a thickness of not smaller than 0.2 xcexcm. Therefore, the thickness of the Cu film can be secured to a thickness of 0.1 xcexcm when the Ni film has the smallest thickness of 0.1 xcexcm. Therefore, the minimum electric characteristic (sheet resistance) of the electric interconnecting line can be secured.
Since the total thickness of the Cu/Au/Ni plating film or the Cu/Ni plating film is set to a thickness of not greater than 1 xcexcm, the influence of the stepped portions of the bus lines exerted on the state of alignment of the liquid crystal layer can be eliminated even when the plating film is used for the bus lines of the LCD. Furthermore, even when a device structure in which other interconnecting lines extend across the bus lines is provided, the probability of the occurrence of the disconnection of the interconnecting lines of the upper layer in the stepped portions can be reduced.
One embodiment is a display device employing the metal line for at least one of a scanning line and a signal line.
According to the display device of this embodiment, the bus lines (scanning lines and signal lines) can be formed by means of an inexpensive apparatus without the need of any vacuum film forming apparatus. The film formation by electroless plating is adopted, and therefore, a film of a uniform thickness can be easily formed even on a large-area substrate. In general, the Cu film has the problem that it is hard to be dry-etched and that improvement in etching accuracy is hard to achieve in the case of the wet etching. According to the metal line of the present invention, a Cu film can be selectively formed on the groundwork Ni film pattern (or an Au/Ni pattern). Therefore, no patterning (etching) of the Cu film is needed, and this allows Cu interconnection to be easily achieved.
Therefore, according to this embodiment, a display device that is allowed to have improved performances by virtue of the adopted Cu interconnection can be provided at a low fabricating cost.
Another embodiment is a thin film transistor having a structure in which the metal line is employed as a gate electrode, and a gate insulating film, a semiconductor film and source and drain electrodes are successively formed on the gate electrode.
One embodiment is an active matrix type display device comprising the thin film transistor.
According to the active matrix type display device of this embodiment, the TFT elements to be used for the display device can be fabricated at low cost, and further the display device that has the active matrix substrate employing the TFT elements can be fabricated at low cost, similarly to the above display device.
One embodiment is a display device, wherein a driver LSI is mounted in a chip-on-glass manner on a glass substrate that constitutes part of the display device, and the metal line is employed as input and output lines of the driver LSI formed on the glass substrate.
According to the display device of the embodiment, the aforementioned metal line is employed as a driver input and output line. With this arrangement, the driver input and output line is allowed to have a reduced resistance in correspondence with the necessity of the reduction in resistance of the driver input and output line formed in the vicinity of the display device in accordance with the increase in area of the display device.
One embodiment is a metal line fabricating method comprising at least the steps of:
forming an oxide film having a specified interconnecting line shape on an insulating substrate;
selectively providing a plating catalyst on the oxide film; and
selectively forming the metal line into a film on the oxide film.
According to the fabricating method of the embodiment, the plating catalyst of Pd (palladium) or the like is selectively provided only on the oxide film wherein the pattern of the oxide film (ITO film, as a representative example) is formed on the insulating substrate such as a glass substrate. As a result, the metal line mentioned in the above can be selectively formed only on the oxide film. Therefore, if the groundwork oxide film is patterned into the specified interconnecting line shape, then there is no need for patterning the plating film, and the metal lines can be simply obtained.
One embodiment is a metal line fabricating method comprising at least the steps of:
coating a photosensitive material containing a plating catalyst on an insulating substrate;
depositing the plating catalyst into a specified interconnecting line shape by irradiation of light or ultraviolet rays on the photosensitive material; and
selectively forming the metal line into a film in a region where the catalyst is deposited.
According to the embodiment, by coating the photosensitive material that contains the plating catalyst on the insulating substrate such as a glass substrate and making the plating catalyst deposit into the specified interconnecting line shape by the irradiation of light or ultraviolet rays, the plating catalyst of Pd (palladium) or the like can be selectively deposited in a specified position on the insulating substrate. As a result, the metal line mentioned in the above can be selectively formed only in the region where the catalyst is provided. Therefore, if the groundwork catalyst is patterned into the specified interconnecting line shape, then there is no need for patterning the plating film, and the metal lines can be simply obtained.