Several different integrated circuit technologies are available to circuit and system designers in which to realize their designs. These technologies include for example, bipolar, complementary metal oxide semiconductor (CMOS), bipolar-CMOS (Bi-CMOS), gallium arsenide (GaAs), and others. As would be expected, integrated circuits based on differing technologies, or based on differing logic families within a technology, are often required to operate within a single system, and hence must accurately communicate one with another. A common problem that must be dealt with is the differing logic level voltages associated with the differing technologies, or between differing circuit families within a single technology. This problem is sometimes further exacerbated by supply voltage levels which may vary significantly, not only between different technologies, but even amongst circuits of like technologies. Additionally, it is now common to have a higher voltage to operate input/output circuits and a second lower voltage to operate internal circuits. In order to deal with such differences between circuits and technologies, designers rely upon input buffer circuits (also known as voltage translators) that are capable of translating input signal levels from an external circuit into needed logic levels of internal circuits.
The input signal levels from the external source need to be made compatible with internal switching levels, typically at the input buffer circuit. One CMOS inverter solution for modifying the circuit threshold voltages involves simply ratioing the two transistors making up an inverter at the input as shown in FIG. 1. Here, the width to length (W/L) ratio of P-type transistor 101 is made much larger than the W/L ratio of N-type transistor 102. The actual effect of this technique upon the switching point is small. This technique, however, also causes vastly unsymmetrical performance because the much larger P-type transistor 101 provides for a much faster rise time than a corresponding fall time provided by N-type transistor 102.
New standard integrated circuit interfaces, however, require differential interfaces, for example, the stub series terminated logic (SSTL), a EIA/JEDEC standard. A Wilson current mirror, as is well known in the art, is useful as a differential input receiver. The Wilson current mirror, however, requires a bias device (possibly a bandgap regulator) for improved performance. Hence, a further improvement on the Wilson current mirror would be a differential amplifier which is self biased. Such a circuit 200 is depicted in FIG. 2 which works very well for a wide range of input logic levels so long as the power supply voltage levels are maintained at a sufficiently high magnitude. The circuit 200 includes an input stage including transistors 201 and 202, a reference stage including transistors 205 and 206, and a bias source having transistors 203 and 204. This circuit 200 provides high gain essentially by modulating the bias source (203, 204) as a function of the incoming logic input signal, V.sub.IN. In addition to higher gain, cross-over currents can be almost eliminated because a logic low output does not require the source supply, and conversely, a logic high output does not require the ground supply. Those skilled in the art will recognize that the function of the input stage and reference stage can be transposed, that is, V.sub.IN can be connected to the reference stage such that the bias source is modulated as a function of the reference stage.
While the circuit 200 is an improvement over prior art circuits, there are also some drawbacks that exist with this solution. For example, by providing a high current, high gain and high bandwidth solution, the circuit 200 also introduces the propagation of noise and glitches. These problems occur because the amplifier is so fast that small perturbances at the input can be amplified and presented at the output. A one shot circuit could be added at the output of the circuit 200 to effectively lock out noise and glitches for some predetermined time (a time dependent solution). However, when that predetermined time is exhausted, any additional noise or glitch will still be propagated through. This may be more acceptable in circuits where the output of the circuit 200 is latched within the predetermined time such that later propagated errors are ignored. A non-time dependent solution includes adding a Schmidt trigger at the input thus introducing DC hysteresis (i.e., the switch point exhibits a differential between the logic high level and logic low level inputs). Yet another solution includes adding a filter stage to filter noise and suppress glitches. These solutions help to alleviate the propagation problems at a cost of additional delays, some behavioral unpredictability due to the randomness of noise, and additional design time. Thus, what is needed is a mechanism internal to the differential amplifier that is able to alleviate the problem of propagating noise or glitches through the circuit independent of time, without additional delay or operation unpredictability.
Accordingly it is desired to provide a self biased differential amplifier having DC hysteresis that does not further delay the input signal and that is predictable and easily designed into the circuit.