1. Field of the Invention
This invention relates in general to an isolation process for integrated circuits and more particularly to a method of designing an active layer mask with a dummy pattern by computer aided design (CAD) using chemical mechanical polishing (CMP) in shallow trench isolation to achieve global planarization.
2. Description of Related Art
As integrated circuit designs become more complex and the line width used in the forming process is reduced to less than 1.0 .mu.m, the development of trench isolation of the CMOS has its limitations. This is because shorter wavelengths of the light source in a photolithography process are needed for the feature size to obtain better resolution. However, its deficiency is the reduction of depth of focus. For example, when using deep ultra-violet ray of Krypton Fluoride laser (KrF laser) with a wavelength of 248 nm as a light source, to define CMOS elements with line width under 0.25 .mu.m, a short depth of focus less than 0.8 .mu.m is obtained. With this limitation, global planarization cannot be achieved by conventional trench isolation methods when the distances between active regions are too large. For chemical mechanical polishing process, if there is a region larger than 10 .mu.m without an active region in the under layer, a disk-like recess will be formed at this region after polishing; thus, the conventional trench isolation method cannot meet the requirement of global planarization.
The conventional method of trench isolation is now described with reference to FIGS. 1A to 1D. As shown in FIG. 1A, a pad oxide layer 20 is formed on a semiconductor substrate 10. A dielectric layer 30, such as a silicon nitride layer, is formed on the pad oxide layer 20. Active regions 11, 12 and 13 are formed by photolithography and etching process. Using photoresist (not shown) on the active regions as a mask, a plurality of trenches are formed by anisotropically etching the substrate 10 to a predetermined depth. As shown in FIG. 1B, an oxide layer 40 is deposited on the substrate 10 by chemical vapor deposition (CVD). After that, the oxide layer 40 is polished by CMP, using the surface of the dielectric layer 30 as a stop layer, to form a plurality of trenches 14, 15 and 16 as shown in FIG. 1C. After removing the dielectric layer and forming a gate oxide layer 50 and a polysilicon layer 60, the trench isolation process is completed as shown in FIG. 1D.
Since trenches have different widths, for example trench 15 is much wider than trench 14, the polysilicon layer 80 will have a flat surface on trench 14, but a recessed surface on the trench 15. That is, only local planarization but not global planarization can be accomplished using the conventional technique.