Outsourcing chips for fabrication is an effective way to save money and to reduce the time from design to market. However, it raises numerous security challenges for chip designers, as some of the foundries try to identify the functionality of the chip to take its ownership. Furthermore, a Trojan circuit can be implanted deliberately by some of the foundries to control or divert the chip's function by a predetermined set of states or to steal important information about the design such as encryption key. S. Skorobogatov and C. Woods, “Breakthrough silicon scanning discovers backdoor in military chip,” in PROC. 14TH INT. WORKSHOP CRYPTOGRAPHIC HARDWARE. EMBEDDED SYST., 2012, pp. 23-40; K. Vaidyanathan, B. P. Das, and L. Pileggi, “Detecting reliability attacks during split fabrication using test-only BEOL stack,” in PROC. 51ST ACM/EDAC/IEEE DES. AUTOM. CONF., 2014, pp. 1-6.
The Semiconductor Industry Association (SIA) estimates that counterfeit parts cost U.S. semiconductor companies more than $7.5 billion per year in lost revenue. While the financial losses are significant, the greater threat is the use of counterfeit electronics parts in commercial transportation and military systems. Nicole Faubert, “Counterfeit threats for electronic parts”, EDN NETWORK (Dec. 30, 2013).
Due to physical limitations in transistor scaling, Moore's law (number of transistors must be doubled every 18 months) has become obsolete. One solution to revive this law is utilizing the 3D integrated circuit (3D IC) instead of 2D. 3D ICs have multiple layers which are stacked on top of each other. These layers are connected by vertical interconnects called Through Silicon Vias (TSVs).
3D-IC can be an effective solution to the challenges that threaten the security of the chip by splitting the manufacturing process of the chip among different foundries. Y. Xie, J. Cong, and S. S. Sapatnekar, “Three-Dimensional Integrated Circuit Design”, New York, N.Y., USA: Springer, 2010. In 3D IC manufacturing the entire design of the chip is distributed among different tiers in the 3D stack. Imeson, Frank, et al. “Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation”, USENIX Security Symposium, 2013. Tiers containing critical logic blocks are sent to a trusted local foundry to be fabricated while the less critical tiers are sent to the less reliable foundries to meet their limited financial budget. The final bonding of tiers also carries out by a most trusted foundry because here is always a possibility that the final foundry to extract the gate level netlist of the design by utilizing some of the reverse engineering techniques since they have access to the entire tiers. Xie, Yang, et al. “Security and vulnerability implications of 3D ICs”, IEEE Transactions on Multi-Scale Computing Systems 2.2 (2016), pp. 108-122.
Today, chip reverse engineering uses imaging equipment to analyze and to recreate the chip. W. Li et al., “Reverse engineering circuits using behavioral pattern mining”, HARDWARE-ORIENTED SECUR. TRUST (HOST), 2012. The images can be obtained by a combination of de-layering and imaging of the chip followed by pattern recognition and pattern matching to extract the schematic of the chip. R. Torrance et al., “The State-of-the-Art in IC Reverse Engineering”, PROC. 11TH INT. WORK. CRYPTOGR. HARDW. EMBED. SYST., 2009. With all the current techniques that are used to safeguard the design of an IC chip once the manufactured chip is in the possession of an adversary the hardware design can be obtained by the reverse engineering the chip. Therefore, currently there is no high assuring way to prevent the total reverse engineering of the chip. However, if a combination of software and hardware skims is used to secure the chip, the design extraction of the chip will be nearly impossible even if the chip were subjected to the most intense reverse engineering techniques. Consequently, there is a need in the market for a more secure method for performing this chip integration.