SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.
The use of germanium in SMOS processes can cause germanium contamination problems for IC structures, layers and equipment. In particular, germanium outgassing or outdiffusion can contaminate various components associated with the fabrication equipment and integrated circuit structures associated with the processed wafer. Germanium outgassing can be particularly problematic at the very high temperatures and ambient environments associated with integrated circuit fabrication. For example, conventional IC fabrication processes can utilize temperatures of approximately 1000° C., which enhance germanium outgassing. Germanium outgassing can also negatively affect the formation of thin films. In addition, germanium outdiffusion can cause germanium accumulation or “pile up” at the interface of layers.
High levels of germanium at the surface of a wafer can adversely affect the formation of silicide layers. In particular, high concentration of germanium in a top surface of a substrate can adversely affect the formation of silicide layers above the source and drain regions. The germanium concentration at the top surface can be exacerbated by the fabrication steps associated with source and drain regions and gate structures.
Germanium contamination of IC equipment is becoming a more serious issue as IC fabrication processes explore the advantages of the higher carrier mobility of strained silicon (SMOS) devices. IC fabrication equipment that tends to become contaminated with germanium can include deposition chambers, furnaces, diffusion equipment, etching tools, etc. The quartzware associated with such equipment is particularly susceptible to germanium contamination.
Germanium contamination is particularly problematic when equipment is used in both non-germanium and germanium fabrication lines. Shared equipment must be purged of germanium contamination before it is used in non-germanium processes, because such contamination is particularly damaging to metals used during conventional IC fabrication. Further, high levels of germanium contamination can be problematic even for strained silicon (SMOS) processes.
Flash devices are particularly sensitive to low level germanium contamination, because Flash technology uses IC structures and processes that are incompatible with germanium. For example, germanium contamination may cause data retention problems for the Flash memory cell. It is nevertheless desirous to use equipment associated with the Flash fabrication line with germanium containing products (e.g., SMOS products).
Thus, there is a need for an efficient process for decontaminating a wafer surface. Further, there is a need for a system and a method which reduces germanium contamination. Even further, there is a need for a method of removing germanium from a strained silicon layer. Yet further, there is a need for a process which reduces the adverse effects of germanium on silicidation processes. Further, there is a need for a decontamination process that allows shared equipment to be used in both a Flash production line and a germanium production line.