This relates to a semiconductor device and method of manufacture of a semiconductor device having at least two transistors with different gate insulation film thicknesses.
MOSFET (metal-oxide-semiconductor field-effect transistors) elements are widely used as basic elements in semiconductor devices. In high voltage-rated ICs (integrated circuits), high voltage-rated MOS transistors are used that can be driven with voltages of 10-20 V, or more (hereinafter referred to as “high voltage transistors”).
FIG. 7 is a cross section view of a semiconductor device having high and low voltage (that is, high voltage-rated and low voltage-rated) transistors according to a conventional configuration. FIG. 7 shows high voltage PMOS and NMOS transistors Tr1, Tr2 and low voltage PMOS and NMOS transistors Tr3, Tr4, formed on a p-type semiconductor substrate 101. In semiconductor substrate 101, the regions of transistors Tr1, Tr2, Tr3 and Tr4 are separated from each other by means of element-separating insulator film 102.
In the high voltage PMOS transistor formation region, n-type well 111, p-type drain region 112, and p+-type drain region 113 are formed in semiconductor substrate 101. At a prescribed distance from the end portion of p-type drain region 112, p+-type source region 114 is formed on the surface of n-type well 111, and the portion between p-type drain region 112 and p+-type source region 114 becomes the channel-formation region. Also, n+-type back gate 115 is formed adjacent to the side opposite to the channel-formation region of p+-type source region 114. And, gate-insulation film 116 is formed to cover the channel-formation region, and gate electrode 117 is formed as the upper layer on it. This arrangement forms the high voltage PMOS transistor Tr1.
In the high voltage NMOS transistor formation region, n-type drain region 121 and n+-type drain region 122 are formed in semiconductor substrate 101. At a prescribed distance from the end portion of n-type drain region 121, n+-type source region 123 is formed on the surface of semiconductor substrate 101, and the portion between n-type drain region 121 and n+-type source region 123 becomes the channel-formation region. Also, p+-type back gate 124 is formed adjacent to the side opposite the channel-formation region of n+-type source region 123. And, gate-insulation film 125 is formed to cover the channel-formation region, and gate electrode 126 is formed as the upper layer on it. This arrangement forms the high voltage NMOS transistor Tr2.
In the low voltage PMOS transistor formation region, n-type well 131 is formed in semiconductor substrate 101. On its surface, a pair of p+-type source/drain regions 132 are formed separated from each other by a prescribed distance, and the region between them becomes the channel-formation region. Also, gate-insulation film 133 is formed to cover it, and gate electrode 134 is formed as the upper layer on it. This forms the low voltage PMOS transistor Tr3.
In the low voltage NMOS transistor formation region, a pair of n+-type source/drain regions 141 are formed on the surface of semiconductor substrate 101, separated from each other by a prescribed distance, and the region between them becomes the channel-formation region. Also, gate-insulation film 142 is formed to cover it, and gate electrode 143 is formed as the upper layer on it. This forms the low voltage NMOS transistor Tr4.
As shown in the drawings, the various regions on semiconductor substrate 1 are allotted to formation region R1 of high voltage PMOS transistor Tr1, formation region R2 of high voltage NMOS transistor Tr2, formation region R3 of low voltage PMOS transistor Tr3, and formation region R4 of low voltage NMOS transistor Tr4, and the divided regions will be explained.
First, as shown in FIG. 8A, n-type well 111, p-type drain region 112, n-type drain region 121, and n-type well 131 are formed on semiconductor substrate 101 by means of ion implantation, etc. Then, for example, a silicon oxide film or other insulating film 102a is formed on the entire surface. Then, as shown in FIG. 8B, insulating film 102a is subjected to patterning processing to form element-separating insulator films 102. Then, as shown in FIG. 9A, thermal oxidation treatment is performed on the entire surface to form gate-insulation film 116 in high voltage PMOS transistor formation region R1. In this case, insulating film 116a is formed on the surface of semiconductor substrate 101 in high voltage NMOS transistor formation region R2 and low voltage PMOS and NMOS transistor formation regions R3, R4. Then, as shown in FIG. 9B, a pattern of a resist film is formed, and openings are formed on insulating film 116a of high voltage NMOS transistor formation region R2, and low voltage PMOS and NMOS transistor formation regions R3, R4, followed by etching treatment to remove the insulating film 116a. Next, as shown in FIG. 10A, thermal oxidation treatment is performed on the entire surface to form gate-insulation films 125, 133, 142 in high voltage NMOS transistor Tr2 formation region R2, low voltage PMOS transistor Tr3 formation region R3 and low voltage NMOS transistor Tr4 formation region R4. Then, as shown in FIG. 10B, gate electrodes (117, 126, 134, 143) are formed on gate insulated films (116, 125, 133, 142) on high breakthrough PMOS transistor (Tr1) forming region R1, high breakthrough NMOS transistor (Tr2) forming region R2, low breakthrough PMOS transistor (Tr3) forming region R3, and low breakthrough NMOS transistor (Tr4) forming region R4, respectively. Then, in each of high voltage PMOS transistor Tr1 formation region R1, high voltage NMOS transistor Tr2 formation region R2, low voltage PMOS transistor Tr3 formation region R3, and low voltage NMOS transistor Tr4 formation region R4, gate electrode, resist film, etc. are used as masks for ion implantation to form source/drain regions connected to the channel-formation regions of the various transistor formation regions.
In addition to the aforementioned manufacturing method, there is also the manufacturing method described in Japanese Kokai Patent Application No. 2004-207498.