1. Field of the Invention
The present invention relates to a manufacturing method of an integrated semiconductor circuit, and more particularly, to a method for forming a metal interconnection in a semiconductor device.
2. Description of the Related Art
In general, a semiconductor device includes transistors, resistors and capacitors. A metal interconnection is required for realizing the semiconductor device on a semiconductor substrate. The metal interconnection which transmits electric signals must have low electric resistance, and be economical and reliable. Aluminum has been widely used as a metal interconnection.
As semiconductor devices become more highly integrated, the width or thickness of the metal interconnection must be reduced, requiring the size of a contact hole be reduced. Therefore, the aspect ratio of the contact hole increases, requiring new methods for completely filling the contact hole with the metal interconnection. One proposed method for completely filling a contact hole that has a high aspect ratio and a metal interconnection is the selective chemical vapor deposition (CVD) process. The selective CVD process uses the characteristic in which a growth rate of the metal layer on an insulating layer is different from that on a conductive layer. However, as the integration density of the semiconductor device increases, the junction depth of a source/drain region of a transistor is reduced. Accordingly, an aluminum layer used as the metal interconnection is penetrated to the shallow source/drain region to be diffused to a semiconductor substrate, thereby causing a junction spiking phenomenon. Therefore, a method for interposing a barrier metal layer between the aluminum layer and the source/drain region has been used to suppress the reaction of aluminum atoms of the aluminum layer with silicon atoms of the source/drain region. The barrier metal layer is formed on the entire surface of the resultant structure where the contact hole is formed Therefore, it is impossible to selectively form the metal interconnection only in the contact hole by selective CVD process since a blanket barrier metal layer is present.
To solve the above problems, it is an objective of the present invention to provide a method for forming a metal interconnection capable of selectively forming a metal layer for interconnection in a contact hole or a groove.
According to one embodiment of the present invention for achieving the above objective, an interdielectric layer is formed on a semiconductor substrate. Then, a predetermined region of the interdielectric layer is etched, to form an interdielectric layer pattern having a recessed region. Here, the recessed region may be a contact hole for exposing the predetermined region of the semiconductor substrate or a groove which is shallower than the thickness of the interdielectric layer. When the recessed region is a groove, the metal interconnection is formed through a damascene process.
Subsequently, a barrier metal layer, i.e. a titanium nitride (TiN) layer, is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. Here, when the recessed region is the contact hole for exposing the predetermined region of the semiconductor substrate, i.e. a source/drain region of a transistor, an ohmic metal layer must be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer. Then, the barrier metal layer is annealed at a predetermined temperature if necessary, to fill the grain boundary region of the barrier metal layer with oxygen atoms. This is for preventing the diffusion of silicon atoms of the semiconductor substrate through the barrier metal layer.
Subsequently, an anti-nucleation layer, e.g. an insulating layer, is selectively formed only on the barrier metal layer formed on the non-recessed region, to thereby expose only the barrier metal layer formed on the sidewalls and the bottom of the recessed region. The insulating layer is for selectively forming a metal interconnection only in the recessed region in a process to be performed later. That is, using a characteristic in which the metal layer is not deposited on the insulating layer, the metal layer used for the metal interconnection is formed by the CVD process. Preferably, the insulating layer is one selected from the group consisting of a metal oxide layer, a metal nitride layer, a SiC layer, a BN layer, a SiN layer, a TaSiO layer and a TiSiO layer.
The metal oxide layer can be formed by selectively forming a layer having excellent oxidation characteristics, i.e. a metal layer, only on the barrier metal layer formed on the non-recessed region, and then exposing the metal layer to air or to O2 plasma. Also, the metal oxide layer can be formed by loading and oxidizing the resultant structure in a furnace, where the metal layer has excellent oxidation characteristics. The metal nitride layer, e.g. an aluminum nitride layer, may be formed by selectively forming an aluminum layer only on the barrier metal layer formed on the non-recessed region, and then exposing the aluminum layer to N2 or NH3 plasma or performing RTP in an atmosphere of NH3 and/or N2.
Preferably, a metal layer for forming the metal oxide layer is formed of an Al layer, a Cu layer, a Au layer, a Ag layer, a W layer, a Mo layer, a Ta layer or a Ti layer. Also, the metal layer may be formed of a metal alloy film containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg.
The metal layer may be formed through sputtering, a chemical vapor deposition (CVD) or a plating process. Preferably, the CVD process is performed at a temperature range corresponding to a mass transported region instead of a surface reaction limited region and at a pressure of 5 Torr or higher so that the metal layer is not formed in the recessed region. It is preferable that an argon gas and a hydrogen gas are used for a carrier gas and a reducing gas, respectively. The hydrogen gas may be used as a carrier gas. Also, the sputtering process for forming the metal layer is performed such that atoms sputtered from the target lose directionality to prevent the anti-nucleation layer from being formed in the recessed region. That is, it is preferable that the sputtering process for forming the anti-nucleation layer is performed at several mTorr using a DC magnetron sputtering apparatus without a collimator to utilize the poor step-coverage.
Alternatively, the anti-nucleation layer may be formed through a reactive sputtering process. The metal oxide layer may be formed through a O2 reactive sputtering process, and the metal nitride layer, i.e. an aluminum nitride layer, may be formed through a N2 reactive sputtering process.
As described above, the anti-nucleation layer for exposing the barrier metal layer formed in the recessed region has characteristics of the insulating layer, so that a metal layer, i.e. an aluminum layer or a copper layer, may be selectively formed in the recessed region. This is because the time required for forming metal nuclei on the anti-nucleation layer being an insulating layer is several tens through several hundreds times longer than the time required for forming metal nuclei on the barrier metal layer being a metal layer. Subsequently, a metal plug for filling a region surrounded by the exposed barrier metal layer, e.g. an aluminum plug, is formed through a selective MOCVD process. The metal plug may be formed of Cu or W instead of Al. Preferably, the aluminum plug is formed through a selective MOCVD process using a precursor containing Al. It is also preferable that the selective MOCVD process for forming the aluminum plug is performed at a temperature corresponding to a surface reaction limited region of aluminum, e.g. at a temperature lower than 300xc2x0 C. It is preferable that the precursor containing the aluminum is one selected from the group consisting of tri-methyl aluminum, tri-ethyl aluminum, tri-iso butyl aluminum, di-methyl aluminum hydride, di-methyl ethyl amine alane, and tri-tertiary butyl aluminum. Also, the selective MOCVD process uses an argon carrier gas and a hydrogen reducing gas.
Before forming the metal plug, a metal liner may be selectively formed on a surface of the exposed barrier metal layer. Preferably, the metal liner is formed of one selected from the group consisting of Al, Cu, Au, Ag, W, Mo and Ta. Also, the metal liner may be formed of a metal alloy film containing one selected from the group consisting of Al, Ag, Au, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg. It is preferable that the metal liner, e.g. a Cu liner is formed by a selective CVD process, e.g. a selective MOCVD process. The selective MOCVD process for forming the Cu liner is performed using a metal source containing Cu, e.g. Cu+1(hfac)TMVS. When the Cu liner is formed, the metal plug and Cu liner are mixed during an annealing process to thereby form a metal interconnection containing copper. Accordingly, the reliability of the metal interconnection, i.e. an electromigration characteristic thereof is improved.
When the metal plug, i.e. the aluminum plug overgrows, a sharp protrusion may be formed on a surface of the metal plug. This is because the aluminum layer has a face centered cubic (FCC) structure. Accordingly, when the metal plug overgrows, it is preferable that the metal plug is planarized through a sputter etch process or a chemical mechanical polishing (CMP) process. The above-described process is a process for forming a damascene interconnection. If necessary, the metal interconnection may be formed by additionally forming a metal layer for covering the planarized metal plug, i.e. an aluminum layer, a tungsten layer, a copper layer or an aluminum alloy layer.
According to another (second) embodiment of the present invention for accomplishing the above object, an interdielectric layer pattern having a recessed region, a barrier metal layer pattern and an anti-nucleation layer are formed in the same manner as the first embodiment, to thereby expose the barrier metal layer formed on the sidewalls and bottom of the recessed region. Also, like the first embodiment, an ohmic metal layer may be formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed, before forming the barrier metal layer, and the barrier metal layer may be annealed after forming the barrier metal layer. Then, the metal liner is selectively formed on a surface of the exposed barrier metal layer. Here, the metal liner may be a single metal liner or a double metal liner obtained by sequentially forming first and second metal liners. It is preferable that the single metal liner is a metal layer formed of one selected from the group consisting of Cu, Al, Ag, Au, W, Mo and Ta. Also, the single metal liner may be a metal alloy layer containing one selected from the group consisting of Al, Au, Ag, W, Mo and Ta, and at least one selected from the group consisting of Cu, Si, Ge, Ti and Mg. It is preferable that the first and second metal liners of the double metal liner are a copper liner and an aluminum liner, respectively. The copper liner is formed through a selective MOCVD process using a precursor containing Cu, e.g. Cu+1(hfac)TMVS, as a metal source and the aluminum liner is formed through a selective MOCVD using a precursor containing Al as a metal source. Here, the copper liner and the aluminum liner are formed at temperature ranges corresponding to surface reaction limited regions of Cu and Al, respectively. Preferably, the precursor containing Al is one selected from the group consisting of tri-methyl aluminum, tri-ethyl aluminum, tri-iso butyl aluminum, di-methyl aluminum hydride, di-methyl ethyl amine alane, and tri-tertiary butyl aluminum.
Subsequently, a metal layer, e.g. an aluminum layer, a W layer, a Cu layer or an Al alloy layer, is formed on the resultant structure where the metal liner is formed, through a combination of CVD and sputtering process. Then, the metal layer is reflowed at 350xcx9c500xc2x0 C. to form a planarized metal layer for completely filling the region surrounded by the metal liner. At this time, the planarized metal layer is changed to a metal alloy layer in which the metal liner, e.g. the Cu liner and the metal layer are mixed during the reflow process. Accordingly, the reliability of the metal interconnection, i.e. an electromigration characteristic, may be improved.
According to the present invention, the anti-nucleation layer is selectively formed only on the barrier metal layer formed on the non-recessed region, thereby selectively forming the metal plug or the metal liner in the recessed region and further form the metal interconnection for completely filling a contact hole and a groove having a high aspect ratio.