As the switching speed (edge rates) and the number of input/outputs (I/O) of an integrated circuit (IC) assembly increase, the number of outputs that can switch synchronously (simultaneously in the same direction) also increase. An IC assembly can include one or more IC die and discrete components in and/or on an IC package. This results in switching currents in the power and ground paths with larger peak magnitudes and rates of change (di/dt). These large switching current peaks and rates of change generate voltages across the series resistance (V=R*i) and inductance (V=Ldi/dt) of the power and ground paths between the IC die inside the IC package and its host printed wiring board (PWB). These power and ground paths may include bond wire, trace, via and lead paths. The voltages developed across these power and ground paths leads to fluctuations in the power and ground voltages at the IC die relative to those of its host PWB, commonly referred to as rail bounce. As operating voltages decrease, rail bounce tolerance also decreases.
To reduce IC rail bounce in common IC assemblies, interfacial power and ground attach pads are added to the bottom of the IC assembly and bypass capacitor attach pads are added to the top of the IC assembly. When soldered to a mating attach pad on PWB, a single interfacial path can have a much lower series resistance and inductance than multiple parallel peripheral lead paths.
The adhesive force that causes liquid solder to spread across a metal surface is commonly referred to as whetting. The cohesive force that causes liquid solder to pull into a shape with minimum surface area (e.g. a sphere) is commonly referred to as surface tension. The combined effect of adhesive and cohesive forces will cause liquid solder to flow into a dome shape (a portion of a sphere) on a single circular pad. When identical interfacial pads are soldered together, the combined effect of adhesive and cohesive forces tends to pull these pads into alignment to form a vertical solder column. The solder column height is defined by the solder volume and the pad area.
IC package manufacturing and assembly tolerances (e.g. location of top IC assembly lead frame attach pads relative to bottom PWB interfacial attach pads) together with IC/PWB assembly tolerances (e.g. forming and shearing of peripheral leads and part placement) can buildup to cause variations in the PWB interface of an IC/PWB assembly. These include variations in the gap between the IC assembly interfacial attach pads and the seating plane of formed and sheared peripheral leads. These variations also include variations in the positions of one or more PWB interfacial attach pads relative to the formed and sheared peripheral leads. The PWB footprint is designed around the nominal positions of the IC assembly interfacial attach pad and formed and sheared peripheral leads. These variations due to manufacturing and assembly tolerances can cause various negative effects on the IC/PWB assembly processes and on the performance and reliability of IC/PWB assemblies. To better understand the present invention further background of the problems caused by manufacturing and assembly tolerances are described in relation to FIGS. 1A-1C.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system and method to alleviate the adverse effects of variations in package manufacturing tolerances and assembly tolerances.