1. Technical Field
The disclosure relates to an electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device.
2. Description of Related Art
In recent years, with the rapid development of semiconductor process and the increase in the complexity of IC design and the demand to circuit performance, the integration of 3D IC has been developed so that the lengths of connecting wires and accordingly the RC delay can be reduced and circuit performance can be improved. Besides, different layers in the 3D IC can be fabricated through different techniques and then stacked together, so that the fabrication cost of the IC can be reduced.
Different chips are usually connected by a through-silicon via (TSV). This is a new technique in the 3D IC technology, wherein a vertical electrical connection completely passes through the chips or wafers to connect the same. Unlike the conventional IC packaging/bonding techniques and the conventional stacking technique by using bumps, this new TSV technique can maximize the stacked density of chips in 3 directions and minimize the size of the IC, and meanwhile, this technique can also increase the speed and reduce the signal delay and power consumption of the IC. Thereby, the TSV technique has become one of the most focused techniques in today's 3D IC technology.
However, because a 3D IC is composed of stacked chips, each chip has different fabrication technique and power supply, and these chips are connected through a TSV device, when the TSV device receives a high-voltage electrostatic or noise (for example, the electrostatic produced by a human-body model (HBM), a machine model (MM), a charged-device model (CDM), or a field-induced model (FIM)), the electrostatic can run to all the stacked chips through the TSV device, and thus the 3D IC or the TSV device may be damaged.