1. Field of the Invention
The present invention relates to strained semiconductor devices that incorporate strained active layers. The invention also relates to methods of making strained semiconductor devices using a sacrificial stressor layer.
2. Description of the Related Art
Strained silicon is widely viewed as an important technology for obtaining desired advancements in integrated circuit performance. Mobility enhancement results from a combination of reduced effective carrier mass and reduced intervalley (phonon) scattering. For MOS field effect transistors (MOSFETs) fabricated on conventional {100} oriented Si substrates with conduction primarily along orthogonal <110> crystal axes, n-channel MOSFETs achieve improved performance with induced biaxial tensile stress in the top silicon layer along both the width and length axes of the active area, p-channel MOSFETs exhibit improved performance with induced uniaxial tensile stress in the top silicon layer along the width axis only (transverse tensile stress). p-channel MOSFETs also exhibit improved performance with induced uniaxial compressive stress in the top silicon layer along the length axis only (longitudinal compressive stress). Compressive stress can be provided selectively in a silicon surface layer, for example, by using recessed selective epitaxial SiGe stressors in the source and drain regions of a MOSFET to induce a desired compressive stress along the length axis (longitudinal).
Strained silicon is conventionally obtained by first growing a thick layer of silicon germanium alloy (SiGe) on a silicon substrate. The SiGe layer is grown to a sufficient thickness that the SiGe layer is relaxed to an unstrained condition at its surface. The in-plane lattice parameter of the SiGe surface is similar to that of a bulk crystal of SiGe of the same composition. SiGe alloys have larger lattice parameters than silicon. Hence the relaxed surface of the SiGe layer provides an in-plane lattice parameter larger than that of silicon. A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the SiGe layer. The thin epitaxial layer of silicon assumes the larger in-plane lattice parameter of the SiGe and grows in a strained state with bonds in the crystal lattice elongated in the growth plane. This approach, sometimes known as substrate-strained silicon or “virtual substrate” technology, grows a thin pseudomorphic layer of silicon on the relaxed surface of a SiGe layer.
So long as the strained silicon layer does not exceed a “critical thickness” for strain relaxation and some care is taken, the tensile strain is maintained in the strained silicon layer throughout the various implantation and thermal processing steps typical of CMOS manufacturing.
The use of a relaxed SiGe layer as a “virtual substrate” to strain a subsequently deposited epitaxial silicon layer inevitably requires acceptance of a very high dislocation density in the SiGe layer because the SiGe relaxation mechanism is plastic in nature. In other words, relaxation in the SiGe layer occurs through the generation of strain-relieving misfit dislocations. A SiGe layer thinner than the critical thickness on a silicon substrate is not relaxed and exhibits few misfit dislocations. If the SiGe layer is thicker than the critical thickness, the strained lattice undergoes plastic deformation and the stress is relieved by the nucleation and propagation of misfit dislocations. Some fraction of misfit dislocations give rise to threading dislocations (at least 104-105 cm−2) which propagate through the overlying strained silicon layer. Threading dislocations represent extended defects and give rise to multiple undesirable consequences in MOSFETs including source/drain junction leakage, reduction of channel mobility, variability of threshold voltage and enhanced diffusion paths leading to potential drain-to-source shorting in short-channel MOSFETs.