A 3-dimensional stack package of a packaging technology of a semiconductor integrated circuit includes a plurality of chips, which are stacked, having a same memory storage, and is normally referred to as a stack chip package.
A technology of the chip stack package has advantages to improve a performance of a chip package, reduce a manufacturing cost and be easy of a mass productions by stacking the plurality of chips using a simple manufacturing process. The technology of the chip stack package has disadvantages to be short of a line distribution for an electrical coupling of the chip stack package according as the number or the size of the plurality of chips, which are stacked, increase.
In other words, since a conventional chip stack package is manufactured to couple a bonding pad of each chip to a conductive circuit pattern of a substrate using a wire for an electrical coupling to between the bonding pad of each chip and the conductive circuit pattern of the substrate under a circumference where a plurality of chips are stacked in a chip stack region of the substrate, the conventional chip stack package needs an additional space for a wire bonding within a chip package and a conductive circuit pattern of the substrate to which a wire is coupled, and has disadvantages to increase a size of the chip package.
In order to consider these points, a structure using a TSV as an example of a stacked package has been developed. In recent, a method for forming a through-hole electrode composed of a conductive material within a semiconductor chip and electrically coupling semiconductor chips through the through-hole electrode has been used.
The TSV is formed through a via-first process, a via-middle process and a via-last process according to a forming time of the via-hole.
FIGS. 1A to 1C are cross sectional views illustrating forming process of a conventional TSV.
Referring to FIGS. 1A to 1C, a trench is formed in a silicon wafer 110 using an RIE (reactive ion etching) process or a laser drilling process (a).
Then, an isolation film including an insulation layer, a diffusion prevention layer and a seed layer is grown on a surface of the silicon wafer 110 (b). The TSV is formed by filling a conductive material 130 in the trench using an electroplating process, and performing a back-grinding process, a CMP (chemical-mechanic polishing) process, a thin film process and a stacking process (c).
A tungsten (W), a copper (Cu), a poly (Poly) and an aluminum (Al) are used as the conductive material.
In a TSV forming process as described above, an electrical isolation between the TSV and a silicon (Si) substrate is worked as an important factor. Herein, it is one of very difficult processes to deeply form and isolate the trench in the silicon (Si) substrate and fill the conductive material.
That is, in case that an etch is performed on the surface of the silicon substrate at a predetermined oblique angle or a vertical angle, it is very difficult to oxide a side wall of the via-hole.
A leak may be occurred when a thickness of a target region of an oxidation is uneven or a thin. Moreover, in case that the TSV including a conductive material, an oxidation layer and a silicon operates as a MOS (Metal Oxide silicon), as a capacitance increases, an insertion loss may increase.
Especially, in case of an aspect ratio is large, it is more difficult to insulate a side wall of the TSV.