In most computer systems, communications between different components is typically provided by a bus. The bus architecture is designed to be well established and portable such that it can be utilized in multiple configurations without excessive additional development expenses when designing for derivative products. In addition a bus is designed to perform high-speed communication processing to support an increase in frequency of a processor's clock.
FIG. 1 shows an exemplary block diagram of a typical bus architecture of a bus 100 operative within a computer system. The typical bus architecture of a computer system carries data and control flows. The bus 100 is a physical implementation of shared connections between all components within a computer system for the purpose of inter-communication. The communication is defined by, in most cases, a strict bus protocol. The bus protocol regulates the inter-communication between all components attached to bus 100. The bus 100 typically consists of an arbitration unit 110, used to determine which one of the attached components to the bus 100 should control the operations on the bus at a selected time. Arbitration unit 110 assigns the ownership of bus 100 for any given operation. The bus 100 also includes a management unit 120 for providing higher-level functions associated with system operations such as queue management and bus monitoring for error detections. Functional components are attached to bus 100 through respective interface units 140-1 to 140-N. To the extent that reference is made to the interface units without regard to a specific one thereof, such interface device(s) will be referenced as 140. Thus, each interface unit 140 is capable of generating control signals and transferring data across bus 100. The interface units 140 may interface with components, such as processors, controllers (e.g., disk controllers), and so on. Examples of buses employing such a bus architecture are a peripheral component interconnect (PCI) bus, a small computer systems interface (SCSI) bus, and the like. Other examples of similar bus architectures may be found in U.S. Pat. Nos. 5,001,625, 5,796,964, and 6,314,484, each of which is incorporated herein by reference for their useful background descriptions of the state of the art heretofore.
Another type of bus architecture disclosed in the related art is mainly utilized in application specific integrated circuits (ASICs). This type of bus architecture is also referred to as an “internal bus”. Typically, an ASIC includes one or more core processors, one or more memory units, and other functional modules, all integrated on a single semiconductor chip. Having the modules on the same chip allows data to be easily and quickly transferred between the various modules. To provide high speed data transfers on a chip, specialized buses are designed specifically for this purpose. One example for such specialized bus is the advanced high-performance bus (AHB), developed by ARM™ Ltd. The AHB operates in accordance with the advanced microcontroller bus architecture (AMBA) protocol and provides high-speed data transfers between various components on a chip. Another example is the advanced peripheral bus (APB), which provides the basic peripheral macro-cell communication infrastructure as a secondary bus from the higher bandwidth pipelined main system bus. The APB is designed to reduce interface complexity for the support of peripheral functions. A detailed description of the AHB and APB architectures may be found in U.S. Pat. Nos. 6,442,642, 6,810,460, 6,633,944, and 6,857,037, each of which is incorporated herein by reference for its useful background description of the state of the art heretofore. A limitation of the AHB, APB in addition to other types of internal buses is their inability to support inter-connection and inter-communication between the various modules on an ASIC.
Therefore, in the view of the limitations of in the prior art, it would be advantageous to provide a high-speed internal bus architecture that supports both inter-connection and inter-communication among various modules connected in an integrated circuit (IC).