Q:

CPU pipelining stages

I have read that in some pipelined architectures, memory access requires more than just one clock cycle. In that case how does processor handles the next instruction if the next instruction tries to access something the previous memory instruction has yet to write to its register files?

A:

There are many ways this kind of situation be handled.

Clever compilers

If you are are writing the contents of, lets say register 5 to the memory location 0x12345, and the next instruction is reading from the memory location 0x12345 and the variable allocated at memory location 0x12345 is not "volatile", compiler will optimize your code so that the next instruction will use the contents of register 5, instead of reading data from the memory.

Instruction reordering

Ordering of the instructions are changed so that the next instruction is pushed down, as far as required without compromising the outcome of the program. This way, more non-dependent instruction can be executed until the memory write is complete.

Multiple threads

When the scheduler detects that there is a read after write dependency, it can pick another thread for thread for the IF stage. That way, the current thread will stay inactive until the memory write is complete. Once completed it becomes active again, and will get picked up by the scheduler when a similar situation arises for the current thread. 

Bubbles

And of course, you can have many bubbles in the pipeline, until the write is complete :-). BTW, this is a bad idea.

