Over the years, developments and improvements in semiconductor performance have been achieved by focusing on a wide range of disciplines. Significant semiconductor improvements have resulted, for example, from device miniaturization, while others have been realized by creating multifunction devices on a single semiconductor chip or die.
Historically, semiconductor devices can be broadly divided into two categories: data processing (logic) devices and data storage (memory) devices. Devices that perform these two different functions have customarily been located on their own separate physical devices. However, with increasing miniaturization and complexity, these functions are increasingly being located together on the same semiconductor chip or die. Memory cells, for example, will typically be located in one region (a “core” region), but will also be provided with surrounding supporting devices in outer “periphery” regions. The periphery regions contain functions that support the memory cells (functions such as address decoders, read/write buffers, and sense amplifiers) that require different manufacturing procedures from those required for the core regions.
The creation of many semiconductor devices starts with growing a first layer of gate oxide over the surface of the silicon wafer where the semiconductor device is to be located. The gate oxide is a thin layer that allows better adhesion between the overlying layers (to be applied later) and the underlying silicon. The first layer of gate oxide also acts as a stress relaxation layer during manufacturing of the semiconductor device.
Device performance is highly dependent on the thickness of the first layer of gate oxide. Modern devices combine field effect transistor (“FET”) devices with other logic devices on the same semiconductor die. The differing functions provided by the various individual semiconductors in the core and in the periphery regions require gate oxide layers of different thicknesses. Typically, logic function devices require the use of a thin layer of gate oxide to enhance overall device performance, while a thicker gate oxide is required for the access transistors of dynamic random access memory (“DRAM”) cells. As an example, when the gate voltage on an FET access transistor for the memory cells is 7 volts, the corresponding gate voltage on FET's of the logic portion of the circuit will be only about 3.3 volts.
In flash memory electrically-erasable programmable and read-only memory (“EEPROM”) devices, the gate oxide (also called a tunnel oxide in this type of device) is located under the floating gates of the flash memory cells. Data retention requirements of EEPROM devices require that these layers of tunnel oxide have at least a fairly large thickness, a requirement that may conflict with the oxide layer thickness requirements of periphery devices within the overall EEPROM device die. That is, for non-volatile memory devices, the data entry and erase transistors typically require high data retention, which also means relatively thick layers of gate oxide. But the surrounding periphery logic functions require high operating speed, which means relatively thin layers of gate oxide.
Thus, high voltage devices such as program and erase transistors require a relatively thick layer of gate oxide to protect the device against high voltage breakdown. However, other devices that are designed for speed require a thin layer of oxide. These differing requirements gain further importance as devices get smaller and smaller (with device features in the micron and sub-micron range). Thus, the layers of gate oxide that are required for these various devices need to be of different thickness levels. As time passes and circuits become smaller and ever more complex, it is becoming increasingly important to be able to fabricate all these devices on the same semiconductor die regardless of such gate oxide thickness differences.
Non-volatile memory devices are currently in widespread and increasing use in electronic products. Non-volatile memory devices retain stored information after the electrical power is terminated. In addition to EEPROM devices, non-volatile memory devices include read-only-memory (“ROM”), programmable-read-only memory (“PROM”), and erasable-programmable-read-only memory (“EPROM”) devices. EEPROM devices differ from other non-volatile memory devices in that EEPROM devices can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that the memory cells can be programmed and erased electrically. However, flash EEPROM devices also enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, and reducing cell dimensions. In this regard, one important dielectric material for the fabrication of the EEPROM devices is an oxide-nitride-oxide (“ONO”) structure. This structure is three dielectric materials layered on one another, such as silicon oxide (“SiO2”), silicon nitride (“SiN”), and silicon oxide. During programming, electrical charge is transferred to the silicon nitride layer in the ONO structure, where it is retained even after the device has been turned off. A flash memory cell that utilizes the ONO structure is referred to as a Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”) type cell.
An advantage of SONOS flash memory transistors is that they may have a lower programming voltage than some other nonvolatile memory devices. As an example, a SONOS transistor may be programmed and/or erased with a voltage of about half the voltage of other nonvolatile memory technology. Such a lower programming voltage can result in a nonvolatile storage circuit that may be more easily utilized with existing manufacturing processes.
Although there are many advantages with SONOS type memory devices, there are some disadvantages as well. In some instances, it is difficult to form the charge trapping layer over a silicon substrate or gate oxide layer with precision, uniformity, high quality (no defects), and without contamination. This presents challenges for precisely and uniformly forming ONO sub-layers having predetermined thicknesses. Thus, important factors toward achieving high performance SONOS cells include the thickness, quality, and cleanliness of the ONO structure, which cannot be sufficiently guaranteed with many known fabrication techniques.
Another disadvantage with SONOS type memory devices is the high temperature process that is needed to make the ONO structures. This high heat can cause undesirable distortion of prior structures already formed on the semiconductor die.
There is thus an unmet need for more advanced and economical methods for producing SONOS-type nonvolatile memory devices having improved material purity (leading to improved poly-to-source/drain isolation), little or no heat-induced distortion (such as excessive diffusion of implants), and multiple gate oxide thicknesses on a single chip for accommodating core and periphery devices that are formed at the same time and with the same processes. Desirably, these more advanced methods will use existing processing techniques, thus avoiding additional complexity and expense in the wafer fabrication process.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.