1. Field of the Invention
The present invention is broadly directed towards novel contact planarization methods which utilize thermoplastic, thermally curable, and photo-curable planarizing materials for manufacturing microelectronic, photonics, optoelectronic, optical, microelectromechanical system (MEMS), bio-chip, and sensor devices as well as other processes in which lithographic processing is required.
2. Description of the Prior Art
The market demand for microelectronic devices to have smaller physical profiles has driven the need for building smaller microstructures into the devices. In addition, such devices are expected to be more energy efficient and feature more powerful functions while being more cost-effective to build. To achieve these objectives, the feature sizes found on integrated circuit (IC) chips must become increasingly smaller. Therefore, multiple layers of interconnect having smaller microstructures such as lines, trenches, vias, and holes must be patterned onto the device substrates. Currently, photolithography is used to construct these microstructures on the device substrates. This process is normally accomplished with a single photoresist layer. Emerging lithography technologies, such as imprint lithography, nano-imprint lithography, hot embossing lithography, and stamping pattern transfer, have been proposed. These technologies use a patterned mold to transfer patterns onto the substrate surface instead of relying on photolithographic patterning.
To build smaller microstructures, shorter wavelengths of exposure light (e.g., from 248 nm to 193 nm to 157 nm to extreme ultraviolet (EUV) and beyond) have been used in the photolithography process. As a result, the depth of focus (DOF) becomes more narrow, thus leading to a smaller photolithographic processing latitude. Therefore, the substrate surface topography and the thickness and thickness uniformity of the coating(s) applied to the surface to be patterned become critical factors in the fabrication of microstructures having the desired feature sizes. As the wavelength of the exposure light gets shorter, the tolerance of the substrate surface topography becomes more narrow. In addition, the film to be patterned needs to be sufficiently thin to be within the DOF of the photolithography process, assuming that the substrate surface is perfectly planar. As more layers of interconnect are built, the substrate surface topography becomes so severe that it is beyond the limits of what the DOF of the lithography process will allow. Therefore, fine feature sizes cannot be patterned on the substrate surface.
Another challenge posed by surface topography is that a film coating applied over the surface tends to contour to the underlying topography with a non-uniform thickness. That is, the topography of the underlying surface is somewhat reproduced in a slightly less severe manner. The film coating in the recessed areas tends to be thicker than in other areas. The non-uniformity of film thickness, along with the surface topology, create problems by causing under- and overexposed areas and by causing areas that are out of focus (that is, out of the DOF range) in the photolithography process. Therefore, the required critical dimension (CD) control of the microstructures in the photolithographic process cannot be achieved. These factors prohibit achieving the desired feature sizes of the microstructures.
As the DOF narrows, the single-layer photoresist photolithography process has very limited capabilities for meeting patterning requirements due to the topography of the substrate surface and to the thickness and thickness uniformity of the photoresist. Therefore, multi-layer coating processes have been proposed and pursued. A thick layer of planarization material is first coated onto the substrate surface to provide a more planar surface onto which additional coating layers can be applied. The topmost layer undergoes the photolithographic patterning. The patterned structures on the topmost layer are then transferred downward to the substrate, through all the layers applied onto the substrate, with appropriate processes such as anisotropic plasma etching. This technique is referred to as a top-surface imaging process. This top-surface imaging process could involve applying two, three, or even more layers of coatings onto the substrate surface before the photosensitive topmost layer is applied and patterned.
FIGS. 1(a)-(c) depict a prior art process. As shown in FIG. 1(a), as more layers of interconnect are constructed onto the surface of a device substrate 10, the topography 12 produced by the layers becomes unacceptable. Under these circumstances, a single-layer photoresist process is no longer suitable for patterning the desired structures on such a topographic surface. Therefore, a bilayer process has been pursued to improve the lithography process window. This bilayer process involves spin coating a planarization material 14 onto the surface to fill in the recessed areas, such as vias and trenches 16, followed by a thermal reflow process. This planarization material may be an anti-reflective coating, a photoresist, or a similar material. However, the spin-coated layer tends to contour to the surface topology of the underlying layer (see FIG. 1(b)). The thermal gravity reflow process allows coated material to flow into the recessed areas (vias and trenches 16) to somewhat reduce the topography of the surface, as shown in FIG. 1(b). This coated material can be thermally crosslinked during or after the reflow process if necessary. This provides a more planar surface onto which additional layers may be applied. A top layer 18, which is typically a photoresist, is applied on top of the planarization layer as shown in FIG. 1(c). This photoresist layer is patterned during the photolithography process. Therefore, the film thickness, thickness uniformity, and surface topography are critical factors affecting the performance of this top imaging layer. Once the images are patterned into the top layer 18, the substrate surface undergoes a plasma etch process. The images are transferred to the bottom layer, and all the way to the substrate if necessary, by etching the unprotected open areas in the photoresist layer. Because the thickness of the bottom planarization material 14 is not uniform as it coats the topographic substrate surface, and could be thicker than that of the top layer 18, the plasma etch rate of each layer is critical. Preferably the top layer 18 will have a substantially lower plasma etch rate than the bottom layers. The top layer 18 can then act as an etch mask during the pattern transferring process, that is, the plasma etch process. Therefore, the plasma etch selectivities of the bottom and top layers are critical for transferring the patterned imaged from the top layer to the bottom layer and to the underlying substrate.
To ease the etch selectivity requirement and prevent the interaction between the bottom and photoresist layers, it has been proposed that a very thin hardmask layer be applied between the bottom layer and the photoresist layer. This hardmask layer would have the required plasma etch properties and would serve to separate the bottom and photoresist layers. This new process has been referred as a trilayer process. The hardmask layer does not improve the surface planarity of the planarization layer because the hardmask is very thin and conforms to the planarization surface. Therefore, it does not improve the photolithography process latitude so a planarizing bottom layer is still needed for the trilayer process. A specific plasma etch process is needed to transfer the pattern to the hardmask layer, and an additional plasma etch process is used to transfer the pattern further to the bottom planarization layer. In both bilayer and trilayer processes, a planarizing bottom layer is needed to provide a planar surface onto which additional coating layers may be applied.
The dual damascene (DD) process, a widely used technology in advanced IC manufacturing processes, enables the deposition of two metal layers in one metal deposition step. The dielectric layer(s) is etched once or twice (or even more times, depending on the scheme of the DD process) to construct two layers of patterns in the dielectric layer(s). If more than two dielectric layers are involved in a DD process application, the dielectric layers might be separated by a thin hardmask layer that acts as an etch-stop barrier layer. Once the DD patterns are formed, a metal interconnect material is then deposited into the patterns. In one DD process approach, a layer of dielectric material (or photoresist) is spin coated onto the surface of a substrate 20 (FIGS. 2(a)-(c)). Photolithography is used to create microstructures (vias/trenches 22) having the required aspect ratios with different feature density areas in the layer, as shown in FIG. 2(a). The substrate 20 has an area 24 with isolated structures as well as an area 26 with densely located features. Thus, the feature density varies within the die and across the substrate surface. The topography is as profound as it can be when the first planarization layer 28 is coated onto this patterned surface because feature density plays a critical role in determining the final film thickness as shown in FIG. 2(b). The film thickness on top of the structure is much thinner in area 26 over densely located features than the film thickness over area 24 containing isolated structures. As a result, local planarization is achieved within an area having the same feature density. However, recessed areas occur as a result of the thinner film thickness over high feature density areas. In the worst cases, if the coated film is not thick enough, the high aspect ratio structures (such as vias and trenches) in the dense feature density areas may be only partially filled while the structures in less dense feature areas may be fully filled by the first planarization material layer 28. Therefore, global planarity is absent within the die and across the substrate surface.
A second layer 30 is then coated onto the planarization layer 28 that lacks global planarity. This second layer can be the photosensitive photoresist layer (for the bilayer process) or a thin hardmask material (for the trilayer process). As shown in FIG. 2(c), the second layer 30 tends to contour the topography of the underlying layer 28, with the film layer being thicker over the area 26. One approach to minimize the top layer film thickness non-uniformity and improve the global planarity is to apply a fairly thick (as thick as several microns or even thicker) underlying planarization layer that will provide a better local and global surface planarity onto which additional layer(s) can be applied. The thick planarization layer results in a longer plasma etch time and requires a higher plasma etch selectivity. The plasma etch rate of the planarization layer needs to be much higher than that of the top-imaging layer. These qualities raise the concerns of throughput and materials compatibility with the process. Another approach is to have dummy structures built into the areas having lower feature density to provide less variation of feature density within the die and across the substrate surface to alleviate the feature density effect. Therefore, a better global planarity can be achieved on the planarization layer surface. However, with the use of dummy structures, the designs and circuitry layouts are more complicated. The approach may also increase the die size needed, which is not desirable.
As alternatives to the photolithography process, several emerging lithography technologies, such as imprint lithography, nano-imprint lithography, hot embossing lithography, stamping pattern transfer, etc. have been proposed and pursued in creating microstructures. Imprint lithography, nano-imprint lithography, and hot embossing lithography utilize a mold to imprint the patterns onto a substrate surface onto which a thin, flowable molding material is coated. These processes can be carried out at either ambient temperatures or elevated temperatures. When the mold surface makes contact with the molding material, the material is forced to flow, under the imprint or embossing processing conditions, and to conform to the patterned mold surface. The molded material is then hardened either by a photo or thermal means. The mold is separated from the hardened molded material. Negative patterns of the mold's patterns are transferred to the molded material. The patterned surface is plasma etched with adequate parameters and sequences to transfer the patterns to the underlying layer, if necessary. These lithography technologies do not rely on light exposure through the pattern-bearing photomask (or reticle) to transfer patterns to the photoresist layer. Therefore, DOF is not an issue. However, the coated flowable molding material needs to have a very uniform thickness with a nearly perfect global planarity across the substrate surface. It is reasoned that the mold is rigid and the structures to be transferred are very tiny. The mold surface needs to be kept perfectly parallel to the surface to be patterned. Any topography and thickness non-uniformity in the molding material layer have a high possibility of catastrophic impacts on the final patterns transferred to the substrate surface. A topographic surface will cause incomplete pattern transferring. A non-uniform molding material thickness will cause complexity during plasma etch. That is, thicker film areas will be under-etched while thinner areas will be over-etched. Therefore, a global planar substrate surface is needed onto which a uniform thickness and globally planar surface of a flowable molding material layer can be obtained for the pattern transferring process. A globally planar surface is needed for the stamping process as well when fine structures are stamped onto a device surface.