1. Field of the Invention
This invention relates to a complementary MOS data input-output (I/O) CMOS type input-output circuit, and more particularly to a CMOS data input-output circuit suitable for microprocessors.
2. Description of the Prior Art
CMOS input-output circuits are commonly used in CMOS microprocessors or CMOS microcomputers because they consume very little electrical power. Such CMOS input-output circuits include circuits capable of bidirectional transmission of information between an external circuit connected to an I/O port and an internal data bus.
The CMOS data input output circuit generally comprises a data output circuit which transmits information on a bit line of the internal data bus to an external circuit through the I/O port, and a data input circuit which transmits information from the external circuit to the bit line of the data bus through the I/O port.
An example of a conventional data input-output circuit including a CMOS output buffer is described in "MICRO-CONTROLLER HANDBOOK 1983 (INTEL, 1983 ed., Pages 10-1 and 10-2).
With such conventional input-output circuits, however, it is difficult to directly connect the I/O port to an external circuit the output logic state of an external circuit must be the same as the logic state of the I/O port, before these circuits are powered down. In a power down mode, these CMOS data input-output circuits should electrically isolate their internal data bus from the I/O port in order to avoid their effects of the external circuits attached thereto.
However, in this case, there is a disadvantage in that when the I/O port becomes open or high impedance, the data input circuit portion of the data I/O circuit consumes electrical power in spite of the power-down mode.
To avoid this power consumption problem, it is necessary to connect an external pull-up or pull-down resistor to the I/O port to fix the I/O port at an H or L logic level. However, the external resistor is troublesome in that it requires handling and occupies additional mounting space.
As described above, in the conventional CMOS data I/O circuit, it has been difficult to simultaneously satisfy three requirements: no special means for interfacing an I/O port and an external circuit; low operational power consumption in a power-down mode; elimination of external pull-up or pull-down resistors. It has been strongly desired to obtain an improved CMOS data I/O circuit which can solve the contradictionary problems.