The present invention relates generally to integrated circuits, and more particularly, to a system for synchronizing functional resets in an integrated circuit.
Integrated circuits (ICs) such as System-on-a-Chip (SoC) type circuits, include various functional modules for performing different tasks. Examples of functional modules include processors, control logic, memories, system buses, and so forth. These modules usually are driven by one or more clock signals and depending on the system requirements, different functional modules may require different clock signals (having different frequencies); e.g., an integrated circuit may include one set of functional circuits that operates in a first clock domain and another set of functional circuits that operates in a second clock domain.
Often times, flip-flops in a first clock domain may generate a reset signal that is required to reset flip-flops in the second clock domain. An example of such an IC 102 is shown in FIG. 1. The IC 102 includes multiple clock domains including first and second clock domains 104a and 104b that operate on first and second clock signals, respectively. Each clock domain 104 includes a plurality of functional circuits such as flip-flops 106. For example, the first clock domain 104a includes a first chain of flip-flops of which the last flip-flop 106a is shown and the second clock domain includes a second chain of flip-flops of which first and last, i.e., receive and capture flip-flops 106b and 106c are shown. The path between the receive and capture flip-flops 106b and 106c is represented by a combinational path 108. In this example, the first chain of flip-flops receives the first clock signal and the second chain of flip-flops receives the second clock signal. The first chain of flip-flops generates a functional reset signal that is used to reset the second chain of flip-flops. To enable the reset mechanism, an output of the flip-flop 106a is connected to a NOT gate 110 and an output of the NOT gate 110 is input to an AND gate 112. An output of the AND gate 112 then is input to a reset terminal of the receive flip-flop 106b. A second input of the AND gate 112 and a reset terminal of the capture flip-flop 106c both receive a power-on-reset (POR) signal generated internally in the IC 102. The POR signal goes active (logic high) unless a system reset is required.
When the first chain of flip-flops generates a functional reset signal (that appears at the output of the flip-flop 106a), the NOT gate 110 inverts the reset signal to provide a logic low signal, which is received by the AND gate 112. The output of the AND gate 112 is a logic low signal, which resets the receive flip-flop 106b. As the first and second clock signals are asynchronous, the receive flip-flop 106b generates a logic low signal asynchronous to the second clock signal, which leads to timing violations at the capture flip-flop 106c through the combinational path 108. These timing violations can lead to erroneous operation of the IC 102.
Therefore, there is a need for a system that synchronizes a functional reset across multiple clock domains of an IC without introducing any timing violations, and that overcomes the above-mentioned limitations of existing IC.