1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus. More particularly, the embodiment described herein relates to a clock buffer and a semiconductor memory apparatus using the same.
2. Related Art
A semiconductor memory apparatus, particularly, a dynamic random access memory (DRAM) generates a delay clock synchronized with an external clock and operates in synchronization with the delay clock. The delay clock is input to a clock buffer provided in the DRAM, and the clock buffer transfers the delay clock to circuits, which operate in synchronization with the delay clock, in response to an enable signal that activates the clock buffer.
In general, in order to reduce power consumption, the DRAM may inactivate the clock buffer and then operate the clock buffer only when a signal representing an output of the delay clock, that is, the enable signal is activated.
FIG. 1 is a circuit diagram showing a configuration of a conventional clock buffer. The conventional clock buffer includes first and second AND gates AND1 and AND2. The first AND gate AND1 receives a first clock ‘rclk’ and a clock enable signal ‘clken’ to generate a first internal clock ‘rclk_d’. The second AND gate AND2 receives a second clock ‘fclk’ and the clock enable signal ‘clken’ to generate a second internal clock ‘fclk_d’. The first and second clocks ‘rclk’ and ‘fclk’ are delay clocks synchronized with an external clock, and refer to a pair of clocks having a phase difference of 180° therebetween.
FIGS. 2 and 3 are timing charts showing an operation of the conventional clock buffer.
FIG. 2 shows a case in which the clock enable signal ‘clken’ is enabled when the first clock ‘rclk’ is at a high level and the second clock ‘fclk’ is at a low level. In such a case, the first clock ‘rclk’ is primarily output as the first internal clock ‘rclk_d’ and then the second clock ‘fclk’ is output as the second internal clock ‘fclk_d’.
FIG. 3 shows a case in which the clock enable signal ‘clken’ is enabled when the first clock ‘rclk’ is at a low level and the second clock ‘fclk’ is at a high level. In such a case, the second clock ‘fclk’ is primarily output as the second internal clock ‘fclk_d’ and then the first clock ‘rclk’ is output as the first internal clock ‘rclk_d’.
As described above, the sequence of the outputted clock may vary depending on the enable timing point of the clock enable signal ‘clken’. When operating a semiconductor memory apparatus by primarily outputting the first clock ‘rclk’ as the first internal clock ‘rclk_d’, the semiconductor memory apparatus can normally operate in the case of FIG. 2. However, in the case of FIG. 3, if the second clock ‘fclk’ is primarily output as the second internal clock ‘fclk_d’, the semiconductor memory apparatus may abnormally operate.