Field of the Invention
The present invention is directed in general to electrical circuitry for data conversion. In one aspect, the present invention relates generally to analog-to-digital converter (ADC) systems.
Description of the Related Art
In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is a system that converts an analog signal into a digital signal. A successive approximation register (SAR) ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search. During this binary search, the ADC makes a decision for each bit of resolution, thus converging upon a digital output for each conversion. SAR ADCs can be designed as fully synchronous, using a fixed time for each bit decision based on an input clock, or asynchronous, having variable time for each bit decision based on a self-timed comparator delay. As will be appreciated, there are advantages and disadvantages associated with synchronous and asynchronous SAR ADCs. For example, fully synchronous SAR ADCs typically require an over-sampling clock that is a multiple of the ADC sample frequency, and are designed on the basis of a fixed DAC settling time and fixed compare times, in which case the clock frequency must be chosen to meet the worst case combination of those delays, thereby reducing the overall speed of data conversion operations. And with fully synchronous SAR ADCs, it is also difficult to optimize for compare vs DAC settling time without duty cycle adjustments or higher frequency clocks. In contrast, fully asynchronous SAR ADCs are much faster and do not require a fast input clock, but there are design complexities and performance drawbacks for asynchronous ADCs which typically require that an analog delay be generated in order to match the worst case DAC settling time. Designing this delay adds power and complexity and likely requires some trimming/calibration. In addition, the difficulty in knowing the end of the conversion time with asynchronous converters typically requires that the input clock rate be chosen for worst case approximation times, thereby sacrificing some of the speed performance advantages that would otherwise accrue for a fully asynchronous SAR ADC.
As seen from the foregoing, the existing SAR ADC solutions for quickly and efficiently performing analog-to-digital conversions are extremely difficult at a practical level by virtue of the difficulty balancing the design constraints for providing an efficient, low complexity SAR ADC with the performance demands for performing high speed analog-to-digital conversion. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.