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Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming progressively more important.
There are various stages in the life cycle of a device in which testing is important. For example, testing is important in the design of the device, in the manufacturing of the device, and in the operation of the device. At the design stage, testing is intended to verify the design of the device and to identify flaws in the design. Testing may be performed at the architectural level and RTL levels using high level languages or some for of hardware description language (HDL) to simulate the functionality of the device. Simulation testing may also be used to test the gate level design of the device. Testing during the manufacturing of the device may be performed to ensure that the timing, proper operation and performance of the device are as expected from the testing at the design stage. Because the size of features (e.g., transistors and other components) in modern integrated circuits is very small, it is very easy for defects to arise, so testing at this stage is very important. Finally, after the device is manufactured, it may be necessary to test the device to ensure that it continues to operate properly during normal usage.
Logic circuits in digital devices typically include many interconnected logic gates. The various logic gates may include, “AND” gates, “OR” gates, “NAND” gates, “NOR” gates, “NOT” gates, “XOR” gates, and various other types of gates. A logic circuit may receive data through multiple inputs, and may provide resulting output data through multiple outputs. The logic circuit is designed to take the inputs and, depending upon the particular state of the circuit, produce a corresponding predetermined output pattern is produced at the outputs of the circuit. If there is a defect in the logic circuit, then for at least one of the input patterns and corresponding circuit, the patterns produced at the outputs of the circuit will differ from the expected predetermined output patterns.
One way to test for defects in a logic circuit is to apply each possible input pattern at the inputs of the logic circuit, with each possible set of state values in the circuit, and to compare the observed output pattern with the expected output pattern. If there are only a small number of possible input patterns and state values, the cost of storing the input patterns, state information and expected output patterns and then performing deterministic testing of each possible input/state/output combination may be reasonable. If the number of possible input patterns and state values is high, however, the cost of deterministic testing of all the combinations is generally too high. An alternative method of testing that has a lower cost would therefore be desirable.
One alternative method of testing for defects in a logic circuit takes a non-deterministic approach. In this method, random input test patterns are applied to the inputs of the logic circuit, and the output patterns generated by the logic circuit are compared with the expected output patterns. Because this type of testing is not deterministic (i.e., it does not test each and every possible combination of inputs, states and outputs), it does not provide the simple result that the logic circuit either does or does not have any defects. Instead, it provides a level of confidence that the logic circuit does or does not have defects. The greater the number of inputs and states that are tested (i.e., whose outputs are compared to expected values), the higher the confidence level that any defects have been identified by the testing. The number of random test patterns that are needed to achieve a particular level of confidence that the logic circuit contains no defects depends on the design of the logic circuit.
In a variation on this type of testing, the random input test patterns may be weighted. Without weighting, the number of 1's in a random pattern is likely to be very nearly the same as the number of 0's. Weighting can be implemented in order to cause the generated random pattern to more 1's than 0's, or vice versa. For instance, it may be desirable to generate an input test pattern that has 30 percent 0's and 70 percent 1's. The weighted input test patterns are then input to the logic circuit, and the resulting observed output patterns are compared to the expected output patterns to determine whether there are defects in the logic circuit.
As digital devices (e.g., integrated circuits) have become more complex and more densely packed with logic gates and other electronic components, the need for effectively testing these devices has become more important. With respect to the testing of devices, and more particularly manufactured integrated circuits, one mechanism that is very useful is a built-in self test (BIST). This may also be referred to as a logic built-in self test (LBIST).
BIST and LBIST methodologies are generally considered part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies involve incorporating features into the actual designs of the circuits that are to be tested to facilitate testing of the circuits. BIST methodologies involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the functional portion of the circuitry.