1. Field of the Invention
The present invention relates to an I/O (Input/Output) protection circuit, and particularly to an I/O protection circuit in a semiconductor device provided with SOI (Silicon-on-Insulator) field-effect transistors.
2. Description of the Background Art
In an MOS device on a bulk silicon substrate, surge can be discharged to a substrate via a p-n junction. However, in an SOI device having MOS transistors and others formed on an insulating layer, surge cannot be discharged to a substrate, because the substrate is electrically isolated by an insulating layer. Particularly, in a thin-film SOI structure having a source region and a drain region which extend to a buried oxide film (insulating layer), it is necessary to discharge the surge laterally, because a vertical junction is not present. Therefore, the surge is discharged laterally through a power supply line or a ground line via a diode or an MOS transistor.
FIG. 17 is a circuit diagram showing an example of a conventional input protection circuit. Referring to FIG. 17, the input protection circuit is connected between an input terminal 30 and an internal circuit 31, and includes a rush resistor 36, an internal resistor 37, and diodes 38 and 39.
FIG. 18 is a circuit diagram showing an inverter which is a typical example of internal circuit 31. Referring to FIG. 18, the inverter includes a P-channel MOS transistor 44 and an N-channel MOS transistor 45. In this example, the protection circuit shown in FIG. 17 is connected to an input node 72 of an inverter so as to protect the inverter against a surge applied through input terminal 30.
The protection circuit may be connected to an output node 73 of the inverter. In this case, the protection circuit protects the inverter against a surge applied through output node 73, and therefore is called an output protection circuit. The input protection circuit and the output protection circuit are generally called an I/O circuit.
An I/O protection circuit shown in FIG. 17 will be described below. When a surge due to static electricity is applied through input terminal 30, rush resistor 36 first delays the surge and prevents rapid application thereof to diodes 38 and 39. The surge passed through rush resistor 36 is applied to a signal line 71. Further, the surge is rapidly discharged to power supply line 32 by diode 38 and to ground line 33 by diode 39. Here, internal resistor 37 does not flow the surge toward internal circuit 31, but flows the same toward diodes 38 and 39.
When a positive high voltage surge is applied, a p-n junction of diode 39 breaks down, and the surge is discharged to ground line 33. At the same time, diode 38 is biased forward, and the surge is discharged to power supply line 32. Meanwhile, when a negative high voltage surge is applied, a p-n junction of diode 38 breaks down, and the surge is discharged to ground line 32. At the same time, diode 39 is biased forward, and the surge is discharged to ground line 33. An ordinary input signal applied to input terminal 30 is sent to internal circuit 31 via signal line 71 as it is.
Although the I/O protection circuit has a surge resistance, i.e., a resistance against a surge as described above, the surge resistance generally decreases in accordance with reduction in size of elements. There is also such a tendency that reduction in size promotes employment of SOI structures. Therefore, the semiconductor device having the SOI structure requires an I/O protection circuit having a higher resistance against surge.