The present invention relates generally to semiconductor integrated circuits and, more particularly, to internal voltage generation circuits.
In general, a semiconductor memory device receives a power supply voltage VDD and a ground voltage VSS from an external device to generate internal voltages used in operation of internal circuits of the semiconductor memory device. The internal voltages for operating the internal circuits of the semiconductor memory device may include a core voltage VCORE supplied to a memory core region, a high voltage VPP used to drive or overdrive word lines or the like, and a back-bias voltage VBB applied to a bulk region (or a substrate) of NMOS transistors in the memory core region.
The core voltage VCORE may be a positive voltage which is less than the power supply voltage VDD supplied by the external device. Thus, the core voltage VCORE may be generated by reducing the power supply voltage VDD to a certain level. In contrast, the high voltage VPP may be greater than the power supply voltage VDD, and the back-bias voltage VBB may be a negative voltage which is less than the ground voltage VSS. Thus, charge pump circuits may be required to generate the high voltage VPP and the back-bias voltage VBB.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generation circuit of the prior art.
As illustrated in FIG. 1, the conventional internal voltage generation circuit is configured to include a comparator 1 and a driver 2.
The comparator 1 may compare a voltage level of a node ND10 between two resistors R1 and R2, which are serially connected to an output node having an internal voltage VINT, with a reference voltage VREF to generate a comparison signal COMP. The comparison signal COMP may be enabled to have a logic “low” level when the voltage level of the node ND10 is less than the reference voltage VREF.
The driver 2 may turn on a PMOS transistor P1 to pull up the internal voltage VINT to a power supply voltage VDD when the comparison signal COMP is enabled to have a logic “low” level. If the internal voltage VINT is pulled up, the level of the node ND10 may also be pulled up. Accordingly, the driver 2 may continuously pull up the internal voltage VINT until the level of the node ND10 is equal to the reference voltage VREF.
However, if the power supply voltage VDD applied to the driver 2 is less than a target level of the internal voltage VINT, it may be impossible to drive the internal voltage VINT to the target level over the power supply voltage VDD.