1. Technical Field
The present invention relates to methods of fabricating a dielectric layer and methods of fabricating a semiconductor device using the same, and more particularly, to methods of fabricating a lanthanum oxide layer, and methods of fabricating a MOSFET and a capacitor using the same.
2. Discussion of the Related Art
In a semiconductor memory device, a dielectric layer is used for various applications, and is generally used for a capacitor dielectric layer or a gate dielectric layer of a MOSFET. In order to operate a semiconductor device in a normal way, the gate dielectric layer or a capacitor dielectric layer should maintain an appropriate level of capacitance C. A capacitance C of a dielectric layer can be calculated by the formula C=ε*A/d (where C is the capacitance, ε is the dielectric constant, A is the area of a dielectric layer, and d is the thickness of a dielectric layer). That is, a capacitance of a dielectric layer is directly proportional to a dielectric constant and an area of a dielectric layer, and inversely proportional to a thickness thereof. A consequence of increasing the integration of a semiconductor memory device is that an area of a unit cell of the semiconductor memory device is reduced, and thus, an area of the gate dielectric layer or an area of the capacitor dielectric layer is also reduced. As a result, the capacitance of this element is also reduced. Therefore, various methods have been employed to compensate for a reduction of the capacitance due to a decrease of an area of the gate dielectric layer or of an area of the capacitor dielectric layer. Such methods may include a reduction of a thickness of the dielectric layer or use of a higher-k dielectric layer. However, the approach of reducing a thickness of the dielectric layer may lead to an undesirable increase in leakage current as the dielectric layer thickness is reduced. Therefore, it is generally necessary to employ a high-k dielectric layer in order to maintain an appropriate capacitance without an increase of a leakage current.
High-k dielectric layers such as an aluminum oxide layer (Al2O3) having a dielectric constant of about 9, a hafnium oxide layer (HfO2) having a dielectric constant of about 20, or a zirconium oxide layer (ZrO2) having a dielectric constant of about 25 can be used for the gate dielectric layer or for the capacitor dielectric layer Also, the high-k dielectric layers may include a tantalum oxide layer (Ta2O5) having a dielectric constant of about 20 to 60, and a titanium oxide layer (TiO2) having a dielectric constant of about 40. Further, it is also known to create a dielectric layer having an ultra high dielectric constant, for example using a BST layer having a dielectric constant of about 200 to 300, a PZT layer having a dielectric constant of about 2000 to 3000, or the like. However, even though a new dielectric layer may have a desirably high dielectric constant, such a dielectric layer may not be suitable for use in a semiconductor device. Therefore, whether or not to use one of the new dielectric layers having an ultrahigh dielectric constant property involves many considerations such as an adaptability with existing fabrication processes of a typical semiconductor device, a reliability, a productivity, or the like, which factors will be considered in greater detail below.
Some of the problems which may be caused when applying the high-k dielectric layers to a gate dielectric layer are as follows. First, use of a BST layer, a titanium oxide layer, a tantalum oxide layer, and the like may result in an increase of a leakage current, a degradation of a carrier mobility, and/or similar interface problems because interface characteristics can deteriorate due to a high reactivity of the high-k layers with a silicon substrate. On the other hand, in the case of using an aluminum oxide layer, the aluminum oxide layer has a relatively excellent thermal stability, but its use as a dielectric layer is limited due to its relatively low dielectric constant. Further, aluminum oxide has a disadvantage in that it creates a difficulty in controlling a threshold voltage due to a negative fixed charge. Furthermore, the use of a hafnium oxide layer or a zirconium oxide layer is also limited because such materials may be crystallized during an annealing step of subsequent semiconductor fabrication processes, thereby increasing a leakage current.
In addition to the above-described problems, efforts to apply the high-k and ultra high-k dielectric layers to the capacitor dielectric layer may cause further problems as follows. Even though the BST layer and the PZT layer have ultra high dielectric constants, such layers are difficult to form with a uniform composition on a lower electrode structure having a high aspect ratio. The use of a high-k tantalum oxide layer is also limited because of the tendency to cause a high leakage current when used with a lower electrode consisting of a polysilicon layer due to a low conduction band offset at the polysilicon layer interface. Further, the use of a zirconium oxide layer or a hafnium oxide layer may cause a rapid increase in a leakage current during a subsequent annealing process step because these materials have relatively low crystallization temperatures. An aluminum oxide layer has the advantages of a relatively high conduction band offset at a polysilicon interface as well as a high crystallization temperature and an excellent step coverage, but it has a limited ability to increase a capacitance of a capacitor due to having a relatively low dielectric constant.
A lanthanum oxide layer (La2O3) as a dielectric layer has the several advantages of having a relatively high dielectric constant of about 27, a relatively high conduction band offset of about 2.7 eV, and a high crystallization temperature of about 900° C. In spite of such desirable dielectric properties, research for applying a lanthanum oxide layer to a gate dielectric layer (such as gate dielectric 104 as seen in FIG. 6) or to a capacitor dielectric layer (such as capacitor dielectric layer 324 as seen in FIG. 13) has not been actively carried out, presumably due to an absence of an appropriate precursor. One method of forming a lanthanum oxide layer which uses a CVD technology and a metal organic material, which includes a β-diketonate group of La(thd)3 (Lanthanum tris(2,2,6,6-tetramethyl-3,5-heptanedionate)) as precursor, is disclosed in U.S. Pat. No. 6,110,529 and U.S. Pat. No. 5,916,359, which patents are incorporated herein by reference. However, the compound La(thd)3 which is employed as a lanthanum precursor in these patents may not be suitable for actual commercial applications because of productivity and/or economic performance, or other operational limitations due to such process requirements as a low vapor pressure, a high process temperature, a low growth rate, or the like in comparison with the processes employed for forming other types of dielectric layers.
These and other problems with and limitations of prior art dielectric materials and fabrication/layer-formation processes are addressed in whole or at least in part by the methods and techniques of this invention.