Vertical fin-based field-effect transistor (finFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area overlying a substrate. However, as circuits are scaled to smaller dimensions and thus a smaller area, the required lateral spacing between adjacent vertical fins may become too small to enable the vertical finFET devices to operate properly. A main reason for this limitation is that it is difficult to form the desired metal thicknesses between the adjacent fins along the height of the vertical fins, which may have a height in a range of about 35 nm to about 50 nm, in particular, it may be difficult to form either or both of a work-function tuning metal and a low-resistance capping; metal of a metal portion of a gate stack in the small lateral spacing between the fins. If the low-resistance capping metal is not fully formed along the about 35-50 nm height of the vertical fins, then a large gate resistance may occur that may cause a circuit including the vertical finFET to have reduced AC performance. If the work-function tuning metal is not formed or not fully formed along the about 35-50 nm height of the vertical fins, then the vertical finFET may be inoperable due either to no gate control of the channel potential, for example, no transistor action, or ill-centered and/or uncontrolled threshold voltage, VT.
Reference is now made to FIG. 1, which is a cross sectional view schematically illustrating a conventional vertical finFET semiconductor device. A conventional vertical finFET semiconductor device 100 may include a substrate 150. The conventional vertical finFET semiconductor device 100 may also include multiple vertical fins 110 that serve as channel regions of the conventional vertical finFET semiconductor device 100. Adjacent ones of the multiple vertical fins 110 may be separated by a horizontal spacing distance h in a dimension parallel to a surface of the substrate 150. The conventional vertical finFET semiconductor device 100 may include a gate stack on top surfaces of the vertical fins 110 and extending down sidewall surfaces of the vertical fins 110. The gate stack may include gate dielectric layers 120 formed on the top surfaces and sidewall surfaces of the vertical fins 110. The gate stack may include work function tuning metal layers 130 formed on the gate dielectric layers 120. The gate stack may include a low resistance gate metal layer 140 formed on the work function tuning metal layers 130. A minimum of the horizontal spacing distance h separating adjacent ones of the multiple vertical fins 110 of the conventional vertical finFET semiconductor device 100 may be limited to a minimum distance required to form the gate dielectric layers 120 and work function tuning metal layers 130 on the sidewall surfaces of the vertical fins 110, as illustrated in FIG. 1, The minimum of the horizontal spacing distance h of the conventional finFET may limit a minimum size of the vertical finFET semiconductor device 100. An effective channel conduction width of the conventional vertical finFET semiconductor device 100 may be approximately equal to a sum of lengths of the surfaces of the vertical fins 110 that arc surrounded by the low resistance gate material metal layer 140. For example, the effective channel conduction width of the conventional vertical finFET semiconductor device 100 may be approximately equal to a sum of lengths of the top surfaces and sidewall surfaces of the vertical fins 110 that are surrounded by the low resistance gate material metal layer 140.