1. Field of the Invention
The present invention relates to a variable resistance memory device in which respective memory cells are formed by serially connecting memory elements, resistance of which changes according to applied voltage, and access transistors.
2. Description of the Related Art
There is known a variable resistance memory device having, for each of memory cells, a memory element, resistance of which changes according to injection of conductive ions into an insulating film or removal of conductive ions from the insulating film (see, for example, K. Aratani, etc. “A Novel Resistance Memory with High Scalability and Nanosecond Switching”, Technical Digest IEDM 2007, pp. 783 to 786 (Non-Patent Document 1).
The memory element has a laminated structure in which a supply layer for the conductive ions and the insulating film are formed between two electrodes.
The memory cell is formed by serially connecting the memory element and an access transistor between first and second active-matrix drivable common lines. Such a memory cell is called 1T1R-type memory cell because the memory cell has one transistor (T) and one (variable) resistor (R).
The memory device having this 1T1R-type memory cell is called ReRAM.
The ReRAM is capable of performing write and erase operation with a pulse having short duration in nanosecond [ns] order with the level of resistance associated with write and erase of data. Therefore, the ReRAM attracts attention as a nonvolatile memory (NVM) capable of performing operation at speed as high as that of a random access memory (RAM).
However, there are several barriers that should be overcome in order to replace the existing FG (Floating Gate) NAND NVM (flash memory) with the ReRAM. One of the barriers is that write and erase characteristics of the memory cell have dependency on the number of times of rewriting.
Therefore, an optimum operation condition applied to the memory cell changes according to the number of times of rewriting. In other words, if a use condition such as frequency of rewriting is different, rewriting current and voltage stress necessary and sufficient for the memory cell is also different. Excessive rewriting current and voltage stress is undesirable because the rewriting current and voltage stress increases leak and varies (reduces) a rewritable number of times.
In other words, the nonvolatile memory device of this type can attain both the guarantee of an upper limit of the number of times of rewriting and the maintenance of a data storage characteristic on condition that rewriting current and voltage stress necessary and sufficient at every moment is given.
There is known a driving method for carrying out, for the purpose of performing the necessary and sufficient driving, verification readout operation (hereinafter referred to as verify operation) after pulse application with an initial current or an initial voltage, which are applied to the memory cell during one rewriting, set rather low. In this driving method, in general, a current value or a voltage value that should be applied next is determined according to a result of the verification readout (a verify result).
However, in this driving method, the verify operation needs to be performed every time write or erase is performed. This hinders the high-speed operation.
Various devices for improving high-speed properties in the driving method involving the verify operation are proposed (JP-A-2008-10035, JP-A-2000-76878, and JP-A-2002-319289 (Patent Documents 1 to 3) and K. Aratani, etc. “A Novel Resistance Memory with High Scalability and Nanosecond Switching”, Technical Digest IEDM 2007, pp. 783 to 786 and K. Tsunoda, etc. “Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V”, 2007 IEEE, pp. 267 to 270 (Non-Patent Document 1 and 2)).
Patent Document 1 and Non-Patent Document 2 describe or indicate that voltage (or electric current) applied to a 1T1R-type memory cell is controlled by controlling a gate voltage of an access transistor and a drain voltage of the access transistor. In Patent Document 1 and Non-Patent Document 2, the control of the gate voltage and the drain voltage enables high-speed operation while guaranteeing write and erase characteristics even if the memory cell has dependency on the number of times of rewriting.
In a MONOS flash memory, there is also known a technique for controlling a gate voltage and a drain voltage of a transistor (see, for example, Patent Documents 2 and 3).
In a variable phase memory, there is also known a technique for controlling a drain voltage (a bit line voltage) (see, for example, JP-A-155700 (Patent Document 4)). In this technique, a configuration for providing plural bit line drivers and switching the bit line drivers is disclosed.