1. Field of the Invention
The present invention is related to a gate array and a manufacturing method of a semiconductor integrated circuit using the gate array, and especially to a gate array including a row composed of gate electrodes each having a different etching rate and a manufacturing method of a semiconductor integrated circuit using the gate array.
2. Background of the Invention
In a conventional gate array, since gate electrodes of P-channel and N-channel transistors are of the same shape, at first glance, it is impossible to distinguish between a row in which the P-channel transistor is formed and a row in which the N-channel transistor is formed. For example, FIG. 11 shows a layout pattern of a structure of a gate array generally called xe2x80x9csea-of-gatexe2x80x9d. A semiconductor chip is formed of various elements integrated on one semiconductor substrate. In the outskirts of the semiconductor chip 1 of FIG. 11, a pad 2 connected to a lead line for electrically connecting with the outside of the semiconductor chip 1, and an I/O buffer cell 3 for buffering, for example, a signal to be exchanged between the semiconductor chip 1 and the outside thereof, are arranged. At the central portion of the semiconductor chip 1, gate electrodes 4 are arranged in arrays. In rows C1 through C7 of the gate electrodes, the conductivity type of the transistors are allotted in order, for example, xe2x80x9cPNNPPNNxe2x80x9d.
In a general logic device, a gate length is an important factor to determine transistor performance, so that measuring and managing a gate length during process is very important. For a conventional device, since gate electrodes of P-channel and N-channel MIS transistors are formed of the same material, there is no need to distinguish the channel type of the MIS transistors to measure the gate length.
However, when the gate electrode of the P-channel MIS transistor is formed of a P-type polysilicon and the gate electrode of the N-channel MIS transistor is formed of an N-type polysilicon, their etching rates become different from each other due to the difference of impurity. Thus, for a proper management, it becomes necessary to distinguish between the P-channel and N-channel MIS transistors to measure the respective gate lengths. FIG. 13 is a graph for explaining variations in gate length between lots of the semiconductor chip. In this figure, a closed circle indicates an average gate length of the N-channel MIS transistor; an open circle indicates an average gate length of the P-channel MIS transistor; and the straight line attached to those circles indicates a distribution range (for example, three times as large as a standard deviation). In the case of FIG. 13, the gate length is managed so as to fall in the range of xc2x10.05 xcexcm centered at 0.35 xcexcm. From this figure, it is understood that, under the same etching condition, the gate length of the P-channel MIS transistor is always longer than that of the N-channel MIS transistor. Thus, the proper management is only possible with the distinction between the N-channel and P-channel MIS transistors.
Then, it becomes necessary to measure the respective gate length by making a distinction between the gate electrodes of the P-channel and N-channel MIS transistors. When the whole semiconductor chip 1 is within the visual field as shown in FIG. 11, the conductivity type of the transistors in a region AR1, for example, can be quickly distinguished as an N-type by counting the number of rows. However, when a part of the region AR1 of the semiconductor chip 1 is enlarged by a scanning electron microscope, for example, as shown in FIG. 12, to measure the gate lengths of the N-channel and the P-channel MIS transistors, it becomes difficult to distinguish the channel type of the transistors in the region AR1.
In the above-described conventional gate array and manufacturing method of the semiconductor integrated circuit using the gate array, when the gate electrodes are formed of materials having different etching rates, the gate electrodes need to be separated into groups according to their materials to measure the gate length. However, there is no mark for distinguishing between the gate electrodes at the gate electrodes or in the vicinity of the gate electrodes in the conventional gate array. Thus, for an enlarged gate electrode, it is difficult to determine which group the gate electrode to be measured, for example, belongs to, and thereby the processing time for measurement is increased.
A first aspect of the present invention is directed to a gate array comprising: a plurality of first rows formed by arranging a plurality of first MIS transistors on a semiconductor substrate; and a plurality of second rows formed by arranging a plurality of second MIS transistors on the semiconductor substrate, wherein there is a difference in shape of a predetermined structural member, distinguishable by appearances, between the first and second rows.
Preferably, according to a second aspect of the present invention, in the gate array according to the first aspect, the predetermined structural member is a contact pad portion of a gate electrode.
Preferably, according to a third aspect of the present invention, in the gate array according to the second aspect, the contact pad portion of the gate electrode includes a protruding part; the protruding part in one row is arranged in a direction determined by a predetermined rule; and the predetermined rule for the first row is different from that for the second row.
Preferably, according to a fourth aspect of the present invention, in the gate array according to the third aspect, the protruding part in the first row is arranged in the opposite direction to that in the second row; and both center lines of the contact pad portions in the first and second rows almost agree with the same straight line.
Preferably, according to a fifth aspect of the present invention, in the gate array according to the third aspect, the protruding part in the first row is arranged in the opposite direction to that in the second row; and both center lines of portions of the gate electrodes in the first and second rows, except the contact pad portions, almost agree with the same straight line.
Preferably, according to a sixth aspect of the present invention, in the gate array according to the third aspect, the predetermined rule provides a plurality of arrangements each corresponding to different information.
Preferably, according to a seventh aspect of the present invention, in the gate array according to the first aspect, the predetermined structural member is a field oxide film.
Preferably, according to an eighth aspect of the present invention, in the gate array according to the first aspect, the predetermined structural member is a field shield electrode.
Preferably, according to a ninth aspect of the present invention, in the gate array according to the eighth aspect, there is a difference in the shape of a hole for body contact provided in the field shield electrode, between the first and second rows.
A tenth aspect of the present invention is directed to a manufacturing method of a semiconductor integrated circuit using a gate array, comprising the steps of: forming a plurality of first rows by arranging a plurality of first MIS transistors on a semiconductor substrate, and a plurality of second rows by arranging a plurality of second MIS transistors each having a gate electrode which is different from that of the first MIS transistor in an etching rate of a material, the second row including a difference in shape, distinguishable by the appearance of the semiconductor substrate, from the first row; and measuring a gate length by distinguishing between the first and second rows on the basis of the difference in shape while enlarging a gate electrode.
In the gate array of the first aspect or the manufacturing method of the semiconductor integrated circuit using the gate array of the tenth aspect, when the gate length is measured, for example, the gate electrodes formed of materials having different etching rates can be distinguished by the difference in shape between the first and second rows. This prevents misjudgment of the material of the gate electrode to be measured, and further shortens time to confirm the material of the gate electrode.
In the gate array of the second aspect, the first and second rows are distinguishable by the shape of the contact pad portion of the gate electrode, that is, only by the gate electrode. This brings about quick measurement.
In the gate array of the third aspect, the difference in shape is easily distinguishable because the protruding part whose direction is examined is relatively large in shape.
In the gate array of the fourth aspect, the source/drain contacts in the first and second rows can be positioned in the same straight line. Thus, the design for the position of the source/drain contact remains the same as before, which reduces the complexity of design.
In the gate array of the fifth aspect, the design for the position of the contact arranged in the contact pad portion of the gate electrode remains the same as before, which reduces the complexity of design.
In the gate array of the sixth aspect, it is possible to transmit information necessary for measurement except that for distinguishing between the first and second rows, depending on the combination of arrangements. This reduces the movement of the visual field when the gate electrode is enlarged, resulting in quick measurement when such transmission of information is required.
In the gate array of the seventh aspect, the first and second rows can be distinguished by observing the field oxide film in the vicinity of the gate electrode, which brings about quick measurement. Further, since the design of the gate array remains the same as before except for the shape of the field oxide film, the complexity of design can be suppressed.
In the gate array of the eighth aspect, the first and second rows can be distinguished by observing the field electrode in the vicinity of the gate electrode, which brings about quick measurement. Further, since the design of the gate array such as the shape of the gate electrode remains the same as before except for the shape of the field oxide film, the complexity of design can be suppressed.
In the gate array of the ninth aspect, the first and second rows can be distinguished by observing the hole for body contact, in large numbers for each row, formed in the vicinity of the gate electrode, which brings about quick measurement. Further, since the design of the gate array remains the same as before except for the shape of the hole for body contact, the complexity of design can be suppressed.
The object of the present invention is to simplify the distinction between groups of enlarged gate electrodes by adding information of the grouping at the gate electrode or in the vicinity of the gate electrode, and thereby to shorten the processing time to recognize the gate electrode with the scanning electron microscope.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.