1. Field of the Invention
The present invention generally relates to the structure of a flash memory and, more particularly, to an electrically erasable and programmable non-volatile semiconductor memory device and its methods of read, write and erasure.
2. Description of the Related Art
Until we arrive at the present, there are many proposals and practical applications of various NOR-type flash memories. As illustrated in FIG. 16, there are two major types of practical applications. One is a floating gate type as a memory cell of flash memory. The other is a type of flash memory, with charge stored in silicon nitride film (SONOS hereinafter). (See “Evolution of Embedded Flash Memory Technology for MCU” as published by Hideto Hidaka in IEEE ICICDT 2011, Tech. dig) Moreover, the flash memories whose memory cells comprise “1-transistor”, “1.5-transistors”, or “2-transistors” per cell have been practically applied. The “1.5-transistors” type has 2 transistors in one memory cell, but the space between the 2 transistors is smaller than the space of the “2-transistors” type. So, it is named the “1.5-transistors” type in this invention. They potentially have advantages and disadvantages. Considering the cell size, the cell structures of the “1.5-transistors” and “2-transistors” types may cause the disadvantage of cell size increase owing to the increased number of transistors per cell compared with the “1-transistor” type. In addition, the “1.5-transistors” type has a large cost increase due to the complicated structures. Thus, the “1-transistor” memory cell with a floating gate has been widely used as a batch erase NOR-type flash memory. However, this type of flash memory likely causes over-erase when erasing, which leads to a narrow operation margin.
FIG. 17 is a drawing to illustrate the cross-sectional view of the conventional SONOS flash memory cell of the “1.5 transistors” type. FIG. 18 is a drawing to illustrate the equivalent circuit of a memory cell array of those SONOS flash memory cells. (See U.S. Pat. No. 5,408,115) (See Non “Investigation of the Data Retention Mechanism and Modeling for the High Reliability Embedded Split-Gate MONOS Flash Memory” as published by Yoshiyuki Kawashima, Takashi Hashimoto, Ichiro Yamakawa in IEEE IRPS 2015). The memory cell 30 shown in FIG. 17 comprises a MOS-type transistor having a 3-layer insulating film 33 and a control gate 32 thereon on the right side of the figure and a MOS transistor having a 1-layer gate oxide and a select gate 36 thereon. Those transistors are nearest neighbors to each other on a P-type silicon substrate 31 or a P-well thereon, and two N-type diffusion layers are formed. One of them, on the side of the MOS-type transistor having the 3-layer insulating film 33, is a source 34. The other is a drain 35. The 3-layer insulating film 33 is a lamination comprising silicon oxide (33-1 in FIG. 18), silicon nitride (33-2 in FIG. 18), and silicon oxide (33-3 in FIG. 18) from the substrate. The silicon nitride 33-2 plays a role of a charge trapping layer.
FIG. 18 illustrates the memory cell array 40 with the memory cells 30 in FIG. 17 arrayed in a matrix. In this matrix array of those memory cells, there are control gate lines 32-1 and 32-2 which connect to the control gate 32 of the memory cell 30 in FIG. 17, select gate lines 36-1 and 36-2 which connect to the select gate 36 of the memory cell 30 in FIG. 17, and a source line 37 along the column direction. There are bit lines 38-1 and 38-2 which connect to the drain 35 of the memory cell 30 in FIG. 17 along the row direction. The sources 34 and the drains 35, which are parallel-arrayed along the column direction, connect to the source line 37 and the bit lines 38-1 or 38-2, respectively, and may be used for controlling the memory cell array 40.
To write the memory cell 30, a hot electron injection (depicted SSI hereinafter) is performed by applying about 5V, about 0V, about 10V, and about 1V to the source 34, the drain 35, the control gate 32, and the select gate 36, respectively. The high electric field is applied on a space between the select gate 36 and the control gate 32. Then, a portion of electrons having high energy are injected into the silicon nitride 33-2 serving as the charge storage layer, and, then, the threshold voltage of the transistor with the control gate 32 is increased.
To erase the memory cell 30, the tunneling phenomena of valence electrons to the conduction band (depicted BTBT hereinafter) is performed by applying a high voltage more than 4V, about −5V, and about 0V to the source 34, the control gate 32, and the select gate 36, respectively. However, the drain 35 is floating or grounded. This causes the BTBT, and, then, holes having high energies are generated on the source side of the transistor with the control gate 32. A portion of those holes injects into the silicon nitride 33-2 serving as a charge storage layer. Thus, the threshold voltage of the transistor with the control gate 32 is shifted negative.
To fabricate the conventional type of SONOS flash memory with “1.5 transistors” per cell, which is illustrated in FIG. 17, the select gate 36 is first formed, and, then, the control gate 32 is formed right thereto by a kind of self-align method. Thereby, the select gate 36 is influenced by a thermal process at the step of forming the control gate 32. In general, on the other hand, the select gate 36 is simultaneously formed with periphery memory cell control circuit transistors or other logic circuit transistors, in order to reduce the complexity of the fabrication process and the manufacturing cost. In this event, those periphery memory cell control circuit transistors or other logic circuit transistors are also influenced by the thermal process at the step of forming the control gate 32, and, then, the characteristics of periphery memory cell control circuit transistors or other logic circuit transistors degrade. Moreover, since the 3-layer insulating film 33 and the control gate 32 to be used in the memory cell are formed after forming those periphery memory cell control circuit transistors or other logic circuit transistors, it has been necessary to avoid an excess 3-layer insulating film 33 and control gate 32 to be formed in the region of the periphery memory cell control circuit or other logic circuit for suppressing the influence on the periphery memory cell control circuit transistors or other logic circuit transistors there. This also has caused the manufacturing process to be complex. In addition, a metal silicide film has been formed on the polysilicon of the control gate 32 and the select gate 36 to reduce the resistivity. However, this increases the difficulty of manufacturing owing to the vital risk of a short of the adjoining control gate 32 and select gate 36.