As it is well known, the reading modalities of the cells of an electronic memory circuit integrated onto semiconductor are possible due to a predetermined sequence of operations known in the technical field as "reading cycle". A reading cycle starts when the memory address of data, which needs to be read, is presented at the input terminals for the memory circuit. An input stage detects the commutation of an address present on such terminals, thus starting a reading operation. Line and column decoding circuits select the memory word which has been addressed.
The circuit portion for reading the memory cell content and for carrying out the conversion of the read analog data into a digital one is called a sense amplifier or reading amplifier. Normally such an amplifier is of a differential type and is provided with a pair of inputs which are respectively connected to a cell of the memory matrix and to a reference cell. Reading becomes possible because of an unbalance of the matrix branch opposite to the reference branch. The data received by the sense amplifier then appears at the output through a buffer output stage.
Each of the previously described phases of the reading cycle must have a predetermined duration which should be compatible with the access time to the memory foreseen by the specifications of the memory circuit. All phases of the reading cycle are timed by synchronization pulses derived from a unique main pulse named ATD (Address Transition Detection). The ATD pulse is generated within the memory circuit each time an address commutation is detected on the input terminals. The ATD pulse generation is generally the task of a NOR structure, which usually has a high logical level output. When a logical level commutation occurs even at only one of the input terminals, the NOR structure commutates its own output allowing the discharging to ground of a terminal wherefrom the ATD pulse is taken via a logic inverter. According to what is at the moment foreseen by the prior art, in the herein attached FIG. 1 there is shown a schematic view of the circuitry dedicated to generating of the ATD signal.
FIG. 1 shows a circuitry 11, or ATD cell, which comprises two N-channel MOS input transistors, indicated by the symbols M1 and M2, respectively, which are very conductive due to their sizing been carried out according to a high W/L ratio. Cell 11 comprises a pair of inverters I1, I2, each one thereof including a complementary CMOS pair with a pull-up transistor and a pull-down transistor. The pull-up transistors of the inverters I1 and I2 are resistive, and therefore little conductive, having been sized according to a low W/L ratio.
The resulting structure of the coupling of the two inverters I1 and I2 corresponds to that of a latch register 3 having outputs Q and Q#. Such latch register 3 is connected to a first capacitor C1 and to a second capacitor C2, as well as to corresponding first and second NMOS transistors M1 and M2, respectively, creating a bistable circuit, which receives as input a signal AX and the corresponding NOT signal AX_N from one of said input terminals. As a result we have a fully symmetric structure, with outputs Q and Q# linked to the values of the input signals AX and A_N. At an idle stage only one of the input signals will have a logical high value, for example equal to A_N. The capacitor C2 will be discharged and will be maintained at mass, whereas it will be possible to charge the capacitor C1 by the pull-up of the first inverter I1. In these conditions, the output Q is at a high logical level, the output Q# accordingly being at a low logical level.
When an input transition occurs, the capacitor C1 will be quickly discharged by the transistor M1, whereas the capacitor C2 will start to recharge thanks to the pull-up of the second inverter I2. Accordingly, the first output Q of the latch 3 will immediately be brought to a low logical level. It will take some more time for the other output Q# to commutate its state, as the pull-up transistors of the inverters I1, I2 are very resistive. There will be a moment when both said outputs will be at a low logical level.
As such outputs Q and Q# are directly connected to the respective inputs of a NOR type logical gate I3, the output of such gate I3 will be forced to a high logical value, thus allowing the switching on of an NMOS transistor connected to the output node 4 of the logical gate I3, as well as to the output node of the circuit 11, referenced by W in FIG. 1.
At each address input terminal of the memory circuit there is associated a cell 11, as schematically shown in FIG. 2. A cell 11 may be associated also to different input terminals, for example to control signals adapted for triggering an ATD signal.
This solution, in the technical field known as distributed NOR, foresees that each cell has its output connected to a single ATD-LINE line 7, which is usually given by a metalization line connected to the VDD power supply by means of a PMOS transistor M4 having a control terminal GND connected to ground.
The nodes W of the output transistors of the circuit 11, as shown in FIG. 1, are connected to each other to comprise the ATD-LINE line 7 of FIG. 2.
From this line 7 the ATD pulse is taken by means of an inverter 5. The ATD is generated by a transition of at least one of the input terminals, and it represents the signal that triggers the reading.
In ideal operating conditions, the addresses are shown at the same time at the memory device pins, or are modified within a time interval not smaller than the access time, as shown for instance in the diagrams of FIG. 3. Unfortunately, no specification guarantees that the user will work adopting these precautions.
The user obviously has the right to continuously and arbitrarily change the addresses of the memory locations which he likes to access; the valid address is the last one, that is the one for which the memory device must for sure show the data at the output. Anyway, as it is impossible to know in advance which is the last address on the basis of the present specifications, the device must always be ready on any transition of the addresses because any of them could be the last. In the case of a fully static memory, that is a memory which is not provided with precharged nodes, no major problem occurs as the signal flow, from the addresses to the outputs, behaves like a flow of signals within combinatory logic.
In presence of precharged nodes, on the contrary, it is necessary to observe compelling timings for the recharge of the nodes, otherwise reading errors may be encountered.
Let's consider, for example, the case wherein commutations occur the one after the other spaced by a time greater than the ATD pulse duration. In this situation, schematically shown by the solid line 12 of FIG. 4, various distinct ATD pulses would occur in sequence. On the other end should the commutations be closer, as highlighted by the solid line 13 of FIG. 4, then the single pulses would be such as to keep the line 7 to ground and the ATD output signal would remain high till the last commutation.
Therefore it is essential to trigger the reading phase on the declining ramp of the ATD pulse, otherwise it may happen that reading phases are triggered on non valid addresses.
To fully understand all the aspects of this invention, it is important to consider a further constraint.
At the moment, the operating range typical of a non volatile memory is characterized by a temperature of between -40.degree. C. and 130.degree. C. and by a feed voltage between 2.5 and 3.8 V. For example, the variation of these two parameters brings a variation in the ATD pulse duration. This latter may have a maximum duration of about 10 ns at 3.8 V and -40.degree. C. and a minimum duration of about 2 ns at 2.5 V and 130.degree. C.
The sizing of the ATD pulse should therefore fulfill two requirements:
it should be long enough not to be filtered during its propagation by the parasitic capacitances which are given in the circuitry for the reading path; PA1 it should be short enough to quickly show the declining ramp after the address commutation; in fact the true reading phase only starts on the declining ramp of the ATD and therefore the ATD duration fully influences the access time.
Prior art proposes to carry out a temperature and voltage compensation with the purpose to obtain a pulse of reasonable duration in all the operating conditions.
This possible solution, however, is not able to solve the problem, when the number of ATD cells is quite high. For example, in the modern memory devices there are at least twenty ATD cells and their number is likely to increase along with the density increase of the devices because in this way the number of address bits increases.
To compensate all these cells means a problem of occupied circuit area, of accuracy and of circuit complexity.