In DRAM, since the capacitor of a memory cell is in a floated state, accumulated charges are gradually lost by a pn junction leak and leak of current across drain and source of a transistor in a memory cell. In order to prevent this unfavorable phenomenon, refresh operation is carried out. That is, even when there is no request for reading or writing, information is periodically read and rewritten. This DRAM is suitable for an increase in capacitance and, thus, together with CPU, has been widely used in electronic equipment (devices) such as personal computers.
Switching of the refresh mode of DRAM has hitherto been carried out in specific routine in the preparation of a software, for example, at the time of idling of the device, at the time of the operation of the suspend mode, or at the time of description using a power supply control routine or the like. A specific example thereof is that suspend or standby processing routine/resume processing routine is prepared and switching of refresh mode of DRAM is carried out within the routine. When suspend (or standby) processing routine for suppressing the power consumption is mounted in the equipment, design is carried out so that the refresh mode of DRAM is switched from auto-refresh mode to self-refresh mode within the routine.
Here the “auto-refresh mode” refers to a mode wherein, when there is no access to DRAM for a given period of time due to the occurrence of loop processing or the like, a DRAM controller carries out refresh in a predetermined refresh cycle. The “self-refresh mode” refers to a mode wherein, upon the receipt of a command, the DRAM per se carries out refresh in a long refresh cycle. In the self-refresh mode, the refresh cycle is long, and, thus, the power consumption in DRAM can be advantageously reduced.
In electronic equipment provided with CPU and a memory, however, the tendency toward the adoption of multifunction has led to enlargement of softwares which has in turn led to a demand for high-capacity memories. In PDAs (personal digital assistants) and portable telephones (cellular phones), PHS (personal handyphone systems) and the like which operate using a cell as a power supply, due to the limitation of supply of power, SRAMs (static random access memories) having low power consumption have hitherto been used although these SRAMs are expensive for use as memories.
In recent years, however, also in electronic equipment which is operated using a cell as a power supply, an increase in capacity of the memory has led to a tendency toward the use of DRAMS, which is low in cost and can realize an increase in capacity, instead of SRAMs. In this case, in personal computers and the like which are operated through an ac power supply, the contents of DRAM are if necessary stored in a hard disk, while, in portable telephones and the like, the use of DRAM instead of SRAM poses a problem of loss of data upon turn-off of the power supply, which problem does not occur in SRAM wherein data is stored even when the power is supply in turn-off state. Therefore, refresh control of DRAM is very important. Further, since many persons always carry portable telephones and the like with them, there is a demand for an increase in operation time, that is, a demand for a reduction in power consumption in a standby state with the power supply being turned on. To meet this demand, refresh control should be properly carried out while taking the status of operation of the device into consideration.
In the conventional DRAM device and refresh control method therefor, specifications of the switching control of the refresh mode are determined at the time of the preparation of a software. Therefore, when a person responsible for the preparation of the software prepares the software without properly understanding the behavior of the software on the device, for example, occurrence of interruption and the status of transition of task, a problem occurs such that, despite the fact that DRAM is operated in self-refresh mode, a software, which enables access to this DRAM, is incorporated.
Another problem is as follows. Upon switching of DRAM to self-refresh mode during the operation of DRAM in such a state that there is return address, CPU executes switching from auto-refresh to self-refresh. At that time, data on return address is lost by the self-refresh, and this makes it impossible to continue processing. In this case, storage of the return address in a different recording medium (SRAM) or the like is effective for avoiding this problem. This, however, complicates the construction and processing, leading to an increase in cost.
The adoption of multifunction in the above-described personal digital assistants, portable telephones and the like has led to an increase in size of softwares. This is making it difficult to perform switching of refresh mode while controlling the status of the hardware.