Accurate timing closure is an essential part of any programmable logic device, or any other integrated circuit design flow. As designs are reaching device maximum frequencies, the margin left for correct timing closure is shrinking with every new design. Consequently, no guard band is left for error. Thus, for any integrated circuit, especially non-reprogrammable integrated circuits, it is important to account for clock uncertainties in order to avoid redesigns and costly mask changes should a design not work out after being committed to silicon.
Clock uncertainty needs to be considered in order to guarantee timing analysis accuracy. In an ideal situation, the clock edge in a system will be repeated at a fixed interval of time. However, due to noise, coupling and other effects, the clock edge will wander from the ideal position, causing both setup and hold clock uncertainty during a register-to-register data transfer. Whenever the setup or hold time spec is violated, an error occurs in the data transfer, which causes the circuit to function incorrectly.
Traditional systems with one or no PLL could get around calculating the clock uncertainty by ignoring it or adding an extra guard band to the timing closure. As the complexity of the system increased, additional clock uncertainty was added. However, this additional clock uncertainty was estimated rather than calculated and did not realistically represent the actual number.
Accordingly, there is a need to determine an impact of clock uncertainties on an integrated circuit design during the design phase to avoid costly re-designs.