1. Field of the Invention
The invention relates generally to memory systems, and more particularly to systems and methods for enabling memories to operate properly despite the presence of multiple defective memory cells.
2. Related Art
Digital circuits are becoming increasingly complex. It is not unusual for one of these circuits to be made up of millions of transistors. As digital circuits become more complex, they typically have greater capabilities, but there is also a greater chance that one or more of the components of the circuits will not operate properly. In some instances, even a single incorrect bit can cause a malfunction that will render an entire circuit useless. This may be particularly true of expensive digital circuits, such as advanced microprocessors. It is therefore very important to minimize the number of defects that arise in the manufacturing of digital circuits.
Even though a great deal of effort goes into minimizing the number of defects that are present in digital circuits, it is virtually impossible to eliminate all defects. Consequently it is important, not only to minimize the number of defects that arise during manufacturing processes, but also to take advantage of mechanisms that allow digital circuits to operate properly even in the presence of these defects.
Memory systems provide one example of systems that can be designed to operate normally despite having one or more defective memory cells. A memory array includes a large number of identical memory cells, each of which can store a single bit of data. A set of these memory cells can store a block of data (e.g., an eight-bit byte or a 32-bit word) that has a unique address within the memory array. If a single memory cell in the array is defective, data that is stored at an address in the array which includes the defective cell may be corrupted, and a program using this data may produce erroneous results. Because the memory cells are functionally identical, however, a mechanism may be provided to substitute properly operating memory cells for the defective memory cells.
Conventionally, this memory replacement is achieved using a line-replacement redundancy mechanism in which a defective row or column of memory cells is replaced functionally by a redundant row or column that is provided in the memory array. In some systems, there is a single redundant row or column, although in more recent systems there may be several. If it is determined that a particular row or column of the memory array is defective, a memory management circuit coupled to the memory array is configured to access the redundant row or column in place of the defective row or column. Put another way, an address translation is effectively performed for a single row/column of the memory array, so that when there is an attempt to access the defective row/column, this access is redirected to the redundant row/column.
While a conventional line-replacement redundancy mechanism may be effective to enable use of a memory array despite a small number of defects, this mechanism has some shortcomings. For instance, typically, only one or a few replacement rows/columns are available to replace defective rows/columns. Providing additional replacement rows/columns can be prohibitively expensive, especially in the case of cache memory that is constructed on the same chip as a processor. As the size of cache memories increase, the potential for defective memory cells increases as well, but it is difficult to scale up the line replacement mechanism to meet the increased potential for defects.
It would therefore be desirable to provide improved systems and methods to enable memory systems, and particularly cache memories, to operate properly despite an increasing number of potentially defective memory cells, thereby increasing the yield of corresponding devices.