The present invention relates generally to design of integrated circuit and more particularly the present invention defines a method and system for new logic entry.
The logic design is the first phase of the hardware development process of an integrated circuit. The logic design describes the functions that the integrated circuit will execute. The logic design describes the set of elements related together with the data flows which will all contribute to the execution of the functions. To design integrated circuits for ASICs (Application Specific Integrated Circuits) or FPGAs (Field Programmable Gate Array) or any dedicated integrated circuits such as processors, basic hardware elements are combined in the chip. These hardware elements, the gates, form a basic set comprising Read/Write memories and registers to store and modify data, or signal and buses to convey data from one element to one other etc. The logic design describes how a global function of the circuit is realized by combining basic elements. The logic design step must also produce an xe2x80x98entryxe2x80x99 to the following hardware development phases. As a matter of fact, the hardware development process is computerized and standardized. In the language based design automation process, the first phase consists in describing the logic, for instance with a High level Description Language (HDL) which are high level programming languages such as VHDL, Verilog or AHDL. The programs are then compiled and the following phases start from the execution of these compiled programs for performing further simulation or synthesis for the creation of netlists.
The VHDL programs include the algorithmic description of the functions, they describe the behavior of the logic. This is a way to enter the logic by defining xe2x80x98what it doesxe2x80x99.
One other way to enter the logic is to describe the structure of the logic. The existing methods involve a graphical description of the logic circuit This is a way to enter the logic by defining xe2x80x98what it isxe2x80x99. The Computer Aided Drawing tools are graphical, they allow the designer to create, through the graphical user interface of the computer, block diagrams which illustrate the designer thoughts as for the high-level architecture of the circuit and the functions of the logic. Such tools allow also, then, to represent the architecture in terms of basic elements. One such design graphical editor is described in the U.S. Pat. No. 6,110,223. This editor allows the designer to organize his thoughts as to the high-level architecture and functionalities of the logic. Also the editor provides output VHDL libraries usable for the following computerized and standardized phases of the hardware development process.
Furthermore, the two methods can be combined in some way, for example, by describing graphically the logic as interconnected blocks, each block calling a behavioral description of its internal logic.
However, none of these methods include an explicit and intuitive notion of time, and more particularly do not provide any indication of the behavior of the logic in time. In electronic industry, timing in hardware components a fundamental constraint as, depending on the technology used, performing a function in a basic component takes a defined and invariable amount of time. One major challenge in designing a logic is to have the functions performed and synchronized in a time which may correspond to the data flow speed in input and the data flow speed expected in output of a function implemented as an integrated circuit. Clocks are hardware signals used for sequencing the data flow between all the components of an integrated circuit. Consequently, during the phase of logic design, the functions are split into basic elements while respecting the timing for synchronizing the execution of all of them. In the following phases of development such as the simulation after compilation of the logic design or later when the integrated circuit is tested during the bringup phase, for performing the logic verification, the functions are checked against the timing. At these steps a logic can be rejected because of unrealistic timing for execution of functions. One editor used to test the validity of timing for the scheduling of functions in a design is described in the U.S. Pat. No. 5,600,567. This editor provides a visual and scheduling criteria assigned to an algorithmic description of a function.
It is noted also that logic designers refer virtually always to some timing diagrams when creating logic circuits, whether they are in actual design documentation, or just as mental representation of what actions are triggered by their logic in time. User of logic circuits or elements invariably find in the data book describing them, some timings representing the behavior in time of some parts of the element.
There is a need to give to the designers a tool for designing a logic while taking into account its timing behavior.
The tool should take into account the two ways to design logic today which are either writing the algorithm in a HDL programming language or drawing with a graphical editor to have a comprehensible representation of the hardware elements.
As the designers may use different graphical editors to create a graphical representation of a logic design, the method to create a timing based logic entry should be adapted to any graphical editor. The method should be also stable enough to avoid having to change it each time a new version of a graphical editor is made available by the software manufacturer.
It is thus an object of the present invention to provide a method for logic entry taking into account the timing constraints of the design.
A second object of the invention is to have a computer based method using a graphical representation of the timing based logic entry.
It is a third object of the present invention to provide a computer based method for creating graphical logic design taking into account the timing constraints.
A fourth object of the invention is to create, starting from a graphical timing based logic design, the corresponding statements describing the logic in High level Design Language.
A fifth object of the invention is to have a method adapted to the use of any kind of computer graphical editor.
These objects are reached with a method for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer, said method comprising the steps of:
drawing with a single line at least one time line representing the at least one clock of the circuit;
drawing other bit signal time lines;
drawing direct arrows going from one of the drawn signal time line to at least one other drawn signal time line to describe the signal assignments of the circuit;
drawing function symbols and writing function names identifying the functions of the circuit;
drawing arrows connecting signals through functions symbols for conditional signal assignments; and,
writing signal names.
Alternatively, the method also further comprises the steps of:
reading the graphical editor output file;
identifying the signal names;
identifying the direct arrows and the signals of the signal assignments;
identifying the functions, the arrows and the signals of the conditional signal assignments;
identifying the input and output signals of the circuit;
creating an HDL file and writing the HDL statements corresponding to the elements and behavior identified in the previous identifying steps.
Alternatively, the method also further comprises the following steps of:
identifying in the graphical editor output file function names corresponding to predefined functions;
looking for HDL statements of said predefined functions in a library of predefined function HDL files;
inserting in the created HDL file the HDL statements read in the said predefined function HDL files.
Additionally, these objects are reached with a method for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer, said method comprising the steps of:
drawing with a single line at least one time line representing the at least one clock of the circuit;
drawing other bit signal time lines;
drawing direct arrows going from one of the drawn signal time line to at least one other drawn signal time line to describe the signal assignments of the circuit;
drawing function symbols and writing function names identifying the functions of the circuit;
drawing arrows connecting signals through functions symbols for conditional signal assignments; and,
writing signal names;
translating the graphical editor output file into a PostScript format file;
translating the PostScript format file into a bitmap file;
reading the bitmap file;
identifying the signal names;
identifying the direct arrows and the signals of the signal assignments;
identifying the functions, the arrows and the signals of the conditional signal assignments;
identifying the input and output signals of the circuit;
creating an HDL file and writing the HDL statements corresponding to the elements and behavior identified in the previous identifying steps.
Alternatively, the method also further comprises the following steps of:
identifying in the graphical editor output file function names corresponding to predefined functions;
looking for HDL statements of said predefined functions in a library of predefined function HDL files;
inserting in the created HDL file the HDL statements read in the said predefined function HDL files.
The objects are also achieved with the use of a computer program product comprising programming code instructions for executing the steps of the method when said program is executed on a computer.
The objects are also achieved with the use of a system adapted for carrying out the method.
A primary advantage of the invention is to have a timing representation of the behavior of the logic in consistence with the use of timing during the phase of testing, simulation and documentation used in the following phases of the hardware development process.
Additionally, this method leads to simplified verification activities because the information used to describe the logic are the same information that can be used to check the correctness of operation of a simulated circuit in the following steps of hardware development process.
Furthermore, to be open to optimized design processes, it is possible to use classical logic entry methods on some parts of a circuit and to use the timing based logic entry on the other parts. This can be required to reuse existing blocks already described in HDL, while using timing based logic entry for the design of blocks such as interfaces, clock circuits, data flow description etc . . . Such mixed design entry is possible by the method of the present invention which translates a timing diagram into a logic described in HDL, thereby enabling the interconnection with HDL based circuits.
As the format timing diagram graphical file is modified by two successive translations into a PostScript format then a bitmap file, the final steps of the method for translating from a bitmap file to a HDL description file can be xe2x80x9cuniversallyxe2x80x9d used. As a matter of fact, the PostScript or bitmap format software programs are widely used and very stable with the printing software providers. Furthermore, if a graphical editor provides a new version, the PostScript translation will be always updated by the graphical editor manufacturers who accomodate the device driver provided with the operating system. Consequently, once written, the bitmap to HDL format translation method of the invention is widely used for any hardware graphical design environment and stable because there will be no change in the bitmap definition.