Traditional computers which receive a sequence of instructions and execute the sequence one instruction at a time are known, and are referred to as "scalar" computers. With each new generation of computing machines, new acceleration mechanism must be discovered for traditional scalar machines. A recent mechanism for accelerating computational speed is found in reduced instruction set architecture (RISC) that employs a limited set of very simple instructions executing at a high rate of speed. Alternatively, another acceleration mechanism may be to add more complex instructions to the architecture to provide more computation function per instruction and thus reduce the number of instructions in a program. Application of either of these approaches to an existing scalar computer would require a fundamental alteration of the instruction set and architecture of the machine. Such a far-reaching transformation is fraught with expense, down-time, and an initial reduction in the machine's reliability and availability.
Recently, "superscalar" computers have been developed which further accelerate computation speed. These machines are essentially scalar machines whose performance is increased by adapting them to execute more than one instruction at a time from an instruction stream including a sequence of single scalar instructions. These machines typically decide at instruction execution time whether two or more instructions in a sequence of scalar instructions may be executed in parallel. The decision is based upon the operation codes (OP codes) of the instructions and on data dependencies which may exist between instructions. An OP code signifies the computational hardware required for an instruction. In general, it is not possible to concurrently execute two or more instructions which utilize the same hardware (a hardware dependency) or the same operand (a data dependency). These hardware and data dependencies prevent the parallel execution of some instruction combinations. In these cases, the affected instructions are executed serially. This, of course, reduces the performance of a superscalar machine.
Superscalar computers suffer from disadvantages which it is desirable to minimize. A concrete amount of time is consumed in deciding at instruction execution time which instructions can be executed in parallel. This time cannot be readily masked by overlapping with other machine operations. This disadvantage becomes more pronounced as the complexity of the instruction set architecture increases. Also, the parallel execution decision must be repeated each time the same instructions are to be executed.
In extending the useful lifetime of existing scalar computers, every means of accelerating execution is vital. However, acceleration by means of reduced instruction set architecture, complex instruction set architecture, or traditional superscalar techniques is potentially too costly or too disadvantageous to consider for an existing scalar machine.
It would be preferred to accelerate the speed of execution of such a computer by parallel, or concurrent, execution of instructions in an existing instruction set without requiring change of the instruction set, change of machine architecture, or extension of the time required for instruction execution.