1. Field of the Invention
The present invention relates generally to apparatus for generating a variable frequency reference clock for use in disk drives. In particular, the invention is a circuit for generating a write clock synchronized to the rotation of the disk and suitable for both dedicated servo and sector servo architectures.
2. Description of the Prior Art
Disk drives typically include at least one disk for storing information, a spindle, a spindle controller for controlling disk rotational speed, a read/write head, an actuator, read and write signal generator, and a channel.
The disk is coated with magnetic material and divided into concentric tracks. The tracks are further divided into two or more sectors having radially oriented boundaries.
The disk is rotated by the spindle, and speed of rotation is determined by the spindle controller. The actual rotation speed varies with respect to a nominal frequency.
The channel forms an interface between the disk drive and a central processing unit (CPU). During a write operation, packets of binary digitized information are received by the channel. These packets, or blocks, may be of fixed length as in a conventional fixed block architecture (FBA), or of variable length, as in a conventional count-key-data (CKD) architecture. The information received contains both data and address information. Data is encoded by the write signal generator, synchronized to a write clock, and transmitted to the read/write head. Concurrently, address information is provided to the actuator. The actuator uses the address information in conjunction with positional information residing on one of the disks to position the head over an appropriate track. The data is then recorded into the appropriate area of the media by the read/write head.
The amount of data written to a track will vary with the write clock frequency and the disk's speed of rotation. The write clock frequency will be dictated by the desired "bit density". In other words, the write clock frequency must be sufficient to enable a certain quantity of information to be written to a track as the disk rotates at a given speed.
As one moves away from the center of a disk, the physical length of a track increases. Thus, if the write clock frequency remains constant over the entire surface of a disk, the number of bits written per track remains constant, but bits at the outer region of the disk surface will be spaced at greater distances from each other than bits at the inner region of the disk.
One data recording method is directed to enhancing the bit density across the disk, thus making use of otherwise wasted disk space. In "zoned" or "constant density" recording, a disk surface is partitioned into a number of concentric zones, each zone comprising a plurality of tracks. The write clock is readjusted at the inner track of each zone to achieve a bit density substantially equivalent to that of the innermost disk track. As a result, the amount of information stored within each zone increases with distance away from the center of the disk.
To assure equal spacing between data bits written to a disk surface, the write clock may be synchronized to disk rotation. Thus fluctuations in disk speed will not adversely affect bit spacing. Data integrity is further enhanced by inserting spaces or "gaps" between records of data as they are written to the disk. Such the gaps guard against the inadvertent overwriting of data in subsequent writes that may result from an inaccurately positioned head.
There are two conventional methods for storing positional or "servo" information in a disk drive. In a "dedicated servo" architecture, all servo information is located on one predetermined disk surface, and the remaining disk surfaces are reserved exclusively for data. In contrast, servo information and data both reside on the each disk surface in "sector servo" architectures. The servo information is typically located along two or more radial sector boundaries.
Data is read from the disk in a manner similar to that for writing data. A read instruction and address information are received by the channel from the CPU. The channel relays address information to the actuator, which uses the address and positional information on one of the disks to position the head over a desired track. The head synchronizes itself to the regularly spaced data on the track, then transduces the magnetic patterns into encoded data. The data is then decoded by the read signal generator and is transmitted through the channel to the CPU.
A number of methods have been employed in the past to generate data write clocks in disk drives. These generally involve either an asynchronous or a synchronized clocking scheme. Asynchronous write clocks are usually provided by crystal oscillators. But asynchronous clocks are unable to track variations in disk rotation speed in order to consistently space the magnetic patterns. For this reason, the protective gaps between data blocks must be large enough to accommodate such variations and to prevent overwriting of previously recorded data.
In a fixed block architecture (FBA), the size of a data block is consistent, e.g. 512 bytes per block. FBA block sizes are relatively small. For this reason the increase in gap size required with the use of an asynchronous write clock may be perfectly acceptable. In contrast, variable block formats such as CKD may be thousands of bytes in length, and the corresponding increase in gap size may be impractical.
To solve this problem, previous CKD applications have employed write clocks synchronized to disk rotation. Perhaps the most common method for generating a synchronous clock is with the phase locked loop (PLL) circuit. A reference signal is read from a dedicated servo disk and provided to the PLL circuit. The PLL circuit multiplies the reference signal to generate a higher frequency clock signal. Since the reference signal is synchronized to disk rotation, the clock signal accurately reflects variations in disk speed. Consequently, gap size requirements are minimized as compared to the asynchronous clocking method.
There are several disadvantages associated with the use of a PLL circuit, however. First, the reference signal supplied to the PLL must have a frequency on the order of 1/2 to 1/20 of the desired clock frequency. This requirement limits the application of PLL's to dedicated servo architectures, since only dedicated servo disks may be encoded with a pattern which is continuous throughout each complete rotation of the disk. Moreover, writing suitable servo patterns requires costly manufacturing equipment. In addition, PLL's are not well-suited to implement zoned recording because they are designed to operate at a fixed frequency. Finally, clock signals generated by a PLL exhibit "jitter" or high frequency modulation caused by the high bandwidth control loop required to accurately track changes in the disk velocity. This jitter appears on the recorded data, increasing the possibility of retrieving faulty data.
Attempts have been made to reduce PLL jitter. For example, U.S. Pat. No. 4,818,950 entitled "Low Jitter Phase-Locked Loop" by M. H. Ranger discloses a PLL having an averaging operation and reduced error-correction circuitry. The averaging operation minimizes noise and "bit jitter". Bit jitter is defined as an irregularity in both the incoming signal and the reference signal manifested in a slightly premature or slightly late rising or falling edge. The reduced error-correction circuitry reduces the effects of electrical variations in purportedly identical circuit components. But such attempts do not resolve the limitations of PLL circuits previously mentioned.
What is needed is a clock generating circuit for producing a synchronous high frequency write clock signal from a relatively low frequency reference signal, e.g. as low as one cycle per disk revolution. The low frequency reference signal should be provided by either dedicated servo or sector servo patterns, or from the spindle controller. In addition, the synchronous clock should minimize gap size requirements so that it is well-suited for either FBA or CKD architectures. Finally, the clock generator must be capable of fast and frequent readjustment as required by zoned recording.