For the past 20 years, the integrated circuit (IC) device density has doubled in about every 18 months. When the gate length of integrated circuits is less than 0.18 .mu.m, the propagation time or delay time is dominated by interconnect delay instead of device gate delay. As the distance between metal lines decreases, the need for materials which can protect the integrity of the circuits also increases.
Aluminum and copper are the metal of choice for manufacture of integrated circuits with feature sizes of less than 0.18 .mu.m. Furthermore, as methods for etching copper are developed, integrated circuits with feature sizes of less than 0. 13 .mu.m can be made using copper damascene along with LKD materials.
I. Packaging of Integrated Circuits
When aluminum or copper is used in integrated circuits, titanium nitride (TiN) is used as barrier layer to improve interfacial adhesion between metal and Si0.sub.2 dielectric materials and to prevent corrosion of the metal by the wet chemicals used during semiconductor processing or from fluorine liberated from fluorinated Si0.sub.2 or other fluorinated polymers in the low dielectric polymer films. Corrosion results in the migration of metal ions from the metal line into the surrounding dielectric material. This results in increased leakage of current from the metal line into the adjacent circuit components, degrading circuit performance. Thus, one purpose of the glue layer or barrier layer is to prevent migration of metal ions from the metal lines. If TiN is used as a barrier layer, it must be about 200 .ANG. to about 300 .ANG. in thickness to be effective to protect against metal corrosion and degradation of circuit performance. Because metal lines are close together, the distance between them is limited by the thickness of the barrier layer (2.times.200 .ANG.=400 .ANG.) and by the intervening low dielectric material. In an integrated circuit with 0.13 .mu.m feature size, the thickness of the barrier layer of 400 .ANG. leaves only 900 .ANG. of space available for the low dielectric material. Moreover, as the space available for dielectric material decreases, there is the increased likelihood of gaps or voids being formed in the dielectric layers, further degrading circuit performance. Therefore, currently there is a need for new ways of protecting metal lines from corrosion while still maintaining proper dielectric efficiency.
Moreover, when the metal gap is equal to or smaller than 0.13 .mu.m and when copper is used as conductor, the dielectric effectiveness of currently available materials is so limited that TiN or any other currently available metal barrier will become unsuitable for protecting against metal corrosion. Furthermore, the potential interfacial corrosion problem for copper will be even more severe than for aluminum.
To address this problem and others, new adhesion layer and barrier layer materials with low dielectric constants are being developed. Organic polymers are considered an improvement over inorganic low dielectric materials because the K of organic polymers can be as low as 2.0. However, most of the currently available organic polymers have serious problems. Specifically, they are not sufficiently effective as barrier layers.
A. Siloxane Containing Polymers for Packaging Integrated Circuits
In the 1980s, very extensive studies have been conducted to find hermetic packaging technologies for copper that used in Multi-Chip Modules (MCM). Due to their excellent electrical and thermal properties, polysiloxanes are among the most prevalent materials currently used in the encapsulation of electronic components. It has been found that only silicone gels and some siloxane containing polymers can prevent increases of leakage currents for encapsulated Triple Track Testers (TTT) under pressure cooker conditions. C. P. Wong, "High Performance Silicone Gels in IC Device Chip Encapsulation," Mat. Res. Symp. 108:175-187 (1988). However, most of the conventional polysiloxanes have either gel-like or rubbery in consistency, and therefore have limited applications in areas demanding high mechanical strength of the coating material.
The mechanisms for superior insulation property of siloxane-containing polymers are remained to be fully elucidated. It was rationalized though siloxanes are permeable to water vapor, they are perfect barriers for liquid water due to their high hydrophobicity. Their near zero water absorption can be attributed to the presence of siloxane derivatives presented in these polymers: ##STR1## where R', R", R'", and R"" are alkyl groups, such as --CH.sub.3, and wherein n is an integer of from 1 to 5. Due to very high rotational and oscillatory freedom of the substituted siloxanes including R groups such as --CH.sub.3, these siloxane groups can achieve very close contact with metal. The close contact prevents water from coming between the polymer and metal components thereby providing a watertight seal to prevent the degradation of critical circuit components by water. These siloxanes therefore are suitable for barrier layer materials.
B. Spin On Glass (SOG)
Currently, spin-on-glass (SOG) processes uses both organic and inorganic compounds as precursors. Organic precursors include siloxanes which contain many Si--CH.sub.3 groups and inorganic siloxane precursors contain few Si--H groups. These precursors, produce polymer produce thin films having dielectric constants in the range of from about 2.7 to 3.0. However, a crack-free SOG dry film is only attainable when its thickness is less than 0.25 to 0.3 .mu.m. Therefore, it is necessary to perform several sequential SOG steps to manufacture a layer of SOG that is thick enough (about 1 .mu.m) to provide desirable sealing and dielectric properties. The total time needed to make SOG layers of this thickness is about 3 to 4 hours. This makes manufacturing SOG siloxane seals very inefficient. Furthermore, the SOG process is expensive due to the high losses (about 80% to 90%) of materials during spin coating.
These SOG deposited precursors also require post-deposition treatments at temperatures higher than 410.degree. C. to reduce out gassing during deposition, reflow or annealing of metals. This high temperature treatment results in high residual stress, which ranges from about 200 to about 500 MPa at room temperature. High residual stress can cause delamination at dielectric materials and metal surfaces, and can crack metal features in integrated circuits. Therefore, chemical processes that can deposit other siloxane-containing polymers are desirable.
II. Precursors and Polymers for Manufacturing Low Dielectric Constant Materials
During the past few years, several types of precursors have been used to manufacture polymers with low dielectric constants for use in manufacture of integrated circuits. Transport Polymerization (TP) and Chemical Vapor Deposition (CVD) methods have been used to deposit low dielectric materials. The starting materials, precursors and end products fall into three groups, based on their chemical compositions. The following examples of these types of precursors and products are taken from Proceedings of the Third International Dielectrics for Ultra Large Scale Integration Multilevel Interconnect Conference (DUMIC), Feb. 10-11 (1997).
A. Modification of SiO.sub.2 by Carbon (C) and Fluorine (F)
The first method described is the modification of SiO.sub.2 by adding carbon and/or fluorine atoms. McClatchie et al., Proc. 3d Int. DUMIC Conference, 34-40 (1997) used methyl silane (CH.sub.3 --SiH.sub.3) as a carbon source, and when reacted with SiH.sub.4 and the oxidant H.sub.2 0.sub.2 and deposited using a thermal CVD process, the dielectric constant (K) of the resulting polymer was 3.0. However, this K is too high to be suitable for the efficient miniaturization of integrated circuits.
Sugahara et al., Proc. 3d Int. DUMIC Conference, 19-25 (1997) deposited the aromatic precursor, C.sub.6 H.sub.5 --Si--(OCH.sub.3).sub.3 on SiO.sub.2 using a plasma enhanced (PE) CVD process that produced a thin film with a dielectric constant K of 3.1. The resulting polymer had only fair thermal stability (0.9% weight loss at 450.degree. C. in 30 minutes under nitrogen). However, the 30 min heating period is shorter than the time needed to manufacture complex integrated circuits. Multiple deposition steps, annealing, and metalizing steps significantly increase the time during which a wafer is exposed to high temperatures. Thus, this dielectric material is unsuitable for manufacture of multilevel integrated circuits.
Shimogaki et al., Proc. 3d Int. DUMIC Conference, 189-196 (1997) modified SiO.sub.2 using CF.sub.4 and SiH.sub.4 with NO.sub.2 as oxidant in a PECVD process. The process resulted in a polymer with a dielectric constant of 2.6, which is much lower than that of SiO.sub.2 (K=4.0). However, one would expect low thermal stability due to low bonding energy of sp.sup.3 C--F and sp.sup.3 C--Si bonds (BE=110 and 72 kcal/mol., respectively) in the film. The low thermal stability would result in films which could not withstand the long periods at high temperatures necessary for integrated circuit manufacture.
Siloxanes have been deposited using plasma dissociation processes (e.g., H. Yasuda, Plasma Polymerization, Academic Press (1985); M. Shen and A. T. Bell Editors: Plasma Polymerization, ACS Symposium Series, Vol.108, ACS (1979). These references are herein incorporated fully by reference. However, because these siloxane-containing polymers have low thermal stability, none of the mentioned siloxane polymers is adequate for IC fabrication meeting the requirements for small feature size.
B. Amorphous-Carbon (.alpha.C)- and Fluorinated Amorphous Carbon (F-.alpha.C)-Containing Low Dielectric Materials
The second approach described involves the manufacture of .alpha.-carbon and .alpha.-fluorinated carbon films. Robles et al., Proc. 3d Int. DUMIC Conference, 26-33 (1997) used various combinations of carbon sources including methane, octafluorocyclobutane and acetylene with fluorine sources including C.sub.2 F.sub.6 and nitrogen trifluoride (NF.sub.3) to deposit thin films using a high density plasma (HDP) CVD process.
The fluorinated amorphous carbon products had dielectric constants as low as 2.2 but had very poor thermal stability. These materials shrank as much as 45% after annealing at 350.degree. C. for 30 minutes in nitrogen.
Recently, LKD materials with dielectric constants as low as 2.5 were prepared by adding fluorinated aliphatic compounds into high density plasma chemical vapor deposition (HDPCVD). Highly cross-linked amorphous poly(tetrafluoroethylene) (PFTE; Teflon.TM., registered tradename of DuPont Inc.) with a dielectric constant of 2.0 has also been made by plasma polymerization of CF.sub.2 .dbd.CF.sub.2. However, these materials have poor thermal stability.
One theory which could account for the low thermal stability of the fluorinated amorphous carbon products is the presence of large numbers of sp.sup.3 C--F and sp.sup.3 C--sp.sup.3 C bonds in the polymers. These bonds have a bonding energy of 110 kcal/mol and 92 kcal/mol, respectively. Thus, the films cannot withstand the long periods of high temperatures necessary for IC manufacture.
Poly(para-xylylenes) or PPX have dielectric constants ranging from of 2.4 to 3.5. They can be deposited at low temperatures. The fluorinated PPX (F-PPX; Parylene-F.TM., a trademark of Special Coating Systems, Inc.) has greater thermal stability than cross-linked poly(tetrafluoroethylene) due to the presence of phenylene groups in the repeating units. However, like cross-linked poly(tetrafluoroethylene), decomposition of F-PPX will potentially cause corrosion of copper in integrated circuits. Decomposition liberates free fluoride ions (F-), which can corrode circuit components. Therefore, there is a need for the development of new materials for sealing integrated circuit components.
III. Methods for Deposition of Materials With Low Dielectric Constant
The deposition of low dielectric materials onto wafer surfaces has been performed using spin on glass (SOG), but for newer devices which have features smaller than 0.25 .mu.m, SOG processes cannot fill the small gaps between features. Therefore, vapor deposition methods are preferred. Of these, transport polymerization (TP) and chemical vapor deposition (CVD) are most suitable.
Commercial organic and inorganic spin on glass (SOG) methods deposit mostly low molecular weight siloxanes. They have disadvantages for integrated circuit manufacture. SOG processes generate waste solvents and also have low deposition efficiencies, resulting in wasting of materials and increased cost of final products.
In both TP and CVD, in contrast, the precursor molecule is dissociated (or cracked) to yield a reactive radical intermediate. The reactive intermediate contains at least one unpaired electron which upon deposition onto the wafer can bind with other reactive intermediate molecules to form a polymer. The polymer thus forms a thin film of material on the substrate. These processes are more efficient at utilizing precursors than are SOG processes. No extra precursors are needed to overcome the losses due to material spinning off of the wafer. Thus, transport polymerization and chemical vapor deposition are more desirable than SOG processes for depositing sealants to integrated circuits.
A. Chemical Vapor Deposition
Chemical vapor deposition has been used to deposit thin films with low dielectric constant. Sharangpani and Singh, Proc. 3d Int. DUMIC Conference, 117-120 (1997) reported deposition of amorphous poly(tetrafluoroethylene) using a liquid injection system. A dispersion of PFTE is sprayed directly on a wafer substrate, which is exposed to ultraviolet light and light from tungsten halogen lamps. Unfortunately, PFTE has a low glass transition temperature (Tg) and cannot be used for IC fabrication requiring temperatures of greater than 400.degree. C.
Labelle et al., Proc. 3d Int. DUMIC Conference, 98-105 (1997) reported using pulsed radio frequency (RF) plasma enhanced CVD (PECVD) process for deposition of hexafluoropropylene oxide. However, as with poly(tetrafluoroethylene), the resulting polymers have low Tg values and cannot withstand the high temperatures required for semiconductor processing.
Kudo et al., Proc. 3d Int. DUMIC Conference, 85-92 (1997) reported using a PECVD process for deposition of hydrocarbons including C.sub.2 H.sub.2 /(C.sub.2 H.sub.2 +C.sub.4 F.sub.4).
Lang et al., Mat. Res. Soc. Symp. Proc. 381:45-50 (1995) reported thermal CVD process for deposition of poly(naphthalene) and poly(fluorinated naphthalene). Although polymers made from these materials have low dielectric constants, the polymers are very rigid, being composed of adjoining naphthalene moieties. Thus, they are prone to shattering with subsequent processing such as CMP.
Selbrede and Zucker, Proc. 3d Int. DUMIC Conference, 121-124 (1997) reported using a thermal TP process for deposition of Parylene-N.TM.. The dielectric constant of the resulting polymer (K=2.65-2.70) also was not low enough. Furthermore, the decomposition temperature (Td) of the thin film was also too low to withstand temperatures greater than 400.degree. C.
Wang et al., Proc. 3d Int. DUMIC Conference, 125-128 (1997) reported that annealing a deposited layer of poly(para-xylylene) increases the thermal stability, but even then, the loss of polymer was too great to be useful for future IC manufacturing.
Wary et al. (Semiconductor International, June 1996, pp: 211-216) used the precursor (.varies., .varies., .varies.', .varies.', tetrafluoro-di-p-xylylene) and a thermal TP process for making polymers of the structural formula: {--CF.sub.2 --C.sub.6 H.sub.4 --CF.sub.2 --}.sub.n. Films made from Parylene AF-4.TM. have a dielectric constant of 2.34 and have increased thermal stability compared to the hydrocarbon dielectric materials mentioned above. Under nitrogen atmosphere, a polymer made of Parylene AF-4.TM. lost only 0.8% of its weight over 3 hours at 450.degree. C. However, the melting point of Parylene AF-4.TM. is about 400.degree. C., which is too low for metal annealing. In addition, Parylene AF-4.TM. has poor adhesion to metal and its dimer precursor is too expensive and not readily available for future IC manufacturing.
All of the aforementioned references arc hereby incorporated fully by reference.
B. Transport Polymerization
In contrast to a CVD process, transport polymerization (TP) (Lee, C. J., Transport Polymerization of Gaseous Intermediates and Polymer Crystal Growth. J Macromol. Sci. -Rev. Macromol. Chem. C16:79-127 (1977-1978), avoids several problems by cracking the precursor in one chamber and then transporting the intermediate molecules into a different deposition chamber. By doing this, the wafer can be kept cool, so that metal lines are not disrupted, and multiple layers of semiconductor devices may be manufactured on the same wafer. Further, the conditions of cracking can be adjusted to maximize the cracking of the precursor, ensuring that very little or no precursor is transported to the deposition chamber. Moreover, the density of the transported intermediates may be kept low, to discourage re-dimerization of intermediates. Thus, the thin films of low dielectric material are more homogeneous and more highly polymerized than films deposited by CVD. Therefore, these films have higher mechanical strength and can be processed with greater precision, leading to more reproducible deposition and more reproducible manufacturing of integrated circuits.