The present invention relates generally to semiconductor manufacturing and, more particularly, to a method of forming ultra shallow junctions.
The escalating need for high densification and performance associated with large scale integrated semiconductor device requires design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 micron and under challenges the limitations of conventional semiconductor manufacturing techniques.
As design features continue to shrink below 0.25 micron, it is necessary to significantly reduce the depth of the source and drain regions below the surface of the semiconductor substrate of a typical MOS transistor, particularly the source/drain regions (i.e., the junction depth). The conventional method of forming such junctions involve ion implanting boron as p-type dopants for the source/drain or ion implanting arsenic or phosphorous as n-type dopants for the source/drain. The implantation is performed at very low energy levels to achieve a shallow junction depth. Because boron is an extremely light element, it is implanted at a very low energy. With a polysilicon gate width of 0.25 micron, the junction depth should be on the order of 800 Å. The ion energy for implanting boron is typically about 5 KeV. The resulting structure is then activation annealed, typically at about 800–1000° C. to cause activation of the boron dopant to form the source and drain regions.
Achievement of a small junction depth is problematic, especially for a p+ region formed using boron ions. It has been found that during dopant activation anneal, boron diffusion in the crystalline silicon layer is significantly large, so that the junction depth of the boron tends to be much deeper than planned. The problem becomes more critical as the design features shrink to 0.18 micron or 0.13 micron and below.
The problem of undefined dopant junction depth is believed to stem from various factors. For example, boron implantation is known to damage the monocrystalline silicon substrate generating interstitial atoms of silicon, i.e., silicon atoms that are displaced from the monocrystalline lattice to occupy spaces between silicon atoms in the monocrystalline lattice. During the high temperature activation anneal, boron diffuses into the monocrystalline silicon layer by attaching to the generated interstitial silicon atoms, causing an extremely rapid diffusion of boron into the monocrystalline silicon layer. Such a rapid boron diffusion causes the dopant profile and hence the junction depth to extend below the targeted maximum, despite the low initial implantation energy. This has been referred to as the transient enhanced diffusion (TED).
One approach to reduce or eliminate TED is to form an amorphous layer from the surface to a certain depth in the monocrystalline silicon by ion implanting germanium or silicon. Boron is then ion implanted into this amorphous silicon region. Subsequent annealing at high temperature avoids TED of boron due to the lack of interstitials. The amorphous silicon is recrystallized to monocrystalline silicon by solid phase epitaxy during activation annealing. The junction depth is controlled by selecting the appropriate ion implantation energy of boron.
To form the amorphous layer, a very high dose of Ge or Si has to be implanted. At such high doses, significant crystal damage is done to the silicon. It was found that the end-of-range damage remains upon crystallization of the surface amorphous region during activation annealing. The damage includes defects such as dislocations and stacking faults. The end-of-range defects in a subsequently formed depletion layer cause junction leakage, resulting in poor transistor performance. See U.S. Pat. Nos. 6,008,098 and 6,074,937.