1. Technical Field
The present invention relates generally to preventing double patterning odd cycles, and in particular, to a computer implemented method for preventing odd cycle occurrences in double patterning layouts.
2. Description of Related Art
As semiconductor processing has improved faster than photolithography light source and photoresist technology, a technique called double patterning has emerged as a mainstream semiconductor process. Double patterning allows one to generate semiconductor structures through photolithography than are smaller and closer together than the wavelength of the photolithography light source. As a result, structures such as small as 20 nm or even smaller may be generated using a 193 nm light source using double patterning techniques. There are several techniques for double patterning including dual tone photoresist or development, double exposure, double exposure/double etch, etc.
Many adjoining structures may be generated utilizing double patterning. An issue called odd cycles can arise with double patterning. That is, if an odd number of structures are adjoining in a closed loop pattern, then double patterning cannot be successfully implemented. For example, if there are 5 tightly grouped adjoining structures arranged in a closed loop, then double patterning may not be utilized. If those 5 tightly grouped adjoining structures are in a sequence A, B, C, D and E with E also adjoining A, then a 5 sided closed loop is generated. However, with double patterning, no two adjoining structures may be generated in the same mask or mask sequence due to their close proximity (e.g., 20 nm). That is, A and C may be generated using one mask, but not E because it is adjoining A. In addition, B and D can be generated in the second mask, but not E because it is adjoining D. As a result, no odd number of tightly grouped structures in a closed loop can be double patterned, only an even number.