In a switch-mode direct current (DC) to direct current (DC) converter, the error amplifier must slew rapidly when the control mode changes from a pulse frequency modulation (PFM) control mode to a pulse width modulation (PWM) control mode or from a pulse width modulation (PWM) control mode to a pulse frequency modulation (PFM) control mode. The slew rate is the rate of change in output voltage in response to an input signal. It is desirable to have a high value of slew rate.
Circuitry in a DC-DC converter that is capable of providing a high slew rate may not be compatible with achieving a desired level of performance for other circuit elements. For example, circuitry that enables a high slew rate to be maintained in a DC-DC converter may be in conflict with a design requirement to maintain a low value of bias current.
In DC-DC converter circuits that employ both a pulse frequency modulation (PFM) control mode of operation and a pulse width modulation (PWM) of operation it is difficult to prevent the occurrence of a large transient in the output voltage when the control mode is changed. The large transient in the output voltage when the control mode is changed is due in large part to the slow operation of the error amplifier of the DC-DC converter.
FIG. 1 illustrates a typical prior art error amplifier 100 of a DC-DC converter. The error amplifier 100 comprises a first stage and a second stage. The first stage comprises a first current source 110 having a current value of I1. A typical value of current I1 for first current source 110 is eight microamperes (8 μA). A first end of the first current source 110 is connected to a V+ power supply rail. A typical value of voltage for the V+ power supply rail is three and six tenths volts (3.6 V). A second end of the first current source 110 is connected to the source of a first PMOS transistor M1 and to the source of a second PMOS transistor M2 as shown in FIG. 1. A typical value of size for the PMOS transistor M1 and for the PMOS transistor M2 is two hundred microns (200 μm) by three microns (3 μm). The gate of PMOS transistor M1 is connected to a negative differential input signal and the gate of PMOS transistor M2 is connected to a positive differential input signal.
The drain of the PMOS transistor M1 is connected to the drain of a first NMOS transistor M3 and the drain of the PMOS transistor M2 is connected to the drain of a second NMOS transistor M4 as shown in FIG. 1. A typical value of size for the NMOS transistor M3 and for the NMOS transistor M4 is twenty microns (20 μm) by five microns (5 μm). The source of NMOS transistor M3 and the source of NMOS transistor M4 are connected to ground. The gate of NMOS transistor M3 is connected to the gate of the NMOS transistor M4. The gate of the NMOS transistor M3 is also connected to the drain of NMOS transistor M3. The drain of the PMOS transistor M2 and the drain of the NMOS transistor M4 are connected to the second stage of the error amplifier 100 by signal line 130.
The second stage of the error amplifier 100 comprises a second current source 120 having a current value of I2. A typical value of current I2 for second current source 120 is sixteen microamperes (16 μA). A first end of the second current source 120 is connected to the V+ power supply rail. A second end of the second current source 120 is connected to the drain of a third NMOS transistor M5. A typical value of size for the NMOS transistor M5 is twenty microns (20 μm) by three microns (3 μm). The gate of the third NMOS transistor M5 is connected to the signal line 130 and the source of the NMOS transistor M5 is connected to ground.
Resistor R1 and capacitor C1 are compensation components of the error amplifier 100. A typical value of resistance for resistor R1 is fifty thousand ohms (50 kilohms). A typical value of capacitance for capacitor C1 is fifty picofarads (50 pF). Resistor R1 and capacitor C1 are connected in series as shown in FIG. 1. A first end of resistor R1 is connected to the signal line 130. A second end of the resistor R2 is connected to a first end of the capacitor C1. A second end of the capacitor C1 is connected to a node 140 that is located between the second current source 120 and the third NMOS transistor M5.
Node 140 is also connected to an output node 150 of the error amplifier 100 that provides the control voltage VCTRL. As shown in FIG. 1, the error amplifier 100 also comprises a first diode D1 and a second diode D2 that are connected to clamping voltages. The anode of the first diode D1 is connected to a clamping voltage that is designated CLAMP− in FIG. 1. A typical voltage value for the clamping voltage CLAMP− is one half volt (0.5 V). The cathode of the first diode D1 is connected to the output node 150. The anode of the second diode D2 is also connected to the output node 150. The cathode of the second diode D2 is connected to a clamping voltage that is designated CLAMP+ in FIG. 1. A typical voltage value for the clamping voltage CLAMP+ is one and one half volt (1.5 V).
The relatively large value of capacitance for the capacitor C1 and the relatively small values of the bias currents cause the error amplifier to be relatively slow to respond to the ripple voltage in the output of the DC to DC converter in the pulse frequency modulation (PFM) control mode.
Therefore, there is a need in the art for a system and method that is capable of improving the performance of an error amplifier when the control mode of the error amplifier is changed. There is a need in the art for a system and method that is capable of increasing the slew rate of the error amplifier so that the error amplifier will perform sufficiently quickly when the control mode of the error amplifier is changed.