The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit. More specifically, the methods include at least two operations. The first operation deposits barrier material via PVD or CVD to provide some coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming metal lines on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well-suited to metals such as Cu that cannot readily be patterned by plasma etching. In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below.
Presented in FIGS. 1A-1G, is a cross sectional depiction of a dual Damascene fabrication process. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which; a diffusion barrier 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive material provides the conductive paths of the semiconductor wafer, the underlying silicon devices must be protected from metal ions (e.g., copper) that might otherwise diffuse into the silicon. Suitable materials for diffusion barrier 105 include tantalum, tantalum nitride, tungsten, titanium, titanium tungsten, titanium nitride, and the like. In a typical process, barrier 105 is formed by a physical vapor deposition (PVD) process such as sputtering or a chemical vapor deposition (CVD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit 101 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1G.
As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.
The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.
Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a conformal diffusion barrier 123. As mentioned above, barrier 123 is made of tantalum, titanium, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay. FIG. 1G shows the completed dual Damascene process, in which copper conductive routes 125 are inlayed (seed layer not depicted) into the via and trench surfaces over barrier 123.
Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated by only by diffusion barrier 123 which is itself somewhat conductive. Although conformal barrier layers are sufficiently conductive for conventional circuitry, with the continuing need for faster (signal propagation speed) and more reliable microchip circuitry, the resistance of conformal barrier layers made of the materials mentioned above is problematic. The resistance of such barrier layers can be from ten to one hundred times that of copper. Thus, to reduce resistance between the copper routes, a portion of the diffusion barrier may be etched away, specifically at the via bottom, in order to expose the lower copper plug. In this way, the subsequent copper inlay can be deposited directly onto the lower copper plug. Conventional methods for etching away diffusion barriers at the bottom of vias (for example, the region of barrier 123 contacting copper inlay 107 in FIG. 1F) are problematic in that they are not selective enough. That is, conventional etch methods remove barrier material from undesired areas as well, such as the corners (edges) of the via, trench, and field regions. This can destroy critical dimensions of the via and trench surfaces (faceting of the corners) and unnecessarily exposes the dielectric to plasma.
In addition, conventional etching methods do not address unlanded contact regions. As illustrated in FIG. 1F, a portion of diffusion barrier 123 located at via bottom 127 does not fully contact copper inlay 107. In this case, a portion of the barrier rests on copper inlay 107 and a portion rests on dielectric 103. A conventional barrier etch, meant to expose copper inlay 107, would expose both copper inlay 107 and dielectric 103 in region 127. In that case, more process steps would be needed to repair or replace diffusion barrier on the newly-exposed region of dielectric 103, before any subsequent copper could be deposited thereon. Using conventional unselective xe2x80x9cblanketxe2x80x9d conformal deposition methods to re-protect the dielectric, one would create the same problem that existed before the etch, that is, higher resistance between copper routes due to the barrier itself.
What is therefore needed are improved methods of forming diffusion barriers on integrated circuit structures, selective methods in which the portion of the diffusion barrier at the bottom of vias is either completely or partially removed without sacrificing the integrity of the diffusion barrier in other regions. In this way, the resistance between inlayed metal conductive routes is reduced.
The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit in which the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. At least part of the first operation is performed in the same reaction chamber as the second operation. Some preferred methods of the invention are entirely done in a single process tool, without breaking vacuum. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In some aspects of the invention, selective etching is also used to remove contaminants under the barrier material, thus. obviating a separate preclean operation.
The invention accomplishes simultaneous etch and deposition by creation of unique plasma producing process conditions such that barrier material is etched away in some regions while in other regions barrier material is deposited. Thus, the descriptive term xe2x80x9cetch to deposition ratioxe2x80x9d or xe2x80x9cE/Dxe2x80x9d is used from herein. More specifically, in the context of a partially fabricated integrated circuit having via and trench surface features, methods described herein provide that E/D varies as a function of the elevation profile of the surface features to which the plasma is applied. Generally, E/D is greatest at the bottom most regions of the wafer surface features and decreases in magnitude as elevation increases.
In this invention, there are three E/D scenarios created by control of process conditions. In the first scenario, E/D is greater than 1 at the via bottom, on the trench step, and on the field region. In the second scenario, E/D is greater than 1 at the via bottom and on the trench step, but less than one on the field region. In the third scenario, E/D is greater than 1 at the via bottom, but less than 1 on the trench step and on the field region. By using these three E/D scenarios, a variety of stack barrier layer structures are realized.
A preferred material for this etch/deposition sputter is tantalum, although the invention is not limited to tantalum. Other materials for which the invention is applicable include but are not limited to titanium, tungsten, cobalt, solid solutions (interstitial forms) of tantalum and nitrogen, and binary nitrides (e.g. TaNx, TiN, WNx). After diffusion barriers of the invention are formed, a metal conductive layer is deposited thereon. Where methods of the invention create a diffusion barrier having no barrier material at the bottom of the vias, the metal conductive layer makes direct contact with exposed metal conductive routes. Thus, one aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (b) etching through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate, and (c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts an underlying metal layer only at the bottom of the plurality of vias. Preferably at least part of (a) and all of (b) are performed in the same processing chamber. Additionally, the wafer may be precleaned before (a) in some preferred methods. In some preferred embodiments, all of (a)-(c) are performed in the same processing tool.
For unlanded vias (and in some instances for fully landed vias as well), methods of the invention create a diffusion barrier having minimal barrier material at the bottom of the vias. In this case, the resistance of the barrier between the metal conductive layer and underlying metal conductive routes is minimized. Thus, another aspect of the invention is a method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate. Such methods may be characterized by the following sequence: (a) precleaning the wafer substrate, (b) depositing a first portion of the diffusion barrier over the surface of the wafer substrate, (c) etching part-way through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate such that the diffusion barrier has a minimum thickness at the bottom of the plurality of vias, and (d) depositing the metal conductive layer over the surface of the wafer substrate. Preferably at least part of (b) and all of (c) are performed in the same processing chamber. In some preferred embodiments, all of (a)-(d) are performed in the same processing tool.
Preferably methods of the invention are used in Damascene processing in which the metal conductive layer and interconnects are made of copper. In some preferred methods of the invention, the metal conductive layer is a copper seed layer. Preferably seed layers of the invention are formed using PVD, but the invention is not limited in this way. As mentioned, in some methods of the invention, all aspects of a process flow for forming a diffusion barrier and depositing a metal conductive route thereon are done in the same processing tool.
Methods of the invention create diffusion barriers having stack structures. Distinct portions of each stack may be deposited (layered) using PVD, CVD, or other methods. Thus diffusion barriers of the invention may have bilayered or trilayered structures. Preferably, the portions include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. More detail of preferred arrangements for the layering of these materials, methods of depositing, and structure of the diffusion barriers formed therefrom, will be described in the detailed description below.
Methods of the invention create diffusion barriers within integrated circuitry using at least the materials described above. Therefore, another aspect of the invention pertains to an integrated circuit or a partially fabricated integrated circuit. Preferably integrated circuits or partially fabricated integrated circuits of the invention include: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches except that there is no diffusion barrier material at the bottom of the plurality of vias, and a metal conductive layer provided thereon, such that the metal conductive layer comes in direct contact with a plurality of metal conductive routes at the bottom of the plurality of vias. Particularly (but not necessarily) for unlanded vias, yet another aspect of the invention is an integrated circuit or a partially fabricated integrated circuit comprising: a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches, said diffusion barrier having a thickness of between about 50 and 400 xc3x85 on said surfaces except at the bottom of the plurality of vias where there is less than about 50 xc3x85 of diffusion barrier material; and a metal conductive layer provided thereon.