Advances in electronic devices generally include reducing the size of components that form integrated circuits. With smaller circuit components, the value of each unit area on a semiconductor wafer becomes higher because the ability to use all of the wafer area for circuit components improves. To properly form an integrated circuit with advanced circuit designs that use higher percentages of the wafer area for smaller components, it is critical that defect counts on the semiconductor wafer be reduced below levels which were previously acceptable for many circuit designs. For example, minute particles of less than 0.2 microns are unacceptable for many of the current advanced circuit designs. This is because the small particles or defects can damage the integrated circuit by shorting out two or more circuit lines or by cutting or otherwise impairing the operation of these circuits. In order to improve the overall planarity of a semiconductor wafer and to improve the immunity of the wafer to certain types of defects, a process known as chemical mechanical polish (CMP) has become popular.
CMP is a process for improving the surface planarity of a semiconductor wafer and involves the use of mechanical pad polishing systems usually with a silica-based slurry. CMP offers a practical approach for achieving the important advantage of global wafer planarity. CMP systems for global planarization have certain limitations.
A significant limitation of existing CMP systems relates to a part of the system known as the polishing pad. The polishing pad contacts the semiconductor wafer and polishes the wafer. A slurry is usually applied to the polishing pad to lubricate the interface between the wafer and the polishing pad. The slurry also serves the function, because of its silica content, of mildly abrading or affecting the surface of the semiconductor wafer. In addition to the silica, the potassium hydroxide that the slurry contains catalyzes and helps break atomic bonds in the slurry. This further helps to increase the polishing rate for the semiconductor wafer. Most polishing pads are formed of a cellular microstructure polymer material. This material between its cells has numerous voids and pockets that the slurry may fill. As the slurry contacts the semiconductor wafer, it picks up particles and absorbs them.
A problem that often occurs with these particles and the slurry within the cell structure of the pad is a densification of the slurry within the voids. To overcome this problem, most CMP systems use a polishing pad conditioner that rakes or scratches the pad surface to remove the slurry within the pad cellular structure and, in effect, "renew" the polishing pad surface. The pad conditioners are only partially effective because used or contaminated slurry remains within the voids of the polishing pads cellular structure.
Another problem with CMP systems that use pad conditioners of a conventional type is that they are controlled by a robotic arm or other similar mechanism that places the pad conditioner in contact with the polishing pad. These conditioners may be either post polish or in situ systems that typically constitute a computer-controlled robot arm with X-Y movement in an arc and limited Z movement to position the conditioning head and determine downward force. These arms require a mounting plate at the periphery of the polishing platen and a rinse station to clean the head after conditioning. This adds complexity and additional space to the polishing tool as well as additional software control complexity. The post polish conditioners do not correct pad glazing during the duration of the polish. In situ pad conditioners have been cumbersome to implement and can be tool reliability limiters. As they condition the polishing pad the conditioners sweep across the polishing pad to condition the pad prior to the pad contacting the semiconductor wafer. Because of the sweep of the robotic arm and the need to maintain a high degree of prepared surface in contact with the semiconductor wafer, the polishing pad must be large. In many CMP systems, the polishing pad is often many times the area of the semiconductor wafer.
These problems with known polishing pads cause polishing rate to vary according to the condition of the polishing pad, which seriously affects and can degrade uniformity. The result is a far less robust polishing process that may even contribute to lower yields in the semiconductor device circuits.