The present invention relates to a frequency modulation circuit, and more particularly, to a frequency modulation circuit that can perform frequency modulation accurately when the percentage modulation is small.
In interface standards typified by Serial ATA, spread spectrum clocking (SSC) is recommended for reducing electromagnetic interference (EMI) (see Serial ATA Workgroup, “Serial ATA: High Speed Serialized AT Attachment”, Revision 1.0a, Jan. 7, 2003, pp. 83–85).
FIG. 18A is a graph showing a change in clock frequency under SSC in a Serial ATA standard. FIG. 18B shows a spectrum of a clock signal under SSC in the Serial ATA standard. The SSC is a technique of modulating the frequency of a clock signal output from a clock source so as to have a predetermined percentage modulation (δ=0.5%) and a predetermined modulation period (fm=30 kHz to 33 kHz), as shown in FIG. 18A, to thereby reduce the peak value of the spectrum.
The spectrum of a clock signal under SSC is defined to have a frequency component lower than the frequency of a clock signal obtained when no SSC is performed, as shown in FIG. 18B. Also, the peak value of the spectrum of a clock signal under SSC is recommended to be smaller by at least 7 dB than that obtained when no SSC is performed.
As methods for implementing SSC, a division ratio switch method and a direct modulation method are known. These methods will be briefly described in the context of using a phase locked loop (PLL).
FIG. 19 is a block diagram of a frequency modulation circuit adopting the division ratio switch method. The frequency modulation circuit of FIG. 19 includes a frequency phase comparison circuit (PFD) 902, a charge pump circuit (CP) 904, a filter (LPF) 906, a voltage-controlled oscillation circuit (VCO) 908, a frequency division circuit (FD) 912 and a division ratio switch circuit 914.
In the illustrated frequency modulation circuit, the frequency division circuit 912 is configured to be able to perform frequency division with a plurality of division ratios. The frequency division circuit 912 performs switching among the plurality of division ratios with time according to a control signal output from the division ratio switch circuit 914, to thereby change the frequency of an output signal CKOUT of the VCO 908 (see Japanese Laid-Open Patent Publication No. 2000-209033 (FIG. 1) and No. 2001-251185, for example).
FIG. 20 is a block diagram of a frequency modulation circuit adopting the direct modulation method. The frequency modulation circuit of FIG. 20 includes a frequency division circuit 932 and a modulation signal generation circuit 934, in place of the frequency division circuit 912 and the division ratio switch circuit 914 of the frequency modulation circuit of FIG. 19.
In the frequency modulation circuit of FIG. 20, a modulation signal output from the modulation signal generation circuit 934 is given to the VCO 908 as its control voltage, to thereby change the frequency of the output signal CKOUT of the VCO 908 (see Japanese Laid-Open Patent Publication No. 2001-44826 (FIG. 1), for example).
Both the frequency modulation circuits described above perform the frequency modulation within the PLL. If variations exist in the characteristics of the PLL, therefore, such variations affect the output of the frequency modulation circuit, resulting in that the spectrum of the clock signal tends to be deviated from the standard.
In particular, for a high-frequency clock signal, it is conventionally impossible to perform stably frequency modulation with such a small percentage modulation as is defined in Serial ATA standards. Also, it is difficult to design a PLL permitting such modulation. Moreover, in the frequency modulation circuit adopting the division ratio switch method, setting of a small percentage modulation is difficult when the division ratio of the frequency division circuit is small.