In recent years, with technology of wireless LAN, third-generation mobile phone, digital broadcasting, and the like, digitalized communication/broadcasting has a purpose of switching the frequency of a channel signal. As a method for converging a frequency outputted from a wireless communication device or the like to the frequency of a channel signal when switching the frequency of the channel signal as described above, technology using a digital FLL/PLL is known.
FIG. 12 is a diagram illustrating a digital FLL 900 in the conventional art. In FIG. 12, the digital FLL 900 includes a frequency comparator 910, an FIR filter 920, an IIR filter 930, a digital-analogue convertor (DAC) 940, a voltage-controlled oscillator (VCO) 950, and a frequency-digital convertor 960.
The frequency comparator 910 compares a channel signal D_ref inputted to the digital FLL 900 to a loopback signal D_vco and outputs a frequency error signal D_error between the channel signal D_ref and the loopback signal D_vco. The FIR filter 920 and the IIR filter 930 output a control voltage signal D_vtune on the basis of the frequency error D_error outputted from the frequency comparator 910.
Here, the FIR filter 920 includes first to third delay blocks Z-1 921 to 923, first and second adders 924 and 925, and a multiplier 926 having a fixed multiplying factor of ⅓. The FIR filter 920 performs a moving average process on the frequency error D_error by using the third delay blocks Z-1 921 to 923. In addition, the IIR filter 930 includes first and second multipliers 931 and 933, first and second adders 932 and 934, and a delay block Z-1 935. An output of the FIR filter 920 is inputted to the first multiplier 931 and the first adder 932 of the IIR filter 930. The first multiplier 931 multiplies the output of the FIR filter 920 by a weighting factor β. The first adder 932 adds an output of the second multiplier 933 to the output of the FIR filter 920. The second multiplier 933 multiplies an output of the first adder 932 looped back via the delay block Z-1 935, by a weighting factor α. The second adder 934 sums an output of the first multiplier 931 and an output of the first adder 932, and outputs the summed output as the control voltage signal D_vtune to the DAC 940.
The control voltage signal D_vtune is analogue-converted by the DAC 940 and then inputted to the VCO 950. The VCO 950 controls an oscillation frequency fout outputted from the VCO 950, on the basis of the inputted control voltage signal. The oscillation frequency fout generated by the VCO 950 is digital-converted by the frequency-digital convertor 960 and returns as the loopback signal D_vco to the frequency comparator 910.
In this manner, the digital FLL 900 generates the control voltage signal D_vtune on the basis of the frequency error signal D_error between the channel signal D_ref and the loopback signal D_vco, and further controls the oscillation frequency fout outputted from the VCO 950, on the basis of the control voltage signal D_vtune.
FIG. 13 is a diagram illustrating a situation where the oscillation frequency fout from the VCO 950 of the digital FLL 900 in the conventional art converges to a desired frequency. In FIG. 13, between times t0 and t1, the reference frequency of the channel signal D_ref and the oscillation frequency fout from the VCO 950 are in a stationary state at the same frequency f1.
When the frequency of the channel signal D_ref is switched from f1 to f2 at time t1, the oscillation frequency fout from the VCO 950 does not instantly come into a stationary state at the frequency f2. The oscillation frequency fout from the VCO 950 converges to the desired frequency f2 with repeated vibrations, and substantially comes into a stationary state at time t3.
The reason why the oscillation frequency fout from the VCO 950 converges to the desired frequency f2 with repeated vibrations as described above is that due to group delays of the FIR filter 920 and the IIR filter 930, the frequency error signal D_error is not instantly transferred.
FIG. 14A is a diagram illustrating the frequency error signal D_error that is an output from the frequency comparator 910, D_FIR that is an output from the FIR filter 920, and D_IIR_B that is an output from the first multiplier 931 of the IIR filter 930. FIG. 14B is a diagram illustrating D_IIR_A that is an output from the first adder 932 of the IIR filter 930, and D_IIR_C that is an output from the second multiplier 933 of the IIR filter 930. Hereinafter, timings of operations of the digital FLL 900 will be described with reference to FIGS. 14A and 14B.
Between times t0 and t1 between which the oscillation frequency fout from the VCO 950 is in a stationary state at the frequency f1, the frequencies of the frequency error signal D_error, D_FIR, and D_IIR_B are in a stationary state at 0 in FIG. 14A, and the frequencies of D_IIR_A and D_IIR_C are in a stationary state at f1 in FIG. 14B.
Here, when the frequency of the channel signal D_ref is switched from f1 to f2 at time t1, the frequency of D_error rapidly falls to near —(f1-f2) in FIG. 14A. This is because the frequency of the channel signal D_ref is switched to f2 at time t1 but the frequency of the oscillation frequency fout does not instantly become f2. The frequency difference between the channel signal D_ref and the loopback signal D_vco based on the oscillation frequency fout becomes about —(f1-f2), and the frequency comparator 910 outputs a frequency error signal D_error having a frequency of —(f1-f2).
Then, the FIR filter 920 outputs D_FIR on the basis of the frequency error D_error outputted from the frequency comparator 910. In FIG. 14A, D_FIR delays from D_error. This is due to the delay properties of the FIR filter 920 (the third delay blocks Z-1 921 to 923 and the like). Further, D_FIR is multiplied by the weighting factor β by the first multiplier 931 of the IIR filter 930 and outputted as D_IIR_B. Here, the weighting factor β=0.3.
Further, when the frequency of the channel signal D_ref is switched from f1 to f2 at time t1, the frequency of D_IIR_A falls from f1 to f2 slightly after time t1 in FIG. 14B. This is because D_IIR_A is obtained by adding the output of the second multiplier 933 to D_FIR, which is the output of the FIR filter 920, and thus influenced by the above delay properties of the FIR filter 920. Then, D_IIR_C is obtained by looping back the above D_IIR_A via the delay block Z-1 935 and multiplying D_IIR_A by the weighting factor α by the second multiplier 933 of the IIR filter 930, and thus further delays from D_IIR_A. Here, the weighting factor α=1.0.
As described above, according to the digital FLL 900, when the frequency of the channel signal D_ref is switched from f1 to f2 at time t1, due to the group delays of the FIR filter 920 and the IIR filter 930, the frequency error signal D_error is not instantly transferred, and the oscillation frequency fout from the VCO 950 converges to the desired frequency f2 while repeatedly vibrating in a regular attenuation vibration cycle T (=1/ωn (ωn: natural frequency). In other words, in the digital FLL 900, it takes a certain time (time t3−time t1) until the oscillation frequency fout from the VCO 950 converges to the desired frequency f2. The above conventional art is disclosed, for example, in Non-Patent Literature 1.