Q:

rules for makefile

let's assume I have some Makefile for Unix
prog:a.o b.o c.o
    gcc a.o b.o c.o -o prog
a.o:a.c a.h b.h
    gcc -c a.c
b.o:b.c b.h
    gcc -c b.c
c.o:c.c c.h b.h
    gcc -c c.c

I read that if I change *.c file I must recompile only this file, but if I change *.h file I must recompile all files which are depending on my *.h file, after both cases anyway I must link all files from the beginning
1)let's assume that I change only b.h, so what do I need to do?
my variant is make a.o b.o c.o am I right?
2)let's assume that I change only c.c, so what do I need to do?
my variant is make c.o am I right?
and finally if I write make c.o for example my makefile ONLY recompile c.o but what about linker? I have only gcc -c c.c and not -o
thanks in advance for any help

A:

What exactly do you mean 'what do I need to do?'. In every case, just run make prog, and let make figure it out, that's the whole point.
EDIT: If you're curious what make will do in each case, assuming you're running make prog every time, read on:
In case 1) b.h has changed, so anything depending on it (a.o, b.o and c.o) will be rebuilt, and prog will be relinked.
In case 2) c.o is only a direct dependency of c.c, so only c.o is built and prog relinked.
BTW, gcc can give you it's take on your dependencies by just running gcc -MM *.c in your project directory.

