1. Field of the Invention
The present invention relates to an amplifying device and its control method.
2. Description of Related Art
In FIG. 11, there is disclosed a general configuration of an intermediate frequency (hereinafter called IF) type receiver 11 for digital TV. An RF signal received by an antenna (not shown in the figure) is input to an input terminal 1, amplified by a low noise amplifier (hereinafter called LNA) 2 and down-converted by a down-conversion-mixer 3. The frequency of a local signal input from a local signal input terminal 4 to the down-conversion-mixer 3 is set to a frequency that is higher than the carrier frequency of a desired RF signal by the intermediate frequency.
An IF signal output from the down-conversion-mixer 3 is converted to a digital signal through a low pass filter (LPF) 5 for selecting a channel, a gain variable amplifier 6 and an analog/digital converter (ADC) 7. The converted digital signal is down-converted to a signal frequency IQ by an IQ mixer 8, and processed by a base band (BB) signal processor 9. Further a gain setting unit 10 controls the gain of the LNA 2 and the gain variable amplifier 6 depending on the time slot, bit error rate, received signal strength and the like of the received signal.
In the IF type receiver mentioned above, the down-conversion to an IF signal by the down-conversion mixer 3 is performed before filtering out signal components other than the channel signal. Considering the existence of disturbing waves, therefore, enough gain cannot be gained at the stage preceding the down conversion mixer 3. Thus, the strength of a desired component of IF after the down-conversion is generally weak. The gain of the gain variable amplifier 6 needs to be adjusted so that the range of the weak desired component conforms to the dynamic range of ADC 7. Here, examples of the desired properties of the gain variable amplifier 6 include a wide gain variable range and a wide input dynamic range.
Now two types described below are well known as a gain variable amplifier 6. One type is a valuable gain amplifier (hereinafter called VGA) type which changes gain continuously depending on the control voltage. Another type is a programmable gain amplifier (hereinafter called PGA) type which changes gain stepwise by logic control.
In FIG. 12, there disclosed a typical circuit diagram of the valuable gain amplifier (VGA). The circuit disclosed in FIG. 12 divides a signal current from transistors Q1, Q2 into a current to transistors Q3, Q4 and a current to transistors Q3, Q4. Its division ratio changes depending on the control voltage and, as a result, the gain of the circuit is changed. The gain property changes depending on temperature and variations in the manufacturing process, and therefore these changes should be taken into consideration in the circuit design because the gain of this circuit is controlled by the properties themselves of the transistors in the circuit scheme shown in FIG. 12. Further the circuit has such problems that when a level of input signal is high, the output signal would be distorted, and that the maximum output level is low because it is difficult to achieve high gain in the circuit
Next, in FIG. 13, there disclosed a typical circuit diagram of the programmable gain amplifier (PGA). The circuit disclosed in FIG. 13 produces a gain by the cascade connection of a plurality of inverted amplifier circuits of an operational amplifier (OP-Amp). The gain of an amplifier circuit Al at the first stage is determined by the ratio of an input resistor R11 to feedback resistors R12, R13. For instance, in the case that R12=R11, R13=39.81×R11 and the gain selection switch S11 connects to the R12 side, the gain of the amplifier circuit A1 becomes zero because R12/R11=1. Further, in the case that the selection switch S11 connects the R13 side, the gain of the amplifier circuit Al becomes 32 dB because R13/R11=39.81. Therefore the amplifier circuit A1 becomes a gain changeable amplifier by switching gain selection switch S11 wherein the amplifier circuit A1 may take the gain value of 0 dB and 32 dB.
As mentioned above, the gain of an amplifier circuit is determined by the ratio of an input resistor to feedback resistor when the gain of each operational amplifier (Op-Amp) itself is sufficiently high.
In FIG. 14, there disclosed a differential amplifier circuit as a programmable gain amplifier which does not include an operational amplifier (Op-Amp). The gain of this circuit is determined by the following equation. (R1×(R2+2×R3)/(R2×2×R3).
Therefore the gain of the differential amplifier circuit can be determined only by the ratio of the resistors. Variations of resistors in a one integrated circuit can be kept below several percents by using current semiconductor manufacturing technology, so those amplifier circuits disclosed in FIGS. 13 and 14 can produce a stable gain. Further, those amplifier circuits disclosed in FIGS. 13 and 14 have a good distortion property because they form a feedback circuit, and the maximum output level can be maintained roughly constant regardless of the gain setting.
In FIG. 13, an amplifier circuit in the second stage is composed of an Op-Amp A21, an input resistor R21, feedback resistors R22, R23, and a gain selection switch S21; an amplifier circuit in the third stage is composed of an Op-Amp A31, an input resistor R31, feedback resistors R32, R33 and a gain selection switch S31. Amplifier circuits in the fourth and subsequent stages can be formed similarly. Here, the feedback resisters of each of the amplifier circuits (A1, A2, . . . ) are set so that each amplifier circuit has a respective one of amplification gains from 1 dB to (n-th power of 2) dB (n=0, 1, 2, 3, 4, 5 and 6). Then, the total gain of the amplifying device can be set to any value between 1 dB and 64 dB in increments of 1 dB by selectively controlling the gain selection switchs S11-S61.
As mentioned above, the gain of a PGA type amplifying device can be set by the ratio of resistors. However, the actual circuits include the on-resistance (Rs) of the gain selection switches. In the actual circuit of FIG. 13, there are on-resistances (Rs); R12′=R12+Rs11, R13′=R13+Rs11. Likewise, in the actual circuit of FIG. 14, there are also on-resistances (Rs); R3′=R3+Rs÷2.
These on-resistances of such switches vary significantly from a fraction to several ten-fold depending on temperature, bias conditions and variations in the manufacturing process In the case of low gain setting, on-resistances do not cause the problem because the on-resistances are sufficiently low compared to the feedback resistance and emitter resistance. However, on-resistances give an effect on gain in the case of high gain setting because the feedback resistance and emitter resistance became low under the condition. Therefore, in this case, the designed gain value cannot be achieved.
Here, we describe control data and gain setting in the specification of the present application. In the specification, we define “0” as low gain setting and “1” as high gain setting. For example, in FIG. 15, “A=010111” means that an amplifier 51 and an amplifier 53 are set as low gain, and an amplifier 52 and amplifiers 54-57 are set as high gain. In FIG. 15, each of the amplifiers 51-57 is set so as to have a respective one of amplification gains from 0.5 dB to (n-th power of 2) dB (n=0, 1, 2, 3, 4, 5, 6 and 7), and the amplifiers 51-57 are connected in series. In FIG. 15, a two-state amplifier 51 whose gain can be switched between 0 dB and 32 dB is represented as (0/32+α). This expression clearly shows that since the amplifier 51 has high gain, the amplifier 51 tends to be strongly affected by a switching resistance and the like and the deviation from the set value (32 dB in this case) thereby becomes comparatively noticeable.
Conventional, PGAs disclosed in FIG. 13 and FIG. 15 tends to produce gain errors caused by properties and the layouts of circuit elements included in each of the amplifiers. These gain errors emerge significantly at the time of all-bit inversion, for example, when the gain setting is changed from A=0111111 to A=1000000. In FIG. 16, there disclosed a gain change which occurs when the total gain setting of amplifying device gradually increases. FIG. 17 is a magnified view of the gain change at the time of all-bit inversion in FIG. 16.
As shown in FIG. 16, when the total gain setting increases gradually, the accumulated gain error becomes so large that it cannot be ignored. When the gain error becomes so large that it cannot be ignored compared to gain step of the PGA, the linearity of overall gain change of the amplifying device cannot be maintained as shown in FIG. 17. In FIG. 17, when the gain changes from 31.5 dB (A=0111111) to 32 dB (A=1000000), the gain error α of the amplifier 51 becomes too large to be ignored, and gain adjustment of 0.5 dB cannot be properly performed. Further, after that, it draws a nonlinear gain characteristic curve including the gain error α. Furthermore, in cases other than the all-bit inversion, a similar problem also occurs when more than a certain number of bits are inverted, for example, when the gain setting is changed from A=0011111 to A=0100000.
If the gain does not change linearly, a gain control circuit repeats gain-up and gain-down control to achieve the optimal gain because it cannot achieve designed gain. This makes it impossible to stabilize the signal level, so the signal processing becomes impossible. Therefore, it is necessary for the PGA to have a circuit system that can maintain the linearity of gain change in order to make the signal processing possible.
Here, we describe the art disclosed in Japanese Unexamined Application Publication No. 11-251851 (Patent Document 1) as a related art. A gain control amplifying device disclosed in the Patent Document 1 has a configuration in which a plurality of amplifiers are connected in series, as is similar to the configurations disclosed in FIGS. 13 and 15. But each amplifier has the configuration shown in FIG. 18 so that on-resistances of gain selection switches do not give an effect on the gain setting. The gain is controlled by on-off switching of the two amplifiers connected in parallel and the switch to change negative feedback line of Op-Amp is eliminated.
We describe the configuration and its circuit behavior shown in FIG. 18. A first differential amplifier 81 includes transistors Q9 and Q10, and emitters of the transistors Q9, Q10 are connected to the collector of a transistor Q18 for constant current source. A second differential amplifier 82 includes transistors Q11 and Q12, and emitters of the transistors Q11, Q12 are connected to the collector of a transistor Q20 for constant current source. An input signal input from an input terminal is supplied to the bases of transistors Q9, Q12 via resistors R4, R5. The collectors of transistor Q9, Q12 are connected to the collector of transistor Q13, and the collectors of transistors Q10, Q11 are connected to the collector of transistor Q14.
Transistors Q13, Q14 forms a current mirror circuit 83 in which the transistor Q13 serves as the input side and a power-supply line serves as a reference potential point. Assuming that R4=R5, differential amplifiers 81 and 82 are connected in parallel.
The collector outputs of transistors Q10, Q11 and Q14 are supplied to the bases of output transistors Q15, Q16 via a drive circuit. Push pull output of transistors Q15, Q16 is output to the output terminal. Further negative feedback resistances R6, R7 are connected between the output terminal and transistors Q9, Q12.
A switch circuit to control ON/OFF switching of the two differential amplifiers 81, 82 is composed of current mirror circuits 84 and 85. A current mirror circuit 84 is composed of transistors Q17-Q19 in which the transistor Q17 serves as the input side and a ground potential serves as a reference potential point. The base of the transistor Q17 is connected to a gain control terminal. A current mirror circuit 85 is composed of transistors Q20, Q21 in which transistor Q21 serves as the input side and a ground potential serves as a reference potential point. A predetermined current is supplied to a transistor Q21 through a resistor R8. The collector of the transistor Q19 is connected to the transistor Q21.
In the above-mentioned configuration, because the transistor Q17 is turned on when the gain control terminal is “H”. As a result, a transistor Q18 is turned on, and the transistors Q17, Q18 operate as the differential amplifier 81 in which transistor Q18 serves as the constant current generator. On the other hand, when a transistor Q17 is turned on, because transistor Q19 is also turned on, the transistor Q20 is turned off. As a result, neither transistor Q11 nor Q12 work as the differential amplifier 82. The gain at this time is determined by the ratio of resistances R6 and R4.
When the gain control terminal is “L” level, because the transistor Q17 is turned off, the transistor Q18 is turned off. As a result, neither transistor Q9 nor Q10 work as the differential amplifier 81. On the other hand, when transistor Q17 is turned off, because transistor Q19 is turned off, the transistor Q20 is turned on. As a result, transistor Q11 and Q12 work as the differential amplifier 82 in which transistor Q20 serves as a constant current source. The gain at this time is determined by the ratio of resistances R5 and R7.
Further, as a method of maintaining the linearity of the overall gain of the amplifying device, it is conceivable to combine overlapping the range of gain change for each amplifier with the control technique. The gain setting of each amplifier is made to overlap over other amplifiers and the gain control has such a hysteresis that the gain change followsconforms to a gain-up line shown in FIG. 19 when the gain increases and followsconforms to a gain-down line shown in FIG. 19 when the gain decreases. This setting makes it possible to maintain the linearity of the overall gain of the amplifying device. In FIG. 19, the gain setting has an overlap over a point where all-bit inversion from A=0111111 to A=1000000 occurs. The overlapping of gain setting like his is set for other bit inversions (e.g. from A=0011111 to A=0100000). However, as the number of gain overlapping increases, this method needs to increase the number of stages of the amplifiers to cover desired range of a variable gain. This causes the problem such as the expansion of the chip area and an increase of current consumption.
Further, in Japanese Unexamined Application Publication No. 2003-158435 (Patent Document 2), there disclosed such a configuration that the gain change of the amplifying device is made to be linear, and both of design complexity and high costs design are avoided by narrowing the input dynamic range required for the amplifying device. In the Patent Document 2, a variable attenuator is provided between an input terminal and a variable gain amplifier. When gain is adjusted, not only the variable gain amplifier but also the variable attenuator are controlled at the same time. This makes the variable gain range of the variable gain amplifier narrower. Further, the circuit design for linearity adjustment is made easier because the dynamic range of peripheral circuits after the variable attenuator are made narrower. And in the Patent document 2, when the gain of the gain variable amplifier is controlled, a gain coarse-adjustment control signal and a gain fine-adjustment control signal are used, where the gain fine-adjustment control signal is used to make fine adjustments to the gain coarse-adjustment control signal by feedback control.
In Japanese Unexamined Application Publication No. 2002-353756 (Patent document 3), there disclosed such a gain control method that the AGC characteristic curve of the AGC amplifier is interpolated by linear interpolation method. However, the linear interpolation method cannot work properly in the case that the AGC characteristic curve is very steep. In addition, it takes a lot of trouble to adjust a plurality of AGC amplifiers required to obtain a large gain. Thus, when creating linear interpolation tables based on the AGC character of each of a plurality of AGC amplifiers, the linear interpolation table of one AGC amplifier is composed so that the excess and deficiency of the gain of another AGC amplifier is compensated. For example, the first AGC amplifier and the second AGC amplifier are actually combined. Then, while measuring the transmitting power value (output electric power value), a DAC code is determined so that analog variations can be mutually absorbed. Thus, approximation is improved even in the area where the gain-control voltage character curve of the AGC amplifier is steep, and as a result, the dynamic range of the AGC amplifier can be used effectively.