The present invention relates to an electronic interconnect system. More specifically, the invention relates to the three dimensional use of planar and edge surfaces of a circuitized sub assembly and the interconnection between circuit components or devices that are edge and surface mounted on the sub assembly. This arrangement allow for very dense packaging of such devices on the sub assembly.
To reduce the cost and size of electronic computers while concomitantly increasing their performance capabilities, it is desirable to place as many electronic components in as small an area as possible. This can be achieved by creating many electronic circuits on a given region of a semiconductor chip. These chips are generally attached to the two planar surfaces of a printed circuit board (PCB), ceramic module or other substrate in a side by side arrangement with sufficient space between the chips to allow for the various electrical connections to be made from the PCB to the chips. Chip contact locations can be electrically interconnected to substrate contact locations by wires, flip-chip configurations, fuzz buttons, or other suitable means such as TAB tape.
As performance requirements of computers continue to increase, the time required to propagate and to deliver signals between chips and substrates remains critical. Yet, in conventional practice, only the two exterior faces of the substrate are used. The number of connections is typically increased by making the substrate larger in the planar (the x-y) directions. However, there are practical limits to the maximum size to which this plane can be expanded. At present, there may be as many as 30,000 connection points on the surface area of the board. Test probes for checking the continuity of all of these contacts are complex and are very expensive to build and maintain. Yet, there are continuing efforts to create even more pins and connections on the circuit boards, without increasing the size of the landscape. Others have attempted to overcome this problem in various ways.
U.S. Pat. No. 4,770,640 proposes the use of a monolithic integrated circuit device with a pattern of conductive paths on its surface. The device is placed against the edges of a multilayer microelectric module to provide connections between the layers of the module and with external devices.
U.S. Pat. No. 5,424,920 describes a number of integrated circuit chips secured together in a stack for such uses as DRAM and SRAM memory modules. The interior circuitry is connected through a dielectric end cap on the stack to external circuitry. Similarly, U.S. Pat. No. 5,246,566 and U.S. Pat. No. 5,517,057, owned by the assignee of the present invention, describe a laminated integrated circuit chip package with one or more metallization patterns on the edges of the package, and external circuits.
U.S. Pat. No. 5,718,936 describes a matrix head for electrostatic printing comprising a plurality of stacked printed circuit boards. The head includes conductive leads in the x-y plane of the stack that terminate at common edges of the stack. However, there is no reference to specific devices connected to these edge contacts.
An improvement in chip packaging density is possible if three dimensional wiring between closely spaced chips and other devices on electronic sub-assemblies can be achieved.
The present invention utilizes the third or edge dimension of a substrate to achieve a high density of connection points. This is achieved by creating a grid of the connection points in the other two planes (x-z or y-z planes).
The present invention relates to a printed circuit board having top and bottom generally parallel surfaces and at least one common edge surface between the top and bottom surfaces. A plurality of conductive leads are embedded in the circuit board and terminate in one or more connection points along the edge surface. These points electrically join one or more active or passive devices mounted to the top and/or the bottom surfaces (hereinafter referred to as surface mounted devices) to devices mounted on the edge surface of the printed circuit board (hereinafter referred to as edge mounted devices). A via may be used to electrically connect the surface mounted device to the conductive lead joined to the edge mounted device.
The invention further includes a method of increasing the number of devices on a circuitized substrate. The method comprises the steps of providing the substrate with top and bottom surfaces and at least one edge surface between the other two surfaces. A plurality of conductive leads are embedded in the substrate and terminate in one or more connection points along the edge surface. These leads serve to join active or passive devices on one of the planar surfaces to other active or passive devices mounted on the edge surfaces of the circuitized substrate. According to the method, numerous types of devices may be attached to the edge of the substrate including, for example, semiconductor chips, diodes, resistors and capacitors. Any laminated substrate, such as a circuit card or a flex circuit or a ceramic module, can be modified according to the present invention to achieve a high density pattern of connection points.
The substrate may be fabricated by building individual laminates with one or more conventional connectors embedded in each laminate. The edge of the laminate is then cross-sectioned to expose a matrix of electrical contact points to which connections may be made.
The invention also relates to an electronic sub assembly and to the method of making it. The sub assembly comprises a circuitized laminated substrate having top and bottom surfaces and at least one edge surface between the other two surfaces. The laminated substrate may be a conductive layer, for example a thin sheet of conductive material, such as copper laminated to a non-conductive sheet, such as a fiberglass reinforced prepreg or a ceramic. One or more active or passive devices are mounted on at least one of the top or bottom surfaces. A conductive lead is embedded in the non-conductive sheet of the substrate and is connected to an active or passive device mounted on the edge surface. The conductive lead is electrically connected to at least one of the devices on the planar surface of the substrate. The active or passive devices on the planar surfaces and on the edge surface may be any combination of semiconductor chips, diodes, resistors, capacitors and printed wiring boards. A via or plated through hole joins each device on the top or bottom surface to the conductive lead that is embedded in a non conductive layer and that is connected to an edge mounted device. The invention also relates to a printed circuit board and to its fabrication. The board has two spaced-apart parallel surfaces comprising a top surface and a bottom surface and at least one edge surface between the top and bottom surfaces. A plurality of conductive leads are embedded in the circuit board parallel to the planar surfaces and terminate in one or more connection points along the edge surface. An active or passive device is mounted on the edge surface and is joined through at least one of said connection points to at least one of the conductive leads. At least one active or passive device mounted on one of the parallel surfaces is joined to the edge mounted device. The printed circuit board may include a via or a plated through hole extending into the substrate from a surface mounted device into contact with a conductive lead connected to an edge mounted device.
The invention also relates to a device comprising a multi-layered circuitized sub assembly, and a semiconductor chip, preferably an optical chip coupled thereto. The sub assembly has two substantially parallel surfaces and at least one edge surface between the parallel surfaces. At least one conductive lead is embedded in the sub assembly generally parallel to the two parallel faces at surfaces, with one end forming electrical connection points. These points terminate in one or more electrical contact pads on said one edge surface. The semiconductor chip contains contacts electrically connected to the contact pads on the edge of the sub assembly. At least one active or passive device is mounted on a planar surface of the sub assembly and is in electrical contact with this conductive lead. The optical chip can be connected to the contact pads of the sub assembly using solder balls or any number of other connectors. The sub assembly may be formed into a plurality of laminates to make a stack. The laminates in the stack all have coplanar edge surfaces. They also have a stepped edge surface whereby each successive laminate in the stack is shorter than the laminate immediately there beneath. This serves to form an exposed planar surface or land on the lower laminate to accommodate an active or passive device that can be mounted on the exposed surfaces. One or more of the devices can be standard pin connectors that permit the device to be interfaced with a computer or suitable diagnostic device. One or more vias extend from each of the exposed planar surfaces of a laminate into the respective laminate to make contact with a conductive lead, thereby providing a connection between the semiconductor chip and the surface mounted connector. The coplanar edge of the stack of laminates can form a right angle with respect to the planar surfaces of the laminate. Alternatively, each edge may form a bias angle less or greater than 90xc2x0 with respect to the planar surface. This bias angle increases the size of the contact surface of the pad to which the component connection points can be made. The connection points on the edge surface may be exposed by any suitable means, such as cutting or shearing of the edge of the laminates collectively or individually, followed by stacking in such a manner as to make the edges coplanar.