The loop filter in a PLL (phase-locked loop) is perhaps one of the most crucial pieces as it is effectively the ‘brains’ of the PLL. The performance of the loop filter is a trade-off between locking time and noise rejections. In an ideal world, all sources of noise in the PLL would be understood and characterized. The designer can select a cutoff frequency for the loop filter that allows the PLL to minimize noise or can allow more noise but provide faster lock times.
Unfortunately, in practice, noise sources are very difficult to understand and characterize. Often the designer may have to deal with not just the ‘natural’ noises (thermal, shot, flicker, etc.) inherent in any device, but also noise coupled into the circuit from outside sources. Therefore, it may be desirable to adjust the loop filter after manufacture. While this may not be particularly difficult for PLLs with lumped-element filters mounted on a printed circuit board (PCB), it's quite difficult if the filter is inside an integrated circuit. Worse, high quality integrated capacitors can be very space consuming and process variations may lead to inaccurate capacitance values.
External loop filters have very significant drawbacks as well. Driving signals off chip requires a great deal of power because of the added package parasitics. The same package parasitics which increase power consumption also complicate the analysis, since the parasitics vary with the package and PCB layout. The leads and bond wires used to bring the signal off the chip act as antennae and can actually couple additional noise into the circuit. Careful PCB layout techniques will mitigate this but never truly resolve the problem.
Other alternatives to the continuous time filters (both on and off chip) are discrete time filters, both analog and digital. While a digital filter is very attractive from a performance point of view, they aren't compact and the designer is left with a digital output which isn't adequate for driving a voltage (or current) controlled oscillator (VCO). Some sort of digital/analog conversion is required and that inherently requires an additional filter on the output, which leads back to the need for a high-performance on-chip analog filter. One nice aspect of discrete time filters, whether they be digital or analog, is decimation. The filtering action is dependent on the ratio of the sampling frequency to the input frequency. After the input signal has been filtered through one stage of the filter, the sampling frequency can be cut down and a second stage of filtering can be employed to dramatically decrease the cut-off frequency.
Creation of low bandwidth, low noise filters for silicon control systems face many difficulties. Passive low bandwidth filters require large components to be placed on the board, which is subject to additional cost and inductive noise sensitivity. On-chip passive filters require large areas and suffer from capacitive noise sensitivity. Active filters are not very successful at reducing area. Switched capacitor filters can be small, but they inject switching noise intolerable for high precision applications.
Accordingly, a need exists for a flexible, tunable, and high performance discrete time analog filter that can be manufactured on-chip. The present invention addresses such a need.