FIG. 1 is a block diagram of a conventional data processing apparatus 10. FIG. 2 illustrates packets transmitted from the data processing apparatus 10 illustrated in FIG. 1. FIG. 3 is a diagram for explaining a skew problem of valid video data generated by the data processing apparatus 10 illustrated in FIG. 1. Referring to FIGS. 1 through 3, the data processing apparatus 10 includes a master 12 (e.g., a timing controller), a plurality of slaves S1 through Sn (e.g., column drivers), and a display panel 14.
The master 12 receives parallel video data P-Data, serializes the parallel video data P-Data, and outputs serialized video data DATA, a clock signal CLK, and a valid video data indication signal VVDS. The valid video data indication signal VVDS indicates a time (or, time-point) at which valid video data starts in the video data DATA.
The serialized video data DATA is transmitted from the master 12 to the individual slaves S1 through Sn via data lines D-Line. The clock signal CLK is transmitted from the master 12 to the individual slaves S1 through Sn via clock lines C-Line. The valid video data indication signal VVDS is transmitted from the master 12 to the individual slaves S1 through Sn via start signal lines S-Line.
Each of the slaves S1 through Sn is enabled by the valid video data indication signal VVDS, deserializes the vide data DATA in response to the clock signal CLK, and detects and outputs valid video data. The display panel 14 displays an image based on the detected valid video data.
However, since the master 12 transmits the valid video data indication signal VVDS to the slaves S1 through Sn via the independent start signal lines S-Line, the start signal lines S-Line may be as many as the number of the slaves S1 through Sn. In addition, since the valid video data indication signal VVDS is transmitted at a complementary metal oxide semiconductor (CMOS) level, it may be distorted due to electromagnetic interference (EMI) during high-speed data transmission between the master 12 and the slaves S1 through Sn. As a result, it may be difficult to detect the valid video data in the slaves S1 through Sn.
Referring to FIG. 2, which illustrates packets transmitted from the master 12 to the individual slaves S1 through Sn, the packet including the valid video data does not include information on where the valid video data starts, and therefore, timepoints at which the valid video data reaches the respective slaves S1 through Sn may be different. Accordingly, the valid video data can be accurately detected when skews between start timing of the valid video data indication signal VVDS and arrival timing when the valid video data reaches the respective slaves S1 through Sn match with one another.
However, as illustrated in FIG. 3, when the valid video data indication signal VVDS is distorted, the valid data may not be detected after a period L2 but may be detected after a period L1. At this time, the valid video data may not be accurately detected. In other words, the valid video data indication signal VVDS may be distorted and thus a skew corresponding to a difference between the period L1 and the period L2 may occur. Due to the skew, the valid video data may not be accurately detected or invalid data may be received.