The present invention relates to a clock synchronization signal generating circuit for achieving clock synchronization between digital operation systems such as data modem.
In the case where data are transferred from the transmitting section (master) in a digital operation system to the receiving section (slave) in another digital operation system, it is necessary to operate the data modem of synchronization type so as to accord or clock-synchronize bit repetitive frequency in the receiving section with that in the transmitting section. In order to establish clock synchronization between digital operation systems which are in master and slave relation, a clock signal generated through the voltage controlled oscillator (VCO) which is formed of analog circuits in the slave system is automatically adjusted responsive to a clock signal employed in the master system to thereby accord these clock signals in master and slave systems with each other.
As the technique of processing digital data and manufacturing LSI has been developed these days, the frequency variable oscillator circuit of digital type is often used instead of analog VCO. Different from the analog VCO, the digital frequency variable oscillator circuit can not change the instantaneous frequency continuously and is intended to accord in frequency the clock signal in the slave system with that in the master system by extracting or inserting one clock pulse from or into the clock output signal for every constant time period.
As usually well known, the data modem of synchronization type has the transmitting section which operates as master unit and the receiving section which operates as slave unit, and can carry out master and slave operations simultaneously or selectively. It is advantageous in this data modem of synchronization type that as many circuits as possible are designed to be used commonly in master and slave units. It is also advantageous that master and slave units in the data modem are driven by the same clock signal. However, as will be later described in detail referring to FIGS. 1 and 2, it is necessary in the conventional clock synchronizing method that a specific clock generator is arranged in master and slave units in each operation system for the purpose of selectively operating two operation systems in master and slave modes and always clock-synchronizing the slave system with the master system.