1. Field of the Invention
The present invention relates to a frequency divider, and more particularly, to a fractional frequency divider with phase selection functionality.
2. Description of the Prior Art
Clock generating systems such as phase locked loops and delay locked loops have a variety of applications in wireless communication systems. In order to minimize interference between crucial components within a system-on-chip (SOC), signals with large power should be well-defined and separated from each other in the frequency domain to obtain a better performance. As a result, fractional frequency dividers are significant building blocks within a wireless transmitter or receiver.
Conventional frequency dividers in low frequency range are usually implemented with dual-modulus or multi-modulus prescalers; for example, a divide-by-4.5 circuit can be realized by a prescaler with its modulus equally distributed between 4 and 5. Since these prescalers are required to change their modulus during simultaneous outputting of divided signals, noise generated from modulus transition may degrade the outcome of the prescaler, leading to undesired jitter.
In addition, dual-modulus or multi-modulus prescalers work in a digital fashion and are not suitable for operation at high frequency. Some conventional high-speed frequency dividers utilize a self-mixing mechanism to overcome the speed issue. Unfortunately, this is at the expense of inductor area, wherein inductors are necessary to filter out a desired signal amongst mixed results. Therefore, circuit designers still seek a more elegant solution to derive a frequency dividing topology with less jitter noise and more efficiency.