1. Field of the Invention
The present invention relates generally to a method of manufacturing an input circuit of a semiconductor device, and in particular to a method of manufacturing an input circuit with its internal circuitry being free from the influence of a surge voltage in an input signal.
2. Description of the Background Art
FIG. 7 is a block diagram schematically showing a semiconductor device to which the present invention is applied. Referring to FIG. 7, a semiconductor integrated circuit device 31, to which the present invention is applied, receives an externally applied signal from an external input terminal 32 to transmit the signal through an input protection circuit 33 to the internal circuit. Generally, as shown in FIG. 7, the semiconductor integrated circuit device 31 is usually provided with a circuit called an input protection circuit 33 between the external input terminal 32 and the internal circuit, in order to prevent the breakdown of the internal circuit due to a surge voltage from the external input terminal 32.
The present invention relates to a method of manufacturing a semiconductor device capable of solving a problem caused by injection of electrons from the part where the input signal is communicated to the substrate by a well layer and a diffusion layer, when a surge voltage such as undershoot is applied to the external input terminal 32 and does not relate exclusively to the input protection circuit 33 specifically shown in FIG. 7. An input circuit is described in detail, for example, in U.S. Pat. No. 4,692,781 entitled "Semiconductor Device With Electrostatic Discharge Protection".
Now referring to FIG. 8, a problem concerning a semiconductor device caused by an undershoot will be described. FIG. 8 is a schematic diagram of a dynamic RAM (referred to as DRAM hereinafter) as an example of a semiconductor device. Referring to FIG. 8, the DRAM includes an input circuit 40 and a plurality of memory cells 43. The input circuit 40 includes an N.sup.+ diffusion layer 47, and an input terminal 46 connected to the N.sup.+ diffusion layer 47. Each of the memory cells 43 includes an NMOS transistor 44 and a capacitor 45. The N.sup.+ diffusion layer 47 is connected to the input terminal 46. The N.sup.+ diffusion layer 47 forms a part of an NMOS transistor 42 for discharging current generated by voltage, when a high voltage is applied.
In the DRAM having such a configuration, an undershoot in an input signal for example has significant influence upon the characteristic of memory cells. Referring to FIG. 8, if an undershoot in an input signal from the input terminal 46 is input, for example, electrons which are minority carriers are injected into a P-type semiconductor substrate 41, as shown by a dotted line in the figure. The electrons reach the memory cell 43 causing the charge information stored in the memory cell 43 to be broken down. If the memory cell 43 and the input circuit 40 are closely disposed, it becomes easier for the injected electrons to reach the memory cell 43 thereby causing the breakdown. For preventing this problem, a sufficient distance is provided between the memory cell 43 and the input circuit 40, and at the same time a substrate voltage generation circuit is usually provided on the semiconductor substrate 41, which applies a negative voltage V.sub.BB to the substrate.
FIG. 11 shows one example of a conventional input circuit. Referring to FIG. 11, the conventional input circuit 70 comprises a P type semiconductor substrate 71, a P well 72 formed on a main surface of the P type semiconductor substrate 71 and an N well 73 formed adjacent to the P well 72. On the main surface of the P well 72, an N.sup.+ diffusion layer 78 and an NMOS transistor 75 adjacent to the N.sup.+ diffusion layer 78 and connected to the ground potential are formed. An input terminal 77 is connected to the N.sup.+ diffusion layer 78, and an input resistance 76 exists in an interconnecting layer therebetween. An input signal is transmitted from the interconnecting layer connecting the input terminal 77 and the N.sup.+ diffusion layer 78 to the internal circuit. In the conventional input circuit 70, a parasitic bipolar transistor 74 is formed by the N.sup.+ diffusion layer 79, the P well 72 and the N.sup.+ diffusion layer 78. A negative voltage V.sub.BB is applied by the substrate voltage generating circuit to the P type semiconductor substrate 71. Generally, the substrate potential V.sub.BB is about -3V.
The operation of the conventional input circuit 70 will be described. An external input signal is applied through the input terminal 77 and transmitted to the internal circuit through the input resistance 76 as well as to the N.sup.+ diffusion layer 78. The NMOS transistor 75 has a very thick gate oxide film, and the gate potential is 0V, and therefore it is normally off. However, when a high electrostatic pulse is applied to the input terminal and a high voltage is applied to the N.sup.+ diffusion layer 78, a punch through phenomenon occurs in the NMOS transistor 75 so that the transistor is turned ON, whereby the high voltage is discharged to the ground potential and gate breakdown or the like is prevented in the internal circuit. When an overshoot is applied to the N.sup.+ diffusion layer 78, the P-N junction between the N.sup.+ diffusion layer 78 and the P well 72 is reversely biased, so that electrons are not introduced to the semiconductor substrate 71.
When an undershoot is applied to the N.sup.+ diffusion layer 78, introduction of electrons to the substrate 71 can be prevented until the undershoot reaches -(.vertline.V.sub.BB .vertline.+V.sub.D) V where diffusion potential of the P-N junction is represented as V.sub.D, since the P-N junction between the N.sup.+ diffusion layer 78 and the P well 72 is reversely biased, as the negative voltage V.sub.BB is applied to the substrate 71. For example, if V.sub.D =0.8V and V.sub.BB =-3V, introduction of electrons to the substrate can be prevented when the undershoot is up to about -3.8V. However, if a plurality of DRAMs are mounted on a board and they are to be operated in the system, an undershoot exceeding this value may be applied to the DRAMs. In such a case, a forward direction voltage is biased to the P-N junction between the above mentioned N.sup.+ diffusion layer 78 and the P well 72. Consequently, electrons are introduced to the substrate, which may destroy the information stored in the memory cell. In addition, introduction of the electrons to the substrate also affects the substrate potential itself, which may affect refresh characteristic which is an important characteristic of the DRAM, degrade soft error rate, and cause fluctuation of transistor characteristics such as the threshold value V.sub.TH of the memory transistor, current supplying capability .beta. of the memory transistor, and so on. Therefore, in the conventional input circuit, not only is a negative voltage V.sub.BB applied to the substrate, but the parasitic bipolar transistor 74 is utilized to prevent introduction of electrons to the substrate. More specifically, referring to FIG. 11, a region formed of an N.sup.+ diffusion layer 79 and an N well 73 is formed, and the potential of this region is fixed to the supply voltage V.sub.CC. By providing such a region, a parasitic bipolar NPN transistor 74 is formed between the N.sup.+ diffusion layer 79, the N well 73, the P well 72 and the N.sup.+ diffusion layer 78. An equivalent circuit thereof is shown in FIG. 12.
Referring to FIG. 12, the operation of the parasitic bipolar NPN transistor 74 will be described. If an undershoot whose absolute value is smaller than (.vertline.V.sub.BB .vertline.+V.sub.D) V is applied to the N.sup.+ diffusion layer 78, the parasitic bipolartransistor 74 is OFF. However, if an undershoot whose absolute value exceeds (.vertline.V.sub.BB .vertline.+V.sub.D) V is applied, the parasitic bipolar transistor 74 is turned ON. In principle, the electrons introduced from the N.sup.+ diffusion layer 78 hardly flow to the substrate, but flow to the supply voltage V.sub.CC through the N.sup.+ diffusion layer 79. However, actually, the parasitic bipolar transistor 74 has wide base, so that part of the electrons introduced from the N.sup.+ diffusion layer 78 flow to the substrate 71.
Consequently, in the conventional input circuit, destruction of information stored in the memory cells, degradation of refresh characteristic and soft error rate caused by fluctuation of the substrate voltage, malfunctions caused by fluctuation of transistor characteristics derived from fluctuation of the substrate voltage and so on caused by electrons introduced by an undershoot or an overshoot of the input circuit can not be perfectly prevented, and the operation of the internal circuit in the semiconductor device is unstable.
Now a method of manufacturing a conventional input circuit which is free from the above mentioned problem will be described below. FIG. 9 is a schematic diagram showing the structure of the conventional input circuit disclosed in Japanese patent laying open 62-224057.
Referring to FIG. 9, the conventional input circuit includes a P well 55 formed on the main surface of a P-type semiconductor substrate 51, an N.sup.+ diffusion layers 52, 60, 60 provided so as to encircle the P-well 55; N.sup.+ diffusion layers 62, 62, 64 formed on the main surface of the P well 55; and P.sup.+ diffusion layers 63, 63. The N.sup.+ diffusion layer 64 is supplied with an input voltage, N.sup.+ diffusion layers 62, 64, and a conductor layer formed on the main surface therebetween form an NMOS transistor, and P.sup.+ diffusion layers 63, 63 are supplied with a substrate bias potential V.sub.BB.
Referring to FIGS. 10A to 10F, a method of manufacturing is shown for the input circuit of the conventional semiconductor device shown in FIG. 9. Referring to FIG. 10A, an N.sup.+ diffusion layer 52 is formed on the main surface of the P type semiconductor substrate 51 by ion implantation. Referring to FIG. 10B, a P-type epitaxial layer 53 is formed covering over the N.sup.+ diffusion layer 52. Referring to FIG. 10C, N wells 54, 54 are formed in prescribed positions on the main surface of the P-type epitaxial layer 53. Referring to FIG. 10D, P-type ion implantation is performed onto the main surface of the P epitaxial layer 53 thereby providing a P well 55. Referring to FIG. 10E, oxide films 56, 56, 57, 57, 58, 58 for the separation of the device are formed on the main surface of the P well 55 and the N wells 54, 54. Referring to FIG. 10F, N wells 60, 60 are formed between the oxide films 57 and 56 by ion implantation. Consequently, the P well 55 is divided into three P wells 55, 59, 59, and the P well 55 is encircled by the N.sup.+ diffusion layers 52, 60, 60. A P.sup.+ diffusion layers 63, 63 are formed in the two regions which are surrounded by the oxide films 57, 58, and on the main surface of the P well 55 between the two oxide films 58, 58, three N.sup.+ diffusion layers 62, 62, 64 are formed. These N.sup.+ diffusion layers 62, 62, 64 are utilized to form two NMOS transistors to provide the configuration shown in FIG. 9.
In the structure shown in FIG. 9, when an undershoot with its absolute value beyond (.vertline.V.sub.BB .vertline.+V.sub.D) V is applied, most of the electrons injected from the N.sup.+ diffusion layer 64 do not flow toward the substrate 51 but flow into the supply voltage V.sub.CC through the N.sup.+ diffusion layer 52 and 60.
Therefore, the destruction of the information stored in the memory cell caused by electrons introduced to the substrate at input undershoot, degradation of refresh characteristic or the soft error rate caused by fluctuation of the substrate voltage, and fluctuation of the transistor characteristics can be suppressed. Consequently, an input circuit of a semiconductor device whose internal circuit operates stably can be provided.
The method of manufacturing an input circuit of a conventional semiconductor device is performed as mentioned above. The method of manufacturing the input circuit required not only the implantation of ions but also the growth of epitaxial layer or corresponding techniques and had to go through a very much complicated process flow as a result.