In the electronics industry, as products such as cell phones and camcorders become smaller and smaller, increased miniaturization of integrated circuit (IC) or chip packages has become more and more critical. At the same time, higher performance and lower cost have become essential for new products.
Usually, many individual integrated circuit devices are constructed on the same wafer and groups of integrated circuit devices are separated into individual integrated circuit die.
One approach to putting more integrated circuit dies in a single package involves stacking the dies with space between the dies for wire bonding. The space is achieved by means of a thick layer of organic adhesive or in combination with inorganic spacers of material such as silicon (Si), ceramic, or metal. Unfortunately, the stacking adversely affects the performance of the package because of decreased thermal performance due to the inability to remove heat through the organic adhesive and/or inorganic spacers. As the number of dies in the stack increases, thermal resistance increases at a faster rate. Further, such stacked dies have a high manufacturing cost.
Generally, semiconductor packages are classified into a variety of types in accordance with their structures. In particular, semiconductor packages are classified into an in-line type and a surface mount type in accordance with their mounting structures. Examples of in-line type semiconductor packages include a dual in-line package (DIP) and a pin grid array (PGA) package. Examples of surface mount type semiconductor packages include quad flat package (QFP) and a ball grid array (BGA) package.
Various types of bonding problems have been encountered with stacked dies. One potential problem is with bond wires shorting to the bottom die due to bond wire sagging during top die bonding. The actual failure mode shows electrical shorting by wire sagging is very critical and occurs frequently in mass production. This problem is especially acute in reverse bonding of the wire bond at the top of the bottom die.
Another type of potential problem is with bond wire shorting to the top die due to higher loop height of the bond wire than expected. This problem is especially acute in normal bonding of the wire bond at the top of the bottom die.
Recently, the use of surface mount type semiconductor packages has increased, as compared to in-line type semiconductor packages, in order to obtain an increased element mounting density of a package board. A conventional semiconductor package has a size considerably larger than that of the semiconductor chip used. For this reason, this semiconductor package cannot meet the recent demand for a light, thin, simple, miniature structure. As a result, it is hard for the conventional semiconductor package to meet the demand for a highly integrated miniature structure.
Furthermore, the fabrication method used to fabricate the conventional semiconductor package involves a relatively large number of processes. For this reason, a need therefore exists for reducing the costs through use of simplified processes. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.