It is known to make electrical interconnects or electrical contact pick-ups in a substrate by forming vias, i.e. holes or cavities, in that substrate, then performing a metallization of these vias, i.e. by filling them with an electrically conductive material such as metal.
Such a metallization of vias formed in a substrate can be obtained by implementing traditional vacuum deposition methods, for example PVD (physical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), electrolysis, etc. These methods are adapted to metalize vias with small diameters, for example smaller than about 100 μm, and small depths. The document “New Front to Back-side 3D Interconnects Based High Aspect Ratio Through Silicon Vias” by Mohamed Saadaoui et Al., 10th EPTC, Singapore, describes a method in which the vias are metalized by an electrolysis done in an ascending manner, i.e. of the “bottom-up” type.
However, these methods become inappropriate when one wishes to metalize vias with larger depths, for example in the case of through vias made in the entire thickness of a silicon substrate whereof the standard thickness is equal to about 720 μm, and even for vias comprising patterns with large dimensions, i.e. comprising a diameter larger than or equal to about 200 μm, due to the extremely long implementation times necessary, and therefore the cost to perform such metallization.
In order to reduce this cost, it is also known to perform metallization of vias by serigraphy: the electrically conductive material is arranged on the substrate in the form of a paste then, using a scraper, that paste is introduced into the vias.
However, such a metallization by serigraphy poses problems in the case of so-called “blind” vias, i.e. non-through vias that emerge at a single face of the substrate and that include a bottom wall. The more frequent flaws then encountered are the imprisonment of air bubbles in the vias, under the electrically conductive material, and/or partial filling of the vias preventing the subsequent realization of electrical contact pick-up formed by the vias on the side of the bottom walls of the vias. Moreover, serigraphy is also not suitable for metalizing vias having a substantial shape factor (ratio of the depth over the diameter of the via), for example greater than 2.
To offset these problems, document JP 2002/144523 A proposes to perform a metallization of the vias by the implementation of vacuum serigraphy. However, the drawbacks related to the implementation of such vacuum serigraphy are numerous:                the modifications that need to be made to the serigraphy material to perform such vacuum serigraphy are very expensive,        the time necessary to vacuum the substrate before proceeding with the serigraphy is significant,        the serigraphy material used to metalize the vias must be compatible with vacuuming, which requires the use of a polymer/metal composite as metallization material,        the quality of the electrical interconnect obtained for example between the serigraphed metallization material and the electrically conductive walls of the via is random.        