Futurebus+ is an IEEE specification for high-performance backplane-based computing that permits architectural consistency across a broad range of computer products. Key attributes of Futurebus+ are discussed in the article of J. Theus in Microprocessor Report, Volume 6, Number 7, May 27, 1992. Futurebus+ is a comprehensive architectural specification designed as an open standard; that is, an interface standard for which there are no preconceived restrictions in terms of architecture, microprocessor, and software implementations. It is also a standard explicitly designed to support multiple generations of computer technology, leading to system speeds significantly greater than current systems.
Futurebus+ provides a 64-bit architecture with a compatible 32-bit subset and data path extensions to 128 or 256 bits. The protocols, while providing headroom for system growth, explicitly support real-time scheduling, fault tolerance, and high-availability and high-reliability systems.
The logical layering of the Futurebus+ specifications offers a wealth of architectural features with which designers may implement a wide variety of systems. Both loosely coupled and tightly coupled compute paradigms are supported via the parallel protocols and in the message-passing and cache-coherence protocols. The control and status registers provide a standard software interface to the Futurebus+, easing the development and transportability of I/O drivers and other system software.
Unlike older standard buses, Futurebus+ is optimized for a backplane environment. Backplane transceiver logic (BTL) circuits provide incident-wave switching capability (thus no set up and hold times), low capacitance with high current drive capability, and controlled one-volt voltage swings for better noise margins.
Bus arbitration is the process of unambiguously issuing a single bus grant. Futurebus+ specifies doing bus arbitration through the use of either a central system or a distributed system.
The central system requires each module's arbitration circuitry to send a non-bused request and grant signal to the central arbiter.
The distributed system relies on bused signals to implement a distributed, asynchronous state machine and therefore does not use central facilities. The redundancy of distributed arbitration elements allows greater fault-tolerant operation. The distributed system is logically complex and significantly slower than the central system. The distributed system uses a byte-wide data path to choose a winner during the competition phase. This data path can also be used as a message facility that is completely independent of the main bus so it is useful for fault recovery and for signaling events.
Current arbitration systems require separate software and protocol hardware for central and distributed arbitration modes. Such systems impose significant software and hardware overheads for fault tolerant systems.
It is a technical advantage of this invention to provide common run time software and common hardware protocol for distributed mode and central mode operations.
Other advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein.