Integrated circuit memory devices are often organized into rows and columns of memory cells, with the rows and columns separately selected based on the value of the portions of the memory address which represent row and column addresses. In such devices, the term "word lines" generally refers to a set of conductors of which one, when active, selects the addressed row of memory cells; the term "bit lines" generally refers to a set of conductors which communicate data between memory cells in the addressed row and a sense amplifier. The sense amplifier is a circuit which senses the data state of the data on an associated bit line, and which generally amplifies the sensed data state for communication to output stages of the circuit.
Recently, the use of both bipolar and MOS transistors in a single integrated circuit (such use commonly referred to as BiCMOS technology) has been applied to static random access memories (SRAMs). Such an SRAM is described in my copending applications Ser. No. 018,874, filed Feb. 24, 1987, and Ser. No. 156,520, filed Feb. 16, 1988, both assigned to Texas Instruments Incorporated, and also described in "An 8ns Battery Back-Up Submicron BiCMOS 256k ECL SRAM" by H. V. Tran et al., 1988 International Solid-State Circuits Conference Digest of Technical Papers (IEEE, 1988), pp. 188-89, and 364, and in "An 8ns Battery Back-Up Submicron BiCMOS 256k ECL SRAM" by H. V. Tran et al., IEEE J. Solid State Circuits, Vol. 23 (IEEE, October 1988), pp. 1041-47, all incorporated herein by this reference. The memory described in said application Ser. No. 156,520 provides a single sense amplifier for each column in the memory cell array. The provision of such a single sense amplifier improves the sensing resolution, as the length of the bit lines associated therewith is reduced from that if a single sense amplifier were associated with multiple columns in the memory.
In said application Ser. No. 156,520, the sense amplifier is formed of a pair of emitter-coupled bipolar transistors, with their bases connected to the complementary bit lines of the column. A current source, such as an MOS transistor, is connected to the emitters of the pair, so that the differential current received by the bases of the transistors creates a differential collector current through the pair, creating a differential voltage at the collectors which is communicated to a second stage sense amplifier. Each of the bit lines in the selected column are actively pulled down; the lower potential bit line is pulled down through the memory cell, and the higher potential bit line is pulled down by the current into the base of the sense amplifier transistor.
As the size of the memory device using such a sense amplifier increase, the length and parasitic capacitance of the bit lines also increases. If the capacitance of the bit lines is sufficiently great, the current pulled down into the base of the sense amplifier transistor may not be sufficiently large to fully pull down the bit line at the higher potential, so that the bit line effectively floats. If the bit line which is at the high logic state is effectively floating-power supply noise which couples onto the bit line can raise the potential of the bit line, widening the differential voltage, and slowing the response of the memory if the next cycle reads another memory cell in the same column of the opposite data state.
It is therefore an object of this invention to provide an improved sense amplifier by providing active pull-down devices for the bit lines.
It is a further object of this invention to provide such pull-down devices which are selectively enabled by the column address signal.
Variations in the differential bit line voltage of such a memory are also not desired. Such variations can result from variations in the manufacturing process of the device, resulting in variations in electrical parameters such as the threshold voltage, effective channel length and k' parameters of the MOS transistors. If the differential bit line voltage is sensitive to these transistor parameters, it is likely that the manufacturing yield of the memory device will be degraded due to performance sensitivity of the device to changes in the manufacturing parameters. Such variations in the differential bit line voltage can also be due to variations in the operating parameters of the device, such as power supply voltage and temperature; if performance is sensitive to variations in these parameters, the specified operating range of the device may be limited.
It is therefore a further object of this invention to provide such a memory having performance which has a reduced sensitivity to manufacturing and operating parameters.
Furthermore, for long bit line architectures, the resistance of the bit line between the pull-up resistors and the selected cell can significantly affect the bit line differential voltage. It is preferable to adjust the bit line differential voltage in such a way as to take into consideration the series bit line resistance, as well as to keep the bit line differential voltage constant regardless of the position of the selected cell in the column, so that address-dependent performance variations are not present.
It is therefore a further object of this invention to provide such a sense amplifier which further has series current source transistors controlled by a gain control circuit, so that the bit line differential voltage is maintained relatively constant regardless of the position of the selected cell in the column.
Other objects of the invention will be apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.