Field of the Invention
The present invention relates to a semiconductor device, and a method for manufacturing the semiconductor device.
Description of the Related Art
An SAC (Self-Aligned Contact) technique has been conventionally used to form contact holes. The SAC technique eliminates the need to provide an alignment margin between a gate electrode and a contact hole. The SAC technique is thus used as a method suitable for miniaturization.
The SAC technique generally uses a method utilizing the high etching selectivity of silicon oxide and silicon nitride. According to this method, a silicon nitride film is formed on the top surface and side surfaces of a gate electrode (in this case, the silicon nitride film on the side surfaces of the gate electrode forms sidewalls). Then, etching is carried out using the silicon nitride film as an etching stopper, to form contact holes in a self-aligned manner.
Japanese Patent Laid-Open No. 10-163477 discloses a technique to grow a single silicon layer on an impurity diffusion region by a selective epitaxial growth method. This technique reduces the aspect ratio of the contact holes and thus the etching amount of oxide film dry etching. Thus, a decrease in bottom diameter is avoided, and the short circuit between a contact plug and the gate electrode is prevented.