The present invention relates to cache memory systems with a capacity exceeding that of their controller, and in particular to an expanded cache memory system for Intel's 82385 cache controller.
A cache controller, such as the 82385, is used to provide a quicker access time than main memory for often used data. Such a system is shown in FIG. 1. A microprocessor, such as the 80386 processor 10, normally accesses a main memory 12 which is typically a very large memory. A smaller cache memory 14 can be accessed more quickly using an intermediate cache controller 16. The 82385 cache controller of Intel is designed to work with a 4K.times.8 cache memory. Upon a request from the 80386, the cache memory is examined, and if the data is there, it is provided to the 80386. Otherwise, the 80386 will access main memory at a slower speed.
It would be desirable to use the cache controller to access a larger memory, such as an 8K.times.8 memory or a 128K.times.8 memory. This could be done with a system such as shown in FIG. 2. A controller 18 is connected through interface logic 20 to a cache memory 22. The interface logic produces more addresses to the memory than are provided by the controller. This can be done through a number of methods which are well known to those of skill in the art. For instance, the appearance of a certain address key could indicate that a different section of memory should be used. Such an address key could be a certain sequence of bits within a certain portion of the address field which is decoded to produce another address bit at the output interface logic. An obvious problem with this type of system is that the interface logic adds an additional time delay to the system, requiring that memory 22 be a faster memory so that the memory access can be done at the same speed as the direct access of FIG. 1. Obviously, such a fast memory will be more expensive and difficult to design.