1. Field of the Invention
This invention relates to interconnections made between a multilayer printed circuit board (PCB) and a connector. More particularly, it relates to a PCB-connector combination for establishing firm contacts, continuing adequate control of signal line characteristic impedance, and minimizing the length of signal paths to maintain the integrity of high speed logic signals and for establishing circuits to provide supply voltages at required current levels.
2. Description of the Related Art
Historically, the interconnection of digital integrated circuits has not been a significant engineering challenge since circuit switching speeds (signal transition times) have been slow when compared to the length of time required for signals to propagate down a typical printed circuit line. However, with the ever increasing circuit speeds associated with current day integrated circuits and related computer system technology, there is a growing need to design and fabricate PCBs using materials with closely controlled electrical characteristics and physical dimensions to achieve adequate control of signal integrity. The extent to which control must be exercised depends on the interconnect length of the PCB lines as compared to the output circuit's switching speed. Printed circuit interconnections begin to take on transmission line characteristics when the signal propagation time equals one half of the signal transition time. Although multiple rules apply when designing high speed interconnect systems, the technology is well known having been reduced to practice in large scale commercial computers more than 30 years ago.
The capability to provide power supply voltages at the required current levels is typically achieved through the use of a few heavy current contacts or multiple lower capacity contacts.
Continual advancements in integrated circuit packaging in multilayer printed circuit board technology, concurrent with the development of higher speed integrated circuits, has provided a means to build high performance computers on individual printed circuit boards. However, ongoing requirements for high performance systems such as large mainframe and multiple parallel processor computers, and telecommunication switches continue the need for multiple PCB logic cards that require interconnection through a printed circuit backpanel. The same considerations affect transmission lines routed between logic cards and backpanels. These systems typically involve one nanosecond and faster circuit switching times requiring closely controlled transmission line interconnections. The entire interconnection system must be designed and fabricated to tighter specifications to minimize signal integrity problems due to reflections and cross coupling.
An optimum PCB logic card to backpanel interface design includes a logic card connector that achieves minimum physical spacing between the connector edge of the logic card and the backpanel to minimize the length of marginally controlled signal line characteristic impedance. Commonly used designs involve relatively large pin and socket connectors with multiple pins devoted to power and ground strategically located alongside signal pins. This results in a marginal solution that is even more marginal for sub nanosecond circuits. Close control of all dimensions and associated tolerances for the PCB, connector, backpanel, and chassis is essential to the proper functioning of the PCB to backpanel interface because of the small physical dimensions of the two separate connector contact designs. Table I lists dimensions and tolerances available per the major PCB manufacturers.
TABLE 1 ______________________________________ Controlled Impedance Multi-layer Printed Circuit Board Process ______________________________________ Limits Line width and spacing - down to 0.003 inch Drill hole diameters - down to 0.008 inch Thickness to hole diameter plating ratio - up to 16 to 1 Dielectric core thickness - down to 0.002 inch Starting copper weights (thicknesses) - 1/4 ounce (0.00035 inch) to 5 ounce (0.007 inch) Fine pitch SMT pads - down to 0.008 inch pitch Via types - Blind (controlled depth drilled or sequentially processed, 1:1 aspect ratio) Buried Tagged Via in pad Buried resistors Buried capacitance Metalization - SMOBC/HASL Fused tin-lead Selective solder strip (TAB) Deep tank hard gold Deep tank soft-wire bondable gold Deep tank gold flashing Bare copper finish - (Entek-Plus organic coating) Finished PCB thickness tolerance - 10% down to 5% Maximum PCB size - up to 28 inch by 24 inch process panels Electrical - Standard single fixture (through hole, S/S surface mount) Clamshell D/S double density simultaneous test Fixtureless (flying probe test, D/S simultaneous ______________________________________ test)
The present invention provides unique enhancements to the well established card edge connector concept. These enhancements provide significant advantages over the previously described pin and socket solution. Furthermore, microstrip and strip line requirements must be met to achieve 50 ohm impedance transmission lines which are typically employed. The formulas for impedance are shown in FIG. 6.
The microstrip and strip line design requirements are required for both the PCB and backpanel. Also required are plated through hole (PTH) connections between connector contacts and buried signal lines located at the edge of the PCB near the signal contact points. This invention embodies all of these requirements and in addition employs a unique contact design described below.