Bose-Chaudhuri-Hochquenghem (BCH) codes are a generalized from of Hamming code often employed in error detection and correction circuits. In these error detection and correction circuits, an error correction code is generated for a datum based on a BCH code. The datum and the error correction code are then stored together as a data unit. For example, the data unit may be stored in a memory location of a memory device. A check is then performed for data bit errors in the data unit, for example when reading the data unit from the memory location of the memory device. In this error checking process, syndromes are generated based on the data unit and a locator polynomial is generated based on the syndromes.
The locator polynomial indicates a location of a data bit error, if any, in the data unit. Moreover, the locator polynomial may indicate a number of data bit errors in the data unit depending upon the error correction code. Generally, the number of data bit errors that the error detection and correction circuit may detect in the data unit increases with the number of data bits in the error correction code as well as the number of syndromes in the sequence of syndromes. In addition to detecting data bit errors in the data unit, the error detection and correction circuit corrects up to a number of data bit errors detected in the data unit, for example by logically negating each data bit detected as a data bit error. Typically, the error detection and correction circuit corrects each data bit detected as a data bit error in the data unit.
One type of error detection and correction circuit employing BCH codes includes an odd syndrome generation circuit and an even syndrome generation circuit. The odd syndrome generation circuit generates odd syndromes of a sequence of syndromes by performing logical operations on the data bits of the data unit. Typically, the odd syndrome generator circuit includes an exclusive OR tree implemented in logic circuits for generating the odd syndromes. Moreover, the odd syndrome generation circuit writes the odd syndromes into registers dedicated to the odd syndromes.
The even syndrome generation circuit generates the even syndromes of the sequence of syndromes and writes the even syndromes into registers dedicated to the even syndromes. Because the odd syndromes are stored in registers dedicated to the odd syndromes and because the even syndromes are stored in registers dedicated to the even syndromes, the number of registers for storing syndromes in the error detection and correction circuit is equal to the number of syndromes in the sequence of syndromes.
In some applications, it is desirable to have an error detection and correction circuit for detecting and correcting a large number of data bits relative to the number of data bits of a data unit. In these applications, the sequence of syndromes includes a large number of syndromes relative to the number of data bits in the data unit. Moreover, the registers for storing the syndromes consume a considerable amount of power and area in an integrated circuit implementation of the error detection and correction circuit.