Over the years, means to program memory of integrated circuits, such as program memory for programmable logic devices (“PLDs”), have advanced. Briefly, this progression has been from hard coding a program into ROM, to providing a UV-erasable ROM and then to providing an electrically erasable re-programmable ROM. This leads to memory that is reprogrammable after attachment to a printed circuit board or In-System Programmable (“ISP”). Though this type of arrangement permits an integrated circuit's memory to be programmed or reprogrammed while mounted on a printed circuit board, it requires that the entire printed circuit board be powered up.
Each of these advances has added flexibility to the programming and reprogramming of the integrated circuits. Reprogramming is important, for example, to load test programs into the memory to test the integrated circuit or the system in which the integrated circuit is mounted. For example, in the manufacture of printed circuit boards, special apparatus known as automatic test systems, automated test equipment (“ATE”) or “testers” are used to program the integrated circuits with test programs to test the functionality of the integrated circuits and printed circuit boards on which they are mounted. After the automatic test system tests are finished, the automatic test system may program the integrated circuit memory to a customer specified state or erase the integrated circuit to an original unprogrammed state.
Conventionally, Joint Test Action Group (“JTAG”) pins, namely, Test Clock (“TCK”), Test Mode Select (“TMS”), Test Data In (“TDI”) and Test Data Out (“TDO”), are used for ISP of memory. Because automatic test systems are expensive, time programming and testing a microchip (“chip”) or printed circuit board with one or more microchips (“chips”) is costly. It would be desirable to pre-program one or more integrated circuits with test programs prior to mounting the printed circuit board or chip on the automatic test system, and be able to re-program the same integrated circuits or chips with operational programs after the printed circuit board has been removed from the automatic test system. This process can reduce the time printed circuit boards are mounted on relatively expensive automatic test systems that currently must themselves program the integrated circuits with either test or operational programs.
Separate JTAG programming devices today require a power supply to be used to power the entire printed circuit board or chip. Especially in instances where a printed circuit board employs a significant number of integrated circuits, such a power supply can be heavy and add to test equipment cost.
Thus, there is a continuing need to provide additional flexibility in in-system programming of memory, especially memory for programming “PLDs”, especially when it would be desirable to program only one integrated circuit without providing power to an entire printed circuit board. Thus, it would be desirable to add capability to do “Off-Line” ISP (“OL-ISP”), namely, programming without powering the entire printed circuit board.