Ripple adders of the type now used in arithmetic logic units typically include a series of full adder stages arranged in serial succession. The ripple adder computes the sum of two words by individually computing the sums of each corresponding bit pair of the two words beginning with the least significant bit and progressing to the most significant bit. Typically, each full adder stage must decide whether or not to generate a carry bit which is summed into the next successive full adder stage. Accordingly, the speed of such a ripple adder is significantly limited because the addition must be carried out in each full adder stage successively so that the carry bit from the preceding stage is ready when the next full adder stage computes its sum. For example, assuming that only one clock period is required to transfer the carry bit between succeeding stages, the addition of two eight-bit words would require a minimum of eight clock periods before all eight bits were summed.
In the growing technology of very high-speed integrated circuits, a primary goal is to raise the speed of such devices as arithmetic logic units, which requires that the speed of ripple adders used in such logic units be increased.