1. Field
The present disclosure generally relates to the design of circuits to transfer data between computer system components. More specifically, the present disclosure relates to the design of a distributed phase-correction circuit to reduce noise in the timing elements mediating the synchronization of data transfers between computer-system components.
2. Related Art
As the distance between computing/memory nodes continues to increase, long-distance off-chip and on-chip communication is becoming a more-prevalent concern for system designers. At the same time, in order to improve system performance, data rates are increasing. A common technology underlying this long-distance/fast data-rate communication facilitates the retiming of data via amplifying latches to restore signal integrity (e.g., such as in a transmitter and receiver setting, where the phases of the transmitting and receiving ends are arbitrary).
Retiming of synchronous data usually involves some form of phase adjustment of a local clock to synchronize it with the incoming data stream. During this process, the local clock is adjusted so as to sample at the middle (or within a time window) of the data eye (e.g., the edge from a delay-locked loop (DLL) must be within 5 ps of the ideal sampling point). Clock phase alignment is usually accomplished by using a phase-locked loop (PLL) or a DLL. Because faster data rates imply an ever-shrinking data eye, there is a corresponding tighter demand on the position of the sampling edges generated from PLLs and DLLs. Moreover, because noise inherent in systems tends to widen the phase window of PLLs and DLLs, this means that the distribution of edges around the ideal sampling point becomes wider, which makes it harder to meet the constraints of an edge falling in a certain time window. Therefore, lowering the output clock jitter from PLLs and DLLs is of paramount importance.
FIG. 1 presents a block diagram illustrating an existing DLL, which includes: a variable delay line, a filter, and a phase detector. The phase detector compares the arrival time of in and out at its inputs. The corresponding difference, in turn, is used to adjust the delay of the delay line (but with an integer number of cycles) so that edges of in and out align (if in is a periodic signal). The filter serves to accumulate and smooth out the phase errors from the phase detector. In this configuration, input jitter has the potential to be amplified at the output, because: each stage in the variable delay line accumulates and amplifies jitter from its preceding stage; the phase detector does not differentiate jitter between its two inputs, so that, when the inputs deviate in their response to external variations, the loop amplifies this deviation resulting in jitter peaking; and low-pass filtering in the control loop implies the loop is unable to respond to fast external fluctuations. As these problems are not decoupled, there is usually a trade-off in reducing the effects of one at the expense of another. For example, lowering the loop bandwidth reduces jitter peaking at the expense of being less responsive in tracking changes in the reference clock.
Two techniques have been proposed to reduce input-jitter amplification: loop and phase filtering. In loop filtering, a low-pass filter is introduced to filter out high-frequency jitter. This low-pass filter adds an extra pole in the loop response that, when taking loop stability into account, must be positioned at a relatively high frequency, thus diminishing its effectiveness. For phase filtering, a phase-domain filter, such as a ring oscillator, is used to reduce high-frequency jitter, while making jitter peaking more prevalent. A time-shifted averaging voltage-controlled delay line (VCDL) may be used to correct for duty-cycle errors and device mismatch. In addition, this VCDL generates precise multi-phase timing signals. However, this implementation suffers from start-up and locking problems, because it is configured with forward and backward loops, allowing for multiple stable operating regions, which prevents the circuit from locking to a unique state. Alternatively, a similar time-averaging circuit may be used, but with local feedback removed to avoid start-up problems. Instead, two rounds of the time averaging are used to reduce the jitter. Jitter, however, can still be amplified through the delay line, and extra power must be consumed to maintain the outputs within specification. In another approach, a surfing inverter has been proposed to serve as both the phase detector and the delay element, such that the jitter is attenuated while traversing the delay line. However, the locking range for this design is somewhat limited.
Hence, what is needed is a phase-alignment circuit without the above-described problems.