1. Field
Example embodiments relate to a semiconductor device, and more particularly, to a semiconductor device having a bar type active pattern.
2. Description of the Related Art
Along with the development of semiconductor devices towards high speed, high performance and low power consumption, ongoing efforts have been made to increase the density of an integrated circuit (IC) with smaller transistors while maintaining the improved driving performance of the transistors constituting the IC. For a higher device density, transistors with a smaller feature size and a 3-dimensional structure are drawing more attention. Transistors that may be manufactured to be smaller and may improve the performance of devices include MOS transistors with a fin structure, a fully Depleted Lean-channel TrAnsistor (DELTA) structure, and a Gate All Around (GAA) structure.
Because transistors with a GAA gate structure are manufactured using damascene processes, the manufacturing process is complicated and the manufacturing cost rises. In addition, in order to prevent or reduce lifting of an active pattern, either a damascene stack or an “H”-shaped active pattern with a channel region whose width is much smaller than the widths of source and drain regions has been formed. Transistors with such a GAA structure are disadvantageous in terms of higher-density integration because these transistors require an additional process, complicate the manufacturing process itself, and have a limit in reducing the size of devices.