According to a conventional technique, cache hit ratios are measured in a multi-core processor system; and threads are scheduled such that the cache hit ratios of each thread increases (see, e.g., Japanese Laid-Open Patent Publication Nos. 2006-285430 and H4-338837 and Published Japanese-Translation of PCT Application, Publication No. 2008-542925).
According to another technique, cache priority is set for each thread; and the amount of cache to be used by threads assigned to the same central processing unit (CPU) is determined according to the cache priority (see, e.g., Japanese Laid-Open Patent Publication No. H9-101916).
However, for example, when a thread whose cache hit ratio is low is concurrently executed by plural CPUs, the access of shared memory by the plural CPUs cause contention and therefore, a problem arises in that a wait period occurs for access of the shared memory.
Consequently, the execution of each thread does not advance and a problem arises in that the execution performance of the thread drops.