For certain types of semiconductor device fabrication, it may be desirable to mate one semiconductor device to another, such as by using bump bonding. The mated semiconductor devices may be of the same material or different materials, and are mated to physically attach the devices to each other and/or to provide a large number of electrical interconnects between the mated semiconductor devices (e.g., to allow electrical conduction of signals between the semiconductor devices).
For example, modern state-of-the-art infrared components may use this type of interconnect technology, with one semiconductor device material optimized to perform a detection function (e.g., infrared detector) and the other semiconductor device material optimized to perform detector biasing, signal integration, signal processing, and/or multiplexing functions (e.g., read-out integrated circuit (ROIC)). The interconnect array for these devices physically and electrically interconnects the infrared detector to the ROIC, with the interconnect array typically forming thousands to millions of electrical interconnects.
In a typical approach, metallic contacts (also referred to as bumps) may be formed on pads (contact pads) of each semiconductor device (e.g., substrate) to be electrically connected, and then the semiconductor devices with their respective interconnect contact arrays are precisely aligned to one another. The contacts may be attached to each other using elevated temperatures to melt the contacts into each other and/or using elevated pressures to force solid contacts to bond (e.g., in a process known as a “cold weld”). A drawback of this conventional approach is that the devices must be very precisely aligned to provide proper mating for all of the corresponding contacts in the contact arrays, with the very precise alignment maintained during the thermal exposure cycle (e.g., to prevent the contacts from cross-wetting the adjacent contacts). However, for typical devices (e.g., large pitch devices), coarse alignment may be achieved using visible imagery, but it may be difficult to provide very fine alignment as the devices, such as for typical substrates used in semiconductor processing, are opaque to visible light.
As a result, there is a need for improved techniques for forming interconnects between semiconductor devices.