1. Field
The present invention generally relates to computer-based tools for performing circuit simulations. More specifically, the present invention relates to a technique which uses a serial profiler to estimate the performance of a parallel circuit simulation.
2. Related Art
Circuit designers routinely perform simulations to determine how circuit designs will perform before the circuits are actually fabricated. As advances in integrated circuit technologies have enabled circuits to become increasingly more complex, such circuit simulations can take a longer time to complete in spite of the fact that the processors used to perform the simulations are becoming progressively faster. In fact, circuit simulations often take many days to complete, which can give rise to significant delays during the circuit-design process.
Traditionally, circuit simulation has been performed through a sequential process, and attempts to take advantage of multiple processors to parallelize circuit-simulation operations have not achieved any significant market successes to date. As new multi-core processor designs have enabled computer system manufacturers to offer low-cost multiprocessors with very fast interconnects, there is increasing pressure to use parallel processing to speed up circuit-simulation operations.
However, it is very difficult to predict what potential speedup can be attained by parallelizing a circuit simulation. It is also difficult to determine an optimal design partitioning to achieve the best parallel performance. Moreover, it is similarly difficult to understand why a particular parallel simulation job has performed poorly.
Hence, what is needed is a method and an apparatus for efficiently estimating the performance of a parallel circuit simulation.