PWM driving is a method of turning on or off output transistors connected to an inductive load for a motor and varying the ratio of turned-on transistors to turned-off transistors to control the amount of power supplied to the inductive load. The PWM driving is well known as a power-saving driving method. MOSFETs are commonly used as the output transistors connected to the inductive load for the motor. A predrive circuit is required to drive control terminals for the output transistors.
With the output transistors, too high a switching speed for the turn-on or turn-off operation may rapidly vary voltage to cause elements to malfunction or be destroyed. Furthermore, such a switching speed may pose a problem such as possible destruction or the possible disturbance of other electronic apparatuses due to noise. In contrast, too low a switching speed may pose a problem such as operational errors resulting from possible delay or the increased amount of generated heat resulting from increased losses.
To solve the problems, attempts have been made to control a speed at which a voltage is applied to each control terminal or removed from the control terminal, to set the slew rate of a variation in the output voltage from the output transistor at a well-balanced value at the time of turning on or off the output transistor.
As a first example of a conventional technique, an example of a well-known common predrive circuit is shown in FIG. 17. In FIG. 17, reference numerals 1 and 2 denote predrive circuits that control switching of output transistors 3 to 6. The output transistors 3 to 6 are assumed to be N-type MOS transistors. An anode and a cathode of a diode 7 are connected to a source and a drain, respectively, of the output transistor 3. Similarly, diodes 8 to 10 are connected to the output transistors 4 to 6, respectively. Reference numeral 11 denotes a gate-drain parasitic capacitance in the output transistor 3. Reference numeral 12 denotes a gate-source parasitic capacitance in the output transistor 3. The parasitic capacitance is also present in the output transistors 4, 5, and 6 (not shown). Internal circuits in the predrive circuits 1 and 2 are identical. Thus, the internal circuit in the predrive circuit 1 will be described below.
The output transistors 3 and 4 are a high-side output transistor and a low-side output transistor, respectively. The drain of the output transistor 3 and a source of the output transistor 4 are connected together in series between a power supply terminal 13 to which a power supply voltage VCC (first power supply) is applied, and a ground (second power supply). Furthermore, an on control transistor 16, a resistor 18, a resistor 19, and an off control transistor 17 are connected together in series between a booster terminal 14 to which a VPUMP voltage set equal to or higher than the power supply voltage VCC is applied, and the ground. A gate terminal of the output transistor 3 is connected to a connection point between the resistor 18 and the resistor 19. Reference numeral 20 denotes an on and off control circuit for the output transistor 4. A diode 21 prevents a reverse voltage of the gate-source voltage of the output transistor 3 from exceeding a breakdown voltage.
Application of an input signal S1 to an input terminal 22 operates the on control transistor 16. Application of an input signal S2 to an input terminal 23 operates the off control transistor 17. Application of an input signal S3 to an input terminal 24 operates the output transistor 4. The predrive circuit 2 has input terminals 25, 26, and 27 corresponding to the input terminals 22, 23, and 24 of the predrive circuit 1. Input signals S4, S5, and S6 are applied, respectively.
Reference numeral 15 denotes an inductive load. One end of the inductive load is connected to a connection point between the output transistor 3 and the output transistor 4. The other end of the inductive load is connected to a connection point between the output transistor 5 and the output transistor 6.
With reference to a time chart in FIG. 18, a turn-on switching operation of the output transistor 3 will be described. In the time chart in FIG. 18, it is assumed that a driving current is flowing through the inductive load 15 in an a direction and that the output transistor 4 is off.
At an initial to, input signals S1 and S2 are at a high level. Thus, the gate voltage of the output transistor 3 is at a low level, and the output transistor 3 is off. The current flowing through the inductive load 15 in the a direction flows from the ground through a diode 8. Thus, the voltage of a source terminal (node 28) that is an output terminal of the output transistor 3 is at the low level.
At t1, S1 and S2 are switched to the low level, the on control transistor 16 is turned on, and the off control transistor 17 is turned off. This starts charging gate capacitances 11 and 12 of the output transistor 3. The gate-source voltage (gate voltage-source voltage) of the output transistor 3 starts to increase.
At t2, the gate-source voltage of the output transistor 3 increases enough to allow the output transistor 3 to supply all the current flowing through the inductive load 15. The voltage of the node 28 then starts to rise. The gate-source voltage of the output transistor 3 at this point in time is defined as Vhold. While the voltage of the node 28 is rising, the gate-source voltage of the output transistor 3 is smoothed to the given voltage Vhold. Smoothing of the gate-source voltage is a general property of MOS transistors.
After rising completely to the high level at t3, the voltage of the node 28 keeps the high level. After t3, the gate-source voltage of the output transistor 3 starts to increase again. At t4, the gate voltage of the output transistor 3 rises completely to the high level. The gate-source voltage of the output transistor 3 then stops increasing.
During a period from t2 to t3, when the voltage of the node 28 rises, the gate-source voltage of the output transistor 3 is smoothed to the given voltage Vhold. This prevents the gate-source capacitance 12 from being charged. That is, during this period, the gate voltage of the output transistor 3 rises in accordance with time constants for the resistor 18 and the gate-drain capacitance 11. That is, the slew rate of the voltage of the node 28 is controlled by the time constants for the resistor 18 and the gate-drain capacitance 11.
Now, with reference to a time chart in FIG. 19, a turn-off switching operation of the output transistor 3 will be described. In the time chart in FIG. 19, it is assumed that the driving current is flowing through the inductive load 15 in the a direction and that the output transistor 4 is off.
At the initial to, the input signals S1 and S2 are at the low level. Thus, the gate voltage of the output transistor 3 is at the high level, and the output transistor 3 is on. The voltage of the node 28 is at the high level.
At t1, S1 and S2 are switched to the high level, the on control transistor 16 is turned off, and the off control transistor 17 is turned on. This causes the gate capacitances 11 and 12 of the output transistor 3 to discharge. The gate-source voltage of the output transistor 3 starts to decrease.
At t2, the gate-source voltage of the output transistor 3 decreases to the Vhold voltage to start dropping the voltage of the node 28. While the voltage of the node 28 is dropping, the gate-source voltage of the output transistor 3 is smoothed to the given voltage Vhold. As described above, smoothing of the gate-source voltage is a general property of MOS transistors.
After dropping completely to the low level at t3, the voltage of the node 28 keeps the low level. After t3, the gate-source voltage of the output transistor 3 starts to decrease again. At t4, the gate voltage of the output transistor 3 drops completely to the low level. The gate-source voltage of the output transistor 3 then stops decreasing.
During the period from t2 to t3, when the voltage of the node 28 drops, the gate-source voltage of the output transistor 3 is smoothed to the given voltage Vhold. This prevents the gate-source capacitance 12 from discharging. That is, during this period, the gate voltage of the output transistor 3 drops in accordance with time constants for the resistor 19 and the gate-drain capacitance 11. That is, the slew rate of the voltage of the node 28 is controlled by the time constants for the resistor 19 and the gate-drain capacitance 11.
As a second example of the conventional technique, JP2005-86380A describes a method of controlling the slew rate. In the second example, the predrive circuit has a plurality of series circuits connected together in parallel and each including an on control transistor and a resistor and a plurality of series circuits connected together in parallel and each including an off control transistor and a resistor, all the series circuits being connected to the gate terminal of the output transistor. In the configuration of the second example, an inductive load end voltage is sampled in chronological order during the switching operation of the output transistor. A microprocessor is then used to calculate the amount of a variation in voltage. The data obtained is subjected to feedback control to allow the selection of a control transistor to be turned on. The slew rate control is performed by selecting the on control transistor for a turn-on operation, while selecting the off control transistor for a turn-off operation.
As a third example of the conventional technique, JP2004-215493A describes a method of controlling the slew rate. A current source for turn-on control and a current source for turn-off control are connected to the gate terminal of the output transistor. The current values of the current sources can be varied on the basis of information from a current source setting terminal. In the configuration of the third example, the slew rate control is performed by charging the gate terminal with a fixed current for a turn-on operation of the output transistor and causing the gate terminal to discharge a fixed current for a turn-off operation of the output transistor. The variable current value of the current source enables the slew rate to be set. Moreover, the configuration can be generally used for output transistors of various sizes.
The known common configurations disadvantageously have difficulty setting the slew rate of an output voltage from the high-side output transistor (node 28). This is because the slew rate is controlled in accordance with the time constants as described above and is thus high immediately after a rise or drop in output voltage and then decreases gradually. Specifically, in FIGS. 18 and 19, since the slew rate is high immediately after t2, disadvantageously the voltage may vary rapidly to cause malfunctioning or destruction of elements and noise may be generated to disturb other electronic apparatuses. Immediately before t3, the low slew rate may pose a problem such as operational errors resulting from possible delay or the increased amount of generated heat resulting from increased losses, during switching. This means that it is difficult to set the slew rate at a well-balanced value.
Furthermore, the configuration in JP2005-86380A requires the plurality of series circuits each including the on control transistor and the resistor, the plurality of series circuits each including the off control transistor and the resistor, a sampling circuit for the output voltage, the microprocessor calculating a sampling voltage, and the like. This complicates controllability and increases the scale of the circuit. Moreover, the configuration can be generally used for output transistors of various sizes. This means the need for a large number of series circuits each including the on control transistor and the resistor and a large number of series circuits each including the off control transistor and the resistor.
The configuration in JP2004-215493A requires current source setting information. This means that the number of external input terminals increases when the switching control system is composed of a semiconductor integrated circuit. This in turn prevents the use of more inexpensive small-sized packages.
The configurations in JP2005-86380A and JP2004-215493A have the increased circuit scales and the increased numbers of external input terminals. This may inhibit a reduction in the price and size of the switching control system.
The present invention solves the above problems. An object of the present invention is to obtain a desired slew rate and to reduce the price and size of the switching control system. Another object of the present invention is to provide a switching control system that can be generally used for output transistors of various sizes.