1. Field of the Invention
The present invention relates generally to memory devices and, more particularly, to techniques for reducing leakage current in memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In recent years, the minimization of structural dimensions in integrated circuit devices, such as memory devices fabricated using complementary metal oxide semiconductor (CMOS) technology, have led to ever-increasing sub-threshold leakage currents in the devices. The leakage current is typically produced from inherent qualities associated with the CMOS technology that is typically used to manufacture static random access memory (SRAM) and dynamic random access memory (DRAM) devices. CMOS sub-threshold leakage (SVT), junction leakage and gate induced drain leakage (GIDL) in the memory core may negatively impact device performance. To date, most leakage mechanism techniques focus on sub-threshold leakage reduction and junction leakage, without considering the effects of gate induced leakage, since sub-threshold leakage and junction leakage are generally of greater impact on device performance.
Sub-threshold leakage refers generally to the leakage current through the channel of a CMOS transistor. For a one-transistor, one-capacitor (1T-1C) dynamic random access (DRAM) memory cell, for instance, leakage from the charge stored in the capacitor may occur through the channel. One technique for reducing the sub-threshold leakage in a CMOS transistor, is to implant the channel with an impurity, such as boron for a n-channel device. By implanting boron in the channel directly below the gate and directly adjacent to the drain, the threshold voltage (VT) across the gate is increased, thereby lowering the sub-threshold leakage. However, while increasing the threshold voltage may advantageously decrease the sub-threshold leakage, the increased doping in the channel disadvantageously increases the junction leakage between the n+ doped drain region and the p-type substrate material.
Gate induced drain leakage (GIDL) is generally caused by a high gate to drain electric field in the region of the gate that overlaps the drain. As device size decreases and the thickness of the gate oxide is reduced, GIDL currents increasingly impact the total off current of the device.
Techniques for reducing GIDL are primarily implemented by introducing CMOS design level modifications. For instance, one approach for reducing GIDL currents involves symmetrical oxidation to provide a thin gate oxide through the channel of the device, but to provide a thicker gate oxide in the regions of the gate-source and gate-drain overlap. The thick gate oxide in the gate-drain region reduces the GIDL. However, having a thick gate oxide in the gate-source region increases the VT which generally reduces current driving capabilities of the device. Another approach to reducing GIDL currents is asymmetrical oxidation such that the gate oxide is thicker only in the gate-drain region. The material thickness of the oxide layer in gate-drain region is increased by implanting an oxidation accelerating material, such as chlorine or fluorine to physically grow a thicker gate oxide layer in that particular region. Due to the presence of the oxidation accelerating material, the oxide layer in the gate-drain region grows faster than in the remaining portions of the substrate. However, as with the symmetrical oxidation, having an increased material thickness of the oxide layer in the gate-drain region dampers current driving capability of the device and also causes increased stress in the active area near the overlap region due to the volume expansion.
Further, implementing structural changes to the design of the device layers may introduce other variables that may ultimately negatively impact device performance. Implementing such changes may also be impractical in current manufacturing facilities.
The present invention may address one or more of the problems set forth above.