This invention relates generally to floating-point processors used in computers, and more particularly to a method and apparatus for normalizing floating-point numbers.
As it is known in the art, many applications in computers require the use of numbers that are not integers. There are several ways in which non-integers may be represented in computers. The most common approach is the use of so called floating-point numbers in which a number is divided into separate sections or registers. One section is a fraction, which represents the precision of a number, and another section is an exponent which represents in base two, the power to which the representation is raised. A third section of one bit contains the sign bit.
One of the most common operations performed in a floating-point processor is the addition or subtraction of two floating-point numbers or operands. The addition or subtraction of two floating-point numbers requires that the numbers are provided with the same exponent before the fractional parts can be added or subtracted. This is generally referred to as alignment when the fractional part of one of the operands to be added is shifted a predetermined number of bits in accordance with an exponent difference. Generally, the floating point operands or results are stored in normalized form. That is, the fractional part of the floating point number is shifted and the exponent is adjusted so that the MSB of the fraction is a logic "1".
Several approaches are known for normalizing numbers. One approach is to determine the normalization shift amount by finding the leading one for positive results or leading zero for negative results of the fraction adder-subtract unit output. One problem with this approach, however, is that the normalization shift is not determined until after the addition or subtraction is performed on the input operands. Accordingly, there is a delay from the time when the fractional adder-subtract unit provides a valid output to the time when the normalization shift could actually be performed.
One technique which avoids some of the delay inherent in this approach is described in U. S. Pat. No. 4,922,446 by Zurawski et al and assigned to the assignee of the present invention. In this patent, the delay is reduced by determining two possible normalization shift amounts for the fraction adder-subtract result based on the inputs to the fraction adder-subtract result and the sign of the fraction subtract result. This technique employs a low precision adder which operates on a preselected number of the most significant bits of the input operands prior to and after alignment to determine an approximation of the true result sufficient to approximate the normalization shift amount. Although this approach provides an improvement in minimizing the amount of delay occasioned from the time that the normalization shift prediction amount is available to the fractional add or subtracted result from the adder-subtracter, the approach, nevertheless, still has a certain amount of delay and is required to operate on the inputs to the fractional adder-subtracter and not on the input operands themselves. Thus, the normalization shift still requires a sufficient period of time to complete while awaiting the prediction result.
Another technique is described in U.S. Pat. No. 5,317,527 by Britton et. al. and also assigned to the assignee of the present invention. This approach uses two scan circuits which are used to scan the input which is being subtracted. The scan circuits search from MSB to LSB for possible leading "1" and leading "0" bit positions, with different searches being done for positive, negative and zero input operands. Although this approach provides an improvement in minimizing the amount of delay occasioned from the time that the normalization shift prediction amount is available to the fractional add or subtracted result from the adder-subtracter, the approach, nevertheless, still has a certain amount of delay and is required to operate on the inputs to the fractional adder-subtracter and not on the input operands themselves. Most importantly, this approach as with the prior approach requires the sign of the fraction subtraction result to determine which prediction of the normalized shift amount i.e. the leading one or leading zero is the correct one. Thus, the determination of the normalization shift amount does not start until the subtract operands are selected by determining a possible one bit alignment, and can not complete until the sign of the subtract itself has been determined.