The present invention relates generally to floating point processors, and, more particularly, to floating point compare instructions executed by a floating point processor.
A binary floating point processor (“BFP”) typically has to support operands and results in multiple formats, for example, 64-bit double precision (“DP”) in IEEE coding, 32-bit single precision (“SP”) in IEEE coding, SP in 64-bit DP IEEE coding, or 32-bit SP in Graphics or Non-Java coding. State-of-the-art BFPs typically support mixed precision, i.e., the formats of each operand and the result are independent and can be different. To support all of these and other formats in an efficient manner, the BFP converts its operands during the unpacking stage into a special internal format, and after the final rounding stage the result is converted back into the instruction specific format. The entire computation inside the BFP core is mainly independent of the input and output formats.
One common type of instruction that a BFP executes is a floating point compare instruction with two operands. Oftentimes the two operands have different or mixed floating point precision. As a result, known compare operations are generally performed on the floating point format level, which requires additional steps (e.g., a first step to subtract the operands and a second step to evaluate the difference). That is, the format differences must be detected and eliminated before the compare instruction can be completed as a special type of floating point subtraction operation. This type of instruction execution typically takes five clock cycles to complete, even for the most common cases, which is an undesirable amount of time. Clearly, this slows down the speed of the BFP, which is further undesirable given the fact that the compare instructions are performance critical.