This invention generally relates to microprocessors, and more specifically to improvements in cache memory and access circuits, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first aspect of the invention, there is provided a digital system having at least one processor, with an associated multi-segment cache memory circuit. A single global valid bit is associated with a set of segments. The global valid bit is set to indicate that a block transfer has transferred valid data into a portion of the set of segments; however, the global valid bit does not necessarily indicate that all of the segments of the set contain valid data. Block circuitry associated with the memory cache is operable to transfer data to the cache from a pre-selected region of the secondary memory having a fixed address correspondence with the memory cache.
In another embodiment of the invention, direct memory access (DMA) circuitry is connected to the memory cache for transferring data between the memory cache and a selectable region of a secondary memory.
In another embodiment of the invention, there is mode circuitry to select between a cache mode of operation for the memory cache and a RAM mode by disabling miss detection circuitry associated with the memory cache.
In an embodiment of the invention, block circuitry is associated with the cache that has a start register and an end register. The block circuitry is operable to fetch a plurality of segments in response to a miss. The DMA circuitry makes use of these same start and end registers and further has a third register to specify the selectable region of the secondary memory.
Another embodiment of the invention is a method of operating a digital system having a processor and a memory cache. A single global valid bit is associated with a set of segments for indicating data validity of the set. A block of data is transferred to a portion of the set of segments. The global valid bit is then set to a first state to indicate the block transfer is complete and to indicate the portion of segments contains valid data. A transfer request to the any of the plurality of segments of the memory cache by the processor is responded to as a hit whenever the global valid bit is in the first state, even if a second portion of the set of segments does not contain valid data.