1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, specifically, to an ESD protection circuit, which reduces the triggering voltage of a silicon controlled rectifier (SCR), to improves its performance.
2. Discussion of Related Art
The conductive layer or oxide layer of a semiconductor device may be thermally destructed by ESD. In order to reduce the device breakdown due to ESD, there are primary method of removing the cause of generation of ESD, which surrounds the device, and secondary method of performing sequential discharge without affecting the internal circuit of the device using an appropriate ESD protection circuit. Meantime, the SCR used as an ESD protection circuit has high efficiency in current-voltage characteristic, but its triggering voltage is high.
A conventional ESD protection circuit is explained below with reference to the attached drawings. FIG. 1 is a cross-sectional view of a conventional lateral silicon controlled rectifier (LSCR) of ESD protection circuit, and FIG. 2 is a cross-sectional view of a conventional modified lateral SCR (MLSCR) of ESD protection circuit. Referring to FIG. 1, the LSCR includes a semiconductor substrate 1, an N-well region 2 selectively formed in a predetermined region of semiconductor substrate 1, first and second impurity regions 3 and 4 formed in N-well region 2, and a third impurity region 5 formed in a predetermined portion of substrate 1 other than N-well region 2, the third impurity region 5 and N-well region 2 having an isolation layer therebetween.
Semiconductor substrate 1 is p-type, second impurity region 4 has the same conductivity as that of substrate 1, and first and third impurity regions 3 and 5 have a conductivity opposite to that of substrate 1. First and second impurity regions 3 and 4 are connected to an output pad, and third impurity region 5 is connected to Vss line. In the ESD protection circuit constructed as above, first and third impurity regions 3 and 5 form a horizontal NPN bipolar transistor, and second impurity region 2 forms a vertical PNP bipolar transistor. The NPN bipolar transistor and PNP bipolar transistor are latched with each other.
The operation of the LSCR ESD protection circuit is described below. When positive (+) voltage (static electricity) is applied through the pad, avalanche breakdown occurs between N-well region 2 and semiconductor substrate 1. Thus, current which flows through third impurity region 5 to Vss line is increased. The horizontal NPN bipolar transistor is turned on, and then the vertical PNP bipolar transistor is turned on to operate a parasitic thyristor. By doing so, the LSCR circuit is triggered.
However, the LSCR has very high triggering voltage. To solve this problem, the MLSCR is developed. Referring to FIG. 2, the MLSCR includes a semiconductor substrate 20, an N-well region 21 selectively formed in a predetermined region of semiconductor substrate 20, first and second impurity regions 22 and 23 formed in N-well region 21, a third impurity region 24 formed between N-well region 21 and semiconductor substrate 20, and a fourth impurity region 25 formed in a predetermined portion of substrate 1 other than N-well region 21, N-well region 21 and fourth impurity region 25 having an isolation layer therebetween.
Semiconductor substrate 20 is p-type, second impurity region 23 has the same conductivity as that of substrate 20, and first, third and fourth impurity regions 22, 24 and 25 have a conductivity opposite to that of substrate 20. First and second impurity regions 22 and 23 are connected to an output pad, fourth impurity region 25 is connected to Vss line, and third impurity region 24 corresponds to a trigger diffusion region. In this ESD protection circuit, first and fourth impurity regions 22 and 25 form a horizontal NPN bipolar transistor, and second impurity region 23 forms a vertical PNP bipolar transistor.
The operation of the MLSCR ESD protection circuit is described below. When positive (+) voltage (static electricity) is applied through the pad, avalanche breakdown occurs between N-well region 24 and semiconductor substrate 20. Thus, current which flows through fourth region 25 to Vss line increases. Since the horizontal NPN bipolar transistor is turned on, and then the vertical PNP bipolar transistor is turned on, the triggering voltage of MLSCR becomes lower than that of the LSCR by approximately 20V.
FIG. 3A shows the circuit configuration of a conventional LVTSCR ESD protection circuit, and FIG. 3B is a cross-sectional view of the conventional LVTSCR ESD protection circuit. Referring to FIG. 3A, the LVTSCR circuit includes: a first transistor 31 whose emitter is connected to Vss line, the collector of first transistor 31 being connected to an output pad; a second transistor 32 whose emitter is connected to the output pad, the collector of second transistor 32 being connected to the base of first transistor 31; an NMOS transistor 33 whose source is connected to the base of second transistor 32, the drain of NMOS transistor 33 being connected to the emitter of first transistor 31, the gate of NMOS transistor 33 being connected to Vss line, an N-well resistor 34 formed between the collector of first transistor 31 and output pad, and a substrate resistor 35 formed between the collector of second transistor 32 and emitter of first transistor 31. First transistor 31 is an NPN bipolar transistor, and second transistor 32 is a PNP bipolar transistor.
Referring to FIG. 3B, the LVTSCR includes a substrate 40, an N-well region 41 selectively formed in a predetermined portion of substrate 40, first and second impurity regions 42 and 43 formed in N-well region 41, a gate electrode 44 formed on a predetermined portion of substrate 40, having a gate oxide layer formed therebetween, and third and fourth impurity regions 45 and 46 formed in a predetermined region of substrate 40, placed on both sides of gate electrode 44.
Semiconductor substrate 40 is p-type, second impurity region 43 has the same conductivity as that of substrate 40, and first, third and fourth impurity regions 42, 45 and 46 have a conductivity opposite to that of substrate 40. First and second impurity regions 42 and 43 are connected to the output pad, and gate electrode 44 and fourth impurity region 46 are connected to Vss line. Third and fourth impurity regions 45 and 46, and gate electrode 44 form one MOS transistor, first and fourth impurity regions 42 and 46 form an NPN bipolar transistor, and second impurity region 43 forms a PNP bipolar transistor.
The operation of the conventional LVTSCR circuit is explained below. Referring to FIGS. 3A and 3B, when positive voltage (static electricity) is applied through the pad, breakdown occurs at the junction of N-well region 41 and semiconductor substrate 40. Accordingly, current which flows through fourth impurity region 46 to Vss line increases. This increases the voltage of N-well region 41, and thus the NPN bipolar transistor operates.
Referring to FIG. 3A, first transistor 31 is turned on to by-pass the positive voltage, applied to the pad, to the Vss line. When a supply voltage is not applied to the LVTSCR circuit, MOS transistor 33 is floated. That is, if the supply voltage is not applied, the supply power is not supplied to gate 44 of MOS transistor 33, thereby turning off MOS transistor 33. The turning off of MOS transistor 33 makes the resistance of the circuit very high. Accordingly, the triggering voltage of LVTSCR becomes lower than that of MLSCR by approximately 13V. However, the conventional ESD protection circuit has the following problem. The integration in semiconductor chips reduces the thickness of gate oxide layer, so that an ESD protection circuit having lower triggering voltage is required. Accordingly, when the triggering voltage of ESD protection circuit is larger than the breakdown voltage of gate oxide layer, the gate oxide layer placed in the internal circuit of semiconductor chip is damaged when the ESD protection circuit operates.