1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a comparator and a control method thereof, and more particularly, to a cascade comparator for use in an analog-to-digital converter (ADC), from which a hold switch for storing the output result of a comparator stage is removed, and a control method thereof.
2. Description of the Related Art
A comparator is a device which compares an input signal with a reference signal and outputs the comparison result. The comparator is generally used in an analog-to-digital converter (ADC) for converting analog signals into digital signals. For example, a comparator can be used in an ADC in such a manner that the comparator compares a sampled analog voltage with a reference signal to output a value “1” if the sampled analog voltage is higher than the reference voltage and output a value “0” if the sampled analog voltage is lower than the reference voltage.
Examples of such an ADC include a flash ADC, a successive approximation ADC, and an integrating ADC. The flash ADC among the above-mentioned ADCs has been widely used in recent times because it converts small-sized units of data while being able to perform a high-speed operation. The flash ADC performs analog-to-digital conversion by comparing an analog input signal with reference voltages which have been divided by several resistor ladders.
A one-stage comparator can be used according to the number of bits that are to be converted. However, in this case, there is a problem in that a bit error rate (BER) of the corresponding system becomes high when a sample clock period is short. For this reason, related art systems use a multi-stage cascade comparator. The term “cascade connection” means a multi-stage amplification method wherein a plurality of four-terminal devices are sequentially connected in a such a manner as to connect the output terminals of a four-terminal device to the input terminals of the following four-terminal device. By cascading a plurality of comparators together, it is possible to increase regeneration gains and reduce the probability that signals will transit to a meta-stable state.
When a plurality of comparators are cascaded together, the output of a comparator stage needs to be maintained at a constant level and then transferred to an input terminal of the next comparator stage. This is because, in the case of a multi-stage comparator, comparator stages included in the multi-stage comparator sequentially operate according to the phases of clock signals which the comparator stages receive respectively, and each comparator stage enters a reset state when the next comparator stage begins operation. If one comparator stage enters a reset state, the next comparator stage also successively enters a reset state and an input voltage of the next comparator stage changes, so that the reliability of output data cannot be guaranteed after it passes through a plurality of comparator stages.
In order to solve the problem, a method of holding an input level of a signal constant by providing a hold switch between comparator stages is used in the related art. In this method, the hold switch is turned on while one comparator stage operates, to charge an output voltage of the comparator stage in a parasitic capacitor of the next comparator stage, and the next comparator stage operates using the voltage stored in the parasitic capacitor when the hold switch is turned off, so that the resetting of the comparator stage does not affect the next comparator stage and accordingly stable cascading is made possible.
In other words, since the output of each comparator stage needs to be maintained at the same value as the sampled input value of a signal when a plurality of comparator stages are cascaded together, a hold switch for storing the output of a comparator stage is provided so that an input of the next comparator stage can be maintained regardless of a subsequent change in the output of the preceding comparator stage.
However, inclusion of the hold switch unnecessarily increases the size of a circuit. Since an increase in size of a circuit increases the number of parasitic components, power consumption increases, particularly when the circuit is a high-speed operating circuit (for example, a high-speed ADC). Also, the hold switch may deteriorate the performance of a system because a glitch caused by the hold switch may interfere with the linear operation of the circuit.