The prior art is replete with ADC circuits that utilize successive approximation registers (SARs). A charge redistribution SAR ADC includes a bank of binary-weighted capacitors that sample the analog voltage input and are thereafter switched in an appropriate manner to determine the bit-by-bit digital output corresponding to the sampled analog voltage input. One known topology for a charge redistribution SAR ADC is shown in FIG. 1. The illustrated ADC circuit 100 includes seven capacitors that are used to generate a five-bit digital output, along with one polarity bit. This implementation also includes a devoted comparator, which is realized using an operational amplifier circuit 102.
Notably, ADC circuit 100 includes a capacitor 104 that is utilized for purposes of polarity determination. The capacitance of capacitor 104 is the highest in the bank of capacitors. In addition, ADC circuit 100 requires at least four switches per bit. In other words, four different switches are used for the voltage comparison operation associated with each bit. Although ADC circuit 100 functions in an appropriate and adequate manner, the use of capacitor 104 and four switches per bit requires physical space that could otherwise be devoted to other circuits and/or be saved to reduce the package size of the host device. Moreover, since the switches in ADC circuit 100 are typically realized with transistors, the power requirement of ADC circuit 100 increases with each switch. Accordingly, ADC circuit 100 may not be the best choice for low power applications and/or for mobile device applications that rely on batteries for operating power.