Integrated circuits (IC) play a significant role in the field of modern semiconductor technology. The development of integrated circuits has made possible a modern world with advanced electrical technology. Applications of integrated circuits are so widespread and their significance affects our every day lives from cellular phones, digital televisions, to flash memory chips in cameras. The demand for more functionality requires an increase in the number of transistors to be integrated on to a dingle integrated circuit chip. These integrated circuits typically are formed on silicon substrates or wafers, which can include active semiconductor devices with structured processes for a wide range of stacked layers made from different materials, allowing for memory capabilities.
Recently, in modern semiconductor technology, integrated circuits have advanced towards smaller devices (transistors) with more memory. This typically requires shrinking the sizes of the transistors. As the sizes of the transistors decrease, the resulting increased density requires an increasing number of interconnections within the integrated circuit chip. In the manufacture of semiconductor integrated circuits (IC), successive levels can be made on a silicon wafer by etching vias and trenches in non-conducting materials and then filling them with aluminum, copper or other metal. Typically, in advanced silicon integrated circuit wiring, copper can be embedded in insulating materials with low dielectric constant values, resulting in fast chips.
In addition, as the number of transistors proliferate, multiple levels of interconnections are required between the interconnect lines and the vias which connect different levels.
Typically, in order for technology to fabricate high routing density, copper low k (dielectric) interconnects are used. Copper has found to be a better conductor and generally can be more robust than aluminum.
Typically, dielectric etch is used in the copper interconnect manufacturing sequence. Advantages with this method is that it can be repeated as many times as necessary, depending on the number of metal layers needed to create a specific device. Recently, the transition from 130 nm node to 90 nm and beyond is prompting used of a greater diversity of dielectric materials and filmstacks than were previously encountered.
Dual damascene is the dielectric etch approach most widely implemented for copper technology. Damascene typically is known to those skilled in the art as a process by which a metal conductor pattern is embedded within a non-conducting (dielectric) material. In dual damascene, the process sequentially creates embedded vias and trenches, with the vias forming vertical connections from one layer of circuitry (trenches) to the next. Etching the vias and trenches in the dielectric materials typically avoids the difficulties associated with etching copper, instead filling the etched features with copper through a sequence known as metallization.
As technology develops, progressive miniturization has brought with it a succession of technological needs and complexities. In response to these needs, thin film coatings known as anti-reflective coatings were developed. Available Anti-Reflective Coatings include top and bottom coatings (TARC and BARC), based on either organic or inorganic Bottom organic Anti-Reflective Coatings (BARC) typically are applied via spin-on deposition and can provide excellent fill and planarization performance, but can also suffer from poor etch selectivity relative to organic photoresists.
A bottom anti-reflective coating (BARC) and/or organic planarization layer (OPL) can function as patterning over previously etched features, as is in the case of a dual damascene etch. Dual layer BARC method is typically used for 130 nm, and typically is less costly.
As the design rule becomes tighter and tighter for the 65 nm technology node and beyond, trench CD uniformity and bias control, trench profile, trench depth uniformity, low-K dielectric integrity, and etch selectivity between TEOS/low-K dielectric (SiCO) and the BLoK etch stop layer (SiCN) can be a significant aspect in developing complex BARC-assisted low-K dual damascene etch processes. With respect to a dual damascene patterning scheme for copper/low-K dielectric materials, many challenges can be posed by dual damascene etch. Large trench CD non-uniformity, especially at lower level metal lines, such as M2 and M3, can cause either metal line bridging from too narrow of a space between metal lines in the wider CD area, or voids in the copper fill in high aspect ratio trenches in the narrower CD area.
In addition, an appropriate BARC recess into the via is critical to avoid via fence formation and excessive via faceting. This is because the fence could become the nucleus of a copper void resulting from insufficient copper barrier and seed coverage in the subsequent copper electrical plating process, while excessive via faceting would cause erosion of the BLoK etch stop layer during the low-K oxide trench etch. Non-uniform trench depth and low-K damage could increase RC delay, which could compromise device performance. Finally, a non-selective BLoK etch stop layer open can cause trench/via CD widening and excessive erosion of the TEOS cap layer, which could create an insufficient copper polish stop thus resulting in low k dielectric polish damage. Misalignment between the underlying copper line und upper via leads to notching that can cause voids during the copper plating process, giving rise to subsequent device reliability problems.
Traditionally, the organic BARC open process was based on N2/H2 chemistries to take advantages of their good CD and profile control. With this process, however, the present inventors have observed that there can be major disadvantages. The N2/H2 BARC open process can suffer severe reverse microloading effect caused by heavier hydrocarbon polymer formation in the wide trench area. This reverse microloading effect could cause either excessive BARC recess into the via in the narrow trench area or insufficient BARC recess into the via in the wide trench area.
Thus, there is a need to develop a novel BARC etch process in the formation of a dual damascene integrated circuit. Further, there is a need to achieve a microloading-free organic BARC open with excellent CD control and straight sidewall profile. Still further, there is a need to provide a process to overcome one or more of the aforementioned disadvantages, to provide improvements in low-K dual damascene trench profile, CD uniformity, and/or trench depth control.
As those skilled in the art would appreciate, there is a need for methods that can etch organic planarization layers in dual damascene etches. Such methods of etching should preferably not have the undesirable properties of low etch rate. Still further, there is a need for methods to etch BARC organic planarization layers in dual damascene etch, that are cost effective, have high selectivity, and a reasonably high etch rate.