Conventional computer systems have long had a processing unit having registers and logic circuits external to the computer memory, with the processing unit causing the fetching and storing of data in the memory. The processor often fetches data from memory, changes the data, and stores the changed data into the memory, which may be to the same or to a different memory location than the location from which the data was originally accessed. A memory bus and control unit transfer the data between the processor and the memory when fetching and storing the data. Input/output pins on each memory chip connect it to a circuit board which provides connections for transferring address, data and control bits to the I/O pins on the chips. The number of I/O pins on each chip is limited, thereby limiting the number of signals that can be simultaneously transferred between the chip and circuits external to the chip.
Most conventional computer memories are currently made of dynamic random access memory (DRAM) semiconductor chips. Conventional memories are extendable by adding DRAM chips, up to the chip capacity of the circuit board(s). Static random access memory (SRAM) chips are also available for use in memories, but SRAM chips store less memory bits, have faster access time, use more power, and are more costly. Conventional memories often have addressability-control switches which have their settings changed when chips are added or removed for changing the size of the memory.
The semiconductor chips found in conventional computer memories use equal time periods for both fetch (read) and stork (write) operations. Some current memory chips internally contain an interlock circuit that requires the same clocking time periods for both fetch and store operations within the chips.
Conventional memories have used chips in which each chip contains a large-capacity DRAM requiring refreshing to maintain stored data and a small-capacity buffer register, or cache, to speed up external data communications with the chip.
Prior semiconductor memory chips have contained DRAM and SRAM arrays in which the SRAM provide a high speed interface between the slower DRAM arrays and faster data buffers external of the chip.
U.S. Pat. No. 3,740,723 to Beausoleil et al entitled "Integral Hierarchical Binary Storage Element" discloses memory chips using two-dimensional addressing which may have a shift register at the intersections of the two-dimensional address selections. This patent discloses an on-chip cache in a memory chip.
An article published in the IEEE Journal of Solid-State Circuits, Volume SC-20, No. 5, October 1985, pages 914-923 by H. L. Kalter et al discloses a DRAM/SRAM arrangement for reducing the access time for both memory fetches and stores which is an element used by the embodiments of the subject invention. The technique disclosed in this article can be used independently of the subject invention in the same memory to perform its speedup function.
An article in the IBM Technical Disclosure Bulletin, Vol. 19, No. 8, January 1977 at page 3071 by F. J. Aichelmann, Jr. and N. M. DiPilato entitled "Hierarchy Memory for Improved Microprocessor Performance" discloses a page store chip hierarchy.
An article in the IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 1984 at page 6473 by R. C. Tong entitled "Memory Transfer at Arbitrary Byte Boundaries" discloses the use of one or two shift registers external to the chips comprising a memory, for which the shift registers performed the processor function of reordering the bit sequence in a byte location in the memory, by transferring the byte on a bus from the memory to the register, reordering the bits in the byte, and writing the reordered byte back into the memory.
U.S. Pat. No. 4,491,910 to Caudel et al entitled "Microcomputer Having Data Shift Within Memory", and U.S. Pat. No. 4,586,131 to Caudel et al entitled "Microcomputer Having Data Move Circuits For Within-Memory shift of Data Words" have the same specification. They disclose the subject matter of the following claim limitation: "shift means moving an entire data word in the memory from one location to another location having an adjacent address".
U.S. Pat. No. 4,641,276 to Dunki-Jacobs discloses a data communication method and means for transferring data in parallel to a source register, serially shifting the data from the source register to a destination register, and then transferring the data in parallel to another functional unit.
U.S. Pat. No. 4,667,313 to Pinkham et al discloses the use of a shift register to access a row of bits obtained from a memory bus to be serially accessed at a tapped position in the shift register.
U.S. Pat. No. 4,731,758 to Lam et al discloses separate arrays on the same chip connected through a transfer gate.
U.S. patent application serial number 479,145; filed Feb. 13, 1990 by J. E. Barth et al entitled "Dynamic RAM with On-Chip ECC and Optimized Bit and Word Redundancy" discloses on-chip redundancy with scattered groupings. That application is assigned to the same assignee as the subject application.
None of the above cited prior art suggests the invention claimed in the subject application.