The term integrated circuit (IC) is a very general term covering a very broad range of electronic devices based on solid-state electronics, such as microprocessors. It is now notoriously well-known that a vast array of consumer products, especially those products in the area of telecommunications and computerized devices (including personal computers), are based on ICs, such as central processing units (CPUs), microprocessors, and, of course, digital memory devices of many sorts.
In the art of IC design and manufacturing, ongoing research and development in a highly competitive environment is conducted to produce new and better devices, which are manufactured by usually well-know techniques involving many ways of treating semiconductor materials (wafers), applying thin-film materials, patterning, and selectively removing materials to create highly concentrated matrices of interconnected semiconductor elements, such as transistors, providing, in the end, minute, complex circuitry to perform specific tasks of computation and logic with almost unbelievable rapidity and reliability.
Also typically, in the manufacturing process, many ICs are formed on a single wafer. After what is termed in the art the “front-end” processing, during which the ICs are formed, the individual ICs are separated into discrete units termed chips in the art, which may then be packaged and used in a wide variety of ways for different products and purposes.
When developmental engineers conceive a new chip, it is of course necessary to lay out all of the circuits that will accomplish the purposes, which amounts to placing all transistors, resistors, and other devices, and plotting the interconnections that complete the circuitry. In the very early days of chip design this was a relatively straightforward process, at least a lot more straightforward than it is today. The trend in design, however, has always quite naturally been to faster and faster operation (clock speed), higher and higher density (area needed for circuitry), and lower power consumption to attain maximum computing or storage power in the least possible space. The speed motivation is obvious. Part of the density motivation is dictated by space and volume requirements in product design, and part by cost considerations. More good chips per wafer drives the cost per part down.
As need for density and speed steadily increase, new challenges arise in IC design. For example, specific manufacturing techniques, lithography for example, are always limited to such as minimum spacing of elements on a chip, line width in interconnects, and the like, and to achieve higher density it is often necessary to invent new processing techniques or improvements in older techniques. Likewise, even though higher density has a usually beneficial effect on speed capability (devices are connected closer together), allowing higher operating rate (clock speed), there are always limitations associated with device structure, materials, and the like, to speed as well, and achieving higher and higher speed involves new inventions and discoveries in materials, combinations of materials, structures of devices, and so on.
It therefore becomes apparent that a circuit diagram is only a starting point in a new IC design, even though massive computing engines are needed even for this seminal part of a design. Given stringent requirements for a new design for speed, density, and power consumption, development engineers have to pick very carefully among many alternatives for materials, processes, film characteristics and thicknesses, interconnection alternatives, and much more; and the selections one makes almost always influence other possible selections and decisions, as all are intimately related.
Still, even in the face of the complexity of the task, small market windows and short product lifecycles provide no room for error in the execution of chip design projects—schedule slippage is measured not just in terms of additional R&D costs, but in lost market opportunities that can be fatal for a company. Integrated circuit designers are therefore under tremendous pressure to design complex chips to meet design and marketing requirements.
The design of complex multi-million-transistor chips requires the pervasive use of electronic design automation (EDA) software tools. These tools are used to take high-level descriptions of designs in languages that are very similar to programming languages and yield, through a series of complicated steps, the final mask for a chip. This flow is referred to as RTL to GDS-II (RTL is the initial design description in Verilog, VHDL and GDS-II is the mask for chip manufacturing).
To counter the risk of designs not converging on requirements, engineers use virtual prototyping tools, a type of EDA tool, to estimate downstream chip implementation characteristics (speed, area, power) from early design descriptions. The intent is to get an early gauge of design feasibility. Virtual prototyping tools have garnered significant interest in the design community, and virtual prototyping is among the fastest growing of EDA market segments.
Virtual prototyping tools arguably provide reasonable estimates of delays along timing paths on a chip. The feasibility of a design, however, hinges on whether these delays are actually within acceptable bounds. Without good constraints on the permissible delays for the millions of timing paths on a chip, virtual prototyping tools are insufficient to gauge actual design feasibility. Absence of good timing constraints early in the design flow also results in chip implementation tools (logic synthesis, place & route) being asked to meet requirements that are both unnecessarily stringent and uncertain. This severely impacts ability of such tools to generate low-cost, low-power implementations that meet performance requirements without requiring design iterations.
What is clearly needed is a tool that starts with the fundamental speed performance requirements for an IC to be designed, i.e. its clock speed, and by examining the intended functionality of the new chip in regard to how it will be clocked is capable of precisely identifying and constraining acceptable delays of timing paths on the new chip. Such a tool could generate golden timing constraints that must be obeyed for the finished chip to operate at its intended clock speed. Fundamental to the golden timing constraints for a chip is that they describe not only the bounds on path delays that are established by the clock requirements of a chip, but that they also identify paths on a chip where clock requirements are relaxed. The relaxation of clock requirements is referred to in the industry as “exceptions to single-cycle clocking”. The automatic identification of the exceptions to single-cycle clocking is fundamental to the generation of the golden timing constraints for a chip.
The golden constraints, once determined, could then be used to drive existing virtual prototyping tools, logic synthesis tools, and place & route tools. The use of the golden constraints could, because of the automatically generated exceptions to clock requirements, then empower chip design without expensive and time consuming iterations, while also yielding chips that consume less area, less power, or, if required, run faster than was thought possible.
A unique and innovative software system, called Focus by the inventors, for developing such golden timing constraints in IC design is taught in enabling detail in the descriptions of preferred embodiments below.