A scan design is a technique used in design for test (DFT). A scan chain may be formed in a chip, such as system-on-chip, by connecting every flip-flop in the chip as a long shift register when a scan mode or scan test mode is asserted. During the scan mode, a scan shift operation or a scan capture operation may be performed. When the scan shift operation is enabled, one input pin may be used to load a serial input of test pattern to the scan chain. While the scan shift operation is ongoing, the normal operation of the chip may be ceased. During the ensuing scan capture operation, the normal operation of the chip may be performed based on the test pattern in the scan chain as well as functional inputs to combinational circuits in the chip. Then, the result of the scan capture operation may be shifted out during the subsequent scan shift operation, where the result may be compared with the expected test pattern to verify the sound operation of the chip.
As all the flip-flops in the chip perform shifting of the test pattern according to an input clock signal or scan clock signal from a tester (e.g., external tester), the simultaneous shifting or switching of the flip-flops may cause high instantaneous voltage droop (IVD) in the power grid, which is used to supply power to various circuit elements of the chip. The high IVD may impede a faster completion of the scan shift operation, thus causing an additional chip testing time and/or cost.
Consequently, there have been a number of approaches to reduce the IVD. In one such approach, a test pattern which is loaded into the scan chain may be modified to reduce the IVD. For example, 0-fill and/or 1-fill may be an automatic test pattern generation (ATPG) technique employed to reduce the number of flip-flop transitions during the scan shift operation. Although the technique may be effective in reducing the IVD, more test patterns, thus more testing time, may be required to compensate for the modification of the test patterns with extra 0's and 1's.
Alternatively, the design of the chip may be modified to reduce the IVD. For example, in a flip-flop output gating technique, flip-flop outputs may be gated off during the scan shift operation so that circuit elements (e.g., logic gates in combinational circuits) driven by the flip-flop outputs may not see any changes in the flip-flops during the scan shift operation. In another example, the flip-flops in the scan chain may be designed to have separate output pins for functional and scan connections. As a result, the functional outputs of the flip-flops may not change during the scan shift operation, thus reducing the IVD. However, both of the techniques may require additional hardware and/or degrade the performance of the chip.