1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a DRAM cell employing an asymmetrical buried insulating layer and a method of fabricating the same.
2. Discussion of the Related Art
A semiconductor device widely employs a discrete device such as a MOS transistor as a switching device. With the increase of high integration of the semiconductor device, the MOS transistor is gradually scaled down. As a result, a channel length of the MOS transistor is reduced and a short channel effect (SCE) becomes a problem. Therefore, a channel ion concentration should inevitably be increased in order to reduce the short channel effect.
However, this causes an increase of a leakage current, thereby deteriorating refresh characteristics.
Therefore, transistors having an SOI structure are widely studied to improve the short channel effect. The SOI structure includes a lower semiconductor substrate, an upper silicon pattern, and a buried insulating layer interposed between the lower semiconductor substrate and the upper silicon pattern, and insulating the lower semiconductor substrate from the upper silicon pattern. The transistor having the SOI structure has capabilities to reduce a short channel effect and a parasitic capacitance, and operates at high speed while power consumption is small. However, it has a problem of a floating body effect such as a kink effect.
In order to solve the problems related with the floating body effect, a new method has been introduced and studied on a technique of electrically connecting the upper silicon pattern region and the lower semiconductor substrate. Further, a method of electrically connecting the upper silicon pattern region and the lower semiconductor substrate is disclosed in U.S. Pat. No. 6,429,091, titled “Patterned Buried Insulator” to Chen, et al.
In the method disclosed in U.S. Pat. No. 6,429,091, a mask is formed on a semiconductor substrate, and buried doping regions are formed under source/drain regions. Selectively etching the doping regions, and filling an insulator, a buried insulating layer is formed. Then, a transistor has the source/drain regions formed on the top of the buried insulating layer. As a result, patterned buried insulating layers are formed interposed under the source/drain regions, thereby reducing a junction leakage current and improving a floating body effect.
In order to further reduce the junction leakage current, the buried insulating layers need to be extended under the gate electrode, spaced apart from one another. In the above method, in order to form the buried insulating layers extended under the gate electrode, it is necessary to form a mask having a width smaller than that of the gate electrode. However, it is quite difficult to form patterns having a smaller width than that of the gate electrode due to the demand of highly integrated semiconductor devices. Thus, it is also difficult to make buried insulating layers aligned with a smaller gap than the width of the gate electrodes.
Further, in the above method, the gate electrodes may be misaligned with the buried insulating layers. The DRAM device typically has two transistors and two cell capacitors inside one active region. That is, in the DRAM device, two adjacent cells on one active region may be referred to as one unit. The two cells commonly have one bit line. The two cells are required to have identical characteristics. However, due to the above misalignment, the two cells may show different characteristics. Therefore, the buried insulating layers and the gate electrodes require an alignment margin.
As a result, with a high integration of a semiconductor device, using the method disclosed in the U.S. Pat. No. 6,429,091, there is a limitation in forming DRAM cells being capable of minimizing a leakage current and having an alignment margin.