The present invention relates to ultra-low power integrated circuits (IC), and more particularly to ultra-low power design for sub-threshold integrated circuits.
In recent years, the explosive growth of battery-powered portable applications, such as cellular phones and laptop computers, has generated tremendous demand for ultra-low power integrated circuits. Sub-threshold circuits, by definition, are integrated circuits designed to operate at power supply voltages lower than the threshold voltages of Complementary Metal Oxide Semiconductor (CMOS) transistors. At sub-threshold operation, transistor currents are reduced by many orders of magnitudes, promising ultra-low power operations. Although studies of sub-threshold circuits have reported promising results with respect to power saving, the technology has yet to be implemented on practical mass production products. A number of critical problems preventing their practical use have been identified:
Performance Problems: Low voltage operation typically can reduce power by one order of magnitude; however, it also slows down processing speed by one order of magnitude. Although architectural techniques such as pipelining and parallelism can help compensate for loss in performance, these techniques introduce significant overheads in power and cost. Slow processing speed is not the only performance problem; the worst problem is inconsistency in speed. Under sub-threshold operation, a gate delay can vary by 300% due to natural doping variations. These performance problems will disable most applications.
Stability Problems: Transistors in sub-threshold circuits operate at weak inversion conditions in which the source-drain current is an exponential function of temperature, voltage, and manufacturing parameters. Therefore, non-ideal effects (e.g., process variation, noise) are magnified exponentially, causing severe stability problems. Practical-scale integrated circuits can not operate with such stability problems.
Yield Problems: Due to the sensitivity of sub-threshold circuits, their effective defect density is significantly higher than that of nominal-voltage circuits. As a result, the yield of sub-threshold circuits is significantly lower than nominal voltage circuits, making it impractical to build large-scale integrated circuits.
Test Coverage Problems: Because sub-threshold circuits are sensitive to temperature, voltage, and noise, they are likely to have pattern-dependent or event-dependent failures. Testing methodologies developed for nominal-voltage circuits typically are not adequate for sub-threshold circuits.
Reliability Problems: Reliability failures are typically caused by marginal manufacturing defects that are not significant enough to prevent the IC from passing a production test but can cause failure under use. Test-coverage problems and circuit sensitivity are always followed by reliability problems. Reliability problems are the worst kind of problems due to potentially severe consequences.
In the following discussions, we will call the above problems in performance, stability, yield, test coverage, and reliability as the “sub-threshold problems” because they happen when integrated circuits are under sub-threshold operations. Robustness, consistence, testability, and reliability are absolutely essential requirements for IC technologies. The above problems of sub-threshold circuits outweigh their power saving advantage. These problems must be solved before practical applications of sub-threshold circuits can be built.
We believe power saving sub-threshold technology is extremely valuable because of its commercial and environmental benefits. However, sub-threshold circuits are not ready for practical-scale integrated circuits because of the aforementioned problems. It is therefore highly desirable to develop ultra-low power IC design technology that can avoid the “sub-threshold problems”.