Q:

What is the difference between a wait statement and using a while loop in SystemVerilog?

I was wondering what is the difference between waiting for a flag to be set using a wait statement or a tradition loop until the flag is set.
wait (flag === 1); //Implementation 1

while ( flag != 1); //Implementation 2

A:

The wait statement blocks the current process until the expression becomes true.
The while loop you wrote becomes an infinite zero-delay loop if the expression is true (flag is false). This will hang simulation. 

