Network processors are employed in a variety of applications to manage traffic within network devices such as switches and/or routers. Data traffic typically flows between interconnected processors via request (receive) and response (transmit) interfaces. Each processor typically includes core circuitry that operates at a core rate to process requests and responses and sufficient buffer circuitry to temporarily store data received via various transfer rates.
A problem often encountered by network processors involves peak data reception and/or transfer, where the processor core may be unable to keep up with the rate of incoming data traffic from an upstream device. In such circumstances, the buffer circuitry plays a pivotal role in temporarily storing the data, thereby preventing packets from being lost (resulting in retransfers, etc.). Unfortunately, network processor buffers are of limited size to conserve integrated circuit real estate.
One solution to the buffer overflow problem involves slowing the data rate from upstream devices until the core circuitry can catch up. This is generally referred to as “traffic shaping.” In some instances, flow control information may accompany the data to help in allowing multiple network processors to manage variable data transfer rates. However, many modern high-speed networks require coded symbol transfers at fixed line rates in order to satisfy edge transition density requirements.
Thus, the need exists for traffic management methods and apparatus that maintain predefined line rates while minimizing the risk of buffer overflows.
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