Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement.
CMOS devices are usually formed in “well”-s: doped regions in a semiconductor substrate. Forming deep wells in a semiconductor substrate require a relative thick resist to prevent dopants from penetrating into other regions of the substrate. As the dimension of wells shrinks along with device scaling, the depth of wells remains almost unchanged from generation to generation. The thick resist that has been conventionally used to block dopant penetration causes several difficulties. First, a resist thick enough to prevent dopant penetration may reduce the lithography process window, or eventually may become incompatible with advanced lithography that is required for patterning small dimension wells. Second, the aspect ratio of the opening in the resist (the ratio between the resist thickness and the minimum dimension of the opening) keeps increasing as the well dimensions shrink. High aspect ratio resist is susceptible to collapse, and thus may cause defects.