1. Field of the Invention
The present invention relates to a circuit that provides software programs in the form of a masked ROM, and more particularly to an electronic apparatus capable of correcting part of program and data contents in the masked ROM.
2. Description of Related Art
It is essential for an electronic apparatus that carries out software control using a CPU (Central processing Unit) to have a read-only memory for storing software programs. As the read-only memory for mass-produced electronic apparatuses, masked ROMs (Read Only Memories) are often used to reduce their cost. If a software failure is detected in the masked ROM after manufacturing, it is necessary to reproduce the masked ROM. To avoid the reproduction, a method is conceived that corrects part of the data of the masked ROM when using it.
For example, Japanese patent application laid-open No. 4-346127/1992, “Electronic apparatus”, discloses a method of rewriting data of a masked ROM. The conventional method discloses the following two types of rewriting.    (1) When accessing an address to be rewritten, the data output from the masked ROM to the data bus is stopped, and the data to be corrected is placed on the data bus.    (2) When accessing an address to be rewritten, an interrupt is caused. An interrupt handler is placed on a RAM (Random Access Memory), so that it circumvents the faulty software.
To improve the processing speed, recent CPUs often employ a pipeline CPU core that processes data in an assembly-line like method by increasing the operation clock frequency and by passing the data through a plurality of stages with a smaller number of clock pulses.
FIG. 14 is a block diagram showing a configuration of a ROM correcting circuit using a conventional pipeline CPU core, which shows an electronic apparatus that combines the foregoing method (1) disclosed by Japanese patent application laid-open No. 4-346127 with a pipeline CPU core. In FIG. 14, the reference numeral 10 designates an electronic apparatus consisting of an LSI, and 20 designates a rewritable device storing correction data. The reference numeral 100 designates a pipeline CPU core, 200 designates an external I/O device, 300 designates an SRAM (Static Random Access Memory), 400 designates a masked ROM, 500 designates a ROM data correcting circuit, 11 designates a data bus, and 12 designates an address bus.
In the pipeline CPU core 100, the reference numeral 110 designates an instruction prefetch section including an instruction buffer 111, 120 designates a instruction decoding section, and 130 designates a data processing section. The reference numeral 140 designates a memory access section including a data buffer 141, 150 designates a register write-back section, and 160 designates a memory bus IF (interface). In the ROM data correcting circuit 500, the reference numeral 510 designates a selector (SEL), 520 designates a correction address section, and 530 designates a correction data section.
The pipeline CPU core 100 has five pipeline stages consisting of the instruction prefetch section 110, instruction decoding section 120, data processing section 130, memory access section 140 and register write-back section 150. The pipeline CPU core 100 processes each instruction by dividing it into subdivisions corresponding to the pipeline stages. A non-pipeline CPU core executes the entire processing with a single large combination circuit. Accordingly, it is difficult for the non-pipeline CPU core to increase its operation frequency. In contrast, the present pipeline CPU core 100 can reduce the processing amounts of the individual pipeline stages, and increase its operation frequency with ease. However, as for the electronic apparatuses using the pipeline CPU core, a bottleneck arises in increasing the operation frequency in the sections other than the CPU core. It is generally a path from the output of the masked ROM 400 to the memory bus IF 160 through the data bus 11 of FIG. 14.
With the foregoing configuration, the conventional masked ROM correcting circuit includes the selector 510 of the ROM data correcting circuit 500, which is interposed in the path from the data output of the masked ROM 400 to the memory bus IF 160 as show in FIG. 14. This causes a bottleneck in increasing the operation frequency. Consequently, the method (1) presents a problem of reducing the operation speed of the CPU. In addition, the pipeline CPU core 100 limits the number of available interrupts to reduce the load of the data processing stages. Accordingly, the method (2) has a problem of lacking the number of available interrupts.