1. Field of the Invention
The present invention relates to an integrated-circuit device having a microprocessor which comprises rectangular circuit cells, and more particularly to an integrated-circuit device having a microprocessor of a prescribed shape.
2. Description of the Related Art
Various integrated-circuit devices are presently used in various electronic devices. One example of integrated-circuit devices for performing a complex data processing task is referred to as a microprocessor. For data processing purpose, a microprocessor reads various data from a main memory external thereto. However, it is inefficient for the microprocessor to repeatedly read the same data from the main memory.
In view of the above shortcoming, it has been customary to connect a cache memory for temporarily storing data in the microprocessor to increase the data processing rate of the microprocessor. There is available a circuit module comprising a microprocessor and cache memories that are housed together in one package.
One conventional circuit module of the above design will be described below with reference to FIGS. 1 and 2 of the accompanying drawings.
As shown in FIG. 1, the circuit module, generally denoted by 1, comprises a single microprocessor 2 as an integrated-circuit device, eight cache memories 3 as integrated-circuit devices, and two tag memories 4 as integrated-circuit devices. The microprocessor 2, the cache memories 3, and the tag memories 4 are mounted on a main board 5.
As shown in FIG. 2, the microprocessor 2 has a substantially square circuit board 6 supporting a number of connection terminals 7 arranged on outer peripheral edges thereof. An integrated semiconductor circuit (not shown) is mounted centrally on the circuit board 6, and connected to the connection terminals 7.
The microprocessor 2 is mounted substantially centrally on the main board 5. The cache memories 3 and the tag memories 4 are disposed on the main board 5 around the microprocessor 2. The cache memories 3 and the tag memories 4 are connected to some (enclosed by dotted lines in FIG. 2) of the connection terminals 7, and positioned such that interconnections between these memories 3, 4 and the connection terminals 7 are the shortest.
Each of the cache memories 3 and the tag memories 4 comprises an SRAM (Static Random-Access Memory) having a storage capacity of 4 Mbits, and comprises an integrated circuit mounted on a rectangular circuit board. The main board 5 supports a number of connection terminals (not shown) arranged on outer peripheral edges thereof. The microprocessor 2 and the cache memories 3 are connected to these connection terminals on the main board 5.
The microprocessor 2 includes a cache memory and a tag memory (not shown) used as a primary cache. Therefore, the cache memories 3 and the tag memories 4 are used as a secondary cache. In order to decide whether cache data temporarily stored in the cache memories 3 have been hit, the tag memories 4 temporarily store tag data corresponding to the address data of the cache data.
The circuit module 1 of the above structure is used as part of an electronic device (not shown) for processing various data. The microprocessor 2 reads various data from an external main memory (not shown) connected to the circuit module 1, and processes the read data.
Since it is not efficient for the microprocessor 2 to repeatedly read the same data from the main memory, it is customary for the microprocessor 2 to temporarily store various data read from the main memory in the cache memories 3 and temporarily store tag data corresponding to the address data of the stored data in the tag memories 4.
For reading some data from the cache memories 3, the microprocessor 2 compares the tag data in the tag memories 4 with the address data of the data in the cache memories 3. If the tag data agrees with the address data, then since a cache hit is made, the microprocessor 2 reads the stored data from the cache memories 3.
In the circuit module 1, therefore, the number of times that the microprocessor 2 reads the same data from the external main memory can be reduced, and the microprocessor 2 can process various data with high efficiency.
Various processes are available for fabricating integrated-circuit devices such as the microprocessor 2. At present, it is the general practice to design beforehand various circuit cells called standard cells, and combine these circuit cells as desired into an integrated-circuit device.
As described above, the circuit module 1 comprises the microprocessor 2, the cache memories 3, and the tag memories 4, each in the form of an integrated-circuit device, all mounted on the main board 5. Consequently, the circuit module 1 is large in size and cannot be manufactured with high productivity. One approach to reduce the size of the circuit module 1 and increase the productivity of the circuit module 1 is to construct the microprocessor 2, the cache memories 3, and the tag memories 3 as a single integrated-circuit device.
In view of the above approach, the inventor has conceived a process of constructing cache memories and tag memories as small-size DRAMs (Dynamic Random-Access Memories) for use as circuit cells corresponding to standard cells, and combining those circuit cells with a circuit cell as a microprocessor, thereby making up a single integrated-circuit device.
If the microprocessor 2 from which the connection terminals 7 shown in FIG. 2 are omitted is used as a circuit cell, then it is possible to design an integrated-circuit device as efficiently as when designing an integrated-circuit device with only standard cells.
In the above microprocessor 2, since the connection terminals 7 connected to the cache memories 3 are basically positioned on and near the upper and lower edges of the circuit board 6, the inventor developed the concept of the integrated-circuit device 10 shown in FIG. 3 of the accompanying drawings. In the integrated-circuit device 10, two cache memories 12, 13 each comprising a circuit cell are individually positioned above and below a microprocessor 11 comprising a circuit cell.
However, if each of the cache memories 12, 13 comprises a rectangular circuit cell, then since the length of one side thereof corresponds to row addresses and the length of another side thereof corresponds to column addresses, the cache memories 12, 13 are of an elongate rectangular shape that is vertically shorter and horizontally longer than the substantially square microprocessor 11.
Consequently, if the cache memories 12, 13 were simply located on opposite sides of the microprocessor 11, a dead space would be created laterally of the microprocessor 11. In an attempt to avoid this drawback, the inventor tried to position a tag memory 14 comprising a circuit cell in such a dead space formed laterally of the microprocessor 11.
If the tag memory 14 comprises a rectangular circuit cell, however, the length of one side of the tag memory 14 corresponds to the same row addresses as the cache memories 12, 13 and the length of another side of the tag memory 14 corresponds to one column address. Therefore, as shown in FIG. 4 of the accompanying drawings, the tag memory 14 is of an elongate rectangular shape having the same horizontal length as the cache memories 12, 13 and a much smaller vertical length. As a result, the tag memory 14 cannot be positioned in the dead space defined laterally of the microprocessor 11.