Field of the Invention
The present invention generally relates a table lookup for scalable simulation analysis. An exemplary aspect of this invention is based on efficient deployment of Table Lookup (TLU) methodology in enterprise-level scalable circuit simulation architecture.
Description of the Related Art
In large design groups performing integrated circuit design (digital and/or analog), often the most basic verification for the circuit to be designed is running a circuit simulation, that is a numerical model of the circuit and its excitations (input signals) at conditions specified by the designer (environmental settings). The specifications for the output signal (“output specs”) need to be met in order to vet the circuit design for manufacturing and deployment. The most essential and fundamental verification of the circuit design is based on circuit simulation, commonly known within the industry as SPICE (Simulation Program of Integrated Circuit Emphasis).
A circuit simulation job is performed by a computer using extensive numerical techniques and utilizes device models to solve a nonlinear differential algebraic equation solver (also known as transient analysis) to model the input/output relationship of the circuit and to measure the predicted output of the circuit as they are being manufactured. The fundamental cost of computation of circuit simulation is the evaluation of the device models, which is the input/output relationships of the transistor elements. For each transistor (e.g., a field-effect transistor (FET)) there is a set of device parameters (model parameters) and input voltage settings at its ports that evaluate the known quantities of the transistor device (e.g., charges, port currents and their derivatives with respect to the terminal voltages, etc.).
The circuit analysis flow is normally: Circuit Parse>Formulate>Break Down Device Evaluation>MatrixSolve>Iterate Till Converge.