Resistive memory, for example phase-change memory PCM or oxide-based random access memory OxRAM, usually comprises memory points each having a selection transistor and a memory cell that is capable of storing a logic datum, and which are distributed in a matrix along rows and columns in a memory plane. A memory cell is accessed through the selection transistor and via word lines along the rows of the memory plane and bit lines along the columns of the memory plane.
Resistive memory technologies are promising in numerous aspects, in particular in terms of density since the memory cell, incorporated within the back-end-of-line BEOL interconnect layers, may be superposed over the selection transistor formed in and on a semiconductor substrate, in contrast to “conventional” non-volatile memory, for example EEPROM or NAND flash, in which the memory cell is generally also formed in and on the semiconductor substrate.
Consequently, a limitation in terms of the compactness of the resistive memory memory points is the area occupied by a selection transistor.
In this regard it has been proposed, in United States Patent Application Publication No. 2016/0013245 (French Publication No. 3023647A1), incorporated by reference, to form vertical-gate selection transistors, which are more compact than planar transistors. However, in this configuration a vertical gate may introduce the formation of a parasitic conduction channel in an adjacent transistor, causing errors when accessing a memory cell. Doping a region facing a face of the gate makes it possible to limit the formation of such a parasitic conduction channel.
However, resistive memory cells may require a particularly large current for writing a datum.