1. Field of the Invention
The present invention relates to a semiconductor memory having dynamic memory cells needing a refresh operation, and to an operation method therefor.
2. Description of the Related Art
Recently, a semiconductor memory called the pseudo-SRAM has been noted. The pseudo-SRAM has memory cells of DRAM, and operates as the SRAM by internally executing the refresh operation on the memory cell automatically. There is a demand for a pseudo-SRAM, as mounted on a portable equipment such as a mobile phone energized by a battery as a power source, to have a low current consumption in order to elongate the operation time of the portable equipment. Especially, there is a strong demand for reducing the standby current because it leads to a reduction of the current consumption during non-operation period of the portable equipment. For example, the mobile phone is enabled to have a long waiting time by reducing the current consumption while it is non-operative.
In recent years, on the other hand, in order to meet the demands for the reduction of the gate breakdown voltage and the low power current due to the miniaturization of the transistor structure, the operation voltage of a semiconductor integrated circuit has been on the decrease as well as the power supply voltage to be fed from the outside. The threshold value of the transistor hardly depends on the power supply voltage. As a result, the ratio of the threshold value of the transistor to the power supply voltage is enlarged by lowering the operation voltage. In the circuit, in which the source voltage of the nMOS transistor is higher than the earth voltage, for example, the gate-to-source voltage relatively decreases. As a result, the on-resistance of the transistor rises so that the switching speed decreases. The on-resistance of the transistor is lowered by applying a higher voltage than the power supply voltage to the gate.
Generally in the semiconductor memory such as a pseudo-SRAM and DRAM, a higher voltage (or a boost voltage) than the external power supply voltage is established by a boost circuit. The boost voltage is used for the high-level voltage of the word line and the high-level voltage of the bit line resetting signal. Here, the word line is connected with the gate of a transfer transistor for connecting the bit line with a memory cell capacitor. The signal line of the bit line resetting signal is connected with the gate of the transistor for connecting the bit line with the precharge voltage line. By using the boost voltage as the high-level voltage of the word line, the electric charge amount to be written in the memory cell can be enlarged to improve the data retention characteristics of the memory cell. By using the boost voltage as the high-level voltage of the bit line resetting signal, the bit line can be precharged for a short time to thereby shorten the access time.
However, the boost voltage is generated inside the semiconductor memory, needing an electric power for that. Therefore, the use of the boost voltage leads to the increase in the current consumption. Especially, the use of the boost voltage for the standby period exerts serious influences on the standby current.
Here, Japanese Unexamined Patent Application Publication No. 7-85658 has disclosed the technique for the DRAM by which the high-level voltage of the bit line in a self-refresh mode is made lower than the high-level voltage of the bit line in the normal operation mode. In a case that the high-level voltage of the bit line is lowered in the self-refresh mode, however, the electric charge amount to be stored in the memory cell decreases to shorten the refresh period. As a result, the effect to reduce the standby current is low.