1. Field of the Invention
The present invention relates to a semiconductor device such as a MOS FET and a method for manufacturing the semiconductor device, and especially to a super-minute semiconductor device and a method for manufacturing the semiconductor device.
2. Description of Related Art
Relating to MOS FET, a number of cells each including a drain region, a channel region and a source region are formed on a semiconductor substrate sometimes to constitute a discrete part. Recently, in a MOS FET, a drain region, a channel region and a source region are arranged in the vertical direction, that is, in the direction perpendicular to a semiconductor substrate so as to make minute the cell (see, for example, U.S. Pat. Nos. 4,767,722 and 5,034,785). By arranging such minute cells close to one another, the channel forming region (region through which drain current flows) can be enlarged, so that ON-resistance can be reduced.
On the other hand, in a circuit including a MOS FET, when the MOS FET is turned from ON-state to Off-state, a back electromotive force from the inductance component of the circuit is applied to the MOS FET and current flows through a channel region. Thereby, the channel region generates heat and sometimes the device is broken (avalanche breakage). This is because, in a parasitic transistor including a drain region as a collector, a channel region as a base and a source region as an emitter, due to the base resistance of the channel region being high, the parasitic transistor is easily turned to ON-state and high current flows through the channel region.
In order to prevent this, between a source deriving electrode connected to a source region and a channel region in a MOS FET, provided is a region having conductivity higher than that of the channel region (low resistance region) so as to reduce the base resistance. In this case, if a back electromotive force is applied to the MOS FET, the parasitic transistor is not easily turned to ON-state, so that the device can be protected from avalanche breakage.
Such a low resistance region has been formed by using a mask having openings of predetermined pattern and ion-implanting impurities into regions between adjacent cells of the semiconductor substrate through the openings of the mask.
However, for obtaining a further minute (super-minute) semiconductor device, the space between cells becomes smaller and therefore the regions into which impurities are ion-implanted also become smaller. As a result, the openings through which impurities are ion-implanted are required to be minute. However, by ion-implanting through such minute openings, impurities cannot diffuse deep into the semiconductor substrate, so that a low resistance region capable of sufficiently reducing the base resistance cannot be formed.
For example, by conventional methods, a MOS FET provided with a low resistance region capable of sufficiently reducing the base resistance and having cell size of 1.35 μm cannot be manufactured. That is, a MOS FET having low ON-resistance and high tolerance against breakage due to a back electromotive force cannot be manufactured.