The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts. Small scale and discrete plugs can be used with one gate, source, or drain contact, while larger sized plugs can be used to cross couple two contacts such as the gate and the source of a transistor. Cross coupled terminals are commonly used in static random access memory (SRAM) devices.
Small scale devices technologies, such as 32 nanometer (and smaller) processes may require extremely small contact plugs. Fabrication of such contact plugs may be accomplished with contact patterning techniques that employ dimensional shrinkage from a photolithography based pattern to the resulting feature corresponding to the pattern. For example, aggressive etch based targeting for critical via/contact shapes may call for a relatively large amount of feature shrinkage. Unfortunately, larger electrically active features may become too small due to the innate issue with etch based feature size loading (large features will shrink faster than smaller ones). Such feature size dependent micro-loading is a common phenomenon seen in plasma etching.
In contact patterning where a cross coupled contact and a contact hole are being patterned on the same mask, feature size dependent micro-loading can lead to a situation where there is no room to increase the size of the cross coupled contact on the photoresist mask (due to the amount and density of patterned features), and the degree of etch induced shrink required for contact hole critical dimension targeting may lead to a situation where the cross coupled contact will not have sufficient coverage to establish good ohmic contact to the gate and to the active region of interest.
Accordingly, it is desirable to have an improved contact patterning technique that can be used to effectively create conductive plugs having the minimum critical dimension and cross coupled plugs having larger dimensions. In addition, it is desirable to have an improved contact patterning technique that reduces the likelihood of feature merging in small scale technology nodes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.