Technical Field
This disclosure relates generally to a bit-cell voltage control system.
Description of the Related Art
Power consumption by electronic devices has been a growing concern for some time. With the proliferation of mobile devices like mobile phones, tablets, computers and the like, reducing power consumption has become a key design metric. As such, designers are constantly looking for ways to reduce the amount of power consumed by the devices they develop.
There are many ways to reduce power consumption of a device. One mechanism to reduce power consumption is referred to as power gating in which the supply voltage provided to a device or a portion of a device is reduced or removed when that device or portion is in a particular mode, such as a sleep mode or a shutdown mode. Another mechanism is referred to as clock gating in which one or more clock signals that are provided to a device or a portion of a device are stopped when that device or portion is not being used. The stopped clock reduces the device transistor transitions, and thus reduces the power consumed. In some cases, combinations of power and clock gating may be used for even greater reductions.
While these power reduction mechanisms work well, there can be drawbacks. For example, although power gating may reduce sub threshold leakage of components of the device, power gating may have less of an effect on junction leakage of components of the device.