1. Field of the Invention
The present invention relates to a phase change memory device capable of retaining two-bit data in one memory cell.
The present invention can be applied to fields including a phase change memory (PRAM), and MARAM and RRAM (Resistive RAM) that are capable of controlling (changing) resistance values.
Priority is claimed on Japanese Patent Application No. 2007-049947, filed on Feb. 28, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
As a method of realizing a multi-level memory cell (for example, two bits per one memory cell) that uses a phase change film as a storage element (i.e., phase change memory cell) there has been proposed a storage method in which the resistance value of a memory cell is controlled in four levels. In this case, in order to perform writing of an intermediate level resistance value, the resistance value is controlled by controlling the amount of electric current to be applied to an element when writing, thereby creating a resistance value in an intermediate state. Data reading is performed by comparing the resistance value with three types of reference potentials (or reference currents). Such a method has been proposed as a method for storing multi-level data.
FIG. 8A shows a distribution of resistance of a variable-resistance type multi-level memory cell. Since one memory cell retains two-bit data, writing is controlled so that the memory cell has a resistance distribution corresponding to four-levels. FIG. 8B shows a relationship between writing electric current and resistance value of the phase change memory. The resistance value after writing changes in accordance with the electric current values on the horizontal axis. The resistance value increases from the point where the electric current is approximately 500 microamperes, and the phase change memory starts to become amorphous after writing.
In order to control the resistance value, the writing electric current is controlled to change the resistance value. In the case of this example, a resistance distribution shown in FIG. 8A can be created by applying electric currents (1) to (4).
As a multi-level writing method, there have been proposed: a method of controlling the voltage or electric current when writing is performed; and a method of controlling the resistance value by changing the number of application of writing pulses. However, both of the writing methods are still a method for storing data by changing the resistance value of a single phase change region.
Furthermore, FIG. 9A and FIG. 9B respectively show a cross-sectional structure and a schematic circuit diagram of a conventional one bit per memory cell. FIG. 9A is an example of the structure of the phase change memory cell.
In FIG. 9A, a gate electrode 2 is arranged on a silicon (Si) substrate 1, a memory cell transistor is formed, and a VSS contact 3 and a D contact 5 are connected to the memory cell transistor. The VSS contact 3 is connected to a ground line 4. Moreover, a Mid contact 6 is formed on the D contact 5, a lower electrode 7b is arranged on the Mid contact 6, and a heater 9 for creating phase changes is formed on the lower electrode 7b. In order to reduce the writing electric current of the heater 9, after forming an opening, a dielectric film (side wall) 8 is formed in the opening so as to reduce the size of the lower electrode 7b to smaller than the diameter of the opening. A phase change film (GST) 10 is formed on the heater 9, and an upper electrode (bit line BL) 11, which is a metal wiring, is formed thereon.
FIG. 9B shows an equivalent circuit of a conventional memory cell. A single resistance element (phase change element) R is connected to a single transistor (MOS (Metal Oxide Semiconductor) transistor). A phase change region is created in the contact portion between the lower electrode 7b and the phase change film 10. That is, in the case where an electric current is applied to this circuit, the electric current density in this portion becomes the highest, and the temperature of this portion is likely to become the highest due to its heat generation. As described above, the conventional multi-level memory cell employs a method in which the degree of crystallization of a single phase change region is controlled to change resistance values in an analog manner, and four-level data or eight-level data is stored (refer to FIG. 8A and FIG. 8B).
The advantage of the above conventional method is that reading is performed non-destructively and the number of bits to be stored can be increased, for example, to two or four, as long as the resistance value can be controlled accurately. On the other hand, the disadvantage of this method is that the accuracy of the resistance value after writing needs to be improved because the range of the resistance value becomes narrower. To this end, there has been proposed a method of controlling the resistance accurately while performing a verifying operation (refer to Japanese Unexamined Patent Application, First Publication No. 2006-155700 (hereinafter referred to as Patent Document 1)).
However, in this method, writing requires a long period of time because the verifying operation needs to be performed, and the accuracy of the resistance and the value of the reference potential (reference current) used for reading need to be controlled at a high level of precision because the resistance has a temperature dependency.
Moreover, pp. 89-90 of “Technology and Materials for Future Optical Memories”, edited by Masahiro Okuda, CMC Publishing Co., Ltd., Jan. 31, 2004 (hereinafter referred to as Non-Patent Document 1) discloses the result of 16-level recording of a phase change ovonic memory, and it describes the result of 16-level writing between 5 kilo-ohms to 500 kilo-ohms by controlling the writing electric current.
Furthermore, an example of a phase change memory device of a conventional technique is disclosed in Published Japanese Translation No. 2005-522045 of PCT International Publication (hereinafter referred to as Patent Document 2). In this conventional phase change memory device, variable resistance elements formed from four phase change layers are commonly connected to a word line WL via a selection transistor, while the bit line BL is connected to each of the resistance elements, and sixteen-level data are expressed in accordance with the electric current applied to each of the bit lines.
However, this conventional phase change memory device has a problem in that a high level of accuracy is required in electric current detection after writing, and its circuit configuration and writing sequence becomes complex.
Moreover, an example of a semiconductor device of a conventional technique is disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-317713 (hereinafter referred to as Patent Document 3). However, the object of this conventional semiconductor device is to change the crystalline state of a phase change film by heat application after forming a circuit, to thereby change the connection state of the circuit connected to the phase change film, and its object and configuration are therefore different from those of the present invention.
As described above, in the conventional method, a higher level of accuracy is required for the resistance value after writing because the range of the resistance value becomes narrower. As a result, there has been proposed a method of controlling the resistance at a high level of accuracy while performing a verifying operation.
However, there is a problem in this method in that writing requires a long period of time because a verifying operation needs to be performed, and the accuracy in the resistance and the value of reference potentials (reference currents) used when reading need to be controlled at a high level of precision because the resistance has a temperature dependency.
The present invention takes the above circumstances into consideration. and an object of the present invention is to provide a phase change memory device that: requires only one type of a reading reference potential; does not require a verifying operation; enables simplification of its circuit configuration and writing sequence; and is capable of performing writing two bits into a conventional one bit memory cell region.
A phase change memory device of the present invention has a memory cell that uses a phase change film as a storage element, and includes: a first phase change region formed on a side of one face of the phase change film; and a second phase change region formed on a side of another face of the phase change film in a position that corresponds to the first phase change region, and the phase change memory stores two-bit data using combinations of a high resistance state due to amorphization and a low resistance state due to crystallization in the first phase change region with the high resistance state and the low resistance state in the second phase change region, the resistance value of the low resistance state being lower than that of the high resistance state.
In the phase change memory device of the present invention configured as described above, two phase change elements (resistance elements) formed by the two phase change regions are connected in series, and these two phase change elements are capable of being brought into one of two states respectively, namely a high resistance state and a low resistance state, and two-bit data (four-level data) is recorded using combinations of these states.
As a result, it becomes possible to record two-bit data using combinations of the two phase change elements (resistance elements). Moreover, since data reading is performed while judging whether the resistance value of the entire phase change elements (resistance elements) connected in series is a high resistance or a low resistance, the reference potential for reading needs to be only one type, a verifying operation is not required, and the circuit configuration and writing sequence can be simplified. Furthermore, it is possible to perform writing of two-bit data into a conventional one bit memory cell region.
Preferably, in the phase change memory device, the first phase change region is formed in a close vicinity of a contact face between the phase change film and a first electrode that is arranged so as to contact the one face of the phase change film or a recess section on the one face, the second phase change region is formed in a close vicinity of a contact face between the phase change film and a second electrode that is arranged so as to contact the other face of the phase change film or a recess section on the other face, an area of the contact face between the first electrode and the phase change film differs from an area of the contact face between the second electrode and the phase change film, and a common electric current is applied to the first electrode and the second electrode through a transistor that forms the memory cell.
In the phase change memory device of the present invention configured as described above, an electric current is applied to the first phase change region through the first electrode, and the electric current is applied to the second phase change region through the second electrode. In this case, the contact area between the first electrode and the phase change film is made different from that between the second electrode and the phase change film. The electric currents applied to the first electrode and the second electrode are the same electric current. It is a commonly known characteristic that the electric current required for making a phase change film into amorphous (making it a high resistance) or crystallizing the phase change film (making it a low resistance) is proportional to the contact area. Therefore, this characteristic is used to create a difference between the characteristics of the first phase change region and the second phase change region.
Accordingly, the difference between the characteristics of the first phase change region and the second phase change region (difference in the characteristic due to the applied electric current) is utilized, and recording of two-bit data (four-level data) can be realized by making use of combinations thereof.
Preferably, in the phase change memory device, a first heater is formed in a portion where the first electrode and the phase change film are in contact with each other, and a second heater is formed in a portion where the second electrode and the phase change film are in contact with each other.
In the phase change memory device of the present invention configured as described above, the first heater is formed in a portion where the first electrode and the phase change film are in contact with each other, and the second heater is formed in a portion where the second electrode and the phase change film are in contact with each other.
As a result, transition of the phase change film into a crystallized state or into an amorphous state can be carried out efficiently.
Preferably, in the phase change memory device, the first electrode is arranged on a side of a metal wiring on which a bit line of the memory cell is formed, and the second electrode is arranged on a side of the transistor of the memory cell.
In the phase change memory device of the present invention configured as described above, the first electrode is provided on the metal wiring side on which the bit line is formed, and the second electrode is provided on the transistor side.
Therefore, the phase change film having the first phase change region and the second phase change region can be arranged between the second electrode connected to the transistor formed on a silicon substrate or the like and the first electrode connected to the metal wiring that forms the bit line. Thereby, writing of two bits into a conventional one bit memory cell region can be realized, and a memory cell region required for storing one bit can be made smaller.
Preferably, in the phase change memory device, the first phase change region is brought from the high resistance state into the low resistance state by an electric current of a first electric current level Ireset1 applied through the first electrode, and the first phase change region is brought from the low resistance state into the high resistance state by an electric current of a third electric current level Ireset3 applied through the first electrode, and the second phase change region is brought from the high resistance state into the low resistance state by an electric current of a second electric current level Ireset2 applied through the second electrode, and the second phase change region is brought from the low resistance state into the high resistance state by an electric current of a fourth electric current level Ireset4 applied through the second electrode, where Ireset1<Ireset2<Ireset3<Ireset4.
In the phase change memory device of the present invention configured as described above, the range of the electric current for bringing the first phase change region into a low resistance state (Ireset1 to Ireset3) is made to be different from the range of the electric current for bringing the second phase change region into a low resistance state (Ireset2 to Ireset4), and only some portions of these ranges overlap with each other.
As a result, by controlling the electric current to be applied to the first phase change region and the second phase change region, setting (data writing) for bringing each of the first phase change region and the second phase change region into either a high resistance state or a low resistance state can be performed.
Preferably, the phase change memory device further includes: a first resistance value writing device that sets the first phase change region to the high resistance state and to set the second phase change region to the high resistance state by applying an electric current of the fourth electric current level Ireset4 to the first electrode and the second electrode; a second resistance value writing device that sets the first phase change region to the low resistance state and to set the second phase change region to the high resistance state by applying an electric current of the first electric current level Ireset1 to the first electrode and the second electrode after an electric current of the fourth electric current level Ireset4 has been applied to the first electrode and the second electrode; a third resistance value writing device that sets the first phase change region to the low resistance state and to set the second phase change region to the low resistance state by applying an electric current of the second electric current level Ireset2 to the first electrode and the second electrode after an electric current of the fourth electric current level Ireset4 has been applied to the first electrode and the second electrode; and a fourth resistance value writing device that sets the first phase change region to the high resistance state and to set the second phase change region to the low resistance state by applying an electric current of the third electric current level Ireset3 to the first electrode and the second electrode after an electric current of the fourth electric current level Ireset4has been applied to the first electrode and the second electrode.
In the phase change memory device of the present invention configured as described above, when performing setting (data writing) for bringing each of the first phase change region and the second phase change region into either a high resistance state or a low resistance state, an electric current is applied (for example, a pulse voltage is applied) once or twice.
In the case where the first phase change region and the second phase change region are set to a high resistance state, an electric current of Ireset4 is applied once.
In the case where the first phase change region is set to a low resistance state and the second phase change region is set to a high resistance state, an electric current of Ireset1is applied after the electric current of Ireset4 has been applied.
In the case where the first phase change region is set to a low resistance state and the second phase change region is set to a low resistance state, an electric current of Ireset2is applied after the electric current of Ireset4 has been applied.
In the case where the first phase change region is set to a high resistance state and the second phase change region is set to a low resistance state, an electric current of Ireset3is applied after the electric current of Ireset4 has been applied.
As a result, by performing writing once or twice, writing of two bits into a conventional one bit memory cell region can performed.
Preferably, the phase change memory device further includes: a first resistance value reading device that determines whether an entire resistance value of the first phase change region and the second phase change region is in a high resistance state that is higher than a predetermined resistance value or in a low resistance state that is lower than the predetermined resistance value, by applying a voltage within a range in which the crystalline state of the first phase change region and the second phase change region is not changed; a first electric current application device that applies an electric current of the first electric current level Ireset1 to the first phase change region and the second phase change region while limiting a voltage to be applied to the first electrode and the second electrode so as not to exceed a voltage twice a threshold voltage of each phase change region, in the case where the first resistance value reading device determines that the entire resistance value is the high resistance state; a second resistance value reading device that determines whether the entire resistance value is in the high resistance state or in the low resistance state, after the first electric current application device has applied the electric current; a second electric current application device that applies an electric current of the second electric current level Ireset2 to the first phase change region and the second phase change region while limiting a voltage to be applied to the first electrode and the second electrode so as not to exceed the voltage twice the threshold voltage of each phase change region, in the case where the second resistance value reading device determines that the entire resistance value is the high resistance state; and a third resistance value reading device that determines whether the entire resistance value is in the high resistance state or in the low resistance state, after the second electric current application device has applied the electric current.
In the phase change memory device of the present invention configured as described above, the following steps are performed in reading of whether each of the first phase change region and the second phase change region is in a high resistance state or a low resistance state.
First, with a first resistance value reading device, the resistance value of the entire region including the first phase change region and the second phase change region is read. At this time, if the entire resistance value is a low resistance, the first phase change region is judged to be in a low resistance state and the second phase change region is judged to be in a low resistance state.
If the first resistance value reading device judges the resistance as a high resistance, a first electric current application device applies the Ireset1 electric current to the first phase change region and the second phase change region, and then a second resistance value reading device reads the entire resistance value. At this time, if the entire resistance value is a low resistance, the first phase change region is judged to be in a high resistance state and the second phase change region is judged to be in a low resistance state. When applying an Ireset1 electric current, the voltage to be applied in between the first electrode and the second electrode is limited so as not to exceed a voltage twice the threshold (the voltage at which the electric current starts to flow) of each of the phase change regions, and if the first and second phase change regions are in a high resistance state, then this state is maintained.
If the second resistance value reading device judges the resistance as a high resistance, a second electric current application device applies the Ireset2 electric current, and then a third resistance value reading device reads the entire resistance value. At this time, if the entire resistance value is a low resistance, the first phase change region is judged to be in a low resistance state and the second phase change region is judged to be in a high resistance state. When applying an Ireset2 electric current, the voltage to be applied in between the first electrode and the second electrode is limited so as not to exceed a voltage twice the threshold (the voltage at which the electric current starts to flow) of each of the phase change regions, and if the first and second phase change regions are in a high resistance state, then this state is maintained.
If the third resistance value reading device judges the resistance as a high resistance, the first phase change region is judged to be in a high resistance state and the second phase change region is judged to be in a high resistance state.
As a result, it can be read whether each of the first phase change region and the second phase change region is in a high resistance state or in a low resistance state.
Preferably, in the phase change memory device, the first electric current application device and the second electric current application device are provided with a device for performing rewriting for bringing the first phase change region and the second phase change region into their original states, if an electric current has been applied to the first phase change region and the second phase change region.
In the phase change memory device of the present invention configured as described above, since reading of whether each of the first phase change region and the second phase change region is in a high resistance state or in a low resistance state is performed destructively, rewriting for bringing the first phase change region and the second phase change region into their original states is performed in accordance with the read data (high resistance state or low resistance state).
As a result, having read whether each of the first phase change region and the second phase change region is in a high resistance state or in a low resistance state, each of the first phase change region and the second phase change region can be restored to their original states (high resistance state or low resistance state).
Preferably, the phase change memory device, the area of the contact face between the first electrode and the phase change film is set so as to be substantially two thirds of the area of the contact face between the second electrode and the phase change film, and the first electric current level Ireset1, the second electric current level Ireset2, and the third electric current level Ireset3 are respectively set approximately as follows: Ireset1=(⅓)×Ireset4, Ireset2=(½)×Ireset4, and Ireset3=(⅔)×Ireset4.
As a result, the electric current to be applied to the first phase change region and the second phase change region, can be set in a good balance.
A first effect of the phase change memory device of the present invention is that in a phase change memory cell, in order to realize multi-level states of the phase change films (GST) in the close vicinity of the upper electrode and the lower electrode using four combinations of the set state and the reset state, the reading reference potential need be only one type, and since a resistance difference in the case of a high resistance and a low resistance can be large, the reading reference potential can be similar to that in the case of a generic one bit per memory cell.
A second effect is that since there are only two types of states of the resistance of the memory cell, that is, “high resistance in a reset state” and “low resistance in a set state”, the level of accuracy in resistance value control in writing may be low. Therefore, a verifying operation is not required and the circuit configuration and writing sequence can be simplified.
Moreover, a third effect of the present invention is that a multi-level state can be realized by forming the phase change regions in two locations, that is, the upper electrode and the lower electrode. As a result, writing of two bits into a conventional one bit memory cell region can be performed, and a memory cell region required for storing one bit data can be made smaller.