A DRAM cell device is generally divided into a cell array region and a peripheral logic region. The cell array region includes a plurality of memory cells in a matrix-type format, and the peripheral region includes a circuit to operate the memory cells.
Transistors are formed in both the cell array region and in the peripheral region, respectively, to have different optimal characteristics, since the transistors must function differently according to their roles in the device. For example, the transistor in the cell array region may have a single source/drain region made of a low concentration impurity diffusion region, while a transistor in the peripheral region may have a source/drain of a LDD (lightly doped drain) structure. In addition, the transistor in the cell array region may have gate single spacers and the transistor in the peripheral region may have gate double spacers.
FIGS. 1A to 1C are cross-sectional views of MOS transistors formed by a conventional method. FIG. 1A schematically shows a cell array NMOS transistor in a cell array region. Referring to FIG. 1A, the cell array NMOS transistor includes a gate electrode 12 formed over a semiconductor substrate 10, gate spacers 14, with a thickness of about 700 Å to 800 Å, aligned on either lateral side of the gate electrode 12, and a low concentration n-type impurity diffusion region 16 with a predetermined depth in the semiconductor substrate 10, outwardly disposed from the gate spacers 14.
FIGS. 1B and 1C schematically show a peripheral NMOS transistor and a peripheral PMOS transistor, respectively, formed on the peripheral region. The peripheral NMOS transistor includes a gate electrode 22, gate spacers 24, with a thickness of about 700 Å to 800 Å, aligned on either lateral side of the gate electrode 22, a low concentration n-type impurity diffusion region 25 with a predetermined depth, in the semiconductor substrate 10, downwardly disposed from lateral edge of the gate spacers 24, and a high concentration n-type impurity region 26 with a predetermined depth in the semiconductor substrate 10, disposed outwardly from a lateral edge of the gate spacers 24. In other words, the peripheral NMOS transistor has a so-called LDD (lightly doped drain) structure.
Referring to FIG. 1C, the peripheral PMOS transistor includes a gate electrode 32, gate spacers 34, with a thickness of about 700 Å to 800 Å, aligned on lateral side of the gate electrode 32, a low concentration n-type or p-type impurity diffusion region 35, with a predetermined depth in the semiconductor substrate 10 downwardly disposed from a lateral edge of the gate spacers 34, and a high concentration p-type impurity region 36, with a predetermined depth in the semiconductor substrate 10 disposed outwardly from lateral edge of the gate spacers 34. In other words, the peripheral PMOS transistor also has a so-called LDD (lightly doped drain) structure.
The n-type impurity preferably comprises P (phosphorous), As (arsenic), or the like. As is well known, an arsenic impurity has a greater molecular weight than a phosphorous impurity and can therefore cause substrate damage and current leakage. On the other hand, phosphorous has a greater diffusion rate than arsenic and can therefore cause a short channel effect in the transistor. As a result, phosphorous is generally used for the formation of transistors in the cell array region, for clear on/off operation and improved refresh time. In the peripheral region, phosphorous is generally used for long channel transistors, and arsenic is generally used for short channel transistors, despite the danger of leakage loss.
As described above, phosphorous ions have a greater diffusion rate, which increases the short channel effect. To address problems with phosphorous ions and to obtain a maximum effective channel length, cell array NMOS transistors in the cell array region are formed according to the following process sequence. After a gate spacer 24 is formed on the lateral sidewall of the gate 22, an impurity ions implanting process is performed using the gate 22 and gate spacer 24 as a mask, to form an n-type impurity diffusion region 26 and thereby obtain a maximum effective channel length. A heat treatment is required, however, to drive out n-type impurities into the semiconductor substrate both outside of the gate electrode. It is very difficult, however, to diffuse out n-type impurities to a desired depth within the semiconductor substrate.
Also, the impurity in the peripheral region simultaneously diffuses out and the effective channel length of the transistor is likewise reduced, thereby causing the device fail. In particular, a p-type impurity diffusion region of the peripheral PMOS transistor in the peripheral region is formed by implanting boron (B), which has a greater diffusion rate. As a result, the peripheral PMOS transistor is greatly affected by the reduction of the effective channel length.
To address the effect of the reduced effective channel length in the peripheral region, an n-type low-concentration impurity diffusion region can be replaced by a different n-type low concentration impurity diffusion region as shown in FIG. 1C. By doing this, the problem of reduction of the effective channel length encountered in the p-type diffusion region can be prevented. As can be seen in FIG. 1C, a high concentration p-type impurity diffusion region is overlapped with low concentration n-type impurity diffusion region. However, the formation of such diffusion region configuration requires very careful controlling of both the thickness of the gate spacer 34 and of the annealing temperature. Also, the diffusion of a high concentration p-type impurity makes the impurity in the LDD region maintain a high concentration, thus making it difficult to prevent hot carrier effect.