1. Field of the Invention
The present invention relates to a method for dividing a first binary number N1 by a second binary number which can be written in the form 2n/k, n and k being whole numbers, to obtain a result N2.
2. Description of the Related Art
Binary division is an arithmetic operation which can be implemented in various ways in an integrated circuit. When possible, the binary division can be done with a hard-wired logic circuit having a very simple structure. For example, the division of a number N1 by a number forming a power of 2, i.e., the calculation of N1/2n, is done by performing n right shifts of the bits of the number N1. For example, the division of 15, i.e., 00001111 in binary, by 16, is obtained by performing four right shifts of the bits of the number N1, because 16=24. The number 00000000.1111 is obtained, i.e., 0.9375 in decimal.
Within the scope of the production of a radio frequency identification (RFID) contactless integrated circuit conforming to the industrial specification EPC™-GEN2 (“Radio-Frequency Identity Protocols Class-1 Generation-2—UHF RFID Protocol for Communications at 860 MHz-960 MHz”), the authors of the present invention were faced with the need to provide a circuit capable of dividing a binary number by 64/3.
Such a division by 64/3 is provided for by the above-mentioned specification to divide a counting value supplied by a counter that is activated for the duration of an event. The counting is paced by an internal clock signal. After acquisition of the counting value, the integrated circuit divides this value by 64/3. The result of the division is then used as a set-point value for supplying an output signal the period of which is synchronized with the duration of the event.
Although such a division can be done with sophisticated calculation algorithms, using a microprocessor or an arithmetic coprocessor, the UHF contactless integrated circuits produced according to the specification EPC™-GEN2 are intended for the manufacture of low cost price contactless tags. They should consequently have a very simple structure. Thus, the use of a costly calculation circuit which occupies a large surface area of silicon is not possible. In particular, the use of a microprocessor or of a coprocessor is ruled out. The division should be done by a hard-wired logic circuit and preferably asynchronously, i.e., without the need to pace calculation steps by means of a clock signal.