1. Field of the Invention
An exemplary embodiment herein generally relates to a method and device that generates a waveform, having a selected programmable duty cycle, by iteratively incrementing a pulse width of an active portion of the waveform. In particular, a waveform generator of an exemplary embodiment herein may receive an input from a divide-by-n counter, which outputs a duty cycle that varies with the divide-by-n setting of the counter, and may output a selected programmable duty cycle waveform across all possible divide-by-n settings of the counter, without requiring a separate duty cycle counter for each possible divide-by-n setting.
2. Description of Related Art
Many electronic circuits include various logic circuits, e.g., processors, which operate at very high frequencies. Clocks for these logic circuits may be provided by multiplier circuits using phase-locked loops (PLLs) that increase a lower frequency output, e.g., 50 or 100 MHz, to a higher operating frequency for the logic circuit.
Referring to FIG. 1, a phase-locked loop (PLL) can include a phase/frequency detector 110, a loop low-pass filter and charge pump 120, and a voltage-controlled oscillator (VCO) 130. The phase/frequency detector 110 compares two input frequencies and generates an output that is a measure of their phase/frequency difference. If the first input frequency, fREFCLK, does not equal the second input frequency from a negative feedback loop, the phase/frequency detector 110 produces a phase-error signal, εΔφ. Operating on the phase-error signal, a low-pass filter and charge pump 120 provide a voltage control signal, which is applied to the VCO 130. In response to the voltage control signal, the VCO output, fVCO, changes such that the difference between fREFCLK and the second input frequency from the negative feedback loop is minimized. When fVCO is fed back to the phase/frequency detector 110, fVCO quickly “locks” onto the input frequency, fREFCLK, maintaining a fixed phase/frequency relationship to the first input frequency.
A frequency multiplier circuit, using a PLL, is typically produced by adding one or more dividers 140, e.g., divide-by-n counters, into the feedback loop between the output of the VCO 130 and the second input, fCOMP, to the phase/frequency detector 110, as shown in FIG. 1. The frequency multiplier circuit produces a VCO output, fVCO, which is a multiple, n, of the input frequency, fREFCLK. Changing the value of the divide-by-n setting in any of the one or more dividers 140 will result in a commensurate change in the output frequency, fVCO.
One type of divide-by-n counter is a linear feedback shift register (LFSR). The LFSR provides: programmable divide-by-n settings, where n is an integer; high speed; a small footprint; and low power consumption. The output of an LFSR divide-by-n counter has a duty cycle that varies with the value, n, of the divide-by-n counter. However, in the PLL feedback loop of a frequency multiplier circuit, the duty cycle of an LFSR divide-by-n counter is not of concern because the phase/frequency detector 110 is only triggered by either positive or negative edges of the LFSR divide-by-n counter.
Referring to FIG. 1, by further adding an external divider 150, which is external to the PLL feedback loop and the output of the VCO 130, the output frequency of the frequency multiplier circuit can be further varied to produce a timing signal, OUT, for use at various locations within a larger electronic circuit. In this case, if the external divider 150 were an LFSR divide-by-n counter, the external LFSR divide-by-n counter would also provide the benefits of programmable divide-by-n settings, high speed, small size and low power. However, many timing signals require not only a specific frequency, but also a specific duty cycle. As explained above, an LFSR divide-by-n counter cannot produce a single specific duty cycle over a range of divide-by-n settings. Therefore, an external LFSR divide-by-n counter 150, by itself, would be unsuitable when one seeks an output of a single specific duty cycle over a range of divide-by-n settings of the external LFSR divide-by-n counter 150.
The conventional solution to providing a single specific duty cycle for the output of external divider 150, whose duty cycle varies over a range of divide-by-n settings, is to couple the external divider 150 with a separate duty cycle counter, which generates the single specific duty cycle, for each of its divide-by-n settings. For example, assume a particular external LFSR divide-by-n counter outputs a 100 MHz signal, which does not have a 50% duty cycle, and that a 50% duty cycle is required for a 100 MHz timing signal. In this case, the 100 MHz output from the external LFSR divide-by-n counter is fed into a single separate duty cycle counter, which produces the required 50% duty cycle. The output of this single separate duty cycle counter, from among the n separate duty cycle counters that generate a 50% duty cycle for each of the divide-by-n settings of the external divider, is enabled by multiplexing. The remaining n−1 separate duty cycle counters that generate a 50% duty cycle are disabled. This solution works, but as the number of divide-by-n settings increases for the external divider 150, the footprint of the n separate duty cycle counters that generate a single specific duty cycle rapidly becomes prohibitive. Furthermore, this solution requires additional circuitry to deal with odd divide-by-n settings, i.e., odd divide-by-n settings must be shifted ½ of a divide-by-n cycle in order to generate a 50% duty cycle.
There remains a need for a method and device that generates a waveform, in which the device receives a varied duty cycle input from a divide-by-n counter, based on the divide-by-n setting of the counter, and which outputs a selected programmable duty cycle waveform across all possible divide-by-n settings of the counter, without requiring a separate duty cycle counter for each possible divide-by-n setting.