1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a combination of dielectric materials placed upon an integrated circuit topography to form a highly planar interlevel dielectric structure having minimal stress properties.
2. Description of the Relevant Art
Manufacture of an integrated circuit involves numerous processing steps. Electronic devices must be patterned within a semiconductor substrate, and the patterned devices must be interconnected to one another to form a densely arranged integrated circuit. Due to rapid advances in layout density, interconnect between devices may involve numerous levels of interconnect stacked upon each other with a dielectric placed therebetween. Stacking of interconnect must be closely monitored to ensure that the interlevel dielectric is sufficient to electrically isolate the stacked conductors. Moreover, the interlevel dielectrics must be deposited in such a manner as to present a fairly even or smooth (i.e., planar) upper surface upon which a subsequent interconnect layer is placed. If the upper surface of the dielectric is not planar, then subsequent processing problems can occur such as step coverage and depth of focus problems.
Referring now to FIG. 1, a cross-sectional view of a portion of an integrated circuit 10 is shown manufactured according to a prior methodology. Specifically, integrated circuit 10 includes a substrate 12 having an upper surface upon which a plurality of interconnect conductors 14 are arranged. Conductors 14 comprise one level of interconnect and, for illustrative purposes, comprise the first level of interconnect. After conductors 14 are formed, a dielectric material 16 is placed above and between conductors 14. A second level of conductors (not shown) can be placed upon the upper surface of dielectric 16 to form multilevel interconnects. Moreover, another dielectric (not shown) can be placed over the second level of conductors, and the process repeated depending upon the number of interconnect levels desired.
It is important that the interlevel dielectric exhibit numerous mechanical as well as electrical properties. Electrically speaking, the dielectric must be substantially nonconductive and must provide a barrier against movement of mobile ions between conductive overlayers and conductive underlayers. Mechanically speaking, the dielectric must be easily etched, at a substantially uniform etch rate, and must exhibit conformal coverage and, if desired, highly planar coverage above and between uneven or non-planar underlayer. Providing a dielectric which is both conformal as well as having an upper surface which is substantially planar is difficult to achieve.
Referring now to FIG. 2, problems associated with conventional dielectric structures are illustrated. Area 18 of densely patterned conductors 14 requires a substantially planar upper surface of dielectric 16. Thus, dielectric 16 must be conformal, but more importantly, dielectric 16 in area 18 must have an upper surface which is substantially planarized. Densely patterned conductors in area 18 form an uneven topography at the upper surface of dielectric 16 if dielectric 16 is not planarized. Resulting from an uneven dielectric upper surface is poor step coverage of subsequent conductors placed within area 18. Planarization in area 20 is not as crucial as in area 18. Namely, area 20 does not present severe unevenness at the upper surface of conductors 14 and, thereby, will not produce densely patterned disparities in the upper surface topography of dielectric 16.
FIG. 2 not only illustrates the need for conformal dielectric 16 in area 20 and planarizable dielectric 16 in area 18, but also suggests problems associated with lack thereof. In particular, if the upper surface of dielectric 16 in area 18 is not substantially planar, then upper interconnect conductor 22a may experience step coverage problems. Moreover, conductor 22b in area 20 may be larger (wider) than conductor 22a due to another problem often referred to as "depth of focus" problem. Depth of focus problem results from lithography process and, more specifically, from a disparity in resist removal caused by the relative depth of the resist being removed. If the resist (and underlying interconnect) is at a lower elevation level (i.e., is "defocused") relative to an upper elevation level, then the defocused area will cause a wider line width. An illustrated example is shown by the difference between the wider interconnect 22b than that of the narrower interconnect 22a. A shorter wavelength and a smaller numerical aperture of the optical projection source will lessen the depth of focus problem, but will not eliminate it. It is therefore essential that the upper surface of dielectric be maintained as a substantially uniform planar surface both to minimize step coverage problems and depth of focus problems.
Many manufacturers and researchers have focused upon solutions to the planarization problem by carefully selecting the dielectric being used and by selectively etching or polishing the upper dielectric surface. U.S. Pat. No. 4,954,459 describes a dielectric which comprises either tetraethoxysilane (TEOS) or chemical vapor deposition (CVD) oxide. Select areas of the TEOS or CVD dielectric can be removed by subsequent etch-back and polishing steps in order to produce a highly planarized upper surface. While TEOS and CVD dielectrics are highly conformal, they are not highly planarizable unless subsequent etch-back and polishing steps are performed. Unfortunately, subsequent chemical or mechanical planarization steps (etch-back and polish) are time consuming and may leave additional contaminants upon the substrate topography. In order to provide a more planarizable dielectric than TEOS or CVD oxide, spin-on glasses (SOG) are often used. SOGs often called organic silicates (which includes siloxanes), are applied in liquid form across the upper surface of the substrate in the same manner as, for example, photoresist. The liquid silicate is then heated to convert it to a silica film. The liquid silicate easily flows into any deformational valley at the upper surface of the interconnect topography in order to fill and thereby planarize the upper surface. Unfortunately, SOG dielectrics are usually of a lower density than TEOS or CVD dielectrics. The SOG film undergoes a water sorption process that, when subjected to subsequent contact formation and aluminum deposition, causes water "outgassing" to occur. Water outgassing can lead to severe degradation and possible open-circuit failure in small contact windows etched through the SOG. See, e.g., Lifshitz, et al., "Water-Related Degradation of Contacts in the Multilevel MOS IC with Spin-On Glasses as Interlevel Dielectrics", IEEE Electron Device Letters, Vol. 10, No. 12, December 1989.
While TEOS and CVD dielectrics (oxides) are highly conformal and perform well in sparsely patterned areas 20, they do not perform well in densely patterned areas 18. Conversely, SOGs are well suited in densely patterned areas 18, but are usually avoided in sparsely patterned areas 20. Additionally, since TEOS and CVD oxides cannot be easily planarized to suit areas 18 and while SOGs exhibit water outgassing, neither dielectric, in and of itself, provides an adequate solution to the planarization problem. Accordingly, many researchers and manufacturers have focused upon an interlevel dielectric comprising both a deposited oxide (CVD or TEOS) and an SOG. The multi-layered dielectric structure achieves the advantage of presenting a highly conformal dielectric within area 20 and a planarized upper surface within area 18. Unfortunately, the combinational dielectric structure often experiences severe cracking caused by intrinsic stresses within each layer as well as thermal expansivity problems between layers. It is possible that the primary source of the stress properties which cause cracking occur at the interface between the interconnect (or silicon substrate) and the dielectric. In many conventional designs, the dielectric comprises a sandwich structure of an SOG placed between CVD oxides. The CVD oxide which contacts the interconnect or substrate is subjected to significant thermal expansion stress at the juncture as well as inherent, intrinsic stress within the CVD (or TEOS) film.