1. Field of the Invention
This invention relates to an arithmetic device applied to, for example, a microprocessor, and more particularly to an arithmetic device capable of obtaining high-accuracy calculation results.
2. Description of the Related Art
A processor generally reads the data temporarily held in a general-purpose register according to an issued instruction and performs an arithmetical operation. For example, consider a case where expression (1) is calculated on a processor having a 32-bit general-purpose register and a computing unit. Program (2) shows an example of assembler instructions for calculating expression (1):d=(a+b+c)>>2  (1)
where R0=a, R1=b, R2=c, R5=dADDR5,R0,R1ADDR5,R5,F2SRLR5,R5,2  (2)
Here, ADD, which is an add instruction, means adding the contents of the general-purpose registers written second and third in the instruction and substituting the result into the general-purpose register written first in the instruction. For example, an ADD instruction written in the first row of program (2) means adding the data held in general-purpose registers R0 and R1 and holding the result in general-purpose register R5. An ADD instruction means adding the data held in general-purpose registers R5 and R2 and holding the result in general-purpose register R5. An SRL instruction is a shift instruction to shift the contents of the general-purpose register written second in the instruction right (or in the LSB direction) a fixed value written third in the instruction and hold the result in the general-purpose register written first in the instruction.
The calculation accuracy when the program is executed with the processor depends on the bit width of the general-purpose register and the bit width of the computing unit. Specifically, when a 32-bit processor adds 32-bit data “a” and 32-bit data “b”, this may produce a carry. In this case, the calculation result cannot be held correctly with the 32-bit general-purpose register. As described above, when data that might cause an overflow is dealt with, a general-purpose register and a computing unit whose bit width is greater than 32 bits, for example, a 40-bit general-purpose register and a 40-bit computing unit, have to be used. Recent processors have many general-purpose registers. Accordingly, if the bit width of the general-purpose register and computing unit is set to 40 bits, a problem arises: the occupied area of the general-purpose registers in the processor is large.
In a case where there area 32-bit variables “a,” “b”, “c”, and “d”, suppose calculation as shown in equation (3) is made:d=(a+b+c)/4  (3)
In this case, although the value of the final calculation result “d” is invariably a value equal or smaller than 32 bits, it can exceed 32 bits in the middle of calculation, depending on the values of “a”, “b”, and “c”. When an overflow occurs only in the middle of calculation, the bit width of the general-purpose register need not necessarily be increased. In this case, the following devices are frequently used: they are an accumulator composed of, for example, a 33-bit pipeline register for holding the intermediate result of the computing unit and a 40 bit×33 bit adder for adding the contents of the 33-bit register and the data in a 40-bit register and causing the 40-bit register to hold the addition result and a selector for selecting the data in either the 40-bit register or the 33-bit register.
Expression (4) shows an example of writing equation (3) in, for example, the C language. Program (5) shows an example of assembler instructions for calculating expression (4).d=(a+b+c)>>2  (4)
where R0=a, R1=b, R2=c, and R5=dACCR0,R1ACCR2ACCSRL2ACCMOVR5  (5)
In program (5), suppose ACC is an accumulation instruction on an accumulator, ACCSRL is an instruction to shift the contents of the accumulator right a fixed value and load the result into the accumulator again, and ACCMOV is an instruction to copy the contents of the accumulator into a specified general-purpose register. For example, the first row in program (5) means accumulating the data in the general-purpose registers R0 and R1. The second row means further accumulating the data in the general-purpose register R2 to the accumulation result. ACCSRL in the third row means shifting the data in the accumulator right 2 bits. ACCMOV stores the data in the accumulator into the general-purpose register R5.
Using the accumulator enables calculations to be done at high speed using the 40 bit×33 bit adder. In this case, however, the accumulator needs a register whose bit width is large enough to hold the data in the middle of calculation and an adder with the same bit width. Thus, having many accumulators increases the occupied area of the accumulators in the chip. Moreover, an increased number of accumulators increases the number of stages of pipelines, which makes the configuration more complex. Furthermore, there is another problem: an instruction to load the data from the accumulator into a general-purpose register or a memory is needed.
As techniques related to the arithmetic device, Jpn. Pat. Appln. KOKAI Publication No. 2001-109613 has disclosed an arithmetic device comprising a calculation correcting circuit which, when an overflow has occurred in the computing unit, increments or decrements higher-order bits in first input data, and an output data setting circuit, which receives the outputs of the computing unit and calculation correcting circuit and outputs the M-bit calculation result.
Furthermore, Jpn. Pat. Appln. KOKAI Publication No. 07-146777 has disclosed an arithmetic device which makes the calculation accuracy variable and reduces the power consumption by decreasing the number of significant figures.
Accordingly, there has been a demand for an arithmetic device capable of suppressing an increase in the occupied area in the chip and doing high-accuracy calculations even in such a calculation as permits the result in the middle of calculation to exceed the bit width of the general-purpose register.