The present invention relates to a MOS type semiconductor device and a method for manufacturing the same.
In order to operate a MOS.LSI at high speed or to improve the packaging density, it is advantageous to form a MOS transistor on an insulating substrate consisting of, for example, sapphire or spinel. This type of MOS semiconductor device is generally used as a MOS.LSI of SOS structure according to which a MOS transistor is formed on a silicon layer which is, in turn, formed on a sapphire substrate. FIG. 1 is a plan view of a p-channel transistor of a MOS.LSI of SOS structure, and FIG. 2 is a sectional view along the line II--II of FIG. 1. On a sapphire substrate 20 is formed a silicon layer which is completely covered by a field insulator film 22 for insulation. This silicon layer consists of an element region 24 and p.sup.+ -type diffusion wiring layers 26a and 26b extending at the end of this element region 24 along the direction of the channel length. In the element region 24 are formed a p.sup.+ -type source region 30 and a p.sup.+ -type drain region 32 with an n.sup.- -type substrate region 28 interposed therebetween, in which the channel is to be formed. The source region 30 is connected to the p.sup.+ -type diffusion wiring layer 26a, and the drain region 32 is connected to the p.sup.+ -type diffusion wiring layer 26b. A gate electrode 36 is formed on the substrate region 28 with a gate oxide film 34 of silicon oxide interposed therebetween.
In a MOS type semiconductor device of SOS structure according to this construction (hereinafter referred to as SOS/MOS for brevity), each element region 24 is separated from adjacent regions (not shown) by the insulating substrate 20 of sapphire and, the diffusion capacitance of the element region 24 is extremely low. Moreover, the capacitances of the diffusion wiring layers 26a and 26b and the general wiring capacitances are also extremely low. This allows high speed operation of the semiconductor elements. Since the semiconductor elements are insulated and separated from each other, a well diffusion layer need not be formed in the case of a CMOS semiconductor device. This prevents latch-up phenomenon from occurring even when the distance between the semiconductor elements is small. Since the diffusion wiring layers 26a and 26b are separated from the diffusion wiring layers of other semiconductor elements by insulators, punch-through phenomenon will not occur when the diffusion wiring layers are close to each other. The semiconductor elements may thus be formed at a high packaging density.
The SOS/MOS has the advantages as described above as well as the drawbacks to be described below. As may be seen in FIGS. 1 and 2, in an SOS/MOS a substrate electrode is not generally formed since it is hard to form. For this reason, in the case of a p-channel transistor as shown in FIGS. 1 and 2, for example, the potential at the n.sup.- -type region (hereinafter referred to as the substrate region) below the gate electrode 36 where the channel is to be formed is unstable, causing the so-called floating substrate effect in which the potential of the substrate region floats. This results in problems of characteristics to be described below. When a leakage current flows between the drain region 32 and the substrate region 28, charge is stored in the substrate region 28, and the substrate region 28 is forwardly biased with respect to the source region 30. As a result, the threshold voltage is lowered and the transistor may not be cut off. Furthermore, the voltage-current characteristics of the transistor involves the kink phenomenon, and abnormal current flows make the operation of the transistor unstable.
In the case of an n-channel transistor, the so-called charge pump phenomenon arises wherein the channel electrons are left in the substrate region when the transistor is cut off. A reverse bias is thus induced across the substrate region and the source region. The threshold voltage of the transistor is raised by the back gate bias effect caused by the reverse bias. Since the transconductance gm is lowered, the operation delay time tends to depend on the frequency.
In order to eliminate these drawbacks which may be caused in an SOS/MOS due to the floating substrate effect, an SOS/MOS, as shown in FIGS. 3 and 4, has been proposed wherein a substrate wiring layer 38 is formed to extend from the substrate region 28 in the direction of the channel width. A constant potential is supplied to the substrate region 28 through the substrate electrode formed in the substrate wiring layer 38. FIG. 3 is a plan view of a p-channel transistor in a conventional SOS/MOS with a substrate electrode, and FIG. 4 is a sectional view along the line IV--IV of FIG. 3. The substrate wiring layer 38 consists of n.sup.+ -type silicon.
In a conventional SOS/MOS wherein the substrate electrode is formed as shown in FIG. 3, the gate electrode 36 terminates at a part slightly outside the end part of the element region 24 and the end part 40 of the gate electrode 36 is widened, so that the substrate wiring layer may be self-aligned using the gate electrode 36 as a mask. The width of the end part 40 of the gate electrode 36 is increased for the reasons to be described below.
The gate electrode 36 is patterned by photolithography. When an error is caused in the mask alignment, the gate electrode 36 is misaligned. Therefore, if the end part of the gate electrode is not widened, a gate electrode 36a as shown in FIG. 5 is formed. Thereafter, a p-type impurity such as boron is doped using the gate electrode 36a as a mask to form a p.sup.+ -type source region 30a and a p.sup.+ -type drain region 32a. Further, an n-type impurity such as phosphorus is doped to form an n.sup.+ -type substrate wiring layer 38a. FIG. 6 shows an element region 24a and the substrate wiring layer 38a with the gate electrode 36a and the insulating layer being removed. The source region 30a and the drain region 32a formed by doping an impurity using the gate electrode 36a as a mask are of p.sup.+ -type. On the other hand, since the n-type impurity is doped in the element region 24a before the formation of the source region 30a and the drain region 32a to render the element region n.sup.- -type, a substrate region 28a below the gate electrode 36a where the channel is to be formed is of n.sup.- -type. The substrate wiring layer 38a is of n.sup.+ -type, as has already been described. When the gate electrode 36a is misaligned, the p.sup.+ -type drain region 32a and the n.sup.+ -type substrate wiring layer 38a form a direct junction at part A. Consequently, since the junction capacitance is significantly increased by the high concentration p.sup.+ -n.sup.+ junction, the operation speed of the semiconductor element is lowered.
On the other hand, when an end part 40 of the gate electrode 36 is widened as shown in FIG. 3, the element region 24a and the substrate wiring layer 38a as shown in FIG. 7 are formed even when the gate electrode 36 is formed as misaligned. In this case, since the end part 40 of the gate electrode 36 is widened and is used as a mask when forming the p.sup.+ -type source region 30a and the p.sup.+ -type drain region 32a by doping an impurity, the misalignment in the gate electrode 36 does not result in formation of a direct junction between the p.sup.+ -type drain region 32a and the n.sup.+ -type substrate wiring layer 38a. Since the high concentration p.sup.+ -n.sup.+ junction is not formed, a significant increase in the junction capacitance as described above may be prevented. Although the junction areas between the source region 30a and the substrate region 28a and between the drain region 32a and the substrate region 28a are widened, these junctions are p.sup.+ -n.sup.- junctions. The capacitance in this case is much smaller than the junction capacitance of the high concentration p.sup.+ -n.sup.+ junction as described above.
For the reasons described above, the end part 40 of the gate electrode 36 is widened in the conventional SOS/MOS wherein a substrate electrode is formed. However, widening of the end part 40 of the gate electrode 36 causes some problems as follows:
(1) Since the channel length L' of the element region 24a wherein the gate electrode is widened is longer than the channel length L of the element region wherein the gate electrode is not widened, the channel length is not constant throughout the entire element region. Thus, desired characteristics of the semiconductor elements may not be obtained.
(2) Since the area of the end part 40 of the gate electrode is made greater, the gate electrode capacitance is increased. The width (channel length) of the non-widened part of the gate electrode of an SOS/MOS of this type is generally about 2 .mu.m. However, the width of the end part 40 of the gate electrode in this case is 8 to 10 .mu.m. Therefore, the gate electrode capacitance increases due to the end part 40 to an extent which may be considerable.
(3) The widening of the end part 40 of the gate electrode increases the element area.