1. Field of the Invention
The invention relates to an offset correction circuit for a phase detector producing an offset error voltage. More particularly, the invention relates to an offset correction circuit which determines and stores the offset error voltage of the phase detector prior to the application of an input signal to the phase detector.
2. Description of the Prior Art
As is well known in the art, phase modulation is utilized to transmit information. One system of phase modulation, known as phaseshift keying (PSK), modulates digital information by shifting the phase parameter of an AC carrier signal usually between 0.degree. and 180.degree.. This type of modulated signal is generally transmitted as a suppressed carrier signal. Demodulation of a PSK signal requires that the PSK signal be multiplied by a reference signal generated in the demodulator. The reference signal must manifest accurately the frequency and phase of the incoming PSK signal. The components in which the PSK signal and the reference signal generated in the demodulator are multiplied are generally designated as phase detectors or multipliers.
Even if the reference signal is at the correct frequency but slightly out of phase with the incoming PSK signal, the output will be attenuated. For a difference in phase of close to 90.degree., the output of the phase detector will be near zero and a difference greater than 90.degree. will reverse the polarity of the output of the phase detector. Thus, it is desirable that the reference signal be accurately in phase with the incoming PSK signal.
A circuit which employs the above principles is a two phase-locked loop demodulator, also called a Costas loop demodulator. As the name implies, the output of the phase detectors is used as an input to a voltage controlled oscillator generating the reference signal. In a two phase-locked loop demodulator, each of the two loops has a phase detector but only one voltage controlled oscillator is provided. However, the reference signal to one loop is shifted 90.degree. so that when the reference signal is in phase with the incoming PSK signal, the output of the phase detector in that loop is zero. The output of the phase detector in the other loop is negative or positive depending on whether the value of the phase difference is close to 0.degree. or 180.degree., respectively.
It is well known that if the incoming signal has a low signal to noise ratio it is desirable that the output of the phase detectors not contain any offset error voltages. An offset error voltage being undesirable noise that is caused by variations in the parameters of the individual circuit elements of the phase detectors. The presence of this offset error voltage will constitute a portion of the input to the voltage controlled oscillator which generates the reference signal and will significantly degrade the performance of the phase-locked loop.
One means currently being utilized to obviate the possibility of an offset error voltage is to use expensive well-balanced phase detectors which do not produce an offset error voltage. Manual offset adjustments to correct for the offset error voltage have also been provided in the phase-locked loops.