1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) circuit which is used in an optical disk device which records/reproduces information to/from a disk-like recording/reproducing medium. More particularly, the present invention relates to a PLL circuit which generates a signal of which the phase is synchronized with wobbling in case of recording/reproducing information to/from an optical disk on which the track is wobbled.
2. Description of the Related Art
Conventionally, in a case where data is recorded/reproduced to/from an optical disk, address information previously embedded on the optical disk is detected to search for a location on the disk, a desired track location on the disk is accessed based on the detected address information, and then user data is recorded/reproduced to/from the accessed location. Here, on many kinds of optical disks, address information and clock information are embedded by finely wobbling a groove in its width direction.
In the optical disk like this, typically a wobbling constitution has a sine wave shape, and thus a reproduced wobbling signal has approximately a sine wave shape. Then, the address information is embedded by executing modulation such as FSK (frequency shift keying), PSK (phase shift keying), MSK (minimum shift keying) or the like to a part of the reproduced wobbling signal or by providing pre-pits on the land between the adjacent grooves in parallel with the wobbling of the groove.
In case of reproducing the addresses on the optical disk like this, some kind or another carrier signal synchronized with the reproduced wobbling signal is generated, detection timing of the address information such as a PSK modulation component or a pre-pit arranged only a part of the wobbling is captured, and a bit value which is the address information is detected based on the captured timing.
Further, in order to execute velocity control to achieve constant liner velocity, spindle control is executed based on the above carrier signal so as to make a sine-wave frequency of the wobbling signal constant.
Consequently, as disclosed in Japanese Patent Application Laid-Open No. 2004-362630, a PLL circuit is used to generate the carrier signal synchronized with the wobbling signal. Here, the PLL circuit includes a phase comparator (phase error detector), a loop filter and a VCO (voltage controlled oscillator). Hereinafter, the PLL circuit which generates the carrier signal synchronized with the wobbling signal is called a wobble PLL circuit.
As a phase detection method in the wobble PLL circuit, a so-called heterodyne detection method of detecting a beat component which is a frequency difference between two signals respectively having close frequencies is used.
Incidentally, FIG. 14 illustrates an example of a PLL device (circuit). In FIG. 14, the PLL device includes an AD (analog-to-digital) converter 101 having a ten-bit width, a multiplier 102, an LPF (low-pass filter) (or a carrier cut filter) 103 for eliminating a frequency component twice the carrier signal, a loop filter 104, and a digital VCO 105. Here, it should be noted that the LPF 103 is also called a carrier cut filter as illustrated in FIG. 14.
In FIG. 14, a wobbling signal photoelectrically converted by a not-illustrated optical pickup and then reproduced through a matrix operation is converted into ten-bit digital data by the AD converter 101, and then multiplied to an eight-bit carrier signal by the multiplier 102. By doing so, a frequency difference component and a frequency sum component between the wobbling signal and the carrier signal are generated. Then, the generated frequency sum component is eliminated by the LPF 103 whereby only the generated frequency difference component can pass through the LPF 103. Subsequently, based on the passed frequency difference component, a control signal is properly generated by the loop filter 104 having a loop characteristic, and the generated control signal is then supplied to a control input of the digital VCO 105 to form a loop as illustrated in FIG. 14, thereby controlling the frequency of the carrier signal which is output from the digital VCO 105.
By applying such a constitution as above, it is possible to generate the carrier signal which is phase-locked with the wobbling signal.
Incidentally, there are occasions when the DC (direct current) characteristic and the amplitude of a wobbling signal sent from an optical disk vary according to an amount of laser beam and reflectance of the disk. Therefore, to be able to accurately process the wobbling signal like this, as disclosed in Japanese Patent Application Laid-Open No. 2004-362630 and the above description, the multi-bit AD converter is used. Further, in the multiplier disposed at the subsequent stage of the AD converter, the AD-converted signal is multiplied to the multi-bit carrier signal.
Here, if it is assumed that the frequency of the reproduced wobbling signal is about 960 KHz, a sampling signal of which the frequency is 20 times or more the frequency of the wobbling signal is necessary to accurately reproduce the signal, whereby the operation frequency of about 20 MHz is necessary for the AD converter. Further, if it is assumed that the number of bits of the AD converter is ten and the number of bits of the carrier signal is eight, the multiplier having the 18-bit output has to operate at 20 MHz.
Ordinarily, as the operation frequency or the number of bits of the AD converter increases, the circuitry of the AD converter itself becomes complicated, and also power consumption increases. Further, as the number of bits of each of the two inputs to be multiplied increases, the size of the circuitry of the later-stage multiplier increases. Furthermore, as the size of the circuitry increases, operation velocity in an actual IC circuit is limited.
On the other hand, if decreasing the number of bits of the wobbling signal or the carrier signal or decreasing the frequency of the sampling signal, it decreases an S/N ratio of the wobbling signal after digitalization or decreases an S/N ratio in case of phase error detection, thereby resultingly degrading phase detection accuracy. As a result, there is a fear that performance of the PLL circuit degrades.
Further, as described in Japanese Patent Application No. H10-190468, in case of achieving all or a part of the circuits such as the multiplier and the like by analog circuits, the whole constitution is sensitive to temperature characteristics and element variations, whereby it is difficult to maintain sufficient circuitry performance.
Furthermore, in case of recording/reproducing the data to/from the disk at a high velocity, it is necessary to detect the phase error in the wobble PLL circuit at a high velocity. However, the above-described conventional circuitry constitution is not suitable for such a high-velocity operation.
In consideration of such problems as described above, a constitution which suppresses circuitry size and power consumption and has sufficient circuitry performance is desired for the PLL circuit.