A ball grid array (BGA) semiconductor package generally uses a substrate made of a resin material as a chip carrier, with a plurality of array-arranged solder balls being mounted on a bottom surface of the substrate and serving as input/output (I/O) connections for electrically connecting a chip to an external device. This makes the BGA semiconductor package have more I/O connections than a conventional lead-frame-based semiconductor package and satisfy the requirements for highly integrated chips. However, the more highly integrated the chip, the more heat would be generated. Therefore, how to effectively dissipate heat so as not to affect lifetime and reliability of the chip has become an important issue to be addressed.
In order to solve the foregoing problem of heat dissipation, U.S. Pat. No. 5,216,278 has disclosed a semiconductor package with a heat sink being directly attached to a chip and exposed from an encapsulant. As the heat sink is mounted right on the chip, heat generated by the chip can be directly dissipated to the atmosphere via an exposed surface of the heat sink, thereby effectively dissipating the heat from the chip.
Referring to FIG. 9, however, during a molding process for the semiconductor package disclosed by U.S. Pat. No. 5,216,278, a distance H between a top surface 10′ of a heat sink 1′ and an upper surface 30′ of a substrate 3′ mounted with a chip 2′ needs to be equal to a depth h′ of a molding cavity 40′ of a mold 4′. This is to ensure that the top surface 10′ of the heat sink 1′ would be exposed from the encapsulant 5′ and not have resin flashes thereon after the molding process, as well as the chip 2′ would not be cracked by pressure from the heat sink 1′. In other words, if the distance H between the top surface 10′ of the heat sink 1′ and the upper surface 30′ of the substrate 3′ is larger than the depth h′ of the molding cavity 40′, during the molding process, the mold 4′ would unduly press the heat sink 1′ and cause cracks of the chip 2′ that is directly attached by the heat sink 1′. On the contrary, if the distance H between the top surface 10′ of the heat sink 1′ and the upper surface 30′ of the substrate 3′ is smaller than the depth h′ of the molding cavity 40′, a resin material used for forming the encapsulant 5′ would flash over the top surface 10′ of the heat sink 1′. The resin flashes not only impair an appearance of a fabricated product but also reduce an area of the top surface 10′ of the heat sink 1′ exposed to the atmosphere, thereby deteriorating the heat dissipating efficiency. As a result, an additional deflash process is usually performed to remove the resin flashes on the top surface 10′ of the heat sink 1′. However, the deflash process complicates the overall fabrication processes of the semiconductor package and also increases the cost.
Moreover, in order to make the distance H between the top surface 10′ of the heat sink 1′ and the upper surface 30′ of the substrate 3′ equal to the depth h′ of the molding cavity 40′, the attachment between the heat sink 1′ and the chip 2′, the attachment between the chip 2′ and the substrate 3′, and the thickness of the heat sink 1′ all need to be precisely controlled and performed. However, such requirement of preciseness increases the packaging cost and also complicates the fabrication processes, and is thus difficult to be achieved in practice.
U.S. Pat. Nos. 5,736,785 and 5,477,626 have also disclosed similar semiconductor packages, which thus have the foregoing problems to be solved.
In order to prevent cracks of the chip due to pressure from the heat sink and to reduce the requirement of preciseness in fabrication, U.S. Pat. Nos. 6,522,428, 6,528,876, 6,462,405, 6,429,512 and 6,433,420 have respectively proposed a semiconductor package with a heat sink not in contact with a chip. The heat sink of this semiconductor package comprises a plurality of supporting portions attached to a substrate and a flat portion supported above the chip by the supporting portions, such that an appropriate gap is formed between the chip and the flat portion of the heat sink and is filled with an encapsulating resin. Since the chip is not in contact with the heat sink, heat generated by the chip cannot be directly transferred to the heat sink but must be transmitted by the encapsulating resin that has poor thermal conductivity. As a result, the heat dissipating efficiency would be adversely affected in the case of the heat from the chip being transferred via the encapsulating resin to the heat sink, such that the reliability and lifetime of the semiconductor package are also degraded in accordance with the unsatisfactory heat dissipating efficiency.
In order to resolve the drawback of the foregoing semiconductor package caused by no direct contact between the heat sink and the chip, U.S. Pat. Nos. 6,458,626 and 6,444,498 (having the same assignee as that of the present invention) have disclosed a semiconductor package with a heat sink being directly attached to a chip without leading to cracks of the chip or resin flashes on an exposed surface of the heat sink. Referring to FIG. 10, in this semiconductor package, a material layer 5″ is formed on a surface of a heat sink 1″ to be exposed to the atmosphere, wherein the material layer 5″ has poor adhesion with an encapsulating resin or the heat sink 1″. Then, the heat sink 1″ is attached to a chip 2″ mounted on a substrate 3″. Referring to FIG. 11, a molding process is performed to allow the encapsulating resin 4″ to completely encapsulate the heat sink 1″ and the chip 2″ and cover the material layer 5″ on the heat sink 1″. In other words, the depth of a molding cavity of a mold (not shown) used in the molding process is larger than a combined thickness of the chip 2″ and the heat sink 1″. Therefore, during the molding process, the mold would not come into contact with the heat sink 1″ and thus prevents the chip 2″ from being pressed and cracked. Furthermore, referring to FIG. 12, a singulation process is performed to cut off redundant portions and form individual semiconductor package units. Finally, referring to FIG. 13A, the encapsulating resin 4″ formed on the heat sink 1″ is removed. If the adhesion between the material layer 5″ and the heat sink 1″ is larger than that between the material layer 5″ and the encapsulating resin 4″, the material layer 5″ remains on the heat sink 1″ after the resin 4″ is removed from the material layer 5″, and no flash of the resin 4″ is left on the heat sink 1″ by virtue of the poor adhesion between the material layer 5″ and the resin 4″. Referring to FIG. 13B, if the adhesion between the material layer 5″ and the heat sink 1″ is smaller than that between the material layer 5″ and the encapsulating resin 4″, the material layer 5″ would be relatively more strongly attached to the resin 4″ and removed along with the resin 4″, such that no resin flash occurs on the heat sink 1″.
Although the foregoing semiconductor package in U.S. Pat. Nos. 6,458,626 and 6,444,498 does not have the problems of chip cracks and resin flashes on the heat sink, during the singulation process shown in FIG. 12, a cutting tool needs to cut the heat sink made of a metal material (usually copper) and is worn easily, making the packaging cost undesirably increased. Also, burrs are usually incurred at cutting sides of the heat sink exposed to the atmosphere after the singulation process and thus impair an appearance of a fabricated product. If the sides of the heat sink with burrs are subjected to a polishing process, the cost would be further increased and the fabrication processes would become more complicated.
Moreover, in U.S. Pat. No. 6,444,498, a polyimide tape is used and attached to the heat sink, such that after the singulation process, the encapsulation resin cured on the tape can be easily removed along with the tape from the heat sink, and no resin flash is left on the surface of the heat sink exposed to the atmosphere. However, although the use of polyimide tape provides a desirable advantage in U.S. Pat. No. 6,444,498, the polyimide tape is expensive and thus increases the overall cost of the fabrication processes.
Therefore, the problem to be solved here is to provide a semiconductor package with a heat sink, which can eliminate the above drawbacks in the prior art.