Error correction codes (ECC) are used in a variety of signaling applications to detect and correct errors relating to data transmission and storage. The codes generally provide redundancy to the original data so that, when the data is encoded via a particular ECC algorithm, a certain number of data errors may be identified and corrected upon decoding. The redundant portions of the encoded data may take the form of checksums, parity bits, or the like, depending on the type of ECC employed.
Memory systems have employed ECC to encode write data stored in a memory array. As the encoded data is accessed and decoded in response to a read operation, errors are detected and corrected. The corrected read data may then be transmitted back to the requesting device (such as a host or memory controller), and written back into the memory device as corrected data.
As memory density (through decreased device size and the storage of multiple bits per cell) and signaling rates increase, and with them, corresponding bit error rates, operations to re-write corrected data back into a given memory array may be expected to rise. Numerous re-writes may be problematic for memory devices that are susceptible to write endurance issues, such as flash or phase change memory devices. Moreover, numerous write operations to a flash or phase change array dissipate a significant amount of power.