Q:

Persisting an output in comb logic block

I'm having an issue persisting the value of gpo.
I want it to change only at the point in the code below.
gpo_int <= gpo_int when n_wr = '1';
gpo <= gpo_int;
write : process(n_en, n_wr) begin
  if n_wr = '0' and n_en='0' then
    case addr(15 downto 12) is
      when x"f" => -- i/o
        case addr(11 downto 8) is
          when x"0" => -- gpo
            gpo_int <= data;
          when others =>
            gpo_int <= gpo_int;
        end case;
      when others =>
        gpo_int <=  gpo_int;
    end case;
  end if;
end process;

gpo_int is a signal of std_logic_vector(7 downto 0) := x"00";
Firstly gpo_int is not persisted properly (I can see gpo change to x"00" when n_rw goes to '1'. Also is there any way of doing this more neatly (defining the truth table for the comb logic)?

A:

It seems like you are asking for a latch.  In FPGAs particularly, that's not usually the right thing to do (for a variety of reasons).  
Can you not use a clocked process to create the persistence you need using a flipflop?
process (clk)
begin
    if rising_edge(clk) then
        if n_wr = '0' and n_en ='0' and addr(11 downto 8) = x"F0" then
           gpo_int <= data;
        end if;
     end if;
end process;
gpo <= gpo_int;

