When implementing a capacitive structure in an integrated circuit (IC), two design criteria are often at the forefront of consideration; namely, accuracy and area. Accuracy of a capacitive structure indicates the degree to which its measured capacitance matches its expected capacitance. Depending on the application in which the capacitive structure is to be implemented, accuracy can be more or less important. For example, analog filters and voltage controlled oscillators (VCOs) are two exemplary applications that often require capacitors which are relatively accurate.
IC implementations of capacitive structures are particularly vulnerable to accuracy issues. Specifically, process variations, associated with the production of ICs, limit the accuracy that can be guaranteed for typical capacitive structures. Tunable Capacitor can be used to compensate for both capacitor variation and other component variations such as resistor (R) variation in RC constant circuits. However, the capacitive structures used to construct tunable capacitors are similarly vulnerable to accuracy issues. Conventional solutions attempt to provide a higher accuracy for a particular tunable capacitor at the expense of area—the second design consideration often contemplated in the implementation of a capacitor within an IC. However, because IC capacitive structures generally provide low capacitive density, any further increase in area is prohibitive.
Therefore, there exists a need for a system and method that provides for an accurate tunable capacitance within an IC, while limiting any additional area requirements.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.