1. Field of the Invention
This invention relates to power converters that need to provide regulated output(s) for some time after an input-voltage drop out.
2. Description of the Prior Art
The majority of today""s computer and computer peripherals require power supplies that are capable of operating in the 90-270-Vac range and can provide a hold-up time of at least 10 ms. Generally, the hold-up time is the time during which a power supply needs to maintain its output voltage(s) within the specified range after a drop-out of the line voltage. This time is used to orderly terminate the operation of a data-processing equipment or to switch over to the UPS operation after a line failure. The required energy to support the output during the hold-up time is obtained from a properly sized energy-storage capacitor CB, shown in FIG. 1(a). Generally, the front-end rectifier can be either a simple full-wave diode rectifier, or a rectifier with an active power-factor-correction (PFC) circuit.
To achieve a desired hold-up time, the dc/dc converter output stage in FIG. 1(a) must be designed to operate in a certain voltage range with minimum energy-storage-capacitor voltage VBMIN lower than voltage VBH that corresponds to the line voltage at which hold-up time is defined. With such a design of the dc/dc output stage, the energy storage capacitor delivers power to the output after a line dropout until the energy-storage-capacitor discharges to VBMIN, as illustrated in FIG. 1(b).
The relationship between the value of energy-storage capacitor CB and hold-up time TH is given by                                           C            B                    =                                    2              ·                                                P                  OH                                                  η                                      DC                    /                    DC                                                              ·                              T                H                                                                    V                BH                2                            -                              V                BMIN                2                                                    ,                            (        1        )            
where POH is the output power that needs to be provided during hold-up time TH and xcex7DC/DC is the efficiency of the dc/dc converter output stage.
As can be seen from Eq. (1), for a given VBH and VBMIN, larger power POH and/or longer hold-up time TH requires a larger energy-storage capacitor CB. As a result, in high-power application, the size of energy-storage capacitor(s) very often limits the maximum power density. Therefore, to maximize power density the size of energy-storage capacitors must be minimized. A limited size reduction of energy-storage capacitor CB in FIG. 1 can be achieved by extending the regulation range of the dc/dc converter output stage by minimizing voltage VBMIN at which the dc/dc converter output stage drops out of regulation. However, because of a strong trade-off between minimum regulation voltage VBMIN and the conversion efficiency of the dc/dc converter, VBMIN is usually restricted to 80% to 90 % of VBH. With such a selection of VBMIN, only a small part of the energy stored in CB is delivered during the hold-up period. The fraction of the delivered energy can be calculated from                                                         Δ              ⁢                              xe2x80x83                            ⁢                              E                CB                                                    E              CBH                                =                      1            -                                          (                                                      V                    BMIN                                                        V                    BH                                                  )                            2                                      ,                            (        2        )            
where xcex94ECB is the amount of the delivered energy to the output during hold-up time and ECBH is the total stored energy in CB at VCBH.
Equation (2) is shown in a graphical form in FIG. 2. As seen from FIG. 2, only 19% of stored energy is delivered to the load during the hold-up time if VBMIN is selected to be 0.9VBH. Similarly, if VBMIN is selected to be 0.8VBH, 36% of the stored energy is delivered to the output, i.e., still the majority of the stored energy is not used to supple the load during the hold-up time.
To utilize the majority of the stored energy during the hold-up time, VBMIN must be selected well below 80% of VBH. For example, 75% of the stored energy is delivered to the load for VBMIN=0.5VBH. However, with VBMIN=0.5VBH, the efficiency of the dc/dc converter and, therefore, the overall efficiency would be severally penalized because the dc/dc converter output stage would be required to operate with a wider input voltage range. Namely, to regulate the output in a wider input-voltage range, a wider duty-cycle range is needed, which requires that the transformer in the dc/dc converters has a smaller turns ratio. Generally, a smaller turns ratio increases the primary and, very often, secondary conduction losses, which deteriorates the conversion efficiency.
In this invention a method that substantially improves the utilization of the energy stored in the energy-storage capacitor without deterioration of the conversion efficiency is described.
In this invention, a method that substantially improves the utilization of the stored energy in the energy-storage capacitors of a power supply during the hold-up time is described. The improvement is achieved by providing two groups of energy storage capacitors, and by connecting one group of capacitors to the input of a hold-up-time extension circuit that has its output connected to the other group of energy-storage capacitors. (Each group of energy-storage capacitors may consist of a single capacitor, or a number of capacitors connected in parallel.)
The hold-up-time extension circuit is designed so that its output is regulated at voltage that is lower than the minimum regulation voltage of the output-stage dc/dc converter. As a result, the hold-up-time extension circuit is inactive during the normal operation mode. i.e., when the input voltage is present. In fact, during the normal operation mode both groups of capacitors are effectively connected in parallel so that their voltages are equal.
The hold-up-time extension circuit becomes activated after a line-voltage dropout when the voltage across the capacitors discharges to a voltage close to the minimum regulation voltage of output-stage dc/dc converter. Once the hold-up-time extension circuit is activated, the capacitors connected to the input of the hold-up-time extension circuit continues to discharge and provide energy to the regulated output of the hold-up-time extension circuit, which keeps the voltage across the capacitors connected at the output of the hold-up-time extension circuit constant at the voltage slightly above the minimum regulation voltage of the dc/dc converter output stage. Therefore, during this phase of operation, energy stored in the capacitors at the input of the hold-up-time extension circuit is used to deliver the required output power during the hold-up time. The hold-up time is terminated when the voltage of the capacitors at the input of the hold-up-time extension circuit reaches the minimum regulation voltage of the hold-up-time extension circuit.
The hold-up-time extension circuit can be implemented with any boost-like topology, i.e., with any non-isolated or isolated topology that can operate with its output voltage greater than the input voltage. For example, the boost, sepic, and flyback topologies are good candidates for implementing the hold-up-time extension circuit.
In power supplies with a front end implemented with an active power-factor correction circuit, the power-factor-correction circuit itself can be used during hold-up time to perform the function of the hold-up-time extension circuit. This implementation minimizes the number of power-stage and control components necessary to implement the hold-up time circuit, but requires more sophisticated detection and logic circuitry to properly implement hold-up-time extension function.
Finally, it should be noted that the method of this invention could be applied to not only to ac/dc, but also to dc/dc, dc/ac, and ac/ac power converters that require hold-up time capability.