Enhancement in performance of a semiconductor device by integration over a single LSI chip is not necessarily the optimum solution lately owing to the impact of limitations to miniaturization, and an increase in utilization cost of the most advanced process technology. Accordingly, integration in three-dimensional directions, implemented by stacking a plurality of LSIs one another has since attracted attention as a promising technology.
A system of electrical connection between stacked LSIs is important for realization of both desired function and performance of the stacked LSIs. A TSV (Through Silicon Via) system whereby a hole is bored in a silicon chip, and the hole is filled up with a conductor, thereby electrically connecting the surface of the chip with the back surface thereof is expected to be capable of miniaturization of electrodes in a stacking direction (TSVs) to such an extent as to approach metal interconnections on an LSI chip in respect of miniaturization, and as such, is regarded promising as the next-generation connection technology among systems for connection between the stacked LSIs. Accordingly, it is imagined that the days are not far off when logic circuits connected with each other by the TSVs across plural LSIs will be made up.
FIG. 1 is a view showing an example of a configuration of a three-dimensional logic circuit which is made up of plural LSIs in such stacked LSIs as described.
The three-dimensional logic circuit is comprised of two layers of LSI chips, referred to LSI_A, and LSI_B, respectively, and combinational logic circuits A, B, and D are mounted on LSI_A, while combinational logic circuits C, E are mounted on LSI_B, respectively. Further, TSVs 20a, 20b are provided between LSI_A and LSI_B, respectively, and a signal is propagated between the combinational logic circuits B, C, as well as between the combinational logic circuits D, E. Reference numerals 30a to 30h each are a flip-flop with a scan function attached thereto, for storing input/output data of the respective combinational logic circuits.
Data from each of the flip-flops 30a, 30b on LSI_A is inputted to the combinational logic circuit A, whereupon the combinational logic circuit A performs an operation therein, results of the operation being outputted to the combinational logic circuit D. Data from the flip-flop 30c on LSI_A, and data from the combinational logic circuit C on LSI_B via the TSV 20a are inputted to the combinational logic circuit B, whereupon the combinational logic circuit B performs an operation therein, results of the operation being outputted to the combinational logic circuit D. Data from each of the flip-flops 30d, 30e, on the LSI_B, is inputted to the combinational logic circuit C, whereupon the combinational logic circuit C performs an operation therein, results of the operation being outputted to the combinational logic circuit B on the LSI_A, and the combinational logic circuit E on the LSI_B. Data from the combinational logic circuit A, and data from the combinational logic circuit B are inputted to the combinational logic circuit D, whereupon the combinational logic circuit D performs an operation therein, results of the operation being outputted to the flip-flop 30f, the flip-flop 30g, and the combinational logic circuit E on the LSI_B.
Data from the combinational logic circuit C, and data from the combinational logic circuit D on the LSI_A, via the TSV 20b, are inputted to the combinational logic circuit E, whereupon the combinational logic circuit E performs an operation therein, results of the operation being outputted to the flip-flop 30h. 
A technique for performing a scan test, such as an internal scan test, a boundary scan test, and so forth, is well known as the traditional testing technique for inspecting whether or not a semiconductor device is normally made up. FIG. 2, there is shown an example of a configuration of a flip-flop 30 with a three-dimensional scan function attached thereto, for use in the scan test technique.
The flip-flop 30 with the three-dimensional scan function attached thereto incorporates a storage element 100 for signal retention, and a selector 200. The selector 200 has a function for selecting data to be inputted to the storage element 100 between a data input terminal PI and a scan input terminal SI in response to a mode designation signal md. If the mode designation signal md is “0”, operation of the flip-flop 30 will be in a normal operation mode, and a signal entering from the data input terminal PI is stored in the storage element 100 for once to be subsequently outputted to a data output terminal PO. If the mode designation signal md is “1”, the operation will be in a scan mode, and a signal entering from the scan input terminal SI will be in the scan mode to be stored in the storage element 100 before being outputted to the data output terminal PO, and a scan output terminal SO.
Herein, a shift register can be made up by connecting the scan output terminal SO to the respective scan input terminals SI of other flip-flops with the three-dimensional scan function attached thereto in such a way as to resemble beads strung on thread. Control of the mode designation signal md by following a predetermined procedure can render it possible to make setting of desired test data, and observation of an output result with respect to the combinational logic circuit to which this flip-flop with the three-dimensional scan function attached thereto is connected. A path for use in the setting of the test data, and the observation is called as a scan chain, and a path indicated by a dash and a dotted line, in, for example, the logic circuit of FIG. 1, is the scan chain. FIG. 1, interconnections for use in distribution of the mode designation signal md are omitted for the sake of simplicity.
There is described hereinafter the case of performing the scan test against a semiconductor device built on one sheet of LSI chip, for example, the LSI_A shown in FIG. 1.
First, the flip-flops 30a, 30b, and 30c with the scan function attached thereto are each actuated in the scan mode, and concurrently, a predetermined test pattern from outside the logic circuit is inputted thereto from a test data input terminal TDI_A prepared as an external terminal. Next, the flip-flops 30a, 30b, and 30c are set to the normal operation mode, and the combinational logic circuits A, B, and D are actuated. Then, an output of the combinational logic circuit D is fetched by the flip-flops. Thereafter, the flip-flops 30a, 30b, and 30c are again set to the normal operation mode, and respective values fetched by the flip-flops 30f, 30g, with the three-dimensional scan function attached thereto, respectively, are observed from outside the logic circuit by use of a test data output terminal TDO_A prepared as an external terminal.
As a technology for expanding application of the scan test to the plural LSIs, there have been disclosed techniques whereby respective test data input terminals of plural chips, and respective test data output terminals of the plural chips are connected with each other in a such way as to resemble the beads strung on thread, as shown in, for example, Patent Literature 1, and techniques whereby a branch interconnection is provided before and after respective test data input terminals as well as respective test data output terminals, as shown in, for example, Patent Literature 2.