In large scale integration, integrated circuits comprising semiconductor "chips" are mounted on a circuit package and the various input/output ports of the integrated circuit are connected individually to external pins which protrude from the package and afford interconnection with other systems. Thus, the number of different signals which can be coupled as input or output to the integrated circuit is limited by the number of pins in the integrated circuit package.
With recent developments in large scale integration, the number of pins ("pin-out") has become a design critical item. Specifically, in high precision digital signal processing integrated circuits, the number of bits per word is increasing from 8 bits to as high as 32 bits per word for maximum precision. The next largest procaseo industry standard pin-out for integrated circuit packages now stands a 132 pins. However, in the case of a simple multiplication operation performed on-chip for two 32-bit words, a total of 128 pins is required, which leaves only 4 pins out of 132 for control and power, an unacceptable situation. Accordingly, a design rule that has been practiced in this art is to assign just one pin for each different input/output signal to be coupled to or from the chip. Using more than one pin for any given input/output signal would be considered a "waste" of the extra pins used. In the example of the 32-bit multiplier, there would most likely be no extra pins. Hence the importance of the design rule.
The effect of this has been to severely restrict the ability of the circuit designer to optimize the chip layout. Specifically, all circuits which are connected to a given input/output signal, wherever they may be located on the chip, must be connected to the same input/output port on the chip. The input/output port is typically a metal pad located on the periphery of the chip. For example, if a particular voltage must be applied to various circuits throughout the chip, a conductive bus carrying that voltage must extend on the chip for fairly long distances, comparable to the length of the chip. In order to avoid voltage drops along the length of the bus, the width of the bus must be quite large. Otherwise, the voltage applied to various circuits could vary widely, depending upon their location on the chip. Widening the bus necessarily consumes real estate on the chip, thus limiting the space available for different circuit functions on the chip.
One solution to this problem would be to connect both ends of the bus to the voltage source. This would allow the bus width to be decreased by a factor of four without suffering additional voltage drops along the length of the bus. This solution requires that the two ends of the bus be connected to two pads which are nearest the ends of the buse and that the two corresponding external pins be connected to the same voltage source, thus violating the design rule discussed above.
One obvious solution to all of the foregoing is simply to increase the number of external pins on the integrated circuit package. However, this is unacceptable because the greater number of pins would require a reduction in pin-to-pin spacing and an increase in the amount of cross-talk or capacitive coupling between various input/output ports of the chip. Furthermore, at present the commerical availability of such large pin-out circuit packages is limited.
Accordingly, there has existed two apparently irreconcilable goals in the art. The first goal has been to maximize the number of different input/output signals coupled to the integrated circuit chip for a given number of pins on the circuit package, which requires that each pin be used to couple a different input/output signal to the chip. The second goal has been to conserve chip "real estate" to afford the placement of more functions on a given chip. This in turn has required the reduction in dimensions of, for example, the conductive busses carrying signals and supply voltages to or from various portions of the chip. However, such reduction in bus geometry requires the unacceptable duplication of pin-out to permit connection of a signal to both ends of a corresponding bus to minimize voltage drops along the length of the bus. So far, for a given integrated circuit package pin-out and a given chip size, it has not been possible to simultaneously meet both goals without a trade-off.