Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit, and an integrated circuit including the same.
A synchronous semiconductor memory device such as a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) communicates data to external devices by using an internal clock synchronized with an external clock inputted from an external device such as a memory controller (CTRL). The reason for this is that the time synchronization between the external clock applied from a memory controller to a memory and the data outputted from the memory is very important in order to stably transmit data between the memory and the external devices.
However, the internal clock which is applied to the memory in synchronization with the external clock may be asynchronous with the external clock because of a delay resulting from passing through each of the components of the memory. Thus, for stable transmission of the data outputted from the memory, the internal clock and the external clock are to be synchronized with each other by compensating for the load time of the data on a bus so that the internal clock delayed through each of the data transmitting components of the memory is activated accurately at the edge or center of a pulse of the external clock applied from the memory controller.
Examples of such clock synchronization circuits are a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
When the frequency of the external clock and the frequency of the internal clock are different from each other, a phase locked loop (PLL) is mainly used to adjust the frequency. However, when the frequency of the external clock and the frequency of the internal clock are identical to each other, a delay locked loop (DLL) circuit is mainly used because it is less affected by a noise and can be implemented in a smaller area than a phase locked loop (PLL).
FIG. 1 is a block diagram illustrating a conventional delay locked loop (DLL) circuit.
Referring to FIG. 1, the conventional delay locked loop (DLL) circuit includes a phase comparing unit 100R/100F, a timing pulse generating unit 110, a mode control unit 120R/120F, a delay shift control unit 130R/130F, a phase delay unit 140R/140F, a delay replica modeling unit 150R/150F, a pre duty cycle correcting unit 160A, a duty cycle correcting unit 1508, a DLL circuit driver 170, a power-down mode control unit 180A, a clock buffer unit 1808 and a DLL control unit 190.
The phase comparing unit 100R/100F is configured to compare the phase of a source clock REFCLK with the phase of a feedback clock FBCLKR/FBCLKF. The timing pulse generating unit 110 is configured to generate a plurality of timing pulses T_PULSE<0:12> activated sequentially for delay shifting update periods in response to a control clock CONTCLK synchronized with the source clock REFCLK.
The mode control unit 120R/120F is configured to generate mode control signals FM_END, LOCK_STATE, FM_END_F, and LOCK_STATEF corresponding to the comparison results FINE, COARSE, FM_PDOUT, FINEF, COARSEF, and FM_PDOUTF of the phase comparing unit 100R/100F in response to the second timing pulse T_PULSE<2> or the eighth timing pulse T_PULSE<8> among the timing pulses T_PULSE<0:12>.
The delay shift control unit 130R/130F is configured to generate first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FFCLK_SR, SFCLK_SL, and SFCLK_SR for controlling a delay shifting operation in a normal mode and a coarse mode and second delay shift control signals FASTR_SL and FASTF_SL for controlling a delay shifting operation in a fast mode in response to the mode control signals FM_END, LOCK_STATE, FM_END_F and LOCK_STATEF, and the third timing pulse T_PULSE<3>, the sixth timing pulse T_PULSE<6>, the ninth timing pulse T_PULSE<9>, the tenth timing pulse T_PULSE<10>, or the twelfth timing pulse T_PULSE<12> among the timing pulses T_PULSE<0:12>.
The phase delay unit 140R/140F is configured to delay-shift the phase of an internal clock CLKIN1/CLKIN2 synchronized with the source clock REFCLK and the control clock CONTCLK on a delay unit basis in response to the first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FRCLK_SR, SFCLK_SL, and SFCLK_SR in the normal mode, delay-shift the phase of the internal clock CLKIN1/CLKIN2 on a unit basis (the unit is smaller than the delay unit) in response to the first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FFCLK_SR, SFCLK_SL, and SFCLK_SR in the coarse mode, and delay-shift the phase of the internal clock CLKIN1 and CLKIN2 on a delay group basis (the delay group includes a plurality of delay units) in response to the second delay shift control signals FASTR_SL and FASTF_SL in the fast mode.
The delay replica modeling unit 150R/150F is configured to delay output clocks IFBCLKR and IFBCLKF of a duty cycle correcting unit 160B using a delay time corresponding to the actual delay conditions of an internal clock path and output the feedback clocks FBCLKR and FBCLKF.
The clock buffer unit 180B is configured to buffer an external clock CLK and generate the source clock REFCLK, control clock CONTCLK, and internal clocks CLKIN1 and CLKIN2, the phases of which are synchronized. The power-down mode control unit 180A is configured to control an operation of the clock buffer unit 1808 in response to an inversion signal CKEB_COM of a clock enable signal, a signal SAPB with power-down mode information of a mode register set MRS, and a signal RASIDLE with precharge information.
The DLL control unit 190 is configured to generate a reset signal RESET for controlling an operation of the DLL circuit in response to a DLL disable signal DIS_DLL and a DLL reset signal DLL_RESETB inputted from an external device of an integrated circuit.
The pre duty cycle correcting unit 160A is configured to invert the phase of the output clocks MIXOUT_R and MIXOUT_F (mainly MIXOUT_F) of the phase delay unit 140R/140F and output a rising internal clock RISING_CLK with a rising edge corresponding to the rising edge of the internal clocks CLKIN1 and CLKIN2 and a falling internal clock FALLING_CLK with a rising edge corresponding to the falling edge of the internal clocks CLKIN1 and CLKIN2. The duty cycle correcting unit 160B configured to correct the duty cycle ratio of the output clocks RISING_CLK and FALLING_CLK of the pre duty cycle correcting unit 160A in a locking state.
The DLL circuit driver 170 is configured to output DLL output clocks IRCLKDLL and IFCLKDLL, generated by driving the output clocks IFBCLKR and IFBCLKF of the duty cycle correcting unit 160B, to an output driver of the integrated circuit.
FIG. 2 is a block diagram illustrating the timing pulse generating unit of the conventional DLL circuit illustrated in FIG. 1.
For reference, the fact that the last pulse among the timing pulses T_PULSE<0:12> generated by the timing pulse generating unit 110 of the DLL circuit is the twelfth timing pulse means that the delay shifting update period of the DLL circuit illustrated in FIG. 1 is defined by the twelfth time that the external clock CLK toggles. In other words, the duration of the delay shifting update period depends on the time it takes for the external clock to toggle and the number of pulses generated by the timing pulse generating unit 110. For example, where the external clock toggles 12 times in a period of 12 tCK and the timing pulse generating unit 110 generates 12 timing pulses T_PULSE<0:12>, the delay shifting update period is 12 tCK. While here the timing pulse generating unit 110 generates 12 pulses, it should be understood that more or fewer pulses may be generated in which case the delay shifting update period changes.
Referring to FIG. 2, the timing pulse generating unit 110 includes: a timing pulse outputting unit 112 configured to output the timing pulses T_PULSE<1:12> activated/pulsed sequentially in response to the toggling of the control clock CONTCLK synchronized with the source clock REFCLK; and an operation control unit 114 configured to repeat the operation of the timing pulse outputting unit 112.
Here, the timing pulse outputting unit 112 sequentially activates/pulses the timing pulses T_PULSE<1:12> whenever the control clock CONTCLK toggles after the activation/pulsing of the reference timing pulse T_PULSE<0> among the timing pulses T_PULSE<0:12>. Further, the timing pulse outputting unit 112 outputs the timing pulses T_PULSE<0:12> to the operation control unit 114.
The operation control unit 114 activates/pulses the reference timing pulse T_PULSE<0> in response to the deactivation of all the timing pulses T_PULSE<0:12>.
FIG. 3 is a timing diagram illustrating the operations of the conventional timing pulse generating unit illustrated in FIG. 2.
Referring to FIG. 3, the timing pulse generating unit 110 sequentially activates/pulses the other timing pulses T_PULSE<2:12> from the first timing pulse T_PULSE<1>, which is a high active signal, in response to the toggling of the control clock CONTCLK synchronized with the source clock REFCLK after the reference timing pulse T_PULSE<0>, which is a low active signal among the timing pulses T_PULSE<0:12>, is being activated to a logic ‘low’ level. Here, the reference timing pulse T_PULSE<0> is deactivated to a logic ‘high’ level in response to the activation/pulsing of the first timing pulse T_PULSE<1> to a logic ‘high’ level.
The phase comparing unit 100R/100F performs its operation at the time point corresponding to the second timing pulse T_PULSE<2> or the eighth timing pulse T_PULSE<8>, and the mode control unit 120R/120F generates the mode control signals FM_END, LOCK_STATE, FM_END_F, and LOCK_STATEF corresponding to the comparison results FINE, COARSE, FM_PDOUT, FINEF, COARSEF, and FM_PDOUTF. Also, the delay shifting operation is performed in the normal mode and the coarse mode in response to the mode control signals FM_END, LOCK_STATE, FM_END_F, and LOCK_STATEF at the time point corresponding to the third timing pulse T_PULSE<3>, the sixth timing pulse T_PULSE<6>, the ninth timing pulse T_PULSE<9>, the tenth timing pulse T_PULSE<10>, or the twelfth timing pulse T_PULSE<12>.
In this manner, the time points of all the operations of the DLL circuit are defined by the timing pulses T_PULSE<0:12> generated by the timing pulse generating unit 110, which may be predetermined by the designer. For example, as described above, the operation of the phase comparing unit 100R/100F is performed at the time point corresponding to the second timing pulse T_PULSE<2> or the eighth timing pulse T_PULSE<8>, and the delay shifting operation is performed at the time point corresponding to the third timing pulse T_PULSE<3>, the sixth timing pulse T_PULSE<6>, the ninth timing pulse T_PULSE<9>, the tenth timing pulse T_PULSE<10>, or the twelfth timing pulse T_PULSE<12>, which are merely values predetermined by the designer and may vary according to the types of integrated circuits. However, once the DLL operation in the integrated circuit is defined by the timing pulses T_PULSE<0:12>, it is difficult to change its timing.
Thus, as described below, the DLL circuit may malfunction when there is a significant change in the frequency of the source clock REFCLK inputted to the integrated circuit.
FIG. 4 is a timing diagram illustrating the malfunction of the conventional timing pulse generating unit illustrated in FIG. 2.
Referring to FIG. 4, it can be seen that the operations of the timing pulse generating unit 110 are divided into a low frequency operation in which the source clock REFCLK has a relatively low frequency and a high frequency operation in which the source clock REFCLK has a relatively high frequency.
The DLL operation is simplified for convenience in description. That is, it is assumed that the operation of comparing the phase of the source clock FEFCLK with the phase of the feedback clocks FBCLKR and FBCLKF is performed in response to the fourth to sixth timing pulses T_PULSE<4:6> of the timing pulses T_PULSE<0:12>, and that the delay shifting operation, which changes the phase of the feedback clocks FBCLKR and FBCLKF, is performed after the predetermined time tDELAY corresponding to the actual delay of the internal clock path from the phase comparing operation.
Regarding the operation of the timing pulse generating unit 110 in the case of the source clock REFCLK with a relatively low frequency, because the source clock REFCLK has a low frequency, the delay shifting operation may be performed, after the operation of comparing the phase of the source clock FEFCLK with the phase of the feedback clocks FBCLKR and FBCLKF is performed at around the fourth to sixth timing pulses T_PULSE<4:6> of the timing pulses T_PULSE<0:12>, to change the phase of the feedback clocks FBCLKR and FBCLKF before all of the timing pulses T_PULSE<0:12> are activated/pulsed once.
That is, because the source clock REFCLK has a low frequency, the time taken until completion of the delay shifting operation of the DLL circuit is shorter than the time 12 tck taken to pulse/activate all the timing pulses T_PULSE<0:12> once sequentially. Thus, the DLL operation may repeat without any malfunction.
Regarding the operation of the timing pulse generating unit 110 in the case of the source clock REFCLK with a relatively high frequency, because the source clock REFCLK has a high frequency, the phase of the feedback clocks FBCLKR and FBCLKF changes when all the timing pulses T_PULSE<0:12> are sequentially activated/pulsed once and the second pulsing thereof starts, even though the delay shifting operation is performed after the operation of comparing the phase of the source clock FEFCLK with the phase of the feedback clocks FBCLKR and FBCLKF is performed at around the fourth to sixth timing pulses T_PULSE<4:6> of the timing pulses T_PULSE<0:12>.
That is, because the source clock REFCLK has a high frequency, the time taken until completion of the delay shifting operation of the DLL circuit is longer than the time 12 tck taken to activate/pulse all the timing pulses T_PULSE<0:12> once sequentially. Thus, the DLL may malfunction.
The reason for the above malfunction is that the predetermined time tDELAY, corresponding to the actual delay of the internal clock path applied essentially when the feedback clocks FBCLKR and FBCLKF are generated from the source clock REFCLK in the operation of the DLL circuit, is not changed in synchronization with the frequency of the source clock REFCLK.
Thus, when generating the timing pulses T_PULSE<0:12> for controlling the operation of the conventional DLL circuit, the applicable frequency of the source clock REFCLK may be limited. Also, when the applicable frequency bandwidth of the source clock REFCLK is too wide, the time taken to perform the DLL operation of the DLL circuit may increase significantly.