FIG. 1 schematically illustrates a conventional VLSI wafer. The wafer 10 of FIG. 1 comprises a plurality of die regions 20 which are separated by scribe lines 30 and 40. After the fabrication steps of the wafer are completed, the wafer is cut along the scribe lines to separate the individual dies. The individual dies are then mounted and packaged so that they can be used in their intended environments. On the conventional wafer the edges of the wafer are left unpatterned and smooth.
The back-end of the VLSI wafer fabrication process involves the deposition of a plurality of dielectric and/or conducting layers on the wafer surface. For example, the wafer may comprise a plurality of dies each of which is a buried-bit-line ROM. In this case, the back-end processes involve the depositing of passivation layers which are dielectrics such as BPSG (Borophosphosilicate glass) and metalization layers.
A polycide process has been widely used in the fabrication of VLSI circuits to reduce the resistance of local interconnects and improve device performance. The matured polycide structure is a thin LPCVD (Low Pressure Chemical Vapor Deposition) silicide deposited on a polysilicon layer during fabrication of the device. The thin polycide is typically WSi.sub.x, where x is greater than 2 (x &gt;2). Inevitably, an interfacial native oxide is formed between the LPCVD silicide and the underlying polysilicon. The native oxide will degrade the adhesion of the silicide to the polysilicon. The silicide layer of the polycide structure becomes easy to peel off from the polysilicon layer at the edges of the silicon wafer where no dies have been patterned. This silicide peeling significantly decreases the yield of devices during manufacture.
In addition, there exists tremendous stress after the silicide is deposited. The stress increases With each subsequent thermal treatment. The thermal coefficients of expansion for silicide and polysilicon are quite different. It is a major issue to generate thermal stress in the subsequent thermal treatments.
Further, the back-end layers always generate a tremendous stress on the substrate and result in the polycide peeling problem. The polycide peeling makes patterning of the back-end layers difficult and generates many particles which kill the yield. The polycide peeling problem is illustrated in FIGS. 2(a) and (b). At the edge 60 of the wafer 10, the silicide film 50 peels off the polysilicon layer 70 release the thermal stress. The pattern of the conventional wafers does not cover the entire wafer surface 10.
Conventionally, in order to obtain a higher deposition rate and lower resistance, the silicide layer is usually deposited to be of low resistivity, i.e., less silicon rich. In fact, the resistivity of silicide is one tenth (1/10) the resistivity of polysilicon. This is problematic because less silicon rich silicide causes more stress.
It is an object of this invention to provide a silicide on a wafer which does not peel.
It is another object of this invention to provide a device which has low resistivity and high speed.