1. Field of the Invention
The present invention relates to generally to integrated circuits, and, in particular, to an input/output buffer using low voltage semiconductor devices.
2. Description of the Related Art
The fabrication of a semiconductor system on chip (SOC) with three gate oxide thicknesses is known as a triple gate oxide (TGO) process. Gate oxide thicknesses associated with metal-oxide semiconductor field effect transistors (MOSFETs or FETs) on the SOC increase as the operating voltage of the FETs increases. Often, a TGO device might have one thin gate oxide for devices in the lower voltage processor core and two thicker gate oxides for higher voltage input and output (I/O) devices. Using two thicker gate oxide layers inherently lowers the yield of devices from the fabricated silicon wafer and adds complexity to the fabrication process. Alternatively, a TGO device might have two thin gate oxide layers and one thick layer. It is desirable to include only two gate oxide thicknesses—one thin and one thick—but this creates a design trade-off between gate oxide thickness and performance, as lower voltage, thinner gate oxide semiconductors are smaller, consume less power, generate less heat, have lower gate and junction capacitances than higher voltage, thicker gate oxide semiconductors. However, higher operating voltages may be required for I/O devices in order to maintain backward compatibility with other devices.
For example, in a computer disk drive SOC, the designers may choose to use 1.8V I/O devices with a gate oxide thickness of 26 Angstroms. Choosing a thinner gate oxide allows the SOC to support higher performance, lower voltage protocols such as SATA (Serial Advanced Technology Attachment) or DDR3 (Double Data Rate version 3). However, the SOC I/O devices may still be required to interface to higher voltage legacy protocols such as ATA (Advanced Technology Attachment) or CE-ATA (Consumer Electronics Advanced Technology Attachment). Therefore, thinner gate oxide SOC I/O devices might require circuitry to prevent the device from operating in an over-voltage condition that could damage the I/O device.
FIG. 1 shows a schematic diagram of prior art system on chip (SOC) I/O device 100. Input node 102 and input node 122 are configured to receive signals provided from a core of the SOC (not shown). Signals provided to input node 102 may be used to control I/O transistor 112 and signals provided to input node 122 may be used to control I/O transistor 132. Signals received by input nodes 102 and 122 are provided to voltage translator 104 and voltage translator 124, respectively. Voltage translators 104 and 124 are configured to shift the voltage between the low voltage used by the SOC core and the higher voltage, for example Vddio 108, used by I/O device 100. For example, the SOC core might operate at 1.5V, while the SOC I/O might operate at a Vddio of 3.3V, etc. The outputs of voltage translators 104 and 124 are provided to I/O transistor pre-drivers 106 and 126, respectively.
I/O transistor pre-driver 106 and I/O transistor pre-driver 126 are configured to provide adequate biasing to drive I/O transistor 112 and I/O transistor 132, respectively. I/O transistor pre-driver 106 is electrically coupled between voltages Vddio 108 and VPbias 110 and I/O transistor pre-driver 126 is electrically coupled between voltages VNbias 128 and Vss 130. I/O transistor pre-driver 106 provides gate drive signal VPG 111 to I/O transistor 112 and I/O transistor pre-driver 126 provides gate drive signal VNG 131 to I/O transistor 132. Gate drive signals VPG 111 and VNG 131 are configured to drive I/O transistors 112 and 132, respectively.
Voltages VNbias 128 and VPbias 110, which drive the gates of MNIOB 134 and MPIOB 114, respectively, are derived from Vddio 108. Typically, VNbias 128 and VPbias 110 are chosen to be a constant ratio of Vddio 108 such that the DC voltage across any two terminals of I/O transistors 112 and 132 does not exceed the maximum allowable voltage, Vmax, across any two terminals of the transistor. VNbias 128 and VPbias 110 might be, but are not necessarily, substantially equal.
As shown, I/O transistor 112 comprises a P-channel FET and I/O transistor 132 comprises an N-channel FET. Further, over-voltage protection circuit 114 comprises a P-channel FET and over-voltage protection circuit 134 comprises an N-channel FET. Thus, signal VPG 111 is configured to turn I/O transistor 112 on and off, and signal VNG 131 is configured to turn I/O transistor 132 on and off. As used in this specification, and as would be understood by one of skill in the art, the terms “on” and “off” refer to the transistor being in conducting mode or non-conducting mode, respectively. For example, to turn on I/O transistor 132, signal VNG 131 is configured to be greater than or equal to the threshold voltage, Vth, of I/O transistor 132. When I/O transistors 112 and 132 are 1.8V devices with a gate oxide thickness of 26 Angstroms, the threshold voltage, Vth, might be approximately 0.5V.
PAD 140 provides electrical communication with devices outside of I/O device 100, for example, such as devices located on separate silicon dies or separate chips on an external printed circuit board. PAD 140 is configured to be set to a high voltage level (approximately Vddio 108) or a low voltage level (approximately Vss 130). I/O transistor 132 is configured to pull the voltage of PAD 140 down to a low level, approximately Vss 130, when I/O transistor 132 is on and I/O transistor 112 is off. Similarly, I/O transistor 112 is configured to pull the voltage of PAD 140 up to a high level, approximately Vddio 108, when I/O transistor 112 is on and I/O transistor 132 is off.
Generally, I/O transistor 112 may be connected directly between Vddio 108 and PAD 140, and I/O transistor 132 may be connected directly between PAD 140 and Vss 130. However, to protect I/O transistors 112 and 132 from experiencing DC over-voltage conditions, over-voltage protection circuits 114 and 134 are configured to reduce exposure of I/O transistors 112 and 132, respectively, to DC over-voltage conditions.
In operation, when the voltage of PAD 140 is pulled high to approximately Vddio 108, and Vddio 108 is 3.3V, the voltage of PAD 140 may reach as high as 3.6V (e.g., 3.3V+10% worst case tolerance). When the voltage of PAD 140 is pulled high, I/O transistor MNIOA 132 is off. If over-voltage protection transistor MNIOB 134 were not present, I/O transistor MNIOA 132 could be subject to a DC over voltage condition. As would be understood by one of skill in the art, the drain to source voltage, Vds, of MNIOA 132 might be as high as 3.6V. Conversely, when the voltage of PAD 140 is pulled low, I/O transistor MPIOA 112 might have a Vds as high as 3.6V. However, when I/O transistors 112 and 132 are 1.8V devices with a gate oxide thickness of 26 Angstroms, the maximum allowable voltage, Vmax, across any two terminals of the transistor is approximately 1.98V.
Therefore, over-voltage protection transistor MNIOB 134 is intended to limit the DC voltage across any two terminals of I/O transistor MNIOA 132 and over-voltage protection transistor MPIOB 114 is similarly intended to limit the DC voltage across any two terminals of I/O transistor MPIOA 112. As would be apparent to one of skill in the art, an analysis might be performed to show that transistors 112, 114, 132 and 134 are not subject to DC over-voltage conditions regardless of whether the voltage of PAD 140 is pulled high or low.
While transistors 112, 114, 132 and 134 might be protected from DC over-voltage conditions, they might not be protected from transient over-voltage conditions. For example, if PAD 140 is coupled to a capacitive load, such that the rate of charging or discharging PAD 140 is slower than charging or discharging the source of MPIOB 114 or the source of MNIOB 134, transient voltages exceeding Vmax may appear across the nodes of transistors 114 and 134. Depending on the peak and duration of these transient voltages, the lifetime of the transistors may be degraded.