The present invention relates to phase-locked loops, and in particular to the charge pumps used in some phase-locked loops.
1. Field of the Invention
FIG. 1 shows a conventional phase-locked loop, including a charge pump 1. A reference frequency Fref coming from a quartz oscillator is applied to a frequency divider 3. Frequency divider 3 is a divider by R and it provides a signal Fdiv having a frequency equal to Fref/R. Signal Fdiv is provided to a phase comparator 5. Phase comparator 5 also receives a signal Fcomp, the frequency of which corresponds to frequency Fvco of the output signal of the phase-locked loop, divided by a predetermined number N. Phase comparator 5 compares the phases of signals Fdiv and Fcomp. Phase comparator 5 transmits a positive pulse on an output U if signal Fdiv is ahead of signal Fcomp, and a positive pulse on an output D if signal Fcomp is ahead of signal Fdiv. The signals coming from outputs U and D of the phase comparator are provided to charge pump 1. Charge pump 1 drives a loop filter 7.
2. Discussion of the Related Art
Charge pump 1 includes a first current source 6A providing a current I1. Current source 6A is coupled to output OUT of the charge pump via a switch Sa. Switch Sa is controlled by signal U provided by the phase comparator. When signal U is high, switch Sa is on and current I1 is provided by the charge pump to loop filter 7. The charge pump includes a second current source 6B run through by a current I2. Current source 6B is coupled to the charge pump output via a switch Sb. Switch Sb is controlled by signal D provided by phase comparator 5. When signal D is high, switch Sb is on and current I2 is absorbed by the charge pump from loop filter 7.
Loop filter 7 outputs a control voltage Uc. Voltage Uc controls a voltage-controlled oscillator 9. Oscillator 9 provides a signal of frequency Fvco, at the output of the phase-locked loop. The output of oscillator 9 drives a frequency divider 11. Frequency divider 11 divides frequency Fvco by N and provides signal Fcomp to phase comparator 5.
The operation of the phase-locked loop is the following.
To simplify, loop filter 7 will be considered to be only formed of a capacitor Cf connected between the charge pump output and the ground, control voltage Uc being the voltage across capacitor Cf. If the rising edge of signal Fdiv occurs before the rising edge of signal Fcomp, output U of the phase comparator switches high. Switch Sa then turns on and current I1 charges capacitor Cf of loop filter 7. The charge of capacitor Cf occurs during the on time xcex94t of switch Sa. In principle, duration xcex94t is equal to the time interval separating the rising edges of signals Fdiv and Fcomp. The charge stored by capacitor Cf thus increases by I1.xcex94t, and control voltage Uc increases. Accordingly, voltage-controlled oscillator 9 provides a signal of higher frequency Fvco and the interval between the phases of signals Fdiv and Fcomp decreases. At equilibrium, signals Fdiv and Fcomp have a same phase. The frequency provided by voltage-controlled oscillator 9 then is at the desired value Fvco=Fref.(N/R). Strictly speaking, the phases of signal Fdiv and Fcomp are equal, plus the static phase deviation (it should be reminded that the static interval is the phase deviation exhibited by the phase-locked loop when said loop is stabilized, this phase deviation generally causing no charge variation in loop filter 7). It is here assumed that the static phase deviation is sufficiently low to be neglected.
Conversely, if the frequency provided by oscillator 9 is too high, the rising edge of signal Fcomp occurs before the rising edge of signal Fdiv. A positive pulse on terminal D then turns switch Sb on for a time xcex94xe2x80x2t, in principle equal to the time interval between the occurrence of the rising edges of signals Fcomp and Fdiv. Current I2 discharges capacitor Cf, its amount of charge decreasing by I2.xcex94xe2x80x2t. Voltage Uc decreases and the output frequency of oscillator 9 decreases. At equilibrium, the phase-locked loop is stabilized and the phases of signals Fdiv and Fcomp are the same.
The previously-described operation is defective in the case where the pulses on terminals U or D are very short. Indeed, the time necessary to operate switches Sa or Sb may appear to be greater than the duration of the pulse generated by the phase comparator. In this case, switches Sa or Sb do not have time to turn on and do not fulfil their function. A solution to this problem consists of turning on controlled switch Sa or Sb for a longer time, and of turning on, at the same time, the other switch, as illustrated in the diagrams of FIGS. 2a to 2e. 
FIGS. 2a to 2e illustrate the case where frequency Fvco is smaller than what is desired. In this case, the rising edge of signal Fdiv (FIG. 2a) occurs at a time t1 prior to time t2 at which occurs the rising edge of signal Fcomp (FIG. 2b). Signal U switches high at time t1, but, as can be seen on the timing diagram illustrating signal U (FIG. 2c), signal U remains high after time t2, and this until a time t3. During time t3xe2x88x92t2, signal D (FIG. 2d) also switches high, which turns on switch Sb. In duration t3xe2x88x92t2, loop filter 7 is run through by a current I1xe2x88x92I2 (FIG. 2e) and capacitor Cf receives a small amount of electric charge equal to (I1xe2x88x92I2)xc3x97(t3xe2x88x92t2). Difference I1xe2x88x92I2, which is positive or negative, is a residual intensity resulting from technological disparities having an effect on current sources 6A and 6B. Duration t3xe2x88x92t2 is selected to be sufficient for each of switches Sa and Sb to have time to turn on during this time. Thus, even when duration t2xe2x88x92t1 is very short, switches Sa or Sb have in all cases time to turn on and the charge pump can satisfactorily inject (respectively sample) current I1 (respectively I2).
At equilibrium, as shown in FIGS. 2a to 2e after time txe2x80x20, signals Fdiv and Fcomp are in phase. Their rising edges both appear at time txe2x80x21. Signals U and D both switch high at time txe2x80x21 and remain high until time txe2x80x23. Duration txe2x80x23xe2x88x92txe2x80x21 is equal to duration t3xe2x88x92t2. As can be seen in FIG. 2e, at equilibrium, output current Iout of the charge pump is equal to difference I1xe2x88x92I2. This difference causes a misadjustment of the frequency of oscillator 9 that the loop will attempt to compensate by generating a static phase shift, which results, in the power spectrum of the output signal of the phase-locked loop, in a undesirable noise in the form of lines.
Further, the phase-locked loop exhibits a passband, determined by loop filter 7. In this passband, the charge pump noise dominates, and it is desirable to decrease it.
Further, charge pumps of prior art have a heavy consumption and take up a relatively large space.
An object of the present invention is to provide a charge pump for a phase-locked loop such that the noise due to the pump is very attenuated.
Another object of the present invention is to provide a charge pump in which errors due to technological dispersions are avoided.
Another object of the present invention is to provide a charge pump enabling use of smaller components and enabling better integration.
Another object of the present invention is to provide a low-consumption charge pump.
To achieve these and other objects, the present invention provides a charge pump for a phase-locked loop including a first current source, a second current source, several switches adapted to enabling communication of the first and/or the second current source with the charge pump output. The second current source is controlled by a control means adapted to storing a variable corresponding to the value of the current provided by the first current source, so that the value of the current provided by the second current source is substantially equal to the value of the current provided by the first current source, the control means comprising a first branch comprising a first storing means and a second branch comprising a second storing means.
According to an embodiment of the present invention, the control means stores said variable little before enabling communication of the first and/or of the second current source with the charge pump output.
According to an embodiment of the present invention, the first current source is connected between a first supply voltage and a first node, and the switches include:
a first switch connected between the first node and the charge pump output, controlled by a first control signal,
a second switch connected between the first node and a second node, controlled by the inverse of the first control signal,
a third switch connected between the output of the charge pump and a third node, controlled by a second control signal,
a fourth switch connected between the second node and the third node, controlled by the inverse of the second control signal; and the second current source is connected between the third node and a second supply voltage.
According to an embodiment of the present invention, the first branch includes a first capacitor coupled to the second node.
According to an embodiment of the present invention, the second branch includes a fifth switch connected between the second node and the output of the control means.
According to an embodiment of the present invention, the second branch includes a second capacitor coupled to the second node via the fifth switch.
According to an embodiment of the present invention, the second current source is formed by a first MOS-type transistor of a first conductivity type.
According to an embodiment of the present invention, the first current source is formed by a second transistor, of a second conductivity type, and belongs to a current mirror, the current running through the first current source being equal to xcex1 times the value of a reference current of the current mirror, with xcex1 greater than one.
According to an embodiment of the present invention, the first switch is formed of a third transistor of the second conductivity type, the second switch is formed of a fourth transistor of the second conductivity type, the third transistor is formed of a fifth transistor of the first conductivity type, and the fourth transistor is formed of a sixth transistor of the first conductivity type.
According to an embodiment of the present invention, the first supply voltage is a positive voltage, the second supply voltage is the ground voltage, and the transistors of the first conductivity type are N-channel MOS transistors and the transistors of the second conductivity type are P-channel MOS transistors.
The foregoing and other objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, in which: