Sensing data in two-terminal memory cells that store data as a plurality of conductivity profiles can often require significant circuitry resources and die area to accurately sense read currents that are indicative of the stored data. One skilled in the art will appreciated that in large cross-point memory arrays, during the reading of one or more selected memory cells, other memory cells are either un-selected or half-selected. As a result, there can be leakage currents flowing in the half-selected and/or un-selected memory cells. The total current flowing in the array during the read operations is approximately the sum of all the leakage currents plus the read current(s) from selected memory cell(s).
Consequently, sense circuitry configured to sense a signal representing the read current must also be able to distinguish between the noise created by the leakage currents and the read current signal. Ideally, the signal-to-noise ratio S/N between the leakage currents and the read current should be as high as possible so that the sense circuitry can easily distinguish between the signal representing the read current and the signal(s) representing the noise (i.e., the leakage currents). The higher the S/N, the more accurate the data output from the sense circuitry during read operations to the array. Accurately sensing read currents can be exacerbated when each memory cell stores more than one bit of data (e.g., multi-level cell—MLC) because the sense amp circuitry must be able to accurately distinguish between the read current magnitudes for the stored data in a background of noise created by the aforementioned leakage currents. Accordingly, multi-level sensing (MLS) is required to accurately differentiate read currents that represent stored data (e.g., “00”, “01”, “10” “11”).
Turning now to FIG. 1A, a conventional configuration 150 depicts a schematic view of a cross-point array including a plurality of row array lines 110, a plurality of column array lines 112, and a plurality of two-terminal memory cells 100 positioned at an intersection of one of the row lines 110 with one of the column lines 112. Each memory cell 100 includes a first terminal 103 electrically coupled with only one row line 110 and a second terminal 105 electrically coupled with only one column line 112. Here, address decoding circuitry (not shown) generates signals that accesses the memory cell(s) 100 for data operations (e.g., read and write operations). Those signals are operative to electrically couple a read voltage source 130 and an un-select voltage source 140 with row array lines 110 via switches R0-R3. Switches R0-R3 select voltages sources 130 and 140 based on the state of their respective control signals ra-rd. A decoded address can determine which of the controls signals ra-rd goes active and which remain inactive.
Control signal ra for switch R0 goes active (e.g., logic “1”) and switch R0 selects read voltage source 130 and applies a read voltage potential to the row 0 array line 110 causing array line 110 to become a selected array line 110′ as depicted by heavy line. Memory cells 100 on the row 0 array line 110′ become selected memory cells 100′ and have a read voltage potential VRead (e.g., 1.5V) applied to their respective terminals 103. Control signals rb-rd are inactive (e.g., logic “0”) and their respective switches R1-R3 select the un-select voltage source 140 and apply an un-select voltage potential VUN-SELECT (e.g., 0V) to the row 1-3 array lines 110 such that the un-select voltage VUN-SELECT is applied to the terminals 105 of the memory cells 100 in those rows.
Switches C0-C3 for column array lines 112 select between a pre-charge voltage source 160 and a floating potential 180 based on a state of their respective control signals ca-cd. Pre-charge voltage source 160 is selected by the switches C0-C3 when control signals ca-cd are inactive (e.g., logic “0”) and the column array lines 112 are pre-charge to a pre-charge voltage VPre-Charge (e.g., 0V).
Turning now to FIG. 1B, after the read voltage VRead is established on the selected row array line 110′, the control signals ca-cd go active (e.g., logic “1”) and switches C0-C3 select floating potential 180 and the column array lines 112 are allowed to float to a voltage potential VFloat. The selected memory cells 100′ have a potential difference across their terminals (103, 105) due to the read voltage potential VRead on the terminals 103 and the voltage potential VFloat on the terminals 105. Consequently, a read current IRead whose magnitude depends on the resistive state of data stored in the selected memory cell 100′ and the potential difference across the terminals (103, 105) flows through each selected memory cell 100′ and charges up the floating column array lines 112 to a voltage that depends on a RC time constant created by the resistance and capacitance of each of the column array lines 112. For example, given an applied voltage of 1.5V across the terminals (103, 105), if a programmed state is a high resistance (e.g., a logic “0”), and an erased state is a low resistance (e.g., a logic “1”), then a magnitude of the read current IRead is low for the programmed state and is higher for the erased state.
Circuitry 0-3 is electrically coupled with the column lines 112 and output signals s1-s3 that are indicative of the magnitude of the currents flowing through the array lines 112. Circuitry 0-3 can include a current mirror, a current-to-voltage (I/V) converter, a voltage-to-current (V/I) converter, for example, that outputs the signals s1-s3 which are electrically coupled with sense amp circuitry and compared with a reference signal such as a reference current, reference voltage, or the like. The sense amps generate output signals that are indicative of the data stored in the memory cells 100′ in selected row line 110′. The conventional configuration 150 depicts a page mode operation in which several memory cells 100′ on the same row line 110′ are read at the same time and the read current signals from each memory cell 100′ is sensed by sense amp circuitry 0-3 that is electrically coupled with each cells 100′ respective column line 112. Although only 4 memory cells 100 are depicted in each row 110 and column 112, one skilled in the art will appreciate that there can be several hundred to several thousand, or more memory cells 100 in each row 110 and column 112. For example, a page can be a row 110 with 1024 memory cells 100 (e.g., 1K bits: column 0-column 1023) or a row 110 with 32K memory cells 100 for a 32K bits. Regardless of the number of memory cells 100 being read in page mode, it is desirable to simultaneously sense all the memory cells 100 being read in order to obtain a faster read rate so that read data is output to a data bus or the like with the lowest latency possible.
The charging voltage on the column array lines 112 as a function of time for the conventional configuration 150 is depicted in FIG. 2A. Here, a programmed col-line 121 and an erased col-line 123 depict charging characteristics for column lines 112 that are electrically coupled with a terminal 105 of a selected memory cell 100′ that stores data in the programmed state (i.e., 121) or the erased state (i.e., 123), respectively. Although a read operation can access a single bit of data (e.g., only one selected memory cell 100′), a typical read operation will access a larger set of data, such a as a page of data (e.g., 32 k bits). In some applications, multiple pages of data will be read at the same time or at substantially the same time. The multiple pages can be within the same array or distributed among a plurality of arrays. In FIG. 2A, a graph 220 depicts a time window for sensing a page of data is between about 25 μs and about 100 μs. Accurately sensing the page data within the time window requires sense amp circuitry that can sense a difference in voltage between the programmed col-line 121 and the erased col-line 123 versus a reference voltage on a reference column-line (not shown). In the time window depicted, the voltage on the erased col-line 123 has a greater rise in amplitude when compared to the programmed col-line 121. At the 100 μs time point, a voltage difference ΔV between the erased col-line 123 and the programmed col-line 121 is approximately 25 mV. The rate of change in the erased col-line 123 voltage (e.g., the increase in 123 from 25 μs to 100 μs) during the time window makes it difficult to properly bias the sense amp circuitry. Moreover, in some applications each memory cell 100 is configured to store more than one bit of data (e.g., multi-level cell “MLC”). Multiple levels of data (e.g., “00”, “01”, “10”, and “11”) stored in each cell 100 requires sense amp circuitry that can implement multi-level sensing (MLS). Preferably, variations in voltage within the sensing time window for multiple states should be as low as possible so the sense amp circuitry can be biased to accurately distinguish differences between multiple states.
In FIG. 2B, a graph 260 depicts read current magnitudes over time for states “00”, “01”, “10”, and “11”; whereas, a graph 240 depicts a voltage margin of 25 mV between states “00” and “01” during a MLS read operation. As can be seen in the upper portion of graph 240, there is overlap in the voltage over time curves for the states “00” and “01” with the curves for state “00” intersecting the curves for state “01”. Those overlapping voltages make it difficult to properly bias sense amp circuitry and can lead to errors in MLS.
There are continuing efforts to improve signal sensing technology for non-volatile memory devices.
Although the previous drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale.