Buffer circuits (e.g., input/output (I/O) buffers) are widely used to facilitate the transfer of data from one component to another within a system. For example, a microprocessor may use a buffer (driver) to transmit data to and receive data from other components (such as a memory or chipset) via buses.
The performance of a bus buffer is typically characterized by the amount of delay between the time a clock signal is applied to an input of the buffer and the time valid data is provided at an output of the buffer. This delay time is referred to as time from clock to output, or TCO. Generally speaking, if TCO is too long, the system operating frequency may be reduced to allow time for the output to arrive at a receiving end of the bus. On the other hand, if the delay is too short, the output may arrive too quickly. TCO variations, therefore, must be controlled to remain between two limits, i.e., within a TCO window.
The size of the TCO window may be limited by the presence of noise, and especially inter-symbol interference (ISI). As the front-side buses of many microprocessor systems are pushed to faster speeds, timing margins for the bus are reduced. The ISI build-up that results can cause duty cycle mismatches on external signals that vary with different data bit patterns. The resulting mismatches limit the TCO window and thus substantially degrade system performance.