Integrated circuits such as microprocessors, digital signal processors, memory devices, application-specific integrated circuits (ASICs) and the like typically have one or more buses for carrying data, address and/or control information. Driver circuitry is used to drive the information off-chip on the buses. The driver circuitry is typically inverter-type, i.e., when a bit is a logic one, there is no current path, and when a bit is a logic zero, there is a current path through the transmission medium. As such, current consumed by the driver circuitry varies over time as a function of bus voltage level, causing interference.
Data Bus Inversion for DC (DBIdc) is one conventional approach for reducing static or quiescent current draw by data bus driver circuitry. DBIdc involves counting the number of ones and zeros in a data word. If the number of zeros exceeds a predetermined count value, the data word is inverted and a flag is set to indicate the data word has been inverted. Otherwise, the data word is not inverted and the flag is not set. This way, fewer logic zeroes are transmitted and power consumption is correspondingly reduced. The entity that receives the data word interrogates the flag to determine whether the data word has been inverted. The receiver inverts each bit of the data word if the flag is set, else the word is taken as-is.
However, not all DBIdc schemes are the same. Take, for example, memory devices. Different DBIdc schemes are specified across various memory standards. For example, the GDDR4 (Graphics Double Data Rate, version 4) graphics memory standard employs a DBIdc scheme having a predetermined count value of four in a byte-wise DBIdc scheme (i.e., data words are 8 bits in length). A DBIdc flag is set to a logic high state when the number of zeros in a data word exceeds four, indicating bus inversion has occurred. According to the LPDDR2 (Low Power DDR2) DBIdc scheme, the predetermined count value is three and the flag is also set to a logic high state for indicating data bus inversion. The GDDR5 (Graphics Double Data Rate, version 5) DBIdc scheme uses a count value of four as in GDDR4, but the flag is set to a logic low state for indicating data bus inversion. Memory devices are conventionally designed to accommodate the DBIdc scheme associated with a singular application, e.g., GDDR4, GDDR5, LPDDR2, etc. This limits memory device use to a particular application or requires re-design or other alteration each time the device is used in a different application.