As integrated circuit geometries shrink, those concerned with the design of such circuits are forced to use increasingly thinner gate dielectrics. For example, it is anticipated, that 0.25 micron (and below) MOSFET technologies will require a gate dielectric with a thickness of 4 nanometers or less. Such thin dielectrics exhibit comparatively high defect densities, lower breakdown and wearout behavior. Furthermore, such thin dielectrics do not present an adequate barrier to boron penetration from overlying boron doped polysilicon into the substrate. In addition, MOSFETs fabricated with such thin dielectrics frequently exhibit high leakage current at low voltage and lower interface resistance to current stress.
Those concerned with the development of integrated circuit technology have consistently sought better dielectrics and methods for their fabrication.