The explosion of the wireless communication in the area of cellular telephony and wireless local area networks (LANs) has led to several wireless standards operating at frequencies ranging from 900 to 5,200 MHz. New generation mobile terminals are equipped to support data transmission via UMTS and GSM/GPRS frequency bands. For this reason, multi-band frequency synthesizers are required which support both UMTS Frequency-Division Duplex (FDD) and UMTS Time-Division Duplex (TDD) frequency bands as well as triple-band functionality (GSM/GPRS 900 MHz, DCS 1,800 MHz, PCS 1,900 MHz) for GSM/GPRS in both uplink (Tx) and downlink (Rx) directions. DCS hereby stands for Digital Cellular System and PCS for Personal Communications Service. Multi-standard transceivers used for these wireless communication systems should be able to operate over a wide frequency range with minimal amounts of replicated hardware components.
A critical element of any wireless transceiver is the integrated frequency synthesizing unit (FSU). A multi-band frequency synthesizer must be able to synthesize a wide range of frequencies for several wireless standards while simultaneously satisfying strict phase noise specifications. This poses a challenging design problem. Typical phase-locked loop (PLL) frequency synthesizers used in wireless transceivers, which reduce the noise power level in the output spectrum of a synthesized carrier signal, are normally designed and optimized for narrowband operation. When such a PLL frequency synthesizer is applied in a multi-mode transceiver, architectural changes have to be made to the typical loop structure in order to achieve operation over a wide frequency range.
A PLL circuit synchronizes an output signal with an input reference signal generated by a reference frequency source, e.g. a crystal oscillator, by executing a feedback mechanism where the output frequency of a voltage-controlled oscillator (VCO) is locked to the reference frequency. Thereby, an error signal is produced which is proportional to the phase difference of the reference signal and the output signal. The error signal is then filtered in order to generate the VCO's control voltage. The loop is set up in a negative feedback fashion such that the control voltage fed to the input port of the VCO will force the oscillator's output to lock with the input reference signal within certain frequency limits. The rapid advance in integrated circuit technology has led to the use of PLL circuitries in many areas such as wireless communication systems, consumer electronics, and motor control.
FIG. 1 illustrates the principles of a conventional PLL frequency synthesizer subunit 100′. The signals generated at an output port 100b of the subunit constitute either directly a frequency of a respective frequency band or an auxiliary frequency for further processing. The input port 100a of the subunit is supplied with a reference frequency signal fr generated by a crystal oscillator. In a first stage, the reference frequency fr is scaled down to
                                          f            D                    ⁢                      :                          =                                            f              r                        R                    ⁢                      (                                          with                ⁢                                                                  ⁢                R                            ∈              ℕ                        )                                              (        1        )            by a division coefficient R, which is set at a control port of a programmable frequency divider 101 by means of a digital control code (CC). The following phase-locked loop frequency synthesizer subunit 100′ then adjusts the output frequency fo of a VCO 106 to the desired value. The PLL frequency synthesizer subunit 100′ thereby works in principle like a frequency multiplier with a fixed frequency raster for a certain number of channels, wherein the channel spacing is given by fD. This is achieved by using a programmable integer frequency divider 108 in the feedback line of the PLL frequency synthesizer subunit 100′ that scales down the output frequency of the VCO 106 by the integer division coefficient N. Furthermore, the PLL frequency synthesizer subunit 100′ comprises a phase/frequency detector 102 (PFD) which provides an output voltage uo(t) proportional to the phase angle deviation between the input frequency fD and the down-scaled output frequency
                                          f            1                    ⁢                      :                          =                                            f              o                        N                    ⁢                                    (                                                with                  ⁢                                                                          ⁢                  N                                ∈                ℕ                            )                        .                                              (        2        )            
This output voltage u0(t) is filtered by a low-pass filter 104 (LPF) before being supplied to the VCO 106. The filter characteristics of this low-pass filter 104 are wide enough to allow a quick lock time and thus a fast switching of the output frequency when changing between different frequency bands and narrow enough to block off high frequencies which otherwise would cause phase noise in the output spectrum of the VCO 106. The output frequency fo of the VCO 106 is a function of the value of the filtered output voltage uc(t) which is supplied to it. In the feedback line of the PLL frequency synthesizer subunit 100′, this output frequency fo is scaled down by an appropriate integer value N to a value equal to that of fD for being applied to the PFD 102. There, it is compared with the original frequency signal fD to produce the control voltage u0(t) for the VCO 106. After termination of the transient processes, the value of the output frequency fo is controlled by the digital code (CC2) of the integer division coefficient N set at the programmable frequency divider 108 of the feedback loop according to the following equation:
                              f          o                =                              N            ·                          f              D                                =                                    N              R                        ⁢                                                            f                  r                                ⁡                                  (                                                            with                      ⁢                                                                                          ⁢                      N                                        ,                                          R                      ∈                      ℕ                                                        )                                            .                                                          (        3        )            
According to equation (3), the output frequency fo is an integer multiple of the input frequency fD or, in other words, fD defines a frequency raster for fo. A change in the output frequency fo can thus be achieved by changing this division coefficient N, a process sufficiently fast to allow fast frequency hopping (FH). As neither spurious harmonics nor additional phase noise are produced by this procedure, no extra filters for a postprocessing of the output spectra of the PLL frequency synthesizer subunit 100′ are required.
With the increased interest in multi-mode RF transceiver systems, frequency synthesizers which operate over a multiplicity of frequency bands become a necessity. There are many challenges faced in designing a multi-band CMOS frequency synthesizer. Recent efforts are concentrated on narrowband single-mode frequency synthesizers which do not have the frequency range necessary for multi-band systems. Conventional prior-art solutions apply a double-loop architecture to obtain a wide frequency range. However, this double-loop architecture requires effectively twice the chip area as a standard single-loop PLL circuitry. Typical dual-band synthesizers utilize a multiplicity of phase-locked loops with narrowband voltage-controlled oscillators that operate at different center frequencies.
A multi-band frequency synthesizer should be realized in a manner that does not increase the loop complexity significantly. An optimal design would be implemented in a typical CMOS process using the power supplies typically found in multiple products. An approach that minimizes the amount of replicated circuitry is to increase the tuning range of the VCO in such a way that the PLL loop dynamics are not drastically affected.
Integrated voltage-controlled oscillators used in PLL-based frequency synthesizers generally have limited tuning ranges or conversion gains. The most common integrated VCO used in RF systems is the LC oscillator due to its superior phase noise performance. However, this oscillator suffers from a very limited tuning range because it is tuned with varactor capacitors that generally make up only 25% of the total capacitance. One way to increase the tuning range of the VCO is to discretely switch in different capacitive or inductive loads. The use of switched tuning elements to increase the oscillator's tuning range is an old design technique that has been deployed in recent research. When the concept of switched tuning is applied, a wide frequency range is realized by splitting the entire range into different bands of operation. The oscillator changes between these bands by discretely switching in different loads, which also aid in reducing the noise power level of the VCO.
The conversion gain of the VCO must be very large to synthesize a wide range of frequencies. However, as such a large conversion gain is not available with conventional integrated VCOs, their output spectra are severely distorted by phase noise. This makes phase-locked loops with switched tuning voltage-controlled oscillators ideal for a multi-band frequency synthesizer because they can tune over a wide range while simultaneously maintaining a comparatively low conversion gain.
Nowadays, implementations of multi-band frequency synthesizers are based on the usage of independent frequency synthesizers for UMTS applications, one for the uplink, one for the downlink, and a third one for triple-band GSM/GPRS. To achieve the necessary class 12 settling time for GPRS (TS<150 μs), fractional-N frequency synthesizers are commonly used. The greatest advantage of said fractional-N frequency synthesizers is their fast settling time when e.g. switching from an uplink to a downlink frequency band or at an intersystem handover, which fulfills one of the preconditions for a reliable GPRS data transmission. The main drawback of all classes of fractional-N frequency synthesizers is their bad output spectrum performance which is characterized by high phase noise and a high amount of spurious harmonics. Especially when receiving low-level signals, this can be very problematic. When using fractional-N frequency synthesizers, the requirements of the GSM standard 0505 can only be achieved by postprocessing the output spectra with high-quality filters, which are bulky and cost-intensive.
From the prior European patent application EP 01 129 616.7 of the same applicant a frequency synthesizer arrangement for generating signals with carrier frequencies for UMTS and GSM/GPRS frequency bands and a mobile terminal with a respective frequency synthesizer arrangement are known. Said frequency synthesizer arrangement comprises a reference frequency source providing a signal of constant reference frequency, a first frequency synthesizer subunit for converting the signal of the reference frequency source into a signal having a frequency in the range of a first frequency band, and a second frequency synthesizer subunit for transforming the signal of the reference frequency source into a signal having a frequency in the range of a second frequency band. The second frequency synthesizer subunit further converts the signal of the reference frequency source into a signal with an intermediate frequency, and a third frequency synthesizer subunit converts the signal of the reference frequency source into an auxiliary signal with a fixed frequency, which is used together with the intermediate frequency signal for generating signals with frequencies in a range of a third and of a fourth frequency band.
The invention described in the European patent application EP 1 170 874 A1 pertains to a wireless RF reception device comprising a reception (Rx) chain with a down-conversion mixer (M1) followed by an analog-to-digital converter (ADC). An oscillator circuit serving as a reference generator (RG) generates a clock signal (RT) which is respectively fed to the analog-to-digital converter (ADC) and PLL frequency synthesizer (PLL1), which are connected to said down-conversion mixer (M1) by a multiplication (MP1) or a division (TL1) stage where the clock rate is multiplied or divided by an integer coefficient, respectively. Hereby, a particularly energy- and chip-area-saving circuitry with negligible mutual signal distortions can be realized, which is especially appropriate for wireless communication systems based on the UMTS standard. According to the preferred embodiment of this invention, said RF reception unit is developed further to an RF transceiver by providing an additional transmission (Tx) chain. The disclosed transceiver architecture can not be applied to multi-mode operation, however, because it does not comprise any multi-band frequency synthesizing unit.
Next, the invention described in the U.S. Pat. No. 5,408,201 refers to a PLL-based frequency synthesizing circuitry with a reduced power consumption which comprises three PLL subfrequency synthesizers for generating two different output frequencies by using a reference frequency provided by a reference signal source. Said frequency synthesizer can advantageously be used for a digital radio transmitter and receiver such as a radio telephone apparatus using a multiplicity of communication channels of different carrier frequencies or in a TDMA system in which channels need to be switched at high speed. Thereby, said first synthesizer generates a first subfrequency varying in units of a first frequency increment, said second synthesizer generates a second subfrequency varying in units of a second frequency increment being N times the first frequency increment, and said third synthesizer generates a third subfrequency varying in units of the first frequency increment. A first output signal is obtained by mixing the first subfrequency and the second subfrequency, and a second output signal is obtained by mixing the second subfrequency and the third subfrequency.
In the European patent application EP 1 148 654 A1 a wireless RF transmission and reception device is disclosed which enables operation modes based on frequency-division duplex (FDD) and time-division duplex (TDD) and can advantageously be used in a wireless communication system based on the UMTS standard. The proposed unit can also be operated in the GSM/GPRS 900 MHz and the GSM/GPRS (DCS) 1800 MHz frequency band but not 7 in the GSM/GPRS (PCS) 1900 MHz frequency band. In the RF reception chain a received modulated RF signal is firs down-converted to a first intermediate frequency between 0 and 0.5 MHz of a first intermediate frequency stage before it is further down-converted to the baseband, and in the transmission chain a baseband signal to be transmitted is first up-converted to a second intermediate frequency of 190 MHz of a second intermediate frequency stage before it is then further up-converted to the passband. The device needs three local oscillators to produce the carrier signals needed for the signal up- and down-conversion in the transmit (Tx) and receive (Rx) chain, respectively. In case of limited-bandwidth operation, the disclosed transceiver architecture requires only two local oscillators—a first oscillator connected to the up-conversion mixer of the RF transmission chain and a second one connected to the down-conversion mixer of the RF reception chain—and can thus be operated in an energy-saving mode. Thereby, said second intermediate frequency can be tuned by ±5 or ±10 MHz, respectively. In this connection, it should be noted that the applied frequency combining means are not used to achieve a better performance of the frequency synthesizer.
Besides, the invention described in the European patent application EP 0 964 523 A1 pertains to a wireless RF transceiver system including two single-loop PPL frequency synthesizers, that do not use any frequency combining means to achieve a better performance, as well as one modulation loop to respectively transmit and receive signals in the GSM/GPRS 900 MHz and GSM/GPRS (DCS) 1,800 MHz frequency bands. The invention thereby does not employ any frequency synthesizers for generating carrier frequencies to be used in the UMTS frequency bands. To bring about frequency hops, the frequencies in the aforementioned two loops are varied with large increments in opposite directions. It is shown that the obtained noise power level caused by the frequency division in said loops is thereby significantly reduced.