A number of applications, including certain clock and data recovery (CDR) architectures, require a set of evenly spaced clock waveforms to sample a received data waveform. In these applications, this set of clock waveforms is typically generated by using a voltage-controlled delay line (VCDL). A voltage-controlled delay line 110, as shown in FIG. 1, is an electrical circuit that is comprised of a plurality of sequentially arranged time delay elements, which is often known as a delay chain, driven by a reference clock signal. Thus, an N-cell VCDL generates N output clocks, where each successive output clock is delayed from the input clock by an additional unit delay. The time delays of each of the individual elements that comprise the chain are substantially equal, and are controlled by an analog voltage or current.
It is typically desired that the total delay through the chain of N delay cells be equal to the period, T, of the input reference clock signal, often referred to as the injection clock, INJ. As shown in FIG. 2B, this implies that the time delay between the rising edges (and the delay between the falling edges) of adjacent output clocks is equal to T/N, and also that the rising (and falling) edges of the output of the Nth delay cell, often referred to as the return clock, RET, are aligned to the rising (and falling) edges of the injection clock, INJ. In addition, if the duty cycle of CLKIN is exactly 50%, for any two output clocks that are separated by exactly N/2 cells in the chain, the rising (falling) edge of the earlier clock is aligned to the falling (rising) edge of the later clock.
The time delay through an electrical delay cell varies significantly due to variations in the manufacturing process (P) and with the power supply voltage (V) and operating temperature (T), often collectively referred to as PVT variations. Thus, most applications of VCDLs require a continuous feedback loop, known as a delay-locked loop (DLL), that senses the alignment between the edges of relevant clocks and varies the control voltage to increase or decrease the delay of each stage in the chain, as appropriate, to hold the total VCDL delay equal to T. Typically, a phase detector in the DLL senses the alignment of the edges of certain VCDL clocks. For example, the phase detector may sense the alignment between the rising edge of the injection clock and the rising edge of the output of the final delay cell in the chain (i.e., the return clock).
Duty cycle distortion is a source of impairment in a received signal. The duty cycle of a phase locked loop (PLL) is the percentage of time that the output clock signal has a given value. A PLL should typically demonstrate a 50% duty cycle, such that the output clock signal should alternate between two amplitude values, each for 50% of the total duration. Duty cycle distortion (DCD) arises due to device mismatches and due to variations of the differential signal paths for clock and data. The target 50% duty cycle feature is particularly important for high-speed applications where both positive and negative edges ate used. In addition, each delay element in a VCDL chain acts as a low pass filter. Thus, the corresponding frequency-dependent attenuation will cause the DCD to get progressively worse with each delay element, often referred to as DCD build up.
A need exists for an improved control mechanism for starting up a VCDL with a wide capture range. A further need exists for a VCDL edge alignment process that is substantially immune from PVT variability.