Dynamic random access memory devices (DRAMs) have continued to be a preferred method for the storage of data in electronic systems. DRAMs, due to their small memory cell size, can store large amounts of data in a very small device. In addition, DRAM memory cells typically consume less power than other memory cell types (such as static RAM cells) making DRAMs a preferred choice in terms of power consumption. At the same time, with the advent of low power electronic devices, such as portable computers and the like, the need to reduce power consumption continues to be an important goal for designers of DRAMs.
DRAMs enjoy relatively low power consumption due to the "dynamic" manner by which they retain data. In most DRAMs, each memory cell includes a storage capacitor that can be charged or discharged. The state of the capacitor (i.e., whether the capacitor is charged or discharged) determines the information (the logic value) stored within the memory cell. For example a charged capacitor can represent a logic "1" while a discharged, capacitor can represent a logic "0." Despite increases in fabrication technology, no capacitor can be manufactured to be free of charge leakage. As a result, once a storage capacitor is charged to a logic "1," as time passes the charge will begin to leak out of the capacitor. If too much time passes, the amount of charge within the storage capacitor will be too low to be detected. Thus, when the data value is read from the capacitor, the capacitor will appear to be discharged to the memory device, and an erroneous logic "0" will be read instead of the correct logic "1" value.
In order to prevent the data corruption in DRAM memory cells that results from charge leakage, the information within each DRAM memory cell must be periodically "refreshed." To accomplish this, the logic values stored within DRAM memory cells are essentially re-written back into the memory cells with a refresh operation. That is, if a memory cell was storing a logic "1" (its storage capacitor was charged), a logic "1" will be written back into the memory cell (recharging the storage capacitor).
Refresh operations, however, must be accomplished while addressing two competing interests. First, the refresh operation must restore data values. Thus, frequent refresh operations are desirable to ensure that data is not corrupted. At the same time, the amount of current required to charge the memory cells results in increased power consumption. Thus, frequent refresh operations are not desirable as they consume power. These competing interests results in each memory cell being refreshed before a maximum "pause" time passes. The pause time is calculated to account for leakage in a memory cell, and helps to ensure that memory cells storing a logic "1" will be refreshed before the amount of charge falls below a detectable level.
In a typical DRAM array, the memory cells of the same row are accessed by activating a word line common to the row. Because of this, the memory cells are refreshed on a row-by-row basis. To ensure that each row is refreshed, the DRAM typically includes a "refresh" counter. The refresh counter is set to an initial row address, resulting in the initial row being refreshed. According to a refresh clock, the refresh counter is then changed (typically by an increment or decrement operation) to a next row address. This results in the next row address being refreshed. Once a last row address has been reached, the refresh counter returns to the initial row address. In this manner, according to the refresh clock, the refresh counter cycles through all of the rows in the memory device. The speed of the refresh counter will thus determine the rate at which memory cells are refreshed. In order to meet the maximum pause time, the refresh counter must typically cycle through all of the row addresses within the maximum pause time.
A DRAM device can be expected to operate over a range of temperatures. This gives rise a problem associated with prior art refresh circuits. While the maximum pause time may be a certain value at one temperature, it can be different at another temperature. In particular, as the operating temperature of a DRAM decreases, parasitic leakage effects are reduced, resulting in longer maximum pause times. The pause time of a DRAM has been found to roughly double for each 15.degree. C. drop in temperature. Thus, as the operating temperature drops, the memory cells do not need to be refreshed as frequently.
Many prior art DRAM refresh clock circuits actually increase in frequency as the temperature drops. Such circuits are not desirable as they will refresh memory cells more often than is necessary, resulting in wasted power. Prior refresh clock circuits have been built which decrease in frequency as the temperature drops. Such circuits have not been able to provide a drop in frequency sufficient to track the substantial increase in pause time.
It would be desirable to provide a refresh clock circuit that provides substantial drops; in clock speed as the temperature decreases.