1. Field of the Invention
The present invention relates to a semiconductor memory device, and a semiconductor device using the same.
2. Description of the Background Art
Many of EEPROMs (Electrically Erasable Programmable ROMs) currently known in the art employ memory cells of the type where a charge is stored at the floating gate. One of such memory devices, NAND-type flash memory devices, employ a cell array including NAND cell units each having a plurality of memory cells connected together in series. In a NAND cell unit, adjacent memory cells share source/drain diffusion layers. Therefore, by increasing the number of memory cells provided in a NAND cell unit, it is possible to increase the capacity of the NAND-type flash memory with a relatively small chip area.
In a NAND-type flash memory, a plurality of memory cells are connected together in series, as described above, and to a bit line. Data is read out from the NAND-type flash memory by detecting the presence/absence or magnitude of the discharge of the bit line by a selected cell in a NAND cell unit. A pass voltage, which turns ON the cell irrespective of the data therein, is applied to non-selected cells in the NAND cell unit. Since a plurality of cells are connected together in series, a NAND cell unit has a high channel resistance, and the readout cell current is small.
Therefore, it takes a long time before a predetermined voltage difference occurs along the bit line depending on the cell data, and the data read operation of a NAND-type flash memory takes about 20 to 25 μs. During the operation, the NAND-type flash memory externally outputs a busy signal indicating that a read operation is being performed, thereby limiting external accesses to the memory chip of the NAND-type flash memory.
FIG. 16 is a block diagram showing a general configuration of a conventional NAND-type flash memory.
Referring to FIG. 16, a cell array 1 includes a plurality of floating gate-type memory cells arranged in a matrix pattern. A row decoder (including the word line driver) 2 is responsible for selecting a block of the cell array 1, selectively driving a word line, and selectively driving a selected gate line. A sense amplifier circuit 3 forms a page buffer circuit including a page's worth of sense amplifiers for sensing the bit line data of the cell array 1.
A page of readout data is selected by a column decoder (column gate) 4 and is output to an I/O line 13 via an I/O buffer circuit 5. Write data supplied from the I/O line 13 is transferred to the sense amplifier circuit 3 as selected by the column decoder 4. An address signal is input to an address holding circuit 6 via the I/O buffer circuit 5, and a row address and a column address are transferred to the row decoder 2 and the column decoder 4, respectively, via an address predecoder 8.
A controller 9 outputs internal timing signals for the read operation, the write operation and the erase operation based on control signals such as a write enable signal XWE, a read enable signal XRE, an address latch enable signal ALE and a command latch enable signal CLE. Based on the internal timing signals, the sequence operation of the data read operation, the data write operation and the data erase operation is controlled.
A high voltage circuit 10, being controlled by the controller 9, produces a different voltage depending on the operation being performed, i.e., the read operation, the write operation or the erase operation. A busy signal generation circuit 11 outputs a busy signal RY/XBY for indicating, to the outside of the chip, the access status of the cell array 1, depending on the operation being performed, i.e., the read operation, the write operation or the erase operation.
FIG. 17 is a timing chart showing the data read operation of a conventional NAND-type flash memory, and FIG. 18 is a timing chart showing the data write operation thereof.
In the read operation, as the write enable signal XWE and the address latch enable signal ALE=“H” are input to the controller 9 from outside the chip and the address signal Add is input to the I/O buffer circuit 5 from the I/O line 13, the data read operation from the cell array 1 is started. Typically, a NAND-type flash memory performs a data read operation page by page. When the cell data read operation is started, the busy signal RY/XBY=“L” is output from the busy signal generation circuit 11 to outside the chip.
After the cell data read operation for a predetermined amount of time, a page of data read out to the sense amplifier circuit 3 is output to the I/O line 13 via the I/O buffer circuit 5 based on the read enable signal XRE. The operation thus far is one cycle of the read operation. Specifically, one cycle of the read operation includes an operation of reading out the cell data from the cell array 1 to the sense amplifier circuit 3 read operation (hereinafter referred to as the “cell data read operation”), and an operation of outputting the readout data from the sense amplifier circuit 3 to outside the chip (hereinafter referred to as the “readout data outputting operation”). A read cycle as described above is repeated when continuously reading out pages of data.
In a read operation, different cell data cannot be read out during the true busy period where the busy signal RY/XBY=“L”. If the capacity is further increased in the future by increasing the number of memory cells provided in a NAND cell unit, the cell current will be even smaller, thus requiring a longer time for reading out cell data.
In a write operation, the address latch operation (Add.1 IN), the data latch operation (DATA.1 IN) and the data programming operation (PROGRAM 1) are all performed in series in a first write cycle, and then a second write cycle is similarly performed on a different address. As with the read operation, if the number of memory cells in a NAND cell unit increases, it will require a longer time for writing data to memory cells.
In view of this, Japanese Laid-Open Patent Publication No. 2005-25819, for example, discloses a semiconductor memory device (e.g., a NAND-type flash memory) in which the cell array is formed by a plurality of cell array blocks each including a plurality of memory cells arranged therein to thereby increase the speed of the data read operation.
FIG. 19 is a timing chart showing the data read operation of the semiconductor memory device.
In the first read cycle in which the first region in the first cell array block is selected, the semiconductor memory device simultaneously performs the cell data read operation for the first region of the first cell array block and the cell data read operation for the second region of the second cell array block, and outputs the true busy signal from the busy signal generation circuit 11 during this period. In the following second read cycle in which the second region in the second cell array block is selected, the cell data read operation is not performed and the busy signal generation circuit 11 outputs a dummy busy signal RY/XBY=“L”, which is shorter than the true busy signal. Therefore, the busy period is shortened, and the speed of the data read operation is increased without changing the specifications of the NAND-type flash memory.
With a large-capacity NAND-type flash memory, however, in a case where data from a plurality of cell array blocks are read out sequentially or at random, the cell data read operation and the address latch operation for the data to be read out next are performed serially, and data accesses from outside are restricted during the cell data read operation (while the busy signal is being output), thereby making it difficult to realize a high-speed data read operation from the NAND-type flash memory. For example, when reading out a continuous piece of data that is written over a plurality of cell array blocks or when reading out and checking various status data written in all cell array blocks at power-on of the memory chip, it requires a long read time because access from outside is prohibited by the busy signal each time a cell array block is accessed.
In a write operation, a programming operation is performed serially with the write address latch operation and the data latch operation for the next programming operation, thus also lowering the write speed.