Conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise eight or more levels of metallization to satisfy device geometry and micro miniaturization requirements.
A common method for forming metal lines or plugs is known as “damascene”. Generally, this process involves forming an opening in the dielectric interlayer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a via. Excess metal material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
Copper has replaced aluminum because of its lower resistivity and higher reliability, which was expected to be better because of its higher activation energy for diffusion. However, copper still suffers from electro migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink, and current densities increase.
FIG. 1 illustrates a cross sectional view of a conventional interconnection structure 1 formed using damascene process. Metal lines 2 and 4, which are typically formed of copper or copper alloys, are interconnected by via 10. Inter-metal-dielectric (IMD) 8 separates two layers that metal lines 2 and 4 locate. Etch stop layer (ESL) 5 is formed on lower layer copper line 2. Diffusion barrier layers 12 and 14 are formed to prevent copper from diffusing into surrounding materials. The interconnection structure 1 in FIG. 1 suffers from electro migration and stress migration problems. Since the copper line 2 is in direct contact with a dielectric ESL 5, the character difference between copper 2 and dielectric ESL 5 causes higher electro migration and stress migration; therefore device reliability is degraded. FIG. 2 illustrates an improvement made to the conventional interconnection structure 1 by forming a metal cap layer 16 on the copper line 2. Cap layer 16 is typically formed of materials suffering less from electro migration. This layer greatly improved the reliability of the interconnections structure 15 by removing the interface between copper line 2 end dielectric layer 5. The copper surface migration of structure 15 is reduced. It has been found that under stressed conditions, the mean time to failure (MTTF) of the interconnection structure 3 is ten times longer than that of the interconnection structure 1 due to the reduction of electro migration. With the cap layer 16 formed, the stress induced void formation is also significantly reduced.
However, the introduction of the cap layer 16 generates another problem. IMD 8 is etched in order to form an opening for via and then ESL 5 is etched. Metal cap layer 16 is typically etched through due to over etching when ESL 5 is etched. In conventional formation of the interconnect structure, the process is only controlled so that the over etching stops at a time after the ESL 5 has been etched out. Typically, over etching may stop in cap layer 16 or copper 2. If over etching lands in cap layer 16, since metal cap 16 normally has a higher resistance than copper 2, the resistance of the remaining cap layer 16 contributes to the resistance of the interconnection. Higher resistance of the interconnection causes higher RC delay of the integrated circuits; if over etching stops in copper line 2, the contact resistance is much smaller than the contact resistance having a remaining cap layer 16. Therefore, contact resistance and RC delay varies from process to process and is harder to predict.
In order to reduce contact resistance and RC delay, and reduce process variation, a new method of forming interconnection structures is needed.