Computer systems typically include more than one bus, each bus having devices attached which communicate locally with each other. Often, system busses and peripheral busses use different sets of standard protocols or rules to conduct data transfers between the different devices and components that are connected thereover. Devices for translating data that is transferred from one bus architecture to another bus architecture are often called bridges. To permit system-wide communications on different bus systems, bus-to-bus bridges match the communications protocol of one bus with that of another bus.
Presently, "local busses" operate in such a manner as to be more closely associated with central processor operations and are capable of running at speeds that approximate the speed at which the central processor, itself, runs. One popular type of "local bus" is the "peripheral component interconnect" (PCI) bus. A system using a PCI bus includes, in addition to the physical PCI bus, a first bridge circuit which provides an interface and controls transfers of data among the devices connected to the PCI bus. A second bridge circuit (also called a bus controller) provides an interface for transfer of data between a further bus system and the PCI bus. The arrangement is such that components on the PCI bus transfer and receive data via the first bridge, while components on the second bus system transfer and receive data via the second bridge (or bus controller). The two bridges communicate with each other and enable data transfers between elements connected to the PCI bus and the second bus system.
Currently, a widely used bus system protocol for connecting host processors to peripheral devices, such as memory subsystems, is one which adheres to the small computer system interconnect (SCSI) protocol. The prior art includes a number of teachings regarding methods for interconnecting SCSI bus systems to PCI bus systems. Examples of such teachings can be found in U.S. Pat. No. 5,634,033 to Stewart et al. and U.S. Pat. No. 5,522,050 to Amini et al.
U.S. Pat. No. 5,664,117 to Shah et al. discloses a bridge which is arranged to enable highly efficient memory transfers from a first bus to a second bus. One such bus is a PCI bus and the second bus, for example, is one which adheres to either the industry standard architecture (ISA) or the expanded industry standard architecture (EISA). The Shah et al. system describes a procedure for employing the bridge to stage data that is being transferred from a memory system to a host processor (or vice-versa) during a DMA (direct memory access) transfer.
A DMA transfer relieves a central processor of the need to accomplish many of the individual data transfers that are required during operation of a computer system. A DMA device is typically given a memory address and an amount of data to be transferred, by the central processor, and then proceeds to transfer that amount of data, beginning at the specified address. The DMA device generates a series of sequential addresses and accesses the data stored at each of those addresses.
The Shah et al. system describes a bridge with a plurality of line buffers for storing data being read from a first bus to a second bus. The bridge reads an amount of data sufficient to fill the storage space in a first line buffer, beginning at an address being read, and completely fills a next line buffer with data at following sequential addresses, assuming that read operations, after the first line buffer, will occur at sequential addresses. In such manner, Shah et al. accomplish a prestaging of data.
In many bridges, such as the type described by Shah et al., means are provided to assure the integrity of data received during a DMA transfer. Thus, if data transfers are being accomplished in block sizes, presuming that a host processor has requested a plurality of blocks occurring at sequential addresses, the bridge is designed to signal an error if an out-of-sequence address is encountered. In such case, all data prestaged for a block is dumped and data transfer of the block is repeated.
It has been discovered that such an out-of-sequence data transfer can occur when a memory controller, during a DMA, appends check or other control bytes to the data block being transferred. Under such circumstances, the bridge which receives the data block with the appended control or check bytes assumes that the control and check bytes come from sequential addresses to those occupied by the data block.
When a next data block is received which commences at the immediately succeeding address after the first data block (not taking into account the N bytes of metadata), an error state is assumed as the bridge is expecting data starting at the last address plus N of the first block. However, it receives data starting a the last address plus 1 of the first block. As a result, the DMA transfer is suspended and a prestage of the most recent block is repeated.
Accordingly, it is an object of this invention to provide an improved method for handling of data transfers over a bridge circuit, wherein check or other control bytes are appended to data blocks being transferred.