Heretofore, an electronic part and a printed wiring board that have a multilayer structure produced by forming a wiring pattern on an insulating layer and stacking wiring patterns thus formed along their thickness direction have been known.
Various methods of producing such a structure have been proposed and disclosed. FIGS. 5A and 5B are diagrams illustrating steps in a conventional process of producing each layer of an electronic part.
In the step shown in FIG. 5A, a surface of an insulating layer 1 is perforated by irradiation with a layer beam. After a hole 2 is formed by the laser processing, the hole is filled with an electrically conductive paste, or a conductor portion in the form of a film or a column is formed in the hole 2 by plating.
In the step shown in FIG. 5B, conductor portions 4 are formed by plating or etching on a surface of an insulating layer 3, which has been produced in advance. After the conductor portions 4 have been formed by the above process steps, an insulating resin 5 is applied on the surface of the conductor portions 4 by spin coating (see, for example, patent document 1).
In a different known method, a bump of an electrically conductive paste is formed on wiring on a board, then an insulating material for interlayer connection and a metal layer are provided, and the bump is caused to penetrate a molded resin by a pressing process to achieve electrical connection between said bump and the metal layer (see, for example, patent document 2).
Furthermore, a method in which a via hole conductor is formed by forming a through hole by means of a carbon dioxide gas laser or other means and filing the through hole with a paste containing powder of a low resistance metal such as gold, silver, copper and aluminum has also been disclosed (see, for example, patent document 3).
Still further, a method in which an insulating layer is formed by applying a resin around a conductor post for interlayer connection and then pressing the resin with a release film having appropriate surface roughness like an emery paper disposed between (see, for example, patent document 4).
In a different method that has been disclosed, a resin layer in the A stage on which a PET film serving as a protection film is attached is disposed in contact with a surface on which an electrically conductive projection is present, and a thermosetting insulating resin layer is formed by lamination. Then, the PET film is removed, the electrically conductive projection and wirings are brought into contact with each other to form an laminated member (see, for example, patent document 5).
Furthermore, a method of producing a wiring board in which a transfer original and a base board on which wiring is to be formed by transferring are pressed together in a state in which a spacer for keeping the film thickness of an insulating rein layer to a predetermined thickness is disposed therebetween has been disclosed (see, for example, patent document 6).    Patent Document 1: Japanese Patent Application Laid-Open No. 10-22636.    Patent Document 2: Japanese Patent Application Laid-Open No. 2002-137328.    Patent Document 3: Japanese Patent Application Laid-Open No. 2002-134881    Patent Document 4: Japanese Patent publication No. 6-57455    Patent Document 5: Japanese Patent Application Laid-Open No. 2001-177237    Patent Document 6: Japanese Patent Application Laid-Open No. 11-261198
In connection with electronic parts having a multilayer structure, incorporation of an element etc. in the interior of the electronic part has been considered in order to further increase density and functions. If an element such as a passive component is to be formed between wiring patterns stacked along the lamination direction, the distance between the aforementioned wiring patterns is an important factor that determines characteristics of the aforementioned element. Accordingly, from the viewpoint of stabilization of characteristics of the element, there has been a demand for a method for manufacturing an electronic part that enables reliable control of the distance between the aforementioned wiring patterns or the thickness of each layer in the electronic part.
Nevertheless, in the above-mentioned manufacturing method shown in FIG. 5A, a conductor portion is simply formed in a hole 2 that has been formed on an insulating layer 1 by a laser processing, but the overall thickness of the layer is not controlled.
In the manufacturing method shown in FIG. 5B, an insulating resin layer is formed to cover conductor portions by applying resin by spin coating. However, undulation is created on the surface of the insulating resin in accordance with presence/absence of the conductor portions 4, and therefore it is difficult to make the overall thickness of the layer uniform.
Furthermore, in the method in which a bump of electrically conductive paste is formed on wiring on a board and then the bump is caused to penetrate a molded resin by pressing, no consideration has been made on control of the overall thickness of the layer. Still further, Japanese Patent Application Laid-Open No. 2002-134881 only teaches to form a via hole conductor by filling paste, but no consideration is made on control of the overall thickness of the layer.
In the technology disclosed in Japanese Patent Publication 6-57455, it is necessary to remove the release film from the surface of the insulating layer after completion of the pressing process. However, there is a risk that an external force will act on the surface of the insulating layer in this removing operation and deformation etc. may occur on the surface of the insulating layer. In addition, since resin is applied to cover conductor portions as with the process shown in FIG. 5B, there is a risk that undulation will be created on the surface of the insulating resin and it will be difficult to make the overall thickness of the layer.
In the technology disclosed in Japanese Patent Application Laid-Open No. 2001-177237 also, an external force acts on the thermosetting insulating resin layer when the PET film is removed, and therefore, there is a risk that deformation may be created on the surface of the thermosetting insulating resin layer, as with the technology disclosed in the above-mentioned patent document. Accordingly, it might be difficult to make the overall thickness of the layer uniform.
In the method of setting the thickness of a layer by inserting a spacer as disclosed in Japanese Patent Application Laid-Open No. 11-261198, although it is possible to set the layer thickness, it is difficult to achieve connection between layers by a conductor portion at a predetermined position.
In such manufacturing methods, it has generally been desired, in order to reduce the manufacturing cost, to reduce the amount of the material used, namely to reduce surplus of the resin used for forming insulating layers.