1. Field of the Invention
The present invention relates to a semiconductor device, and testing method and device for the semiconductor device and, more specifically, to a semiconductor device having a semiconductor chip mounted therein by flip chip packaging, and testing method and device for such a semiconductor device.
2. Description of the Related Art
With the recent size reduction and performance advancement of electronic devices varying in type, a semiconductor package is increased in density for use in the electronic devices. The high density packaging technology is also growing more advanced for mounting the semiconductor package to a circuit board with high density. Such a technology includes flip chip packaging with which a semiconductor chip is electrically connected directly with its face down to a circuit board. As an example, refer to Patent Document 1 (JP-A-10-50769).
In the below, described is a manufacturing method of a semiconductor package by flip chip packaging by referring to the accompanying drawings.
With the previous flip chip packaging, as shown in FIG. 4A, an electrode 102 of a semiconductor chip 101 is firstly formed with a protruding electrode 103, which is generally called a bump and hereinafter referred to as chip-side bump. The chip-side bump is formed mainly using soft solder with a height of about 15 μm.
Separately from such a chip-side bump, as shown in FIG. 4B, another protruding electrode 106 is formed to an electrode 105 of a circuit board 104, which is a glass-epoxy substrate mounting thereon with a semiconductor chip. The protruding electrode 106 is also formed mainly using soft solder with a height of about 15 μm, and is hereinafter referred to as circuit board-side bump.
As shown in FIG. 4C, the semiconductor chip formed with the chip-side bump is flipped over for adsorptive fixation using a nozzle 107 for mounting use, and the semiconductor-chip-fixed nozzle 107 located above the circuit board is directed downward. With such a downward movement, the chip-side bump formed to the semiconductor chip comes in contact with the circuit board-side bump formed to the circuit board. Even thereafter, a load is continuously applied in the direction of bringing down the mounting nozzle 107 so that the load of a predetermined level is applied to the semiconductor chip. Note here that, with an assumption that both the chip-side bump and the circuit board-side bump remain intact in the state that the chip-side bump formed to the semiconductor chip is being in contact with the circuit board-side bump formed to the circuit board, and in the state that the chip-side bump and the circuit board-side bump are facing each other, a gap between the circuit board and the semiconductor chip is about 30 μm. The gap is indicated by a reference character A in the drawing.
As shown in FIG. 4D, during a heating process, the mounting nozzle is directed downward again this time until the gap between the circuit board and the semiconductor chip becomes about 25 μm. That is, in the state that the soft solder configuring the chip-side bump and the circuit board-side bump is melted, the nozzle is moved down about 5 μm so that the chip-side bump is merged together with the circuit board-side bump. As such, an electric connection is established between the circuit board and the semiconductor chip.
Thereafter, the gap between the circuit board and the semiconductor chip is filled with an underfill material 109. The resulting circuit board filled with the underfill material is loaded to a molding die (not shown) configured by upper and lower dies. The circuit board-loaded mold die is then filled with a mold resin 108 being a glass epoxy resin so that such a semiconductor package as shown in FIG. 4E is derived.
The issue here is that, in view of ensuring the electrical properties and the product durability of the semiconductor package, expected is to control the gap between the circuit board and the semiconductor chip with high accuracy. The reasons are described in detail below.
1. Ensuring Electrical Properties of Semiconductor Package
It is known that the gap size between the circuit board and the semiconductor chip changes the resistance value of a bump being a merge result of the chip-side bump and the circuit board-side bump. When the gap between the circuit board and the semiconductor chip is small, the resistance of the bump being a merge result of the chip-side bump and the circuit board-side bump becomes high in value. When the gap between the circuit board and the semiconductor chip is large, the resistance of the bump being a merge result of the chip-side bump and the circuit board-side bump becomes low in value.
In consideration thereof, to derive any desired value for electrical resistance between the circuit board and the semiconductor chip in the semiconductor package, i.e., to ensure the electrical properties inside of the semiconductor package, there needs to exercise control over the gap between the circuit board and the semiconductor chip with high accuracy.
2. Ensuring Product Durability of Semiconductor Package
As described above about the previous manufacturing method of a semiconductor package, to manufacture a semiconductor package, an underfill material is filled between a gap between a circuit board and a semiconductor chip for the purpose of making more reliable the state of junction between the circuit board and the semiconductor chip. The concern here is the fact that, irrespective of the size of the gap between the circuit board and the semiconductor chip, the amount of the underfill material for use for filling to the gap between the circuit board and the semiconductor chip remains the same. Therefore, when the gap between the circuit board and the semiconductor chip is too large, the underfill material is not to be sufficiently filled to the gap between the circuit board and the semiconductor chip, thereby reducing the product durability of the semiconductor package.
On the other hand, when the gap between the circuit board and the semiconductor chip is too small, the underfill material will overflow from the gap between the circuit board and the semiconductor chip, and the overflowed material will find its way and attach to the upper surface of the semiconductor chip. Because the underfill material generally has no affinity for the mold resin, the underfill material attached to the upper surface of the semiconductor chip prevents the mold resin from being filled to a sufficient level, thereby reducing the product durability of the semiconductor package.
Therefore, in order not to reduce the product durability of the semiconductor package, i.e., in order to ensure the product durability of the semiconductor package, there needs to control the gap between the circuit board and the semiconductor chip with high accuracy.
These are the reasons why the gap between the circuit board and the semiconductor chip is expected to be controlled with high accuracy. For the purpose, semiconductor packages whatever manufactured are all subjected to quality assessment by measuring the gap between the circuit board and the semiconductor chip in each of the semiconductor packages.
For measuring a gap between a circuit board and a semiconductor chip in a semiconductor package, a scanning electron microscope (SEM) is possibly used as an example. With the SEM being an electron microscope, electron beams each having the diameter of a few nm sweep systematically the surface of a sample, and the intensity of generation results of interaction between the electron beams and the sample, i.e., secondary electrons and reflected electrons, is recorded in synchronization with scanning of primary beams.
Alternatively, for measuring a gap between a circuit board and a semiconductor chip in a semiconductor package, a measuring microscope utilizing the characteristics of the depth of focus is also a possibility for use.
That is, two distances are measured, i.e., a distance from a reference position to the surface of a circuit board (semiconductor-chip-side surface of the circuit board), i.e., distance indicated by a reference character B in FIG. 4E, and a distance from the reference position to the surface of a semiconductor chip (surface facing the circuit-board-side surface of the semiconductor chip), i.e., distance indicated by a reference character C in FIG. 4E. From thus calculated distance between the reference position and the surface of the circuit board, i.e., distance B, two values are subtracted so that the gap between the circuit board and the semiconductor chip is measured. The two values for subtraction are the distance from the reference position to the surface of the semiconductor chip, i.e., distance C, and the thickness of the semiconductor chip, i.e., distance indicated by a reference character D in FIG. 4E.
Exemplified above is the semiconductor package including the semiconductor chip mounted over the circuit board by flip chip packaging, and described above are the demand of control exercise over the gap between the circuit board and the semiconductor chip with high accuracy, and the method of measuring the gap between the circuit board and the semiconductor chip. Alternatively, if with a semiconductor package including semiconductor chips mounted by flip chip packaging to a circuit board with an electric connection between the semiconductor chips using a protruding electrode, there needs to control the gap between the semiconductor chips with high accuracy. To measure the gap between the semiconductor chips, used is a method similar to that of measuring the gap between the circuit board and the semiconductor chip.