1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a delay apparatus of a synchronizing circuit and a method of controlling the same.
2. Related Art
A synchronizing circuit according to the related art is divided into a delay locked loop (hereinafter, simply referred to as“DLL”) and a phase locked loop (hereinafter, simply referred to as “PLL”).
As shown in FIG. 1, the DLL uses a delay line, and the delay line includes a plurality of delay units 10, for example, four delay units 10. The first delay unit 10 has two input terminals IN1 and IN2 to which a clock and the inverted clock are input, respectively.
A delay time of each of the delay units 10 is determined by a first control voltage (hereinafter, referred to as “VBP”) that is commonly input to the delay units 10. Further, the delay units 10 commonly receive a second control voltage (hereinafter, simply referred to as “VCN”) such that swing widths of output signals are uniform.
Meanwhile, the PLL uses a voltage controlled oscillator (hereinafter, simply referred to as “VCO”). As shown in FIG. 2, the VCO uses a delay line that is almost same the delay line of the DLL. But, a first delay unit 10 of the PLL is fed back output signals OUT and OUTB of the VCO.
As described above, the delay lines that include the plurality of delay units need to be used for the synchronizing circuits, such as the DLL, the PLL, and the like. The circuits that use the analog-type delay units are very sensitive to a physical mismatch and variations in PVT (Process/Voltage/Temperature). Therefore, when the delay units are designed, in order to increase the yield of the delay units, a range of an operating frequency is determined to cope with all of the above-described variations.
However, in the delay units of the synchronizing circuit according to the related art, as the range of the operating frequency is determined to cope with all of the variations when designing the circuits, jitter characteristics become worse, thereby deteriorating the performance of a device to which the delay units are applied. In particular, the wider the operating frequency band a system has, the more the performance of the system decreases due to the deterioration of the jitter characteristics.