Complicated integrated circuits such as ASICs (application specific integrated circuits) and FPGAs (field programmable gate arrays) are typically designed using CAD (computer aided design) tools. The development of complicated integrated circuits with the aid of CAD tools is referred to as electronic design automation, or EDA. Design, checking, and testing of large-scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient implementation of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures, and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a "silicon compiler"). The computer-implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a "netlist." The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections can be used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology-dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells, which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art, and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest ASIC designs. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. One approach to DFT is to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. On the other hand, issues concerning observability deal with facilitating the capturing the output of the circuitry.
Another approach to DFT is to take the mapped netlist generated form the compiler, and insert observe/control points, or test points, to certain logic portions of the integrated circuit design. Appropriate test vectors are then applied to the input of the integrated circuit design and to the test points and the responses to the test vectors are monitored. Observe points are particularly useful for detecting otherwise unobservable faults. For example, in the circuit 100 illustrated in FIG. 1A, it may be impossible to detect a fault (e.g., a stuck-at-0 fault) at an internal node 102 from the circuit output. As illustrated in FIG. 1B, by incorporating an observe point at the internal node 102, a specific input pattern may be applied to the circuit 100 to detect the fault.
FIGS. 2A and 2B illustrate the usefulness of adding a control point within a circuit. As shown in FIG. 2A, it may be impossible to detect a stuck-at-1 fault with the X-NOR gate 210 of the circuit 200 if the outputs of the logic block 220 are always the same. This problem may be circumvented by the addition of a control point to the circuit 200. A modified circuit 250 including an AND gate 230 is illustrated in FIG. 2B. During normal operation, the control input of the AND gate 230 is set at logic 1. To test for a stuck-at-1 fault at the output of the X-NOR gate, the control input of the AND gate 230 is set at logic 0 and an input combination that produces logic 1 at the outputs of the logic block 220 is applied. In this way, the testability of the circuit 200 is improved.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG. 3. The processes 300 described with respect to this flow chart are implemented within a computer system in a CAD environment. HDL descriptions of the integrated circuit enter at block 301. Accompanying the HDL 301 is a set of performance constraints 305 applicable to the design which typically includes timing, area, power consumption, and other performance related limitations that the compiler 325 will attempt to satisfy when synthesizing the integrated circuit design. Constraints 305 can also include non-performance related constraints, such as structural and routing constraints. Compiler 325 consists of a generic compiler 303 (also called an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs the HDL 301 description and generates therefrom a technology independent or "generic" netlist 307, which is also dependent on the constraints 305. As discussed above, the netlist 307 is a list of technology-independent components, or operators, and the interconnections between them.
The generic netlist 307 is then inputted to a design compiler 309 that includes a computer-implemented logic optimization procedure and a mapping procedure which interfaces with a technology-dependent cell library 330 (e.g., from LSI, VLSI, TI, or Xilinx technologies, etc.). The cell library 330 contains specific information regarding the cells of the specific technology selected, such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library 330. Logic optimization procedure of block 309 includes structuring and flattening procedures. The mapping procedure of block 309 generates a gate level mapped netlist 311 that is technology dependent, having cells specifically selected to satisfy the constraints 305. At this point, this gate-level mapped netlist 311 consists of "mission mode" circuitry.
At block 313, a test point insertion process is performed to implement testability cells or "test mode" cells into the overall integrated circuit design. In the process 313, particular nets of the mapped netlist 311 are selected for test point insertion, and logic gates for implementing test points are inserted into the gate-level mapped netlist 311. The output of this test point insertion process is a DFT netlist 315 including both mission mode circuitry and test point circuitries. In addition to the test point insertion process, other DFT processes, such as scan insertion, can also be applied.
One problem that occurs in the prior art logic synthesis process 300 is that the test point insertion process 313 does not take into account its impact on the mission mode constraints (e.g., constraints 305). Specifically, the addition of the testability cells (e.g., test points), and the addition of other dedicated connections required for operation of the test points can cause the overall design to violate one or more of the defined constraints 305.
Therefore, a second compile process 317 of FIG. 3 (full or incremental compile) is often invoked by the prior art process 300 in order to optimize more effectively the DFT netlist 315 to the constraints 305. It should be appreciated that an incremental compile (e.g., incremental compile 317) may not process all existing structure as in a full compile. An incremental compile may only apply high level logical optimization to the unmapped portions of the design. Those unmapped portions can then be mapped using a technology-dependent library. However, the incremental compile still applies mapping optimizations iteratively on the entire DFT netlist 315. As a result, processing time to perform the second compile process 317 can be on the order of weeks given conventional CAD technology and circuit complexity.
After the second compile process 317 of FIG. 1 completes, a DFT netlist 319 is again generated that contains the testability cells, and, at block 321, the prior art then performs a test to determine if the DFT netlist 319 meets the mission constraints (e.g., constraints 305). If the netlist 319 meets mission mode constraints, at block 323, other circuit synthesis procedures continue until the integrated circuit design can be fabricated onto a substrate and tested.
However, as is often the case, the addition of the testability cells by the test point insertion process 313 does not allow the second compile process 317 to meet test mode constraints 305 without a design modification to the original HDL program 301. In such case, the overall process 300 flows from block 321 back to the HDL 301 where the architect modifies the HDL program 301 so that the addition of the testability cells and other resources will eventually satisfy, when possible, the given test mode constraints 305 after the incremental compile step 317 is again executed.
The prior art process 300 of FIG. 3 has several disadvantages. It is disadvantageous to execute a second substantial compile process 317 in an attempt to match the testability cells and linking resources to the given set of constraints (e.g., test mode and mission mode). Although this process can be an incremental compile step in that many of the gate level connections are not removed, mapping optimization portions of this compile process still operate in an iterative fashion over the entire design. The addition of this second compile process, using conventional technology, delays the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the incremental compile process 317 will generate a scannable netlist satisfying the constraints 305. In this case, a time-consuming task of returning to the HDL for redesign is required. This process involves the chip architect designers once more, and, therefore, it is unclear under the prior art system when a designer can sign off on his or her work in the design process.
Thus, what is needed is a method of and system for improving testability of an integrated circuit design without delaying the overall integrated circuit synthesis process. What is further needed is a method of and system for implementing testability circuitry, particularly test point circuitry, for an integrated circuit design such that a second compile process can be obviated.