Conventional SOI IC chips, independent on how the SOI material is prepared, has one starting silicon thickness. The silicon thickness is determined by the specific silicon device to be built. For example, for so-called partially-depleted CMOS devices, the silicon layer thickness should be thick enough, typically on the order of about 100 to about 300 nm, such that there is always a non-depleted quasi-neutral silicon region left beneath the CMOS device channel region, or in the CMOS “device substrate”. However, for so-called fully depleted CMOS devices, the silicon layer thickness should be thin enough, typically on the order of about 10 to about 150 nm, such that the “device substrate” beneath the gate region is normally depleted of mobile carriers and there is no quasi-neutral region left beneath the CMOS device channel region.
One serious limitation with conventional single-thickness SOI material is that it is not suitable for building several kinds of silicon devices, or silicon devices for different applications, on the same chip. For example, high-speed digital CMOS usually uses a relatively thin Si layer, while analog CMOS prefers a thicker. Si layer. In fact, for precision analog circuits, it is preferred to have the silicon layer thick enough to provide a convenient device substrate contact in order to avoid undesirable floating-body effects associated with SOI MOSFET devices without device substrate contact. Moreover, bipolar devices may require an even thicker silicon layer in order to accommodate the three vertical device regions, namely the emitter, the base and the collector.
In view of the above, there is a need for providing SOI IC chips in which the top Si-containing layer of the SOI wafer has regions of variable thickness. By providing regions of different thickness on the same Si layer, a SOI wafer suitable for integrating various types of silicon devices on the same SOI chip can be obtained. That is, it also permits “system on an SOI chip” to be realized.