A parallel data bus typically comprises a number of bus lines to which the components of a computer system may be connected for communicating information between one another. Each component coupled to the data bus typically includes a set of bus driver circuits for transmitting data via the bus lines by switching the voltages of the bus lines between voltages that correspond to logic states, however defined. The speed at which a bus driver circuit switches the voltages of the bus line between logic states is called the "slew rate," and the slew rate of the bus driver circuit is an extremely important characteristic for ensuring proper operation of the bus driver circuit at the clock speed of the data bus.
FIG. 1 shows a bus driver circuit 100 that operates according to the prior art. Bus driver circuit 100 is shown as comprising NAND gate 105, pass gate 110, inverter 115, and an output buffer 120, which is shown as comprising an n-channel transistor having its source coupled to system ground VSS and its drain coupled to bus line 150. A terminating resistor 125 is shown as being coupled between bus line 150 and a terminating supply voltage V.sub.term.
NAND gate 105 operates as an input buffer and has a first input coupled to receive a data signal DATA and a second input coupled to receive an enable signal EN. When the EN signal is at a logic high value NAND gate 105 operates as an inverter for inverting the DATA signal to produce an inverted data signal DATA. Pass gate 110 is switched on to pass the DATA signal in response to the high level of transmit clock signal TCLK. Inverter 115 receives the DATA signal and inverts it to provide a drive signal DRIVE at the input of output buffer 120. Output buffer 120 is switched on to drive bus line 150 to a low voltage causing the output signal OUT to have a low voltage value when the DRIVE signal is logic high. Output buffer 120 is switched off when the DRIVE signal is a logic low, and the bus line 150 is charged to the terminating voltage V.sub.term in response to terminating resistor 125, causing the OUT signal to have a high voltage value.
The slew rate of the output signal OUT is determined by the slew rate of the DRIVE signal. The nominal slew rate of the DRIVE signal is known because the device sizes of inverter 115 are specified to have known values; however, variations in device sizes and device parameters (e.g. gain and threshold voltage) can occur when fabricating a semiconductor device. Therefore, the actual slew rate of the DRIVE signal may vary from the nominal slew rate due to such "process" variations, and the slew rate of the OUT signal is similarly affected. Furthermore, temperature and power supply variations that occur during operation of bus driver circuit 100 can also affect the slew rate. If the actual slew rates of the DRIVE and OUT signals are too much greater than their nominal values, bus driver circuit 100 may induce undesirable ringing on the bus line and voltage transients or "ground bounce" on the supply lines due to, for example, inductance of an integrated circuit package housing bus driver circuit 100 (i.e., inductance due to bond wires, the lead frame, etc.). If the actual slew rate of the DRIVE and OUT signals are too much less than their nominal values, bus driver circuit 100 may not be able to reliably operate at the frequency of the bus clock. The ability to control slew rate variations of a bus driver circuit is therefore desirable.