As integrated device manufacturers continue to shrink the feature sizes of transistor devices to achieve greater circuit density and higher performance, there is a need to manage transistor drive currents while reducing short-channel effects such as parasitic capacitance and off-state leakage for next-generation devices.
Non-planar transistors, such as fin-based dual- and tri-gate transistors improve control of short channel effects. For example, with tri-gate transistors, the gate forms adjacent to three sides of the channel region. Because the gate structure surrounds the fin on three surfaces, the transistor essentially has three gates controlling the current through the channel region of the fin. These three gates allow for fuller depletion within the fin and result in less short-channel effects due to steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). Recently, wrap-around gate structures have been developed wherein the gate electrode and source/drain contacts wrap around the full perimeter of semiconductor nanowires, enabling greater management of leakage and capacitance in the active regions, even as drive currents increase.
Drive currents are typically tailored to device specifications by varying the gate width. In dual- and tri-gate devices, the fin height can be altered. However, new wrap-around transistors require different strategies to vary gate width of nanowire-based devices, and also require further development of new fabrication methods that can be integrated into current processes.