A resistance change memory has a thinner and longer bit line and a greater resistance value of the bit line if a memory cell is more miniaturized and the memory capacity is increased. This leads to the use of an architecture (hierarchical bit line structure) in which a memory capacity is divided into blocks, a low-resistance global bit line is disposed on these blocks, and the global bit line is connected to a local bit line in each of the blocks.
In this architecture, a read operation is performed by the use of a sense amplifier to compare a read current or a read voltage dependent on data (resistance value) stored in the memory cell with a reference current or a reference voltage. However, in this reading, the load capacity of a conductive line (global bit line) on the side of the memory cell is higher than the load capacity of a conductive line on the side of a reference cell.
Therefore, the time (latency) from a read operation instruction to the start of sensing by the sense amplifier is long.