1. Field of the Invention
The present invention relates generally to a reticle or mask used in a lithography process and, more particularly, to fabricating a reticle or mask for use in an extreme ultraviolet lithography process.
2. State of the Art
Lithography processes are commonly used to create features on a semiconductor wafer by transferring a pattern or image from a reticle or mask. The reticle, which contains the pattern to be transferred, is placed over the semiconductor wafer and light from a light source is transmitted through the reticle. For example, in extreme ultraviolet (xe2x80x9cEUVxe2x80x9d) lithography, light is reflected off the reticle and projected through a series of mirrors onto the semiconductor wafer. The pattern on the reticle creates an image that is reduced in size and transferred to a photoresist layer covering the semiconductor wafer. The resist is then developed and the semiconductor wafer is etched and processed further to form the semiconductor device having the desired circuit pattern.
The wavelength of light transmitted through, or reflected by, the reticle determines the size of the features to be created on the semiconductor device. Generally, light of a shorter wavelength is used to more precisely and accurately create small features. For example, deep ultraviolet radiation is used to create semiconductor devices at 0.15 xcexcm, but for semiconductor devices at 0.05 xcexcm or lower, EUV radiation is used.
In EUV lithography, EUV radiation is directed from a light source onto an EUV reticle through a series of mirrors. The EUV radiation comprises light at a wavelength of approximately 3-50 nm. The EUV reticle comprises a substrate and multiple, reflective layers that are supported on the substrate. On top of the reflective layers is an absorbing layer that is patterned with a circuit design that absorbs some of the EUV radiation. The remaining EUV radiation is reflected by the reflective layers, through a series of aspheric mirrors, to produce a desired pattern on the semiconductor wafer. Since the reticle includes reflective layers, EUV radiation is not transmitted through the substrate. Rather, the EUV radiation is reflected by the reticle.
In order to achieve the desired accuracy and precision of EUV lithography, a surface of the substrate of the EUV reticle must be optically flat or free of defects. If the substrate surface is not flat, the defects may be propagated into the reflective layers and ultimately transferred to the photoresist layer of the semiconductor wafer. In other words, these defects may substantially degrade the image fidelity produced by the reflective layers. Defects on the substrate cause local perturbations in the reflective layers that will generate a phase difference in the light that is reflected at that point. The out-of-phase light will interfere destructively with the surrounding light and alter the desired image. The flatness of the substrate is measured by peak-to-valley flatness of the substrate surface topography. Currently, substrates exhibiting a 200-400 nm (2000-4000 xc3x85) peak-to-valley surface flatness are available from manufacturers in EUV reticles. However, it would be desirable to use substrates having 50 nm (500 xc3x85) or less peak-to-valley surface flatness to achieve the necessary performance. While 50 nm (500 xc3x85) peak-to-valley surface flatness has been achieved for optics, this degree of flatness requires additional, expensive fabrication steps, such as abrasive polishing. These abrasive polishing steps may include chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) or lapping techniques.
In addition to surface flatness, the substrate must also have a low coefficient of thermal expansion (xe2x80x9cCTExe2x80x9d). If the substrate has a high CTE, heat produced by the EUV radiation and conducted to the substrate may cause the substrate to expand, thereby increasing the size of the reticle and features thereof as well as potentially causing distortion. Such changes to the reticle may affect the accuracy and precision of the image to be patterned onto the semiconductor wafer.
An optimal substrate would have a high degree of surface flatness, in order to achieve the desired reflectivity of the reflective layers, and a low CTE, in order to minimize expansion of the substrate. However, an inverse relationship exists between the surface flatness and thermal expansion properties of commonly used substrates. For example, silicon is commonly used as a substrate in EUV reticles because of its easily obtainable surface flatness characteristics. However, silicon has a relatively high CTE (2.5 ppm/xc2x0 C.). Other substrates commonly used in EUV reticles include ultra-low expansion materials, such as ULE(trademark) glass or ZERODUR(trademark) glass ceramic. While ULE(trademark) glass has a low CTE (0.02 ppm/xc2x0 C.), it has a high number of scratches or defects on its surface and, therefore, is not flat.
Since no single substrate has a high degree of surface flatness and a low CTE, various solutions have been proposed to achieve the desired combination of surface flatness and CTE. In U.S. Pat. No. 6,048,652 to Nguyen et al., a reticle blank with a high degree of reflectivity and a low CTE is purportedly disclosed. The reticle blank comprises a reflective layer formed over a flat, silicon substrate. A layer of low thermal expansion material is then formed on the reflective layer to ensure that the reticle blank will have a low CTE. The flat substrate is subsequently removed, leaving the reflective layer overlying the low thermal expansion material.
In U.S. Pat. No. 6,159,643 to Levinson et al., a two-layer substrate is disclosed. A top layer of the substrate comprises silicon exhibiting the optical flatness suitable for EUV lithography. A bottom layer of the substrate comprises a low expansion glass, ceramic, or metal and has a CTE of less than 1.0 ppm/xc2x0 C.
In U.S. Pat. No. 6,011,646 to Mirkarimi et al., a method of reducing stress between a reflective, multilayer film and an optic or substrate is disclosed. A buffer layer is disposed between the multilayer film and the optic or substrate to counteract the stress in the multilayer film. The buffer layer, is asserted to prevent the stress from deforming the optic and is comprised of Mo/Si, Mo/Be, Mo2C/Si, Mo2C/Be, amorphous silicon, or amorphous carbon. The buffer layer is used in the optics of EUV lithography systems. A purported improvement to Mirkarimi et al. is disclosed in U.S. Pat. No. 6,134,049 to Spiller et al. The Spiller et al. method includes reducing the thickness of the total film by incorporating a stress-reducing layer system into the reflective, multilayer film.
In addition to the solutions discussed above, a substrate with a low CTE may also be smoothed by CMP techniques. However, CMP is expensive and increases the number of steps required to fabricate the reticle. Therefore, what is needed in the art is a less expensive method of achieving a sufficiently flat-surfaced substrate that may be used in an EUV reticle.
The present invention relates to the fabrication of a reticle or mask for use in an EUV photolithographic process. The method of fabricating the reticle comprises providing a substrate, forming a planarizing layer over the substrate, and depositing a reflective layer in contact with the planarizing layer. As used herein, the singular term xe2x80x9creflective layerxe2x80x9d includes and encompasses multiple reflective layers as employed in the art. The substrate is a low thermal expansion material that has a coefficient of thermal expansion of less than approximately 0.1 ppm/xc2x0 C., such as a low thermal expansion glass or ceramic. The planarizing layer is formed by spin-coating an anti-reflective material, a dielectric material, or a polymer onto a surface of the substrate. The planarizing layer exhibits a peak-to-valley surface flatness of approximately 20 xc3x85, thereby providing a flat surface upon which the reflective layer may be deposited.
A reticle for use in an EUV photolithographic process is also disclosed. The reticle comprises a substrate and a planarizing layer in contact with the substrate. The substrate comprises a material with a coefficient of thermal expansion of less than approximately 0.1 ppm/xc2x0 C., such as a low thermal expansion glass or glass ceramic. The planarizing layer comprises an anti-reflective material, a dielectric material, or a polymer that is spin-coated onto a surface of the substrate. The reticle also comprises a reflective layer, which in actuality may comprise multiple layers as noted above, in contact with the planarizing layer. The planarizing layer exhibits a peak-to-valley surface flatness of approximately 20 xc3x85 and provides a flat surface upon which the reflective layer may be deposited.