1. Field of the Invention
This invention relates to the fabrication of DRAMs in general, and more particularly to the fabrication of a stacked-capacitor DRAM having improved dielectric layers.
2. Description of the Prior Art
DRAM (dynamic random access memory) is one of the essential integrated memory chips that form the foundation of modern computer memories. The storage capacity of memory chips including DRAMs is indicated in bits. The bit density of DRAMs has doubled every few years, from 16 kbit chips in the 1970s to today's 16 Mbit and 64 Mbit chips. DRAMs are especially suitable for very high density (e.g. 16-256 Megabit), high speed (e.g., 35-nanosecond) applications.
Unlike non-volatile memory chips such as E.sup.2 PROMs (EEPROMS) or flash memory chips, a DRAM cell is a volatile memory device that loses the information stored in it as soon as the power supply is switched off. This unique feature is attributed to the fundamental design of a DRAM cell, which essentially comprises a transistor and a capacitor. Functionally, the capacitor is used to store electrical charges corresponding to the digital information, while the transistor provides for the switching function. The transistor is usually a metal-oxide semiconductor field effect transistor (MOSFET), and the capacitor is usually a parallel-plate capacitor (or a variation thereof). Typically, a DRAM cell is fabricated by sequentially forming a MOSFET and a capacitor on a semiconductor substrate. A contact window is made so that one of the electrodes (i.e., the storage node) of the capacitor can be electrically connected to the source of the MOSFET. This electrical connection allows a capacitor to obtain digital information from bit line and word line arrays through its corresponding MOSFET. The other electrode or node of the capacitor is electrically connected to a reference potential.
In a parallel-plate capacitor, the capacitance is given by EQU C=(.epsilon./t)A
where C is the capacitance, .epsilon. is the permittivity (i.e., the dielectric constant multiplying by the permittivity of vacuum) of the dielectric material located between the top and bottom electrodes, t is the thickness of the dielectric layer, and A is the overlapping area between the top and bottom electrodes, i.e., the surface area of the capacitor. Apparently, the capacitance of a parallel-plate capacitor may be increased by: (1) the use of a different substance having a higher dielectric constant; (2) a reduction in the thickness of the layer of the dielectric substance; and/or (3) an increase in the surface area of the capacitor.
Because most of the available space in a typical DRAM chip is taken up by the capacitors whereas its transistors utilize relative little space, many prior-art developments have focused on various geometry variations to increase the surface area of the capacitors without increasing the overall size of the chip. Such developments involve the cutting of deep trenches with large depth-to-opening aspect ratios in the dielectric layers, the use of three-dimensional stacking of capacitor layers, and the use of corrugated instead of flat surfaces.
Some progress was also made in replacing standard capacitor materials (e.g., silicon nitride) with substances having higher dielectric constants, e.g., tantalum pentoxide (Ta.sub.2 O.sub.5). Other developments include the use of polysilicon with hemispherical grains deposited at the phase transformation temperature (i.e., from amorphous to crystalline) via a chemical vapor deposition (CVD) process; see M. Sakao et al., "A Capacitor-Over-Bit-Line Cell with Hemispherical-Grain Storage Node for 64 Mb DRAMs," IEDM Tech. Dig., 1990, p. 655.; and the use of a cylindrical capacitor incorporating hemispherical grained silicon; see H. Watanabe et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si for 256 Mb DRAMs," IEDM Tech. Dig., December 1992, pp. 259-262. Further, the use of crown-shaped capacitors have also been suggested in T. Kaga et al, IEEE Trans. Electron Devices, Vol. 38, No.2, P.255, 1991. However, the fabrication of each of the above devices requires a much complicated process and is thus not economically competitive.
Furthermore, the aforesaid increase in the bit density of the DRAM chip is accompanied by a trend of shrinkage of the size of the DRAM cell, resulting in not only an increasing number of capacitors per chip but also a drastically decreasing area available for each capacitor. As the capacitor is miniaturized, its surface area and the electrical charges stored therein are also drastically reduced. As a result, more "soft errors" (errors in stored information), e.g., those caused by .varies.particles, may take place, and the capacitor must be "refreshed" more often. Thus, it is imperative that the above shrinkage in the size of the DRAM cells is not done at the expense of the ability of the capacitors to store information.
In a conventional stacked-capacitor DRAM, the dielectric material is either silicon dioxide/silicon nitride/silicon dioxide (O/N/O) or silicon nitride/silicon dioxide (N/O). For DRAMs having bit densities under 64 Megabit, an O/N/O structure having a thickness between 7 nm and 20 nm is the preferred dielectric; for DRAMs having bit densities equal to or more than 64 Megabit, a thinner N/O structure is the preferred dielectric. To form successfully a structure having N/O dielectric layers, however, the native oxide on the substrate must first be removed by, e.g., hydrofluoric acid.
As shown in FIG. 1, a polysilicon (poly-Si) layer 12 is deposited and lithographically patterned on top of a Si substrate 10. This first poly-Si layer 12 will serve as the bottom electrode of the capacitor. During the pre-cleaning before a silicon nitride layer 14 is grown, a native oxide layer 13 forms on top of the polysilicon (poly-Si) layer. This native oxide layer 13 is typically approximately 0.5 to 1 nm thick. After the nitride layer 14 is deposited, a silicon dioxide layer 16 is deposited on top of it. This is followed by the deposition of a second poly-Si layer 18 to serve as the top capacitor electrode.
The aforementioned native oxide layer 13 causes at least two major problems. First, it results in an increase in the incubation time of the nitride layer 14. Second, the nitride layer grown on top of this native layer will initially have an silicon-rich portion before the stoichiometric ratio, i.e., Si.sub.3 N.sub.4, is reached; this Si-rich portion will increase the equivalent thickness of the oxide.
Alternatively, if a CVD or PVD (physical vapor deposition) Ta.sub.2 O.sub.5 is used as the dielectric substance, an annealing process is necessary to reduce any leakage current and hydrocarbon inclusion caused by the deposition of Ta.sub.2 O.sub.5. However, because this annealing process is generally conducted in an oxygenated environment, oxygen may diffuse through the Ta.sub.2 O.sub.5 layer and react with the surface of the bottom poly-Si electrode of the capacitor, resulting in a dielectric constant less than 25. Although the aforesaid oxidation of the bottom electrode may be prevented by forming a thin silicon oxynitride (Si:O:N) layer on the surface of the bottom electrode via either a conventional high-temperature batch furnace annealing process (in NH.sub.3) or a rapid thermal nitridation (RTN) process, the latter process is a single-wafer process which would reduce the throughput of the entire DRAM fabrication process. In addition, both of the above processes may result in the possible penetration of hydrogen atoms through the bottom electrode.