The operating speed and computing power of processor devices continues to increase with each new generation of product. As a result, the ability of such processors to manipulate data can outpace the speed at which data can be provided to the processor by peripheral devices. This limitation on the rate at which data can be transmitted (the data bandwidth), can become the limiting factor in a processor system.
The data bandwidth of a processor system can be increased by expanding the size of a data bus. In the case of personal computer systems, data buses have doubled periodically over time, progressing through 8-, 16-, 32-, 64-, and 128-bit widths. Other applications also use large data buses to address the problem of bandwidth. For example, in the case of parallel computing, multiple parallel processors may employ data buses that are hundreds of bits wide.
The amount by which data buses can be expanded may be limited by the physical requirements necessary to couple integrated circuits to such data buses. Integrated circuits are manufactured in protective packages, and for each bus line, there must be a corresponding package pin to couple the bus line to the integrated circuit within. With possibly hundreds of bus lines, there may not be enough pins available on a package to meet the requirements of the system, or the system may require packages of impractical size.
One approach to increasing data bandwidth without expanding bus size is to use simultaneous bi-directional I/O circuits. In systems having simultaneous bi-directional I/O circuits, data can be transmitted and received on the same data bus line at the same time. This allows the data bandwidth to be essentially doubled without increasing the bus size.
A prior art simultaneous bi-directional I/O circuit is set forth in FIG. 1. The I/O circuit is designated by the general reference character 100, and is shown coupled to a bi-directional data bus line 102. The I/O circuit 100 drives the data bus line 102 between different voltage levels in response to a input data signal (Din) received at data input node 104. The data bus line 102 is coupled to a bond pad 106 that can be connected to a package pin. In addition, the I/O circuit 100 provides an output signal (Dout) at output node 108, in response to variations in the voltage of the data bus line 102.
The I/O circuit 100 is implemented using complementary metal-oxide-semiconductor (CMOS) technology, and includes an output buffer 110 having a driver 112 and a data input inverter I100. The driver 112 is formed from two n-channel metal-oxide-semiconductor (MOS) field effect transistors (FETs), N100 and N101, connected in series between a first high power supply voltage Vcc and a low voltage supply Vss. The Din signal is applied directly from the input node 104 as an input signal to the inverter I100 and as one input to the driver 112. The output of inverter I100 is applied as a second input to the driver 112.
When the Din signal at input node 104 is at a logic high level, transistor N100 is in a conducting state, and a logic high voltage level will applied to the bond pad 106 via data bus line 102. The high Din signal will be inverted by inverter I100, and a logic low will be applied to the gate of transistor N101, and transistor N101 will be in a non-conducting state. When the Din signal at input node 104 is at a logic low level, transistor N100 is in a non-conducting state, and inverter I100 will apply a logic high to the gate of transistor N101, and transistor N101 will be in a conducting state. A logic low will be applied to the bond pad 106 via data bus line 102. In this manner, the data bus line 102 is driven according to the logic values of the Din signal applied at input node 104.
The I/O circuit 100 further includes an input buffer 114 formed by a differential amplifier 116, a multiplexer (MUX) 118, and an output inverter I101. The differential amplifier 116 includes a current source p-channel MOSFET, having a source coupled to a second high power supply voltage Vdd, a gate coupled to Vss, and a drain coupled to a differential pair, formed by p-channel MOSFETs P101 and P102. The sources of the P101 and P102 are commonly coupled to the drain of P100. The gate of P101 is coupled to a reference node 120, which receives one of two reference voltages (Vref1 or Vref2). The gate of P102 is coupled to the data bus line 102. The drains of P101 and P102 are coupled to the drains of two n-channel MOSFETs N102 and N103, which form a current mirror. Transistors N102 and N103 have commonly coupled gates, with the gate of transistor N102 being coupled to its drain. The sources of transistors N102 and N103 are commonly coupled to Vss.
The reference voltage (either Vref1 or Vref2) received by the reference node 120 is determined by the operation of the MUX 118. The MUX 118 receives the Vref1 and Vref2 potential, and couples one or the other to the reference node 120 depending upon the logic level of the Din signal applied at data input node 104 (and as inverted by inverter I100). For example, when Din is a logic high, the reference node 120 is at the Vref2 voltage, and when Din is a logic low, the reference node 120 is at the Vref1 voltage.
The voltage level at which the differential amplifier 116 provides a logic high or logic low output depends upon the potential of the reference node 120. The differential amplifier 116 compares the voltage at the data bus line 102, with the voltage at the reference node 120 (the reference voltage). If the reference voltage (Vref1 or Vref2) is higher than the voltage level of the data bus line 102, the differential amplifier 106 will drive an output line 122 to a logic high level, and data output node 108 will be driven to a logic low level by output inverter I101. Conversely, if the reference voltage (Vref1 or Vref2) is lower than the voltage of the data bus line 102, the differential amplifier 116 will drive the output line 122 to a logic low level, and data output node 108 will be driven to a high logic level by inverter I101. In this manner the input buffer 114 will detect the voltage on the data bus line 102 and drive the output node 108 according to one of two voltage levels (Vref1 or Vref2).
FIG. 2A illustrates a prior art data transmission system 200, that includes first and second bi-directional I/O circuits, shown as 202a and 202b, respectively. The I/O circuits (202a and 202b) are identical to that set forth in FIG. 1, and commonly share a system bus line, DBUS 204. The inherent capacitance of the DBUS line 204 is shown as capacitance C100. The first I/O circuit 202a is shown to include a first output buffer 206a and a first input buffer 208a. The second I/O circuit 202b includes a second output buffer 206b and a second input buffer 208b.
The first I/O circuit 202a drives the DBUS line 204 according to a first data input signal (Din1) at a first data input node 210a, and drives a first output node 212a in response to the DBUS line 204 being driven by the second I/O circuit 202b. In a similar manner, the second I/O circuit 202b drives the DBUS line 204 in response to a second data input signal (Din2) at second data input node 210b, and drives a second output node 212b in response to the DBUS line 204 being driven by the first I/O circuit 202a.
The operation of the data transmission system 200 is best understood with reference to FIG. 2A in conjunction with FIG. 2B. FIG. 2B is a timing diagram setting forth the response of the DBUS line 204, and the data output signals Dout1 and Dout2, according to various transitions in the logic levels of the Din1 and Din2 signals. At time t0, Din1 is at a logic low voltage, and Din2 is at a logic high voltage. The first output buffer 206a in the first I/O circuit 202a, will drive the DBUS line 204 high (Vcc). In contrast, the second output buffer 206b will drive the DBUS line 204 low (Vss). Consequently, the DBUS line 204 will be at a voltage intermediate to Vcc and Vss, shown in FIG. 2B as Vmid.
Referring now to FIG. 2A in conjunction with FIG. 1, it is recalled that if the input signal Din is low, the reference voltage Vref1 will be applied to the differential amplifier 116. The reference voltage Vref1 is selected to be less than Vmid, but greater than Vss. Accordingly, with Vref1 less than the voltage at data bus line 102 (Vmid), the output line 122 will be pulled low, and Dout will be driven to a high logic level. Thus, referring back to FIG. 2A, when Din1 is low and Din2 is high, the DBUS line will be at a voltage level higher than the reference level within first I/O circuit 202a, and the first output signal Dout1 is high. In this manner the first input buffer 208a detects the logic high of the Din2 signal.
In the case of the second I/O circuit 202b, the high Din2 signal will result in the differential amplifier 116 within the second I/O circuit 202b receiving the Vref2 voltage as a reference voltage. Vref2 is selected to be greater than Vmid and less than Vcc. As a result, the second output signal Dout2 will be driven low. Thus, the second input buffer 208b detects the low Din1 signal.
At time t1, Din1 makes a transition from a low logic level to a high logic level. Din2 remains at a logic high level. Referring once again to FIG. 1, when Din makes the low-to-high transition, the MUX 118 will switch from passing Vref1 as the reference voltage, to passing Vref2 as the reference voltage. The gate voltage at transistor P101 will thus transition from Vref1 to Vref2. Simultaneously, the data bus line 102 (which is coupled to the DBUS line 204 in the arrangement of FIG. 2A) will transition from a logic low level to a logic high level. Since the system data bus line DBUS 204 is more capacitively loaded than the reference node 120 within the first I/O circuit 202a, the reference voltage applied to the differential amplifier 116 will switch from Vref1 to Vref2 more quickly than the DBUS line 204 (and consequently the internal data bus line 102) can transition from a logic low level to a logic high level. Accordingly, as set forth in FIG. 2B, while Din1 goes high at time t1, the DBUS line 204 will not go high in response, until time t2.
The delay between the Din1 logic transition and the DBUS line 204 response results in the differential amplifier 118 within I/O circuit 202a reading the DBUS line 204 as a logic low level input signal, even though the logic level of Din2 has not changed. As a result, the Dout1 signal will go low at time t1. When data bus DBUS line 204 reaches the logic high level (above Vref2) at time t2, the differential amplifier 118 within the first I/O circuit 202a will read the correct logic level, and the Dout1 signal will be driven to the logic high level. This dip (glitch) in the Dout1 signal between times t1 and t2 is undesirable.
While the waveforms between times t0 and t2 of FIG. 2A illustrate a low-going glitch that results when one I/O circuit (202b) receives a high input signal (Din2) while the other I/O circuit (202a) receives a low-to-high transition (Din1), a similar adverse effect occurs when one I/O circuit receives a low input signal, while the other input circuit receives a high-to-low transition. This case is illustrated by the waveforms between times t3 and t4.
At time t3, the Din1 signal is low, and the Din2 signal transitions from high to low. The output buffer 206b within the second I/O circuit 202b, begins to drive the DBUS line 204 to a low logic level. At the same, the reference voltage received by MUX 118 within the second I/O circuit 202b changes from Vref2 to Vref1. The same factors giving rise to the low-going glitch in Dout1 result in a high going-glitch in Dout2. The capacitive load presented by DBUS line 204 is greater than that of the reference node 120 within the second I/O circuit 202b, and the DBUS line 204 is not driven low until time t4. Between times t3 and t4, the reference voltage is at Vref1 (Vmid&gt;Vref1&gt;Vss) while the DBUS line 204 is between Vmid and Vref1. As a result, the Dout2 signal will erroneously go high. At time t4, the DBUS line 204 goes lower than Vref1, and Dout2 returns to the proper low logic level.
It would be desirable to provide a simultaneous bi-directional I/O circuit that does not produce the output signal glitches such as those present in the prior art. It also desirable to provide a bi-directional I/O circuit having reduced current consumption.