1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly to a multilayer chip capacitor, which has a low equivalent serial inductance (ESL) in a high frequency circuit.
2. Description of the Related Art
Generally, multilayer chip capacitors have a small size, achieve high capacitance, and are easily mounted on a substrate, thus being widely used in various electronic apparatuses. Multilayer chip capacitors are used as capacitive components of high frequency circuits, particularly as decoupling capacitors arranged in power supply circuits of LSI. In order to use a multilayer chip capacitor in a high-frequency circuit, the multilayer chip capacitor must have a low ESL value. The above requirement is increased according to high frequency and high current trends of electronic apparatuses.
U.S. Pat. No. 5,880,925 proposes that respective lead structures of first internal electrodes are located adjacent respective lead structures of second internal electrodes in an interdigitated arrangement to reduce the ESL of the multilayer chip capacitor. The above arrangement is shown in FIG. 1a. 
FIG. 1a is an exploded perspective view illustrating shapes of internal electrodes of a conventional multilayer chip capacitor. FIG. 1b is a schematic perspective view of the conventional multilayer chip capacitor manufactured using the internal electrodes of FIG. 1a. FIG. 1c is a sectional view of the multilayer chip capacitor of FIG. 1b as taken along the line X–X′. With reference to FIG. 1a, internal electrodes 14 are formed on a plurality of dielectric layers 11a and 11b made of ceramic. The internal electrodes 14 are divided into first internal electrodes 12 and second internal electrodes 13 having different polarities. Leads 16 of the first internal electrodes 12 and leads 17 of the second internal electrodes 13 are connected to respective ones of external electrodes 18 (in FIG. 1b). The leads 16 of the first internal electrodes 12 are located adjacent the leads 17 of the second internal electrodes 13 in an interdigitated arrangement. Since the polarities of the voltages supplied to the nearby leads differ, the magnetic fluxes generated due to the high frequency currents flowing from the external electrodes are canceled out between theses adjoining leads. Therefore, the ESL is reduced. However, such reduced amount of the ESL does not satisfy the level required for the decoupling capacitors for high frequency circuit.
As shown in FIGS. 1b and 1c, in the conventional multilayer chip capacitor 10, the internal electrodes 14 are located at the central portion of the capacitor main body 20 such that a cross section of a capacitor main body 20 has a lower-upper symmetrical structure with regard to a central line (L). That is, the capacitor main body 20 includes a lower dummy layer 51, an upper dummy layer 52 and an active layer 50 between the lower and the upper dummy layers 51 and 52. The lower and the upper layers 51 and 52 have the same thickness (a). The active layer 50 has a plurality of the internal electrodes 14. As shown in FIG. 1a, the dielectric layers 11a and 11b are interposed between the internal electrodes 14. The dummy layers 51 and 52 correspond to the regions without internal electrodes which substantially contribute to capacitance. On the contrary, the active layer 50 corresponds to the region with internal electrodes which substantially contribute to capacitance. The dummy layers 51 and 52 serve to protect the internal electrodes 14 and to assure a designated thickness of the multilayer chip capacitor 10. The lower and upper dummy layers 51 and 52 are made of the same material as that of the dielectric layers 11a and 11b. 
When the internal electrodes 14 are located at the central portion of the capacitor main body 20, a distance (a) from the bottom surface (the surface attached to a pad of a substrate) of the multilayer chip capacitor 10 mounted on a substrate to the lowermost internal electrode 14 is elongated. That is, the thickness (a) of the lower dummy layer 51 is comparatively increased by locating the internal electrodes 14 at the central portion of the capacitor main body 20. When the thickness (a) of the lower dummy layer 51 is increased, the ESL component generated due to current flowing through the external electrodes 18 from the bottom surface is increased. Particularly, in a multilayer chip capacitor with multi-terminals more than 2 terminals, the above ESL component occupies a considerable portion of the overall ESL of the multilayer chip capacitor.
FIG. 1d is a sectional view of the multilayer chip capacitor of FIG. 1b as taken along the line A–A′. FIG. 1e is a schematic view showing a model of the equivalent serial inductance of the mutilayer chip capacitor of FIG. 1d. As shown in FIG. 1e, the conventional mutilayer chip capacitor 10 has the inductance (Lh) in the region H and the inductances (Lv) in the regions V1 and V2. Thus, the total inductance of the multiplayer chip capacitor is Lh+2Lv. Therefore, as the thickness (a) of the lower dummy layer 51 is increase, the ESL of the capacitor is increase.
Additionally, in the conventional multiplayer chip capacitor 10, each of the internal electrodes 14 has four leads, resulting in smaller ESR (equivalent serial resistance). When each of internal electrodes 12 or 13 has four leads as shown in FIG. 1a, the resistances generated from the leads are parallel connected. As a result, the total resistance of the capacitor 10 becomes extremely small. If the ESR is extremely small, it is hard to meet the target impedance and impossible to design power distribution network stably.
In order to prevent the ESR from reducing extremely, U.S. Pat. No. 6,441,459 proposes that each of internal electrodes has one lead to increase to the ESR. However, according to the U.S. Patent, the ESL is increased, and the ESR is not controllable.
In order to solve the problems of the increase in the ESL component, as shown in FIG. 2, a lower dummy layer 51′ and an upper dummy layer 52′ may have a reduced thickness (b′), thus resulting in a thin multilayer chip capacitor. However, when the multilayer chip capacitor is excessively thin, the mechanical strength of the multilayer chip capacitor is decreased. For example, when the multilayer chip capacitor is designed to have a thickness of less than 0.3 mm, the capacitor is easily broken or damaged during the manufacturing process thereof, thus deteriorating a production yield of chip capacitors. Particularly, the above mechanical damage of the capacitor is highly generated when the capacitor main body is polished after sintering or when the manufactured multilayer chip capacitor is mounted on a substrate.