Advanced digital Integrated Circuit (IC) devices often have a low voltage logic core and relatively higher voltage Input/Output (IO) logic for interface with external components on a printed circuit board. As a result, voltage level translation circuits to translate from the low voltage domain to a high voltage domain are common and many such devices may be needed on an IC. Therefore, a logic level shifter that consumes minimum power and minimum die area while introducing minimum delay in the digital signal path is valuable to a very wide range of digital circuit applications including LCD panels, cell phones, MP3 players, microprocessors, memories, and many more devices.
Level shift circuits (also referred to herein as level shifters) change the voltage level of a signal between an input and an output. For example, when an output voltage of a first circuit differs from an operating voltage range of a second circuit, a level shifter may be arranged between the first circuit and the second circuit, and the voltage level of the signal between the first and second circuits may be adjusted.
FIG. 1 illustrates a schematic diagram of a conventional level shift circuit 100. Conventional level shift circuit 100 includes n-channel transistors Q1 and Q2 and p-channel transistors Q3 and Q4. A primary input (Vin) 140 is inverted by inverter 145 to drive a gate of n-channel transistor Q1 with an inverted input signal 150. The inverted input signal 150 drives a second inverter 155 to generate an input signal 160, which drives a gate of the n-channel transistor Q2. An inverted output signal (Vout) 180 is driven by the inverter combination of p-channel transistor Q4 and n-channel transistor Q2. An output signal (Vout) 190 is driven by the inverter combination of p-channel transistor Q3 and n-channel transistor Q1. The output signal 190 and inverted output signal 180 are cross-coupled to assist in making the voltage transitions on the two outputs.
In this conventional level shift circuit 100, the primary input 140 and the two inverters (145 and 155) operate between a ground 130 and a low supply voltage (Vdd) 120. The cross-coupled inverters of transistors Q1, Q3, Q2, and Q4 operate at a high supply voltage (Vcc) 110.
In operation, when the primary input 140 transitions from a low to a high of the low supply voltage 120, the inverted input signal 150 transitions from a high to a low, which turns off n-channel transistor Q1. The input signal 160 transitions from a low to a high, which turns on n-channel transistor Q2. As a result, n-channel transistor Q2 begins pulling the inverted output signal 180 low. However, p-channel transistor Q4 is also on at this time causing a fight between n-channel transistor Q2 and p-channel transistor Q4. This fight, when both transistors of an inverter are on, is often referred to as “shoot-through current” because current can flow through the inverter directly from the high supply voltage 110 to ground 130 in addition to supplying current to charge the inverted output signal 180.
As the inverted output signal 180 begins going low, p-channel transistor Q3 will turn on. N-channel transistor Q1 is now turned off so p-channel transistor Q3 can pull the output signal 190 high. As the output signal 190 goes high, p-channel transistor Q4 is turned off releasing the fight between p-channel transistor Q4 and n-channel transistor Q2. As a result, n-channel transistor Q2 can now easily pull the inverted output signal 180 the rest of the way low. Operation in the opposite direction (i.e., when the primary input 140 transitions from a high to a low) is similar except the shoot-through current occurs between p-channel transistor Q3 and n-channel transistor Q1.
Reduction of the shoot-through current is the subject of many modifications to the basic conventional level shifter, e.g., in an effort to reduce power and reduce propagation delays from a primary input to an output signal and an inverted output signal. As one such example, see U.S. Patent Application No. 2008/0238523. However, most proposals add additional circuitry and complexity in an effort reduce power or reduce propagation delays.
Other, less complex solutions are desirable. The inventor has appreciated that there exists a need for a level shifter that can reduce delays, reduce circuit complexity, reduce overall die size, or combinations thereof