(1) Field of the Invention
The invention relates to an input buffer circuit, and, more particularly, to a circuit to independently adjust rise and fall edge timing of a signal.
(2) Description of the Prior Art
Signal conditioning must be performed on most inputs to an integrated circuit device. Referring to FIG. 1 an example of an IC device 10 is shown. In this very simplified system, an input, SIGNAL 14, appears at an external pin of the device 10. An input circuit, or input buffer circuit, resides in the IC device 10 as the series of inverters I122 and I226. The internal signal, SIGNAL_IC 18, is generated by the input signal SIGNAL 14.
Each of the inverters 22 and 26 comprise transistor devices. These transistor devices, not shown, require a finite time for switching states. This switching time is usually called a delay time, or an edge delay time. The timing diagram of FIG. 1 shows some typical waveforms for SIGNAL 14 and SIGNAL_OUT 18. A transition of SIGNAL 14 from low to high creates a rising edge. SIGNAL_OUT 18 follows this rising edge with a similar rising edge transition. The time delay between the rising edge of SIGNAL 14 and the rising edge of SIGNAL_OUT 18 is defined as the rising edge time delay (Tr) for circuit. Similarly, the falling edge time delay is shown by Tf.
In many applications of an input circuit, the edge timing delays are a critical parameter. More particularly, in systems such as asynchronous devices or double data rate (DDR) DRAM devices, critical device operation is timed from edge transitions. This means that the edge delay for rising and falling edges needs to be carefully controlled. An even more important consideration to the present invention is the need to control the rising edge delay Tr and the falling edge delay Tt independently. The prior art buffer circuit shown is not well suited for providing independent edge delay control. Methods to tailor the edge delay of this simple inverter circuit are known in the art. However, such methods do not allow the rising and falling edge delays to be independently altered. For example, attempts to increase the falling edge delay either will cause a decrease in the rising edge delay or will cause an increase in the rising edge delay that mirrors that for the falling edge delay.
Several prior art inventions relate to methods and circuits for input buffering and edge delay. U.S. Pat. No. 6,294,939 to McClure describes a method and a circuit for data input buffering. Separate paths for rising edge and for falling edge propagation are shown. However, the circuit is designed to filter out noise from the data input, and the rise and fall delays are designed to be substantially the same. U.S. Pat. No. 6,313,681 to Yoshikawa discloses a variable delay circuit. A delay element comprising a comparitor is used in each of the positive and the negative delay paths. U.S. Pat. No. 6,069,511 to Mohan teaches a method and circuit to control signal rise/fall times using slew rate.