1. Field of the Invention
This invention relates to timers with storage devices, circuitry to evaluate the value stored in the devices and more specifically, to counters with circuitry to determine when the counter has decremented to a 0 value.
2. Description of the Prior Art
Timers have been used in computer circuits for some time. The purpose of a timer is to determine the amount of time required to perform specific tasks in the computer. Another purpose for a timer is to prevent an excessive amount of time from being spent either while performing a task or awaiting for an event to occur. Timers for these purposes are called watchdog timers. The common mode of operation of watchdog timers is to load a set value into the counter and decrement this value according to some computer clock signal. If the counter decrements the initially loaded value to a 0 value, then an interrupt is generated by the timer circuitry. Therefore, if a computer is waiting for a certain event to occur and loads the watchdog timer with a set timer value in which the event is to occur, the timer will generate an interrupt when the specified time expires and the event does not occur.
An example of a timer or counter used in a computer circuitry is disclosed in U.S. patent application Ser. No. 253,643 filed 4/13/81 which is herein incorporated by reference. A diagram of a common counter is illustrated in FIG. 1. The initial value is loaded from the data bus into a latch which is, in turn, loaded into a counter circuit. The counter circuit will then decrement the initial value. When the counter value reaches a certain point, the evaluation circuitry connected to the counter circuit will initiate an interrupt. FIG. 2a illustrates the prior art evaluation circuitry for a 4 bit counter. The value in the Bit 0 Counter is loaded into NOR gate 10 by a line 1 where is is NORed with the value in Bit 1 Counter via line 2. The output of the NOR gate 10 is coupled to the inverter 11 via line 3 which is in turn coupled to NOR gate 12 via line 4. The other input to NOR gate 12, line 5, is coupled from the Bit 2 Counter. The output of NOR gate 12 on line 6 is coupled to inverter 7; the output of the inverter 7 is coupled to one of the two inputs for NOR gate 14; the second input for NOR gate 14 is coupled by line 8 to the Bit 3 Counter. The output of NOR gate 14 is on line 9 and becomes active when all bit counter values are 0. The transistor schematic of the evaluation circuit shown in FIG. 2a is illustrated in FIG. 2b. NOR gate 10 is shown to consist of a power source provided to the circuitry at point 15, a precharge device 16 connected to a precharge clock, an isolation device 16 connected to a precharge clock, an isolation device 17 connected to an isolation clock .phi.1, and two inputs, lines 1 and lines 2, provided to devices 18 and 19, respectively. Note that this is the standard dynamic circuit NOR gate. The output of this NOR gate line 3 is provided to inverter 11 which includes the power source at point 20 to precharge device 21 to precharge node 24 during .phi.P2. Also provided is isolation device 22, clocked by .phi.2 with an input device 23 receiving its input on line 3. The inverter 11 output, line 4, is connected to NOR gate 12 which is similar to NOR gate 10. Likewise, the inverter 13 is similar to inverter 11 and NOR gate 14 is similar to NOR gates 12 and 10. The output of NOR gate 14 is line 9.
Referring to the truth table in FIG. 2c, if any of the bit positions in the bit counters 0 through 3 contain a 1, the output on line 9 will be a 0. However, if a 0 value exists in all four bit counter locations, a 1 will be output by the evaluation circuit on line 9.
Two problems exist with this type of evaluation circuitry. The first is that when the circuit is implemented in dynamic logic, a large number of transistor devices are required. The second is that several cycles are required for the values of the bit counters to clock through the serially connected logic as shown in FIG. 2a. In FIG. 2b, the value of NOR gate 10 is evaluated by the inverter 11 at a later precharge and isolation clock time. Therefore, several clocking cycles are required by the circuitry in order to clock the values through the NOR gate inverter evaluation circuit and to produce a valid output on line 9. It is an object of this invention to provide a timer that requires a smaller number of transistor devices while also providing a simultaneous evaluation of all bit counter values.