The invention relates to a logic circuit arrangement suitable for short switching times, for large-scale integration with high component density, and for operation as a power supply with only one polarity of a supply voltage. A field effect transistor is provided in one stage whose drain is direct coupled to a gate of a field effect transistor of a following stage.
Logic circuit arrangements of which a plurality of demands are made are used for digital and analog data processing. On the one hand, such a logic circuit should be realizable with high component density, i.e. for very large-scale integrated circuits (VLSI). Such a circuit should have a high processing speed. Transistors of the silicon bipolar technology, silicon MOS technology and/or transistors of compound semiconductor material such as, for example, MESFET and/or MISFET components, are employed for such circuits.
In addition to the aforementioned component density and the required high switching time, further demands are also made. Specifically, high driver strength, low dissipated power, high signal-to-noise ratio, and/or small differences of the value of the threshold voltage for a plurality of such components integrated on one chip are required. Specifically for analog circuits, the output power, the ratio between radio-frequency (rf) power and power (DC) consumption, and the noise figure play a part.
As an example of such a circuit (known per se), FIG. 1 shows a circuit comprising a NOR gate and a following inverter stage. This circuit is operated with a supply voltage V.sub.DD. The desire is that such a circuit be operable with electrical voltage of only one polarity, both with respect to the supply voltage, as well as the drive voltages for the elements to be provided.
For the present invention, field effect transistors of the normally-off type are important, i.e. of the enhancement type, and that are non-conducting without gate voltage. By applying positive gate voltages V.sub.e1, V.sub.e2, these transistors are switched on or the transistor of the inverter stage becomes inhibiting due to the corresponding reduction of the potential V.sub.a1.
Various such types are available as normally-off field effect transistors.
A gallium arsenide field effect transistor having an extremely thin, active gallium arsenide layer (about 50 nm thick) is known. Details thereof can be found in "1979 GaAs IC Symposium, Lake Tahoe, Sept. 1979". Such a field effect transistor is inhibiting without adjacent gate voltage and becomes conductive with gate voltage. Problems with such field effect transistors result in conjunction with integration because such low thickness of the active layer is difficult to observe over a larger chip area within those limits that are acceptable in view of compensatable fluctuations of the threshold voltage value. A further disadvantage is the unfavorable working range in the non-saturated part of the family of characteristics at low operating voltages, as a consequence whereof the steepness and high switching speed desired for a circuit of the invention would not be obtainable here.
Junction field effect transistors are also known, these comprising a pn diode instead of the Schottky diode, and their logical voltage boost being elevated by a few tenths of a volt. High edge capacitance of the p-region, however, leads to great switching delays.
Insulated gate field effect transistors (MISFET) are also known, the thin insulating layer of these below the Schottky gate serving the purpose of avoiding the high conducting state currents of the Schottky gate which appear given an applied positive gate voltage. A thickness of the insulating layer that is not exactly observed produces fluctuations in the threshold current value that are too great.
A further, known field effect transistor of the normally-off type is the HEMT transistor comprising an extremely thin (50 nm) layer of highly doped gallium aluminum arsenide under the Schottky gate and comprising an intentionally undoped, active gallium arsenide layer.
Realizing a logic circuit with direct coupling of successive transistors according, for example, to FIG. 1 with normally-off transistors of the above types leads to the problems that have already been shown.
For the sake of completeness, logic circuits with normally-on field effect transistors shall also be mentioned. Particularly belonging thereto are depletion MESFET field effect transistors. These, for example, have a 150 nm thick active layer of, for example, gallium arsenide on an electrically insulating substrate or, for example, preferably semi-insulating gallium arsenide. As a consequence of their greater layer thickness, such transistors in integrated circuits have relatively slight differences from one another with respect to the threshold voltage value. They also have a relatively short switching time and high reliability against disturbance. Their essential disadvantage, however, is that they require a gate voltage opposite the supply voltage V.sub.DD in order to be switched non-conductive. This induces an additional voltage supply. Additional switching delays and dissipated power thus also arise.