1. Field of the Invention
This invention relates to a rectifier circuit for rectifying an alternating current signal on a full-wave or half-wave basis and more particularly, to a rectifier circuit which is adapted to be made of metal-oxide semiconductor (MOS) integrated circuits and does not use a clock signal.
2. Description of the Related Art
As a rectifier circuit realized on MOS integrated circuits, such as shown in FIG. 1 is known previously. The rectifier circuit shown in FIG. 1 utilizes a switched capacitor (SC) multiplication circuit (see "Design and Application of SC Circuit", Section 3.1, by Kenji Nakayama published by Tokai University Publication Division).
The circuit shown in FIG. 1 comprises an input terminal 1, an output terminal 2, an SC circuit 3, a comparator 4, a D-type flip-flop block 5, a capacitor C1, switches S1, S2, S3 and S4 and selective switches S5 and S6. The SC circuit 3 comprises an operation amplifier A31, capacitors C31 and C32 and switches S31, S32, S34 and S35. Then, .phi.1 and .phi.2 indicate clock signals.
The switches S1, S2, S3, S4, S31, S32, S33, S34 and S35 are controllably switched by the clock signal .phi.1 or .phi.2 respectively inputted, and when the clock signal .phi.1 or .phi.2 is of a high logic level (logic level "1"), they are closed and when it is of a low logic level (logic level "0"), they are opened.
The clock signals .phi.1 and .phi.2 each is a clock signal having a frequency as high as several ten times that of an alternating current signal applied to the input terminal 1 and when the clock signal .phi.1 is "1", the clock signal .phi.2 is "0" and when the clock signal .phi.2 is "1", the clock signal .phi.1 is "0", having a clock phase at which the clock signals .phi.1 and .phi.2 simultaneously become the logic level "0".
An alternating current signal applied to the input terminal 1 is sent through the switch S1 and the capacitor C1 to the negative side-input terminal of the comparator 4. The positive side-input terminal of the comparator 4 is connected to the ground. When the clock signal .phi.1 is "1", the switch S1 is closed thereby charging the capacitor C1 by the alternating current signal. At that time, the clock signal .phi.2 becomes "0" to make switch S4 open and as a result, the output signal of the comparator 4 is not applied to the input terminal D of the flip-flop block 5.
When the clock signal .phi.2 is "1", the switches S2 and S4 are closed and as a result, the electric charge stored in the capacitor C1 is discharged and the output signal of the comparator 4 at that time is applied to the input terminal D of the flip-flop block 5.
When the clock signal .phi.2 is "1", if the alternating current signal is of the "positive polarity", the output signal of the comparator 4 becomes "1", and if is of the "negative polarity", the output of the comparator becomes "0". Besides, the switch S4 and the flip-flop block 5 make a sample-hold circuit and as a result, the output signal of the flip-flop block 5 becomes "1" while the alternating current signal has the positive polarity and becomes "0" while it has the negative polarity, and the output signal Q (inverted signal of an output signal Q outputted from an output terminal Q) becomes the logic level opposite thereto.
The selective switch 5 is controlled by the output signal Q outputted from the output terminal Q and the switch S6 is controlled by the inverted output signal Q of the flip-flop block 5, thereby selectively outputting the clock signal .phi.1 or .phi.2 from the output terminals Q and Q. Namely, the selective switch S5 outputs the clock signal .phi.1 while the alternating current signal is being the positive polarity and outputs the clock signal .phi.2 while it has the negative polarity. Inversely, the selective switch S6 outputs the clock signal .phi.1 while the alternating current signal has the positive polarity and outputs the clock signal .phi.1 while it has the negative polarity.
The clock signal .phi.1 or .phi.2 outputted from the selective switch S5 controls the switch 31 of the SC multiplication circuit 3 and on the other hand, the clock signal .phi.2 or .phi.1 outputted from the selective switch S6 controls the switch S32 of the SC multiplication circuit 3. When the switch S31 is controllably switched by the clock signal .phi.1 and the switch S32 is controllably switched by the clock signal .phi.2, the SC multiplication circuit 3 executes the "positive-phase multiplying operation". Namely, when the input voltage from the input terminal 1 is expressed as VIN, the output signal from the output terminal 2 is expressed as VOUT and the capacity of the capacitor C32 is supposed to be set as high as K' times that of the capacitor C31, the output voltage VOUT may be expressed as follows: EQU VOUT=K'.multidot.VIN
On the other hand, when the switch S31 is controllably switched by the clock signal .phi.2 and the switch S32 is controllably switched by the clock signal .phi.1, the SC multiplication circuit 3 executes the "negative-phase multiplying operation" and the output signal VOUT may be expressed as follows; EQU VOUT=-K'.multidot.VIN
As a result, when an alternating current signal applied to the input terminal 1 is of the positive polarity, the output terminal 2 outputs a positive-phase signal having an amplitude K' times that of the alternating current signal and, on the other hand, when the alternating current signal is of the negative polarity, the output terminal 2 outputs an opposite-phase signal having an amplitude K' times that of the alternating current signal. Thus, such a signal that the inputted alternating current signal is full-wave rectified can be obtained.
In the circuit shown in FIG. 1, a switch is disposed between the input terminal 1 and the SC multiplication circuit 3, and when the alternating current signal is being the positive polarity, the switch thus disposed is closed to send the alternating current signal to the SC multiplication circuit 3 and on the other hand, when it is being the negative polarity, the switch thus disposed is made open not to send the alternating current signal to the SC multiplication circuit 3, thus such a signal may be obtained that the inputted alternating current signal is half-wave rectified.
With the conventional rectifier circuit shown above, however, as the clock signal is used, there arises such a problem that a rectified signal having a good signal-to-noise (S/N) ratio cannot be obtained influenced by the generation of clock noise. In addition, the circuit itself is complex in structure and large in scale and unavoidably large in chip-size and power consumption when to make it of MOS integrated circuits.
Thus, an object of this invention is to provide a rectifier circuit without using a clock signal.
Another object of this invention is to provide a rectifier circuit realizable with MOS integrated circuits which are small in circuit-scale.