Chemical mechanical polishing (CMP) is generally known in the art. For example U.S. Pat. No. 5,177,908 issued to Tuttle in 1993 describes a finishing element for semiconductor wafers, having a face shaped to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer in order to effect improved planarity of the workpiece. U.S. Pat. No. 5,234,867 to Schultz et al. issued in 1993 describes an apparatus for planarizing semiconductor wafers which in a preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen and a non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. Fixed abrasive finishing elements are known for polishing. Illustrative examples include U.S. Pat. No. 4,966,245 to Callinan, U.S. Pat. No. 5,823,855 to Robinson, and WO 98/06541 to Rutherford.
An objective of polishing of semiconductor layers is to make the semiconductor layers as nearly perfect as possible. Current finishing elements can suffer from being costly to manufacture. Also current finishing elements for semiconductor wafers have relatively homogenous surfaces which inherently limits their versatility in some demanding finishing applications. Still further, current finishing elements do not have built into their construction a local region of material on their surface which can help reinforce them, prolong their useful life, and also improve finishing performance while also improving manufacturability and versatility. Still further, lack of a continuous phase matrix on their surface can reduce the flexibility to add finishing enhancers. Still further, a lack of the above characteristics in a finishing element reduces the versatility of the finishing method which can be employed for semiconductor wafer surface finishing. Still further, current finishing pads are limited in the way they apply pressure to the abrasives and in turn against the semiconductor wafer surface being finished. These unwanted effects are particularly important and can be deleterious to yield and cost of manufacture when manufacturing electronic wafers which require extremely close tolerances in required planarity and feature sizes.
It is an advantage of this invention to improve the finishing method for semiconductor wafer surfaces to make them as perfect as possible. It is an advantage of this invention to make finishing elements with a lower cost of manufacture and thus also reduce the cost of finishing a semiconductor wafer surface. It is an advantage of this invention develop a heterogeneous finishing element surface having local regions which improve versatility of the finishing elements and the methods of finishing semiconductor wafers which result. It is also an advantage of the invention to develop finishing element having local regions reinforced with a continuous phase material. It is further an advantage of the invention to develop a finishing element having local regions for including finishing enhancers such as finishing aids. It is further an advantage of the invention to develop an finishing element with a new method of cooperating between its elements to improve die planarity, global planarity, and finishing performance. It is an advantage of the invention to develop a finishing element which has a unique way of applying pressure to the unitary discrete finishing member and to the workpiece surface being finished. It is further an advantage of this invention to help improve yield and lower the cost of manufacture for finishing of workpieces having extremely close tolerances such as semiconductor wafers.
These and other advantages of the invention will become readily apparent to those of ordinary skill in the art after reading the following disclosure of the invention.