As semiconductor devices have become highly integrated, the line width and spaces of the various patterns for devices has been reduced. This is especially true with regard to the design rule of the gate of transistor, which has become so highly integrated that the gate length has been shortened.
Conventionally, to reduce the delay time of the signal, low resistivity materials are widely used. In particular, there has been much research and development regarding the use of silicide material for reducing the sheet and contact resistance of the gate and source/drain of transistors.
In the conventional silicide process, firstly lightly doped drain (LDD) and source/drain regions formed on a silicon substrate and silicide reactive material such as nickel (Ni), cobalt (Co), Platinum (Pt), titanium (Ti) and etc. are sputtered and annealed, for reducing the resistance of the source/drain regions and the gate, such that the sputtered material reacts with the silicon (Si) on the surface of the source/drain and gate, whereby the silicide layer is formed on the source/drain and gate.
In the conventional method, however, the silicon on the source/drain and gate is consumed for forming the silicide layer, which can cause junction leakage. That is, the silicon consumption allows the dopant to spread into the junction as the silicide layer is formed, so as to change the distribution of the junction, resulting in the junction leakage. Also, the low dopant concentration on the surface of the silicide layer caused by the spread of the dopant increases the contact resistance.
Accordingly, it is required to develop a technique for protecting the junction leakage caused by the consumption of the silicon on the source/drain and gate surfaces.
U.S. Pat. Nos. 5,872,039 and 5,627,097 have disclosed methods for reducing the spread region of the source/drain region by forming an epitaxial layer on the device region and forming a channel region using the epitaxial layer, respectively.