Integration of digital, analog, radio frequency, photonic and other devices into a complex System-on-Chip (“SOC”) has been previously demonstrated. (See, e.g., Reference 1). Recently, for example, sensors, actuators and biochips are also being integrated, into these already powerful SOCs. SOC integration has been enabled by advances in mixed system integration and the increase in the wafer sizes (e.g., currently about 300 mm and projected to be 450 mm by 2018) (see, e.g., Reference 1), and it has also reduced the cost per chip of such SOCs. However, support for multiple capabilities, and mixed technologies, have increased the cost of owning an advanced foundry. For instance, the cost of owning a foundry will be approximately $5 billion in 2015. (See, e.g., Reference 2). Consequently, only advanced commercial foundries can now manufacture such high performance, mixed system, SOCs especially at the advanced technology nodes. (See, e.g., Reference 3). Absent the economies of scale, many of the design companies cannot afford to own and/or acquire expensive foundries, and have to outsource their fabrication process to one-stop-shop foundries.
While the globalization of Integrated Circuits (“IC”) design flow has successfully ameliorated the design complexity and fabrication cost problems, it has led to several security vulnerabilities. If a design is fabricated in a foundry that may not be under the direct control of the fabless design house, attacks, such as reverse engineering, malicious circuit modification and Intellectual Property (“IP”) piracy can be possible. (See, e.g., Reference 3). For example, an attacker, anywhere in this design flow, can reverse engineer the functionality of an IC/IP, and then steal and claim ownership of the IP. An untrusted IC foundry can overbuild ICs and sell them illegally. Further, rogue elements in the foundry can insert malicious circuits (e.g., hardware Trojans) into the design without the designer's knowledge. (See, e.g., References 4 and 5). Because of these attacks and issues, the semiconductor industry loses tens of billions of dollars annually (see, e.g., Reference 6). This can also be because the designers have minimum control over their IP in this distributed design and fabrication flow.
While hardware security and trust is a relatively recent concern, a somewhat similar, yet fundamentally different problem of manufacturing defects has been on the research agenda of VLSI test researchers for the last few decades. The attacks detailed above are man-made, intentional, and meant to be hidden, while manufacturing defects can be more natural and unintentional, hampering the use of existing defect testing techniques. However, many concepts in VLSI testing, such as, for example, justification and sensitization, can be adapted for application in the context of hardware security and trust. Inspired by the design enhancement approach (e.g., Design-for-Testability (“DfT”)) for better testability of manufacturing defects, strong Design-for-Trust (“DfTr”) solutions can be devised against these attacks, detecting and possibly preventing them.
IC reverse engineering techniques can be broadly classified into two types: extraction of gate-level netlist from layout, and extraction of functional specification from gate-level netlist. Reverse engineering of an IC to extract a gate-level netlist has been proposed. (See, e.g., References 8 and 14). Procedures to extract a gate-level netlist from transistors have also been suggested. (See, e.g., Reference 15).
For example, the DARPA IRIS program seeks to obtain the functional specification of a design by reverse engineering its gate-level netlist. Previous techniques can exploit structural isomorphism to extract the functionality of datapath units. (See, e.g., Reference 16). Other techniques have been used to reverse engineer the functionality of unknown units by performing behavioral matching against a library of components with known functionalities such as adders, counters, register files and subtracters. (See, e.g., Reference 17). Still other techniques have identified the functionality of unknown modules by performing a Boolean satisfiability analysis with a library of components with known functionalities. (See, e.g., Reference 18).
Thus, it may be beneficial to provide an exemplary DfTr IC camouflaging technique, system, arrangement, computer accessible medium and method that can utilize fault activation, sensitization and masking, and which can overcome at least some of the deficiencies described herein above.