An integrated circuit (IC) device comprises a semiconductor die in which circuitry has been formed, this circuitry including a collection of circuit elements such as transistors, diodes, capacitors, resistors, etc. To provide electrical connections amongst devices on the die and between the die and a next-level component (e.g., a package substrate), an interconnect structure is formed over a surface of the die. The interconnect structure may comprises a number of levels of metallization, each layer of metallization separated from adjacent levels by a layer of dielectric material and interconnected with the adjacent levels by vias. The dielectric layers of the interconnect structure are often each referred to as an “interlayer dielectric” (or “ILD”), and a common material used to fabricate these ILD layers is SiO2. The metallization on each layer comprises a number of conductors (e.g., traces) that may route signal, power, and ground lines to and from the circuitry formed on the die.
For some IC device applications, it may be desirable to increase the I/O (input/output) density of a semiconductor die while also reducing the size of the die. To achieve such a result, it may be necessary to decrease the spacing between conductive traces in the interconnect structure formed on the die. Space reductions include reducing the spacing between traces in the same level of metallization, as well as reducing the spacing between traces in adjacent metallization levels. As the spacing between conductors of an interconnect structure decreases, the potential for coupling capacitance between closely spaced traces and propagation delays may significantly increase. The coupling capacitance and propagation delays may be minimized by reducing the dielectric constant of the material that separates the conductive traces of the interconnect structure. Thus, manufacturers of IC devices may turn to dielectric materials having a lower dielectric constant—e.g., “low-k” dielectrics—to construct the ILD layers of the interconnect structure. Examples of such low-k dielectric materials include carbon doped oxide (CDO), fluorinated silicon glass (FSG), aerogels, xerogels, nanoporous silicon dioxide, and benzocyclobutane (BCB). However, these low-k dielectrics may have poor mechanical integrity in comparison to traditional dielectric materials (e.g., SiO2) and, therefore, may be more susceptible to cracking and/or delamination during assembly (e.g., wirebonding) and testing.