1. Technical Field
This invention relates generally to memory devices, and more particularly, to a memory device with improved switching speed and data retention.
2. Background Art
The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful, new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Generally, information is stored and maintained in one or more of a number of types of storage devices. Storage devices include long term storage mediums such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like. The long term storage mediums typically store larger amounts of information at a lower cost, but are slower than other types of storage devices. Storage devices also include memory devices, which are often, but not always, short term storage mediums. Memory devices tend to be substantially faster than long term storage mediums. Such memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate memory (DDR), flash memory, read only memory (ROM), and the like. Memory devices are subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain their information whether or not power is maintained to the devices. Non-volatile memory devices include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), flash memory and the like. Volatile memory devices generally provide faster operation at a lower cost as compared to non-volatile memory devices.
Memory devices generally include arrays of memory devices. Each memory device can be accessed or “read”, “written”, and “erased” with information. The memory devices maintain information in an “off” or an “on” state, also referred to as “0” and “1”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g. 8 memory devices per byte). For volatile memory devices, the memory devices must be periodically “refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
The use of portable computer and electronic devices has greatly increased demand for non-volatile memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity non-volatile memory devices (e.g., flash memory, smart media, compact flash, and the like).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity. Typically, fabrication processes for such cells are also not reliable.
Therefore, there is a need to overcome the aforementioned deficiencies.
FIG. 1 illustrates a type of memory device 30 which includes advantageous characteristics for meeting these needs. The memory device 30 includes a Cu electrode 32, a copper sulfide passive layer 34 on the electrode 32, an active layer 36 such as Cu2O or various polymers on the layer 34, and a Ti electrode 38 on the active layer 36. Initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, an increasingly negative voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an increasing electrical potential is applied across the memory device 30 from a higher to a lower potential in the direction from electrode 32 to electrode 38, until electrical potential Vpg (the “programming” electrical potential) is reached (see FIG. 2, a plot of memory device current vs. electrical potential applied across the memory device 30). This potential Vpg is sufficient to cause copper ions to be attracted from the superionic layer 34 toward the electrode 38 and into the active layer 36, causing the active layer 36 (and the overall memory device 30) to switch to a low-resistance or conductive state (A). Upon removal of such potential (B), the copper ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory device 30) remain in a conductive or low-resistance state, as indicated by the resistance characteristic (B).
In order to erase the memory device (FIG. 2), an increasingly positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an increasing electrical potential is applied until electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the reverse direction. This potential Ver is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the superionic layer 34, in turn causing the active layer 36 (and the overall memory device 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory device 30.
FIG. 2 also illustrates the read step of the memory device 30 in its programmed (conductive) state and in its erased (nonconductive) state. An electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the same direction as the electrical potential Vpg. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, if the memory device 30 is programmed, the memory device 30 will readily conduct current (level L1), indicating that the memory device 30 is in its programmed state. If the memory device 30 is erased, the memory device 30 will not conduct current (level L2), indicating that the memory device 30 is in its erased state.
Upon application of the electrical potential Vpg to switch the memory device 32 from an erased state to a low-resistance or conductive state (low-resistance state indicated by the on-resistance line B), the current vs. voltage path A in this environment includes two identifiable connected portions, a first, or initial (in time) portion A1 and a second, or later (in time) portion A2. Typically, upon the programming voltage Vpg being applied to the memory device 30, an initial rapid movement of ions into the active layer 34 takes place (A1), followed by a slower transfer of ions thereinto (A2). Thus, it has been found that the first portion A1 of the switching operation takes place relatively rapidly (i.e., consumes relatively little time), while on the other hand, the second portion A2 of the switching operation takes place relatively slowly (i.e., consumes appreciably more time). It will be understood that high switching speed is desirable, and that this second, slower portion slows down the pace of the switching operation, i.e., causes the overall switching operation to take more time than is desirable.
Therefore, what is needed is an approach which decreases switching operation time in the present environment.