Silicon-on-insulator (SOI) wafer is a starting material for making advanced semiconductor chips. Currently the most advanced method of making the SOI wafers is a layer transfer method. In the layer transfer method, a thin film of crystalline material is delaminated from a first wafer and laminated on a surface of a second wafer. The first wafer is called a donor wafer, and the second one is called a destination wafer. Either the donor or the destination wafer or both can have insulating films on their surfaces. Those insulator films further appear as a middle layer in a 3-layer sandwich structure that is obtained by the layer transfer process. The sandwich structure which consists of a silicon wafer with silicon dioxide and silicon films on its top is referred as the SOI wafer, and it is mostly used in mass production of advanced chips. The layer transfer process was invented by Bruel, and described in U.S. Pat. No. 5,374,564 awarded to him. Bruel's process was later named Smart-Cut. The Smart-Cut process sequence is schematically illustrated on FIG. 1 and FIG. 2. Due to the Smart-Cut process, FIG. 1A an initial donor wafer 101 with a silicon dioxide layer 102 is provided. Then, FIG. 1B, the wafer 101 is implanted through oxide 102 with hydrogen ions 103 which stops inside of silicon wafer and form a hydrogen-rich layer 104. The layer 104 divides the wafer 101 into silicon film 105 to be further transferred and a leftover part 106. Then, FIG. 1C the donor wafer 101 is brought into contact with a destination wafer 107 and a prebonded wafer assembly 108 with bonding interface 109 is formed. Then, FIG. 1D the assembly 108 is heated to cause a spontaneous cleavage along the hydrogen-rich layer 104 and make a SOI wafer 109 and a leftover wafer 110. The SOI wafer 109 consists of a silicon wafer 107 covered with a silicon dioxide film 111 and a single crystalline silicon film 112 having a work side surface 113. More processing details 201–208 of the Smart-Cut are illustrated by FIG. 2.
The Smart-Cut process still has drawbacks that where partially eliminated by numerical improvements as described in patents awarded to Goesele—U.S. Pat. No. 6,150,239, to Henley—U.S. Pat. No. 5,994,207, to Usenko—U.S. Pat. No. 6,352,909, and in others. The most important drawbacks of the Smart-Cut are as follows:    (1) difficult to get thin transferred layer;    (2) high manufacturing cost.
The difficulty in the transfer of thinner layers in the Smart-Cut is caused by the use of hydrogen implantation into plain silicon lattice. In the Smart-Cut, hydrogen implantation depth defines a plane along which a film is further delaminated from the donor wafer. Hydrogen is the lightest ion; therefore it penetrates into targets deeper than any other ion being implanted. At typical hydrogen ion energy of about 100 keV used in the Smart-Cut process, the hydrogen penetrates to a depth of about 1 micrometer below the silicon surface. And, about 1-micron thick layer is delaminated from a donor substrate and laminated to a destination substrate. The typical final Unibond™ wafer (SOI wafer obtained by Smart-Cut process) therefore has about 1-micron thick superficial silicon, or about 1-micron thick stacks consisting of the superficial silicon, and an insulative film. Chip manufacturing, however, requires much thinner superficial silicon, and insulator layer thicknesses. Manufacturing of mainstream chips that have fully depleted CMOS architecture requires the thickness to be no more than 50 nanometers. In the future, manufacturing chips will require even thinner silicon layers as the chipmaking advances mainly by scaling down all features, including the lateral and vertical dimensions of transistors constituting the chips. Smart-cut however, is limited to layer transfers in excess of 200 nm. There were attempts to obtain thinner layers by the Smart-Cut by lowering of hydrogen implantation energy. Bruel's patent does not claim hydrogen energy range, but later it was found that the lowest energy is about 20 keV [Y. V. Nastaushev, T. Gavrilova, M. Kachanova, L. Nenasheva, V. Kolosanov, O. V. Naumova, V. P. Popov, A. L. Aseev “20-nm Resolution of electron lithography for the nano-devices on ultrathin SOI film” Materials Science and Engineering C vol. 19 (2002) 189–192]. At lower energies, Smart-Cut process fails. In the case of low implantation energy, implanted hydrogen does not form an in-depth distribution with a clear peak at some depth. Instead, hydrogen is distributed quite evenly from surface to some depth in silicon. When there is no a well defined peak, the donor wafer is either not cleavable, or it cleaves at various depths along the wafer area, and a layer that is highly non-uniform in thickness is further delaminated and transferred onto a destination wafer. The relative widening of the peak of the implanted specie with energy decrease is a general feature of ion implantation that relates to all kinds of implanted ions. At higher energies, ions show an average depth where they stop (called projection range) that is much bigger, than average depth deviation (called struggle). At low energies, the struggle is approaching ½ of the projection range, and therefore the ion distribution looses peak pattern with energy lowering. High energy (tens of keV or more) ions predominantly loose their energy while penetrating a target by transferring energy to electrons of the target. When ion energy drops to about 20 keV, another mechanism of interaction with a target becomes dominant. The mechanism is displacing of target atoms. Therefore at the end of its track, ion makes numerical displacements of target lattice atoms and quickly stops. This results in quite narrow peak of distribution of high energy ions. Implanting of sub-20-keV ions predominantly results in displacing of target lattice atoms beginning from initial hit into the lattice; in other words, the low energy ion begins to destroy target lattice as soon as it hits the crystal surface. Therefore sub-20-keV implanting results in in-depth profile of implanted ions that is rather diffused, then a peak-like. The diffused profile causes the Smart-Cur failure.
Another reason why Smart-Cut fails to transfer thin films relates to surface damage by sub-20 keV ions. The damaged surface has higher roughness then an initial polished surface. Rough surface donor cannot be bonded to the destination wafer. Without bonding, the layer cannot be transferred, and Smart-Cut fails.
Another cause why Smart-Cut fails to transfer thin films is a premature blistering of wafer surface if the wafer is implanted with low energy ions. Hydrogen implantation results in creating of pressurized hydrogen bubbles under wafer surface. Low energy implantation results in shallow location of the bubbles. Thinner layer of silicon covering the bubbles is easier to break. The wafers implanted with sub-20 keV hydrogen ions blister at implantation doses that are lower than a dose needed for layer transfer.
Attempts to obtain thin superficial silicon by transferring of 200-nm Si—SiO2 stacks mostly consisting from SiO2 (like 50 nm of Si and 150 nm of SiO2) also fails. In this case implanted hydrogen segregates at Si—SiO2 interface instead of forming a cleavage plane inside of silicon. Only SiO2 layer transfers are obtained, and SOI wafers are not obtained.
Additional thinning of transferred films by polishing or etching is typically used to extend the Smart-Cut capabilities into sub-100 nm range. Thinning however increases thickness non-uniformity of the superficial crystalline film of SOI wafer that is highly undesirable.
High manufacturing costs of the Smart-Cut are caused by necessity of prolonged hydrogen implanting. Smart-Cut requires implanting of hydrogen in a dose exceeding 4×1016 cm−2. Even though this dose is two orders of magnitude bigger, than doses used in chip manufacturing, modern implanters allow getting reasonably high throughput for this dose as they have high ion beam current. Hydrogen implantation in Smart-Cut cannot however benefit from high ion beam current. The higher the beam current, the stronger is target heating. If the target (i.e, silicon wafer) is heated over about 80° C. during the implantation, Smart-Cut fails. Heating of the wafer under implantation causes premature blistering. Due to its low solubility in silicon, implanted hydrogen immediately segregates into pressurized bubbles. At elevated temperature the bubbles develop high pressure and cause fracture of silicon film covering the bubble. FIG. 3 shows a typical picture of wafer that is implanted at high beam current. On FIG. 3, areas 301 are not blistered, while areas 302 are blistered. In this case, the blistered areas are closer to the wafer center which had worse contact to a thermal sink and was heated to higher temperature.
To obtain higher throughput of Smart-Cut implantation, cooling of the silicon wafer during the Smart-Cut implantation is typically used. The cooling, however, allows increasing the hydrogen ion beam current no more then by a factor of 2 or 3. It means that the implantation time for one wafer can be decreased from several hours per wafer to about one hour per wafer that is very low throughput in wafer production. Batch implanters process up to about a dozen wafers simultaneously. Those implanters allow increasing the throughput by about a factor equal to a number of the simultaneously processed wafers. Therefore the best achievable throughput in the Smart-Cut is limited to about 10 wph (wafers per hour). This is not enough to achieve a cost-efficient SOI wafer production.
To obtain higher throughput of Smart-Cut implantation, plasma immersion ion implantation was suggested. Henley in U.S. Pat. No. 6,582,999 as well as in his previous 20 related patents (U.S. Pat. Nos. 6,548,382, 6,528,391, 6,511,899, 6,458,672, 6,413,837, 6,321,134, 6,291,326, 6,291,314, 6,290,804, 6,248,649, 6,207,005, 6,162,705, 6,155,909, 6,153,524, 6,146,979, 6,083,324, 6,013,563, 6,010,579, 5,994,207, 5,985,742) describes using of plasma immersion ion implantation instead of conventional beam implantation to introduce hydrogen into silicon to a defined plane for further cleavage and SOI wafer production. The plasma immersion ion implantation is similar to the regular implantation in many considerations. The plasma immersion equipment can be described as a simplified ion implanter: a regular implanter but not equipped with ion separator. Another important feature of the plasma immersion ion implantation is that it is pulsed. In a wafer being implanted, all vacancies and interstitials are generated during the pulse, and therefore, it results in denser concentration of vacancies, and interstitials at the end of the pulse as compared to the steady state defect generation. The denser concentration of the generated defects causes more efficient annihilation of the defects. Finally, in the Smart-Cut at room temperature, about 50% of hydrogen find a vacancy, form a hydrogen-vacancy site, and retain in the silicon, while less then 10% of hydrogen introduces by plasma immersion ion implantation find a vacancy and retain in silicon. However, the plasma immersion ion implantation has an advantage over the beam implantation as it allows obtaining much higher hydrogen fluences. The beam implantation is limited to no more then about 0.1 A hydrogen ion beam current, while plasma immersion ion implantation can yield up to 10 A in averaged hydrogen current into the wafer. Therefore, the plasma immersion ion implantation can potentially give better wafer throughput, than the beam implantation, even though the hydrogen losses are much higher in the plasma immersion case. The direct replacement of the beam implantation by plasma immersion in the Smart-Cut results, however, in much worse quality of final SOI wafers. The reason is that in the plasma immersion case, hydrogen having energies from almost zero to about 40 keV is implanted. That results in hydrogen retention in wide layer from surface to about 0.5 micrometer. Immediately after implantation, hydrogen is in form of bubbles in silicon. High temperature anneal after cleavage removes hydrogen from silicon leaving empty voids in place of hydrogen bubbles. A crystalline quality of that heavily hydrogenated silicon cannot be healed by annealing to a level required by chip production.
Henley does not describe in his patents, what is the minimum hydrogen dose needed to enable the layer transfer with plasma immersion ion implantation. The minimum dose was experimentally determined independently, and it exceeds 1018 cm−2, i.e., much higher dose than in the Smart-Cut. Silicon has about 1018 cm−3 contamination of oxygen, and also non-negligible concentration of other doping and unintentional impurities evenly distributed in silicon. Some of them works as infinite traps for hydrogen; and the higher dose hydrogen implantation, the bigger amount of hydrogen platelets and bubbles will be created on these unintentional and unavoidable traps. The hydrogen platelets and the bubbles are non-point defects, and silicon that contains these features cannot be annealed to restore its initial perfect lattice. Finally, plasma immersion implantation version of the Smart-Cut results in SOI wafers with low quality superficial silicon. That silicon contains voids in high density.
Another problem with Henley's process is that it results in thinner transferred layers at wafer periphery as compared to the wafer center. This is because the plasma immersion implantation equipment is characterized in non-uniform hydrogen energy across the wafer; higher energy at the center, and lower energy near the edges. Fan et al. in Z. Fan, P. K. Chu, N. W. Cheung, C. Chan, Thickness uniformity of silicon-on-insulator fabricated by plasma immersion ion implantation and ion cut, IEEE Transactions on Plasma Science, Vol. 27, 1999, pages 633–636 given an experimental evidence of thickness non-uniformity of the plasma immersion implantation version of the Smart-Cut; the thickness non-uniformity is a serious quality problem in the final SOI wafer.
As it is explained above, the Smart-Cut can be characterized as a trap-controlled process. An availability of properly located traps determines the Smart-Cut efficacy. Without the traps, hydrogen does not retain in silicon, it outdiffuses. In previous art, attempts where made to improve the Smart-Cut throughput by pre-forming a trap layer for hydrogen and further hydrogen injection. Agarwal et al. described helium-than-hydrogen implantation; Goesele at al., Bower, and Nastasi et al. described boron-than-hydrogen implantation; Usenko described trap-creating implantation followed by hydrogenation by either electrolytic or plasma means. These Smart-Cut improvements either partially resolve the thickness and cost related Smart-Cut issues, or create quality issues.
Agarwal et al (A. Agarwal, T. E. Haynes, V. C. Venezia, O. W. Holland, and D. J. Eaglesham, “Efficient production of silicon-on-insulator films by co-implantation of He+ with H+”, Applied Physics Letters, vol. 72 (1998), pp. 1086–1088) describe dual implantation to achieve layer transfer at lower total implantation dose. They report they got the layer transfer at a combined dose of their sequential helium-then-hydrogen implants that is about 2 times lower then minimum dose required in the Smart-Cut (7.5×1015+1×1016 cm−2 against 4×1016 cm −2). Due to Agarwal, helium and hydrogen implantation depths should be the same. Even though, they do not attribute the lower total dose needed to the trapping phenomena, this is a possible explanation in the lowering of minimum required dose they observe. Agarwal's approach, however, does not solve the thickness problems of the Smart-Cut.
Goesele et al. in U.S. Pat. No. 6,150,239 described boron-than-hydrogen implantation to achieve a cleavage at lower total implantation dose. They also report about 2-fold drop in minimum implantation dose required to enable the layer transfer. However, Goesele suggests implantation in conditions when boron implantation peak coincide with hydrogen implantation peak. That restrict hydrogen implantation conditions in peakless, i.e., low energy mode. Subsequently, the thickness limitation is the same as in the Smart-Cut, and thin transfers are not enabled by Goesele. Also, Goesele does not describe that the post-boron hydrogen implantation can be performed in high beam current mode. Therefore the throughput problem is not solved by Goesele either.
Bower in U.S. Pat. No. 6,812,547 describes layer transfer where he implants boron, then anneal the wafer, then implant hydrogen to form a fragile layer for further cleavage at a plane where boron acceptor centers are located. Due to Bower's teaching, the boron and hydrogen energies are not required to be chosen by condition that they have the same projection range. Hydrogen can be implanted anywhere in the wafer, and then hydrogen diffuses until it finds boron acceptor centers, and then hydrogen gets trapped at these centers. Therefore, potentially the Bower's technique might be free from limitation on thickness of layer transfers that is inherent to the Smart-Cut, to Agarwal's, and to Goesele's processes, and it might enable ultrathin layer transfers. Even though Bower describes 330-nm transfer only, let us analyze that possibility. We believe that Bower's process cannot enable the ultrathin transfers. The reasons are as follows. Bower teaches to introduce acceptor centers into silicon to enable the film delamination. Due to Bower's teaching, annealing of the boron-implanted wafer result in complete removal of implantation damages and in electrical activation of boron. The activated boron creates acceptor centers in silicon that further work as traps for hydrogen. Hydrogen is implanted deeper into silicon and diffuse after the implantation until it reaches the boron traps. The acceptor impurity (boron) is introduced in an amount of 1015 cm−2 and activated by annealing at 950° C. due to Bower. An acceptor center concentration in semiconductor cannot exceed a solubility limit of given acceptor impurity in semiconductor at activation temperature. In Bower's case, boron solubility limit at 950° C. is 2×1020/cm3. Therefore, a layer of (1015 cm−2)/(2×1020/cm3)=50 nm in thickness will be doped to the boron solubility limit. This means, that a layer with a thickness of 50 nm will trap hydrogen, and it further means that the splitting plane is defined with 50-nm accuracy. The wafer will split anywhere inside of the 50 nm band. Then, at the best, the as-cleaved surface will have a roughness of 50 nm. This says that sub-100-nm layer transfers will be extremely non-uniform in thickness, and thus are not technically featurable for thin SOI production.
Another reason, why Bower's teaching cannot be applied for manufacturing of thin SOI relates to unwanted altering of electrical properties of the transferred silicon layer. Silicon, doped with boron to 2×1020/cm3 has resistivity of 5×10−4 Ωcm. Chips cannot be manufactured in these heavy doped films for several reasons, for example, because carrier mobility drastically drops in heavy doped semiconductors, and also because a depleted zone will not extend through entire thickness of silicon film, so fully depleted devices cannot be manufactured.
Nastasi et al. in J. K. Lee, T. Hochbauer, R. D. Averitt, and M. Nastasi, “Role of Boron for Defect Evolution in Hydrogen-Implanted Silicon”, Applied Physics Letters, vol. 83, (2003), pp. 3042–3044 describe that at some combination of boron-then-hydrogen implantation conditions they observe that hydrogen follow either boron-caused damage peak, or boron peak, but they did not found conditions that allow very thin layer transfer.
Usenko in U.S. Pat. No. 6,352,909 describes a process for fabricating SOI wafers using ultrathin transfer of silicon film from a donor wafer to a destination wafer. Usenko uses silicon-into-silicon or other electrically non-active implants to form a shallow trap layer for hydrogen in silicon, and further insertion of atomic hydrogen into the wafer either by electrolytic means or from hydrogen plasma. This process is free from limitations inherent to Smart-Cut cut process as relative to thickness and to implant-related cost, but it is more difficult to get high quality SOI wafers using the U.S. Pat. No. 6,352,909 process. The quality problems appear in both, electrolytic, and plasma methods of hydrogenation. If hydrogen plasma contains low-energy hydrogen (as it happen, for example, in RF plasma), the low-energy hydrogen preferentially interact with silicon surface, instead of entering into the silicon lattice and diffusing to a trap layer. The interaction with surface results in silicon etching. The etching preferentially proceeds on defected surface areas, therefore the etching is not area-uniform, and roughness of silicon wafer surface increases. The rough surface wafer is difficult to bond to a destination wafer. The roughness causes bonding voids between the wafers. The voids cause layer transfer faults, and a final SOI wafer has areas with missing superficial silicon. These wafers are rejected and are not useful anymore. In a case of electrolytic hydrogenation, the chemical solution used as an electrolyte also etches silicon surface. The etching is the strongest in areas where silicon crystalline microdefects intersect the wafer surface. Etching pits appear in these areas. Further, the pits translate into voids of transferred silicon film, and the SOI wafers with missing superficial silicon areas are rejected again.
It will be beneficial to the art to have a process that combines high quality of final SOI wafers as in Smart-Cut process and ability of fabricating ultrathin SOI with high throughput as in processes that use trapping of hydrogen.