Printed wiring boards have conductors of conductive metal extending from one pad to another so that components can be mounted on the printed wiring board and connected to the pad to provide complex, extensive interconnections without the expense and chance of error in individual wiring. Single layer printed wiring boards are well known but suffer from the problem of crossing conductors. In order to overcome the crossover problem, multi-layer printed wiring boards are provided. These multi-layer printed wiring boards have conductors on plural layers. Interconnections between layers are provided by vias. The vias are in the form of holes through the boards. The holes are plated to make contact with the printed wiring on each of the appropriate layers.
Pads are provided on the conductors so that connection can be made to the components. These pads are commonly coated with solder and connections are made by reflow of the solder. When the component pad or lead is in contact with the pad on the printed wiring board, sufficient heat is applied to melt the solder on the pad so that it reflows into a connection with the component. The component may be connected by means of a lead frame on a package, individual wiring, or by placement of a leadless chip carrier with its pads directly in contact with the pads on the printed wiring board.
When such a pad is adjacent a via, reflow heating of the solder on the pad on the printed wiring board may permit the solder to run through the adjacent via. Such would starve the joint and would produce molten solder on the backside of the printed wiring board adjacent the via opening. Both are undesirable and should be eliminated.
Excess solder on the pad to accommodate for such outflow reduces control of the solder pad height, and thus is an undesirable adjunct of the prior practice. In addition, it is present practice to make the solder pads on the printed wiring board of greater length than the solder pad on the leadless chip carrier because this greater length is required to place the via outside the periphery of the leadless chip carrier. When the via is eliminated, the leadless chip carrier mounting pads on the printed wiring board need only extend to the periphery of the leadless chip carrier, which is termed zero-extension style pad patterns. Zero-extension style leadless chip carrier pad patterns may be less solder-height sensitive for good quality solder joints and are expected to allow for automated solder joint inspection and increased component spacing density.