1. Field of the Invention
The invention relates in general to a method of fabricating semiconductor device, and more particular, to a method of fabricating a memory device.
2. Related Art of the Invention
Memories are semiconductor devices typically used for storing information or data. As the computer processor becomes more and more powerful, the programs and operations executed by the software are more and more massive; therefore, the demand for memory becomes higher and higher. To fabricate memories with large storage capacity and low cost to complement the development of computer processors, fabrication techniques of memory devices have driven semiconductor fabrication techniques towards higher integration.
For example, flash memory devices that allow multiple operations of saving, reading and erasing and have the advantage that the information stored therein will not disappear after power off have been widely applied for personal computers and other electronic equipment.
The typical flash memory device includes a floating gate and control gate made of doped polysilicon. While performing a programming or erasing operation to the flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate, so that electrons are injected into the polysilicon floating gate, or pulled out from the floating gate.
Generally speaking, the commonly applied mode for electron injection in a flash memory device includes channel hot-electron injection (CHEI) and Fowler-Nordheim (F-N) tunneling. The ways for programming and erasing are varied according to the injection and pulling modes.
In the conventional stacked-gate flash memory fabrication process, a part of gate dielectric (oxide/nitride/oxide) will remain on a sidewall of the floating gate to form a fence during the step for defining the control gate, the gate dielectric layer and the floating gate. Such a residual fence causes particle contamination in the subsequent process. Further, the gate dielectric fence residing on the sidewall of the floating gate may also cause short circuit between the floating gates affecting the device performance. To avoid forming the gate dielectric layer fence on the sidewall of the floating gate, the conventional method includes increasing the etching rate for silicon oxide during the step of etching the gate dielectric layer, so that complete removal of the gate dielectric layer can be achieved. However, increasing the etching rate of silicon oxide results in the exposed field oxide becoming over etched to form a trench therein. Though overetch to the field oxide does not cause problems to normal flash memory devices, for the BiNOR flash memory (as disclosed in U.S. Pat. No. 6,214,668) that requires high implantation energy (about 50 KeV) to dope p-type dopant (Boron ions) into the substrate, so as to form a p-well, the very deep trench in the field oxide (that is, the very shallow field oxide) may cause the dopant to penetrate through to cause current leakage around the drain region. The isolation between the bit lines are very likely ineffective. To resolve such problems, currently, the mask used for performing the p-type ion implantation has been modified from slot type to hole type to expose only the substrate required to be doped (that is, the field oxide is covered). However, in this era where the device integration further increases, and the linewidth is reduced to 0.25 micron, the above method experiences the problems of photo margin, overlay shift and rounding shape, such that certain regions cannot be implanted as required. The device performance is thus affected, and the yield of the device is decreased.
The present invention provides a method of fabricating a memory device to avoid dopant penetrating through the field oxide during the ion implantation step that causes leakage current around the drain region of the memory device.
The method of fabricating a memory device provided by the present invention comprises the following steps. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A selective wet etching step is performed to remove the material layer out of the trenches. A patterned photoresist layer is formed on the substrate, where a part of the substrate predetermined for forming a drain region is exposed thereby. An ion implantation step is performed to implant dopant into the exposed part of the substrate, so as to form a well region. As the trenches are filled with the material layer, the dopant will not penetrate therethrough.
When the gate cap layer, the control gate layer, the gate dielectric layer and the floating layer are patterned to form the stacked gate structures, the trenches formed by over etching the isolation structures are filled with the material layer (bottom anti-reflection coating layer). As mentioned above, such an over etching step is performed to avoid forming the residual gate dielectric layer on the floating gate. The material layer filling the trenches avoids the dopant from penetrating through in the following ion implantation step, so that the current leakage around the drain region is avoided. Therefore, the present invention uses a very simple process to avoid penetration of dopant through the isolation structures in the subsequent ion implantation process, so that the leakage current around the drain region caused thereby is prevented.
Thus, the present invention uses a bottom anti-reflection coating layer to fill the trenches in the isolation layer to prevent subsequent ion implantation process from causing leakage current around the drain region. Therefore, the slot type mask can be used for the ion implantation step to expose the entire area predetermined for forming the drain, including the regions of isolation structures without introducing the problems of photo margin, overlay shift and rounding shape. The degraded device performance and reduced yield caused by the above problems are thus avoided. in addition, the material layer can also be selected from photoresist material.