FIG. 1 shows one example of an SRAM (static random access memory) as a prior art semiconductor memory device.
In FIG. 1, an address decoder 1 generates a word select signal corresponding to an address signal and supplies it to each of memory blocks 10(0)-(n) via a word line 20.
Each of the memory blocks 10(0)-(n) is a memory block of the same configuration, which is formed corresponding to each bit of data signal buses DB0-n.
An internal configuration of the memory block is described below in connection with an example of memory block 10(0).
In the figure, in memory block 10(0), there are provided a number of memory cells for storing one bit of information signal, corresponding to the number, m, of words stored. Each of these memory cells 100 is comprised of inverters 101 and 102 for storing one bit of information signal, a transmission gate 103 for transmitting the output of the inverter 102 to a bit line 21 in response to the word select signal, and a transmission gate 104 for transmitting the output of the inverter 101 to a bit line 22 in response to the word select signal.
Within m memory cells 100(1)-(m), only a memory cell to which a logic "1" word select signal is supplied from the address decoder 1 is accessed. Then, the accessed memory cell sends its stored information signal to the bit line 21 via the transmission gate 103. Furthermore, the accessed memory cell sends an inverted version of the stored information signal to the bit line 22 via the transmission gate 104. If a logic "1" word signal is not supplied to any of the memory cells 100(1)-(m), a precharge circuit (not shown) is activated. This precharge circuit forcefully charges the bit lines 21 and 22 to a logic "1" state.
A FF (flipflop) 30 formed of gates 31 and 33 rapidly determines the read result in accordance with the logic value of a pair of signal lines, such as the afore-mentioned bit lines 21 and 22. When the signal logic state on the bit line 21 is a logic "1" and the signal logic state on the bit line 22 is a logic "0" the FF 30 supplies a logic "0" information signal to the data bus driver 40 in response thereto. When the signal logic state on the bit line 21 is a logic "0" and the signal logic state on the bit line 22 is a logic "1", the FF 30 supplies a logic "1" information signal to the data bus driver 40 in response thereto. When the bit lines 21 and 22 are both in the logic "1" state due to the afore-described precharge circuit operation, the logic state of the information signal supplied to the data bus driver 40 prior to that state is held, while it is supplied to the data bus driver 40.
The data bus driver 40 is rendered into an output enable state when a logic "0" memory read instruction signal is supplied to its inverting output control terminal a. Furthermore, the data bus driver 40 is rendered into an output enable state when a logic "0" memory read instruction signal is supplied via the inverter 41 to its output control terminal b. That is, the data bus driver 40 is rendered into the output enable state depending on the supply of the logic "0" memory read instruction signal. Due to such an output enable state, the data bus driver 40 generates a voltage corresponding to the signal logic value of one bit of information signal stored in the FF 30 and applies it to the data signal bus DB0, whereas if the memory read instruction signal is not supplied, it is rendered into an output disable state. Thus, the data signal bus DB0 is then rendered into a so-called high-impedance state.
As described above, with the above configuration, in response to a logic "1" word select signal, the information signal stored in the memory cell is sent onto the bit line, and a memory read instruction signal is further supplied, so that the information signal on that bit line is read onto the data bus.
With the SRAM so configured, one possible method for reading stored data at a faster access time is to make the supply timing of the word select signal coincide with that of the memory read instruction signal.
FIG. 2 shows one example of operational timing chart where the stored data is read at such a timing.
In this figure, FF 30 stores a logic "0" information signal a as an initial value and outputs it as appropriate. It is also assumed that the memory cell 100 prestores a logic "0" information signal.
First, because the word select signal is in a logic "0" state, the bit line 21 (denoted by a solid line) and bit line 22 (denoted by a dotted line) are both in a logic "1" state, due to the operation of the afore-described precharge circuit. Furthermore, because the memory read instruction signal is a logic "1", the data signal bus DB0 is in a high-impedance state Z.
Next, when the word select signal becomes a logic "1", the logic "0" information signal stored in the memory cell 100 is sent onto the bit line 21 in response thereto. Also, to the bit line 22 is sent a logic "1" signal, or an inverted version of that information signal. Then, until the information signal stored in the memory cell 100 is sent to the bit lines 21 and 22 from a transition point where the word select signal is rendered into a logic "1", a delay is introduced as shown in FIG. 2, due to the influence of component capacitance, length of wiring and the like. After such delay, when the logic values of the bit lines 21 and 22 become "0" and "1", respectively, then the FF 30 outputs a logic "1" information signal b corresponding thereto. Then, concurrent with the afore-described transition of the word select signal to a logic "1" state, a logic "0" memory read instruction signal is supplied. In response to that memory read instruction signal, the data bus driver 40 is rendered into an output enable state. This output enable state causes the data bus driver 40 to generate a voltage corresponding to the logic value of the information signal supplied from the FF 30, and applies it to the data signal bus DB0. During that time, a delay as shown in the figure is present until the information signal b stored in the memory cell 100 is sent onto the bit lines 21 and 22. Thus, although the data bus driver 40 is in the output enable state in response to the memory read instruction signal, the FF 30 cannot immediately supply the information signal b to the data bus driver 40, during which time the information signal a is supplied to the data bus driver 40.
Thus, to read not only the information signal b read from the memory cell 100 but also the information signal a onto the data signal bus DB0, the data bus driver 40 generates a voltage corresponding to that information signal a and applies it to the data signal bus DB0, resulting in wasted power.
To cope with that, one conceivable method is to use a delay circuit to delay the timing of the memory read instruction signal supplied to the data bus driver 40, thereby preventing the aforementioned information signal a from being read onto the data bus. However, since the delay value of such a delay circuit is set somewhat greater in consideration of various factors, such as production process variations, supply voltage fluctuations, ambient temperature, it is difficult to reduce the access time associated with that method.
Accordingly, it is an object of the present invention to provide a low power consumption semiconductor memory device that permits reading of stored data at a faster access time, while minimizing power consumption.