In general, a computer program consists of a sequence of instructions all of which belong to a particular instruction set. At the appropriate time, each instruction is typically loaded into an instruction register where it resides while being decoded and executed. The execution of one instruction normally involves a plurality of steps. In many processors, each of these steps is performed by the execution of a microinstruction which may be stored in a read only memory. Accordingly, for these processors, a stage is required whereby a sequence of microinstruction memory addresses are provided for one instruction. In the prior art, this has been accomplished through the use of hardware logic that decodes the instruction. Commonly, each instruction is divided into a plurality of fields, each field consisting of a single bit or contiguous bits. Examples of fields are format, operation code, address mode, register specification, etc. The number, size, and types of fields may vary within one instruction set. Generally, the hardware decode logic determines the particular format from a delineation field within the instruction and then decodes the remainder of the instruction according to that format. However, when it is desirable to emulate a different processor using a different instruction set, different hardware decode logic is required.