As described in Publication of Japanese Patent Application No. 2001-2986151, a conventional C-MOSFET uses the same material for the gate insulation layer of both a PMOSFET and an NMOSFET in order to simplify fabrication process. In recent years of deep-sub-micron generation, in order to reduce a short channel effect and to improve driving performance, an NMOSFET includes a gate electrode of N-type, while a PMOSFET includes a gate electrode of P-type, which is called “Dual-gate structure”. In fabrication, an N-type impurity, such as phosphorus, is ion-implanted into an N-type poly-silicon gate electrode. On the other hand, a P-type impurity, such as boron, is ion-implanted into a P-type poly-silicon gate electrode.
However, in such fabricated PMOSFET, boron atomics may get out of the gate electrode through the gate insulation layer to the silicon substrate, which may be called “cut-through phenomenon”. As a result, the threshold voltage (Vth) of the PMOSFET is changed in level, and the reliability of the device is decreased as shown in “Kurasawa et al., IEDM Tech. Digest, p. 895, 1993”.
In order to prevent such cut-thorough phenomenon of boron, nitrogen may be added into the gate insulation layer. However, nitrogen atomics may be diffused to the interface between the silicon substrate and the gate insulation layer, so that the composition of nitrogen is increased adjacent the interface. When the composition of nitrogen is increased, fixed charge is generated in response to the composition of nitrogen. Such fixed charge lowers the flat band voltage of the MOSFET, and therefore, the threshold voltage of the NMOSFET is lowered and standby current is increased.
According to “S. Takagi et al., IEEE Trans. On Electron Device, Vol. 41, p. 2357, 1994”, when the nitrogen composition is increased, electron mobility is reduced. Further, there are other problems in that a) the mobility of the MOSFET is decreased and mutual inductance is decreased, “H. Iwai et al., Symp. On VLSI Tech., p. 131, 1990; b) NBTI (Negative Bias Temperature Instability) is worsened; c) the lifetime of a transistor, used at an I/O portion with a higher power supply voltage, is shortened, N. Kimizuka et al., Symp. On VLSI Tech. Digest, p. 73, 1999.
In order to prevent the above described problems, according to an invention described in Publication of Japanese Patent Application No. H05-218405 and E. Hasegawa et al., IEDM Tech. Digest, p. 327, 1995, the nitrogen composition in the gate insulation layer is controlled to not be higher than 1 atom %. However, when the gate insulation layer is thinner in accordance with minuteness of transistors, the amount of nitrogen in the gate insulation layer is reduced. It becomes difficult to prevent the cut-through phenomenon of boron in a PMOSFET.
According to Publication of Japanese Patent Application No. 2001-291865, nitrogen concentration in a gate insulation layer is controlled not to be higher than 1×1021 cm−3, while the nitrogen concentration at the interface between the silicon substrate and the gate insulation layer is controlled not to be higher than 1×1019 cm−3. However, the fabrications steps are increased and mobility of an NMOSFET is still low.