FIG. 9 shows a conventional power synthetic IC in which a high-power output transistor chip 23 is disposed between an input matching circuit 30 and an output matching circuit 31. The input matching circuit 30 and the output matching circuit 31 are disposed on a substrate 22 having a high dielectric constant, and the substrate 22 is disposed on a ceramic substrate 21. The input matching circuit 30 is connected to an input terminal 34 with four wires 33, and the output matching circuit 31 is connected to an output terminal 35 with four wires 33.
The input matching circuit 30 is divided into two patterns 30a and 30b, and the output matching circuit 31 is divided into two patterns 31a and 31b. The purpose of dividing the matching circuit into plural patterns is, since a large matching circuit may have area-to-area variations in characteristics, to make the characteristics of the circuit uniform in each pattern.
In a high-power output transistor employed as a high-frequency power synthetic IC, usually, a plurality of transistor cells (hereinafter referred to simply as cells) are connected in parallel. In the transistor shown in FIG. 9, twelve cells are connected in parallel, and the half of the twelve cells, i.e., six cells, are connected through wires 32 to the input matching circuit pattern 30a and the output matching circuit pattern 31a while the other half of the cells are connected through wires 32 to the input matching circuit pattern 30b and the output matching circuit pattern 31b.
FIG. 10 shows a comb-shaped transistor in which drain electrodes 1 and source electrodes 2 are alternatingly arranged facing each other, as an example of the high-power output transistor chip 23. The source electrodes 2 are connected through an air bridge 3 to source pads 4 and connected through via-holes 5 to a rear electrode (not shown) on the rear surface of a semi-insulating GaAs substrate 18. In the comb-shaped transistor, a single transistor cell comprises fourteen gate fingers, and a gate pad 7 is provided for the fourteen gate fingers. Each gate finger is fed through a gate bus 8.
By the way, in a high-frequency and high-power output transistor, there is a possibility that the transistor might oscillate and form a resonance circuit when a DC or a high frequency signal is applied thereto, because of cell to cell variations in characteristics and impedances. When the transistor forms such a resonance circuit, the operation of the transistor becomes unstable, i.e., no signal is output or unnecessary signals are amplified, whereby the synthesis efficiency is significantly reduced.
In the transistor shown in FIG. 9, the patterns 30a and 30b of the input matching circuit 30 are connected to each other through a resistor 92, and the patterns 31a and 31b of the output matching circuit 31 are connected to each other through a resistor 93, whereby the resistors 92 and 93 serve as gain loss components to prevent the transistor from oscillating when a DC or a high-frequency signal is applied. In this case, however, oscillation between adjacent cells in the transistor chip cannot be prevented.
Meanwhile, Japanese Published Patent Application No. Hei. 4-11743 proposed a semiconductor device capable of preventing unwanted oscillation inside a transistor. This semiconductor device is shown in FIG. 11. In FIG. 11, a bus bar 110 connecting gate electrodes 101 of six transistor cells, and a drain electrode 102 common to the six transistor cells are respectively divided into two parts so that each part corresponds to three transistor cells, and the separated bus bars 110 are connected to each other through a resistor layer 41 while the separated drain electrodes 102 are connected to each other through a resistor layer 42, which resistor layers are disposed on a semiconductor substrate 104. In FIG. 11, reference numerals 113 and 123 designate gate bonding pads and drain bonding pads, respectively. In this semiconductor device, however, oscillation between adjacent cells is not prevented, especially when a high-frequency signal is applied, because of cell to cell variations in characteristics and impedances.
Furthermore, Japanese Published Patent Application No. Hei. 1-166564 proposed a high-power field effect transistor for stable transistor operation. This transistor is shown in FIG. 12. In FIG. 12, a transistor cell comprises a plurality of transistor elements, and gate electrodes 37 of the transistor elements are connected through a gate leading electrode 38 to a gate bonding pad 39. A resistor 36 is connected between each gate electrode 37 and the gate leading electrode 38. In this transistor, however, since the resistor 36 is connected to the gate electrode 37 in series, it significantly reduces the gain of the transistor element.