As integrated circuit devices (e.g., semiconductor devices) become more highly integrated, an associated design rule may be reduced. As a result, the area occupied by the integrated circuit device may also be reduced, which may make it more difficult to form transistors therein. For example, NMOS transistors in a cell region of a memory device and PMOS and NMOS transistors in a peripheral circuit region are fabricated to have predetermined lengths so as to provide the electrical characteristics of these transistors. However, short channel effects associated with the reduced size of the transistors may result in the malfunction of a transistor device.
It is known to increase channel length by forming a raised source/drain using selective epitaxial growth. An epitaxy layer can be formed to a predetermined thickness on a portion of substrate where source/drain junctions are formed so that the resultant structure is higher than the substrate (i.e., a raised source/drain structure). The raised source/drain structure can effectively increase the channel length, thereby reducing short channel effects.
However, the thickness of the raised source/drain structure can also influence the efficacy of the transistor in other ways. For example, if the raised source/drain structure is too thick, the raised source/drain structure may cause an electrical short between the structure and a gate electrode. On the other hand, if the raised source/drain structure is too thin, the raised source/drain structure may not be effective enough in reducing the short channel effects.