Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips to base ceramic chip carriers, for example alumina carriers. In C4 technology or flip chip packaging, one or more integrated circuit chips are mounted above a single or multiple layer ceramic (MLC) substrate or board to internal connecting fingers or pad (C4 pads), and the internal bond pads on the chip(s) are electrically or mechanically connected to corresponding external lands or pads on the other substrate by a plurality of electrical connections, such as solder bumps, referred to as a ball grid array (BGA).
In MLC packages, a ceramic substrate is the platform upon which chips, passive components, protective lids, and thermal enhancement hardware are attached. Wiring patterns within the substrate carrier define escape paths in single chip modules (SCMs) and multichip modules (MCMs), transforming the tight I/O pitch at the die level of the chips to a workable pitch at the board level. The wiring pattern also establishes the modules' power distribution network. Vertical metal vias provide interconnections between the various layers within the MLC. C4 pads can be directly soldered onto MLC vias, providing low inductance, and direct feed to power and ground planes.
Routing of signal lines through a ceramic substrate begins at a die/package interface where signals and power escape the pin field of a given die. The package includes internal routing layers which couple the external landing pads (or ball grid array) to internal landing pads coupled to the die. The internal routing typically contains separate layers for ground, power and signal lines. In many BGA designs, over one half of the internal bond pads are associated with power and ground connections. As linewidths of vias continue to decrease and chip speeds continue to increase, the inductance associated with power and ground loops due to the routing of power and ground signals from the package to the die becomes increasingly problematic.