1. Field of the Invention
The present invention relates to a clock recovery circuit, and more particularly, to an over-sampling type clock recovery circuit which performs sampling of a data signal based on a plurality of clock signals having different phases.
2. Description of the Related Art
In recent years, a high-speed protocol is proposed such as Gbit Ethernet and Fiber Channel for data transmission. For this purpose, high speed processing is requested in a clock recovery circuit to extract a clock signal from a data signal in a high speed transmission and in a PLL circuit to establish frequency synchronization between the clock signal used in the circuit and the transmitted clock signal. In order to respond to such a request, as disclosed in 1996 IEEE International Solid-State Circuits Conference, an over-sampling type clock recovery circuit is proposed in which the transmitted data signal is sampled based on a plurality of clock signals with different phases generated by an internal circuit.
FIG. 1 shows a circuit block diagram of a clock recovery circuit which is disclosed in the conventional example. A data signal is supplied to eight phase comparators TIPD0 to TIPD7. The respective phase comparators TIPD0 to TIPD7 are supplied with 24 clock signals having fixed delays outputted from a fixed delay circuit for every set of three clock signals.
Each phase comparator detects the phase state between the data signal and the set of three clock signals. When the set of clock signals and the data signal are matched in phase to each other, the phase comparator detects a locking state to set a corresponding one of up signals up0 to up7 to an disable state and a corresponding one of dn signals dn0 to dn7 to a disable state, as shown in FIGS. 2A to 2F. When the set of clock signals leads the data signal, the phase comparator detects the leading of the clock signals to set a corresponding one of up signals up0 to up7 to the disable state and a corresponding one of dn signals dn0 to dn7 to an enable state. Similarly, when detecting the delay of the clock signal compared to the data signal, the phase comparator sets the up signal to the enable state and the dn signal to the disable state, as shown in FIGS. 3A to 3F.
Charge pumps CP0 to CP7 increase the output voltages when the up signals are set to the enable state and decrease the output voltages decrease when the dn signal is set to the enable state. The output voltages are supplied to a low pass filter LPF. The low pass filter LPF integrates the changes of the voltages supplied from the charge pumps CP0 to CP7 and outputs the integrated voltage to a variable delay circuit VD. A voltage controlled oscillator VCO oscillates and generates a reference clock signal to output to the variable delay circuit VD. The variable delay circuit VD delays the reference clock signal from the voltage controlled oscillator VCO in accordance with the integrated voltage from the low pass filter LPF. Then, a fixed delay circuit FD receives the delayed clock signal from the variable delay circuit FD and generates the 24 clock signals having fixed delays from the delayed clock signal.
In the clock recovery circuit, the up signal or dn signal is set to the enable state in each phase comparator, as described above. As a result, the voltage outputted from the corresponding charge pump CP increases or decreases, when the leading or delaying state of the set of clock signals is detected. Therefore, the delayed clock signal is outputted from the variable delay circuit VD based on the phase leading or delaying state, and the 24 clock signals are generated by the fixed delay circuit FD based on the delayed clock signal. As a result, the leading or delaying state of the clock signals to be supplied to each of the phase comparators TIPD0 to TIPD7 is controlled so that the appropriate sampling of the data signal can be realized.
However, in this clock recovery circuit, the data sampling cannot be correctly performed, when the phase differences are generated between the 24 clock signals due, to the influence of the wiring layout of the circuit. Especially, when a phase difference is generated between three clocks supplied to the phase comparator, the data sampling cannot be correctly performed. For example, when delay of a clock signal clkn+1 is generated as shown in FIG. 3D, the phase comparator detects a clock delaying state so that the up signal is set to the enable state. For this reason, owing to the operation in the stage subsequent to the charge pump CP receiving the enable state of the up signal, the delay of the 24 clock signals generated in the fixed delay circuit FD is controlled. As a result, the correct data sampling cannot be performed in the whole clock recovery circuit, including other phase comparators.
Also, in such a clock recovery circuit, the number of bits of the transmitted data signal continuously having the same value is limited. Therefore, in a locking state in which any phase difference is not detected, even if the number of clock signals used for the sampling is decreased, the phase difference can be correctly detected.
However, in the above-mentioned clock recovery circuit, the eight phase comparators TIPD0 to TIPD7 are always in the operating state regardless of whether or not they are in the locking state. As the result, in the locking state, ones of the phase comparators other than the phase comparators necessary to detect phase differences perform unnecessary operation. Therefore, the eight phase comparators with the relatively large power consumption operate continuously at the same time. Thus, the power consumption as the whole clock recovery circuit cannot be ignored. Also, each of the charge pumps CP0 to CP7 subsequent to the phase comparators TIPD0 to TIPD7 operate based on phase difference data outputted from the respective phase comparators. Moreover, the power consumption in the low pass filter LPF and the subsequent circuits cannot be ignored.
In addition to the above conventional example, a disqueque apparatus is disclosed in Japanese Examined Patent Application (JP-B-Showa 61-18274). In this reference, the disqueque apparatus is composed of first and second sections and a memory section. The first section determines a majority of sync signals for channels to produce a signal. The second section produces a synthetic signal in response to an output obtained by adding clocks for the channels. The memory section executes performs a read operation in response to the signal and the synthetic signal. Thus, when a data block is composed of a plurality of tracks each of which includes a frame sync signal and a data, the disqueque apparatus can remove a time shift of data between the tracks in a multi-track digital magnetic recording and reproducing apparatus.
Also, a digital signal receiving apparatus is disclosed in Japanese Laid Open Patent application (JP-A-Showa 61-145945). In this reference, the digital signal receiving apparatus is composed of a reproducing section and a majority determining section and a conversion section. The reproducing section reproduces clock signals having a basic clock signal frequency fr and a frequency n (n is a positive integer equal to or larger then 3) times of the basic clock signal frequency fr locked to a digital reproduction signal in phase. The majority determining section extracts n samples values during one bit of the digital reproduction signal based on nfr clock signals, and determines binary values of the n sample values on the majority side as a value during the bit. The converting section converts the determined value to have 1/fr width. Thus, the digital reproduction signal is shaped in units of basic clocks fr of the digital reproduction signal.
Also, a data sampling converting circuit is disclosed in Japanese Laid Open Patent application (JP-A-Showa 61-214842). In this reference, the data sampling converting circuit includes a clock reproducing circuit, a frequency dividing circuit and a determining circuit. The clock reproducing circuit reproduces a clock pulse from a character multiplexed signal. The frequency dividing circuit divides the reproduced clock signal in frequency to 1 to n-th, and generates n sampling pulses with different phases. The determining circuit performs sampling of the character multiplexed signal with the n sampling pulses and determines based on majority determination of m continuous sampling results whether a digital data is in a high level or a low level.
Also, a demodulation data identifying and determining apparatus is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 3-69238). In this reference, the demodulation data identifying and determining apparatus is composed of a detecting and demodulating circuit, a comparator, a clock reproducing circuit, a timing determining section, a latch circuit. The detecting and demodulating circuit demodulate an input signal to output a base band signal. The comparator converts the base band signal into a binary signal. The clock reproducing circuit reproduces a reproduction clock signal having the same frequency as a bit rate of a transmission data, and generates a clock signal faster than the reproduction clock signal. The timing determining section performs sampling of the binary signal using the clock signal and performs majority determination to a plurality of values corresponding to a plurality of sampling points to output the result of the majority determination. The latch circuit latches the output from the timing determining section in accordance with the reproduction clock signal to output as a reproduced digital data.
Also, a digital signal reproducing circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 4-11431). In this reference, the digital signal reproducing circuit is composed of a demodulating section, a sampling section and a majority determining section. The demodulating section demodulates a digital modulated signal. The sampling section performs sampling of the demodulated digital signal in accordance with clock signals from a clock source. The majority determining section performs majority determination to a plurality of sampling values supplied from the sampling section.