1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of driving the semiconductor memory device, and more particularly, to a semiconductor memory device having single-bit cells and multi-bit cells, and a method of driving the semiconductor memory device, by which a malfunction or non-operation of the semiconductor memory device can be addressed.
2. Description of the Related Art
With the development of mobile systems and a variety of application systems, the demand for flash memory, which is a non-volatile type of memory, is increasing. A flash memory, which is an electrically erasable and programmable non-volatile memory device, can retain data even when no power is supplied. In particular, a NAND type flash memory device has a string structure in which a plurality of memory cells are serially connected to each other, and therefore is easily integrated and can be supplied at a low price. For this reason, NAND flash memory devices are used as data memory of a great variety of portable products.
With the development of flash memory devices and their related technology, a flash memory device that can store two or more bits in one memory cell is widely used. A single-level cell (SLC) is used to store one-bit data in one memory cell, and a multi-level cell (MLC) is used to store data corresponding to two or more bits in one memory cell.
FIG. 1A is a graph showing a data state in a single-level cell versus a threshold voltage. As shown in FIG. 1A, when storing one-bit data in the single-level cell, when a programmed threshold voltage is 1 to 3 V, the data stored in the single-level cell is logic“1”, and when the programmed threshold voltage is 5 to 7 V, the data stored in the single-level cell is logic“0”. Data stored in a memory cell is read out by detecting a variation in the current of the memory cell, which is caused due to a change of a threshold voltage.
FIG. 1B is a graph showing a data state in a multi-level cell versus a threshold voltage. As an example, a case where two-bit data is stored in one memory cell is illustrated. As shown in FIG. 1B, when storing two-bit data in a single multi-level cell, when a programmed threshold voltage is 1 to 3 V, data stored in the memory cell has a logic level of “11”. When the programmed threshold voltage is 3.8 to 4.2 V, data stored in the memory cell has a logic level of “10”. Also, when the programmed threshold voltage is 4.9 to 5.4 V, data stored in the memory cell has a logic level of “01”. When the programmed threshold voltage is 6.5 to 7.0 V, data stored in the memory cell has a logic level of “00”.
A memory cell included in a flash memory device can be used as a single-level cell for storing one bit or as a multi-level cell for storing data corresponding to two or more bits. Also, in a single flash memory device, some memory cells included therein are single-level cells and the remainder are multi-level cells.
When various types of memory cells, namely, single-level cells and multi-level cells, are used as memory cells of one flash memory device, the single-level cells and the multi-level cells are driven by different commands. That is, according to predetermined cell area information, some of the memory cells are set as single-level cells and the others are set as multi-level cells. Operations such as a program operation, a read operation, etc. are performed on the single-level cells in response to addresses corresponding to the single-level cells and a command for the single-level cells. Operations such as a program operation, a read operation, etc. are performed on the multi-level cells in response to addresses corresponding to the multi-level cells and a command for the multi-level cells. A conventional flash memory device including single-level cells and multi-level cells as described above will be described with reference to FIG. 2.
FIG. 2 is a block diagram of a conventional semiconductor memory device, that is, a conventional flash memory device 10. As shown in FIG. 2, the conventional flash memory device 10 may include a command decoder 11, a command flag generation unit 12, a logic circuit for SLCs 13, a logic circuit for MLCs 14, a memory controller 15, and a memory cell array 16. An SLC command for programming or reading of single-level cells or an MLC command for programming or reading of multi-level cells is input to the command decoder 11. Some of the memory cells 16 are single-level cells and the others are multi-level cells.
The command decoder 11 receives a command provided by an external host (not shown) and decodes the command. The decoded command is provided to the command flag generation unit 12.
In response to the decoded command, the command flag generation unit 12 outputs a signal for enabling one of the logic circuit for SLCs 13 and the logic circuit for MLCs 14. For example, when the command received by the command flag generation unit 12 is an SLC command, the command flag generation unit 12 activates and outputs a signal EN1 in order to enable the logic circuit for SLCs 13. When the command received by the command flag generation unit 12 is an MLC command, the command flag generation unit 12 activates and outputs a signal EN2 in order to enable the logic circuit for MLCs 14.
When the SLC logic circuit 13 is enabled by the activated signal EN1, the SLC logic circuit 13 provides to the memory controller 15 a control signal C1 that is generated due to a series of operations for driving the single-level cells among the memory cells 16. The memory controller 15 generates various voltage signals (not shown) and control signals C3 and provides the generated signals C3 to the memory cells 16. In this case, the signals C3 are used to drive the single-level cells of the memory cells 16.
On the other hand, when the command received by the command flag generation unit 12 is an MLC command, a signal EN2 is activated and the MLC logic circuit 13 is enabled by the activated signal EN2. The MLC logic circuit 14 provides to the memory controller 15 a control signal C2 that is generated due to a series of operations for driving the multi-level cells among the memory cells 16. The memory controller 15 generates and provides various voltage signals (not shown) and control signals C3 to the memory cells 16. In this case, the signals C3 are used to drive the multi-level cells of the memory cells 16.
In the conventional flash memory device 10 constructed as described above, addresses corresponding to multi-level cells may be input even though a command for single-level cells is input, or addresses corresponding to single-level cells may be input even though a command for multi-level cells is input. Alternatively, when one single-level cell block including 64 pages is driven, wrong addresses deviating from an address range for the pages may be input. In these cases, the conventional flash memory device 10 may malfunction or may be unable to operate. However, in the prior art, these problems cannot be solved.