As the integration density of semiconductor devices has increased, the semiconductor devices are becoming gradually finer. The fine semiconductor devices are formed by repeatedly depositing and patterning material layers. In general, the patterning process comprises a photolithographic process and an etching process, which are sequentially performed. The etching process uses a photoresist pattern, formed during the photolithographic process, as an etch mask. Here, to enhance the integration density of a semiconductor device, the photoresist pattern should be finely formed and overlay accuracy should be improved. In particular, a junction contact hole for electrically connecting source/drains of semiconductor devices has an influence on the size of a unit cell. Thus, to achieve the high integration of semiconductor devices, it is imperative to increase the overlay accuracy during the step of patterning the junction contact hole.
In general, forming the junction contact hole comprises forming a device isolation layer for defining an active region on a semiconductor substrate, and forming a gate pattern on the active region to cross over the device isolation layer. Next, an interlayer dielectric (ILD) is formed to cover the entire surface of the semiconductor substrate including the gate pattern. The ILD is patterned to form a junction contact hole exposing the active region on a side of the gate pattern. As described above, the patterning process for forming the junction contact hole comprises forming a photoresist pattern and using the photoresist pattern as an etching mask. Here, the photoresist pattern should be aligned to the active region and the gate pattern with high overlay accuracy. If the junction contact hole deviates from a predetermined position while the junction contact hole is formed, the gate pattern or the device isolation layer may suffer from etching damages.
The etching damages can be prevented using techniques of sufficiently spacing the junction contact hole from the gate pattern or the device isolation layer. However, as the techniques lead the unit cell to occupy even an unnecessary area, they are not preferable in respect of the high integration of semiconductors. That is, to obtain the high integration necessary for the miniaturization of material patterns, the photolithographic process should have improved overlay accuracy as much as possible. However, although misalignment caused during the photolithographic process can be minimized, it cannot be completely solved with the conventional methods.