This invention relates to a method for fabricating a semiconductor device, and more specifically to a method for removing a poly-silicon residues around the etching pattern by graded etching of poly-silicon which acts as the electrode of the capacitor for a MOS-DRAM.
The fabricating method of the conventional MOS-DRAM is shown in FIG. 2 and will be explained below. First, a field oxide layer 2 and a capacitor dielectric (oxide) layer 3 are grown on a p-type single crystalline-silicon substrate 1 and then a poly silicon layer 4 for a first electrode is deposited as shown in FIG. 2(a). By plasma etching or RIE(Reactive Ion Etching), a restricted portion of said poly-silicon 4 is etched out as shown in FIG. 2(b), and then an oxide layer 6 is grown on the remaining portions of the poly-silicon 4 as shown in FIG. 2(c). A poly silicon layer 5 for a second electrode, which is used as a gate electrode of a MOS transistor, is deposited on the entire surface of the silicon substrate 1.
After etching restricted portions of said poly-silicon layer 5, the fabrication of MOS-DRAM is completed.
However, several problems to be solved remain in a conventional DRAM fabricating method. Since a restricted portion of the poly-silicon 4 for the first electrode of the capacitor is etched out by means of the plasma etching or RIE, using the etching pattern 11 of the poly-silicon layer for the first electrode as shown in FIG. 1, and hence the edges of the remaining part of the poly-silicon 4 have a right-angled section as shown in FIG. 2. For the isolation of the first poly electrode and the second poly electrode 5, the oxide layer 6 is grown on the poly-silicon layer 4. But the thickness of the grown oxide layer is not uniform and a recess 8 is formed on the bottom of the pattern edge as shown in FIG. 2(c).
The recess 8 is formed by the growth rate difference of the oxide layers on the surfaces between the silicon substrate 1 and the poly-silicon 4, because in the poly-silicon 4, the dopant is diffused in order to lower its resistance. The poly-silicon layer 5 for the second electrode is deposited on the entire surface of the silicon substrate 1 and by RIE method, the poly-silicon 5 is etched into the second electrodes 5' which will form the gates of the transistor. During this process, the residues 9 of the poly-silicon for the second electrode are remained in said recess 8. Since such the poly-silicon residues 9 are left in the recess around the first poly etching pattern 11 shown in FIG. 1, the second electrodes, which act as the gates of transistors, are shorted one another. Therefore, in order to prevent the poly-silicon from shorting, another pattern 12 in FIG. 1 for the removal of the residues is formed and another process step for the removal of the poly residues is necessary.