1. Field of the Invention
The present invention relates to an alternate-metal, virtual-ground (AMG) electrically-programmable read-only-memory (EPROM) and, in particular, to a method for preventing bit line-to-bit line leakage in the access transistor region of an AMG EPROM.
2. Discussion of the Related Art
An alternate-metal, virtual-ground (AMG) electrically-programmable read-only-memory (EPROM) is a non-volatile memory that, like conventional EPROMs and electrically-erasable programmable read-only-memories (EEPROMs), retains data which has been stored in the memory when power is removed and which, unlike conventional EPROMs and EEPROMs, uses a series of access transistors to contact the source bit lines of the array.
FIG. 1 shows a plan view that illustrates a portion of a conventional AMG EPROM array 10. As shown in FIG. 1, array 10 includes a series of memory cells 12, a series of access transistors 14, a series of metal bit line contacts MBL1-MBLn, and a series of field oxide regions FOX which isolate the access transistors 14 and metal bit line contacts MBL1-MBLn in the array.
In addition, the memory cells 12 in a row of memory cells share a common word line 16. As is well known, the portion of the word line 16 which is formed over each memory cell 12 in a row of memory cells functions as the control gate of the memory cells in that row. Similarly, the access transistors 14 in a row of access transistors share a common access select line 18.
As also shown in FIG. 1, each memory cell 12 and each access transistor 14 in a column of memory cells and access transistors share a source bit line SOURCE and a drain bit line DRAIN with the remaining memory cells and access transistors in the column, and with the memory cells 12 and access transistors 14 in the horizontally-adjacent columns. In a conventional AMG EPROM, the metal bit lines typically contact the drain bit lines DRAIN once every 2.sup.x cells (e.g., 32 or 64 cells) while, on the other hand, the source bit lines SOURCE are not contacted by a metal bit line.
During the fabrication process of an AMG EPROM, the drain and source bit lines DRAIN and SOURCE can be formed by utilizing a plurality of spaced-apart, parallel, dielectric/floating gate strips as an implant mask. As a result, the isolation between adjacent bit lines may be defined by the width of the dielectric/floating gate strips.
FIGS. 2A-2C show cross-sectional diagrams taken along lines 1A--1A, 1B--1B, and 1C--1C, respectively, that illustrate the formation of a plurality of dielectric/floating gate strips 20. As shown in FIGS. 2A-2C, the dielectric/floating gate strips 20 are initially formed by growing a layer of gate oxide 24 on a semiconductor substrate 22 which has a plurality of previously formed field oxide regions FOX.
Next, a layer of polysilicon (poly1) 26 is deposited over the layer of gate oxide 24 and the field oxide regions FOX, and then doped in a conventional manner. As is well known, the floating gates will be formed from the layer of poly1 26. After the layer of poly1 26 has been deposited, a layer of oxide-nitride-oxide (ONO) 28 is formed over the layer of poly1 26.
Following this, a photoresist mask 30 is formed and patterned to define a series of mask strips on the layer of ONO 28. FIG. 3 shows a plan view that illustrates a pair of mask strips 32 formed over the layer of ONO 28. As shown in FIG. 3, the ends of the strips 32 are formed over the edges of a field oxide region FOX, which also functions as an implant mask.
Once mask 30 has been formed, the unmasked layer of ONO 28 and the underlying layer of poly1 26 are then etched to form the dielectric/floating gate strips 20 from the composite layers of ONO 28 and poly1 26. The strips 20 and the field oxide regions FOX are then used as a self-aligned mask during an arsenic implant which defines the N+ bit lines 34 of the array.
FIGS. 4A and 4B show plan views that illustrate the structure that results after the formation of the bit lines 34. As shown in FIG. 4A, both the dielectric/floating gate strips 20 and the field oxide regions FOX are conventionally depicted as having square corners. In actual practice, however, as shown in FIG. 4B, both the resulting dielectric/floating gate strips 20 and the field oxide regions FOX have rounded corners.
One problem with utilizing the dielectric/floating gate strips 20 and the field oxide regions FOX as an implant mask is that, if mask 30 is slightly misaligned, the misalignment can cause the ends of the strips 20 to be only partially formed over the edges of the field oxide regions FOX. FIG. 5 shows a plan view that illustrates the structure that results after the formation of the bit lines 34 when mask 30 is slightly misaligned.
As shown in FIG. 5, when mask 30 is slightly misaligned, the width of the strips 20 at the edges of the field oxide regions FOX can be substantially reduced. As a result, the bit line-to-bit line isolation may also be substantially reduced. As the isolation between adjacent bit lines is reduced, the probability of bit line-to-bit line leakage increases.
Therefore, there is a need for a method that assures that the width of the dielectric/floating gate strips will be completely formed over the edges of the field oxide regions even when the mask that defines the dielectric/floating gate strips is misaligned, thereby insuring that the bit line-to-bit line isolation will remain constant.