This invention pertains to latch circuits and, in particular, to complementary direct-coupled FET logic (CDCFL) latch circuits.
Latch circuits have numerous applications and are well known in the art. A latch circuit typically consists of an acquire stage and a regeneration stage where data is clocked into the acquire stage when a clock is in first logic state and then stored in the regeneration stage when the clock is in a second logic state, as is known. Most technology has utilized two separate load devices within a latch circuit: one for providing current to the acquire stage and another for providing current to the regeneration stage. Furthermore, since each load device draws a predetermined current, the power of most field-effect transistor (FET) circuits is directly proportional to the number of load devices used therein. Therefore, if a single load device could be shared between two different field effect transistors, a substantial power reduction would result along with a decrease in device count.
Source-coupled FET logic (SCFL) technology has attempted to utilize shared load devices for various applications and circuits. However, SCFL technology, similar to ECL technology, requires the use of a current source coupled to the common sources of two field-effect transistors for operation. Furthermore, to operate SCFL with other FET logic, two separate voltage levels are needed to provide logic level compatibility.
DCFL technology has also attempted to utilize shared load devices and one example is fully disclosed in U.S. patent application entitled "DCFL LATCH HAVING A SHARED LOAD" having U.S. Ser. No. 516,632 and filed on Apr. 30, 1990. However, the above mentioned patent application teaches single-ended use only and does not teach nor suggest a complimentary latch of any kind.
Hence, a need exists for a complimentary direct-coupled FET logic (CDCFL) latch circuit having shared load devices which results in minimum power and minimum device count.