The fabrication of silicon integrated circuits was originally based upon thermally activated processes for both the deposition of material layers and their subsequent etching to form horizontally defined features. In a thermal process, the uniformity of deposition is dependent on the temperature of surfaces exposed to the process, and variations in the temperature cause a variation in the rate of the process. Such temperature dependence detracts from process repeatability. Because of the increasing complexity and decreasing feature sizes, more and more semiconductor processing is being performed in plasma reaction chambers. The plasma, rather than equilibrium heat, provides the necessary activation energy for various types of chemical processes and physical processes (sputter deposition and sputter cleaning), while still maintaining the silicon wafer at moderate temperatures so that deleterious thermally driven subsidiary effects are avoided. That is, an increased number of fabrication steps can be performed without producing deleterious effects due to temperature, both the maximum temperature and the integrated thermal profile.
Some early plasma reactors, particularly for etching and chemical vapor deposition (CVD) of single wafers, resemble the reactor illustrated in FIG. 1. A wafer 50 is supported on a pedestal 52 enclosed within a vacuum chamber 54 having metallic walls 55, which are grounded. An RF electrical power supply 56 is connected to the pedestal 52 to excite a plasma of the gas supplied into the interior of the chamber 54. The grounded chamber walls 55 act as a counter electrode to the pedestal 52. The plasma-excited gas acts upon the wafer 50 to either etch it or to deposit a product of a plasma-activated reaction upon it. The pedestal 50 and chamber walls 55 act as two electrodes to capacitively couple RF energy into the plasma.
The geometry dictates that the RF-driven pedestal 50 acts as a cathode and the large grounded chamber wall 55 acts as an anode. As discussed by Lii in "Etching", ULSI Technology, eds. Chang et al. (McGraw-Hill, 1996), pp. 330-333, the pedestal 50 develops a negative DC potential V.sub.a relative to the grounded wall 55 of magnitude given by ##EQU1##
where V.sub.p is the plasma potential, typically on the order of a hundred volts positive or less, A.sub.a is the surface area of the chamber wall 55 adjacent to the plasma, and A.sub.c is the area of the top surface of the pedestal 50. In the common case of FIG. 1 with a small RF-powered cathode 52 and a large grounded anode 54, the area ratio is quite large and the cathode voltage V.sub.c is negative because the DC plasma voltage is always positive. Thus, the equation can be simplified to ##EQU2##
It is thus seen that for large grounded chamber walls surrounding the plasma, the voltage V.sub.c on the pedestal 50 can reach several hundred negative volts relative to both the plasma and the chamber wall 50, creating a significant diode effect and causing positive ions in the plasma to strike the wafer on the pedestal 50 at high energy.
As wafer sizes have increased and demands for uniformity have intensified, the chamber geometry has changed to present a more planar geometry. See, for example, U.S. Pat. No. 4,892,753 to Wang et al. for a CVD chamber and U.S. Pat. No. 4,948,458 to Ogle for an etch chamber. As illustrated in FIG. 2, a counter electrode 58 is positioned opposite to the pedestal 52 and its supported wafer 50 across a gap that is substantially less than the diameter of the wafer 50. For example, the gap may be a few centimeters for a 200 mm wafer. The counter electrode 58 is typically grounded for etch applications while the RF powering configuration is usually reversed for CVD. Often the counter electrode 58 includes a shower head gas dispenser to uniformly supply reaction gas to the reaction zone adjacent to the wafer 50. In this design, the walls of the chamber 54, although usually grounded, assume less importance in the plasma and the chemical reactions.
Chapman discusses the sheath voltages for the symmetric configuration in Glow Discharge Processes: Splittering and Plasma Etching (Wiley-Interscience, 1980), pp. 156-171. He also gives a more general version of Equation (1) which does not assume a grounded cathode, ##EQU3##
where V.sub.1, and A.sub.1, are the DC self-bias and the area of the first electrode and V.sub.2 and A.sub.2 are the corresponding values for the second electrode.
Ogle et al. in the U.S. Pat. No. 4,871,421 teaches the advantages of splitting RF power in a 50:50 ratio between the pedestal 52 and the counter electrode 58 with respect to the grounded chamber wall 54 so as to avoid arcing to the chamber walls. In the Ogle reference we observe vastly different sizes of the counter electrode and pedestal electrode, such as shown in FIG. 1. Such a difference in the electrode sizes creates the above described diode effect even for split RF power. Again, the differently sized electrodes cause high-energy charged ions to be ejected across the sheath of the plasma, causing increased physical sputtering (ion etching) rather than purely chemical activation.
Recent developments in plasma reaction chambers have been directed to high-density plasma (HDP) reactors in which large amounts of RF energy create a plasma having a very high ion density, typically above 10.sup.11 cm.sup.-3. HDP reaction chambers provide high deposition and etching rates as well as other advantages. There are several types of HDP reaction chambers, but the most popular involve induction coupling of RF energy into the source plasma. Inductively coupled plasma reaction chambers can be divided into three main types.
The first type, as illustrated in FIG. 3, includes a helical coil 60 wrapped around a dielectric sidewall 62, typically of quartz, and powered by an RF electrical source 64. The pedestal 52 continues to have its own RF source 56. For oxide etching, a counter electrode 66 is grounded and is composed of silicon in order to scavenge fluorine from the fluorocarbon plasma gas performing the etching. This approach is described generally by Collins et al. in U.S. Pat. No. 5,556,501 and European Patent Application 552,491. A1 and Rice et al. describe a specific embodiment in U.S. Pat. No. 5,477,975. Their specific embodiments will be described later in more detail in FIGS. 7 and 8. The configuration including a helical coil necessarily increases the size of the walls surrounding the sides of the plasma region. As a result, unlike in reactors with closely spaced capacitive electrodes, wall interactions become important both for forming the plasma and for the deposition or etching chemistry.
The second type of inductively coupled plasma reactor chambers, as illustrated in FIG. 4, includes a planar, spiral coil 70, often referred to as a pancake coil or stove top coil, placed outside a top, planar dielectric wall 72 to be close and parallel to the wafer 50. The pancake coil 70 is similarly powered by the RF source 64 to inductively couple power into the chamber plasma. For process control, the pedestal 52 may be RF biased. In the closely spaced configuration of FIG. 4, the chamber walls 74, which are typically conductive and grounded, are effectively decoupled from the plasma and its chemistry because of their physical displacement and small size relative to the closely spaced planar coil 70 and pedestal 52. Examples of the pancake coil are disclosed by Ogle in the aforecited patent and by Marks et al. in European Patent Application 601,468-A1.
The third type of inductively coupled plasma reactor chamber, as illustrated in FIG. 5, includes a hemispherical dielectric dome 80 positioned above the wafer 50. A concave spiral inductive coil 82 conformally following the shape of the doubly concave dome 80 is coupled to the RF power source 64. Its shape closely follows the shape of the hemispherical dome. As should be recognized, the hemispherical geometry of FIG. 5 is intermediate between the cylindrical geometry of FIG. 3 and the planar geometry of FIG. 4. Benzing et al. have disclosed the hemispherical coil in U.S. Pat. Nos. 5,346,578 and 5,405,480, and Sahin et al. have disclosed a similar but radially multi-curvature CVD reactor in European Patent Application 680,072-A2.
All these chamber geometries present respective advantages and disadvantages. It should be noted that the inductive coupling of these various embodiments relies upon the coils 60, 70, 82 driven by their respective RF sources to induce an RF magnetic field within a portion of the reaction chamber containing the excited plasma. The RF magnetic field induces an orthogonal electric field according to Faraday's law of induction ##EQU4##
As a result, the oscillating magnetic field, which generally lies at least partially along the axial chamber direction in the cases of the cylindrical and doubly concave domes, produces a rotary electric field within the plasma, that is, an electric field loop extending around the axial magnetic field and the electric field that closes on itself. This is alternatively called an azimuthal field since it has circular shape in a generally cylindrical geometry. The electrons circulating in the plasma along the rotary electric field lines collide with the plasma ions to keep the plasma in an excited state.
In free space, the solenoidal (cylindrical) coil 60 of FIG. 3 provides a uniform axial magnetic field that would be desirable for uniform etching or deposition on the relatively large wafer 50. However, the plasma created by the RF magnetic field effectively shields the inner portions of the plasma inside the cylindrical chamber 62, especially at higher chamber pressures. As a result, the plasma density for the cylindrical geometry of FIG. 3 tends to droop at the center. The planar pancake coil 70 of FIG. 4 potentially avoids this problem by inducing an RF magnetic field across the radius of the cylindrical chamber. While the pancake coil offers some advantages for planar uniformity, it also presents a difficult configuration for inductive coupling, since the magnetic field lines created by the pancake coil need to close on themselves, a disadvantageous electromagnetic configuration, especially near the center.
The third type of inductive coupling involving a curved-dome configuration illustrated in FIG. 5 combines advantages of the first two types. The hemispherical coil 82 of FIG. 5 attempts to combine the advantages of the other two approaches. The geometry resembles the electromagnetically favorable helical coil, but a substantial amount of power is coupled into the plasma above the central region of the wafer. Also, insofar as diffusion of species excited by the immediately adjacent coil 82 is important, all parts of the wafer 50 are generally equidistant from the coil 82. Sahin et al. in the previously cited application have suggested multiple radial curvatures for the dome that could be used to further improve the uniformity. However, the curvilinear dome of FIG. 5, while offering superior processing capability, presents several mechanical problems. A curvilinear dome is difficult to form whether by casting or machining. Further, the dome needs to be temperature controlled by heating and cooling elements in intimate contact within the dome. Unfortunately, differential thermal expansion between the dome and the thermal control elements tend to disrupt effective thermal contact between them over the two-dimensionally curved surface. Further, although a pure dome is mechanically strong, it is sometimes desirable to include a planar counter electrode at the top of a truncated dome, see Sahin et al. The resultant truncated curvilinear dome is structurally weak, and structural integrity is becoming increasingly important for a vacuum chamber of larger size necessary to enclose 200 mm and 300 mm wafers.
Collins et al. in U.S. patent application, Ser. No. 08/648,254, filed May 13, 1996 have suggested using a conical spiral coil, but the base of the cone is placed adjacent to a flat roof of the chamber, with the result that a large portion of the spiral coil is displaced far away from the chamber, thus decreasing RF coupling into the plasma.
The portions of an inductively coupled plasma chamber adjacent to the inductive coil are in the prior art typically made of quartz. Although a metal (electrically conductive) wall would generally pass the magnetic field that the coil couples into the chamber, the circulating RF currents dictated by Equation (4) would be set up in the metal wall as well as in the plasma. Hence, the chamber wall is generally formed of a dielectric (electrically insulating) material.
Quartz has always been favored for walls of a plasma reactor, especially for semiconductor processing equipment. Quartz can be made in very pure form. Its chemical composition is essentially silica (SiO.sub.2), which is usually compatible with silicon processing. Other commonly available ceramics, i.e., alumina (A1.sub.2 O.sub.3) or sintered silicon carbide (SiC), commonly contain elements having uncertain effects on silicon chemistry and semiconducting characteristics.
Quartz however presents problems in advanced plasma reactors, especially oxide etchers for the semiconductor industry. Oxide etchers must etch the insulating layers of the substrate being processed, particularly layers of SiO.sub.2. As a result, the very chemistry that effectively etches the wafer being processed can also effectively etch the quartz wall. Furthermore, quartz tends to be a dirty material when it is etched since it is formed of small crystallites joined in a matrix. When quartz is etched, the etching tends to accelerate in localized areas between the crystallites so as to undercut the unetched crystallites, which are then liberated from the matrix and become particulates, which can eventually settle on the wafer. Particle contamination is an increasing problem as the feature sizes of integrated circuits shrink and the number of circuit elements increases.
The etching of advanced integrated circuits, particularly oxide etching, has many severe requirements. Vias and contacts etched through oxide layers need to be narrow and deep, having aspect ratios of over 1:1 and sometimes 5:1 and greater. Etching is required that is highly anisotropic and very highly selective for silica over silicon. The thin layers require that the etching be highly selective to the underlying silicon so that the etching stops once the oxide layer has been etched through. The increased size of wafers has intensified the problem of uniformity of etching over the wafer.
Collins et al. disclose in the previously cited European application that the desired selectivity can be achieved by using a fluorocarbon etching gas, such as CF.sub.4, C.sub.2 F.sub.6, or C.sub.3 F.sub.8 or a hydrofluorocarbon such as CHF.sub.3 in combination with a silicon-containing counter electrode placed over the wafer in order to scavenge fluorine from the fluorocarbon plasma. This process deposits a polymer over silicon but does not deposit it over silicon dioxide, thus protecting the silicon from etching once it is exposed. A similar differential polymer deposition on the walls of a via through silica produces nearly vertical sidewalls. As postulated by Rice in U.S. Pat. No. 5,477,975 and in U.S. patent application Ser. No. 08/524,135, filed Sep. 5, 1995, that process includes a dependency upon temperature, not only of the wafer, but also of the silicon counter electrode and of other chamber components among other process factors which may be involved.
Reaction rates generally vary as a power of the temperature, usually in the range of T.sup.2 to T.sup.3, and, in the spatially differential reaction process of selective etching, variations in temperature can drive the process between etching and depositing upon the various parts. For example, a start-up effect has been observed when a chamber is first turned on, say at the beginning of the day or after routine maintenance. Curve 90 in FIG. 6 shows the etching rate for silicon dioxide and curve 92 shows the corresponding etching rate for photoresist, both as a function of the number of wafers processed after the start of processing. The oxide etching rate increases with wafer number while the photoresist etching rate falls. Only after about 25 wafers have been processed do the rates approach steady-state values. It is believed that the variations reflect the rise of temperature of components within the chamber interior caused by the plasma processing. The effect can be circumvented by using dummy wafers for the first run of the day, but this significantly reduces throughput. Also, lesser temperature variations can occur when the processing is interrupted for minor equipment failures or because wafers are not immediately available. Hence, the temperature of many parts of the chamber need to be tightly controlled. Some past designs have attempted to control wall and component temperatures, but these designs need to be improved.
Furthermore, quartz presents a fundamental materials problem. It is a ceramic with poor thermal conductivity, typically in the range of 0.5 W/m-.degree. C. Even if a temperature control body (heater/cooler) is applied to the exterior of the quartz chamber wall, the temperature of the wall side facing the reaction chamber may still be poorly controlled. This problem is exacerbated by the configuration of the cylindrical design of FIG. 3. A detailed embodiment of this configuration is illustrated in the cross-sectional view of FIG. 7 and the detailed cross-sectional view of FIG. 8. A cylindrical chamber wall 100 is surrounded by a cylindrical temperature control jacket 102, in this case accommodating an solenoidal RF coil 104. The cylindrical chamber wall 100 rests on a lower chamber 106, generally a massive body machined from aluminum, and the upper part of the cylindrical chamber wall 100 supports a roof 108, which for oxide etching is preferably in the prior art composed of polysilicon. An RF connector 110 supplies RF power to the roof 108. A heater plate 112 is pressed against the top of the roof 108 and contains a spiral resistive heater powered through two electrical connectors 114, 116. A chilling assembly is pressed against the top of the heater plate 112 and includes a chilling plate 118 having at least one spiral groove 120 formed in it for a cooling fluid, such as chilled water. A cover plate 122 covers and seals the groove 120.
Referring to FIG. 8, an annular resistive heater 122 is embedded in a groove 124 at the bottom of the jacket 102 to selectively heat the jacket 102 and hence the chamber wall 100, particularly when the RF coil 104 is not energized.
An assembly gap 126 is formed between the chamber wall 100 and the thermal jacket 102 when the two are put together. The assembly gap 126 is required for two reasons, the need to slide the parts together during assembly and the inevitable differential thermal expansion between the two parts 100, 102. If the assembly gap 126 were absent, assembly would require complex procedures, and the parts, once assembled, would tend to crush each other under a sufficient difference in temperature. The assembly gap 126 creates a region across which thermal energy is poorly transferred, when compared with heat conduction in a conductive material. The rate of heat transfer is dependent on the size of the gap 126 and the pressure of the gas within the gap 126. That is, thermal expansion create variations in the gap and the resulting heat transfer rate across the gap. Further, the gap between cylindrical components is generally not equally distributed around the cylindrical shape because of inevitable asymmetries, but is smaller on one side than on the other side. The variation in the gap causes a variation in the rate of heat transfer between the cylindrical bodies depending on size of the adjacent gap. Thus, the rate of heat transfer at different locations around the wall differs depending on the size of the adjacent gap. Furthermore, the cylindrical chamber wall has typically been made of quartz, a poor thermal conductor. These variations render the use of conventional modes of temperature control in this configuration less effective than desired when precise temperature control in a small range of temperature is required.
The cylindrical chamber of FIG. 7 results in the general geometry of FIG. 9 of a cylindrical sidewall 124 and a top 126 of generally the same diameter. The diameter of a wafer area 128 is necessarily smaller than that of the chamber sidewall 124 and its top 126. The cylindrical sidewall 124 is good for supporting the vacuum-loaded weight of the top 126, but, as the top 126 extends over larger spans for large substrates, such as 300 mm wafers, it is prone to bend inwardly unless made excessively thick.
In the past, when chamber components have been replaced, in addition to the cold-start phenomenon, additional wafer cycling has been required to return the process to its baseline process performance. It is assumed that the new parts require some conditioning to achieve their final effect. Temperature instability due to the use of new components having new component interfaces is at least partially to blame for the need for additional thermal cycling to eliminate process drift and return the process to a baseline performance standard.