One of the persistent challenges faced in the development of semiconductor technology is the desire to increase the density of circuit elements and interconnections on substrates without introducing spurious interactions between them. Unwanted interactions are typically prevented by providing gaps or trenches that are filled with electrically insulative material to isolate the elements both physically and electrically. As circuit densities increase, however, the widths of these gaps decrease, increase their aspect ratios and making it progressively more difficult to fill the gaps without leaving voids. The formation of voids when the gap is not filled completely is undesirable because they may adversely affect operation of the completed device, such as by trapping impurities within the insulative material.
Common techniques that are used in such gapfill applications are chemical-vapor deposition (“CVD”) techniques. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD (“PECVD”) techniques promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes when compared with conventional thermal CVD processes. These advantages may be further exploited by high-density-plasma (“HDP”) CVD techniques, in which a dense plasma is formed at low vacuum pressures so that the plasma species are even more reactive. While each of these techniques falls broadly under the umbrella of “CVD techniques,” each of them has characteristic properties that make them more or less suitable for certain specific applications.
In some instances where gaps have a large aspect ratio and narrow width, gaps have been filled with thermal CVD techniques using a “dep/etch/dep” process by sequentially depositing material, etching some of it back, and depositing additional material. The etching step acts to reshape the partially filled gap, opening it so that more material can be deposited before it closes up and leaves an interior gap. Such dep/etch/dep processes have also been used with PECVD techniques, but some thermal and PECVD techniques are still unable to fill gaps having very large aspect ratios even by cycling deposition and etching steps.
Dep/etch/dep processes have also been shown to improve gapfill in HDP-CVD processes. Originally, the application of dep/etch/dep processes to HDP-CVD was considered counterintuitive because, unlike PECVD processes, the high density of ionic species in the plasma during HDP-CVD processes already causes there to be sputtering of a film while it is being deposited. This simultaneous sputtering and deposition of material during a deposition process tends to keep the gap open during deposition, and was therefore believed to render a separate intermediate etching step superfluous. Nevertheless, in U.S. Pat. No. 6,194,038, filed Mar. 20, 1998 by Kent Rossman, the unexpected result was demonstrated that gapfill could be improved even further by using a dep/etch/dep process under certain HDP-CVD process conditions. This result was later confirmed in U.S. Pat. No. 6,030,181, filed May 5, 1998 by George D. Papasouliotis et al.
However, even for processes that combine HDP-CVD and dep/etch/dep for dielectric gapfills, there are still limits on the size and aspect ratios of the gaps that can be filled. For example, small gaps with high aspect ratios may need to undergo an impractical number dep-etch cycles to keep the top portion of the gap from overfilling with dielectric material. The increased frequency and duration of the etch cycles presents a possibility of damaging the structures that define the gaps to be filled. This possibility exists when insufficient material is deposited during the prior deposition and/or when too much of the deposited material is removed during the etching step. Optimization of a recipe is hindered by the fact that individual chamber characteristics and/or individual wafer characteristics may affect the deposition and etching. As the trend towards more densely packed devices continues, it will be desirable to find new methods of depositing dielectric materials into the gaps that can accommodate their increasing aspect ratios.