The present invention relates to a parallel comparator and an A/D converter.
Such a circuit as is shown in FIG. 1 is examined as a parallel comparator to be used in an A/D converter by the Inventor. This circuit is made into a two-stage differential amplifier so as to steepen the switching characteristics, i.e., to increase the gain.
Therefore, that circuit has defects that the number of circuit constituting elements is large and that the power consumption is increased.
Moreover, since comparator outputs OUT.sub.1 to OUT.sub.3 respectively vary with reference to reference voltages V.sub.1 to V.sub.3, there arises another defect in that the logic circuit construction in the case of conversion into digital signals of binary code is complicated.
Since the A/D converter constructed as a monolithic or hybrid IC has its circuit construction fixed, it is convenient to extend the output bits.