This invention relates generally to demultiplixers and particularly to a single stage circuit which functions as a two stage demultiplexer. In its broader aspects the circuit can be used as a three state gate.
Liquid crystal television and computer displays (LCDs) are known in the art. For example, see U.S. Pat. Nos. 4,742,346 and 4,766,430, both issued to G. G. Gillette et al. and incorporated herein by reference. Displays of the type described in the Gillette patents include a matrix of liquid crystal cells which are arranged at the crossovers of data lines and select lines. The select lines are sequentially selected to produce the horizontal lines of the display. The data lines apply the brightness signals to the columns of liquid crystal cells as the select lines are sequentially selected. Each liquid crystal cell is associated with a switching device through which a ramp voltage is applied to the liquid crystal cells in the selected line. Each of the switching devices is held on by a comparator, or a counter, which receives the brightness (grey scale) signal to permit the ramp voltage to charge the associated liquid crystal device to a voltage proportional to the brightness level received by the comparator from the data line. When the display is a color television display, the incoming signal is analog and must be digitized. Each data line of the display must therefore be associated with a demultiplexer having a sufficient number of stages to apply all data bits of the digitized brightness signal to the comparator for that line.
In the prior art two stage demultiplexers are utilized in order to reduce the lead count. For example, a display having a thousand data lines and eight bits of grey scale requires loading a total of eight thousand pieces of information for each image line and would require 180 leads (two times the square root of eight thousand). Even with an optimized single stage demultiplexer this is an excessive lead count. A two stage demultiplexer substantially reduces the lead count by a cube root relationship, instead of a square root relationship (three times the cube root of eight thousand). The lead count is thus reduced from 180 to 60 by the use of two stage demultiplexing.
A prior art two stage demultiplexing circuit is shown in FIG. 1. The demultiplexer 10 includes N sections 15-1 through 15-N, one for each bit of the digital word. Each section 15 includes a data input terminal 11, a capacitor 12, an input node 13, an intermediate node 14 and output nodes 16. The capacitor 12 stores the input data signal to keep node 13 at the data input level. Additional capacitors 17 and 18 keep nodes 14 and 16 respectively at their applied voltage levels. Each data input section 15 has a most significant bit (MSB) stage including a plurality of transistors 19 equal in number to the number of MSB lines (three of which Mi, M2, M3 are shown) in the stage. The control electrode of each transistor is connected to one of the MSB lines M. Each data input section 15 also has a least significant bit stage (LSB) including a plurality of transistors 21 equal in number to the number of LSB lines (four of which L1 to L4 are shown) in the stage. The control electrode of each transistor 21 is connected to one of the LSB lines L. Transistors 19 and 21 preferably are thin film transistors (TFT's). The conduction path of each MSB TFT 19 is connected in series with the conduction paths of all of the LSB TFT's 21. Accordingly, each input signal is connected to an output line through two TFT's. Thus, when an MSB line and an LSB line are simultaneously high current flows from input node 13 to an output node 16 through the conduction paths of the conductive TFT's. For example, when MSB line M2 and LSB line L3 are simultaneously high, transistors 19-2 and 21-3 are on and current flows from input node 13 to output node 16.
In a full voltage swing situation, the slow down caused by the drain to source impedance of two TFT's in series is approximately a factor of two, that is, approximately half as much current flows through the serial combination and it takes approximately twice as long to charge node 16. However, in high speed applications, such as those for LCD displays, the time available for signal transfer is very short and the signal swings on node 14 are not the full voltage swing. The full impact of a serial transistor combination in a high speed display therefore is much worse than a factor of two. In FIG. 2, the data input voltage 22 has a sharp rise and then is substantially flat. The voltage 23 on node 14 rises approximately linearly with time. However, the voltage 24 on node 16 rises much more slowly than that on node 14. This is because the current passing through the least significant bit decoder stage to output node 16 is proportional to the voltage on node 14, which rises approximately linearly with time. The actual voltage on output node 16 rises as a function of the square of time. Accordingly, for the short time period available for voltage transfer in LCD applications the signal coupled to node 16 is very small. The frequency response of this demultiplexer arrangement is therefore limited.
For these reasons there is a need for a single stage demultiplexer which enables the reduction in input line count that a two stage demultiplexer permits while simultaneously allowing the speed of operation necessary for LCD and other types of display devices. The present invention fulfills these needs.