Q:

Intel x86 to ARM assembly conversion

I am currently learning ARM assembly language; 
To do so, I am trying to convert some x86 code (AT&T Syntax) to ARM assembly (Intel Syntax) code.
__asm__("movl $0x0804c000, %eax;");

__asm__("mov R0,#0x0804c000");

From this document, I learn that in x86 the Chunk 1 of the heap structure starts from 0x0804c000. But I when I try do the same in arm,
 I get the following error:
/tmp/ccfNZp9F.s:174: Error: invalid constant (804c000) after fixup

I am assuming the problem is that ARM can only load 32bit instructions. 
Question 1: Any idea what would be the first chunk in case of ARM processors?

Question 2:

From my previous question, I know how memory indirect addressing works. 
Are the snippets written below doing the same job?
movl (%eax), %ebx

LDR R0,[R1]

I am using ARMv7 Processor rev 4 (v7l)

A:

Trying to learn arm by looking at x86 is not a good idea one is CISC and quite ugly the other is RISC and much cleaner..  Just learn ARM by looking at the instruction set reference in the architectural reference manual.  Look up the mov instruction the add instruction, etc.
ARM doesnt use intel syntax it uses ARM syntax.
Dont learn by using inline assembly, write real assembly.  Use an instruction set simulator first not hardware.
ARM, Mips and others aim for fixed word length.  So how would you for example fit an instruction that says move some immediate to a register, specify the register, and fit the 32 bit immediate all in 32 bits?  not possible.  So for fixed length instruction sets you cannot simply load any immediate you want into any register.  You must read up on the rules for that instruction set.  mips allows for 16 bit immediates, arm for 8 plus or minus depending on the flavor of arm instruction set and the instruction.  mips limits where you can put those 16 bits either high or low, arm lets you put those 8 bits anywhere in the 32 bit register depending on the flavor of arm instruction set (arm, thumb, thumb2 extensions).
As with most assembly languages you can solve this problem by doing something like this
ldr r0,my_value
...
my_value: .word 0x12345678

With CISC that immediate is simply tacked onto the instruciton, so whether it 0 bytes a way or 20 bytes away it is still there with either approach.
ARM assemblers also generally allow you this shortcut:
ldr r0,=something
...
something:

which says load r0 with the ADDRESS of something, not the contents at that location but the address (like an lea)
But that lends itself to this immediate shortcut
ldr r0,=0x12345678

which if supported by the assembler will allocate a memory location to hold the value and generate a ldr r0,[pc,offset] instruction to read it.  If the immediate is within the rules for a mov then the assembler might optimize it into a mov rd,#immediate.

A:

Answer to Question 1
The MOV instruction on ARM only has 12 bits available for an immediate value, and those bits are used this way: 8 bits for value, and 4 bits to specify the number of rotations to the right (the number of rotations is multiplied by 2, to increase the range). 
This means that only a limited number of values can be used with that instruction. They are:

0-255
256, 260, 264,..., 1020
1024, 1040, 1056, ..., 4080
etc

And so on. You are getting that error because your constant can't be created using the 8 bits + rotations. You can load that value onto the register following instruction:
LDR r0, =0x0804c000

Notice that this is a pseudo-instruction though. The assembler will basically put that constant somewhere in your code and load it as a memory location with some offset to the PC (program counter). 
Answer to question 2
Yes those instructions are equivalent.

