In an Advanced Super Dimension Switch (thereinafter, referred to as ADS) mode display device, all liquid crystal molecules located between and right above slit electrodes in a liquid crystal layer are enabled to rotate by means of an electric field generated by edges of the slit electrodes arranged in the same plane and a multi-dimensional electric field formed between a slit electrode layer and a plate electrode layer, so as to improve light transmittance of the liquid crystal layer and achieve a relatively wide angle of view.
FIG. 1 is a schematic diagram of an array substrate in an existing ADS display device, and in FIG. 1, in order to clearly illustrate a via hole penetrating through an etch stop layer, a structure located above the etch stop layer is not shown, or a portion, located above the via hole, of the structure located above the etch stop layer is not shown; FIG. 2 is a schematic cross-sectional diagram of a thin film transistor in the array substrate shown in FIG. 1. As shown in FIGS. 1 and 2, the array substrate 1 includes a substrate 10 and thin film transistors (TFT) 11, common electrodes 12, pixel electrodes 13, gate lines 14 each used for providing a voltage signal to a gate 110 of the thin film transistor 11, data lines 15 each used for providing a voltage signal to a source 114 of the thin film transistor 11 and common electrode lines 16 each used for providing a voltage signal to the common electrode 12 that are all formed above the substrate 10 (in direct or indirect contact with a surface of the substrate 10). Here, the pixel electrode 13 is located above the common electrode 12 (i.e., the common electrode 12 is located between the pixel electrode 13 and the substrate 10), the common electrode 12 is a plate electrode, and the pixel electrode 13 is a slit electrode. The thin film transistor 11 includes a gate 110, a gate insulation layer 111, an active layer 112, an etch stop layer (ESL) 113, a source 114 and a drain 115, and a passivation layer 116 that are sequentially formed above the substrate 10. Specifically, source holes 1130 and a drain hole 1131 that penetrate through the etch stop layer 113 are formed at positions of the etch stop layer 113 corresponding to the active layer 112, respectively. As shown in FIG. 1, in each thin film transistor 11, there may be two source holes 1130, the source holes 1130 and the drain hole 1131 are commonly referred to as ESL holes, and the source 114 and the drain 115 are formed by depositing a source-drain metal (SD metal) at the source holes 1130 and the drain hole 1131, respectively. The common electrode 12 and the common electrode line 16 may be formed on the surface of the substrate 10. Connecting holes 1133 penetrating through the etch stop layer 113 and the gate insulation layer 111 are formed above both the common electrode line 16 and the common electrode 12, and a conducting wire may be formed by depositing a conductive material (the SD metal, in general) on a surface of the etch stop layer 113 between the connecting hole 1133 located above the common electrode line 16 and the connecting hole 1133 located above the common electrode 12, so as to connect each common electrode 12 to the common electrode line 16, and to connect a plurality of common electrodes 12 to each other as well. Specifically, a material for forming the active layer 112 may be Indium Gallium Zinc Oxide (thereinafter, referred to as IGZO).
In forming the above-mentioned array substrate 1, the substrate 10 will be subject to friction, movement, adsorption, pressure, separation, heating and cooling continuously, and as a result, static electricity is generated on the substrate 10, that is, a large amount of electrostatic charges accumulate on the surface of the substrate 10. Under certain circumstance, a large amount of static electricity will be released, thus resulting in damage to some structure(s) on the array substrate 1. For example, in the process of forming the etch stop layer 113 (i.e., ESL mask) through exposure and development, electrostatic discharge will occur, and in the process of etching the etch stop layer 113 to obtain the ESL holes and the connecting holes 1133, intensity of the electrostatic discharge will be further increased, which may result in abnormal ESL holes and connecting holes 1133. Furthermore, static electricity generated between the gate 110/gate line 14 and the active layer 112 will discharge at the ESL holes (the source holes 1130 and the drain hole 1131) to damage structures at the ESL holes. Also, static electricity generated between the conducting wire connecting the common electrode 12 to the common electrode line 16 and the common electrode 12/the common electrode line 16 will discharge at the connecting holes 1133. In this case, sources of the static electricity discharging at the ESL holes and at the connecting holes 1133 are different, and therefore, the intensities of electrostatic discharge at the connecting holes 1133 and the ESL holes may differ significantly, and therefore, a relatively large voltage difference may exist between a connecting hole 1133 and the ESL hole closest to said connecting hole 1133. In this case, the connecting hole 1133 and the ESL hole actually form a capacitor, and as a result of the relatively large voltage difference, both of the holes are more likely to be broken down, which will generally cause the ESL hole closest to the connecting hole 1133 to be abnormal. As shown in FIG. 3, if the active layer 112 and the gate insulation layer 111 at the ESL hole are broken down, in the subsequent manufacturing process, SD metal will be deposited on the gate 110 when depositing the SD metal into said ESL hole. That is to say, the source 114 or drain 115 is short-circuited with the gate 110, and this will result in a bright line or gradient bright line that is generally horizontal, vertical or crosswise, on the ADS display device, thereby influencing product quality and lowering product yield.