It is known in the prior art to drive a flat panel display using a pulse width modulation (PWM) technique. The pulse width of a drive signal is modulated to control the brightness of the flat panel display. The pulse width modulation is implemented using a PWM clock. First, an n-bit video word is fed to a signal generator, which has n inputs for receiving the n bits. The signal generator generates one output control signal per video word. The output control signal controls the drive signal.
A drive signal is applied to each column of the display while an individual row is addressed for a duration equal to a line time. Typically, the number, n, of bits in the video word determines the number of cycles of the PWM clock during the display line time. Specifically, the number of cycles is equal to 2.sup.n. Thus, for an 8-bit video word the PWM clock cycles through 256 cycles. A typical value for the line time is on the order of tens of microseconds. Thus, use of an 8-bit video word results in a very short PWM clock cycle. The characteristic response time of certain display systems is such that the rise and fall times of the drive signals become significant, so that a very short PWM clock cycle can adversely affect display performance. While an 8-bit video word is useful for encoding a large number of brightness levels, it would be preferable to have a longer PWM clock cycle. Furthermore, the drivers typically used for processing 8-bit video word data are complex and costly.
Accordingly, there exists a need for an improved method for driving a pulse-width modulated flat panel display, which relaxes rise and fall time requirements and which utilizes simpler and less costly driver configurations.