1. Field of the Invention
This invention relates to semiconductor memory devices, and more particularly, to a ROM (read-only memory) device of the type consisting of a plurality of MOS (metal-oxide semiconductor) transistor memory cells and a method for fabricating the same. It is a distinctive feature of this invention that a thick insulating layer is used to separate the bit lines from the word lines of the ROM device such that the parasitic capacitance therebetween the same can be reduced.
2. Description of Related Art
Read-only memory (ROM) is a nonvolatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information including programs and data that are repeatedly used, such as the BIOS (abbreviation for Basic Input/Output System, a widely used operating system on personal computers) or the like. The manufacture of ROMs involves very complicated and time-consuming processes and requires costly equipment and material to achieve. Therefore, the information to be stored in ROMs is usually first defined by the customer and then furnished to the factory to be programmed into the ROMs.
The feature size of ROMs is dependent on the semiconductor fabrication technology. Conventional ROMs are formed by an array of MOSFETs (metal-oxide semiconductor field-effect transistor), each MOSFET being associated with one single memory cell of the ROM device. The binary state of each MOSFET is dependent on a particular electrical characteristic of the MOSFET, for example the threshold voltage of the MOSFET. If the channel of a MOSFET is doped with high-concentration impurities, the threshold voltage of this MOSFET will be reduced to a low level less than the gate voltage, thus setting the MOSFET to a permanently-ON state representing a first binary value, for example 0. On the other hand, if not doped with impurities, the threshold voltage will remain at a top level greater than the gate voltage, thus setting the MOSFET to a permanently-OFF state representing another binary value, for example 1. This conventional method for assigning binary data to the memory cells of a ROM device will be described in more detail in the following with reference to FIGS. 1 through 3.
Referring to FIG. 1, there is shown a schematic top view of a conventional ROM device. This ROM device is formed with a plurality of substantially parallel-spaced diffusion regions which serve as a plurality of buried bit lines 12a, 12b, 12c beneath a plurality of field oxide layers 100. Further, a plurality of word lines (WL1, WL2) 18, 18' are formed in such a manner as to intercross the bit lines 12a, 12b, 12c at right angles. The intersections between the bit lines 12a, 12b, 12c and the word lines WL1, WL2 are the locations where the memory cells of the ROM device are formed. For instance, a first memory cell 16a is formed on the word line WL2 between the bit lines 12a, 12b; a second memory cell 16b is formed on the word line WL2 between the bit lines 12b, 12c; a third memory cell 16c is formed on the word line WL1 between the bit lines 12a, 12b; and a fourth memory cell 16d is formed on the word line WL1 between the bit lines 12b, 12c. The binary data that are permanently stored in these memory cells 16a, 16b, 16c, 16d are dependent on the concentration of the associated diffusion regions. For instance, the N.sup.+ regions in FIG. 1 represent that the associated memory cells 16a, 16d are set to a permanently-ON state; and on the other hand, the memory cells 16b, 16c are set to an permanently-OFF state.
FIG. 2 is a perspective view of a cutaway part of the ROM device of FIG. 1, with the front side thereof showing a cross section cutting through the line II--II in FIG. 1 This perspective diagrams shows that the ROM device includes a P-type silicon substrate 10 on which the bit lines 12a, 12b, 12c and the overlaying field oxide layers 100 are formed. Beside these, the ROM device includes a thin insulating layer 14 on which the word lines (WL1, WL2) 18, 18' are formed.
FIG. 3 is an equivalent circuit diagram of the ROM device of FIG. 1. This circuit diagram shows that the two word lines WL1 and WL2 are used to access the binary data stored in the four memory cells 16a, 16b, 16c, 16d via the three bit lines (BL1, BL2, BL3) 12a, 12b, 12c. In this example, the first memory cell 16a is set to a permanently-ON state; the second memory cell 16b is set to a permanently-OFF state; the third memory cell 16c is set to a permanently-OFF state; and the fourth memory cell 16d is set to a permanently-ON state.
One drawback to the foregoing ROM device, however, is that, since the bit lines (BL1, BL2, BL3) 16a, 16b, 16c and the word lines (WL1, WL2) 18, 18' are only separated by the thin insulating layer 14, a parasitic capacitance could arise therebetween. The existence of the parasitic capacitance will increase the resistance-capacitance time constant of the memory cells, thus causing a delay in the access time to the memory cells.