Memory cells which have members which may be electrically charged are well-known in the prior art. Most often, these cells employ polysilicon floating gates which are completely surrounded by insulation (e.g., silicon dioxide). These gates are electrically charged by electron transfer from the substrate through a variety of mechanisms such as avalanche injection, channel injection, tunneling, etc. The presence or absence of this charge represents a stored, binary information. An early example of such a device is shown in U.S. Pat. No. 3,500,142.
One category of semiconductor floating gate memory devices are both electrically programmable and electrically erasable (EEPROMs). Such a device is shown in U.S. Pat. No. 4,203,158. These cells are characterized by a substrate region including source and drain regions which define a channel therebetween. Disposed above this channel is a floating gate separated from the substrate region by a relatively thin gate insulative material. Typically, a layer of silicon dioxide is employed as the insulator. A control gate is disposed above, and insulated from, the floating gate. Normally, the control gate is also fabricated of polysilicon.
A more recent category of floating gate memory devices uses channel injection for charging the floating gate and tunnelling for removing charge. For these devices the memory cell comprises only a single device and the entire memory array is erased at one time. That is, individual cells or groups of cells are not separately erasable as in current EEPROMs. These memories are sometimes referred to as flash EPROMs or flash EEPROMs. An example of these devices is disclosed in pending application Ser. No. 892,446, filed Aug. 4, 1986, entitled "Low Voltage EEPROM Cell", which application is assigned to the assignee of the present application. U.S. Pat. No. 4,698,787 of Mukherjee et al., also discloses an electrically erasable programmable memory device which is programmed by hot-electron injection from the channel onto the floating gate, and erased by Fowler-Nordheim tunnelling from the floating gate to the substrate.
The principle upon which these EEPROM cells operate is that electrons (i.e., charge) are stored on the floating gate in a capacitive manner. By way of example, during programming of an EEPROM device, the control gate is usually taken to a high positive potential ranging between 12 and 20 volts. The source is grounded and the drain is taken to an intermediate potential of approximately 7 volts. This creates a high lateral electrical field within the channel region nearest to the drain. The high lateral electric field accelerates electrons along the channel region to the point where they become "hot". These hot-electrons create additional electron-hole pairs through impact ionization. A large number of these electrons are attracted to the floating gate by the large positive potential on the control gate.
During erasing of an EPROM device, the control gate is usually grounded and the drain is left unconnected. The source is taken to a high positive potential, creating a high vertical electric field from the source to the control gate. Charge is erased from the floating gate by the mechanism of Fowler-Nordheim tunnelling of electrons through the gate oxide region between the source and the floating gate in the presence of such a field.
In certain instances, floating gate memory devices are fabricated in arrays where each device or device pair is separated from other devices by thick field oxide regions. An example of this is shown in U.S. Pat. No. 4,114,255. In these arrays a metal contact is ordinarily required for each device or device pair. Obviously, these metal contacts limit the reduction of device area.
Other architectures substantially reduce the number of metal contacts required by employing elongated source/drain regions disposed beneath oxide regions. These arrays sometimes are referred to as having "buried bit lines" or using "contactless cells" and need virtual ground circuitry for sensing and programming. An example of this type of array is shown in U.S. Pat. No. 4,267,632; virtual ground circuitry is shown in U.S. Pat. No. 4,460,981. A process for fabricating an electrically alterable contactless memory array is described in U.S. Pat. No. 4,780,424 of Holler et al., which is assigned to the assignee of the present invention.
Although the contactless memory array architecture provides an increase in device density, it is not without certain drawbacks. For instance, prior art floating gate memory devices generally require a relatively thick oxide for capacitive coupling concerns. These thick oxide regions contribute significantly to the overall cell size. Perhaps more importantly, prior art floating gate memory devices are characterized by a floating gate having a large horizontal dimension. Often, as is the case in U.S. Pat. No. 4,780,424, the floating gate extends beyond the channel regions to overlap the isolation regions of the device. This increased lateral dimension is necessary to increase the capacitive coupling between the floating gate and the control gate. This large lateral floating gate dimension further increases the minimal cell dimension geometry for this technology.
As will be seen, the present invention provides an electrically erasable and programmable memory cell which utilizes both the vertical and the planar dimension of the floating gate to achieve a minimal area memory cell. When fabricated in the contactless array, the present invention yields the absolute smallest cell size with any given design rule.