The invention relates to a binary logic unit to apply any desired Boolean operation on two input signals plus a method to operate such a binary logic unit.
A binary logic unit used to apply logic Boolean operations on two input signals va, vb comprises a plurality of basic logic gates like AND, OR, XOR and XNOR gates, each one consisting of one or more transistors. Table 1, shown in FIG. 8, gives an overlook over the Boolean operations that can be performed on two input signals va, vb by a binary logic unit.
A binary logic unit 1 according to the state of the art is shown in FIG. 1. It is a static CMOS realization of thirty-eight transistors that are arranged to different logic gates 2. The logic gates 2 are a 4:1 multiplexer 3, a 2:1 multiplexer 4, two XOR-gates 5, 6, and two inverters 7, 8. The logic gates 2 are controlled by control signals ctl switching the transistors of the logic gates 2 in a way that an output signal vo of the binary logic unit 1 is achieved equivalent to the result of a desired Boolean operation applied on the input signals va, vb.
The principle of such a binary logic unit is shown in FIG. 2. Thereby the two input signals va, vb are linked to a number of combinatory circuits 11 equal to the number of Boolean operations to be applied on the two input signals va, vb. The results of these Boolean operations are applied on the data inputs of a multiplexer 12. A control signal ctl applied on the control input of the multiplexer 12 selects the result according to the desired Boolean operation.
Regarding FIG. 1, in order to implement this principle, the input signal va is applied on the XOR-gate 5 and the input signal vb is applied on the XOR-gate 6 and together with its inverse on two data inputs of the 4:1 multiplexer 3. Two static signals marked with ‘1’ and ‘0’ are applied on the remaining two data inputs of the 4:1 multiplexer 3. The 4:1 multiplexer 3 is controlled by a pair of control signals applied on the control inputs of the 4:1 multiplexer 3. Each of the XOR-gates 5, 6 is also controlled by a control signal respectively. The 2:1 multiplexer 4 is controlled by the output of the XOR-gate 5 wherein the outputs of the other XOR-gate 5 and of the 4:1 multiplexer 3 are fed in the data inputs of the 2:1 multiplexer 4. The output signal vo of the 2:1 multiplexer 4 is the result of a Boolean operation selected by the control signals and applied on the input signals va, vb.
It can be seen that the implementation of a binary logic unit according to the state of the art requires many transistors and in consequence of this also a large silicon area. Thereby in modern microprocessors power consumption particularly due to leakage power is a huge problem and is to be reduced. According to a rule of thumb, leakage power is a function of silicon area. The larger the silicon area required, the higher the leakage power suffered.
As a binary logic unit performs on each input bit in any logic unit within a microprocessor, like e.g., a vector unit such as VMX used in IBM PowerPC and POWER processors, a realization for a single bit with reduced power consumption and with a reduced requirement of silicon area would have a noticeable impact on the total power consumption and size of any chip.