In data communication systems, a plurality of digital devices may be connected together by transmission lines to communicate with each other at high speed and over a large voltage swing. To achieve such a result, the device may include a line driver, which is often necessary to drive the transmission line. For example, a 10BaseT Ethernet (IEEE Standard 802.3) line driver is required to drive a signal having a peak-to-peak voltage swing of 5 volts (V) at a 10 megabit per second rate (MHz) on an unshielded twisted pair cable of a 50 ohm load.
FIG. 1 is a schematic diagram of a conventional digital line driver 5 comprising PMOS transistors 1 and 4 and NMOS transistors 2 and 3. The input signals of a square waveform applied at the input terminals IN+ and IN- are provided from an internal element of a digital device. The input signals, however, have a low power density (low current level), and the digital line driver 5 amplifies the input signals to provide signals with a high power density (high current) at the output terminals OUT+ and OUT-. Such output signals are necessary to drive the transmission line of 50 ohms connected at the output terminals OUT+ and OUT-.
In FIG. 1, every MOS transistor 1-4 is working in a "switch" mode. When the PMOS transistor 1 is switched ON, the NMOS transistor 3 is switched ON at the same time, and the NMOS and PMOS transistors 2 and 4 are switched OFF. Similarly, when the NMOS and PMOS transistors 2 and 4 are switched ON at the same time, the PMOS and NMOS transistors 1 and 3 are switched OFF. Thus, each output signal has only two levels, i.e., a logic high (when the transistors 1 and 3 are ON) and a logic low (when the transistors 2 and 4 are ON).
Since the line driver 5 has a simple design structure, a minimum area on a silicon wafer is used for the driver. Further, the line driver 5 has a high power efficiency since the transistors are turned ON only when they deliver the high current output signals to the output terminals OUT+ and OUT-. Thus, no quiescent bias is needed.
Since the line driver 5 outputs a square waveform of only two output levels, i.e. a step function, the output signals have unacceptable harmonic contents or electromagnetic interference (EMI), and cannot be used to directly drive an unshielded twisted pair cable. An additional off-chip filter module is used to "clean up" an output signal from an output port of a digital device prior to the transmission into the unshielded twisted pair cable. Since the digital device may have many output ports, additional off-chip filter modules increase the cost, and reduce integration.
FIG. 2 is an illustration of a digital-to-analog converter (DAC) 10, which is used as a digital line driver, to reduce the high frequency harmonics. Each of the MOS transistors 6.sub.1 -6.sub.n+i functions as a fixed value current source, and a plurality of paired MOS transistors 8.sub.1 -8.sub.n+i functions as switches and turns ON and OFF in response to two level digital input signals at the input terminals IN0+ to INn+ and IN0- to INn-. The amount of the current flow into output terminals OUT+ and OUT-, and the shape of the output signals are controlled by a number of transistors that are switched ON to create a conductive path between the current sources and the output terminals.
Compared to the output signals of FIG. 1, the output signals of the FIG. 2 circuit reach a logic high or a logic low level gradually in multiple steps or increments. The number of steps or increments is based on the number of current sources of the DAC 10. Ideally, a DAC 10 should be able to generate output signals having any type of waveform shape in response to the digital input signals.
The DAC 10 can change the output signals in a continuous fashion such that a dominant frequency content is limited to be below a certain bandwidth. For example, if a cable is driven by a single frequency sinusoidal signal, the frequency content will not go beyond that frequency, since a pure analog sinusoidal signal has no harmonics.
The DAC 10 eliminates the fast transition from a logic low to a logic high. The waveform of the output signals can be shaped as desired such that spectral energy is limited below a certain bandwidth. Hence, a costly off-chip filter module for digital line driver 5 is no longer necessary. However, the output signals of the DAC still cannot be directly connected to the transmission line. As described above, the output signals are incremented in a plurality of steps. Each step is a high frequency signal, which needs to be cleaned up using a less costly one-pole filter, such as a capacitor, to smooth out the output signal at each output terminal.
Further, the "sum of currents" in a digital-to-analog conversion requires many large sized transistors to deliver sufficient weighted currents to the output nodes OUT+ and OUT-. Hence, the DAC 10 requires significantly larger silicon area compared to the digital driver 10. Since the transistors are larger, the DAC 10 also consumes more power than the digital line driver 5.
FIG. 3 is an illustration of a line driver 20 comprising a DAC 10' with the output nodes connected to the input terminals V+ and V- of an operational amplifier (op-amp 14). U.S. Pat. Nos. 5,166,635 and 5,336,946 disclose an operational based line driver with similar configurations. The operational amplifier 20 is a Voltage Controlled Voltage Source (VCVS), i.e., the voltage levels of the input signals control other voltage sources of the operational amplifier to control the voltage levels of the output signals, which is used to amplify a pre-shaped waveform outputted from the DAC 10'. The output power density of the DAC 10' is significantly lower compared to that of the DAC 10 of FIG. 2.
The operational amplifier 14 receives the sampled-data of a low power density and outputs a continuous signal of a required power density to a load, e.g., a transmission line. Since the current density of the weighted current source in the DAC 10' is very small, the major silicon usage is the operational amplifier 14, which delivers all the power to the load.
The operational amplifier 14 is easy to design, and delivers a well defined power density to the load with high voltage swing and high efficiency. Further, the operational amplifier 14 has a certain frequency response limited by the gain bandwidth, which may totally eliminate the requirement for the off-chip filter modules.
The design of the operational amplifier requires a high gain stage and certain feedback circuit(s) (not shown) to provide an overall stable current/voltage gain. A high gain bandwidth is also required for a stable output impedance over a certain frequency range. However, the high gain and closed loop (feedback) design introduce unstable conditions in the operation of the operational amplifier 14.
For example, resistors (not shown) are used in a negative feedback path of the operational amplifier 14. During fabrication of the resistor, the temperature or process may change. Hence, the original design conditions for the operational amplifier 14 may not be meet, and the operation amplifier 14 may operate in an unstable state, i.e., produce oscillation. Further, the parasitic resistance changes over the frequency range, and the operational amplifier 14 becomes unstable.
Moreover, an operational amplifier with a high gain bandwidth requires the transistors of the operational amplifier to have a high characteristic frequency f.sub.T, which is not always available, especially in CMOS based components. For example, the transistors made from a CMOS process based on a prescribed micron (u) technology (e.g., 1.0 u, 0.8 u, 0.35 u, etc) may not have a high characteristic frequency to operate in very high frequencies (e.g, 100 MHz, 600 Mz, 1 GHz, etc).