1. Field of the Invention
The present invention relates to a semiconductor integrated circuit
2. Description of the Related Art
Semiconductor integrated circuits (ICs) are known containing a nonvolatile memory such as an erasable programmable read only memory (EPROM) or an electrically erasable programmable read only memory (EEPROM) that are provided with a function for protecting the nonvolatile memory against an external surge voltage or an overvoltage. The following describes an example of surge protection circuit for a write terminal to a nonvolatile memory of such a conventional semiconductor integrated circuit. FIG. 6 is a circuit diagram showing a construction of a conventional semiconductor integrated circuit. FIG. 7 is a plan view showing an example of a pattern of the semiconductor IC of FIG. 6.
As shown in FIG. 6 and FIG. 7, a conventional semiconductor integrated circuit has a nonvolatile memory 103 and a Zener diode 104 for protecting the nonvolatile memory 103 connected in parallel between a write terminal 101 and a ground terminal 102 with independent wiring lines of a write terminal line 111, a first ground line 112, and a second ground line 113. The nonvolatile memory 103 is connected to the write terminal 101 with the write terminal line 111, and connected to the ground terminal 102, which is a ground pad, with the first ground line 112. The cathode of the Zener diode 104 is connected to the write terminal line 111 at a node 111a, and the anode of the Zener diode 104 is connected to the ground terminal 102 with the second ground line 113. The first ground line 112 has a parasitic resistance r12 and the second ground line 113 has a parasitic resistance r11.
Japanese Unexamined Patent Application Publication No. 2009-231650 discloses a semiconductor integrated circuit provided with a protecting function against a surge voltage, having a first diode and a p channel metal-oxide-semiconductor (MOS) transistor connected in series between a write terminal and a Vcc line, and having a second diode connected between the write terminal and a ground line. The p channel MOS transistor in the Japanese Unexamined Patent Application Publication No. 2009-231650 is formed in an n well diffusion region that is formed on a substrate of a p conductivity type. The n well diffusion region of the p channel MOS transistor is electrically independent, or floating, of other circuit component. This construction allows simultaneously ensuring an electrostatic withstand voltage and enabling a high voltage write terminal.
Japanese Unexamined Patent Application Publication No. 2005-026307 discloses another semiconductor integrated circuit, which has a first power supply line connected to a first external power supply terminal and a second power supply line connected to a second external power supply terminal. The first power supply line supplies an operation voltage to a first circuit and the second power supply line supplies an operation voltage to a second circuit. The first external power supply terminal and the second external power supply terminal have a protection circuit for electrostatic discharge (ESD) toward the corresponding power supply lines, and bridge circuits for ESD are arranged between the first power supply line and the second power supply line. The circuit of the Japanese Unexamined Patent Application Publication No. 2005-026307 restricts transmission of power supply noises, and enhances surge withstand voltage by transmitting the surge voltage applied on one side of the power supply terminal to the other power supply line through the bridge circuit for ESD.
Japanese Unexamined Patent Application Publication No. 2012-209526 discloses still another semiconductor integrated circuit that comprises: a nonvolatile memory, a write control line that receives a write voltage for the nonvolatile memory, a first node connected to the write control line, an external terminal connected to the first node through a switch, an ESD protection circuit connected to the external terminal without intervening the switch, and a control circuit for ON/OFF-controlling the switch corresponding to an operation mode. In the circuit of
Japanese Unexamined Patent Application Publication No. 2012-209526, a switch is provided between the nonvolatile memory and a write terminal, which is the write control line. The switch is turned ON in a test mode for testing the characteristics of the nonvolatile memory, and turned OFF in a user mode for writing into the nonvolatile memory, thereby performing surge protection for the nonvolatile memory.
Japanese Unexamined Patent Application Publication No. 2012-160611 discloses a different semiconductor integrated circuit comprising: a ring of ground line along an outer periphery of a semiconductor substrate, and a ring of first power supply line inside the ground line. A ring of a second power supply line is provided inside the first power supply line. Inside the second power supply line, internal circuits including a nonvolatile memory are provided. Power supply cells are provided along the four sides of the first and second power supply lines and the ground line. The power supply cells include a power supply terminal and a protection circuit.
The circuit of Japanese Unexamined Patent Application Publication No. 2012-160611 comprises a protection circuit connected between the first power supply line and the ground line, the protection line releasing surge current influent to the first power supply line to the ground line, thereby performing surge protection of the internal circuit components.
In the conventional semiconductor integrated circuit as shown in FIG. 6 and FIG. 7, however, a breakdown current flows from the Zener diode 104 to the ground terminal 102 through the second ground line 113 when a surge voltage higher than the breakdown voltage Vr of the Zener diode 104 used for a protection device is applied. This breakdown current is an anode-cathode current Iak through the Zener diode 104 when a voltage Vak applied between the anode and cathode of the Zener diode 104 exceeds the breakdown voltage Vr of the Zener diode 104. The breakdown current Iak of the Zener diode 104 generally increases in proportion to the increment of the voltage ΔVd applied between the ground terminal 102 and the write terminal 101. (See FIG. 3.)
Because of the characteristic of the Zener diode 104, a high surge voltage applied to the write terminal 101 increases the breakdown current Iak, which in turn results raises the voltage at the write terminal 101 due to the anode-cathode resistance Rvr, which is equal to ΔVak/ΔIak. Because the nonvolatile memory 103 is connected in parallel to the Zener diode 104, the raised voltage at the write terminal 101 is directly applied to the nonvolatile memory 103. Despite the surge protection by the Zener diode 104, the voltage rise at the write terminal 101 is hardly suppressed in the case of high surge voltage applied to the write terminal 101, which may impose a voltage higher than the surge withstand voltage, or surge breakdown voltage, Vbm on the nonvolatile memory 3, leading breakdown thereof.
The device in Japanese Unexamined Patent Application Publication No. 2009-231650 comprises protection devices of a diode and a p channel MOS transistor that exhibit a finite, nonzero resistance value proportional to the size of the device upon breakdown of the device elements. The resistances are a resistance between the anode and cathode of the diode, and a resistance between the source and drain of the p channel MOS transistor. Consequently, when a high external surge voltage is given, the terminal voltage surges up due to the resistance upon breakdown of the protective device element. Thus, there exists an upper limit in surge protection with the protective device elements, and a surge voltage exceeding this upper limit value may breakdown the nonvolatile memory. Enhancement of the upper limit value of surge protection with a protective device element is only achieved by increasing the size of the protection device. Thus, a tradeoff relationship exists between improvement of surge withstand voltage and reduction of the chip area.
In the device of Japanese Unexamined Patent Application Publication No. 2005-026307, the surge withstand voltage of the nonvolatile memory is improved with the protection device by transferring the surge voltage applied to the write terminal to the other terminal that is not relevant to the nonvolatile memory. Thus, the area occupied by the protecting device element is prevented from enlarging and the problem of chip area that was a problem in Japanese Unexamined Patent Application Publication No. 2009-231650 can be alleviated to some extent. On the other hand, the surge voltage transferred to a terminal irrelevant to the nonvolatile memory is transmitted also to the write terminal, which means many factors are left likely to cause the failure of the nonvolatile memory due to the surge. In the case the semiconductor integrated circuit is used under an environment of severe noise and unstable ground level potential, for example, on-board application in particular, the device construction of Japanese Unexamined Patent Application Publication No. 2005-026307, which includes a multiple of surge transmission paths, would increase the failure risk.
The voltage applied to the write terminal is generally higher than the voltage impressed on other integrated circuits. Thus, the construction of Japanese Unexamined Patent Application Publication No. 2012-209526 solves the problem that exists in the technologies in Japanese Unexamined Patent Application Publication No. 2009-231650 and Japanese Unexamined Patent Application Publication No. 2005-026307. However, the nonvolatile memory is isolated after writing into the nonvolatile memory. Thus, a noise possibly penetrates into the nonvolatile memory. In addition, a high withstand voltage is hardly achieved in a device produced by some manufacturing processes. Therefore the technology of Japanese Unexamined Patent Application Publication No. 2012-209526 has disadvantages of the need of a high withstand voltage device element for the switch to changeover connection between the nonvolatile memory and the write terminal, and the requirement for a costly manufacturing process to cope with avoiding the leak of surge current through a parasitic current path in the substrate.