1. Field of the Invention
Embodiments of the present invention relate to a low profile semiconductor device and method of fabricating same.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. Although not shown in FIGS. 1 and 2, the semiconductor die are formed with die bond pads (40 in FIGS. 3 and 4). Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form a conductance patterns including electrical leads and contact pads (52, FIGS. 3 and 4). Wire bonds are soldered to the die bond pads 40 of the semiconductor die 22, 24 and contact pads 52 of the substrate 26 as explained hereinafter to electrically couple the semiconductor die to the substrate.
It is known to layer semiconductor die on top of each other either with an offset (prior art FIG. 1) or in a stacked configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die are stacked with an offset so that the bond pads of the next lower die are left exposed. Such configurations are shown for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled, “Multichip Module Having A Stacked Chip Arrangement.” An offset configuration provides an advantage of convenient access of the bond pads on each of the semiconductor die. However, the offset requires a greater footprint on the substrate, where space is at a premium.
In the stacked configuration of FIG. 2, two or more semiconductor die are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the wire bond 30 to be bonded to the die bond pad on the lower die 24. Instead of a spacer layer 34, it is also known to bury the wire bond loops between two adjacent semiconductor die within an adhesive layer between the respective die. Such configurations are shown for example in U.S. Pat. No. 6,388,313 to Lee et al., entitled, “Multi-Chip Module,” and U.S. Pat. No. 7,037,756 to Jiang et al., entitled, “Stacked Microelectronic Devices and Methods of Fabricating Same.”
There is an ever-present drive to increase storage capacity within memory modules. One method of increasing storage capacity is to increase the number of memory die used within the package. In portable memory packages, the number of die which may be used is limited by the thickness of the package. There is accordingly a keen interest in decreasing the thickness of the contents of a package while increasing memory density.
The package 20 shown in prior art FIGS. 1 and 2 requires that additional space be provided within the package to accommodate the height of the wire bond loops. Further details relating to conventional processes for forming wire bond loops 30 are explained with reference to the perspective views of prior art FIGS. 3 and 4. FIGS. 3 and 4 show lower semiconductor die 24 wire bonded to substrate 26 via bond wires 30. The structure affixed atop semiconductor die 24 can be another semiconductor die, such as die 22 of FIG. 1, or the structure can be a spacer layer, such as layer 34 of FIG. 2.
FIG. 3 shows bond wires 30 formed by a ball bonding process. This process uses a wire bonding device referred to as a wire bonding capillary. A length of wire (typically gold or copper) is fed through a central cavity of the wire bonding capillary. The wire protrudes through a tip of the capillary, where a high-voltage electric charge is applied to the wire from a transducer associated with the capillary tip. The electric charge melts the wire at the tip and the wire forms into a ball (38 in FIG. 3) owing to the surface tension of the molten metal.
As the ball solidifies, the capillary is lowered to the surface of a die bond pad 40 formed on the surface of semiconductor die 24. The surface of die 24 may be heated to facilitate a better bond. The wire bond ball 38 is deposited on the die bond pad 40 under a load, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy create a bond between the wire bond ball 38 and the die bond pad 40.
The wire bonding capillary is then pulled up and away from the surface of semiconductor die 24, as wire is payed out through the capillary. The capillary then moves over to a contact pad 44 receiving the second end of the wire bond on the substrate 26. The second bond, referred to as a wedge or tail bond, is then formed on contact pad 44 again using heat, pressure and ultrasonic energy, but instead of forming a ball, the wire is crushed under pressure to make the second bond. The wire bonding device then pays out a small length of wire and tears the wire from the surface of the second bond. The small tail of wire hanging from the end of the capillary is then used to form the wire bond ball 38 for the next subsequent wire bond. The above-described cycle can be repeated about 20 to 30 times per second until all wire bond loops 30 are formed between the semiconductor die and the substrate. It is understood that there may be many more wire bond loops 30 than are shown in FIGS. 3 and 4.
Due to the fact that the wire 30 must be pulled upwards from ball 38 on each wire bond loop 30, the wire bonds shown in FIG. 3 formed by the ball bonding process have a relatively large height. As indicated above, this height adds to the overall thickness of the package where space is at a premium. Prior art FIG. 4 is a perspective view of die 24, substrate 26 and wire bonds 30 formed by a reverse ball bonding process. In a reverse ball bonding process, a ball 50 is initially formed on the die bond pads 40 of semiconductor die 24. Namely, the capillary forms the ball and bonds it to the bond pad 40, but pulls away without paying out wire. Thereafter, to form a first wire bond loop, a second ball 52 is formed on a contact pad 44 of the substrate, and the capillary pulls up and away from the ball 52 while paying out wire. The capillary then bonds the wire 30 to the corresponding ball 50 on the die bond pad 40 using a wedge bond. As the capillary attaches the wire 30 to the ball 50 using a flat wedge bond, the wire bond has a lower profile than in the forward ball bonding process of FIG. 3, where the wire was lifted up and away from the ball 38 on the die bond pads.
Conventionally, the ball 50 is required on die bond pads 40 in the reverse ball bonding process of FIG. 4 for at least two reasons. First, unlike the substrate contact pads 44, the die bond pads 40 are too small to receive a wedge bond. Second, the die bond pads are recessed slightly below the upper surface of the semiconductor die, further preventing the capillary from forming a wedge bond directly to the die bond pads. This problem is solved in the prior art by first affixing the balls 50 to the die bond pads 40 of die 22 and then wedge bonding to the balls 50 in a reverse ball bonding process.