Integrated Graphics chipsets typically include a graphics accelerator and a memory controller. The graphics accelerator includes a 2D/3D instruction processing unit to control the 2D and 3D graphics engines. These graphics engines interact with a main memory device through the memory controller. The instructions to the memory are carried out through certain command requests, which are processed through a queuing mechanism. The queuing mechanism is used to store some of the information from the graphics engines prior to the information being presented to the memory.
As the size of integrated circuit dies have increased it has become necessary to split up a die into different partitions in order to fulfill the constraints of various back-end tools. Back-end is the process where the die logic is synthesized (e.g., using Synopsys), and goes through layout for auto place and route (APR), after which parasitic extraction and delay calculation are implemented to determine inter-connect delays and the delays through various gates. This extracted information is then used to determine the performance validation (PV) timings using Prime Time. This process is further complicated by the fact that the operating frequencies are also increasing.