The present invention relates to a circuit for generating a constant reference voltage in a semiconductor device.
In the process of semiconductor device, a circuit for supplyng a constant reference voltage to a memory circuit of the semiconductor device, is required.
FIG. 1 is an example of such a conventional reference voltage generating circuit.
An enhancement-mode P type MOS transistor M1 connected to a supply voltage Vcc and an enhancement-mode N type MOS transistor M2 connected to a ground voltage Vss, is coupled in series as diode construction. The reference voltage Vo is taken out from the connecting point between M1 and M2.
Accordingly, N MOS transistor M2 performs a function for taking the reference voltage of low level, and P MOS transistor M1 performs a function for controlling the requisite reference voltage.
This circuit has, however, a problem that the reference voltage Vo varies sensitively due to variation of the supply voltage Vcc.
FIG. 2 is another example of the conventional reference voltage generating circuit.
In this circuit, a series path is formed by P MOS transistor M11, N MOS transistor M12 and N.sup.+ - P.sup.+ junction diodes D11 and D12.
P and N MOS transistors M11 and M12 always turn on and a reference voltage is taken out from the connecting node between M11 and M12.
P and N MOS transistors perform reducing the standby current flowing in the circuit and a resistance component consisting of N MOS transistor M12 and N.sup.+ - P.sup.+ juction diode D11 forms the reference voltage level.
Accordingly, this circuit can reduce variation of the reference voltage Vo due to variation of the supply voltage Vcc better than the circuit as shown by FIG. 1 .
This circuit has, however, a problem that the standby current of several tens uA flows in this circuit because of a direct current path between the suppy voltage Vcc and the ground voltage Vss.