As feature sizes of integrated circuits continue to decrease, the effects of feature-related defects are becoming increasingly important. For example, the lithographic techniques used to realize today's integrated circuit often use light having a wavelength that is larger than the features it creates. One consequence of sub-wavelength lithography is that failures caused by the lithography process (for example, distortion that causes shorts and opens to appear in the resulting design) become more numerous. Indeed, the effect of feature defects on the production yield of integrated circuits is increasing and has become more dominant than the effect of random particles present during fabrication.
To reduce the number of defective chips being produced, foundries (integrated circuit manufacturers) often provide a number of recommended design rules that designers can use to help improve the yield of their particular design. Such rules are generally referred to herein as Design for Manufacturability (DFM) rules and can pertain to a wide variety of parameters related to integrated circuit design. For example, the rule could pertain to a physical characteristic or trait of the design, such as a distance between two wires or between corners of two features. Among the possible design issues addressed by DFM rules are: redundancy, spacing, width, length, area, enclosure, extension, overlap, density, orientation, job/notch, antenna, and matching. Further, each of these categories can have numerous rules that apply. Further, a foundry can provide multiple rules for a given design parameter, each having a different potential effect on yield. For instance, a foundry can provide a minimum or maximum value for a particular parameter as well as a recommended value. In general, the use of DFM rules helps ensure that the integrated circuit is actually manufacturable using the process and technology implied by the DFM rules.
DFM rules have been traditionally determined through the use of test chips. A test chip is a specialized chip comprising numerous groups of identical test structures that systematically vary across some parameter being targeted for a particular DFM rule. Test results obtained from the test chips can then be statistically analyzed and used to determine the values for the targeted DFM rules. Test chips, however, can be expensive to use—both in terms of actual cost and in terms of the lost wafer capacity resulting from the creation, testing, and analyzing of the test chips. Test chips also provide limited information. For example, test chips cannot ordinarily provide information on the impact of features of a circuit not contained in a test structure of the test chip. Further, as new DFM rules are developed to address process changes or new knowledge obtained, new test chips must be designed and manufactured—a process that commonly takes weeks to months.
Accordingly, improved methods of determining, modifying, and using design manufacturing rules to increase yield are desired.