Field
Implementations of the present disclosure generally relate to the fabrication and cobalt metallization of integrated circuits using, for example, single and dual Damascene processes.
Description of the Related Art
Microelectronic devices, such as micro-scale electronic, electro-mechanical or optical devices are generally fabricated on and/or in work pieces or substrates, such as silicon wafers. In a typical fabrication process, for example on a semiconductor material wafer, a conductive seed layer is first applied onto the surface of the substrate using chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating processes, or other suitable methods. After forming the seed layer, a layer of metal is plated onto the substrate by applying an appropriate electrical potential between the seed layer and one or more electrodes in the presence of an electro-processing solution containing metal ions. The substrate is then cleaned and/or annealed in subsequent procedures to form devices, contacts or conductive lines. Some substrates may have a barrier layer with the seed layer formed on the barrier layer.
Currently, most microelectronic devices are made on substrates plated with copper (Cu). Although copper has high conductivity, it typically involves a barrier layer such as tantalum nitride (TaN) to prevent diffusion of copper into the substrate or dielectric material on the substrate. These types of barrier layers have relatively low conductivity. Using known techniques, features on the substrate are filled with electroplated copper using acidic copper electroplating solutions. These electroplating solutions often use additives to promote a super-conformal fill process (with the features filling primarily from the bottom up, rather than inwardly from the sides) to create a void-free fill. As the feature sizes shrink, achieving void-free fill with the traditional copper plating processes has become more difficult. In addition, as the features get smaller, the barrier layer used for copper occupies a larger relative volume of the smaller feature, because a minimum barrier layer thickness is typically necessary to prevent copper diffusion, regardless of feature size.
For example, if a minimum barrier layer thickness of 3 nanometers is necessary to prevent diffusion of copper, then for a feature having a 60 nanometers critical dimension with an aspect ratio of 4:1, the barrier layer occupies roughly 11% of the cross-sectional area. However, with a feature a having a 20 nanometers critical dimension with an aspect ratio of 2:1, the barrier layer remains 3 nanometers thick, but it now occupies 33% of the cross sectional area. In this case the volume of the barrier layer (which has low conductivity) is proportionally higher, so the resistance of the interconnect, via or other feature is proportionally higher. With progressively smaller features, the proportion of copper to barrier layer increases, to the extent that the resistance becomes unacceptable.
One approach proposed for overcoming this technical challenge is to replace copper with a metal that does not have need of a barrier layer, such as cobalt (Co). Although cobalt has a higher resistance than copper (6 μOhm-cm versus 2 μOhm-cm), cobalt may not have need of a barrier layer to prevent diffusion into the silicon or dielectric. Chemical vapor deposition (CVD) is a useful technique for filling large and small features by applying cobalt, but has some limitations. Although this method works well for smaller features (e.g., 7-10 nm), such as interconnect level features or contact level features, CVD is not well suited for filling features larger than about 10 nm.
Therefore, new techniques are needed for the super-conformal and defect free filling of narrow features with cobalt, such as improved cobalt electroplating baths that contain new and improved plating bath additives.