As shown in FIG. 1, a typical computer system 10 includes at least a microprocessor 12 (often referred to and known as xe2x80x9cCPUxe2x80x9d) and some form of memory 14. The microprocessor 12 has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system 10. Specifically, FIG. 1 shows the computer system 10 having the microprocessor 12, memory 14, integrated circuits (ICs) 16 that have various functionalities, and communication paths 19, i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system 10.
In order to keep pace with improving technologies, computer system and circuit designers are constantly trying to improve and get the most out of their designs through the most cost-effective means. As faster versions of a particular CPU become available, a designer will often try to improve the throughput of their existing design by simply increasing the CPU clock frequency. However, after a certain point, the speed of the system""s main memory becomes a limiting factor in optimizing the throughput of the system. To this end, designers have produced faster memories, which, in turn, has necessitated high-speed memory interfaces.
One type of design that has been used for high-speed memory interface applications involves the use of stub series termination logic (SSTL). SSTL is a standard created by the Joint Electron Device Engineering Council (JEDEC) to provide a termination scheme for high speed signaling in applications such as DDR-SDRAM. SSTL specifies particular switching characteristics such that high operating frequencies are available. As operating frequencies continue to increase and as the demand for faster memory interfaces has and continues to grow, the STTL interface standard continues to enjoy wide acceptance.
According to one aspect of the present invention, a computer system comprises a pre-driver stage comprising a voltage translator and an output buffer, wherein the voltage translator comprises: a first device that, dependent on a first bias signal, causes an output signal from the voltage translator to be pulled down, where the first bias signal is dependent on an input signal to the voltage translator; and a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.
According to another aspect, a computer system comprises means for translating an input signal having a first voltage swing to an output signal having a second voltage swing, where the means for translating comprises: means for driving the output signal; and means for dynamically biasing the means for driving the output signal dependent on the input signal.
According to another aspect, a method for performing a SSTL interface operation comprises: inputting an input signal; dynamically generating a voltage on a first bias signal dependent on the input signal; dynamically generating a voltage on a second bias signal dependent on the input signal; and driving an output signal dependent on the first bias signal and the second bias signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.