1. Field of the Invention
The invention relates to an inverting delay circuit, i.e., a delay circuit whose output signal is the product of a negative factor and its input signal.
2. Description of the Related Art
The use of switched capacitor techniques has acquired increased importance in recent times. A large number of video applications are presently being investigated, which include multi-standard video comb filters and multi-standard color decoders. Complex sampled data systems (continuous amplitude, discrete time) can be produced in the latest standard digital CMOS process with, often, a considerable saving in chip area with respect to comparable digital systems.
With the realization of complex FIR or IIR filters, accurate matching of coefficients is required. Up till now, a problem in switched capacitor filters has been the accurate generation of positive and negative filter coefficients, since positive and negative filter coefficients require inherently different switched capacitor building blocks for their generation. For instance, in an anti-symmetrical FIR filter, as given by the following transfer function EQU H(z)=C.sub.M.z.sup.0 +C.sub.M-1.z.sup.-1 + . . . -C.sub.M-1.z.sup.-(N-1) -C.sub.M.Z.sup.-N,
the coefficient C.sub.i at one sample instant has to match the coefficient -C.sub.i at another instant. A similar problem arises in switched capacitor multipliers where exact matching of positive and negative coefficients is required, for example, when successive multiplication factors 0, +1, 0, -1 are used. Present techniques for realizing an inverting delay either cause distortion (gain errors and clock feed-through) or require an extra buffer or amplifier for realization.
Electronics Letters, 11th May 1989, Vol. 25, No. 10, pp. 623-625 shows several switched capacitor delay circuits, none of them multiplying by a negative coefficient.