The present invention generally relates to an output buffer circuit having a level conversion function, and more particularly to an output buffer circuit having a CMOS/ECL (complementary metal oxide semiconductor/emitter coupled logic) level conversion function.
Conventionally, a CMOS LSI chip (or circuit) and an ECL LSI chip (or circuit) are connected to a common power source, as shown in FIG. 1. Each of the CMOS LSI chip and the ECL LSI chip is connected between a power source in line of 0 volt and a power source line of -5.2 volts. As is well known, the logic level potentials of a CMOS LSI are different from those for an ECL LSI. For example, a high level of CMOS logic is represented by a potential equal to 0 volt, and a low level of CMOS logic is represented by a potential equal to -5.2 volts. That is, the logic levels of CMOS LSI are defined by the power source voltages. On the other hand, a high level of ECL logic is represented by a potential equal to -0.9 volts, and a low level of ECL logic is represented by a potential equal to -1.7 volts, for example. That is, the logic levels of ECL LSI are different from the power source voltages. From the above-mentioned viewpoints, it is impossible to directly apply the logic level potentials of the CMOS LSI chip to the ECL LSI chip. In other words, the CMOS level potentials must be converted into the ECL level potentials in the CMOS LSI chip, and then applied to the ECL LSI chip. For this purpose, an output buffer circuit having a CMOS/ECL level conversion function is provided in the CMOS LSI chip, which generates a first potential and a second potential corresponding to the required high and low voltage levels for the ECL logic.
FIG. 2 is a circuit diagram of an open drain type output buffer circuit provided in a CMOS LSI chip. Referring to FIG. 2, the illustrated output buffer includes an intermediate voltage generating circuit 5 and an open drain circuit 6. Hereinafter, the intermediate generate voltage generating circuit 5 is referred to as a prestage circuit for the sake of simplicity. The prestage circuit 5 is made up of P-channel MOS transistors 7 and 10, and N-channel MOS transistors 8 and 9. Hereinafter, a P-channel MOS transistor is simply referred to as a PMOS transistor, and an N-channel MOS transistor is simply referred to as an NMOS transistor. The gates of the PMOS transistor 7 and the NMOS transistor 8 are supplied with an input voltage Vin derived from an CMOS logic circuit (not shown). A bias voltage V.sub.B equal to -3 volts for example, is applied to the gate of the NMOS transistor 9. The open drain circuit 6 includes an open-drain type PMOS transistor 11. An output voltage of the prestage circuit 5 is applied to the gate of the PMOS transistor 11. A power source voltage V.sub.DD is set equal to 0 volt, and a power source voltage V.sub.SS is set equal to -5.2 volts. A resistor RT connected between an output terminal OUT of the CMOS LSI chip and a line of a terminating voltage V.sub.LL corresponds to a resistance of an ECL circuit (50 ohms for example) to be connected to the output terminal OUT.
In order to generate the ECL level output voltages, the prestage circuit 5 can generate an intermediate voltage equal to -3 volts, for example. The value of the intermediate voltage is controlled by the bias volta V.sub.B. When the input voltage Vin is at a low (L) level (-5.2 volts), the output voltage of the prestage circuit 5 is equal to the power source voltage V.sub.DD equal to 0 volt. At this time, the PMOS transistor 11 is OFF, and thus the potential Vout of the output terminal OUT is equal to -1.7 volts corresponding to the low Level of the ECL logic. On the other hand, when the input voltage Vin is at a high (H) level (0 volt), the output voltage of the prestage circuit 5 is set equal to the intermediate voltage equal to -3 volts. At this time, the PMOS transistor 11 is ON. When the gate voltage of the PMOS transistor 11 is -3 volts, volts, the ON resistance of the PMOS transistor 11 is approximately 40 ohms, for example. Thus, the power source V.sub.DD is divided by the ON resistance of the PMOS transistor 11 and the resistance RT. As a result, the potential Vout of the output terminal OUT is approximately equal to -0.9 volts. In this manner, the CMOS logic levels are converted into the ECL logic levels, which may be referred to as a first potential and a second potential.
However, the conventional output buffer circuit shown in FIG. 2 has the following disadvantages. It is noted that the operating speed of the output buffer circuit is based on charging and discharging speeds at which a parasitic capacitance (not shown) coupled to the gate of the PMOS transistor 11 is charged and discharged. When the input voltage Vin changes from L level to H level, a charge stored in the parasitic capacitance is allowed to pass through the NMOS transistors 8 and 9. However, since the NMOS transistor 9 is completely ON due to the bias voltage equal to -3 volts, it takes long to discharge the capacitance. Thus, it takes long the gate voltage of the NMOS transistor 11 to decrease to the intermediate potential equal to -3 volts. For this reason, the NMOS transistor 11 cannot operate at high speeds.