A digital audio interface (DAI) transmission system as shown in FIG. 1 is known as one of digital transmission systems. Since the DAI transmits L-channel and R-channel data through a single digital cable, it employs a time-division-multiplexing transmission system which permits the L-channel and R-channel data to be alternately transmitted and received, as shown in FIG. 6A. If the sampling frequency is chosen to be, for example, 44.1 kHz as in the case of the compact disc, 44100 samples of the respective R-channel and L-channel data, that is, totally 88200 samples of data of both the channels are transmitted per second. One channel data period (word) is 11.34 sec. One word is formed of 32 bits which are divided, for example, as shown in FIG. 6B. Specifically, in the same figure, the first four bits are assigned to be a SYNC portion for synchronization in which a preamble, later referred to, is inserted. The subsequent portion, for storing audio data, has a capacity of 24 bits. However, in many cases audio data is formed of 16 bits as the compact disc, so that only 16 bits from the end are presently used. The last four bits are assigned to be a control portion for storing information added to the data such as ON/OFF of emphasis, sub-code and so on.
The data thus arranged is subjected to a so-called biphase mark modulation in which data "0" corresponds to one transition and data "1" corresponds to two transitions as shown in FIG. 6C. However, the SYNC portion is an exception and written with a particular pattern called "preamble". In the preamble, the correspondent relationship between the transition and the data values is ignored so that this portion has a high-level period longer than any other portion.
In FIG. 1, reference numeral 1 designates a transmitter such as a compact disc player, and 2 a receiver such as a D/A converter system. The transmitter 1 comprises an oscillator 3 for generating a master clock of a predetermined frequency, a data read-out circuit 4 for reading out data from a recording medium (not shown), for example a compact disc or the like, on the basis of the master clock, and an encoder 5 for encoding the data read out on the basis of the master clock in accordance with a DAI format signal.
The receiver 2 comprises a detecting circuit 6 for detecting a synchronizing signal having a frequency, for example, double the frequency of the audio data sampling frequency fs from the above-mentioned DAI format signal, a PLL circuit 7 for generating a clock signal having a frequency, for example, 256 times the sampling frequency fs and phase-locked with the detected synchronizing signal, a decoder 8 for decoding the input signal on the basis of the clock signal, and a D/A converter 9 for converting the digital decoded signal to an analog signal.
The encoder 5 of the transmitter 1 supplies the receiver 2 with a DAI format signal Rx as shown in FIG. 5A. The upper portion of FIG. 5A shows in detail the waveform of the DAI format signal Rx, and the lower portion of FIG. 5A typically shows the same DAI format signal Rx. Such the DAI format signal Rx is supplied to the detecting circuit 6. In the detecting circuit 6, a synchronizing signal 2FSR having one edge (a rising edge) per one SYNC as shown in FIG. 5B is detected. The synchronizing signal 2FSR has the frequency double the sampling frequency fs, as described above.
The synchronizing signal 2FSR from the detecting circuit 2 is supplied to a phase comparator circuit (not shown) of the PLL circuit 7, wherein it is phase-compared with a fed-back signal 2FSV (FIG. 5F) from a frequency divider (not shown). Then, a phase comparison error signal is converted to a direct current voltage by a loop filter (not shown), and the oscillating frequency of an oscillator (not shown) is controlled on the basis of this direct current voltage, whereby a clock signal for decoding the DAI format signal Rx is derived at the output side of the PLL circuit 7, that is, at the output side of the oscillator.
The clock signal thus derived from the PLL circuit 7 is supplied to the decoder 8 together with the DAI format signal Rx, wherein the DAI format signal Rx is decoded on the basis of the clock signal. Consequently, 16-bit serial digital data DATA, a clock BCK for shifting the same, and LRCK for identifying the L-channel and the R-channel, as shown in FIG. 5C, are derived at the output side of the decoder 8.
These outputs are supplied to an S/P converting circuit (not shown), whereby parallel data PDATA having 16 bits per channel, as shown in FIG. 5D, is derived at the rising edge of the clock LRCK, that is, at the end point of the R-channel at the output side of the S/P converting circuit. The parallel data PDATA is supplied to the D/A converter 9 together with the clock signal from the PLL circuit 7, and consequently an output current I.sub.OUT corresponding to the parallel data PDATA as shown in FIG. 5E is taken out at the output side thereof as an analog signal.
In the case of a conventional system constructed as shown in FIG. 1, however, the synchronizing signal is generated from the oscillator 3 of the transmitter 1 on the basis of the master clock as mentioned above, and the PLL circuit 7 of the receiver 2 generates a variety of clock signals on the basis of this synchronizing signal to operate in synchronism with the transmitter 1, wherein one of the clock signals is supplied to the D/A converter 9 to be used as the timing for the D/A converter so that if there occur minute vibrations or jitter in the clock signal, the quality of sound is badly affected. Particularly, in the conventional system which generates the clocks from the DAI format signal Rx it is inevitable that jitter is mixed in the clock signal from the PLL circuit 7 of the receiver 2 in comparison with the master clock from the oscillator 3 of the transmitter 1.