As the speed and information capacity of semiconductor devices continue to improve, silicide layers formed on the gate or source/drain contact regions are widely used to prevent the decrease of devices operational speed due to the increase of gate resistance and contact resistance of source/drain contact.
Conventionally, the silicide layer is formed by a so-called salicide process (self-aligned silicide), where silicide reaction is occurred selectively on the upper region of gate or source/drain contact without using additional photo-mask. Titanium (Ti), cobalt (Co), tungsten (W) and nickel (Ni) metals are used for the silicide metal.
With reference to FIGS. 1a to 1c, conventional method for forming the silicide layer in semiconductor device is explained.
Referring to FIG. 1a, an isolation layer 11 is formed in a semiconductor substrate 10 including silicon (Si) by using a known shallow trench isolation (STI) technology. On the substrate 10 with the isolation layer 11 are sequentially formed a gate oxide 12 and polysilicon gate 13.
With the gate 13 being mask, Lightly Doped Drain (LDD) ion implantation into the substrate 10 is carried out, and then spacers 14 made of oxide or nitride are formed at both sides of the gate 13. Then highly doped impurity ion is implanted to the substrate 10 by using the spacers 14 as an implantation mask to form source/drain region of the LDD structure.
Relatively thin Ti and TiN layers are sequentially deposited on the substrate 10 by a sputtering method to form Ti/TiN layer 16, which covers the gate 13 and spacers 14. The purpose of additionally forming TiN layer on the Ti layer is to prevent oxidation of the surface of the Ti layer during subsequent thermal treatment processes.
Referring to FIG. 1b, by carrying out a first thermal treatment process in N2 environment and using 750° C. temperature for 30 seconds, Ti on the Ti/TiN layer 16 is made to react with Si of the source/drain contact region 15 and gate 13 to form titanium silicide (TiSi2) layer 17a of C-49 phase on the contact region 15 and gate 13, respectively. The TiSi2 layer 17a of C-49 phase has resistivity of 90 μcm.
Referring to FIG. 1c, the unreacted Ti/TiN layer 16 is removed by a wet etching method using H2SO4/H2O2 compound and a second thermal treatment process of N2 environment is performed at 825° C. temperature for 20 seconds to transform the C-49 phase TiSi2 layer 17a to a thermodynamically stable C-54 phase TiSi2 layer 17b, which has lower resistivity of 16 to 20 μcm than the C-49 TiSi2 layer 17a. 
As explained above, in the conventional method, two thermal treatment processes have to be performed for obtaining the stable C-54 TiSi2 layer 17b. Further, for completely removing the unreacted Ti/TiN layer 16 after the first thermal treatment process, the wet etching should be done overly and thus the substrate can be damaged by chemicals used in the wet etching process.