High Efficiency Video Coding (HEVC) is latest generation of video compression standard jointly developed by ISO/IEC and ITU-T. HEVC promises half bit-rate compared to the current de-facto standard H.264 at a similar video quality. The HEVEC standard is expected to be deployed in wide variety of video applications.
FIG. 1 illustrates an example video processing engines supporting both codecs. Video processing engine 100 includes several external interfaces: host control port 101; clock, reset and power management (PM) port 102; debug and test input 103; debug output to master 104; interface to host shared level 2 memory (SL2); two interface ports to master level 3 (L3) memory 106; and two interface ports to master level 3 (L3) memory 107. Configuration (CFG) interface 110 couples host control port 101 and debug output to master 104 to plural operational units 130. Shared level 2 memory interface (SL2IF) 140 connects operational units 130 to interface to host shared level 2 memory (SL2), dual port interface to master level 3 (L3) memory 106, and second dual port interface to master L3 memory 107.
It is important to have common DMA engine supporting multi-standard video platform to leverage its interface within the System On Chip (SOC) in both hardware and software.